./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:19,898 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:19,900 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:19,929 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:19,929 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:19,932 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:19,933 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:19,935 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:19,937 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:19,938 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:19,939 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:19,941 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:19,941 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:19,945 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:19,946 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:19,947 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:19,948 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:19,950 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:19,951 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:19,956 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:19,958 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:19,959 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:19,960 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:19,961 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:19,962 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:19,963 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:19,964 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:19,964 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:19,965 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:19,965 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:19,966 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:19,966 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:19,967 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:19,967 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:19,968 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:19,968 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:19,968 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:19,969 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:19,969 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:19,969 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:19,970 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:19,971 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:20,000 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:20,001 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:20,002 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:20,002 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:20,003 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:20,003 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:20,004 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:20,004 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:20,004 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:20,004 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:20,005 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:20,005 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:20,005 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:20,005 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:20,005 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:20,005 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:20,006 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:20,006 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:20,006 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:20,007 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:20,007 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:20,011 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:20,011 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:20,011 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:20,012 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:20,012 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:20,012 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:20,013 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:20,013 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:20,013 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:20,013 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:20,014 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:20,014 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2022-02-21 04:24:20,205 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:20,236 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:20,237 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:20,238 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:20,239 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:20,240 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-02-21 04:24:20,301 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a9d312037/3ba2eacd70a147808f2e1a0f5b977988/FLAG000c14f3a [2022-02-21 04:24:20,655 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:20,656 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-02-21 04:24:20,690 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a9d312037/3ba2eacd70a147808f2e1a0f5b977988/FLAG000c14f3a [2022-02-21 04:24:21,053 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a9d312037/3ba2eacd70a147808f2e1a0f5b977988 [2022-02-21 04:24:21,055 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:21,056 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:21,068 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:21,068 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:21,071 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:21,072 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,073 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@726cc9ba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21, skipping insertion in model container [2022-02-21 04:24:21,073 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,078 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:21,109 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:21,229 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-02-21 04:24:21,322 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:21,330 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:21,339 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-02-21 04:24:21,390 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:21,404 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:21,404 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21 WrapperNode [2022-02-21 04:24:21,404 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:21,405 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:21,405 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:21,405 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:21,410 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,420 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,505 INFO L137 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2022-02-21 04:24:21,506 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:21,507 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:21,507 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:21,507 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:21,513 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,513 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,533 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,533 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,564 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,591 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,599 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,621 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:21,622 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:21,622 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:21,623 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:21,623 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (1/1) ... [2022-02-21 04:24:21,628 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:21,634 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:21,655 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:21,671 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:21,701 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:21,701 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:21,701 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:21,702 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:21,810 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:21,815 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:23,574 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:23,586 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:23,587 INFO L299 CfgBuilder]: Removed 17 assume(true) statements. [2022-02-21 04:24:23,589 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:23 BoogieIcfgContainer [2022-02-21 04:24:23,589 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:23,590 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:23,590 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:23,593 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:23,594 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:23,594 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:21" (1/3) ... [2022-02-21 04:24:23,595 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@afbe962 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:23, skipping insertion in model container [2022-02-21 04:24:23,595 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:23,595 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:21" (2/3) ... [2022-02-21 04:24:23,595 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@afbe962 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:23, skipping insertion in model container [2022-02-21 04:24:23,595 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:23,595 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:23" (3/3) ... [2022-02-21 04:24:23,597 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.15.cil.c [2022-02-21 04:24:23,624 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:23,624 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:23,624 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:23,624 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:23,624 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:23,625 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:23,625 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:23,625 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:23,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2022-02-21 04:24:23,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:23,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:23,961 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,962 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,962 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:23,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,163 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2022-02-21 04:24:24,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:24,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:24,166 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,166 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,173 INFO L791 eck$LassoCheckResult]: Stem: 461#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1833#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 352#L1855true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 201#L874true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1759#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1072#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1410#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 272#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1401#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 545#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 439#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 795#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 306#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 554#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 683#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 803#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 833#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 920#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 313#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1814#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1399#L1258-2true assume !(0 == ~T1_E~0); 490#L1263-1true assume !(0 == ~T2_E~0); 709#L1268-1true assume !(0 == ~T3_E~0); 1365#L1273-1true assume !(0 == ~T4_E~0); 1748#L1278-1true assume !(0 == ~T5_E~0); 1152#L1283-1true assume !(0 == ~T6_E~0); 1780#L1288-1true assume !(0 == ~T7_E~0); 1568#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1539#L1298-1true assume !(0 == ~T9_E~0); 1383#L1303-1true assume !(0 == ~T10_E~0); 215#L1308-1true assume !(0 == ~T11_E~0); 186#L1313-1true assume !(0 == ~T12_E~0); 1838#L1318-1true assume !(0 == ~T13_E~0); 189#L1323-1true assume !(0 == ~E_1~0); 277#L1328-1true assume !(0 == ~E_2~0); 1789#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 973#L1338-1true assume !(0 == ~E_4~0); 1112#L1343-1true assume !(0 == ~E_5~0); 1650#L1348-1true assume !(0 == ~E_6~0); 1667#L1353-1true assume !(0 == ~E_7~0); 725#L1358-1true assume !(0 == ~E_8~0); 999#L1363-1true assume !(0 == ~E_9~0); 1061#L1368-1true assume !(0 == ~E_10~0); 105#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 489#L1378-1true assume !(0 == ~E_12~0); 250#L1383-1true assume !(0 == ~E_13~0); 1101#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 729#L607true assume 1 == ~m_pc~0; 1009#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1108#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1626#L619true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 667#L1560true assume !(0 != activate_threads_~tmp~1#1); 1724#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 196#L626true assume !(1 == ~t1_pc~0); 1266#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 339#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 441#L638true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1907#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 147#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1336#L645true assume 1 == ~t2_pc~0; 205#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1300#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 584#L657true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1899#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 652#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1704#L664true assume 1 == ~t3_pc~0; 1633#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1126#L676true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 417#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1419#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1627#L683true assume !(1 == ~t4_pc~0); 986#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 785#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 810#L695true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1694#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 931#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 615#L702true assume 1 == ~t5_pc~0; 1684#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 925#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1343#L714true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1391#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1237#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90#L721true assume !(1 == ~t6_pc~0); 77#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 161#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 557#L733true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 422#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1524#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 867#L740true assume 1 == ~t7_pc~0; 116#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 757#L752true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 762#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 385#L759true assume !(1 == ~t8_pc~0); 1373#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1843#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 923#L771true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1083#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1670#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1567#L778true assume 1 == ~t9_pc~0; 1341#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1273#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73#L790true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 733#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203#L797true assume !(1 == ~t10_pc~0); 265#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1306#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1181#L809true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 488#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 696#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1390#L816true assume 1 == ~t11_pc~0; 57#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 588#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 463#L828true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 427#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1511#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 802#L835true assume 1 == ~t12_pc~0; 705#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 151#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 222#L847true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1783#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 527#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1442#L854true assume !(1 == ~t13_pc~0); 307#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 336#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1081#L866true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 160#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1230#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1790#L1401true assume !(1 == ~M_E~0); 419#L1401-2true assume !(1 == ~T1_E~0); 1240#L1406-1true assume !(1 == ~T2_E~0); 858#L1411-1true assume !(1 == ~T3_E~0); 1611#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 595#L1421-1true assume !(1 == ~T5_E~0); 305#L1426-1true assume !(1 == ~T6_E~0); 1014#L1431-1true assume !(1 == ~T7_E~0); 75#L1436-1true assume !(1 == ~T8_E~0); 745#L1441-1true assume !(1 == ~T9_E~0); 483#L1446-1true assume !(1 == ~T10_E~0); 1772#L1451-1true assume !(1 == ~T11_E~0); 1107#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 744#L1461-1true assume !(1 == ~T13_E~0); 436#L1466-1true assume !(1 == ~E_1~0); 1767#L1471-1true assume !(1 == ~E_2~0); 1082#L1476-1true assume !(1 == ~E_3~0); 1314#L1481-1true assume !(1 == ~E_4~0); 1592#L1486-1true assume !(1 == ~E_5~0); 225#L1491-1true assume !(1 == ~E_6~0); 42#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 756#L1501-1true assume !(1 == ~E_8~0); 481#L1506-1true assume !(1 == ~E_9~0); 1037#L1511-1true assume !(1 == ~E_10~0); 454#L1516-1true assume !(1 == ~E_11~0); 14#L1521-1true assume !(1 == ~E_12~0); 41#L1526-1true assume !(1 == ~E_13~0); 319#L1531-1true assume { :end_inline_reset_delta_events } true; 1171#L1892-2true [2022-02-21 04:24:24,175 INFO L793 eck$LassoCheckResult]: Loop: 1171#L1892-2true assume !false; 1867#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1513#L1233true assume !true; 81#L1248true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 804#L874-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1629#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1898#L1258-5true assume !(0 == ~T1_E~0); 154#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1603#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1618#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1905#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1620#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 267#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1788#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1168#L1298-3true assume !(0 == ~T9_E~0); 1693#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1427#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1167#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 658#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 155#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1301#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1672#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 229#L1338-3true assume !(0 == ~E_4~0); 1055#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1540#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1311#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1352#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 627#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 340#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1884#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 884#L1378-3true assume !(0 == ~E_12~0); 1459#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1099#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1766#L607-42true assume !(1 == ~m_pc~0); 911#L607-44true is_master_triggered_~__retres1~0#1 := 0; 510#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1075#L619-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 697#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1219#L626-42true assume 1 == ~t1_pc~0; 399#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1471#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600#L638-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1130#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 171#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1573#L645-42true assume 1 == ~t2_pc~0; 1415#L646-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1695#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1252#L657-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1661#L664-42true assume 1 == ~t3_pc~0; 457#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1623#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1474#L676-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 832#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1015#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1787#L683-42true assume 1 == ~t4_pc~0; 1698#L684-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 840#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1768#L695-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1411#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1903#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162#L702-42true assume !(1 == ~t5_pc~0); 395#L702-44true is_transmit5_triggered_~__retres1~5#1 := 0; 590#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1733#L714-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1287#L1600-42true assume !(0 != activate_threads_~tmp___4~0#1); 33#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114#L721-42true assume 1 == ~t6_pc~0; 123#L722-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 368#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1619#L733-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1587#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 470#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379#L740-42true assume !(1 == ~t7_pc~0); 236#L740-44true is_transmit7_triggered_~__retres1~7#1 := 0; 561#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560#L752-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 459#L1616-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 650#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1895#L759-42true assume 1 == ~t8_pc~0; 540#L760-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 493#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 673#L771-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 547#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 617#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1174#L778-42true assume !(1 == ~t9_pc~0); 620#L778-44true is_transmit9_triggered_~__retres1~9#1 := 0; 808#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1749#L790-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 732#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1612#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 780#L797-42true assume !(1 == ~t10_pc~0); 1045#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 937#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1375#L809-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1876#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 809#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1708#L816-42true assume !(1 == ~t11_pc~0); 347#L816-44true is_transmit11_triggered_~__retres1~11#1 := 0; 1851#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 285#L828-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 486#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 328#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 587#L835-42true assume !(1 == ~t12_pc~0); 507#L835-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1243#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 314#L847-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1837#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1236#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 949#L854-42true assume 1 == ~t13_pc~0; 1781#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 482#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86#L866-14true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 515#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 435#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1854#L1401-3true assume !(1 == ~M_E~0); 1093#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 204#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 136#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1679#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 465#L1421-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1052#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 228#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 293#L1436-3true assume !(1 == ~T8_E~0); 17#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1144#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1135#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 521#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 309#L1461-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1610#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1816#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 279#L1476-3true assume !(1 == ~E_3~0); 1686#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 514#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 292#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1481#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 544#L1501-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1594#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 881#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 874#L1516-3true assume !(1 == ~E_11~0); 1718#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 630#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 969#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1842#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1880#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 760#L1032-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 494#L1911true assume !(0 == start_simulation_~tmp~3#1); 1304#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 906#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1024#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 842#L1032-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 107#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 224#L1874true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1348#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1171#L1892-2true [2022-02-21 04:24:24,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,180 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2022-02-21 04:24:24,186 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,187 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834124810] [2022-02-21 04:24:24,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,347 INFO L290 TraceCheckUtils]: 0: Hoare triple {1924#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {1924#true} is VALID [2022-02-21 04:24:24,348 INFO L290 TraceCheckUtils]: 1: Hoare triple {1924#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {1926#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:24,349 INFO L290 TraceCheckUtils]: 2: Hoare triple {1926#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1926#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:24,349 INFO L290 TraceCheckUtils]: 3: Hoare triple {1926#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1926#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:24,350 INFO L290 TraceCheckUtils]: 4: Hoare triple {1926#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,350 INFO L290 TraceCheckUtils]: 5: Hoare triple {1925#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1925#false} is VALID [2022-02-21 04:24:24,350 INFO L290 TraceCheckUtils]: 6: Hoare triple {1925#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,350 INFO L290 TraceCheckUtils]: 7: Hoare triple {1925#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 8: Hoare triple {1925#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 9: Hoare triple {1925#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 10: Hoare triple {1925#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 11: Hoare triple {1925#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,352 INFO L290 TraceCheckUtils]: 12: Hoare triple {1925#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,352 INFO L290 TraceCheckUtils]: 13: Hoare triple {1925#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1925#false} is VALID [2022-02-21 04:24:24,352 INFO L290 TraceCheckUtils]: 14: Hoare triple {1925#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,353 INFO L290 TraceCheckUtils]: 15: Hoare triple {1925#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,353 INFO L290 TraceCheckUtils]: 16: Hoare triple {1925#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,353 INFO L290 TraceCheckUtils]: 17: Hoare triple {1925#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,353 INFO L290 TraceCheckUtils]: 18: Hoare triple {1925#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1925#false} is VALID [2022-02-21 04:24:24,354 INFO L290 TraceCheckUtils]: 19: Hoare triple {1925#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1925#false} is VALID [2022-02-21 04:24:24,354 INFO L290 TraceCheckUtils]: 20: Hoare triple {1925#false} assume !(0 == ~T1_E~0); {1925#false} is VALID [2022-02-21 04:24:24,354 INFO L290 TraceCheckUtils]: 21: Hoare triple {1925#false} assume !(0 == ~T2_E~0); {1925#false} is VALID [2022-02-21 04:24:24,354 INFO L290 TraceCheckUtils]: 22: Hoare triple {1925#false} assume !(0 == ~T3_E~0); {1925#false} is VALID [2022-02-21 04:24:24,354 INFO L290 TraceCheckUtils]: 23: Hoare triple {1925#false} assume !(0 == ~T4_E~0); {1925#false} is VALID [2022-02-21 04:24:24,355 INFO L290 TraceCheckUtils]: 24: Hoare triple {1925#false} assume !(0 == ~T5_E~0); {1925#false} is VALID [2022-02-21 04:24:24,355 INFO L290 TraceCheckUtils]: 25: Hoare triple {1925#false} assume !(0 == ~T6_E~0); {1925#false} is VALID [2022-02-21 04:24:24,355 INFO L290 TraceCheckUtils]: 26: Hoare triple {1925#false} assume !(0 == ~T7_E~0); {1925#false} is VALID [2022-02-21 04:24:24,355 INFO L290 TraceCheckUtils]: 27: Hoare triple {1925#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1925#false} is VALID [2022-02-21 04:24:24,356 INFO L290 TraceCheckUtils]: 28: Hoare triple {1925#false} assume !(0 == ~T9_E~0); {1925#false} is VALID [2022-02-21 04:24:24,356 INFO L290 TraceCheckUtils]: 29: Hoare triple {1925#false} assume !(0 == ~T10_E~0); {1925#false} is VALID [2022-02-21 04:24:24,356 INFO L290 TraceCheckUtils]: 30: Hoare triple {1925#false} assume !(0 == ~T11_E~0); {1925#false} is VALID [2022-02-21 04:24:24,356 INFO L290 TraceCheckUtils]: 31: Hoare triple {1925#false} assume !(0 == ~T12_E~0); {1925#false} is VALID [2022-02-21 04:24:24,357 INFO L290 TraceCheckUtils]: 32: Hoare triple {1925#false} assume !(0 == ~T13_E~0); {1925#false} is VALID [2022-02-21 04:24:24,357 INFO L290 TraceCheckUtils]: 33: Hoare triple {1925#false} assume !(0 == ~E_1~0); {1925#false} is VALID [2022-02-21 04:24:24,357 INFO L290 TraceCheckUtils]: 34: Hoare triple {1925#false} assume !(0 == ~E_2~0); {1925#false} is VALID [2022-02-21 04:24:24,357 INFO L290 TraceCheckUtils]: 35: Hoare triple {1925#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1925#false} is VALID [2022-02-21 04:24:24,357 INFO L290 TraceCheckUtils]: 36: Hoare triple {1925#false} assume !(0 == ~E_4~0); {1925#false} is VALID [2022-02-21 04:24:24,358 INFO L290 TraceCheckUtils]: 37: Hoare triple {1925#false} assume !(0 == ~E_5~0); {1925#false} is VALID [2022-02-21 04:24:24,358 INFO L290 TraceCheckUtils]: 38: Hoare triple {1925#false} assume !(0 == ~E_6~0); {1925#false} is VALID [2022-02-21 04:24:24,358 INFO L290 TraceCheckUtils]: 39: Hoare triple {1925#false} assume !(0 == ~E_7~0); {1925#false} is VALID [2022-02-21 04:24:24,358 INFO L290 TraceCheckUtils]: 40: Hoare triple {1925#false} assume !(0 == ~E_8~0); {1925#false} is VALID [2022-02-21 04:24:24,358 INFO L290 TraceCheckUtils]: 41: Hoare triple {1925#false} assume !(0 == ~E_9~0); {1925#false} is VALID [2022-02-21 04:24:24,359 INFO L290 TraceCheckUtils]: 42: Hoare triple {1925#false} assume !(0 == ~E_10~0); {1925#false} is VALID [2022-02-21 04:24:24,359 INFO L290 TraceCheckUtils]: 43: Hoare triple {1925#false} assume 0 == ~E_11~0;~E_11~0 := 1; {1925#false} is VALID [2022-02-21 04:24:24,359 INFO L290 TraceCheckUtils]: 44: Hoare triple {1925#false} assume !(0 == ~E_12~0); {1925#false} is VALID [2022-02-21 04:24:24,359 INFO L290 TraceCheckUtils]: 45: Hoare triple {1925#false} assume !(0 == ~E_13~0); {1925#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 46: Hoare triple {1925#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1925#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 47: Hoare triple {1925#false} assume 1 == ~m_pc~0; {1925#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 48: Hoare triple {1925#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {1925#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 49: Hoare triple {1925#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1925#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 50: Hoare triple {1925#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1925#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 51: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp~1#1); {1925#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 52: Hoare triple {1925#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1925#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 53: Hoare triple {1925#false} assume !(1 == ~t1_pc~0); {1925#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 54: Hoare triple {1925#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1925#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 55: Hoare triple {1925#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1925#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 56: Hoare triple {1925#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1925#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 57: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___0~0#1); {1925#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 58: Hoare triple {1925#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1925#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 59: Hoare triple {1925#false} assume 1 == ~t2_pc~0; {1925#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 60: Hoare triple {1925#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1925#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 61: Hoare triple {1925#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1925#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 62: Hoare triple {1925#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1925#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 63: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___1~0#1); {1925#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 64: Hoare triple {1925#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1925#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 65: Hoare triple {1925#false} assume 1 == ~t3_pc~0; {1925#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 66: Hoare triple {1925#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1925#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 67: Hoare triple {1925#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1925#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 68: Hoare triple {1925#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1925#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 69: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___2~0#1); {1925#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 70: Hoare triple {1925#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1925#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 71: Hoare triple {1925#false} assume !(1 == ~t4_pc~0); {1925#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 72: Hoare triple {1925#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1925#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 73: Hoare triple {1925#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1925#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 74: Hoare triple {1925#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1925#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 75: Hoare triple {1925#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1925#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 76: Hoare triple {1925#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1925#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 77: Hoare triple {1925#false} assume 1 == ~t5_pc~0; {1925#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 78: Hoare triple {1925#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1925#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 79: Hoare triple {1925#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1925#false} is VALID [2022-02-21 04:24:24,367 INFO L290 TraceCheckUtils]: 80: Hoare triple {1925#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1925#false} is VALID [2022-02-21 04:24:24,367 INFO L290 TraceCheckUtils]: 81: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___4~0#1); {1925#false} is VALID [2022-02-21 04:24:24,367 INFO L290 TraceCheckUtils]: 82: Hoare triple {1925#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1925#false} is VALID [2022-02-21 04:24:24,367 INFO L290 TraceCheckUtils]: 83: Hoare triple {1925#false} assume !(1 == ~t6_pc~0); {1925#false} is VALID [2022-02-21 04:24:24,367 INFO L290 TraceCheckUtils]: 84: Hoare triple {1925#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1925#false} is VALID [2022-02-21 04:24:24,368 INFO L290 TraceCheckUtils]: 85: Hoare triple {1925#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1925#false} is VALID [2022-02-21 04:24:24,368 INFO L290 TraceCheckUtils]: 86: Hoare triple {1925#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1925#false} is VALID [2022-02-21 04:24:24,368 INFO L290 TraceCheckUtils]: 87: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___5~0#1); {1925#false} is VALID [2022-02-21 04:24:24,368 INFO L290 TraceCheckUtils]: 88: Hoare triple {1925#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1925#false} is VALID [2022-02-21 04:24:24,368 INFO L290 TraceCheckUtils]: 89: Hoare triple {1925#false} assume 1 == ~t7_pc~0; {1925#false} is VALID [2022-02-21 04:24:24,369 INFO L290 TraceCheckUtils]: 90: Hoare triple {1925#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1925#false} is VALID [2022-02-21 04:24:24,369 INFO L290 TraceCheckUtils]: 91: Hoare triple {1925#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1925#false} is VALID [2022-02-21 04:24:24,369 INFO L290 TraceCheckUtils]: 92: Hoare triple {1925#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1925#false} is VALID [2022-02-21 04:24:24,369 INFO L290 TraceCheckUtils]: 93: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___6~0#1); {1925#false} is VALID [2022-02-21 04:24:24,369 INFO L290 TraceCheckUtils]: 94: Hoare triple {1925#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1925#false} is VALID [2022-02-21 04:24:24,369 INFO L290 TraceCheckUtils]: 95: Hoare triple {1925#false} assume !(1 == ~t8_pc~0); {1925#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 96: Hoare triple {1925#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1925#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 97: Hoare triple {1925#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1925#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 98: Hoare triple {1925#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1925#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 99: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___7~0#1); {1925#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 100: Hoare triple {1925#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1925#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 101: Hoare triple {1925#false} assume 1 == ~t9_pc~0; {1925#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 102: Hoare triple {1925#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1925#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 103: Hoare triple {1925#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1925#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 104: Hoare triple {1925#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1925#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 105: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___8~0#1); {1925#false} is VALID [2022-02-21 04:24:24,372 INFO L290 TraceCheckUtils]: 106: Hoare triple {1925#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1925#false} is VALID [2022-02-21 04:24:24,372 INFO L290 TraceCheckUtils]: 107: Hoare triple {1925#false} assume !(1 == ~t10_pc~0); {1925#false} is VALID [2022-02-21 04:24:24,372 INFO L290 TraceCheckUtils]: 108: Hoare triple {1925#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1925#false} is VALID [2022-02-21 04:24:24,372 INFO L290 TraceCheckUtils]: 109: Hoare triple {1925#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1925#false} is VALID [2022-02-21 04:24:24,372 INFO L290 TraceCheckUtils]: 110: Hoare triple {1925#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1925#false} is VALID [2022-02-21 04:24:24,373 INFO L290 TraceCheckUtils]: 111: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___9~0#1); {1925#false} is VALID [2022-02-21 04:24:24,373 INFO L290 TraceCheckUtils]: 112: Hoare triple {1925#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1925#false} is VALID [2022-02-21 04:24:24,373 INFO L290 TraceCheckUtils]: 113: Hoare triple {1925#false} assume 1 == ~t11_pc~0; {1925#false} is VALID [2022-02-21 04:24:24,373 INFO L290 TraceCheckUtils]: 114: Hoare triple {1925#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {1925#false} is VALID [2022-02-21 04:24:24,373 INFO L290 TraceCheckUtils]: 115: Hoare triple {1925#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1925#false} is VALID [2022-02-21 04:24:24,374 INFO L290 TraceCheckUtils]: 116: Hoare triple {1925#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1925#false} is VALID [2022-02-21 04:24:24,374 INFO L290 TraceCheckUtils]: 117: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___10~0#1); {1925#false} is VALID [2022-02-21 04:24:24,374 INFO L290 TraceCheckUtils]: 118: Hoare triple {1925#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1925#false} is VALID [2022-02-21 04:24:24,374 INFO L290 TraceCheckUtils]: 119: Hoare triple {1925#false} assume 1 == ~t12_pc~0; {1925#false} is VALID [2022-02-21 04:24:24,374 INFO L290 TraceCheckUtils]: 120: Hoare triple {1925#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {1925#false} is VALID [2022-02-21 04:24:24,375 INFO L290 TraceCheckUtils]: 121: Hoare triple {1925#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1925#false} is VALID [2022-02-21 04:24:24,375 INFO L290 TraceCheckUtils]: 122: Hoare triple {1925#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {1925#false} is VALID [2022-02-21 04:24:24,375 INFO L290 TraceCheckUtils]: 123: Hoare triple {1925#false} assume !(0 != activate_threads_~tmp___11~0#1); {1925#false} is VALID [2022-02-21 04:24:24,375 INFO L290 TraceCheckUtils]: 124: Hoare triple {1925#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {1925#false} is VALID [2022-02-21 04:24:24,375 INFO L290 TraceCheckUtils]: 125: Hoare triple {1925#false} assume !(1 == ~t13_pc~0); {1925#false} is VALID [2022-02-21 04:24:24,376 INFO L290 TraceCheckUtils]: 126: Hoare triple {1925#false} is_transmit13_triggered_~__retres1~13#1 := 0; {1925#false} is VALID [2022-02-21 04:24:24,376 INFO L290 TraceCheckUtils]: 127: Hoare triple {1925#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {1925#false} is VALID [2022-02-21 04:24:24,376 INFO L290 TraceCheckUtils]: 128: Hoare triple {1925#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {1925#false} is VALID [2022-02-21 04:24:24,376 INFO L290 TraceCheckUtils]: 129: Hoare triple {1925#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {1925#false} is VALID [2022-02-21 04:24:24,377 INFO L290 TraceCheckUtils]: 130: Hoare triple {1925#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1925#false} is VALID [2022-02-21 04:24:24,377 INFO L290 TraceCheckUtils]: 131: Hoare triple {1925#false} assume !(1 == ~M_E~0); {1925#false} is VALID [2022-02-21 04:24:24,377 INFO L290 TraceCheckUtils]: 132: Hoare triple {1925#false} assume !(1 == ~T1_E~0); {1925#false} is VALID [2022-02-21 04:24:24,377 INFO L290 TraceCheckUtils]: 133: Hoare triple {1925#false} assume !(1 == ~T2_E~0); {1925#false} is VALID [2022-02-21 04:24:24,377 INFO L290 TraceCheckUtils]: 134: Hoare triple {1925#false} assume !(1 == ~T3_E~0); {1925#false} is VALID [2022-02-21 04:24:24,377 INFO L290 TraceCheckUtils]: 135: Hoare triple {1925#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,378 INFO L290 TraceCheckUtils]: 136: Hoare triple {1925#false} assume !(1 == ~T5_E~0); {1925#false} is VALID [2022-02-21 04:24:24,378 INFO L290 TraceCheckUtils]: 137: Hoare triple {1925#false} assume !(1 == ~T6_E~0); {1925#false} is VALID [2022-02-21 04:24:24,378 INFO L290 TraceCheckUtils]: 138: Hoare triple {1925#false} assume !(1 == ~T7_E~0); {1925#false} is VALID [2022-02-21 04:24:24,378 INFO L290 TraceCheckUtils]: 139: Hoare triple {1925#false} assume !(1 == ~T8_E~0); {1925#false} is VALID [2022-02-21 04:24:24,378 INFO L290 TraceCheckUtils]: 140: Hoare triple {1925#false} assume !(1 == ~T9_E~0); {1925#false} is VALID [2022-02-21 04:24:24,379 INFO L290 TraceCheckUtils]: 141: Hoare triple {1925#false} assume !(1 == ~T10_E~0); {1925#false} is VALID [2022-02-21 04:24:24,379 INFO L290 TraceCheckUtils]: 142: Hoare triple {1925#false} assume !(1 == ~T11_E~0); {1925#false} is VALID [2022-02-21 04:24:24,379 INFO L290 TraceCheckUtils]: 143: Hoare triple {1925#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,379 INFO L290 TraceCheckUtils]: 144: Hoare triple {1925#false} assume !(1 == ~T13_E~0); {1925#false} is VALID [2022-02-21 04:24:24,379 INFO L290 TraceCheckUtils]: 145: Hoare triple {1925#false} assume !(1 == ~E_1~0); {1925#false} is VALID [2022-02-21 04:24:24,380 INFO L290 TraceCheckUtils]: 146: Hoare triple {1925#false} assume !(1 == ~E_2~0); {1925#false} is VALID [2022-02-21 04:24:24,380 INFO L290 TraceCheckUtils]: 147: Hoare triple {1925#false} assume !(1 == ~E_3~0); {1925#false} is VALID [2022-02-21 04:24:24,380 INFO L290 TraceCheckUtils]: 148: Hoare triple {1925#false} assume !(1 == ~E_4~0); {1925#false} is VALID [2022-02-21 04:24:24,380 INFO L290 TraceCheckUtils]: 149: Hoare triple {1925#false} assume !(1 == ~E_5~0); {1925#false} is VALID [2022-02-21 04:24:24,380 INFO L290 TraceCheckUtils]: 150: Hoare triple {1925#false} assume !(1 == ~E_6~0); {1925#false} is VALID [2022-02-21 04:24:24,380 INFO L290 TraceCheckUtils]: 151: Hoare triple {1925#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1925#false} is VALID [2022-02-21 04:24:24,381 INFO L290 TraceCheckUtils]: 152: Hoare triple {1925#false} assume !(1 == ~E_8~0); {1925#false} is VALID [2022-02-21 04:24:24,381 INFO L290 TraceCheckUtils]: 153: Hoare triple {1925#false} assume !(1 == ~E_9~0); {1925#false} is VALID [2022-02-21 04:24:24,381 INFO L290 TraceCheckUtils]: 154: Hoare triple {1925#false} assume !(1 == ~E_10~0); {1925#false} is VALID [2022-02-21 04:24:24,381 INFO L290 TraceCheckUtils]: 155: Hoare triple {1925#false} assume !(1 == ~E_11~0); {1925#false} is VALID [2022-02-21 04:24:24,381 INFO L290 TraceCheckUtils]: 156: Hoare triple {1925#false} assume !(1 == ~E_12~0); {1925#false} is VALID [2022-02-21 04:24:24,382 INFO L290 TraceCheckUtils]: 157: Hoare triple {1925#false} assume !(1 == ~E_13~0); {1925#false} is VALID [2022-02-21 04:24:24,382 INFO L290 TraceCheckUtils]: 158: Hoare triple {1925#false} assume { :end_inline_reset_delta_events } true; {1925#false} is VALID [2022-02-21 04:24:24,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,384 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,384 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834124810] [2022-02-21 04:24:24,384 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834124810] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,385 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,385 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,386 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493859376] [2022-02-21 04:24:24,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,389 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:24,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1403862028, now seen corresponding path program 1 times [2022-02-21 04:24:24,390 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,391 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025714720] [2022-02-21 04:24:24,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,440 INFO L290 TraceCheckUtils]: 0: Hoare triple {1927#true} assume !false; {1927#true} is VALID [2022-02-21 04:24:24,440 INFO L290 TraceCheckUtils]: 1: Hoare triple {1927#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1927#true} is VALID [2022-02-21 04:24:24,441 INFO L290 TraceCheckUtils]: 2: Hoare triple {1927#true} assume !true; {1928#false} is VALID [2022-02-21 04:24:24,441 INFO L290 TraceCheckUtils]: 3: Hoare triple {1928#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1928#false} is VALID [2022-02-21 04:24:24,441 INFO L290 TraceCheckUtils]: 4: Hoare triple {1928#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1928#false} is VALID [2022-02-21 04:24:24,441 INFO L290 TraceCheckUtils]: 5: Hoare triple {1928#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,441 INFO L290 TraceCheckUtils]: 6: Hoare triple {1928#false} assume !(0 == ~T1_E~0); {1928#false} is VALID [2022-02-21 04:24:24,442 INFO L290 TraceCheckUtils]: 7: Hoare triple {1928#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,442 INFO L290 TraceCheckUtils]: 8: Hoare triple {1928#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,442 INFO L290 TraceCheckUtils]: 9: Hoare triple {1928#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,442 INFO L290 TraceCheckUtils]: 10: Hoare triple {1928#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,442 INFO L290 TraceCheckUtils]: 11: Hoare triple {1928#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,442 INFO L290 TraceCheckUtils]: 12: Hoare triple {1928#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,443 INFO L290 TraceCheckUtils]: 13: Hoare triple {1928#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,443 INFO L290 TraceCheckUtils]: 14: Hoare triple {1928#false} assume !(0 == ~T9_E~0); {1928#false} is VALID [2022-02-21 04:24:24,443 INFO L290 TraceCheckUtils]: 15: Hoare triple {1928#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,443 INFO L290 TraceCheckUtils]: 16: Hoare triple {1928#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,443 INFO L290 TraceCheckUtils]: 17: Hoare triple {1928#false} assume 0 == ~T12_E~0;~T12_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,444 INFO L290 TraceCheckUtils]: 18: Hoare triple {1928#false} assume 0 == ~T13_E~0;~T13_E~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,444 INFO L290 TraceCheckUtils]: 19: Hoare triple {1928#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,444 INFO L290 TraceCheckUtils]: 20: Hoare triple {1928#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,444 INFO L290 TraceCheckUtils]: 21: Hoare triple {1928#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,444 INFO L290 TraceCheckUtils]: 22: Hoare triple {1928#false} assume !(0 == ~E_4~0); {1928#false} is VALID [2022-02-21 04:24:24,444 INFO L290 TraceCheckUtils]: 23: Hoare triple {1928#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,445 INFO L290 TraceCheckUtils]: 24: Hoare triple {1928#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,445 INFO L290 TraceCheckUtils]: 25: Hoare triple {1928#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,445 INFO L290 TraceCheckUtils]: 26: Hoare triple {1928#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,445 INFO L290 TraceCheckUtils]: 27: Hoare triple {1928#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,445 INFO L290 TraceCheckUtils]: 28: Hoare triple {1928#false} assume 0 == ~E_10~0;~E_10~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,445 INFO L290 TraceCheckUtils]: 29: Hoare triple {1928#false} assume 0 == ~E_11~0;~E_11~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,446 INFO L290 TraceCheckUtils]: 30: Hoare triple {1928#false} assume !(0 == ~E_12~0); {1928#false} is VALID [2022-02-21 04:24:24,446 INFO L290 TraceCheckUtils]: 31: Hoare triple {1928#false} assume 0 == ~E_13~0;~E_13~0 := 1; {1928#false} is VALID [2022-02-21 04:24:24,446 INFO L290 TraceCheckUtils]: 32: Hoare triple {1928#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1928#false} is VALID [2022-02-21 04:24:24,446 INFO L290 TraceCheckUtils]: 33: Hoare triple {1928#false} assume !(1 == ~m_pc~0); {1928#false} is VALID [2022-02-21 04:24:24,446 INFO L290 TraceCheckUtils]: 34: Hoare triple {1928#false} is_master_triggered_~__retres1~0#1 := 0; {1928#false} is VALID [2022-02-21 04:24:24,447 INFO L290 TraceCheckUtils]: 35: Hoare triple {1928#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1928#false} is VALID [2022-02-21 04:24:24,447 INFO L290 TraceCheckUtils]: 36: Hoare triple {1928#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1928#false} is VALID [2022-02-21 04:24:24,447 INFO L290 TraceCheckUtils]: 37: Hoare triple {1928#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,447 INFO L290 TraceCheckUtils]: 38: Hoare triple {1928#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1928#false} is VALID [2022-02-21 04:24:24,447 INFO L290 TraceCheckUtils]: 39: Hoare triple {1928#false} assume 1 == ~t1_pc~0; {1928#false} is VALID [2022-02-21 04:24:24,448 INFO L290 TraceCheckUtils]: 40: Hoare triple {1928#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1928#false} is VALID [2022-02-21 04:24:24,448 INFO L290 TraceCheckUtils]: 41: Hoare triple {1928#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1928#false} is VALID [2022-02-21 04:24:24,448 INFO L290 TraceCheckUtils]: 42: Hoare triple {1928#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1928#false} is VALID [2022-02-21 04:24:24,448 INFO L290 TraceCheckUtils]: 43: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,448 INFO L290 TraceCheckUtils]: 44: Hoare triple {1928#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1928#false} is VALID [2022-02-21 04:24:24,449 INFO L290 TraceCheckUtils]: 45: Hoare triple {1928#false} assume 1 == ~t2_pc~0; {1928#false} is VALID [2022-02-21 04:24:24,449 INFO L290 TraceCheckUtils]: 46: Hoare triple {1928#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1928#false} is VALID [2022-02-21 04:24:24,449 INFO L290 TraceCheckUtils]: 47: Hoare triple {1928#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1928#false} is VALID [2022-02-21 04:24:24,449 INFO L290 TraceCheckUtils]: 48: Hoare triple {1928#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1928#false} is VALID [2022-02-21 04:24:24,449 INFO L290 TraceCheckUtils]: 49: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,450 INFO L290 TraceCheckUtils]: 50: Hoare triple {1928#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1928#false} is VALID [2022-02-21 04:24:24,450 INFO L290 TraceCheckUtils]: 51: Hoare triple {1928#false} assume 1 == ~t3_pc~0; {1928#false} is VALID [2022-02-21 04:24:24,450 INFO L290 TraceCheckUtils]: 52: Hoare triple {1928#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1928#false} is VALID [2022-02-21 04:24:24,450 INFO L290 TraceCheckUtils]: 53: Hoare triple {1928#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1928#false} is VALID [2022-02-21 04:24:24,450 INFO L290 TraceCheckUtils]: 54: Hoare triple {1928#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1928#false} is VALID [2022-02-21 04:24:24,450 INFO L290 TraceCheckUtils]: 55: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,451 INFO L290 TraceCheckUtils]: 56: Hoare triple {1928#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1928#false} is VALID [2022-02-21 04:24:24,451 INFO L290 TraceCheckUtils]: 57: Hoare triple {1928#false} assume 1 == ~t4_pc~0; {1928#false} is VALID [2022-02-21 04:24:24,451 INFO L290 TraceCheckUtils]: 58: Hoare triple {1928#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1928#false} is VALID [2022-02-21 04:24:24,451 INFO L290 TraceCheckUtils]: 59: Hoare triple {1928#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1928#false} is VALID [2022-02-21 04:24:24,451 INFO L290 TraceCheckUtils]: 60: Hoare triple {1928#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1928#false} is VALID [2022-02-21 04:24:24,452 INFO L290 TraceCheckUtils]: 61: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,452 INFO L290 TraceCheckUtils]: 62: Hoare triple {1928#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1928#false} is VALID [2022-02-21 04:24:24,452 INFO L290 TraceCheckUtils]: 63: Hoare triple {1928#false} assume !(1 == ~t5_pc~0); {1928#false} is VALID [2022-02-21 04:24:24,452 INFO L290 TraceCheckUtils]: 64: Hoare triple {1928#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1928#false} is VALID [2022-02-21 04:24:24,452 INFO L290 TraceCheckUtils]: 65: Hoare triple {1928#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1928#false} is VALID [2022-02-21 04:24:24,453 INFO L290 TraceCheckUtils]: 66: Hoare triple {1928#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1928#false} is VALID [2022-02-21 04:24:24,453 INFO L290 TraceCheckUtils]: 67: Hoare triple {1928#false} assume !(0 != activate_threads_~tmp___4~0#1); {1928#false} is VALID [2022-02-21 04:24:24,453 INFO L290 TraceCheckUtils]: 68: Hoare triple {1928#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1928#false} is VALID [2022-02-21 04:24:24,453 INFO L290 TraceCheckUtils]: 69: Hoare triple {1928#false} assume 1 == ~t6_pc~0; {1928#false} is VALID [2022-02-21 04:24:24,453 INFO L290 TraceCheckUtils]: 70: Hoare triple {1928#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1928#false} is VALID [2022-02-21 04:24:24,453 INFO L290 TraceCheckUtils]: 71: Hoare triple {1928#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1928#false} is VALID [2022-02-21 04:24:24,454 INFO L290 TraceCheckUtils]: 72: Hoare triple {1928#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1928#false} is VALID [2022-02-21 04:24:24,454 INFO L290 TraceCheckUtils]: 73: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,454 INFO L290 TraceCheckUtils]: 74: Hoare triple {1928#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1928#false} is VALID [2022-02-21 04:24:24,454 INFO L290 TraceCheckUtils]: 75: Hoare triple {1928#false} assume !(1 == ~t7_pc~0); {1928#false} is VALID [2022-02-21 04:24:24,454 INFO L290 TraceCheckUtils]: 76: Hoare triple {1928#false} is_transmit7_triggered_~__retres1~7#1 := 0; {1928#false} is VALID [2022-02-21 04:24:24,455 INFO L290 TraceCheckUtils]: 77: Hoare triple {1928#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1928#false} is VALID [2022-02-21 04:24:24,455 INFO L290 TraceCheckUtils]: 78: Hoare triple {1928#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1928#false} is VALID [2022-02-21 04:24:24,455 INFO L290 TraceCheckUtils]: 79: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,455 INFO L290 TraceCheckUtils]: 80: Hoare triple {1928#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1928#false} is VALID [2022-02-21 04:24:24,455 INFO L290 TraceCheckUtils]: 81: Hoare triple {1928#false} assume 1 == ~t8_pc~0; {1928#false} is VALID [2022-02-21 04:24:24,456 INFO L290 TraceCheckUtils]: 82: Hoare triple {1928#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1928#false} is VALID [2022-02-21 04:24:24,456 INFO L290 TraceCheckUtils]: 83: Hoare triple {1928#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1928#false} is VALID [2022-02-21 04:24:24,456 INFO L290 TraceCheckUtils]: 84: Hoare triple {1928#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1928#false} is VALID [2022-02-21 04:24:24,456 INFO L290 TraceCheckUtils]: 85: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,456 INFO L290 TraceCheckUtils]: 86: Hoare triple {1928#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1928#false} is VALID [2022-02-21 04:24:24,457 INFO L290 TraceCheckUtils]: 87: Hoare triple {1928#false} assume !(1 == ~t9_pc~0); {1928#false} is VALID [2022-02-21 04:24:24,457 INFO L290 TraceCheckUtils]: 88: Hoare triple {1928#false} is_transmit9_triggered_~__retres1~9#1 := 0; {1928#false} is VALID [2022-02-21 04:24:24,457 INFO L290 TraceCheckUtils]: 89: Hoare triple {1928#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1928#false} is VALID [2022-02-21 04:24:24,457 INFO L290 TraceCheckUtils]: 90: Hoare triple {1928#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1928#false} is VALID [2022-02-21 04:24:24,457 INFO L290 TraceCheckUtils]: 91: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,457 INFO L290 TraceCheckUtils]: 92: Hoare triple {1928#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1928#false} is VALID [2022-02-21 04:24:24,458 INFO L290 TraceCheckUtils]: 93: Hoare triple {1928#false} assume !(1 == ~t10_pc~0); {1928#false} is VALID [2022-02-21 04:24:24,458 INFO L290 TraceCheckUtils]: 94: Hoare triple {1928#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1928#false} is VALID [2022-02-21 04:24:24,458 INFO L290 TraceCheckUtils]: 95: Hoare triple {1928#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1928#false} is VALID [2022-02-21 04:24:24,458 INFO L290 TraceCheckUtils]: 96: Hoare triple {1928#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1928#false} is VALID [2022-02-21 04:24:24,458 INFO L290 TraceCheckUtils]: 97: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,459 INFO L290 TraceCheckUtils]: 98: Hoare triple {1928#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1928#false} is VALID [2022-02-21 04:24:24,459 INFO L290 TraceCheckUtils]: 99: Hoare triple {1928#false} assume !(1 == ~t11_pc~0); {1928#false} is VALID [2022-02-21 04:24:24,459 INFO L290 TraceCheckUtils]: 100: Hoare triple {1928#false} is_transmit11_triggered_~__retres1~11#1 := 0; {1928#false} is VALID [2022-02-21 04:24:24,459 INFO L290 TraceCheckUtils]: 101: Hoare triple {1928#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1928#false} is VALID [2022-02-21 04:24:24,459 INFO L290 TraceCheckUtils]: 102: Hoare triple {1928#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1928#false} is VALID [2022-02-21 04:24:24,459 INFO L290 TraceCheckUtils]: 103: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,460 INFO L290 TraceCheckUtils]: 104: Hoare triple {1928#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1928#false} is VALID [2022-02-21 04:24:24,460 INFO L290 TraceCheckUtils]: 105: Hoare triple {1928#false} assume !(1 == ~t12_pc~0); {1928#false} is VALID [2022-02-21 04:24:24,460 INFO L290 TraceCheckUtils]: 106: Hoare triple {1928#false} is_transmit12_triggered_~__retres1~12#1 := 0; {1928#false} is VALID [2022-02-21 04:24:24,460 INFO L290 TraceCheckUtils]: 107: Hoare triple {1928#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1928#false} is VALID [2022-02-21 04:24:24,460 INFO L290 TraceCheckUtils]: 108: Hoare triple {1928#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {1928#false} is VALID [2022-02-21 04:24:24,461 INFO L290 TraceCheckUtils]: 109: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,461 INFO L290 TraceCheckUtils]: 110: Hoare triple {1928#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {1928#false} is VALID [2022-02-21 04:24:24,461 INFO L290 TraceCheckUtils]: 111: Hoare triple {1928#false} assume 1 == ~t13_pc~0; {1928#false} is VALID [2022-02-21 04:24:24,461 INFO L290 TraceCheckUtils]: 112: Hoare triple {1928#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {1928#false} is VALID [2022-02-21 04:24:24,461 INFO L290 TraceCheckUtils]: 113: Hoare triple {1928#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {1928#false} is VALID [2022-02-21 04:24:24,462 INFO L290 TraceCheckUtils]: 114: Hoare triple {1928#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {1928#false} is VALID [2022-02-21 04:24:24,462 INFO L290 TraceCheckUtils]: 115: Hoare triple {1928#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {1928#false} is VALID [2022-02-21 04:24:24,462 INFO L290 TraceCheckUtils]: 116: Hoare triple {1928#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1928#false} is VALID [2022-02-21 04:24:24,462 INFO L290 TraceCheckUtils]: 117: Hoare triple {1928#false} assume !(1 == ~M_E~0); {1928#false} is VALID [2022-02-21 04:24:24,462 INFO L290 TraceCheckUtils]: 118: Hoare triple {1928#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,463 INFO L290 TraceCheckUtils]: 119: Hoare triple {1928#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,463 INFO L290 TraceCheckUtils]: 120: Hoare triple {1928#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,463 INFO L290 TraceCheckUtils]: 121: Hoare triple {1928#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,463 INFO L290 TraceCheckUtils]: 122: Hoare triple {1928#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,463 INFO L290 TraceCheckUtils]: 123: Hoare triple {1928#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,463 INFO L290 TraceCheckUtils]: 124: Hoare triple {1928#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,464 INFO L290 TraceCheckUtils]: 125: Hoare triple {1928#false} assume !(1 == ~T8_E~0); {1928#false} is VALID [2022-02-21 04:24:24,464 INFO L290 TraceCheckUtils]: 126: Hoare triple {1928#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,464 INFO L290 TraceCheckUtils]: 127: Hoare triple {1928#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,464 INFO L290 TraceCheckUtils]: 128: Hoare triple {1928#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,464 INFO L290 TraceCheckUtils]: 129: Hoare triple {1928#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,465 INFO L290 TraceCheckUtils]: 130: Hoare triple {1928#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,465 INFO L290 TraceCheckUtils]: 131: Hoare triple {1928#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,465 INFO L290 TraceCheckUtils]: 132: Hoare triple {1928#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,465 INFO L290 TraceCheckUtils]: 133: Hoare triple {1928#false} assume !(1 == ~E_3~0); {1928#false} is VALID [2022-02-21 04:24:24,465 INFO L290 TraceCheckUtils]: 134: Hoare triple {1928#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,465 INFO L290 TraceCheckUtils]: 135: Hoare triple {1928#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,466 INFO L290 TraceCheckUtils]: 136: Hoare triple {1928#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,466 INFO L290 TraceCheckUtils]: 137: Hoare triple {1928#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,466 INFO L290 TraceCheckUtils]: 138: Hoare triple {1928#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,466 INFO L290 TraceCheckUtils]: 139: Hoare triple {1928#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,466 INFO L290 TraceCheckUtils]: 140: Hoare triple {1928#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,467 INFO L290 TraceCheckUtils]: 141: Hoare triple {1928#false} assume !(1 == ~E_11~0); {1928#false} is VALID [2022-02-21 04:24:24,467 INFO L290 TraceCheckUtils]: 142: Hoare triple {1928#false} assume 1 == ~E_12~0;~E_12~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,467 INFO L290 TraceCheckUtils]: 143: Hoare triple {1928#false} assume 1 == ~E_13~0;~E_13~0 := 2; {1928#false} is VALID [2022-02-21 04:24:24,467 INFO L290 TraceCheckUtils]: 144: Hoare triple {1928#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {1928#false} is VALID [2022-02-21 04:24:24,468 INFO L290 TraceCheckUtils]: 145: Hoare triple {1928#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {1928#false} is VALID [2022-02-21 04:24:24,468 INFO L290 TraceCheckUtils]: 146: Hoare triple {1928#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {1928#false} is VALID [2022-02-21 04:24:24,468 INFO L290 TraceCheckUtils]: 147: Hoare triple {1928#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {1928#false} is VALID [2022-02-21 04:24:24,468 INFO L290 TraceCheckUtils]: 148: Hoare triple {1928#false} assume !(0 == start_simulation_~tmp~3#1); {1928#false} is VALID [2022-02-21 04:24:24,468 INFO L290 TraceCheckUtils]: 149: Hoare triple {1928#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {1928#false} is VALID [2022-02-21 04:24:24,468 INFO L290 TraceCheckUtils]: 150: Hoare triple {1928#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {1928#false} is VALID [2022-02-21 04:24:24,469 INFO L290 TraceCheckUtils]: 151: Hoare triple {1928#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {1928#false} is VALID [2022-02-21 04:24:24,469 INFO L290 TraceCheckUtils]: 152: Hoare triple {1928#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {1928#false} is VALID [2022-02-21 04:24:24,469 INFO L290 TraceCheckUtils]: 153: Hoare triple {1928#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1928#false} is VALID [2022-02-21 04:24:24,469 INFO L290 TraceCheckUtils]: 154: Hoare triple {1928#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1928#false} is VALID [2022-02-21 04:24:24,469 INFO L290 TraceCheckUtils]: 155: Hoare triple {1928#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {1928#false} is VALID [2022-02-21 04:24:24,470 INFO L290 TraceCheckUtils]: 156: Hoare triple {1928#false} assume !(0 != start_simulation_~tmp___0~1#1); {1928#false} is VALID [2022-02-21 04:24:24,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,471 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,471 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025714720] [2022-02-21 04:24:24,471 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025714720] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,471 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,471 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:24,471 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479428088] [2022-02-21 04:24:24,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,473 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:24,473 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:24,490 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:24:24,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:24:24,497 INFO L87 Difference]: Start difference. First operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,551 INFO L93 Difference]: Finished difference Result 1919 states and 2840 transitions. [2022-02-21 04:24:25,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:24:25,552 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,673 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 157 edges. 157 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:25,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1919 states and 2840 transitions. [2022-02-21 04:24:25,776 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:25,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1919 states to 1914 states and 2835 transitions. [2022-02-21 04:24:25,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:25,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:25,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:25,877 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:25,877 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-02-21 04:24:25,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:25,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:25,952 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:25,958 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2835 transitions. Second operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,962 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2835 transitions. Second operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,966 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. Second operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,054 INFO L93 Difference]: Finished difference Result 1914 states and 2835 transitions. [2022-02-21 04:24:26,055 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:26,059 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:26,059 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:26,064 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2835 transitions. [2022-02-21 04:24:26,069 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2835 transitions. [2022-02-21 04:24:26,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,163 INFO L93 Difference]: Finished difference Result 1914 states and 2835 transitions. [2022-02-21 04:24:26,163 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:26,165 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:26,165 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:26,165 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:26,165 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:26,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2022-02-21 04:24:26,257 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-02-21 04:24:26,257 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-02-21 04:24:26,257 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:26,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:26,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:26,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:26,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:26,266 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:26,266 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:26,266 INFO L791 eck$LassoCheckResult]: Stem: 4709#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4710#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4529#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4245#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4246#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5422#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5423#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4381#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4382#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4836#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4671#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4672#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4448#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4449#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4847#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5024#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5178#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5215#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4459#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4460#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5635#L1258-2 assume !(0 == ~T1_E~0); 4754#L1263-1 assume !(0 == ~T2_E~0); 4755#L1268-1 assume !(0 == ~T3_E~0); 5058#L1273-1 assume !(0 == ~T4_E~0); 5617#L1278-1 assume !(0 == ~T5_E~0); 5478#L1283-1 assume !(0 == ~T6_E~0); 5479#L1288-1 assume !(0 == ~T7_E~0); 5715#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5703#L1298-1 assume !(0 == ~T9_E~0); 5629#L1303-1 assume !(0 == ~T10_E~0); 4274#L1308-1 assume !(0 == ~T11_E~0); 4216#L1313-1 assume !(0 == ~T12_E~0); 4217#L1318-1 assume !(0 == ~T13_E~0); 4223#L1323-1 assume !(0 == ~E_1~0); 4224#L1328-1 assume !(0 == ~E_2~0); 4391#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5350#L1338-1 assume !(0 == ~E_4~0); 5351#L1343-1 assume !(0 == ~E_5~0); 5452#L1348-1 assume !(0 == ~E_6~0); 5738#L1353-1 assume !(0 == ~E_7~0); 5077#L1358-1 assume !(0 == ~E_8~0); 5078#L1363-1 assume !(0 == ~E_9~0); 5368#L1368-1 assume !(0 == ~E_10~0); 4053#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4054#L1378-1 assume !(0 == ~E_12~0); 4340#L1383-1 assume !(0 == ~E_13~0); 4341#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5084#L607 assume 1 == ~m_pc~0; 5085#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4411#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5450#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5004#L1560 assume !(0 != activate_threads_~tmp~1#1); 5005#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4236#L626 assume !(1 == ~t1_pc~0); 4237#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4505#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4506#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4675#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4136#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4137#L645 assume 1 == ~t2_pc~0; 4253#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4210#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4887#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4888#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4980#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4981#L664 assume 1 == ~t3_pc~0; 5737#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3977#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3978#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4636#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4637#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5645#L683 assume !(1 == ~t4_pc~0); 5200#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5152#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5153#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5187#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5311#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4930#L702 assume 1 == ~t5_pc~0; 4931#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4856#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5306#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5604#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5545#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4025#L721 assume !(1 == ~t6_pc~0); 3999#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4000#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4163#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4645#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4646#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5247#L740 assume 1 == ~t7_pc~0; 4074#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3887#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3888#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3877#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3878#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4581#L759 assume !(1 == ~t8_pc~0); 4582#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4611#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5304#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5305#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5436#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5714#L778 assume 1 == ~t9_pc~0; 5601#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4052#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3992#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3921#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3922#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4249#L797 assume !(1 == ~t10_pc~0); 4250#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4368#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5502#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4752#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4753#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5042#L816 assume 1 == ~t11_pc~0; 3957#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3958#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4713#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4652#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4653#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5177#L835 assume 1 == ~t12_pc~0; 5055#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4121#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4143#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4284#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4809#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4810#L854 assume !(1 == ~t13_pc~0); 4450#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4451#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4501#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4161#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4162#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5541#L1401 assume !(1 == ~M_E~0); 4640#L1401-2 assume !(1 == ~T1_E~0); 4641#L1406-1 assume !(1 == ~T2_E~0); 5236#L1411-1 assume !(1 == ~T3_E~0); 5237#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4903#L1421-1 assume !(1 == ~T5_E~0); 4446#L1426-1 assume !(1 == ~T6_E~0); 4447#L1431-1 assume !(1 == ~T7_E~0); 3995#L1436-1 assume !(1 == ~T8_E~0); 3996#L1441-1 assume !(1 == ~T9_E~0); 4743#L1446-1 assume !(1 == ~T10_E~0); 4744#L1451-1 assume !(1 == ~T11_E~0); 5449#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5103#L1461-1 assume !(1 == ~T13_E~0); 4664#L1466-1 assume !(1 == ~E_1~0); 4665#L1471-1 assume !(1 == ~E_2~0); 5434#L1476-1 assume !(1 == ~E_3~0); 5435#L1481-1 assume !(1 == ~E_4~0); 5583#L1486-1 assume !(1 == ~E_5~0); 4289#L1491-1 assume !(1 == ~E_6~0); 3929#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3930#L1501-1 assume !(1 == ~E_8~0); 4741#L1506-1 assume !(1 == ~E_9~0); 4742#L1511-1 assume !(1 == ~E_10~0); 4698#L1516-1 assume !(1 == ~E_11~0); 3873#L1521-1 assume !(1 == ~E_12~0); 3874#L1526-1 assume !(1 == ~E_13~0); 3928#L1531-1 assume { :end_inline_reset_delta_events } true; 4471#L1892-2 [2022-02-21 04:24:26,267 INFO L793 eck$LassoCheckResult]: Loop: 4471#L1892-2 assume !false; 5494#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5692#L1233 assume !false; 5675#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5007#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4987#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5145#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3971#L1046 assume !(0 != eval_~tmp~0#1); 3973#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4007#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5179#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5736#L1258-5 assume !(0 == ~T1_E~0); 4149#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4150#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5728#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5734#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5735#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4373#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4374#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5491#L1298-3 assume !(0 == ~T9_E~0); 5492#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5651#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5490#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4991#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4151#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4152#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5575#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4294#L1338-3 assume !(0 == ~E_4~0); 4295#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5407#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5580#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5581#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4947#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4507#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4508#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5264#L1378-3 assume !(0 == ~E_12~0); 5265#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5446#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5447#L607-42 assume 1 == ~m_pc~0; 5060#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4788#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4789#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4521#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4522#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5043#L626-42 assume 1 == ~t1_pc~0; 4605#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4606#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4910#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4911#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4185#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4186#L645-42 assume !(1 == ~t2_pc~0); 5385#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5386#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5551#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4392#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3899#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3900#L664-42 assume !(1 == ~t3_pc~0); 4426#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4427#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5678#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5213#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5214#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5379#L683-42 assume 1 == ~t4_pc~0; 5744#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5088#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5220#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5640#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5641#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5485#L702-42 assume !(1 == ~t5_pc~0); 4597#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4598#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4894#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5567#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 3915#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3916#L721-42 assume 1 == ~t6_pc~0; 4069#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4089#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4553#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5720#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4725#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4571#L740-42 assume !(1 == ~t7_pc~0); 4308#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4309#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4850#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4705#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4706#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4979#L759-42 assume 1 == ~t8_pc~0; 4828#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4760#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4761#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4839#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4840#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4935#L778-42 assume 1 == ~t9_pc~0; 4772#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4774#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5184#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5089#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5090#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5147#L797-42 assume 1 == ~t10_pc~0; 4314#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4315#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5316#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5625#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5185#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5186#L816-42 assume 1 == ~t11_pc~0; 3863#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3864#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4406#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4407#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4486#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4487#L835-42 assume 1 == ~t12_pc~0; 4891#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4784#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4461#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4462#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5544#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5328#L854-42 assume 1 == ~t13_pc~0; 5329#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4405#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4015#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4016#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4662#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4663#L1401-3 assume !(1 == ~M_E~0); 5441#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4252#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4116#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4117#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4716#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4717#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4292#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4293#L1436-3 assume !(1 == ~T8_E~0); 3879#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3880#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5469#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4800#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4453#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4454#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5731#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4393#L1476-3 assume !(1 == ~E_3~0); 4394#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4794#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4421#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4422#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4834#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4835#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5261#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5251#L1516-3 assume !(1 == ~E_11~0); 5252#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4951#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4952#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5346#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4228#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5121#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4762#L1911 assume !(0 == start_simulation_~tmp~3#1); 4763#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5285#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4353#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5223#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4057#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4058#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4287#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4288#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4471#L1892-2 [2022-02-21 04:24:26,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:26,268 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2022-02-21 04:24:26,268 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:26,268 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457971567] [2022-02-21 04:24:26,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:26,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:26,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:26,330 INFO L290 TraceCheckUtils]: 0: Hoare triple {9593#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {9593#true} is VALID [2022-02-21 04:24:26,331 INFO L290 TraceCheckUtils]: 1: Hoare triple {9593#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {9595#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:26,331 INFO L290 TraceCheckUtils]: 2: Hoare triple {9595#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {9595#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:26,331 INFO L290 TraceCheckUtils]: 3: Hoare triple {9595#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {9595#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:26,332 INFO L290 TraceCheckUtils]: 4: Hoare triple {9595#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,332 INFO L290 TraceCheckUtils]: 5: Hoare triple {9594#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {9594#false} is VALID [2022-02-21 04:24:26,332 INFO L290 TraceCheckUtils]: 6: Hoare triple {9594#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,332 INFO L290 TraceCheckUtils]: 7: Hoare triple {9594#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,333 INFO L290 TraceCheckUtils]: 8: Hoare triple {9594#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,333 INFO L290 TraceCheckUtils]: 9: Hoare triple {9594#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,333 INFO L290 TraceCheckUtils]: 10: Hoare triple {9594#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,333 INFO L290 TraceCheckUtils]: 11: Hoare triple {9594#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,333 INFO L290 TraceCheckUtils]: 12: Hoare triple {9594#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,334 INFO L290 TraceCheckUtils]: 13: Hoare triple {9594#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {9594#false} is VALID [2022-02-21 04:24:26,334 INFO L290 TraceCheckUtils]: 14: Hoare triple {9594#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,334 INFO L290 TraceCheckUtils]: 15: Hoare triple {9594#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,334 INFO L290 TraceCheckUtils]: 16: Hoare triple {9594#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,334 INFO L290 TraceCheckUtils]: 17: Hoare triple {9594#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,334 INFO L290 TraceCheckUtils]: 18: Hoare triple {9594#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {9594#false} is VALID [2022-02-21 04:24:26,335 INFO L290 TraceCheckUtils]: 19: Hoare triple {9594#false} assume 0 == ~M_E~0;~M_E~0 := 1; {9594#false} is VALID [2022-02-21 04:24:26,335 INFO L290 TraceCheckUtils]: 20: Hoare triple {9594#false} assume !(0 == ~T1_E~0); {9594#false} is VALID [2022-02-21 04:24:26,335 INFO L290 TraceCheckUtils]: 21: Hoare triple {9594#false} assume !(0 == ~T2_E~0); {9594#false} is VALID [2022-02-21 04:24:26,335 INFO L290 TraceCheckUtils]: 22: Hoare triple {9594#false} assume !(0 == ~T3_E~0); {9594#false} is VALID [2022-02-21 04:24:26,335 INFO L290 TraceCheckUtils]: 23: Hoare triple {9594#false} assume !(0 == ~T4_E~0); {9594#false} is VALID [2022-02-21 04:24:26,336 INFO L290 TraceCheckUtils]: 24: Hoare triple {9594#false} assume !(0 == ~T5_E~0); {9594#false} is VALID [2022-02-21 04:24:26,336 INFO L290 TraceCheckUtils]: 25: Hoare triple {9594#false} assume !(0 == ~T6_E~0); {9594#false} is VALID [2022-02-21 04:24:26,336 INFO L290 TraceCheckUtils]: 26: Hoare triple {9594#false} assume !(0 == ~T7_E~0); {9594#false} is VALID [2022-02-21 04:24:26,336 INFO L290 TraceCheckUtils]: 27: Hoare triple {9594#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {9594#false} is VALID [2022-02-21 04:24:26,336 INFO L290 TraceCheckUtils]: 28: Hoare triple {9594#false} assume !(0 == ~T9_E~0); {9594#false} is VALID [2022-02-21 04:24:26,336 INFO L290 TraceCheckUtils]: 29: Hoare triple {9594#false} assume !(0 == ~T10_E~0); {9594#false} is VALID [2022-02-21 04:24:26,337 INFO L290 TraceCheckUtils]: 30: Hoare triple {9594#false} assume !(0 == ~T11_E~0); {9594#false} is VALID [2022-02-21 04:24:26,337 INFO L290 TraceCheckUtils]: 31: Hoare triple {9594#false} assume !(0 == ~T12_E~0); {9594#false} is VALID [2022-02-21 04:24:26,337 INFO L290 TraceCheckUtils]: 32: Hoare triple {9594#false} assume !(0 == ~T13_E~0); {9594#false} is VALID [2022-02-21 04:24:26,337 INFO L290 TraceCheckUtils]: 33: Hoare triple {9594#false} assume !(0 == ~E_1~0); {9594#false} is VALID [2022-02-21 04:24:26,337 INFO L290 TraceCheckUtils]: 34: Hoare triple {9594#false} assume !(0 == ~E_2~0); {9594#false} is VALID [2022-02-21 04:24:26,338 INFO L290 TraceCheckUtils]: 35: Hoare triple {9594#false} assume 0 == ~E_3~0;~E_3~0 := 1; {9594#false} is VALID [2022-02-21 04:24:26,338 INFO L290 TraceCheckUtils]: 36: Hoare triple {9594#false} assume !(0 == ~E_4~0); {9594#false} is VALID [2022-02-21 04:24:26,338 INFO L290 TraceCheckUtils]: 37: Hoare triple {9594#false} assume !(0 == ~E_5~0); {9594#false} is VALID [2022-02-21 04:24:26,338 INFO L290 TraceCheckUtils]: 38: Hoare triple {9594#false} assume !(0 == ~E_6~0); {9594#false} is VALID [2022-02-21 04:24:26,338 INFO L290 TraceCheckUtils]: 39: Hoare triple {9594#false} assume !(0 == ~E_7~0); {9594#false} is VALID [2022-02-21 04:24:26,339 INFO L290 TraceCheckUtils]: 40: Hoare triple {9594#false} assume !(0 == ~E_8~0); {9594#false} is VALID [2022-02-21 04:24:26,339 INFO L290 TraceCheckUtils]: 41: Hoare triple {9594#false} assume !(0 == ~E_9~0); {9594#false} is VALID [2022-02-21 04:24:26,339 INFO L290 TraceCheckUtils]: 42: Hoare triple {9594#false} assume !(0 == ~E_10~0); {9594#false} is VALID [2022-02-21 04:24:26,339 INFO L290 TraceCheckUtils]: 43: Hoare triple {9594#false} assume 0 == ~E_11~0;~E_11~0 := 1; {9594#false} is VALID [2022-02-21 04:24:26,339 INFO L290 TraceCheckUtils]: 44: Hoare triple {9594#false} assume !(0 == ~E_12~0); {9594#false} is VALID [2022-02-21 04:24:26,339 INFO L290 TraceCheckUtils]: 45: Hoare triple {9594#false} assume !(0 == ~E_13~0); {9594#false} is VALID [2022-02-21 04:24:26,340 INFO L290 TraceCheckUtils]: 46: Hoare triple {9594#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9594#false} is VALID [2022-02-21 04:24:26,340 INFO L290 TraceCheckUtils]: 47: Hoare triple {9594#false} assume 1 == ~m_pc~0; {9594#false} is VALID [2022-02-21 04:24:26,340 INFO L290 TraceCheckUtils]: 48: Hoare triple {9594#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {9594#false} is VALID [2022-02-21 04:24:26,340 INFO L290 TraceCheckUtils]: 49: Hoare triple {9594#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9594#false} is VALID [2022-02-21 04:24:26,340 INFO L290 TraceCheckUtils]: 50: Hoare triple {9594#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {9594#false} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 51: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp~1#1); {9594#false} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 52: Hoare triple {9594#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9594#false} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 53: Hoare triple {9594#false} assume !(1 == ~t1_pc~0); {9594#false} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 54: Hoare triple {9594#false} is_transmit1_triggered_~__retres1~1#1 := 0; {9594#false} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 55: Hoare triple {9594#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9594#false} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 56: Hoare triple {9594#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {9594#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 57: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___0~0#1); {9594#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 58: Hoare triple {9594#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {9594#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 59: Hoare triple {9594#false} assume 1 == ~t2_pc~0; {9594#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 60: Hoare triple {9594#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {9594#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 61: Hoare triple {9594#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {9594#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 62: Hoare triple {9594#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {9594#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 63: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___1~0#1); {9594#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 64: Hoare triple {9594#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {9594#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 65: Hoare triple {9594#false} assume 1 == ~t3_pc~0; {9594#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 66: Hoare triple {9594#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {9594#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 67: Hoare triple {9594#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {9594#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 68: Hoare triple {9594#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {9594#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 69: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___2~0#1); {9594#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 70: Hoare triple {9594#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {9594#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 71: Hoare triple {9594#false} assume !(1 == ~t4_pc~0); {9594#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 72: Hoare triple {9594#false} is_transmit4_triggered_~__retres1~4#1 := 0; {9594#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 73: Hoare triple {9594#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {9594#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 74: Hoare triple {9594#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {9594#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 75: Hoare triple {9594#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {9594#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 76: Hoare triple {9594#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {9594#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 77: Hoare triple {9594#false} assume 1 == ~t5_pc~0; {9594#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 78: Hoare triple {9594#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {9594#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 79: Hoare triple {9594#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {9594#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 80: Hoare triple {9594#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {9594#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 81: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___4~0#1); {9594#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 82: Hoare triple {9594#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {9594#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 83: Hoare triple {9594#false} assume !(1 == ~t6_pc~0); {9594#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 84: Hoare triple {9594#false} is_transmit6_triggered_~__retres1~6#1 := 0; {9594#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 85: Hoare triple {9594#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {9594#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 86: Hoare triple {9594#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {9594#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 87: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___5~0#1); {9594#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 88: Hoare triple {9594#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {9594#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 89: Hoare triple {9594#false} assume 1 == ~t7_pc~0; {9594#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 90: Hoare triple {9594#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {9594#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 91: Hoare triple {9594#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {9594#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 92: Hoare triple {9594#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {9594#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 93: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___6~0#1); {9594#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 94: Hoare triple {9594#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {9594#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 95: Hoare triple {9594#false} assume !(1 == ~t8_pc~0); {9594#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 96: Hoare triple {9594#false} is_transmit8_triggered_~__retres1~8#1 := 0; {9594#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 97: Hoare triple {9594#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {9594#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 98: Hoare triple {9594#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {9594#false} is VALID [2022-02-21 04:24:26,349 INFO L290 TraceCheckUtils]: 99: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___7~0#1); {9594#false} is VALID [2022-02-21 04:24:26,349 INFO L290 TraceCheckUtils]: 100: Hoare triple {9594#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {9594#false} is VALID [2022-02-21 04:24:26,349 INFO L290 TraceCheckUtils]: 101: Hoare triple {9594#false} assume 1 == ~t9_pc~0; {9594#false} is VALID [2022-02-21 04:24:26,349 INFO L290 TraceCheckUtils]: 102: Hoare triple {9594#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {9594#false} is VALID [2022-02-21 04:24:26,349 INFO L290 TraceCheckUtils]: 103: Hoare triple {9594#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {9594#false} is VALID [2022-02-21 04:24:26,349 INFO L290 TraceCheckUtils]: 104: Hoare triple {9594#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {9594#false} is VALID [2022-02-21 04:24:26,349 INFO L290 TraceCheckUtils]: 105: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___8~0#1); {9594#false} is VALID [2022-02-21 04:24:26,350 INFO L290 TraceCheckUtils]: 106: Hoare triple {9594#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {9594#false} is VALID [2022-02-21 04:24:26,350 INFO L290 TraceCheckUtils]: 107: Hoare triple {9594#false} assume !(1 == ~t10_pc~0); {9594#false} is VALID [2022-02-21 04:24:26,350 INFO L290 TraceCheckUtils]: 108: Hoare triple {9594#false} is_transmit10_triggered_~__retres1~10#1 := 0; {9594#false} is VALID [2022-02-21 04:24:26,350 INFO L290 TraceCheckUtils]: 109: Hoare triple {9594#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {9594#false} is VALID [2022-02-21 04:24:26,350 INFO L290 TraceCheckUtils]: 110: Hoare triple {9594#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {9594#false} is VALID [2022-02-21 04:24:26,350 INFO L290 TraceCheckUtils]: 111: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___9~0#1); {9594#false} is VALID [2022-02-21 04:24:26,351 INFO L290 TraceCheckUtils]: 112: Hoare triple {9594#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {9594#false} is VALID [2022-02-21 04:24:26,351 INFO L290 TraceCheckUtils]: 113: Hoare triple {9594#false} assume 1 == ~t11_pc~0; {9594#false} is VALID [2022-02-21 04:24:26,351 INFO L290 TraceCheckUtils]: 114: Hoare triple {9594#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {9594#false} is VALID [2022-02-21 04:24:26,351 INFO L290 TraceCheckUtils]: 115: Hoare triple {9594#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {9594#false} is VALID [2022-02-21 04:24:26,351 INFO L290 TraceCheckUtils]: 116: Hoare triple {9594#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {9594#false} is VALID [2022-02-21 04:24:26,351 INFO L290 TraceCheckUtils]: 117: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___10~0#1); {9594#false} is VALID [2022-02-21 04:24:26,351 INFO L290 TraceCheckUtils]: 118: Hoare triple {9594#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {9594#false} is VALID [2022-02-21 04:24:26,352 INFO L290 TraceCheckUtils]: 119: Hoare triple {9594#false} assume 1 == ~t12_pc~0; {9594#false} is VALID [2022-02-21 04:24:26,352 INFO L290 TraceCheckUtils]: 120: Hoare triple {9594#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {9594#false} is VALID [2022-02-21 04:24:26,352 INFO L290 TraceCheckUtils]: 121: Hoare triple {9594#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {9594#false} is VALID [2022-02-21 04:24:26,352 INFO L290 TraceCheckUtils]: 122: Hoare triple {9594#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {9594#false} is VALID [2022-02-21 04:24:26,352 INFO L290 TraceCheckUtils]: 123: Hoare triple {9594#false} assume !(0 != activate_threads_~tmp___11~0#1); {9594#false} is VALID [2022-02-21 04:24:26,352 INFO L290 TraceCheckUtils]: 124: Hoare triple {9594#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {9594#false} is VALID [2022-02-21 04:24:26,352 INFO L290 TraceCheckUtils]: 125: Hoare triple {9594#false} assume !(1 == ~t13_pc~0); {9594#false} is VALID [2022-02-21 04:24:26,353 INFO L290 TraceCheckUtils]: 126: Hoare triple {9594#false} is_transmit13_triggered_~__retres1~13#1 := 0; {9594#false} is VALID [2022-02-21 04:24:26,353 INFO L290 TraceCheckUtils]: 127: Hoare triple {9594#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {9594#false} is VALID [2022-02-21 04:24:26,353 INFO L290 TraceCheckUtils]: 128: Hoare triple {9594#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {9594#false} is VALID [2022-02-21 04:24:26,353 INFO L290 TraceCheckUtils]: 129: Hoare triple {9594#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {9594#false} is VALID [2022-02-21 04:24:26,353 INFO L290 TraceCheckUtils]: 130: Hoare triple {9594#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9594#false} is VALID [2022-02-21 04:24:26,353 INFO L290 TraceCheckUtils]: 131: Hoare triple {9594#false} assume !(1 == ~M_E~0); {9594#false} is VALID [2022-02-21 04:24:26,353 INFO L290 TraceCheckUtils]: 132: Hoare triple {9594#false} assume !(1 == ~T1_E~0); {9594#false} is VALID [2022-02-21 04:24:26,354 INFO L290 TraceCheckUtils]: 133: Hoare triple {9594#false} assume !(1 == ~T2_E~0); {9594#false} is VALID [2022-02-21 04:24:26,354 INFO L290 TraceCheckUtils]: 134: Hoare triple {9594#false} assume !(1 == ~T3_E~0); {9594#false} is VALID [2022-02-21 04:24:26,354 INFO L290 TraceCheckUtils]: 135: Hoare triple {9594#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,354 INFO L290 TraceCheckUtils]: 136: Hoare triple {9594#false} assume !(1 == ~T5_E~0); {9594#false} is VALID [2022-02-21 04:24:26,354 INFO L290 TraceCheckUtils]: 137: Hoare triple {9594#false} assume !(1 == ~T6_E~0); {9594#false} is VALID [2022-02-21 04:24:26,354 INFO L290 TraceCheckUtils]: 138: Hoare triple {9594#false} assume !(1 == ~T7_E~0); {9594#false} is VALID [2022-02-21 04:24:26,354 INFO L290 TraceCheckUtils]: 139: Hoare triple {9594#false} assume !(1 == ~T8_E~0); {9594#false} is VALID [2022-02-21 04:24:26,355 INFO L290 TraceCheckUtils]: 140: Hoare triple {9594#false} assume !(1 == ~T9_E~0); {9594#false} is VALID [2022-02-21 04:24:26,355 INFO L290 TraceCheckUtils]: 141: Hoare triple {9594#false} assume !(1 == ~T10_E~0); {9594#false} is VALID [2022-02-21 04:24:26,355 INFO L290 TraceCheckUtils]: 142: Hoare triple {9594#false} assume !(1 == ~T11_E~0); {9594#false} is VALID [2022-02-21 04:24:26,355 INFO L290 TraceCheckUtils]: 143: Hoare triple {9594#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,355 INFO L290 TraceCheckUtils]: 144: Hoare triple {9594#false} assume !(1 == ~T13_E~0); {9594#false} is VALID [2022-02-21 04:24:26,355 INFO L290 TraceCheckUtils]: 145: Hoare triple {9594#false} assume !(1 == ~E_1~0); {9594#false} is VALID [2022-02-21 04:24:26,355 INFO L290 TraceCheckUtils]: 146: Hoare triple {9594#false} assume !(1 == ~E_2~0); {9594#false} is VALID [2022-02-21 04:24:26,356 INFO L290 TraceCheckUtils]: 147: Hoare triple {9594#false} assume !(1 == ~E_3~0); {9594#false} is VALID [2022-02-21 04:24:26,356 INFO L290 TraceCheckUtils]: 148: Hoare triple {9594#false} assume !(1 == ~E_4~0); {9594#false} is VALID [2022-02-21 04:24:26,356 INFO L290 TraceCheckUtils]: 149: Hoare triple {9594#false} assume !(1 == ~E_5~0); {9594#false} is VALID [2022-02-21 04:24:26,356 INFO L290 TraceCheckUtils]: 150: Hoare triple {9594#false} assume !(1 == ~E_6~0); {9594#false} is VALID [2022-02-21 04:24:26,356 INFO L290 TraceCheckUtils]: 151: Hoare triple {9594#false} assume 1 == ~E_7~0;~E_7~0 := 2; {9594#false} is VALID [2022-02-21 04:24:26,356 INFO L290 TraceCheckUtils]: 152: Hoare triple {9594#false} assume !(1 == ~E_8~0); {9594#false} is VALID [2022-02-21 04:24:26,356 INFO L290 TraceCheckUtils]: 153: Hoare triple {9594#false} assume !(1 == ~E_9~0); {9594#false} is VALID [2022-02-21 04:24:26,357 INFO L290 TraceCheckUtils]: 154: Hoare triple {9594#false} assume !(1 == ~E_10~0); {9594#false} is VALID [2022-02-21 04:24:26,357 INFO L290 TraceCheckUtils]: 155: Hoare triple {9594#false} assume !(1 == ~E_11~0); {9594#false} is VALID [2022-02-21 04:24:26,357 INFO L290 TraceCheckUtils]: 156: Hoare triple {9594#false} assume !(1 == ~E_12~0); {9594#false} is VALID [2022-02-21 04:24:26,357 INFO L290 TraceCheckUtils]: 157: Hoare triple {9594#false} assume !(1 == ~E_13~0); {9594#false} is VALID [2022-02-21 04:24:26,357 INFO L290 TraceCheckUtils]: 158: Hoare triple {9594#false} assume { :end_inline_reset_delta_events } true; {9594#false} is VALID [2022-02-21 04:24:26,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:26,358 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:26,358 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457971567] [2022-02-21 04:24:26,358 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1457971567] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:26,358 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:26,359 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:26,359 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1688041944] [2022-02-21 04:24:26,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:26,359 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:26,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:26,360 INFO L85 PathProgramCache]: Analyzing trace with hash 1475252753, now seen corresponding path program 1 times [2022-02-21 04:24:26,360 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:26,360 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744853099] [2022-02-21 04:24:26,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:26,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:26,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:26,432 INFO L290 TraceCheckUtils]: 0: Hoare triple {9596#true} assume !false; {9596#true} is VALID [2022-02-21 04:24:26,433 INFO L290 TraceCheckUtils]: 1: Hoare triple {9596#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {9596#true} is VALID [2022-02-21 04:24:26,433 INFO L290 TraceCheckUtils]: 2: Hoare triple {9596#true} assume !false; {9596#true} is VALID [2022-02-21 04:24:26,433 INFO L290 TraceCheckUtils]: 3: Hoare triple {9596#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {9596#true} is VALID [2022-02-21 04:24:26,433 INFO L290 TraceCheckUtils]: 4: Hoare triple {9596#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {9596#true} is VALID [2022-02-21 04:24:26,433 INFO L290 TraceCheckUtils]: 5: Hoare triple {9596#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {9596#true} is VALID [2022-02-21 04:24:26,433 INFO L290 TraceCheckUtils]: 6: Hoare triple {9596#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {9596#true} is VALID [2022-02-21 04:24:26,434 INFO L290 TraceCheckUtils]: 7: Hoare triple {9596#true} assume !(0 != eval_~tmp~0#1); {9596#true} is VALID [2022-02-21 04:24:26,434 INFO L290 TraceCheckUtils]: 8: Hoare triple {9596#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {9596#true} is VALID [2022-02-21 04:24:26,434 INFO L290 TraceCheckUtils]: 9: Hoare triple {9596#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {9596#true} is VALID [2022-02-21 04:24:26,434 INFO L290 TraceCheckUtils]: 10: Hoare triple {9596#true} assume 0 == ~M_E~0;~M_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,435 INFO L290 TraceCheckUtils]: 11: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,435 INFO L290 TraceCheckUtils]: 12: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,435 INFO L290 TraceCheckUtils]: 13: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,436 INFO L290 TraceCheckUtils]: 14: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,436 INFO L290 TraceCheckUtils]: 15: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,436 INFO L290 TraceCheckUtils]: 16: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,437 INFO L290 TraceCheckUtils]: 17: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,437 INFO L290 TraceCheckUtils]: 18: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,438 INFO L290 TraceCheckUtils]: 19: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,438 INFO L290 TraceCheckUtils]: 20: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,438 INFO L290 TraceCheckUtils]: 21: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,439 INFO L290 TraceCheckUtils]: 22: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,439 INFO L290 TraceCheckUtils]: 23: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,439 INFO L290 TraceCheckUtils]: 24: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,440 INFO L290 TraceCheckUtils]: 25: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,440 INFO L290 TraceCheckUtils]: 26: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,440 INFO L290 TraceCheckUtils]: 27: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,441 INFO L290 TraceCheckUtils]: 28: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,441 INFO L290 TraceCheckUtils]: 29: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,441 INFO L290 TraceCheckUtils]: 30: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,442 INFO L290 TraceCheckUtils]: 31: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,442 INFO L290 TraceCheckUtils]: 32: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,442 INFO L290 TraceCheckUtils]: 33: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,443 INFO L290 TraceCheckUtils]: 34: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,443 INFO L290 TraceCheckUtils]: 35: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,444 INFO L290 TraceCheckUtils]: 36: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,444 INFO L290 TraceCheckUtils]: 37: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,444 INFO L290 TraceCheckUtils]: 38: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,445 INFO L290 TraceCheckUtils]: 39: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,445 INFO L290 TraceCheckUtils]: 40: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,445 INFO L290 TraceCheckUtils]: 41: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,446 INFO L290 TraceCheckUtils]: 42: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,446 INFO L290 TraceCheckUtils]: 43: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,446 INFO L290 TraceCheckUtils]: 44: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,447 INFO L290 TraceCheckUtils]: 45: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,447 INFO L290 TraceCheckUtils]: 46: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,447 INFO L290 TraceCheckUtils]: 47: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,448 INFO L290 TraceCheckUtils]: 48: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,448 INFO L290 TraceCheckUtils]: 49: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,448 INFO L290 TraceCheckUtils]: 50: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,449 INFO L290 TraceCheckUtils]: 51: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,449 INFO L290 TraceCheckUtils]: 52: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,449 INFO L290 TraceCheckUtils]: 53: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,450 INFO L290 TraceCheckUtils]: 54: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,450 INFO L290 TraceCheckUtils]: 55: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,450 INFO L290 TraceCheckUtils]: 56: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,451 INFO L290 TraceCheckUtils]: 57: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,451 INFO L290 TraceCheckUtils]: 58: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,452 INFO L290 TraceCheckUtils]: 59: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,452 INFO L290 TraceCheckUtils]: 60: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,452 INFO L290 TraceCheckUtils]: 61: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,453 INFO L290 TraceCheckUtils]: 62: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,453 INFO L290 TraceCheckUtils]: 63: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,453 INFO L290 TraceCheckUtils]: 64: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,454 INFO L290 TraceCheckUtils]: 65: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,454 INFO L290 TraceCheckUtils]: 66: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,454 INFO L290 TraceCheckUtils]: 67: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,455 INFO L290 TraceCheckUtils]: 68: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,455 INFO L290 TraceCheckUtils]: 69: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,455 INFO L290 TraceCheckUtils]: 70: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,456 INFO L290 TraceCheckUtils]: 71: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,456 INFO L290 TraceCheckUtils]: 72: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,457 INFO L290 TraceCheckUtils]: 73: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,457 INFO L290 TraceCheckUtils]: 74: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,457 INFO L290 TraceCheckUtils]: 75: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,458 INFO L290 TraceCheckUtils]: 76: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,458 INFO L290 TraceCheckUtils]: 77: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,458 INFO L290 TraceCheckUtils]: 78: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,459 INFO L290 TraceCheckUtils]: 79: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,459 INFO L290 TraceCheckUtils]: 80: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,459 INFO L290 TraceCheckUtils]: 81: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,460 INFO L290 TraceCheckUtils]: 82: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,460 INFO L290 TraceCheckUtils]: 83: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,460 INFO L290 TraceCheckUtils]: 84: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,461 INFO L290 TraceCheckUtils]: 85: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,461 INFO L290 TraceCheckUtils]: 86: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,461 INFO L290 TraceCheckUtils]: 87: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,462 INFO L290 TraceCheckUtils]: 88: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,462 INFO L290 TraceCheckUtils]: 89: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,462 INFO L290 TraceCheckUtils]: 90: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,463 INFO L290 TraceCheckUtils]: 91: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,463 INFO L290 TraceCheckUtils]: 92: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,463 INFO L290 TraceCheckUtils]: 93: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,464 INFO L290 TraceCheckUtils]: 94: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,464 INFO L290 TraceCheckUtils]: 95: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,464 INFO L290 TraceCheckUtils]: 96: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,465 INFO L290 TraceCheckUtils]: 97: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,465 INFO L290 TraceCheckUtils]: 98: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,465 INFO L290 TraceCheckUtils]: 99: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,466 INFO L290 TraceCheckUtils]: 100: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,466 INFO L290 TraceCheckUtils]: 101: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,467 INFO L290 TraceCheckUtils]: 102: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,467 INFO L290 TraceCheckUtils]: 103: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,467 INFO L290 TraceCheckUtils]: 104: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,468 INFO L290 TraceCheckUtils]: 105: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,468 INFO L290 TraceCheckUtils]: 106: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,468 INFO L290 TraceCheckUtils]: 107: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,469 INFO L290 TraceCheckUtils]: 108: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,469 INFO L290 TraceCheckUtils]: 109: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,469 INFO L290 TraceCheckUtils]: 110: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,470 INFO L290 TraceCheckUtils]: 111: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,470 INFO L290 TraceCheckUtils]: 112: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,470 INFO L290 TraceCheckUtils]: 113: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,471 INFO L290 TraceCheckUtils]: 114: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,471 INFO L290 TraceCheckUtils]: 115: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,471 INFO L290 TraceCheckUtils]: 116: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,472 INFO L290 TraceCheckUtils]: 117: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,472 INFO L290 TraceCheckUtils]: 118: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,472 INFO L290 TraceCheckUtils]: 119: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,473 INFO L290 TraceCheckUtils]: 120: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,473 INFO L290 TraceCheckUtils]: 121: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9598#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:26,474 INFO L290 TraceCheckUtils]: 122: Hoare triple {9598#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {9597#false} is VALID [2022-02-21 04:24:26,474 INFO L290 TraceCheckUtils]: 123: Hoare triple {9597#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,474 INFO L290 TraceCheckUtils]: 124: Hoare triple {9597#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,474 INFO L290 TraceCheckUtils]: 125: Hoare triple {9597#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,474 INFO L290 TraceCheckUtils]: 126: Hoare triple {9597#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,474 INFO L290 TraceCheckUtils]: 127: Hoare triple {9597#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,475 INFO L290 TraceCheckUtils]: 128: Hoare triple {9597#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,475 INFO L290 TraceCheckUtils]: 129: Hoare triple {9597#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,475 INFO L290 TraceCheckUtils]: 130: Hoare triple {9597#false} assume !(1 == ~T8_E~0); {9597#false} is VALID [2022-02-21 04:24:26,475 INFO L290 TraceCheckUtils]: 131: Hoare triple {9597#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,475 INFO L290 TraceCheckUtils]: 132: Hoare triple {9597#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,475 INFO L290 TraceCheckUtils]: 133: Hoare triple {9597#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,475 INFO L290 TraceCheckUtils]: 134: Hoare triple {9597#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,476 INFO L290 TraceCheckUtils]: 135: Hoare triple {9597#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,476 INFO L290 TraceCheckUtils]: 136: Hoare triple {9597#false} assume 1 == ~E_1~0;~E_1~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,476 INFO L290 TraceCheckUtils]: 137: Hoare triple {9597#false} assume 1 == ~E_2~0;~E_2~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,476 INFO L290 TraceCheckUtils]: 138: Hoare triple {9597#false} assume !(1 == ~E_3~0); {9597#false} is VALID [2022-02-21 04:24:26,476 INFO L290 TraceCheckUtils]: 139: Hoare triple {9597#false} assume 1 == ~E_4~0;~E_4~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,476 INFO L290 TraceCheckUtils]: 140: Hoare triple {9597#false} assume 1 == ~E_5~0;~E_5~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,477 INFO L290 TraceCheckUtils]: 141: Hoare triple {9597#false} assume 1 == ~E_6~0;~E_6~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,477 INFO L290 TraceCheckUtils]: 142: Hoare triple {9597#false} assume 1 == ~E_7~0;~E_7~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,477 INFO L290 TraceCheckUtils]: 143: Hoare triple {9597#false} assume 1 == ~E_8~0;~E_8~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,477 INFO L290 TraceCheckUtils]: 144: Hoare triple {9597#false} assume 1 == ~E_9~0;~E_9~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,477 INFO L290 TraceCheckUtils]: 145: Hoare triple {9597#false} assume 1 == ~E_10~0;~E_10~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,477 INFO L290 TraceCheckUtils]: 146: Hoare triple {9597#false} assume !(1 == ~E_11~0); {9597#false} is VALID [2022-02-21 04:24:26,477 INFO L290 TraceCheckUtils]: 147: Hoare triple {9597#false} assume 1 == ~E_12~0;~E_12~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,478 INFO L290 TraceCheckUtils]: 148: Hoare triple {9597#false} assume 1 == ~E_13~0;~E_13~0 := 2; {9597#false} is VALID [2022-02-21 04:24:26,478 INFO L290 TraceCheckUtils]: 149: Hoare triple {9597#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {9597#false} is VALID [2022-02-21 04:24:26,478 INFO L290 TraceCheckUtils]: 150: Hoare triple {9597#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {9597#false} is VALID [2022-02-21 04:24:26,478 INFO L290 TraceCheckUtils]: 151: Hoare triple {9597#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {9597#false} is VALID [2022-02-21 04:24:26,478 INFO L290 TraceCheckUtils]: 152: Hoare triple {9597#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {9597#false} is VALID [2022-02-21 04:24:26,478 INFO L290 TraceCheckUtils]: 153: Hoare triple {9597#false} assume !(0 == start_simulation_~tmp~3#1); {9597#false} is VALID [2022-02-21 04:24:26,479 INFO L290 TraceCheckUtils]: 154: Hoare triple {9597#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {9597#false} is VALID [2022-02-21 04:24:26,479 INFO L290 TraceCheckUtils]: 155: Hoare triple {9597#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {9597#false} is VALID [2022-02-21 04:24:26,479 INFO L290 TraceCheckUtils]: 156: Hoare triple {9597#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {9597#false} is VALID [2022-02-21 04:24:26,479 INFO L290 TraceCheckUtils]: 157: Hoare triple {9597#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {9597#false} is VALID [2022-02-21 04:24:26,479 INFO L290 TraceCheckUtils]: 158: Hoare triple {9597#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {9597#false} is VALID [2022-02-21 04:24:26,479 INFO L290 TraceCheckUtils]: 159: Hoare triple {9597#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {9597#false} is VALID [2022-02-21 04:24:26,479 INFO L290 TraceCheckUtils]: 160: Hoare triple {9597#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {9597#false} is VALID [2022-02-21 04:24:26,480 INFO L290 TraceCheckUtils]: 161: Hoare triple {9597#false} assume !(0 != start_simulation_~tmp___0~1#1); {9597#false} is VALID [2022-02-21 04:24:26,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:26,481 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:26,481 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744853099] [2022-02-21 04:24:26,481 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744853099] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:26,481 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:26,481 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:26,481 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1970498054] [2022-02-21 04:24:26,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:26,482 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:26,482 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:26,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:26,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:26,483 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,285 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-02-21 04:24:28,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:28,285 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,388 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:28,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:28,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-02-21 04:24:28,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:28,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:28,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:28,633 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-02-21 04:24:28,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:28,668 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:28,672 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2834 transitions. Second operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,674 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2834 transitions. Second operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,677 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. Second operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,773 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-02-21 04:24:28,773 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,775 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:28,776 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:28,791 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,795 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,900 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-02-21 04:24:28,900 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,903 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:28,903 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:28,903 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:28,903 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:28,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-02-21 04:24:28,993 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-02-21 04:24:28,993 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-02-21 04:24:28,993 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:28,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:28,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:28,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:29,001 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:29,001 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:29,001 INFO L791 eck$LassoCheckResult]: Stem: 12374#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12375#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12194#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11910#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11911#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13087#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13088#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 12046#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12047#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12501#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12336#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12337#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12113#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12114#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12512#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12689#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12843#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12880#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12124#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12125#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13300#L1258-2 assume !(0 == ~T1_E~0); 12419#L1263-1 assume !(0 == ~T2_E~0); 12420#L1268-1 assume !(0 == ~T3_E~0); 12723#L1273-1 assume !(0 == ~T4_E~0); 13282#L1278-1 assume !(0 == ~T5_E~0); 13143#L1283-1 assume !(0 == ~T6_E~0); 13144#L1288-1 assume !(0 == ~T7_E~0); 13380#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13368#L1298-1 assume !(0 == ~T9_E~0); 13294#L1303-1 assume !(0 == ~T10_E~0); 11939#L1308-1 assume !(0 == ~T11_E~0); 11881#L1313-1 assume !(0 == ~T12_E~0); 11882#L1318-1 assume !(0 == ~T13_E~0); 11888#L1323-1 assume !(0 == ~E_1~0); 11889#L1328-1 assume !(0 == ~E_2~0); 12056#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13015#L1338-1 assume !(0 == ~E_4~0); 13016#L1343-1 assume !(0 == ~E_5~0); 13117#L1348-1 assume !(0 == ~E_6~0); 13403#L1353-1 assume !(0 == ~E_7~0); 12742#L1358-1 assume !(0 == ~E_8~0); 12743#L1363-1 assume !(0 == ~E_9~0); 13033#L1368-1 assume !(0 == ~E_10~0); 11718#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11719#L1378-1 assume !(0 == ~E_12~0); 12005#L1383-1 assume !(0 == ~E_13~0); 12006#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12749#L607 assume 1 == ~m_pc~0; 12750#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12076#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13115#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12669#L1560 assume !(0 != activate_threads_~tmp~1#1); 12670#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11901#L626 assume !(1 == ~t1_pc~0); 11902#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12170#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12171#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12340#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11801#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11802#L645 assume 1 == ~t2_pc~0; 11918#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11875#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12552#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12553#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12645#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12646#L664 assume 1 == ~t3_pc~0; 13402#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11642#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11643#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12301#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12302#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13310#L683 assume !(1 == ~t4_pc~0); 12865#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12817#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12818#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12852#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12976#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12595#L702 assume 1 == ~t5_pc~0; 12596#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12521#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12971#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13269#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13210#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11690#L721 assume !(1 == ~t6_pc~0); 11664#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11665#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11828#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12310#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12311#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12912#L740 assume 1 == ~t7_pc~0; 11739#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11552#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11553#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11542#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11543#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12246#L759 assume !(1 == ~t8_pc~0); 12247#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12276#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12969#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12970#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13101#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13379#L778 assume 1 == ~t9_pc~0; 13266#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11717#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11657#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11586#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11587#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11914#L797 assume !(1 == ~t10_pc~0); 11915#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12033#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13167#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12417#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12418#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12707#L816 assume 1 == ~t11_pc~0; 11622#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11623#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12378#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12317#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12318#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12842#L835 assume 1 == ~t12_pc~0; 12720#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11786#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11808#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11949#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12474#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12475#L854 assume !(1 == ~t13_pc~0); 12115#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12116#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12166#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11826#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11827#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13206#L1401 assume !(1 == ~M_E~0); 12305#L1401-2 assume !(1 == ~T1_E~0); 12306#L1406-1 assume !(1 == ~T2_E~0); 12901#L1411-1 assume !(1 == ~T3_E~0); 12902#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12568#L1421-1 assume !(1 == ~T5_E~0); 12111#L1426-1 assume !(1 == ~T6_E~0); 12112#L1431-1 assume !(1 == ~T7_E~0); 11660#L1436-1 assume !(1 == ~T8_E~0); 11661#L1441-1 assume !(1 == ~T9_E~0); 12408#L1446-1 assume !(1 == ~T10_E~0); 12409#L1451-1 assume !(1 == ~T11_E~0); 13114#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12768#L1461-1 assume !(1 == ~T13_E~0); 12329#L1466-1 assume !(1 == ~E_1~0); 12330#L1471-1 assume !(1 == ~E_2~0); 13099#L1476-1 assume !(1 == ~E_3~0); 13100#L1481-1 assume !(1 == ~E_4~0); 13248#L1486-1 assume !(1 == ~E_5~0); 11954#L1491-1 assume !(1 == ~E_6~0); 11594#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11595#L1501-1 assume !(1 == ~E_8~0); 12406#L1506-1 assume !(1 == ~E_9~0); 12407#L1511-1 assume !(1 == ~E_10~0); 12363#L1516-1 assume !(1 == ~E_11~0); 11538#L1521-1 assume !(1 == ~E_12~0); 11539#L1526-1 assume !(1 == ~E_13~0); 11593#L1531-1 assume { :end_inline_reset_delta_events } true; 12136#L1892-2 [2022-02-21 04:24:29,002 INFO L793 eck$LassoCheckResult]: Loop: 12136#L1892-2 assume !false; 13159#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13357#L1233 assume !false; 13340#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12672#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12652#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12810#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11636#L1046 assume !(0 != eval_~tmp~0#1); 11638#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11672#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12844#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13401#L1258-5 assume !(0 == ~T1_E~0); 11814#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11815#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13393#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13399#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13400#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12038#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12039#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13156#L1298-3 assume !(0 == ~T9_E~0); 13157#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13316#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13155#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12656#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11816#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11817#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13240#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11959#L1338-3 assume !(0 == ~E_4~0); 11960#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13072#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13245#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13246#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12612#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12172#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12173#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12929#L1378-3 assume !(0 == ~E_12~0); 12930#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13111#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13112#L607-42 assume 1 == ~m_pc~0; 12725#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12453#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12454#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12186#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12187#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12708#L626-42 assume !(1 == ~t1_pc~0); 12272#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12271#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12575#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12576#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11850#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11851#L645-42 assume !(1 == ~t2_pc~0); 13050#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13051#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13216#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12057#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11564#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11565#L664-42 assume !(1 == ~t3_pc~0); 12091#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12092#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13343#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12878#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12879#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13044#L683-42 assume !(1 == ~t4_pc~0); 12752#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12753#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12885#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13305#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13306#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13150#L702-42 assume !(1 == ~t5_pc~0); 12262#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 12263#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12559#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13232#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 11580#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11581#L721-42 assume 1 == ~t6_pc~0; 11734#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11754#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12218#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13385#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12390#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12236#L740-42 assume !(1 == ~t7_pc~0); 11973#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 11974#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12515#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12370#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12371#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12644#L759-42 assume 1 == ~t8_pc~0; 12493#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12425#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12426#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12504#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12505#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12600#L778-42 assume 1 == ~t9_pc~0; 12437#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12439#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12849#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12754#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12755#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12812#L797-42 assume 1 == ~t10_pc~0; 11979#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11980#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12981#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13290#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12850#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12851#L816-42 assume 1 == ~t11_pc~0; 11528#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11529#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12071#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12072#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12151#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12152#L835-42 assume !(1 == ~t12_pc~0); 12448#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 12449#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12126#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12127#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13209#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12993#L854-42 assume 1 == ~t13_pc~0; 12994#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12070#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11680#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11681#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12327#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12328#L1401-3 assume !(1 == ~M_E~0); 13106#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11917#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11781#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11782#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12381#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12382#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11957#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11958#L1436-3 assume !(1 == ~T8_E~0); 11544#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11545#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13134#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12465#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12118#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12119#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13396#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12058#L1476-3 assume !(1 == ~E_3~0); 12059#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12459#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12086#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12087#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12499#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12500#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12926#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12916#L1516-3 assume !(1 == ~E_11~0); 12917#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12616#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12617#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13011#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11893#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12786#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12427#L1911 assume !(0 == start_simulation_~tmp~3#1); 12428#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12950#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12018#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12888#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11722#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11723#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11952#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11953#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12136#L1892-2 [2022-02-21 04:24:29,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:29,003 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2022-02-21 04:24:29,003 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:29,003 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397748233] [2022-02-21 04:24:29,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:29,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:29,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:29,031 INFO L290 TraceCheckUtils]: 0: Hoare triple {17258#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {17258#true} is VALID [2022-02-21 04:24:29,032 INFO L290 TraceCheckUtils]: 1: Hoare triple {17258#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {17260#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,032 INFO L290 TraceCheckUtils]: 2: Hoare triple {17260#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17260#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,032 INFO L290 TraceCheckUtils]: 3: Hoare triple {17260#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17260#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,033 INFO L290 TraceCheckUtils]: 4: Hoare triple {17260#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {17260#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,033 INFO L290 TraceCheckUtils]: 5: Hoare triple {17260#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17260#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,033 INFO L290 TraceCheckUtils]: 6: Hoare triple {17260#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,033 INFO L290 TraceCheckUtils]: 7: Hoare triple {17259#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,033 INFO L290 TraceCheckUtils]: 8: Hoare triple {17259#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,033 INFO L290 TraceCheckUtils]: 9: Hoare triple {17259#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,034 INFO L290 TraceCheckUtils]: 10: Hoare triple {17259#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,034 INFO L290 TraceCheckUtils]: 11: Hoare triple {17259#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,034 INFO L290 TraceCheckUtils]: 12: Hoare triple {17259#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,034 INFO L290 TraceCheckUtils]: 13: Hoare triple {17259#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {17259#false} is VALID [2022-02-21 04:24:29,034 INFO L290 TraceCheckUtils]: 14: Hoare triple {17259#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,034 INFO L290 TraceCheckUtils]: 15: Hoare triple {17259#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,034 INFO L290 TraceCheckUtils]: 16: Hoare triple {17259#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,034 INFO L290 TraceCheckUtils]: 17: Hoare triple {17259#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,035 INFO L290 TraceCheckUtils]: 18: Hoare triple {17259#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17259#false} is VALID [2022-02-21 04:24:29,035 INFO L290 TraceCheckUtils]: 19: Hoare triple {17259#false} assume 0 == ~M_E~0;~M_E~0 := 1; {17259#false} is VALID [2022-02-21 04:24:29,035 INFO L290 TraceCheckUtils]: 20: Hoare triple {17259#false} assume !(0 == ~T1_E~0); {17259#false} is VALID [2022-02-21 04:24:29,035 INFO L290 TraceCheckUtils]: 21: Hoare triple {17259#false} assume !(0 == ~T2_E~0); {17259#false} is VALID [2022-02-21 04:24:29,035 INFO L290 TraceCheckUtils]: 22: Hoare triple {17259#false} assume !(0 == ~T3_E~0); {17259#false} is VALID [2022-02-21 04:24:29,035 INFO L290 TraceCheckUtils]: 23: Hoare triple {17259#false} assume !(0 == ~T4_E~0); {17259#false} is VALID [2022-02-21 04:24:29,035 INFO L290 TraceCheckUtils]: 24: Hoare triple {17259#false} assume !(0 == ~T5_E~0); {17259#false} is VALID [2022-02-21 04:24:29,036 INFO L290 TraceCheckUtils]: 25: Hoare triple {17259#false} assume !(0 == ~T6_E~0); {17259#false} is VALID [2022-02-21 04:24:29,036 INFO L290 TraceCheckUtils]: 26: Hoare triple {17259#false} assume !(0 == ~T7_E~0); {17259#false} is VALID [2022-02-21 04:24:29,036 INFO L290 TraceCheckUtils]: 27: Hoare triple {17259#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {17259#false} is VALID [2022-02-21 04:24:29,036 INFO L290 TraceCheckUtils]: 28: Hoare triple {17259#false} assume !(0 == ~T9_E~0); {17259#false} is VALID [2022-02-21 04:24:29,036 INFO L290 TraceCheckUtils]: 29: Hoare triple {17259#false} assume !(0 == ~T10_E~0); {17259#false} is VALID [2022-02-21 04:24:29,036 INFO L290 TraceCheckUtils]: 30: Hoare triple {17259#false} assume !(0 == ~T11_E~0); {17259#false} is VALID [2022-02-21 04:24:29,036 INFO L290 TraceCheckUtils]: 31: Hoare triple {17259#false} assume !(0 == ~T12_E~0); {17259#false} is VALID [2022-02-21 04:24:29,036 INFO L290 TraceCheckUtils]: 32: Hoare triple {17259#false} assume !(0 == ~T13_E~0); {17259#false} is VALID [2022-02-21 04:24:29,037 INFO L290 TraceCheckUtils]: 33: Hoare triple {17259#false} assume !(0 == ~E_1~0); {17259#false} is VALID [2022-02-21 04:24:29,037 INFO L290 TraceCheckUtils]: 34: Hoare triple {17259#false} assume !(0 == ~E_2~0); {17259#false} is VALID [2022-02-21 04:24:29,037 INFO L290 TraceCheckUtils]: 35: Hoare triple {17259#false} assume 0 == ~E_3~0;~E_3~0 := 1; {17259#false} is VALID [2022-02-21 04:24:29,037 INFO L290 TraceCheckUtils]: 36: Hoare triple {17259#false} assume !(0 == ~E_4~0); {17259#false} is VALID [2022-02-21 04:24:29,037 INFO L290 TraceCheckUtils]: 37: Hoare triple {17259#false} assume !(0 == ~E_5~0); {17259#false} is VALID [2022-02-21 04:24:29,037 INFO L290 TraceCheckUtils]: 38: Hoare triple {17259#false} assume !(0 == ~E_6~0); {17259#false} is VALID [2022-02-21 04:24:29,037 INFO L290 TraceCheckUtils]: 39: Hoare triple {17259#false} assume !(0 == ~E_7~0); {17259#false} is VALID [2022-02-21 04:24:29,037 INFO L290 TraceCheckUtils]: 40: Hoare triple {17259#false} assume !(0 == ~E_8~0); {17259#false} is VALID [2022-02-21 04:24:29,038 INFO L290 TraceCheckUtils]: 41: Hoare triple {17259#false} assume !(0 == ~E_9~0); {17259#false} is VALID [2022-02-21 04:24:29,038 INFO L290 TraceCheckUtils]: 42: Hoare triple {17259#false} assume !(0 == ~E_10~0); {17259#false} is VALID [2022-02-21 04:24:29,038 INFO L290 TraceCheckUtils]: 43: Hoare triple {17259#false} assume 0 == ~E_11~0;~E_11~0 := 1; {17259#false} is VALID [2022-02-21 04:24:29,038 INFO L290 TraceCheckUtils]: 44: Hoare triple {17259#false} assume !(0 == ~E_12~0); {17259#false} is VALID [2022-02-21 04:24:29,038 INFO L290 TraceCheckUtils]: 45: Hoare triple {17259#false} assume !(0 == ~E_13~0); {17259#false} is VALID [2022-02-21 04:24:29,038 INFO L290 TraceCheckUtils]: 46: Hoare triple {17259#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17259#false} is VALID [2022-02-21 04:24:29,038 INFO L290 TraceCheckUtils]: 47: Hoare triple {17259#false} assume 1 == ~m_pc~0; {17259#false} is VALID [2022-02-21 04:24:29,039 INFO L290 TraceCheckUtils]: 48: Hoare triple {17259#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {17259#false} is VALID [2022-02-21 04:24:29,039 INFO L290 TraceCheckUtils]: 49: Hoare triple {17259#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17259#false} is VALID [2022-02-21 04:24:29,039 INFO L290 TraceCheckUtils]: 50: Hoare triple {17259#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17259#false} is VALID [2022-02-21 04:24:29,039 INFO L290 TraceCheckUtils]: 51: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp~1#1); {17259#false} is VALID [2022-02-21 04:24:29,039 INFO L290 TraceCheckUtils]: 52: Hoare triple {17259#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17259#false} is VALID [2022-02-21 04:24:29,039 INFO L290 TraceCheckUtils]: 53: Hoare triple {17259#false} assume !(1 == ~t1_pc~0); {17259#false} is VALID [2022-02-21 04:24:29,039 INFO L290 TraceCheckUtils]: 54: Hoare triple {17259#false} is_transmit1_triggered_~__retres1~1#1 := 0; {17259#false} is VALID [2022-02-21 04:24:29,039 INFO L290 TraceCheckUtils]: 55: Hoare triple {17259#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17259#false} is VALID [2022-02-21 04:24:29,040 INFO L290 TraceCheckUtils]: 56: Hoare triple {17259#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17259#false} is VALID [2022-02-21 04:24:29,040 INFO L290 TraceCheckUtils]: 57: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___0~0#1); {17259#false} is VALID [2022-02-21 04:24:29,040 INFO L290 TraceCheckUtils]: 58: Hoare triple {17259#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17259#false} is VALID [2022-02-21 04:24:29,040 INFO L290 TraceCheckUtils]: 59: Hoare triple {17259#false} assume 1 == ~t2_pc~0; {17259#false} is VALID [2022-02-21 04:24:29,040 INFO L290 TraceCheckUtils]: 60: Hoare triple {17259#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17259#false} is VALID [2022-02-21 04:24:29,040 INFO L290 TraceCheckUtils]: 61: Hoare triple {17259#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17259#false} is VALID [2022-02-21 04:24:29,040 INFO L290 TraceCheckUtils]: 62: Hoare triple {17259#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17259#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 63: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___1~0#1); {17259#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 64: Hoare triple {17259#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17259#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 65: Hoare triple {17259#false} assume 1 == ~t3_pc~0; {17259#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 66: Hoare triple {17259#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17259#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 67: Hoare triple {17259#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17259#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 68: Hoare triple {17259#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17259#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 69: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___2~0#1); {17259#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 70: Hoare triple {17259#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17259#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 71: Hoare triple {17259#false} assume !(1 == ~t4_pc~0); {17259#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 72: Hoare triple {17259#false} is_transmit4_triggered_~__retres1~4#1 := 0; {17259#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 73: Hoare triple {17259#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17259#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 74: Hoare triple {17259#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17259#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 75: Hoare triple {17259#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17259#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 76: Hoare triple {17259#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17259#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 77: Hoare triple {17259#false} assume 1 == ~t5_pc~0; {17259#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 78: Hoare triple {17259#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17259#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 79: Hoare triple {17259#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17259#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 80: Hoare triple {17259#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17259#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 81: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___4~0#1); {17259#false} is VALID [2022-02-21 04:24:29,052 INFO L290 TraceCheckUtils]: 82: Hoare triple {17259#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17259#false} is VALID [2022-02-21 04:24:29,052 INFO L290 TraceCheckUtils]: 83: Hoare triple {17259#false} assume !(1 == ~t6_pc~0); {17259#false} is VALID [2022-02-21 04:24:29,052 INFO L290 TraceCheckUtils]: 84: Hoare triple {17259#false} is_transmit6_triggered_~__retres1~6#1 := 0; {17259#false} is VALID [2022-02-21 04:24:29,052 INFO L290 TraceCheckUtils]: 85: Hoare triple {17259#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17259#false} is VALID [2022-02-21 04:24:29,052 INFO L290 TraceCheckUtils]: 86: Hoare triple {17259#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {17259#false} is VALID [2022-02-21 04:24:29,053 INFO L290 TraceCheckUtils]: 87: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___5~0#1); {17259#false} is VALID [2022-02-21 04:24:29,053 INFO L290 TraceCheckUtils]: 88: Hoare triple {17259#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17259#false} is VALID [2022-02-21 04:24:29,053 INFO L290 TraceCheckUtils]: 89: Hoare triple {17259#false} assume 1 == ~t7_pc~0; {17259#false} is VALID [2022-02-21 04:24:29,053 INFO L290 TraceCheckUtils]: 90: Hoare triple {17259#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {17259#false} is VALID [2022-02-21 04:24:29,053 INFO L290 TraceCheckUtils]: 91: Hoare triple {17259#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17259#false} is VALID [2022-02-21 04:24:29,053 INFO L290 TraceCheckUtils]: 92: Hoare triple {17259#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {17259#false} is VALID [2022-02-21 04:24:29,053 INFO L290 TraceCheckUtils]: 93: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___6~0#1); {17259#false} is VALID [2022-02-21 04:24:29,053 INFO L290 TraceCheckUtils]: 94: Hoare triple {17259#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17259#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 95: Hoare triple {17259#false} assume !(1 == ~t8_pc~0); {17259#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 96: Hoare triple {17259#false} is_transmit8_triggered_~__retres1~8#1 := 0; {17259#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 97: Hoare triple {17259#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17259#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 98: Hoare triple {17259#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {17259#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 99: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___7~0#1); {17259#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 100: Hoare triple {17259#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {17259#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 101: Hoare triple {17259#false} assume 1 == ~t9_pc~0; {17259#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 102: Hoare triple {17259#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {17259#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 103: Hoare triple {17259#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {17259#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 104: Hoare triple {17259#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {17259#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 105: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___8~0#1); {17259#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 106: Hoare triple {17259#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {17259#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 107: Hoare triple {17259#false} assume !(1 == ~t10_pc~0); {17259#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 108: Hoare triple {17259#false} is_transmit10_triggered_~__retres1~10#1 := 0; {17259#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 109: Hoare triple {17259#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {17259#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 110: Hoare triple {17259#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {17259#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 111: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___9~0#1); {17259#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 112: Hoare triple {17259#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {17259#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 113: Hoare triple {17259#false} assume 1 == ~t11_pc~0; {17259#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 114: Hoare triple {17259#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {17259#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 115: Hoare triple {17259#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {17259#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 116: Hoare triple {17259#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {17259#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 117: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___10~0#1); {17259#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 118: Hoare triple {17259#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {17259#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 119: Hoare triple {17259#false} assume 1 == ~t12_pc~0; {17259#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 120: Hoare triple {17259#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {17259#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 121: Hoare triple {17259#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {17259#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 122: Hoare triple {17259#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {17259#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 123: Hoare triple {17259#false} assume !(0 != activate_threads_~tmp___11~0#1); {17259#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 124: Hoare triple {17259#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {17259#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 125: Hoare triple {17259#false} assume !(1 == ~t13_pc~0); {17259#false} is VALID [2022-02-21 04:24:29,058 INFO L290 TraceCheckUtils]: 126: Hoare triple {17259#false} is_transmit13_triggered_~__retres1~13#1 := 0; {17259#false} is VALID [2022-02-21 04:24:29,058 INFO L290 TraceCheckUtils]: 127: Hoare triple {17259#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {17259#false} is VALID [2022-02-21 04:24:29,058 INFO L290 TraceCheckUtils]: 128: Hoare triple {17259#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {17259#false} is VALID [2022-02-21 04:24:29,058 INFO L290 TraceCheckUtils]: 129: Hoare triple {17259#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {17259#false} is VALID [2022-02-21 04:24:29,058 INFO L290 TraceCheckUtils]: 130: Hoare triple {17259#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17259#false} is VALID [2022-02-21 04:24:29,058 INFO L290 TraceCheckUtils]: 131: Hoare triple {17259#false} assume !(1 == ~M_E~0); {17259#false} is VALID [2022-02-21 04:24:29,058 INFO L290 TraceCheckUtils]: 132: Hoare triple {17259#false} assume !(1 == ~T1_E~0); {17259#false} is VALID [2022-02-21 04:24:29,058 INFO L290 TraceCheckUtils]: 133: Hoare triple {17259#false} assume !(1 == ~T2_E~0); {17259#false} is VALID [2022-02-21 04:24:29,059 INFO L290 TraceCheckUtils]: 134: Hoare triple {17259#false} assume !(1 == ~T3_E~0); {17259#false} is VALID [2022-02-21 04:24:29,059 INFO L290 TraceCheckUtils]: 135: Hoare triple {17259#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,059 INFO L290 TraceCheckUtils]: 136: Hoare triple {17259#false} assume !(1 == ~T5_E~0); {17259#false} is VALID [2022-02-21 04:24:29,059 INFO L290 TraceCheckUtils]: 137: Hoare triple {17259#false} assume !(1 == ~T6_E~0); {17259#false} is VALID [2022-02-21 04:24:29,059 INFO L290 TraceCheckUtils]: 138: Hoare triple {17259#false} assume !(1 == ~T7_E~0); {17259#false} is VALID [2022-02-21 04:24:29,059 INFO L290 TraceCheckUtils]: 139: Hoare triple {17259#false} assume !(1 == ~T8_E~0); {17259#false} is VALID [2022-02-21 04:24:29,059 INFO L290 TraceCheckUtils]: 140: Hoare triple {17259#false} assume !(1 == ~T9_E~0); {17259#false} is VALID [2022-02-21 04:24:29,059 INFO L290 TraceCheckUtils]: 141: Hoare triple {17259#false} assume !(1 == ~T10_E~0); {17259#false} is VALID [2022-02-21 04:24:29,060 INFO L290 TraceCheckUtils]: 142: Hoare triple {17259#false} assume !(1 == ~T11_E~0); {17259#false} is VALID [2022-02-21 04:24:29,060 INFO L290 TraceCheckUtils]: 143: Hoare triple {17259#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,060 INFO L290 TraceCheckUtils]: 144: Hoare triple {17259#false} assume !(1 == ~T13_E~0); {17259#false} is VALID [2022-02-21 04:24:29,060 INFO L290 TraceCheckUtils]: 145: Hoare triple {17259#false} assume !(1 == ~E_1~0); {17259#false} is VALID [2022-02-21 04:24:29,060 INFO L290 TraceCheckUtils]: 146: Hoare triple {17259#false} assume !(1 == ~E_2~0); {17259#false} is VALID [2022-02-21 04:24:29,060 INFO L290 TraceCheckUtils]: 147: Hoare triple {17259#false} assume !(1 == ~E_3~0); {17259#false} is VALID [2022-02-21 04:24:29,060 INFO L290 TraceCheckUtils]: 148: Hoare triple {17259#false} assume !(1 == ~E_4~0); {17259#false} is VALID [2022-02-21 04:24:29,060 INFO L290 TraceCheckUtils]: 149: Hoare triple {17259#false} assume !(1 == ~E_5~0); {17259#false} is VALID [2022-02-21 04:24:29,061 INFO L290 TraceCheckUtils]: 150: Hoare triple {17259#false} assume !(1 == ~E_6~0); {17259#false} is VALID [2022-02-21 04:24:29,061 INFO L290 TraceCheckUtils]: 151: Hoare triple {17259#false} assume 1 == ~E_7~0;~E_7~0 := 2; {17259#false} is VALID [2022-02-21 04:24:29,061 INFO L290 TraceCheckUtils]: 152: Hoare triple {17259#false} assume !(1 == ~E_8~0); {17259#false} is VALID [2022-02-21 04:24:29,061 INFO L290 TraceCheckUtils]: 153: Hoare triple {17259#false} assume !(1 == ~E_9~0); {17259#false} is VALID [2022-02-21 04:24:29,061 INFO L290 TraceCheckUtils]: 154: Hoare triple {17259#false} assume !(1 == ~E_10~0); {17259#false} is VALID [2022-02-21 04:24:29,061 INFO L290 TraceCheckUtils]: 155: Hoare triple {17259#false} assume !(1 == ~E_11~0); {17259#false} is VALID [2022-02-21 04:24:29,061 INFO L290 TraceCheckUtils]: 156: Hoare triple {17259#false} assume !(1 == ~E_12~0); {17259#false} is VALID [2022-02-21 04:24:29,062 INFO L290 TraceCheckUtils]: 157: Hoare triple {17259#false} assume !(1 == ~E_13~0); {17259#false} is VALID [2022-02-21 04:24:29,062 INFO L290 TraceCheckUtils]: 158: Hoare triple {17259#false} assume { :end_inline_reset_delta_events } true; {17259#false} is VALID [2022-02-21 04:24:29,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:29,062 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:29,062 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1397748233] [2022-02-21 04:24:29,063 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1397748233] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:29,063 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:29,063 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:29,063 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285843613] [2022-02-21 04:24:29,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:29,073 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:29,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:29,074 INFO L85 PathProgramCache]: Analyzing trace with hash -1106627154, now seen corresponding path program 1 times [2022-02-21 04:24:29,074 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:29,074 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1897751901] [2022-02-21 04:24:29,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:29,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:29,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:29,141 INFO L290 TraceCheckUtils]: 0: Hoare triple {17261#true} assume !false; {17261#true} is VALID [2022-02-21 04:24:29,142 INFO L290 TraceCheckUtils]: 1: Hoare triple {17261#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17261#true} is VALID [2022-02-21 04:24:29,142 INFO L290 TraceCheckUtils]: 2: Hoare triple {17261#true} assume !false; {17261#true} is VALID [2022-02-21 04:24:29,142 INFO L290 TraceCheckUtils]: 3: Hoare triple {17261#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {17261#true} is VALID [2022-02-21 04:24:29,142 INFO L290 TraceCheckUtils]: 4: Hoare triple {17261#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {17261#true} is VALID [2022-02-21 04:24:29,142 INFO L290 TraceCheckUtils]: 5: Hoare triple {17261#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {17261#true} is VALID [2022-02-21 04:24:29,142 INFO L290 TraceCheckUtils]: 6: Hoare triple {17261#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {17261#true} is VALID [2022-02-21 04:24:29,143 INFO L290 TraceCheckUtils]: 7: Hoare triple {17261#true} assume !(0 != eval_~tmp~0#1); {17261#true} is VALID [2022-02-21 04:24:29,143 INFO L290 TraceCheckUtils]: 8: Hoare triple {17261#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17261#true} is VALID [2022-02-21 04:24:29,143 INFO L290 TraceCheckUtils]: 9: Hoare triple {17261#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17261#true} is VALID [2022-02-21 04:24:29,143 INFO L290 TraceCheckUtils]: 10: Hoare triple {17261#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,143 INFO L290 TraceCheckUtils]: 11: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,144 INFO L290 TraceCheckUtils]: 12: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,144 INFO L290 TraceCheckUtils]: 13: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,144 INFO L290 TraceCheckUtils]: 14: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,145 INFO L290 TraceCheckUtils]: 15: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,145 INFO L290 TraceCheckUtils]: 16: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,145 INFO L290 TraceCheckUtils]: 17: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,145 INFO L290 TraceCheckUtils]: 18: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,146 INFO L290 TraceCheckUtils]: 19: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,146 INFO L290 TraceCheckUtils]: 20: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,146 INFO L290 TraceCheckUtils]: 21: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,147 INFO L290 TraceCheckUtils]: 22: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,147 INFO L290 TraceCheckUtils]: 23: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,147 INFO L290 TraceCheckUtils]: 24: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,148 INFO L290 TraceCheckUtils]: 25: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,148 INFO L290 TraceCheckUtils]: 26: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,148 INFO L290 TraceCheckUtils]: 27: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,148 INFO L290 TraceCheckUtils]: 28: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,149 INFO L290 TraceCheckUtils]: 29: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,155 INFO L290 TraceCheckUtils]: 30: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,155 INFO L290 TraceCheckUtils]: 31: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,156 INFO L290 TraceCheckUtils]: 32: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,156 INFO L290 TraceCheckUtils]: 33: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,156 INFO L290 TraceCheckUtils]: 34: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,157 INFO L290 TraceCheckUtils]: 35: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,157 INFO L290 TraceCheckUtils]: 36: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,157 INFO L290 TraceCheckUtils]: 37: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,158 INFO L290 TraceCheckUtils]: 38: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,158 INFO L290 TraceCheckUtils]: 39: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,158 INFO L290 TraceCheckUtils]: 40: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,159 INFO L290 TraceCheckUtils]: 41: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,159 INFO L290 TraceCheckUtils]: 42: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,159 INFO L290 TraceCheckUtils]: 43: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,159 INFO L290 TraceCheckUtils]: 44: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,160 INFO L290 TraceCheckUtils]: 45: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,160 INFO L290 TraceCheckUtils]: 46: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,160 INFO L290 TraceCheckUtils]: 47: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,161 INFO L290 TraceCheckUtils]: 48: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,161 INFO L290 TraceCheckUtils]: 49: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,161 INFO L290 TraceCheckUtils]: 50: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,161 INFO L290 TraceCheckUtils]: 51: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 52: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 53: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 54: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,163 INFO L290 TraceCheckUtils]: 55: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,163 INFO L290 TraceCheckUtils]: 56: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,163 INFO L290 TraceCheckUtils]: 57: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,163 INFO L290 TraceCheckUtils]: 58: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,164 INFO L290 TraceCheckUtils]: 59: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,164 INFO L290 TraceCheckUtils]: 60: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,164 INFO L290 TraceCheckUtils]: 61: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,165 INFO L290 TraceCheckUtils]: 62: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,165 INFO L290 TraceCheckUtils]: 63: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,165 INFO L290 TraceCheckUtils]: 64: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,165 INFO L290 TraceCheckUtils]: 65: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,166 INFO L290 TraceCheckUtils]: 66: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,166 INFO L290 TraceCheckUtils]: 67: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,166 INFO L290 TraceCheckUtils]: 68: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,166 INFO L290 TraceCheckUtils]: 69: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,167 INFO L290 TraceCheckUtils]: 70: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,167 INFO L290 TraceCheckUtils]: 71: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,167 INFO L290 TraceCheckUtils]: 72: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,168 INFO L290 TraceCheckUtils]: 73: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,168 INFO L290 TraceCheckUtils]: 74: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,168 INFO L290 TraceCheckUtils]: 75: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,168 INFO L290 TraceCheckUtils]: 76: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,169 INFO L290 TraceCheckUtils]: 77: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,169 INFO L290 TraceCheckUtils]: 78: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,169 INFO L290 TraceCheckUtils]: 79: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,170 INFO L290 TraceCheckUtils]: 80: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,170 INFO L290 TraceCheckUtils]: 81: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,170 INFO L290 TraceCheckUtils]: 82: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,170 INFO L290 TraceCheckUtils]: 83: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,171 INFO L290 TraceCheckUtils]: 84: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,171 INFO L290 TraceCheckUtils]: 85: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,171 INFO L290 TraceCheckUtils]: 86: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,171 INFO L290 TraceCheckUtils]: 87: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,172 INFO L290 TraceCheckUtils]: 88: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,172 INFO L290 TraceCheckUtils]: 89: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,172 INFO L290 TraceCheckUtils]: 90: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,173 INFO L290 TraceCheckUtils]: 91: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,173 INFO L290 TraceCheckUtils]: 92: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,173 INFO L290 TraceCheckUtils]: 93: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,173 INFO L290 TraceCheckUtils]: 94: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,174 INFO L290 TraceCheckUtils]: 95: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,175 INFO L290 TraceCheckUtils]: 96: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,175 INFO L290 TraceCheckUtils]: 97: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,176 INFO L290 TraceCheckUtils]: 98: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,179 INFO L290 TraceCheckUtils]: 99: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,180 INFO L290 TraceCheckUtils]: 100: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,180 INFO L290 TraceCheckUtils]: 101: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,180 INFO L290 TraceCheckUtils]: 102: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,180 INFO L290 TraceCheckUtils]: 103: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,181 INFO L290 TraceCheckUtils]: 104: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,181 INFO L290 TraceCheckUtils]: 105: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,181 INFO L290 TraceCheckUtils]: 106: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,182 INFO L290 TraceCheckUtils]: 107: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,182 INFO L290 TraceCheckUtils]: 108: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,182 INFO L290 TraceCheckUtils]: 109: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,182 INFO L290 TraceCheckUtils]: 110: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,183 INFO L290 TraceCheckUtils]: 111: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,183 INFO L290 TraceCheckUtils]: 112: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,183 INFO L290 TraceCheckUtils]: 113: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,184 INFO L290 TraceCheckUtils]: 114: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,184 INFO L290 TraceCheckUtils]: 115: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,184 INFO L290 TraceCheckUtils]: 116: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,184 INFO L290 TraceCheckUtils]: 117: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,185 INFO L290 TraceCheckUtils]: 118: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,185 INFO L290 TraceCheckUtils]: 119: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,185 INFO L290 TraceCheckUtils]: 120: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,185 INFO L290 TraceCheckUtils]: 121: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 122: Hoare triple {17263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {17262#false} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 123: Hoare triple {17262#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 124: Hoare triple {17262#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 125: Hoare triple {17262#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 126: Hoare triple {17262#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 127: Hoare triple {17262#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 128: Hoare triple {17262#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 129: Hoare triple {17262#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 130: Hoare triple {17262#false} assume !(1 == ~T8_E~0); {17262#false} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 131: Hoare triple {17262#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 132: Hoare triple {17262#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 133: Hoare triple {17262#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 134: Hoare triple {17262#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 135: Hoare triple {17262#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 136: Hoare triple {17262#false} assume 1 == ~E_1~0;~E_1~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 137: Hoare triple {17262#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 138: Hoare triple {17262#false} assume !(1 == ~E_3~0); {17262#false} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 139: Hoare triple {17262#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 140: Hoare triple {17262#false} assume 1 == ~E_5~0;~E_5~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 141: Hoare triple {17262#false} assume 1 == ~E_6~0;~E_6~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 142: Hoare triple {17262#false} assume 1 == ~E_7~0;~E_7~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 143: Hoare triple {17262#false} assume 1 == ~E_8~0;~E_8~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 144: Hoare triple {17262#false} assume 1 == ~E_9~0;~E_9~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 145: Hoare triple {17262#false} assume 1 == ~E_10~0;~E_10~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 146: Hoare triple {17262#false} assume !(1 == ~E_11~0); {17262#false} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 147: Hoare triple {17262#false} assume 1 == ~E_12~0;~E_12~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 148: Hoare triple {17262#false} assume 1 == ~E_13~0;~E_13~0 := 2; {17262#false} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 149: Hoare triple {17262#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {17262#false} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 150: Hoare triple {17262#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {17262#false} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 151: Hoare triple {17262#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {17262#false} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 152: Hoare triple {17262#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {17262#false} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 153: Hoare triple {17262#false} assume !(0 == start_simulation_~tmp~3#1); {17262#false} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 154: Hoare triple {17262#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {17262#false} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 155: Hoare triple {17262#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {17262#false} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 156: Hoare triple {17262#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {17262#false} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 157: Hoare triple {17262#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {17262#false} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 158: Hoare triple {17262#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17262#false} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 159: Hoare triple {17262#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17262#false} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 160: Hoare triple {17262#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {17262#false} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 161: Hoare triple {17262#false} assume !(0 != start_simulation_~tmp___0~1#1); {17262#false} is VALID [2022-02-21 04:24:29,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:29,192 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:29,192 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1897751901] [2022-02-21 04:24:29,193 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1897751901] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:29,193 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:29,193 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:29,193 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [521075923] [2022-02-21 04:24:29,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:29,194 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:29,194 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:29,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:29,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:29,195 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,639 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-02-21 04:24:30,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:30,639 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,757 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:30,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:30,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:30,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-02-21 04:24:30,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:30,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:30,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:30,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:30,952 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-02-21 04:24:30,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:30,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:30,979 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:30,982 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2833 transitions. Second operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,984 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2833 transitions. Second operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,986 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. Second operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:31,071 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-02-21 04:24:31,071 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,074 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:31,074 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:31,077 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,079 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:31,168 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-02-21 04:24:31,168 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,170 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:31,170 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:31,171 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:31,171 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:31,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-02-21 04:24:31,254 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-02-21 04:24:31,254 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-02-21 04:24:31,254 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:31,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,259 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:31,259 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:31,259 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:31,261 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,261 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,261 INFO L791 eck$LassoCheckResult]: Stem: 20039#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 20040#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 19859#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19575#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19576#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20752#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20753#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19711#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 19712#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 20166#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20001#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20002#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19778#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19779#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20177#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20354#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20508#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20545#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19789#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19790#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20965#L1258-2 assume !(0 == ~T1_E~0); 20084#L1263-1 assume !(0 == ~T2_E~0); 20085#L1268-1 assume !(0 == ~T3_E~0); 20388#L1273-1 assume !(0 == ~T4_E~0); 20947#L1278-1 assume !(0 == ~T5_E~0); 20808#L1283-1 assume !(0 == ~T6_E~0); 20809#L1288-1 assume !(0 == ~T7_E~0); 21045#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21033#L1298-1 assume !(0 == ~T9_E~0); 20959#L1303-1 assume !(0 == ~T10_E~0); 19604#L1308-1 assume !(0 == ~T11_E~0); 19546#L1313-1 assume !(0 == ~T12_E~0); 19547#L1318-1 assume !(0 == ~T13_E~0); 19553#L1323-1 assume !(0 == ~E_1~0); 19554#L1328-1 assume !(0 == ~E_2~0); 19721#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20680#L1338-1 assume !(0 == ~E_4~0); 20681#L1343-1 assume !(0 == ~E_5~0); 20782#L1348-1 assume !(0 == ~E_6~0); 21068#L1353-1 assume !(0 == ~E_7~0); 20407#L1358-1 assume !(0 == ~E_8~0); 20408#L1363-1 assume !(0 == ~E_9~0); 20698#L1368-1 assume !(0 == ~E_10~0); 19383#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19384#L1378-1 assume !(0 == ~E_12~0); 19670#L1383-1 assume !(0 == ~E_13~0); 19671#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20414#L607 assume 1 == ~m_pc~0; 20415#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19741#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20780#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20334#L1560 assume !(0 != activate_threads_~tmp~1#1); 20335#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19566#L626 assume !(1 == ~t1_pc~0); 19567#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19835#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19836#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20005#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19466#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19467#L645 assume 1 == ~t2_pc~0; 19583#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19540#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20217#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20218#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20310#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20311#L664 assume 1 == ~t3_pc~0; 21067#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19307#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19308#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19966#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19967#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20975#L683 assume !(1 == ~t4_pc~0); 20530#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20482#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20483#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20517#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20641#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20260#L702 assume 1 == ~t5_pc~0; 20261#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20186#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20636#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20934#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20875#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19355#L721 assume !(1 == ~t6_pc~0); 19329#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19330#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19493#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19975#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19976#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20577#L740 assume 1 == ~t7_pc~0; 19404#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19217#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19218#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19207#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19208#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19911#L759 assume !(1 == ~t8_pc~0); 19912#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19941#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20634#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20635#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20766#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21044#L778 assume 1 == ~t9_pc~0; 20931#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19382#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19322#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19251#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19252#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19579#L797 assume !(1 == ~t10_pc~0); 19580#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19698#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20832#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20082#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20083#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20372#L816 assume 1 == ~t11_pc~0; 19287#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19288#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20043#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19982#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19983#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20507#L835 assume 1 == ~t12_pc~0; 20385#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19451#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19473#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19614#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20139#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20140#L854 assume !(1 == ~t13_pc~0); 19780#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19781#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19831#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19491#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19492#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20871#L1401 assume !(1 == ~M_E~0); 19970#L1401-2 assume !(1 == ~T1_E~0); 19971#L1406-1 assume !(1 == ~T2_E~0); 20566#L1411-1 assume !(1 == ~T3_E~0); 20567#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20233#L1421-1 assume !(1 == ~T5_E~0); 19776#L1426-1 assume !(1 == ~T6_E~0); 19777#L1431-1 assume !(1 == ~T7_E~0); 19325#L1436-1 assume !(1 == ~T8_E~0); 19326#L1441-1 assume !(1 == ~T9_E~0); 20073#L1446-1 assume !(1 == ~T10_E~0); 20074#L1451-1 assume !(1 == ~T11_E~0); 20779#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20433#L1461-1 assume !(1 == ~T13_E~0); 19994#L1466-1 assume !(1 == ~E_1~0); 19995#L1471-1 assume !(1 == ~E_2~0); 20764#L1476-1 assume !(1 == ~E_3~0); 20765#L1481-1 assume !(1 == ~E_4~0); 20913#L1486-1 assume !(1 == ~E_5~0); 19619#L1491-1 assume !(1 == ~E_6~0); 19259#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19260#L1501-1 assume !(1 == ~E_8~0); 20071#L1506-1 assume !(1 == ~E_9~0); 20072#L1511-1 assume !(1 == ~E_10~0); 20028#L1516-1 assume !(1 == ~E_11~0); 19203#L1521-1 assume !(1 == ~E_12~0); 19204#L1526-1 assume !(1 == ~E_13~0); 19258#L1531-1 assume { :end_inline_reset_delta_events } true; 19801#L1892-2 [2022-02-21 04:24:31,261 INFO L793 eck$LassoCheckResult]: Loop: 19801#L1892-2 assume !false; 20824#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21022#L1233 assume !false; 21005#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20337#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20317#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20475#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19301#L1046 assume !(0 != eval_~tmp~0#1); 19303#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19337#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20509#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21066#L1258-5 assume !(0 == ~T1_E~0); 19479#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19480#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21058#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21064#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21065#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19703#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19704#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20821#L1298-3 assume !(0 == ~T9_E~0); 20822#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20981#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20820#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20321#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19481#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19482#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20905#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19624#L1338-3 assume !(0 == ~E_4~0); 19625#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20737#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20910#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20911#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20277#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19837#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19838#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20594#L1378-3 assume !(0 == ~E_12~0); 20595#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20776#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20777#L607-42 assume 1 == ~m_pc~0; 20390#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20118#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20119#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19851#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19852#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20373#L626-42 assume !(1 == ~t1_pc~0); 19937#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 19936#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20240#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20241#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19515#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19516#L645-42 assume !(1 == ~t2_pc~0); 20715#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20716#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20881#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19722#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19229#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19230#L664-42 assume 1 == ~t3_pc~0; 20032#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19757#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21008#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20543#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20544#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20709#L683-42 assume !(1 == ~t4_pc~0); 20417#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20418#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20550#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20970#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20971#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20815#L702-42 assume !(1 == ~t5_pc~0); 19927#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 19928#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20224#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20897#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 19245#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19246#L721-42 assume 1 == ~t6_pc~0; 19399#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19419#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19883#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21050#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20055#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19901#L740-42 assume !(1 == ~t7_pc~0); 19638#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19639#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20180#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20035#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20036#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20309#L759-42 assume 1 == ~t8_pc~0; 20158#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20090#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20091#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20169#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20170#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20265#L778-42 assume 1 == ~t9_pc~0; 20102#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20104#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20514#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20419#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20420#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20477#L797-42 assume 1 == ~t10_pc~0; 19644#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19645#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20646#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20955#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20515#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20516#L816-42 assume 1 == ~t11_pc~0; 19193#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19194#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19736#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19737#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19816#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19817#L835-42 assume !(1 == ~t12_pc~0); 20113#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 20114#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19791#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19792#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20874#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20658#L854-42 assume 1 == ~t13_pc~0; 20659#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 19735#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19345#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19346#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19992#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19993#L1401-3 assume !(1 == ~M_E~0); 20771#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19582#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19446#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19447#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20046#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20047#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19622#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19623#L1436-3 assume !(1 == ~T8_E~0); 19209#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19210#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20799#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20130#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19783#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 19784#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21061#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19723#L1476-3 assume !(1 == ~E_3~0); 19724#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20124#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19751#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19752#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20164#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20165#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20591#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20581#L1516-3 assume !(1 == ~E_11~0); 20582#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20281#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20282#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20676#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19558#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20451#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 20092#L1911 assume !(0 == start_simulation_~tmp~3#1); 20093#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20615#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19683#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20553#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19387#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19388#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19617#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19618#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19801#L1892-2 [2022-02-21 04:24:31,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,262 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2022-02-21 04:24:31,262 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,262 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911704409] [2022-02-21 04:24:31,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:31,288 INFO L290 TraceCheckUtils]: 0: Hoare triple {24923#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {24923#true} is VALID [2022-02-21 04:24:31,288 INFO L290 TraceCheckUtils]: 1: Hoare triple {24923#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {24925#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,289 INFO L290 TraceCheckUtils]: 2: Hoare triple {24925#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {24925#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,289 INFO L290 TraceCheckUtils]: 3: Hoare triple {24925#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {24925#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,289 INFO L290 TraceCheckUtils]: 4: Hoare triple {24925#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {24925#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,289 INFO L290 TraceCheckUtils]: 5: Hoare triple {24925#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {24925#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,290 INFO L290 TraceCheckUtils]: 6: Hoare triple {24925#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {24925#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,290 INFO L290 TraceCheckUtils]: 7: Hoare triple {24925#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,290 INFO L290 TraceCheckUtils]: 8: Hoare triple {24924#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,290 INFO L290 TraceCheckUtils]: 9: Hoare triple {24924#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,290 INFO L290 TraceCheckUtils]: 10: Hoare triple {24924#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,290 INFO L290 TraceCheckUtils]: 11: Hoare triple {24924#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,291 INFO L290 TraceCheckUtils]: 12: Hoare triple {24924#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,291 INFO L290 TraceCheckUtils]: 13: Hoare triple {24924#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {24924#false} is VALID [2022-02-21 04:24:31,291 INFO L290 TraceCheckUtils]: 14: Hoare triple {24924#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,291 INFO L290 TraceCheckUtils]: 15: Hoare triple {24924#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,291 INFO L290 TraceCheckUtils]: 16: Hoare triple {24924#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,291 INFO L290 TraceCheckUtils]: 17: Hoare triple {24924#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,291 INFO L290 TraceCheckUtils]: 18: Hoare triple {24924#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {24924#false} is VALID [2022-02-21 04:24:31,291 INFO L290 TraceCheckUtils]: 19: Hoare triple {24924#false} assume 0 == ~M_E~0;~M_E~0 := 1; {24924#false} is VALID [2022-02-21 04:24:31,291 INFO L290 TraceCheckUtils]: 20: Hoare triple {24924#false} assume !(0 == ~T1_E~0); {24924#false} is VALID [2022-02-21 04:24:31,292 INFO L290 TraceCheckUtils]: 21: Hoare triple {24924#false} assume !(0 == ~T2_E~0); {24924#false} is VALID [2022-02-21 04:24:31,292 INFO L290 TraceCheckUtils]: 22: Hoare triple {24924#false} assume !(0 == ~T3_E~0); {24924#false} is VALID [2022-02-21 04:24:31,292 INFO L290 TraceCheckUtils]: 23: Hoare triple {24924#false} assume !(0 == ~T4_E~0); {24924#false} is VALID [2022-02-21 04:24:31,292 INFO L290 TraceCheckUtils]: 24: Hoare triple {24924#false} assume !(0 == ~T5_E~0); {24924#false} is VALID [2022-02-21 04:24:31,292 INFO L290 TraceCheckUtils]: 25: Hoare triple {24924#false} assume !(0 == ~T6_E~0); {24924#false} is VALID [2022-02-21 04:24:31,292 INFO L290 TraceCheckUtils]: 26: Hoare triple {24924#false} assume !(0 == ~T7_E~0); {24924#false} is VALID [2022-02-21 04:24:31,292 INFO L290 TraceCheckUtils]: 27: Hoare triple {24924#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {24924#false} is VALID [2022-02-21 04:24:31,292 INFO L290 TraceCheckUtils]: 28: Hoare triple {24924#false} assume !(0 == ~T9_E~0); {24924#false} is VALID [2022-02-21 04:24:31,292 INFO L290 TraceCheckUtils]: 29: Hoare triple {24924#false} assume !(0 == ~T10_E~0); {24924#false} is VALID [2022-02-21 04:24:31,293 INFO L290 TraceCheckUtils]: 30: Hoare triple {24924#false} assume !(0 == ~T11_E~0); {24924#false} is VALID [2022-02-21 04:24:31,293 INFO L290 TraceCheckUtils]: 31: Hoare triple {24924#false} assume !(0 == ~T12_E~0); {24924#false} is VALID [2022-02-21 04:24:31,293 INFO L290 TraceCheckUtils]: 32: Hoare triple {24924#false} assume !(0 == ~T13_E~0); {24924#false} is VALID [2022-02-21 04:24:31,293 INFO L290 TraceCheckUtils]: 33: Hoare triple {24924#false} assume !(0 == ~E_1~0); {24924#false} is VALID [2022-02-21 04:24:31,293 INFO L290 TraceCheckUtils]: 34: Hoare triple {24924#false} assume !(0 == ~E_2~0); {24924#false} is VALID [2022-02-21 04:24:31,293 INFO L290 TraceCheckUtils]: 35: Hoare triple {24924#false} assume 0 == ~E_3~0;~E_3~0 := 1; {24924#false} is VALID [2022-02-21 04:24:31,293 INFO L290 TraceCheckUtils]: 36: Hoare triple {24924#false} assume !(0 == ~E_4~0); {24924#false} is VALID [2022-02-21 04:24:31,293 INFO L290 TraceCheckUtils]: 37: Hoare triple {24924#false} assume !(0 == ~E_5~0); {24924#false} is VALID [2022-02-21 04:24:31,293 INFO L290 TraceCheckUtils]: 38: Hoare triple {24924#false} assume !(0 == ~E_6~0); {24924#false} is VALID [2022-02-21 04:24:31,294 INFO L290 TraceCheckUtils]: 39: Hoare triple {24924#false} assume !(0 == ~E_7~0); {24924#false} is VALID [2022-02-21 04:24:31,294 INFO L290 TraceCheckUtils]: 40: Hoare triple {24924#false} assume !(0 == ~E_8~0); {24924#false} is VALID [2022-02-21 04:24:31,294 INFO L290 TraceCheckUtils]: 41: Hoare triple {24924#false} assume !(0 == ~E_9~0); {24924#false} is VALID [2022-02-21 04:24:31,294 INFO L290 TraceCheckUtils]: 42: Hoare triple {24924#false} assume !(0 == ~E_10~0); {24924#false} is VALID [2022-02-21 04:24:31,294 INFO L290 TraceCheckUtils]: 43: Hoare triple {24924#false} assume 0 == ~E_11~0;~E_11~0 := 1; {24924#false} is VALID [2022-02-21 04:24:31,294 INFO L290 TraceCheckUtils]: 44: Hoare triple {24924#false} assume !(0 == ~E_12~0); {24924#false} is VALID [2022-02-21 04:24:31,294 INFO L290 TraceCheckUtils]: 45: Hoare triple {24924#false} assume !(0 == ~E_13~0); {24924#false} is VALID [2022-02-21 04:24:31,294 INFO L290 TraceCheckUtils]: 46: Hoare triple {24924#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24924#false} is VALID [2022-02-21 04:24:31,295 INFO L290 TraceCheckUtils]: 47: Hoare triple {24924#false} assume 1 == ~m_pc~0; {24924#false} is VALID [2022-02-21 04:24:31,295 INFO L290 TraceCheckUtils]: 48: Hoare triple {24924#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {24924#false} is VALID [2022-02-21 04:24:31,295 INFO L290 TraceCheckUtils]: 49: Hoare triple {24924#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24924#false} is VALID [2022-02-21 04:24:31,295 INFO L290 TraceCheckUtils]: 50: Hoare triple {24924#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24924#false} is VALID [2022-02-21 04:24:31,295 INFO L290 TraceCheckUtils]: 51: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp~1#1); {24924#false} is VALID [2022-02-21 04:24:31,295 INFO L290 TraceCheckUtils]: 52: Hoare triple {24924#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24924#false} is VALID [2022-02-21 04:24:31,295 INFO L290 TraceCheckUtils]: 53: Hoare triple {24924#false} assume !(1 == ~t1_pc~0); {24924#false} is VALID [2022-02-21 04:24:31,295 INFO L290 TraceCheckUtils]: 54: Hoare triple {24924#false} is_transmit1_triggered_~__retres1~1#1 := 0; {24924#false} is VALID [2022-02-21 04:24:31,295 INFO L290 TraceCheckUtils]: 55: Hoare triple {24924#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24924#false} is VALID [2022-02-21 04:24:31,296 INFO L290 TraceCheckUtils]: 56: Hoare triple {24924#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24924#false} is VALID [2022-02-21 04:24:31,296 INFO L290 TraceCheckUtils]: 57: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___0~0#1); {24924#false} is VALID [2022-02-21 04:24:31,296 INFO L290 TraceCheckUtils]: 58: Hoare triple {24924#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24924#false} is VALID [2022-02-21 04:24:31,296 INFO L290 TraceCheckUtils]: 59: Hoare triple {24924#false} assume 1 == ~t2_pc~0; {24924#false} is VALID [2022-02-21 04:24:31,296 INFO L290 TraceCheckUtils]: 60: Hoare triple {24924#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {24924#false} is VALID [2022-02-21 04:24:31,296 INFO L290 TraceCheckUtils]: 61: Hoare triple {24924#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24924#false} is VALID [2022-02-21 04:24:31,296 INFO L290 TraceCheckUtils]: 62: Hoare triple {24924#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24924#false} is VALID [2022-02-21 04:24:31,296 INFO L290 TraceCheckUtils]: 63: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___1~0#1); {24924#false} is VALID [2022-02-21 04:24:31,297 INFO L290 TraceCheckUtils]: 64: Hoare triple {24924#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24924#false} is VALID [2022-02-21 04:24:31,297 INFO L290 TraceCheckUtils]: 65: Hoare triple {24924#false} assume 1 == ~t3_pc~0; {24924#false} is VALID [2022-02-21 04:24:31,297 INFO L290 TraceCheckUtils]: 66: Hoare triple {24924#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24924#false} is VALID [2022-02-21 04:24:31,297 INFO L290 TraceCheckUtils]: 67: Hoare triple {24924#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24924#false} is VALID [2022-02-21 04:24:31,297 INFO L290 TraceCheckUtils]: 68: Hoare triple {24924#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24924#false} is VALID [2022-02-21 04:24:31,297 INFO L290 TraceCheckUtils]: 69: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___2~0#1); {24924#false} is VALID [2022-02-21 04:24:31,297 INFO L290 TraceCheckUtils]: 70: Hoare triple {24924#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24924#false} is VALID [2022-02-21 04:24:31,297 INFO L290 TraceCheckUtils]: 71: Hoare triple {24924#false} assume !(1 == ~t4_pc~0); {24924#false} is VALID [2022-02-21 04:24:31,298 INFO L290 TraceCheckUtils]: 72: Hoare triple {24924#false} is_transmit4_triggered_~__retres1~4#1 := 0; {24924#false} is VALID [2022-02-21 04:24:31,298 INFO L290 TraceCheckUtils]: 73: Hoare triple {24924#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24924#false} is VALID [2022-02-21 04:24:31,298 INFO L290 TraceCheckUtils]: 74: Hoare triple {24924#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {24924#false} is VALID [2022-02-21 04:24:31,298 INFO L290 TraceCheckUtils]: 75: Hoare triple {24924#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {24924#false} is VALID [2022-02-21 04:24:31,298 INFO L290 TraceCheckUtils]: 76: Hoare triple {24924#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24924#false} is VALID [2022-02-21 04:24:31,298 INFO L290 TraceCheckUtils]: 77: Hoare triple {24924#false} assume 1 == ~t5_pc~0; {24924#false} is VALID [2022-02-21 04:24:31,298 INFO L290 TraceCheckUtils]: 78: Hoare triple {24924#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {24924#false} is VALID [2022-02-21 04:24:31,298 INFO L290 TraceCheckUtils]: 79: Hoare triple {24924#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24924#false} is VALID [2022-02-21 04:24:31,298 INFO L290 TraceCheckUtils]: 80: Hoare triple {24924#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {24924#false} is VALID [2022-02-21 04:24:31,299 INFO L290 TraceCheckUtils]: 81: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___4~0#1); {24924#false} is VALID [2022-02-21 04:24:31,299 INFO L290 TraceCheckUtils]: 82: Hoare triple {24924#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24924#false} is VALID [2022-02-21 04:24:31,299 INFO L290 TraceCheckUtils]: 83: Hoare triple {24924#false} assume !(1 == ~t6_pc~0); {24924#false} is VALID [2022-02-21 04:24:31,299 INFO L290 TraceCheckUtils]: 84: Hoare triple {24924#false} is_transmit6_triggered_~__retres1~6#1 := 0; {24924#false} is VALID [2022-02-21 04:24:31,299 INFO L290 TraceCheckUtils]: 85: Hoare triple {24924#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24924#false} is VALID [2022-02-21 04:24:31,299 INFO L290 TraceCheckUtils]: 86: Hoare triple {24924#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {24924#false} is VALID [2022-02-21 04:24:31,299 INFO L290 TraceCheckUtils]: 87: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___5~0#1); {24924#false} is VALID [2022-02-21 04:24:31,299 INFO L290 TraceCheckUtils]: 88: Hoare triple {24924#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24924#false} is VALID [2022-02-21 04:24:31,300 INFO L290 TraceCheckUtils]: 89: Hoare triple {24924#false} assume 1 == ~t7_pc~0; {24924#false} is VALID [2022-02-21 04:24:31,300 INFO L290 TraceCheckUtils]: 90: Hoare triple {24924#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {24924#false} is VALID [2022-02-21 04:24:31,300 INFO L290 TraceCheckUtils]: 91: Hoare triple {24924#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24924#false} is VALID [2022-02-21 04:24:31,300 INFO L290 TraceCheckUtils]: 92: Hoare triple {24924#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {24924#false} is VALID [2022-02-21 04:24:31,300 INFO L290 TraceCheckUtils]: 93: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___6~0#1); {24924#false} is VALID [2022-02-21 04:24:31,300 INFO L290 TraceCheckUtils]: 94: Hoare triple {24924#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {24924#false} is VALID [2022-02-21 04:24:31,300 INFO L290 TraceCheckUtils]: 95: Hoare triple {24924#false} assume !(1 == ~t8_pc~0); {24924#false} is VALID [2022-02-21 04:24:31,300 INFO L290 TraceCheckUtils]: 96: Hoare triple {24924#false} is_transmit8_triggered_~__retres1~8#1 := 0; {24924#false} is VALID [2022-02-21 04:24:31,301 INFO L290 TraceCheckUtils]: 97: Hoare triple {24924#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {24924#false} is VALID [2022-02-21 04:24:31,301 INFO L290 TraceCheckUtils]: 98: Hoare triple {24924#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {24924#false} is VALID [2022-02-21 04:24:31,301 INFO L290 TraceCheckUtils]: 99: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___7~0#1); {24924#false} is VALID [2022-02-21 04:24:31,301 INFO L290 TraceCheckUtils]: 100: Hoare triple {24924#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {24924#false} is VALID [2022-02-21 04:24:31,301 INFO L290 TraceCheckUtils]: 101: Hoare triple {24924#false} assume 1 == ~t9_pc~0; {24924#false} is VALID [2022-02-21 04:24:31,301 INFO L290 TraceCheckUtils]: 102: Hoare triple {24924#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {24924#false} is VALID [2022-02-21 04:24:31,301 INFO L290 TraceCheckUtils]: 103: Hoare triple {24924#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {24924#false} is VALID [2022-02-21 04:24:31,301 INFO L290 TraceCheckUtils]: 104: Hoare triple {24924#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {24924#false} is VALID [2022-02-21 04:24:31,301 INFO L290 TraceCheckUtils]: 105: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___8~0#1); {24924#false} is VALID [2022-02-21 04:24:31,302 INFO L290 TraceCheckUtils]: 106: Hoare triple {24924#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {24924#false} is VALID [2022-02-21 04:24:31,302 INFO L290 TraceCheckUtils]: 107: Hoare triple {24924#false} assume !(1 == ~t10_pc~0); {24924#false} is VALID [2022-02-21 04:24:31,302 INFO L290 TraceCheckUtils]: 108: Hoare triple {24924#false} is_transmit10_triggered_~__retres1~10#1 := 0; {24924#false} is VALID [2022-02-21 04:24:31,302 INFO L290 TraceCheckUtils]: 109: Hoare triple {24924#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {24924#false} is VALID [2022-02-21 04:24:31,302 INFO L290 TraceCheckUtils]: 110: Hoare triple {24924#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {24924#false} is VALID [2022-02-21 04:24:31,302 INFO L290 TraceCheckUtils]: 111: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___9~0#1); {24924#false} is VALID [2022-02-21 04:24:31,302 INFO L290 TraceCheckUtils]: 112: Hoare triple {24924#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {24924#false} is VALID [2022-02-21 04:24:31,302 INFO L290 TraceCheckUtils]: 113: Hoare triple {24924#false} assume 1 == ~t11_pc~0; {24924#false} is VALID [2022-02-21 04:24:31,303 INFO L290 TraceCheckUtils]: 114: Hoare triple {24924#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {24924#false} is VALID [2022-02-21 04:24:31,303 INFO L290 TraceCheckUtils]: 115: Hoare triple {24924#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {24924#false} is VALID [2022-02-21 04:24:31,303 INFO L290 TraceCheckUtils]: 116: Hoare triple {24924#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {24924#false} is VALID [2022-02-21 04:24:31,303 INFO L290 TraceCheckUtils]: 117: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___10~0#1); {24924#false} is VALID [2022-02-21 04:24:31,303 INFO L290 TraceCheckUtils]: 118: Hoare triple {24924#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {24924#false} is VALID [2022-02-21 04:24:31,303 INFO L290 TraceCheckUtils]: 119: Hoare triple {24924#false} assume 1 == ~t12_pc~0; {24924#false} is VALID [2022-02-21 04:24:31,303 INFO L290 TraceCheckUtils]: 120: Hoare triple {24924#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {24924#false} is VALID [2022-02-21 04:24:31,303 INFO L290 TraceCheckUtils]: 121: Hoare triple {24924#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {24924#false} is VALID [2022-02-21 04:24:31,304 INFO L290 TraceCheckUtils]: 122: Hoare triple {24924#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {24924#false} is VALID [2022-02-21 04:24:31,304 INFO L290 TraceCheckUtils]: 123: Hoare triple {24924#false} assume !(0 != activate_threads_~tmp___11~0#1); {24924#false} is VALID [2022-02-21 04:24:31,304 INFO L290 TraceCheckUtils]: 124: Hoare triple {24924#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {24924#false} is VALID [2022-02-21 04:24:31,304 INFO L290 TraceCheckUtils]: 125: Hoare triple {24924#false} assume !(1 == ~t13_pc~0); {24924#false} is VALID [2022-02-21 04:24:31,304 INFO L290 TraceCheckUtils]: 126: Hoare triple {24924#false} is_transmit13_triggered_~__retres1~13#1 := 0; {24924#false} is VALID [2022-02-21 04:24:31,304 INFO L290 TraceCheckUtils]: 127: Hoare triple {24924#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {24924#false} is VALID [2022-02-21 04:24:31,304 INFO L290 TraceCheckUtils]: 128: Hoare triple {24924#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {24924#false} is VALID [2022-02-21 04:24:31,304 INFO L290 TraceCheckUtils]: 129: Hoare triple {24924#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {24924#false} is VALID [2022-02-21 04:24:31,304 INFO L290 TraceCheckUtils]: 130: Hoare triple {24924#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24924#false} is VALID [2022-02-21 04:24:31,305 INFO L290 TraceCheckUtils]: 131: Hoare triple {24924#false} assume !(1 == ~M_E~0); {24924#false} is VALID [2022-02-21 04:24:31,305 INFO L290 TraceCheckUtils]: 132: Hoare triple {24924#false} assume !(1 == ~T1_E~0); {24924#false} is VALID [2022-02-21 04:24:31,305 INFO L290 TraceCheckUtils]: 133: Hoare triple {24924#false} assume !(1 == ~T2_E~0); {24924#false} is VALID [2022-02-21 04:24:31,305 INFO L290 TraceCheckUtils]: 134: Hoare triple {24924#false} assume !(1 == ~T3_E~0); {24924#false} is VALID [2022-02-21 04:24:31,305 INFO L290 TraceCheckUtils]: 135: Hoare triple {24924#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,305 INFO L290 TraceCheckUtils]: 136: Hoare triple {24924#false} assume !(1 == ~T5_E~0); {24924#false} is VALID [2022-02-21 04:24:31,305 INFO L290 TraceCheckUtils]: 137: Hoare triple {24924#false} assume !(1 == ~T6_E~0); {24924#false} is VALID [2022-02-21 04:24:31,305 INFO L290 TraceCheckUtils]: 138: Hoare triple {24924#false} assume !(1 == ~T7_E~0); {24924#false} is VALID [2022-02-21 04:24:31,305 INFO L290 TraceCheckUtils]: 139: Hoare triple {24924#false} assume !(1 == ~T8_E~0); {24924#false} is VALID [2022-02-21 04:24:31,306 INFO L290 TraceCheckUtils]: 140: Hoare triple {24924#false} assume !(1 == ~T9_E~0); {24924#false} is VALID [2022-02-21 04:24:31,306 INFO L290 TraceCheckUtils]: 141: Hoare triple {24924#false} assume !(1 == ~T10_E~0); {24924#false} is VALID [2022-02-21 04:24:31,306 INFO L290 TraceCheckUtils]: 142: Hoare triple {24924#false} assume !(1 == ~T11_E~0); {24924#false} is VALID [2022-02-21 04:24:31,306 INFO L290 TraceCheckUtils]: 143: Hoare triple {24924#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,306 INFO L290 TraceCheckUtils]: 144: Hoare triple {24924#false} assume !(1 == ~T13_E~0); {24924#false} is VALID [2022-02-21 04:24:31,306 INFO L290 TraceCheckUtils]: 145: Hoare triple {24924#false} assume !(1 == ~E_1~0); {24924#false} is VALID [2022-02-21 04:24:31,306 INFO L290 TraceCheckUtils]: 146: Hoare triple {24924#false} assume !(1 == ~E_2~0); {24924#false} is VALID [2022-02-21 04:24:31,306 INFO L290 TraceCheckUtils]: 147: Hoare triple {24924#false} assume !(1 == ~E_3~0); {24924#false} is VALID [2022-02-21 04:24:31,306 INFO L290 TraceCheckUtils]: 148: Hoare triple {24924#false} assume !(1 == ~E_4~0); {24924#false} is VALID [2022-02-21 04:24:31,307 INFO L290 TraceCheckUtils]: 149: Hoare triple {24924#false} assume !(1 == ~E_5~0); {24924#false} is VALID [2022-02-21 04:24:31,307 INFO L290 TraceCheckUtils]: 150: Hoare triple {24924#false} assume !(1 == ~E_6~0); {24924#false} is VALID [2022-02-21 04:24:31,307 INFO L290 TraceCheckUtils]: 151: Hoare triple {24924#false} assume 1 == ~E_7~0;~E_7~0 := 2; {24924#false} is VALID [2022-02-21 04:24:31,307 INFO L290 TraceCheckUtils]: 152: Hoare triple {24924#false} assume !(1 == ~E_8~0); {24924#false} is VALID [2022-02-21 04:24:31,307 INFO L290 TraceCheckUtils]: 153: Hoare triple {24924#false} assume !(1 == ~E_9~0); {24924#false} is VALID [2022-02-21 04:24:31,307 INFO L290 TraceCheckUtils]: 154: Hoare triple {24924#false} assume !(1 == ~E_10~0); {24924#false} is VALID [2022-02-21 04:24:31,307 INFO L290 TraceCheckUtils]: 155: Hoare triple {24924#false} assume !(1 == ~E_11~0); {24924#false} is VALID [2022-02-21 04:24:31,307 INFO L290 TraceCheckUtils]: 156: Hoare triple {24924#false} assume !(1 == ~E_12~0); {24924#false} is VALID [2022-02-21 04:24:31,308 INFO L290 TraceCheckUtils]: 157: Hoare triple {24924#false} assume !(1 == ~E_13~0); {24924#false} is VALID [2022-02-21 04:24:31,308 INFO L290 TraceCheckUtils]: 158: Hoare triple {24924#false} assume { :end_inline_reset_delta_events } true; {24924#false} is VALID [2022-02-21 04:24:31,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,308 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,308 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911704409] [2022-02-21 04:24:31,310 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911704409] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,310 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,310 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:31,310 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044129944] [2022-02-21 04:24:31,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,311 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:31,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,312 INFO L85 PathProgramCache]: Analyzing trace with hash -1427949617, now seen corresponding path program 1 times [2022-02-21 04:24:31,312 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,314 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1499657311] [2022-02-21 04:24:31,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:31,378 INFO L290 TraceCheckUtils]: 0: Hoare triple {24926#true} assume !false; {24926#true} is VALID [2022-02-21 04:24:31,378 INFO L290 TraceCheckUtils]: 1: Hoare triple {24926#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {24926#true} is VALID [2022-02-21 04:24:31,378 INFO L290 TraceCheckUtils]: 2: Hoare triple {24926#true} assume !false; {24926#true} is VALID [2022-02-21 04:24:31,379 INFO L290 TraceCheckUtils]: 3: Hoare triple {24926#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {24926#true} is VALID [2022-02-21 04:24:31,379 INFO L290 TraceCheckUtils]: 4: Hoare triple {24926#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {24926#true} is VALID [2022-02-21 04:24:31,379 INFO L290 TraceCheckUtils]: 5: Hoare triple {24926#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {24926#true} is VALID [2022-02-21 04:24:31,379 INFO L290 TraceCheckUtils]: 6: Hoare triple {24926#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {24926#true} is VALID [2022-02-21 04:24:31,379 INFO L290 TraceCheckUtils]: 7: Hoare triple {24926#true} assume !(0 != eval_~tmp~0#1); {24926#true} is VALID [2022-02-21 04:24:31,379 INFO L290 TraceCheckUtils]: 8: Hoare triple {24926#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {24926#true} is VALID [2022-02-21 04:24:31,379 INFO L290 TraceCheckUtils]: 9: Hoare triple {24926#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {24926#true} is VALID [2022-02-21 04:24:31,380 INFO L290 TraceCheckUtils]: 10: Hoare triple {24926#true} assume 0 == ~M_E~0;~M_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,380 INFO L290 TraceCheckUtils]: 11: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,380 INFO L290 TraceCheckUtils]: 12: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,381 INFO L290 TraceCheckUtils]: 13: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,381 INFO L290 TraceCheckUtils]: 14: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,381 INFO L290 TraceCheckUtils]: 15: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,381 INFO L290 TraceCheckUtils]: 16: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,382 INFO L290 TraceCheckUtils]: 17: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,382 INFO L290 TraceCheckUtils]: 18: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,382 INFO L290 TraceCheckUtils]: 19: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,383 INFO L290 TraceCheckUtils]: 20: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,383 INFO L290 TraceCheckUtils]: 21: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,383 INFO L290 TraceCheckUtils]: 22: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,403 INFO L290 TraceCheckUtils]: 23: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,404 INFO L290 TraceCheckUtils]: 24: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,404 INFO L290 TraceCheckUtils]: 25: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,404 INFO L290 TraceCheckUtils]: 26: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,405 INFO L290 TraceCheckUtils]: 27: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,405 INFO L290 TraceCheckUtils]: 28: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,405 INFO L290 TraceCheckUtils]: 29: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,406 INFO L290 TraceCheckUtils]: 30: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,406 INFO L290 TraceCheckUtils]: 31: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,406 INFO L290 TraceCheckUtils]: 32: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,406 INFO L290 TraceCheckUtils]: 33: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,407 INFO L290 TraceCheckUtils]: 34: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,407 INFO L290 TraceCheckUtils]: 35: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,407 INFO L290 TraceCheckUtils]: 36: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,408 INFO L290 TraceCheckUtils]: 37: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,408 INFO L290 TraceCheckUtils]: 38: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,408 INFO L290 TraceCheckUtils]: 39: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,408 INFO L290 TraceCheckUtils]: 40: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,409 INFO L290 TraceCheckUtils]: 41: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,409 INFO L290 TraceCheckUtils]: 42: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,409 INFO L290 TraceCheckUtils]: 43: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,409 INFO L290 TraceCheckUtils]: 44: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,410 INFO L290 TraceCheckUtils]: 45: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,410 INFO L290 TraceCheckUtils]: 46: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,410 INFO L290 TraceCheckUtils]: 47: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,411 INFO L290 TraceCheckUtils]: 48: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,411 INFO L290 TraceCheckUtils]: 49: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,411 INFO L290 TraceCheckUtils]: 50: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,411 INFO L290 TraceCheckUtils]: 51: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,412 INFO L290 TraceCheckUtils]: 52: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,412 INFO L290 TraceCheckUtils]: 53: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,412 INFO L290 TraceCheckUtils]: 54: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,413 INFO L290 TraceCheckUtils]: 55: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,413 INFO L290 TraceCheckUtils]: 56: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,413 INFO L290 TraceCheckUtils]: 57: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,413 INFO L290 TraceCheckUtils]: 58: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,414 INFO L290 TraceCheckUtils]: 59: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,414 INFO L290 TraceCheckUtils]: 60: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,414 INFO L290 TraceCheckUtils]: 61: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,414 INFO L290 TraceCheckUtils]: 62: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,415 INFO L290 TraceCheckUtils]: 63: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,415 INFO L290 TraceCheckUtils]: 64: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,415 INFO L290 TraceCheckUtils]: 65: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,416 INFO L290 TraceCheckUtils]: 66: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,416 INFO L290 TraceCheckUtils]: 67: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,416 INFO L290 TraceCheckUtils]: 68: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,416 INFO L290 TraceCheckUtils]: 69: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,417 INFO L290 TraceCheckUtils]: 70: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,417 INFO L290 TraceCheckUtils]: 71: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,417 INFO L290 TraceCheckUtils]: 72: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,417 INFO L290 TraceCheckUtils]: 73: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,418 INFO L290 TraceCheckUtils]: 74: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,418 INFO L290 TraceCheckUtils]: 75: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,418 INFO L290 TraceCheckUtils]: 76: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,419 INFO L290 TraceCheckUtils]: 77: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,419 INFO L290 TraceCheckUtils]: 78: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,419 INFO L290 TraceCheckUtils]: 79: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,419 INFO L290 TraceCheckUtils]: 80: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,420 INFO L290 TraceCheckUtils]: 81: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,420 INFO L290 TraceCheckUtils]: 82: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,420 INFO L290 TraceCheckUtils]: 83: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,421 INFO L290 TraceCheckUtils]: 84: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,421 INFO L290 TraceCheckUtils]: 85: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,421 INFO L290 TraceCheckUtils]: 86: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,421 INFO L290 TraceCheckUtils]: 87: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,422 INFO L290 TraceCheckUtils]: 88: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,422 INFO L290 TraceCheckUtils]: 89: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,422 INFO L290 TraceCheckUtils]: 90: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,423 INFO L290 TraceCheckUtils]: 91: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,423 INFO L290 TraceCheckUtils]: 92: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,423 INFO L290 TraceCheckUtils]: 93: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,423 INFO L290 TraceCheckUtils]: 94: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,424 INFO L290 TraceCheckUtils]: 95: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,424 INFO L290 TraceCheckUtils]: 96: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,424 INFO L290 TraceCheckUtils]: 97: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,425 INFO L290 TraceCheckUtils]: 98: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,425 INFO L290 TraceCheckUtils]: 99: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,425 INFO L290 TraceCheckUtils]: 100: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,425 INFO L290 TraceCheckUtils]: 101: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,426 INFO L290 TraceCheckUtils]: 102: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,426 INFO L290 TraceCheckUtils]: 103: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,426 INFO L290 TraceCheckUtils]: 104: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,426 INFO L290 TraceCheckUtils]: 105: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,427 INFO L290 TraceCheckUtils]: 106: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,427 INFO L290 TraceCheckUtils]: 107: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,427 INFO L290 TraceCheckUtils]: 108: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,428 INFO L290 TraceCheckUtils]: 109: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,428 INFO L290 TraceCheckUtils]: 110: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,428 INFO L290 TraceCheckUtils]: 111: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,428 INFO L290 TraceCheckUtils]: 112: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,429 INFO L290 TraceCheckUtils]: 113: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,429 INFO L290 TraceCheckUtils]: 114: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,429 INFO L290 TraceCheckUtils]: 115: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,430 INFO L290 TraceCheckUtils]: 116: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,430 INFO L290 TraceCheckUtils]: 117: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,430 INFO L290 TraceCheckUtils]: 118: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,430 INFO L290 TraceCheckUtils]: 119: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,431 INFO L290 TraceCheckUtils]: 120: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,431 INFO L290 TraceCheckUtils]: 121: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24928#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:31,431 INFO L290 TraceCheckUtils]: 122: Hoare triple {24928#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {24927#false} is VALID [2022-02-21 04:24:31,431 INFO L290 TraceCheckUtils]: 123: Hoare triple {24927#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,432 INFO L290 TraceCheckUtils]: 124: Hoare triple {24927#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,432 INFO L290 TraceCheckUtils]: 125: Hoare triple {24927#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,432 INFO L290 TraceCheckUtils]: 126: Hoare triple {24927#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,432 INFO L290 TraceCheckUtils]: 127: Hoare triple {24927#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,432 INFO L290 TraceCheckUtils]: 128: Hoare triple {24927#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,432 INFO L290 TraceCheckUtils]: 129: Hoare triple {24927#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,432 INFO L290 TraceCheckUtils]: 130: Hoare triple {24927#false} assume !(1 == ~T8_E~0); {24927#false} is VALID [2022-02-21 04:24:31,432 INFO L290 TraceCheckUtils]: 131: Hoare triple {24927#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,433 INFO L290 TraceCheckUtils]: 132: Hoare triple {24927#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,433 INFO L290 TraceCheckUtils]: 133: Hoare triple {24927#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,433 INFO L290 TraceCheckUtils]: 134: Hoare triple {24927#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,433 INFO L290 TraceCheckUtils]: 135: Hoare triple {24927#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,433 INFO L290 TraceCheckUtils]: 136: Hoare triple {24927#false} assume 1 == ~E_1~0;~E_1~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,433 INFO L290 TraceCheckUtils]: 137: Hoare triple {24927#false} assume 1 == ~E_2~0;~E_2~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,433 INFO L290 TraceCheckUtils]: 138: Hoare triple {24927#false} assume !(1 == ~E_3~0); {24927#false} is VALID [2022-02-21 04:24:31,433 INFO L290 TraceCheckUtils]: 139: Hoare triple {24927#false} assume 1 == ~E_4~0;~E_4~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,433 INFO L290 TraceCheckUtils]: 140: Hoare triple {24927#false} assume 1 == ~E_5~0;~E_5~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,434 INFO L290 TraceCheckUtils]: 141: Hoare triple {24927#false} assume 1 == ~E_6~0;~E_6~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,434 INFO L290 TraceCheckUtils]: 142: Hoare triple {24927#false} assume 1 == ~E_7~0;~E_7~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,434 INFO L290 TraceCheckUtils]: 143: Hoare triple {24927#false} assume 1 == ~E_8~0;~E_8~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,434 INFO L290 TraceCheckUtils]: 144: Hoare triple {24927#false} assume 1 == ~E_9~0;~E_9~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,434 INFO L290 TraceCheckUtils]: 145: Hoare triple {24927#false} assume 1 == ~E_10~0;~E_10~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,434 INFO L290 TraceCheckUtils]: 146: Hoare triple {24927#false} assume !(1 == ~E_11~0); {24927#false} is VALID [2022-02-21 04:24:31,434 INFO L290 TraceCheckUtils]: 147: Hoare triple {24927#false} assume 1 == ~E_12~0;~E_12~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,434 INFO L290 TraceCheckUtils]: 148: Hoare triple {24927#false} assume 1 == ~E_13~0;~E_13~0 := 2; {24927#false} is VALID [2022-02-21 04:24:31,435 INFO L290 TraceCheckUtils]: 149: Hoare triple {24927#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {24927#false} is VALID [2022-02-21 04:24:31,435 INFO L290 TraceCheckUtils]: 150: Hoare triple {24927#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {24927#false} is VALID [2022-02-21 04:24:31,435 INFO L290 TraceCheckUtils]: 151: Hoare triple {24927#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {24927#false} is VALID [2022-02-21 04:24:31,435 INFO L290 TraceCheckUtils]: 152: Hoare triple {24927#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {24927#false} is VALID [2022-02-21 04:24:31,435 INFO L290 TraceCheckUtils]: 153: Hoare triple {24927#false} assume !(0 == start_simulation_~tmp~3#1); {24927#false} is VALID [2022-02-21 04:24:31,435 INFO L290 TraceCheckUtils]: 154: Hoare triple {24927#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {24927#false} is VALID [2022-02-21 04:24:31,435 INFO L290 TraceCheckUtils]: 155: Hoare triple {24927#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {24927#false} is VALID [2022-02-21 04:24:31,435 INFO L290 TraceCheckUtils]: 156: Hoare triple {24927#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {24927#false} is VALID [2022-02-21 04:24:31,435 INFO L290 TraceCheckUtils]: 157: Hoare triple {24927#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {24927#false} is VALID [2022-02-21 04:24:31,436 INFO L290 TraceCheckUtils]: 158: Hoare triple {24927#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {24927#false} is VALID [2022-02-21 04:24:31,436 INFO L290 TraceCheckUtils]: 159: Hoare triple {24927#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {24927#false} is VALID [2022-02-21 04:24:31,436 INFO L290 TraceCheckUtils]: 160: Hoare triple {24927#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {24927#false} is VALID [2022-02-21 04:24:31,436 INFO L290 TraceCheckUtils]: 161: Hoare triple {24927#false} assume !(0 != start_simulation_~tmp___0~1#1); {24927#false} is VALID [2022-02-21 04:24:31,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,437 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,437 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1499657311] [2022-02-21 04:24:31,437 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1499657311] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,437 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,438 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:31,438 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [847874088] [2022-02-21 04:24:31,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,438 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:31,438 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:31,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:31,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:31,439 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:32,847 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-02-21 04:24:32,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:32,847 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,948 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:32,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:33,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-02-21 04:24:33,158 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:33,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:33,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:33,161 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-02-21 04:24:33,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:33,180 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:33,182 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2832 transitions. Second operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,184 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2832 transitions. Second operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,185 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. Second operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:33,271 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-02-21 04:24:33,271 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,273 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:33,273 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:33,276 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,277 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:33,364 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-02-21 04:24:33,365 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,367 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:33,367 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:33,367 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:33,367 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:33,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-02-21 04:24:33,483 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-02-21 04:24:33,483 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-02-21 04:24:33,484 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:33,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:33,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:33,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:33,491 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:33,492 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:33,492 INFO L791 eck$LassoCheckResult]: Stem: 27704#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 27524#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27240#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27241#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28417#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28418#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27376#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27377#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 27831#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 27666#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 27667#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27443#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27444#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27842#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28019#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28173#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28210#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27454#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27455#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28630#L1258-2 assume !(0 == ~T1_E~0); 27749#L1263-1 assume !(0 == ~T2_E~0); 27750#L1268-1 assume !(0 == ~T3_E~0); 28053#L1273-1 assume !(0 == ~T4_E~0); 28612#L1278-1 assume !(0 == ~T5_E~0); 28473#L1283-1 assume !(0 == ~T6_E~0); 28474#L1288-1 assume !(0 == ~T7_E~0); 28710#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28698#L1298-1 assume !(0 == ~T9_E~0); 28624#L1303-1 assume !(0 == ~T10_E~0); 27269#L1308-1 assume !(0 == ~T11_E~0); 27211#L1313-1 assume !(0 == ~T12_E~0); 27212#L1318-1 assume !(0 == ~T13_E~0); 27218#L1323-1 assume !(0 == ~E_1~0); 27219#L1328-1 assume !(0 == ~E_2~0); 27386#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28345#L1338-1 assume !(0 == ~E_4~0); 28346#L1343-1 assume !(0 == ~E_5~0); 28447#L1348-1 assume !(0 == ~E_6~0); 28733#L1353-1 assume !(0 == ~E_7~0); 28072#L1358-1 assume !(0 == ~E_8~0); 28073#L1363-1 assume !(0 == ~E_9~0); 28363#L1368-1 assume !(0 == ~E_10~0); 27048#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27049#L1378-1 assume !(0 == ~E_12~0); 27335#L1383-1 assume !(0 == ~E_13~0); 27336#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28079#L607 assume 1 == ~m_pc~0; 28080#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27406#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28445#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27999#L1560 assume !(0 != activate_threads_~tmp~1#1); 28000#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27231#L626 assume !(1 == ~t1_pc~0); 27232#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27500#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27501#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27670#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27131#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27132#L645 assume 1 == ~t2_pc~0; 27248#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27205#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27882#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27883#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27975#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27976#L664 assume 1 == ~t3_pc~0; 28732#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26972#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26973#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27631#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27632#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28640#L683 assume !(1 == ~t4_pc~0); 28195#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28147#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28148#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28182#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28306#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27925#L702 assume 1 == ~t5_pc~0; 27926#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27851#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28301#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28599#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28540#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27020#L721 assume !(1 == ~t6_pc~0); 26994#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26995#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27158#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27640#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27641#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28242#L740 assume 1 == ~t7_pc~0; 27069#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26882#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26883#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26872#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26873#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27576#L759 assume !(1 == ~t8_pc~0); 27577#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27606#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28299#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28300#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28431#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28709#L778 assume 1 == ~t9_pc~0; 28596#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27047#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26987#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26916#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26917#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27244#L797 assume !(1 == ~t10_pc~0); 27245#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27363#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28497#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27747#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27748#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28037#L816 assume 1 == ~t11_pc~0; 26952#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26953#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27708#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27647#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27648#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28172#L835 assume 1 == ~t12_pc~0; 28050#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27116#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27138#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27279#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27804#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27805#L854 assume !(1 == ~t13_pc~0); 27445#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27446#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27496#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27156#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27157#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28536#L1401 assume !(1 == ~M_E~0); 27635#L1401-2 assume !(1 == ~T1_E~0); 27636#L1406-1 assume !(1 == ~T2_E~0); 28231#L1411-1 assume !(1 == ~T3_E~0); 28232#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27898#L1421-1 assume !(1 == ~T5_E~0); 27441#L1426-1 assume !(1 == ~T6_E~0); 27442#L1431-1 assume !(1 == ~T7_E~0); 26990#L1436-1 assume !(1 == ~T8_E~0); 26991#L1441-1 assume !(1 == ~T9_E~0); 27738#L1446-1 assume !(1 == ~T10_E~0); 27739#L1451-1 assume !(1 == ~T11_E~0); 28444#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28098#L1461-1 assume !(1 == ~T13_E~0); 27659#L1466-1 assume !(1 == ~E_1~0); 27660#L1471-1 assume !(1 == ~E_2~0); 28429#L1476-1 assume !(1 == ~E_3~0); 28430#L1481-1 assume !(1 == ~E_4~0); 28578#L1486-1 assume !(1 == ~E_5~0); 27284#L1491-1 assume !(1 == ~E_6~0); 26924#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26925#L1501-1 assume !(1 == ~E_8~0); 27736#L1506-1 assume !(1 == ~E_9~0); 27737#L1511-1 assume !(1 == ~E_10~0); 27693#L1516-1 assume !(1 == ~E_11~0); 26868#L1521-1 assume !(1 == ~E_12~0); 26869#L1526-1 assume !(1 == ~E_13~0); 26923#L1531-1 assume { :end_inline_reset_delta_events } true; 27466#L1892-2 [2022-02-21 04:24:33,492 INFO L793 eck$LassoCheckResult]: Loop: 27466#L1892-2 assume !false; 28489#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28687#L1233 assume !false; 28670#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28002#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27982#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28140#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26966#L1046 assume !(0 != eval_~tmp~0#1); 26968#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27002#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28174#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28731#L1258-5 assume !(0 == ~T1_E~0); 27144#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27145#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28723#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28729#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28730#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27368#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27369#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28486#L1298-3 assume !(0 == ~T9_E~0); 28487#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28646#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28485#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27986#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27146#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27147#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28570#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27289#L1338-3 assume !(0 == ~E_4~0); 27290#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28402#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28575#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28576#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27942#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27502#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27503#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28259#L1378-3 assume !(0 == ~E_12~0); 28260#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28441#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28442#L607-42 assume 1 == ~m_pc~0; 28055#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27783#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27784#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27516#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27517#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28038#L626-42 assume 1 == ~t1_pc~0; 27600#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27601#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27905#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27906#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27180#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27181#L645-42 assume !(1 == ~t2_pc~0); 28380#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 28381#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28546#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27387#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26894#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26895#L664-42 assume 1 == ~t3_pc~0; 27697#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27422#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28673#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28208#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28209#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28374#L683-42 assume !(1 == ~t4_pc~0); 28082#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28083#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28215#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28635#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28636#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28480#L702-42 assume 1 == ~t5_pc~0; 27968#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27593#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27889#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28562#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 26910#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26911#L721-42 assume 1 == ~t6_pc~0; 27064#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27084#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27548#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28715#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27720#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27566#L740-42 assume !(1 == ~t7_pc~0); 27303#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 27304#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27845#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27700#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27701#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27974#L759-42 assume !(1 == ~t8_pc~0); 27824#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 27755#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27756#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27834#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27835#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27930#L778-42 assume 1 == ~t9_pc~0; 27767#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27769#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28179#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28084#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28085#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28142#L797-42 assume 1 == ~t10_pc~0; 27309#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27310#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28311#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28620#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28180#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28181#L816-42 assume 1 == ~t11_pc~0; 26858#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26859#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27401#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27402#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27481#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27482#L835-42 assume !(1 == ~t12_pc~0); 27778#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 27779#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27456#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27457#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28539#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28323#L854-42 assume 1 == ~t13_pc~0; 28324#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27400#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27010#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27011#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27657#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27658#L1401-3 assume !(1 == ~M_E~0); 28436#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27247#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27111#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27112#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27711#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27712#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27287#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27288#L1436-3 assume !(1 == ~T8_E~0); 26874#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26875#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28464#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27795#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27448#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 27449#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28726#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27388#L1476-3 assume !(1 == ~E_3~0); 27389#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27789#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27416#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27417#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27829#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27830#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28256#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28246#L1516-3 assume !(1 == ~E_11~0); 28247#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27946#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27947#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28341#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27223#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28116#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27757#L1911 assume !(0 == start_simulation_~tmp~3#1); 27758#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28280#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27348#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28218#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27052#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27053#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27282#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 27283#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27466#L1892-2 [2022-02-21 04:24:33,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:33,493 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2022-02-21 04:24:33,493 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:33,494 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393169931] [2022-02-21 04:24:33,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:33,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:33,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:33,519 INFO L290 TraceCheckUtils]: 0: Hoare triple {32588#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {32588#true} is VALID [2022-02-21 04:24:33,520 INFO L290 TraceCheckUtils]: 1: Hoare triple {32588#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {32590#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:33,520 INFO L290 TraceCheckUtils]: 2: Hoare triple {32590#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {32590#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:33,520 INFO L290 TraceCheckUtils]: 3: Hoare triple {32590#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {32590#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:33,521 INFO L290 TraceCheckUtils]: 4: Hoare triple {32590#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {32590#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:33,521 INFO L290 TraceCheckUtils]: 5: Hoare triple {32590#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {32590#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:33,521 INFO L290 TraceCheckUtils]: 6: Hoare triple {32590#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {32590#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:33,522 INFO L290 TraceCheckUtils]: 7: Hoare triple {32590#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {32590#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:33,522 INFO L290 TraceCheckUtils]: 8: Hoare triple {32590#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,522 INFO L290 TraceCheckUtils]: 9: Hoare triple {32589#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,522 INFO L290 TraceCheckUtils]: 10: Hoare triple {32589#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,522 INFO L290 TraceCheckUtils]: 11: Hoare triple {32589#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,522 INFO L290 TraceCheckUtils]: 12: Hoare triple {32589#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,523 INFO L290 TraceCheckUtils]: 13: Hoare triple {32589#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {32589#false} is VALID [2022-02-21 04:24:33,523 INFO L290 TraceCheckUtils]: 14: Hoare triple {32589#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,523 INFO L290 TraceCheckUtils]: 15: Hoare triple {32589#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,523 INFO L290 TraceCheckUtils]: 16: Hoare triple {32589#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,523 INFO L290 TraceCheckUtils]: 17: Hoare triple {32589#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,523 INFO L290 TraceCheckUtils]: 18: Hoare triple {32589#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {32589#false} is VALID [2022-02-21 04:24:33,523 INFO L290 TraceCheckUtils]: 19: Hoare triple {32589#false} assume 0 == ~M_E~0;~M_E~0 := 1; {32589#false} is VALID [2022-02-21 04:24:33,523 INFO L290 TraceCheckUtils]: 20: Hoare triple {32589#false} assume !(0 == ~T1_E~0); {32589#false} is VALID [2022-02-21 04:24:33,523 INFO L290 TraceCheckUtils]: 21: Hoare triple {32589#false} assume !(0 == ~T2_E~0); {32589#false} is VALID [2022-02-21 04:24:33,524 INFO L290 TraceCheckUtils]: 22: Hoare triple {32589#false} assume !(0 == ~T3_E~0); {32589#false} is VALID [2022-02-21 04:24:33,524 INFO L290 TraceCheckUtils]: 23: Hoare triple {32589#false} assume !(0 == ~T4_E~0); {32589#false} is VALID [2022-02-21 04:24:33,524 INFO L290 TraceCheckUtils]: 24: Hoare triple {32589#false} assume !(0 == ~T5_E~0); {32589#false} is VALID [2022-02-21 04:24:33,524 INFO L290 TraceCheckUtils]: 25: Hoare triple {32589#false} assume !(0 == ~T6_E~0); {32589#false} is VALID [2022-02-21 04:24:33,524 INFO L290 TraceCheckUtils]: 26: Hoare triple {32589#false} assume !(0 == ~T7_E~0); {32589#false} is VALID [2022-02-21 04:24:33,524 INFO L290 TraceCheckUtils]: 27: Hoare triple {32589#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {32589#false} is VALID [2022-02-21 04:24:33,524 INFO L290 TraceCheckUtils]: 28: Hoare triple {32589#false} assume !(0 == ~T9_E~0); {32589#false} is VALID [2022-02-21 04:24:33,524 INFO L290 TraceCheckUtils]: 29: Hoare triple {32589#false} assume !(0 == ~T10_E~0); {32589#false} is VALID [2022-02-21 04:24:33,524 INFO L290 TraceCheckUtils]: 30: Hoare triple {32589#false} assume !(0 == ~T11_E~0); {32589#false} is VALID [2022-02-21 04:24:33,525 INFO L290 TraceCheckUtils]: 31: Hoare triple {32589#false} assume !(0 == ~T12_E~0); {32589#false} is VALID [2022-02-21 04:24:33,525 INFO L290 TraceCheckUtils]: 32: Hoare triple {32589#false} assume !(0 == ~T13_E~0); {32589#false} is VALID [2022-02-21 04:24:33,525 INFO L290 TraceCheckUtils]: 33: Hoare triple {32589#false} assume !(0 == ~E_1~0); {32589#false} is VALID [2022-02-21 04:24:33,525 INFO L290 TraceCheckUtils]: 34: Hoare triple {32589#false} assume !(0 == ~E_2~0); {32589#false} is VALID [2022-02-21 04:24:33,525 INFO L290 TraceCheckUtils]: 35: Hoare triple {32589#false} assume 0 == ~E_3~0;~E_3~0 := 1; {32589#false} is VALID [2022-02-21 04:24:33,525 INFO L290 TraceCheckUtils]: 36: Hoare triple {32589#false} assume !(0 == ~E_4~0); {32589#false} is VALID [2022-02-21 04:24:33,525 INFO L290 TraceCheckUtils]: 37: Hoare triple {32589#false} assume !(0 == ~E_5~0); {32589#false} is VALID [2022-02-21 04:24:33,525 INFO L290 TraceCheckUtils]: 38: Hoare triple {32589#false} assume !(0 == ~E_6~0); {32589#false} is VALID [2022-02-21 04:24:33,525 INFO L290 TraceCheckUtils]: 39: Hoare triple {32589#false} assume !(0 == ~E_7~0); {32589#false} is VALID [2022-02-21 04:24:33,526 INFO L290 TraceCheckUtils]: 40: Hoare triple {32589#false} assume !(0 == ~E_8~0); {32589#false} is VALID [2022-02-21 04:24:33,526 INFO L290 TraceCheckUtils]: 41: Hoare triple {32589#false} assume !(0 == ~E_9~0); {32589#false} is VALID [2022-02-21 04:24:33,526 INFO L290 TraceCheckUtils]: 42: Hoare triple {32589#false} assume !(0 == ~E_10~0); {32589#false} is VALID [2022-02-21 04:24:33,526 INFO L290 TraceCheckUtils]: 43: Hoare triple {32589#false} assume 0 == ~E_11~0;~E_11~0 := 1; {32589#false} is VALID [2022-02-21 04:24:33,526 INFO L290 TraceCheckUtils]: 44: Hoare triple {32589#false} assume !(0 == ~E_12~0); {32589#false} is VALID [2022-02-21 04:24:33,526 INFO L290 TraceCheckUtils]: 45: Hoare triple {32589#false} assume !(0 == ~E_13~0); {32589#false} is VALID [2022-02-21 04:24:33,526 INFO L290 TraceCheckUtils]: 46: Hoare triple {32589#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32589#false} is VALID [2022-02-21 04:24:33,527 INFO L290 TraceCheckUtils]: 47: Hoare triple {32589#false} assume 1 == ~m_pc~0; {32589#false} is VALID [2022-02-21 04:24:33,527 INFO L290 TraceCheckUtils]: 48: Hoare triple {32589#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {32589#false} is VALID [2022-02-21 04:24:33,527 INFO L290 TraceCheckUtils]: 49: Hoare triple {32589#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32589#false} is VALID [2022-02-21 04:24:33,527 INFO L290 TraceCheckUtils]: 50: Hoare triple {32589#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32589#false} is VALID [2022-02-21 04:24:33,527 INFO L290 TraceCheckUtils]: 51: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp~1#1); {32589#false} is VALID [2022-02-21 04:24:33,527 INFO L290 TraceCheckUtils]: 52: Hoare triple {32589#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32589#false} is VALID [2022-02-21 04:24:33,527 INFO L290 TraceCheckUtils]: 53: Hoare triple {32589#false} assume !(1 == ~t1_pc~0); {32589#false} is VALID [2022-02-21 04:24:33,527 INFO L290 TraceCheckUtils]: 54: Hoare triple {32589#false} is_transmit1_triggered_~__retres1~1#1 := 0; {32589#false} is VALID [2022-02-21 04:24:33,528 INFO L290 TraceCheckUtils]: 55: Hoare triple {32589#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32589#false} is VALID [2022-02-21 04:24:33,528 INFO L290 TraceCheckUtils]: 56: Hoare triple {32589#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32589#false} is VALID [2022-02-21 04:24:33,528 INFO L290 TraceCheckUtils]: 57: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___0~0#1); {32589#false} is VALID [2022-02-21 04:24:33,528 INFO L290 TraceCheckUtils]: 58: Hoare triple {32589#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32589#false} is VALID [2022-02-21 04:24:33,528 INFO L290 TraceCheckUtils]: 59: Hoare triple {32589#false} assume 1 == ~t2_pc~0; {32589#false} is VALID [2022-02-21 04:24:33,528 INFO L290 TraceCheckUtils]: 60: Hoare triple {32589#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {32589#false} is VALID [2022-02-21 04:24:33,528 INFO L290 TraceCheckUtils]: 61: Hoare triple {32589#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32589#false} is VALID [2022-02-21 04:24:33,528 INFO L290 TraceCheckUtils]: 62: Hoare triple {32589#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32589#false} is VALID [2022-02-21 04:24:33,528 INFO L290 TraceCheckUtils]: 63: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___1~0#1); {32589#false} is VALID [2022-02-21 04:24:33,529 INFO L290 TraceCheckUtils]: 64: Hoare triple {32589#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32589#false} is VALID [2022-02-21 04:24:33,529 INFO L290 TraceCheckUtils]: 65: Hoare triple {32589#false} assume 1 == ~t3_pc~0; {32589#false} is VALID [2022-02-21 04:24:33,529 INFO L290 TraceCheckUtils]: 66: Hoare triple {32589#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {32589#false} is VALID [2022-02-21 04:24:33,529 INFO L290 TraceCheckUtils]: 67: Hoare triple {32589#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32589#false} is VALID [2022-02-21 04:24:33,529 INFO L290 TraceCheckUtils]: 68: Hoare triple {32589#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32589#false} is VALID [2022-02-21 04:24:33,529 INFO L290 TraceCheckUtils]: 69: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___2~0#1); {32589#false} is VALID [2022-02-21 04:24:33,529 INFO L290 TraceCheckUtils]: 70: Hoare triple {32589#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32589#false} is VALID [2022-02-21 04:24:33,529 INFO L290 TraceCheckUtils]: 71: Hoare triple {32589#false} assume !(1 == ~t4_pc~0); {32589#false} is VALID [2022-02-21 04:24:33,529 INFO L290 TraceCheckUtils]: 72: Hoare triple {32589#false} is_transmit4_triggered_~__retres1~4#1 := 0; {32589#false} is VALID [2022-02-21 04:24:33,530 INFO L290 TraceCheckUtils]: 73: Hoare triple {32589#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32589#false} is VALID [2022-02-21 04:24:33,530 INFO L290 TraceCheckUtils]: 74: Hoare triple {32589#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32589#false} is VALID [2022-02-21 04:24:33,530 INFO L290 TraceCheckUtils]: 75: Hoare triple {32589#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {32589#false} is VALID [2022-02-21 04:24:33,530 INFO L290 TraceCheckUtils]: 76: Hoare triple {32589#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32589#false} is VALID [2022-02-21 04:24:33,530 INFO L290 TraceCheckUtils]: 77: Hoare triple {32589#false} assume 1 == ~t5_pc~0; {32589#false} is VALID [2022-02-21 04:24:33,530 INFO L290 TraceCheckUtils]: 78: Hoare triple {32589#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {32589#false} is VALID [2022-02-21 04:24:33,530 INFO L290 TraceCheckUtils]: 79: Hoare triple {32589#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32589#false} is VALID [2022-02-21 04:24:33,530 INFO L290 TraceCheckUtils]: 80: Hoare triple {32589#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {32589#false} is VALID [2022-02-21 04:24:33,530 INFO L290 TraceCheckUtils]: 81: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___4~0#1); {32589#false} is VALID [2022-02-21 04:24:33,531 INFO L290 TraceCheckUtils]: 82: Hoare triple {32589#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32589#false} is VALID [2022-02-21 04:24:33,531 INFO L290 TraceCheckUtils]: 83: Hoare triple {32589#false} assume !(1 == ~t6_pc~0); {32589#false} is VALID [2022-02-21 04:24:33,531 INFO L290 TraceCheckUtils]: 84: Hoare triple {32589#false} is_transmit6_triggered_~__retres1~6#1 := 0; {32589#false} is VALID [2022-02-21 04:24:33,531 INFO L290 TraceCheckUtils]: 85: Hoare triple {32589#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32589#false} is VALID [2022-02-21 04:24:33,531 INFO L290 TraceCheckUtils]: 86: Hoare triple {32589#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {32589#false} is VALID [2022-02-21 04:24:33,531 INFO L290 TraceCheckUtils]: 87: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___5~0#1); {32589#false} is VALID [2022-02-21 04:24:33,531 INFO L290 TraceCheckUtils]: 88: Hoare triple {32589#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32589#false} is VALID [2022-02-21 04:24:33,531 INFO L290 TraceCheckUtils]: 89: Hoare triple {32589#false} assume 1 == ~t7_pc~0; {32589#false} is VALID [2022-02-21 04:24:33,532 INFO L290 TraceCheckUtils]: 90: Hoare triple {32589#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {32589#false} is VALID [2022-02-21 04:24:33,532 INFO L290 TraceCheckUtils]: 91: Hoare triple {32589#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32589#false} is VALID [2022-02-21 04:24:33,532 INFO L290 TraceCheckUtils]: 92: Hoare triple {32589#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {32589#false} is VALID [2022-02-21 04:24:33,532 INFO L290 TraceCheckUtils]: 93: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___6~0#1); {32589#false} is VALID [2022-02-21 04:24:33,532 INFO L290 TraceCheckUtils]: 94: Hoare triple {32589#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32589#false} is VALID [2022-02-21 04:24:33,532 INFO L290 TraceCheckUtils]: 95: Hoare triple {32589#false} assume !(1 == ~t8_pc~0); {32589#false} is VALID [2022-02-21 04:24:33,532 INFO L290 TraceCheckUtils]: 96: Hoare triple {32589#false} is_transmit8_triggered_~__retres1~8#1 := 0; {32589#false} is VALID [2022-02-21 04:24:33,532 INFO L290 TraceCheckUtils]: 97: Hoare triple {32589#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32589#false} is VALID [2022-02-21 04:24:33,532 INFO L290 TraceCheckUtils]: 98: Hoare triple {32589#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {32589#false} is VALID [2022-02-21 04:24:33,533 INFO L290 TraceCheckUtils]: 99: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___7~0#1); {32589#false} is VALID [2022-02-21 04:24:33,533 INFO L290 TraceCheckUtils]: 100: Hoare triple {32589#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {32589#false} is VALID [2022-02-21 04:24:33,533 INFO L290 TraceCheckUtils]: 101: Hoare triple {32589#false} assume 1 == ~t9_pc~0; {32589#false} is VALID [2022-02-21 04:24:33,533 INFO L290 TraceCheckUtils]: 102: Hoare triple {32589#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {32589#false} is VALID [2022-02-21 04:24:33,533 INFO L290 TraceCheckUtils]: 103: Hoare triple {32589#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {32589#false} is VALID [2022-02-21 04:24:33,533 INFO L290 TraceCheckUtils]: 104: Hoare triple {32589#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {32589#false} is VALID [2022-02-21 04:24:33,533 INFO L290 TraceCheckUtils]: 105: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___8~0#1); {32589#false} is VALID [2022-02-21 04:24:33,533 INFO L290 TraceCheckUtils]: 106: Hoare triple {32589#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {32589#false} is VALID [2022-02-21 04:24:33,534 INFO L290 TraceCheckUtils]: 107: Hoare triple {32589#false} assume !(1 == ~t10_pc~0); {32589#false} is VALID [2022-02-21 04:24:33,534 INFO L290 TraceCheckUtils]: 108: Hoare triple {32589#false} is_transmit10_triggered_~__retres1~10#1 := 0; {32589#false} is VALID [2022-02-21 04:24:33,534 INFO L290 TraceCheckUtils]: 109: Hoare triple {32589#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {32589#false} is VALID [2022-02-21 04:24:33,534 INFO L290 TraceCheckUtils]: 110: Hoare triple {32589#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {32589#false} is VALID [2022-02-21 04:24:33,534 INFO L290 TraceCheckUtils]: 111: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___9~0#1); {32589#false} is VALID [2022-02-21 04:24:33,534 INFO L290 TraceCheckUtils]: 112: Hoare triple {32589#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {32589#false} is VALID [2022-02-21 04:24:33,534 INFO L290 TraceCheckUtils]: 113: Hoare triple {32589#false} assume 1 == ~t11_pc~0; {32589#false} is VALID [2022-02-21 04:24:33,534 INFO L290 TraceCheckUtils]: 114: Hoare triple {32589#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {32589#false} is VALID [2022-02-21 04:24:33,535 INFO L290 TraceCheckUtils]: 115: Hoare triple {32589#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {32589#false} is VALID [2022-02-21 04:24:33,535 INFO L290 TraceCheckUtils]: 116: Hoare triple {32589#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {32589#false} is VALID [2022-02-21 04:24:33,535 INFO L290 TraceCheckUtils]: 117: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___10~0#1); {32589#false} is VALID [2022-02-21 04:24:33,535 INFO L290 TraceCheckUtils]: 118: Hoare triple {32589#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {32589#false} is VALID [2022-02-21 04:24:33,535 INFO L290 TraceCheckUtils]: 119: Hoare triple {32589#false} assume 1 == ~t12_pc~0; {32589#false} is VALID [2022-02-21 04:24:33,535 INFO L290 TraceCheckUtils]: 120: Hoare triple {32589#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {32589#false} is VALID [2022-02-21 04:24:33,535 INFO L290 TraceCheckUtils]: 121: Hoare triple {32589#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {32589#false} is VALID [2022-02-21 04:24:33,535 INFO L290 TraceCheckUtils]: 122: Hoare triple {32589#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {32589#false} is VALID [2022-02-21 04:24:33,536 INFO L290 TraceCheckUtils]: 123: Hoare triple {32589#false} assume !(0 != activate_threads_~tmp___11~0#1); {32589#false} is VALID [2022-02-21 04:24:33,536 INFO L290 TraceCheckUtils]: 124: Hoare triple {32589#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {32589#false} is VALID [2022-02-21 04:24:33,536 INFO L290 TraceCheckUtils]: 125: Hoare triple {32589#false} assume !(1 == ~t13_pc~0); {32589#false} is VALID [2022-02-21 04:24:33,536 INFO L290 TraceCheckUtils]: 126: Hoare triple {32589#false} is_transmit13_triggered_~__retres1~13#1 := 0; {32589#false} is VALID [2022-02-21 04:24:33,536 INFO L290 TraceCheckUtils]: 127: Hoare triple {32589#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {32589#false} is VALID [2022-02-21 04:24:33,536 INFO L290 TraceCheckUtils]: 128: Hoare triple {32589#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {32589#false} is VALID [2022-02-21 04:24:33,536 INFO L290 TraceCheckUtils]: 129: Hoare triple {32589#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {32589#false} is VALID [2022-02-21 04:24:33,536 INFO L290 TraceCheckUtils]: 130: Hoare triple {32589#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32589#false} is VALID [2022-02-21 04:24:33,537 INFO L290 TraceCheckUtils]: 131: Hoare triple {32589#false} assume !(1 == ~M_E~0); {32589#false} is VALID [2022-02-21 04:24:33,537 INFO L290 TraceCheckUtils]: 132: Hoare triple {32589#false} assume !(1 == ~T1_E~0); {32589#false} is VALID [2022-02-21 04:24:33,537 INFO L290 TraceCheckUtils]: 133: Hoare triple {32589#false} assume !(1 == ~T2_E~0); {32589#false} is VALID [2022-02-21 04:24:33,537 INFO L290 TraceCheckUtils]: 134: Hoare triple {32589#false} assume !(1 == ~T3_E~0); {32589#false} is VALID [2022-02-21 04:24:33,537 INFO L290 TraceCheckUtils]: 135: Hoare triple {32589#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,537 INFO L290 TraceCheckUtils]: 136: Hoare triple {32589#false} assume !(1 == ~T5_E~0); {32589#false} is VALID [2022-02-21 04:24:33,537 INFO L290 TraceCheckUtils]: 137: Hoare triple {32589#false} assume !(1 == ~T6_E~0); {32589#false} is VALID [2022-02-21 04:24:33,537 INFO L290 TraceCheckUtils]: 138: Hoare triple {32589#false} assume !(1 == ~T7_E~0); {32589#false} is VALID [2022-02-21 04:24:33,537 INFO L290 TraceCheckUtils]: 139: Hoare triple {32589#false} assume !(1 == ~T8_E~0); {32589#false} is VALID [2022-02-21 04:24:33,538 INFO L290 TraceCheckUtils]: 140: Hoare triple {32589#false} assume !(1 == ~T9_E~0); {32589#false} is VALID [2022-02-21 04:24:33,538 INFO L290 TraceCheckUtils]: 141: Hoare triple {32589#false} assume !(1 == ~T10_E~0); {32589#false} is VALID [2022-02-21 04:24:33,538 INFO L290 TraceCheckUtils]: 142: Hoare triple {32589#false} assume !(1 == ~T11_E~0); {32589#false} is VALID [2022-02-21 04:24:33,538 INFO L290 TraceCheckUtils]: 143: Hoare triple {32589#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,538 INFO L290 TraceCheckUtils]: 144: Hoare triple {32589#false} assume !(1 == ~T13_E~0); {32589#false} is VALID [2022-02-21 04:24:33,538 INFO L290 TraceCheckUtils]: 145: Hoare triple {32589#false} assume !(1 == ~E_1~0); {32589#false} is VALID [2022-02-21 04:24:33,538 INFO L290 TraceCheckUtils]: 146: Hoare triple {32589#false} assume !(1 == ~E_2~0); {32589#false} is VALID [2022-02-21 04:24:33,538 INFO L290 TraceCheckUtils]: 147: Hoare triple {32589#false} assume !(1 == ~E_3~0); {32589#false} is VALID [2022-02-21 04:24:33,539 INFO L290 TraceCheckUtils]: 148: Hoare triple {32589#false} assume !(1 == ~E_4~0); {32589#false} is VALID [2022-02-21 04:24:33,539 INFO L290 TraceCheckUtils]: 149: Hoare triple {32589#false} assume !(1 == ~E_5~0); {32589#false} is VALID [2022-02-21 04:24:33,539 INFO L290 TraceCheckUtils]: 150: Hoare triple {32589#false} assume !(1 == ~E_6~0); {32589#false} is VALID [2022-02-21 04:24:33,539 INFO L290 TraceCheckUtils]: 151: Hoare triple {32589#false} assume 1 == ~E_7~0;~E_7~0 := 2; {32589#false} is VALID [2022-02-21 04:24:33,539 INFO L290 TraceCheckUtils]: 152: Hoare triple {32589#false} assume !(1 == ~E_8~0); {32589#false} is VALID [2022-02-21 04:24:33,539 INFO L290 TraceCheckUtils]: 153: Hoare triple {32589#false} assume !(1 == ~E_9~0); {32589#false} is VALID [2022-02-21 04:24:33,539 INFO L290 TraceCheckUtils]: 154: Hoare triple {32589#false} assume !(1 == ~E_10~0); {32589#false} is VALID [2022-02-21 04:24:33,539 INFO L290 TraceCheckUtils]: 155: Hoare triple {32589#false} assume !(1 == ~E_11~0); {32589#false} is VALID [2022-02-21 04:24:33,540 INFO L290 TraceCheckUtils]: 156: Hoare triple {32589#false} assume !(1 == ~E_12~0); {32589#false} is VALID [2022-02-21 04:24:33,540 INFO L290 TraceCheckUtils]: 157: Hoare triple {32589#false} assume !(1 == ~E_13~0); {32589#false} is VALID [2022-02-21 04:24:33,540 INFO L290 TraceCheckUtils]: 158: Hoare triple {32589#false} assume { :end_inline_reset_delta_events } true; {32589#false} is VALID [2022-02-21 04:24:33,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:33,540 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:33,540 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393169931] [2022-02-21 04:24:33,541 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393169931] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:33,541 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:33,541 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:33,541 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352774928] [2022-02-21 04:24:33,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:33,541 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:33,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:33,542 INFO L85 PathProgramCache]: Analyzing trace with hash -744572368, now seen corresponding path program 1 times [2022-02-21 04:24:33,542 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:33,542 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935634435] [2022-02-21 04:24:33,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:33,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:33,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:33,571 INFO L290 TraceCheckUtils]: 0: Hoare triple {32591#true} assume !false; {32591#true} is VALID [2022-02-21 04:24:33,572 INFO L290 TraceCheckUtils]: 1: Hoare triple {32591#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {32591#true} is VALID [2022-02-21 04:24:33,572 INFO L290 TraceCheckUtils]: 2: Hoare triple {32591#true} assume !false; {32591#true} is VALID [2022-02-21 04:24:33,572 INFO L290 TraceCheckUtils]: 3: Hoare triple {32591#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {32591#true} is VALID [2022-02-21 04:24:33,572 INFO L290 TraceCheckUtils]: 4: Hoare triple {32591#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {32591#true} is VALID [2022-02-21 04:24:33,572 INFO L290 TraceCheckUtils]: 5: Hoare triple {32591#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {32591#true} is VALID [2022-02-21 04:24:33,572 INFO L290 TraceCheckUtils]: 6: Hoare triple {32591#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {32591#true} is VALID [2022-02-21 04:24:33,572 INFO L290 TraceCheckUtils]: 7: Hoare triple {32591#true} assume !(0 != eval_~tmp~0#1); {32591#true} is VALID [2022-02-21 04:24:33,572 INFO L290 TraceCheckUtils]: 8: Hoare triple {32591#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {32591#true} is VALID [2022-02-21 04:24:33,584 INFO L290 TraceCheckUtils]: 9: Hoare triple {32591#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {32591#true} is VALID [2022-02-21 04:24:33,594 INFO L290 TraceCheckUtils]: 10: Hoare triple {32591#true} assume 0 == ~M_E~0;~M_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,594 INFO L290 TraceCheckUtils]: 11: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,595 INFO L290 TraceCheckUtils]: 12: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,595 INFO L290 TraceCheckUtils]: 13: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,595 INFO L290 TraceCheckUtils]: 14: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,596 INFO L290 TraceCheckUtils]: 15: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,596 INFO L290 TraceCheckUtils]: 16: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,596 INFO L290 TraceCheckUtils]: 17: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,597 INFO L290 TraceCheckUtils]: 18: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,597 INFO L290 TraceCheckUtils]: 19: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,597 INFO L290 TraceCheckUtils]: 20: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,597 INFO L290 TraceCheckUtils]: 21: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,598 INFO L290 TraceCheckUtils]: 22: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,598 INFO L290 TraceCheckUtils]: 23: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,598 INFO L290 TraceCheckUtils]: 24: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,599 INFO L290 TraceCheckUtils]: 25: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,599 INFO L290 TraceCheckUtils]: 26: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,599 INFO L290 TraceCheckUtils]: 27: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,600 INFO L290 TraceCheckUtils]: 28: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,600 INFO L290 TraceCheckUtils]: 29: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,600 INFO L290 TraceCheckUtils]: 30: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,600 INFO L290 TraceCheckUtils]: 31: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,601 INFO L290 TraceCheckUtils]: 32: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,601 INFO L290 TraceCheckUtils]: 33: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,601 INFO L290 TraceCheckUtils]: 34: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,602 INFO L290 TraceCheckUtils]: 35: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,602 INFO L290 TraceCheckUtils]: 36: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,602 INFO L290 TraceCheckUtils]: 37: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,603 INFO L290 TraceCheckUtils]: 38: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,603 INFO L290 TraceCheckUtils]: 39: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,603 INFO L290 TraceCheckUtils]: 40: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,603 INFO L290 TraceCheckUtils]: 41: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,604 INFO L290 TraceCheckUtils]: 42: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,604 INFO L290 TraceCheckUtils]: 43: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,604 INFO L290 TraceCheckUtils]: 44: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,605 INFO L290 TraceCheckUtils]: 45: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,605 INFO L290 TraceCheckUtils]: 46: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,605 INFO L290 TraceCheckUtils]: 47: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,606 INFO L290 TraceCheckUtils]: 48: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,606 INFO L290 TraceCheckUtils]: 49: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,606 INFO L290 TraceCheckUtils]: 50: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,606 INFO L290 TraceCheckUtils]: 51: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,607 INFO L290 TraceCheckUtils]: 52: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,607 INFO L290 TraceCheckUtils]: 53: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,607 INFO L290 TraceCheckUtils]: 54: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,608 INFO L290 TraceCheckUtils]: 55: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,608 INFO L290 TraceCheckUtils]: 56: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,608 INFO L290 TraceCheckUtils]: 57: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,609 INFO L290 TraceCheckUtils]: 58: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,609 INFO L290 TraceCheckUtils]: 59: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,609 INFO L290 TraceCheckUtils]: 60: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,609 INFO L290 TraceCheckUtils]: 61: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,610 INFO L290 TraceCheckUtils]: 62: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,610 INFO L290 TraceCheckUtils]: 63: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,610 INFO L290 TraceCheckUtils]: 64: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,611 INFO L290 TraceCheckUtils]: 65: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,611 INFO L290 TraceCheckUtils]: 66: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,611 INFO L290 TraceCheckUtils]: 67: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,612 INFO L290 TraceCheckUtils]: 68: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,612 INFO L290 TraceCheckUtils]: 69: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,612 INFO L290 TraceCheckUtils]: 70: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,613 INFO L290 TraceCheckUtils]: 71: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,613 INFO L290 TraceCheckUtils]: 72: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,613 INFO L290 TraceCheckUtils]: 73: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,614 INFO L290 TraceCheckUtils]: 74: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,614 INFO L290 TraceCheckUtils]: 75: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,615 INFO L290 TraceCheckUtils]: 76: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,615 INFO L290 TraceCheckUtils]: 77: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,615 INFO L290 TraceCheckUtils]: 78: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,616 INFO L290 TraceCheckUtils]: 79: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,616 INFO L290 TraceCheckUtils]: 80: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,616 INFO L290 TraceCheckUtils]: 81: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,617 INFO L290 TraceCheckUtils]: 82: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,617 INFO L290 TraceCheckUtils]: 83: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,617 INFO L290 TraceCheckUtils]: 84: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,617 INFO L290 TraceCheckUtils]: 85: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,618 INFO L290 TraceCheckUtils]: 86: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,618 INFO L290 TraceCheckUtils]: 87: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,618 INFO L290 TraceCheckUtils]: 88: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,619 INFO L290 TraceCheckUtils]: 89: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,619 INFO L290 TraceCheckUtils]: 90: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,619 INFO L290 TraceCheckUtils]: 91: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,620 INFO L290 TraceCheckUtils]: 92: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,620 INFO L290 TraceCheckUtils]: 93: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,620 INFO L290 TraceCheckUtils]: 94: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,621 INFO L290 TraceCheckUtils]: 95: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,621 INFO L290 TraceCheckUtils]: 96: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,621 INFO L290 TraceCheckUtils]: 97: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,621 INFO L290 TraceCheckUtils]: 98: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,622 INFO L290 TraceCheckUtils]: 99: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,622 INFO L290 TraceCheckUtils]: 100: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,622 INFO L290 TraceCheckUtils]: 101: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,623 INFO L290 TraceCheckUtils]: 102: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,623 INFO L290 TraceCheckUtils]: 103: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,623 INFO L290 TraceCheckUtils]: 104: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,624 INFO L290 TraceCheckUtils]: 105: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,624 INFO L290 TraceCheckUtils]: 106: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,624 INFO L290 TraceCheckUtils]: 107: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,625 INFO L290 TraceCheckUtils]: 108: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,625 INFO L290 TraceCheckUtils]: 109: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,625 INFO L290 TraceCheckUtils]: 110: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,625 INFO L290 TraceCheckUtils]: 111: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,626 INFO L290 TraceCheckUtils]: 112: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,626 INFO L290 TraceCheckUtils]: 113: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,626 INFO L290 TraceCheckUtils]: 114: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,627 INFO L290 TraceCheckUtils]: 115: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,627 INFO L290 TraceCheckUtils]: 116: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,627 INFO L290 TraceCheckUtils]: 117: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,628 INFO L290 TraceCheckUtils]: 118: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,628 INFO L290 TraceCheckUtils]: 119: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,628 INFO L290 TraceCheckUtils]: 120: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,628 INFO L290 TraceCheckUtils]: 121: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32593#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:33,629 INFO L290 TraceCheckUtils]: 122: Hoare triple {32593#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {32592#false} is VALID [2022-02-21 04:24:33,629 INFO L290 TraceCheckUtils]: 123: Hoare triple {32592#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,629 INFO L290 TraceCheckUtils]: 124: Hoare triple {32592#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,629 INFO L290 TraceCheckUtils]: 125: Hoare triple {32592#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,629 INFO L290 TraceCheckUtils]: 126: Hoare triple {32592#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,629 INFO L290 TraceCheckUtils]: 127: Hoare triple {32592#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,629 INFO L290 TraceCheckUtils]: 128: Hoare triple {32592#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,630 INFO L290 TraceCheckUtils]: 129: Hoare triple {32592#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,630 INFO L290 TraceCheckUtils]: 130: Hoare triple {32592#false} assume !(1 == ~T8_E~0); {32592#false} is VALID [2022-02-21 04:24:33,630 INFO L290 TraceCheckUtils]: 131: Hoare triple {32592#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,630 INFO L290 TraceCheckUtils]: 132: Hoare triple {32592#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,630 INFO L290 TraceCheckUtils]: 133: Hoare triple {32592#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,630 INFO L290 TraceCheckUtils]: 134: Hoare triple {32592#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,630 INFO L290 TraceCheckUtils]: 135: Hoare triple {32592#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,630 INFO L290 TraceCheckUtils]: 136: Hoare triple {32592#false} assume 1 == ~E_1~0;~E_1~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,631 INFO L290 TraceCheckUtils]: 137: Hoare triple {32592#false} assume 1 == ~E_2~0;~E_2~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,631 INFO L290 TraceCheckUtils]: 138: Hoare triple {32592#false} assume !(1 == ~E_3~0); {32592#false} is VALID [2022-02-21 04:24:33,631 INFO L290 TraceCheckUtils]: 139: Hoare triple {32592#false} assume 1 == ~E_4~0;~E_4~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,631 INFO L290 TraceCheckUtils]: 140: Hoare triple {32592#false} assume 1 == ~E_5~0;~E_5~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,631 INFO L290 TraceCheckUtils]: 141: Hoare triple {32592#false} assume 1 == ~E_6~0;~E_6~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,631 INFO L290 TraceCheckUtils]: 142: Hoare triple {32592#false} assume 1 == ~E_7~0;~E_7~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,631 INFO L290 TraceCheckUtils]: 143: Hoare triple {32592#false} assume 1 == ~E_8~0;~E_8~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,631 INFO L290 TraceCheckUtils]: 144: Hoare triple {32592#false} assume 1 == ~E_9~0;~E_9~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,631 INFO L290 TraceCheckUtils]: 145: Hoare triple {32592#false} assume 1 == ~E_10~0;~E_10~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,632 INFO L290 TraceCheckUtils]: 146: Hoare triple {32592#false} assume !(1 == ~E_11~0); {32592#false} is VALID [2022-02-21 04:24:33,632 INFO L290 TraceCheckUtils]: 147: Hoare triple {32592#false} assume 1 == ~E_12~0;~E_12~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,632 INFO L290 TraceCheckUtils]: 148: Hoare triple {32592#false} assume 1 == ~E_13~0;~E_13~0 := 2; {32592#false} is VALID [2022-02-21 04:24:33,632 INFO L290 TraceCheckUtils]: 149: Hoare triple {32592#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {32592#false} is VALID [2022-02-21 04:24:33,632 INFO L290 TraceCheckUtils]: 150: Hoare triple {32592#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {32592#false} is VALID [2022-02-21 04:24:33,632 INFO L290 TraceCheckUtils]: 151: Hoare triple {32592#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {32592#false} is VALID [2022-02-21 04:24:33,632 INFO L290 TraceCheckUtils]: 152: Hoare triple {32592#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {32592#false} is VALID [2022-02-21 04:24:33,632 INFO L290 TraceCheckUtils]: 153: Hoare triple {32592#false} assume !(0 == start_simulation_~tmp~3#1); {32592#false} is VALID [2022-02-21 04:24:33,633 INFO L290 TraceCheckUtils]: 154: Hoare triple {32592#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {32592#false} is VALID [2022-02-21 04:24:33,633 INFO L290 TraceCheckUtils]: 155: Hoare triple {32592#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {32592#false} is VALID [2022-02-21 04:24:33,633 INFO L290 TraceCheckUtils]: 156: Hoare triple {32592#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {32592#false} is VALID [2022-02-21 04:24:33,633 INFO L290 TraceCheckUtils]: 157: Hoare triple {32592#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {32592#false} is VALID [2022-02-21 04:24:33,633 INFO L290 TraceCheckUtils]: 158: Hoare triple {32592#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {32592#false} is VALID [2022-02-21 04:24:33,633 INFO L290 TraceCheckUtils]: 159: Hoare triple {32592#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {32592#false} is VALID [2022-02-21 04:24:33,633 INFO L290 TraceCheckUtils]: 160: Hoare triple {32592#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {32592#false} is VALID [2022-02-21 04:24:33,633 INFO L290 TraceCheckUtils]: 161: Hoare triple {32592#false} assume !(0 != start_simulation_~tmp___0~1#1); {32592#false} is VALID [2022-02-21 04:24:33,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:33,634 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:33,634 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935634435] [2022-02-21 04:24:33,634 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935634435] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:33,634 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:33,634 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:33,635 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923023837] [2022-02-21 04:24:33,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:33,635 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:33,635 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:33,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:33,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:33,636 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:34,991 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-02-21 04:24:34,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:34,992 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,087 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:35,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:35,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:35,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-02-21 04:24:35,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:35,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:35,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:35,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:35,252 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-02-21 04:24:35,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:35,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:35,268 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:35,270 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2831 transitions. Second operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,271 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2831 transitions. Second operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,273 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. Second operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:35,350 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-02-21 04:24:35,350 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:35,352 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:35,352 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:35,354 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2831 transitions. [2022-02-21 04:24:35,356 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2831 transitions. [2022-02-21 04:24:35,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:35,439 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-02-21 04:24:35,439 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:35,440 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:35,441 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:35,441 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:35,441 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:35,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-02-21 04:24:35,526 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-02-21 04:24:35,526 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-02-21 04:24:35,526 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:35,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:35,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:35,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:35,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:35,531 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:35,531 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:35,531 INFO L791 eck$LassoCheckResult]: Stem: 35369#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35189#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34905#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34906#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36082#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36083#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35041#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35042#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35500#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 35331#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 35332#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 35108#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 35109#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35507#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35684#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35839#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35875#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35121#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35122#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36295#L1258-2 assume !(0 == ~T1_E~0); 35414#L1263-1 assume !(0 == ~T2_E~0); 35415#L1268-1 assume !(0 == ~T3_E~0); 35718#L1273-1 assume !(0 == ~T4_E~0); 36277#L1278-1 assume !(0 == ~T5_E~0); 36138#L1283-1 assume !(0 == ~T6_E~0); 36139#L1288-1 assume !(0 == ~T7_E~0); 36376#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36363#L1298-1 assume !(0 == ~T9_E~0); 36289#L1303-1 assume !(0 == ~T10_E~0); 34934#L1308-1 assume !(0 == ~T11_E~0); 34879#L1313-1 assume !(0 == ~T12_E~0); 34880#L1318-1 assume !(0 == ~T13_E~0); 34885#L1323-1 assume !(0 == ~E_1~0); 34886#L1328-1 assume !(0 == ~E_2~0); 35051#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36010#L1338-1 assume !(0 == ~E_4~0); 36011#L1343-1 assume !(0 == ~E_5~0); 36112#L1348-1 assume !(0 == ~E_6~0); 36398#L1353-1 assume !(0 == ~E_7~0); 35737#L1358-1 assume !(0 == ~E_8~0); 35738#L1363-1 assume !(0 == ~E_9~0); 36029#L1368-1 assume !(0 == ~E_10~0); 34713#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34714#L1378-1 assume !(0 == ~E_12~0); 35002#L1383-1 assume !(0 == ~E_13~0); 35003#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35744#L607 assume 1 == ~m_pc~0; 35745#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35071#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36110#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35664#L1560 assume !(0 != activate_threads_~tmp~1#1); 35665#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34896#L626 assume !(1 == ~t1_pc~0); 34897#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35167#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35168#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35337#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34799#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34800#L645 assume 1 == ~t2_pc~0; 34913#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34870#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35550#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35551#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35640#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35641#L664 assume 1 == ~t3_pc~0; 36397#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34641#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34642#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35296#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35297#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36305#L683 assume !(1 == ~t4_pc~0); 35860#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35812#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35813#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35847#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35971#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35594#L702 assume 1 == ~t5_pc~0; 35595#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35517#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35966#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36265#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36206#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34685#L721 assume !(1 == ~t6_pc~0); 34659#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34660#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34823#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35305#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35306#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35907#L740 assume 1 == ~t7_pc~0; 34734#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34547#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34548#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34537#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34538#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35242#L759 assume !(1 == ~t8_pc~0); 35243#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35271#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35964#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35965#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36096#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36374#L778 assume 1 == ~t9_pc~0; 36263#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34712#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34652#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34581#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34582#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34910#L797 assume !(1 == ~t10_pc~0); 34911#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35028#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36162#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35412#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35413#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35702#L816 assume 1 == ~t11_pc~0; 34617#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34618#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35375#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35312#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35313#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35837#L835 assume 1 == ~t12_pc~0; 35715#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34781#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34803#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34944#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35469#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35470#L854 assume !(1 == ~t13_pc~0); 35110#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35111#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35163#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34821#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34822#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36201#L1401 assume !(1 == ~M_E~0); 35300#L1401-2 assume !(1 == ~T1_E~0); 35301#L1406-1 assume !(1 == ~T2_E~0); 35896#L1411-1 assume !(1 == ~T3_E~0); 35897#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35563#L1421-1 assume !(1 == ~T5_E~0); 35106#L1426-1 assume !(1 == ~T6_E~0); 35107#L1431-1 assume !(1 == ~T7_E~0); 34655#L1436-1 assume !(1 == ~T8_E~0); 34656#L1441-1 assume !(1 == ~T9_E~0); 35405#L1446-1 assume !(1 == ~T10_E~0); 35406#L1451-1 assume !(1 == ~T11_E~0); 36109#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35763#L1461-1 assume !(1 == ~T13_E~0); 35324#L1466-1 assume !(1 == ~E_1~0); 35325#L1471-1 assume !(1 == ~E_2~0); 36094#L1476-1 assume !(1 == ~E_3~0); 36095#L1481-1 assume !(1 == ~E_4~0); 36243#L1486-1 assume !(1 == ~E_5~0); 34951#L1491-1 assume !(1 == ~E_6~0); 34589#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34590#L1501-1 assume !(1 == ~E_8~0); 35401#L1506-1 assume !(1 == ~E_9~0); 35402#L1511-1 assume !(1 == ~E_10~0); 35358#L1516-1 assume !(1 == ~E_11~0); 34535#L1521-1 assume !(1 == ~E_12~0); 34536#L1526-1 assume !(1 == ~E_13~0); 34588#L1531-1 assume { :end_inline_reset_delta_events } true; 35132#L1892-2 [2022-02-21 04:24:35,532 INFO L793 eck$LassoCheckResult]: Loop: 35132#L1892-2 assume !false; 36154#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36352#L1233 assume !false; 36335#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35667#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35647#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35805#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34631#L1046 assume !(0 != eval_~tmp~0#1); 34633#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34667#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35838#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36396#L1258-5 assume !(0 == ~T1_E~0); 34809#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34810#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36388#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36394#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36395#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35033#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35034#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36151#L1298-3 assume !(0 == ~T9_E~0); 36152#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36311#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36150#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35651#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34811#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34812#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36235#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34954#L1338-3 assume !(0 == ~E_4~0); 34955#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36067#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36240#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36241#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35607#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35165#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35166#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35924#L1378-3 assume !(0 == ~E_12~0); 35925#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36106#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36107#L607-42 assume 1 == ~m_pc~0; 35720#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35448#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35449#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35181#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35182#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35703#L626-42 assume 1 == ~t1_pc~0; 35265#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35266#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35570#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35571#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34845#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34846#L645-42 assume 1 == ~t2_pc~0; 36304#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36046#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36211#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35052#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34559#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34560#L664-42 assume 1 == ~t3_pc~0; 35362#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35087#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36338#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35873#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35874#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36039#L683-42 assume !(1 == ~t4_pc~0); 35747#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35748#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35880#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36300#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36301#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36145#L702-42 assume 1 == ~t5_pc~0; 35633#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35258#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35554#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36227#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 34575#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34576#L721-42 assume 1 == ~t6_pc~0; 34729#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34749#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35213#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36380#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35385#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35231#L740-42 assume 1 == ~t7_pc~0; 35232#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34969#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35510#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35365#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35366#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35639#L759-42 assume 1 == ~t8_pc~0; 35488#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35420#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35421#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35498#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35499#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35593#L778-42 assume 1 == ~t9_pc~0; 35432#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35434#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35844#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35749#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35750#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35807#L797-42 assume !(1 == ~t10_pc~0); 34976#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 34975#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35976#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36285#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35845#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35846#L816-42 assume 1 == ~t11_pc~0; 34523#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34524#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35066#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35067#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35146#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35147#L835-42 assume !(1 == ~t12_pc~0); 35443#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 35444#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35119#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35120#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36204#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35988#L854-42 assume 1 == ~t13_pc~0; 35989#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35065#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34675#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34676#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35322#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35323#L1401-3 assume !(1 == ~M_E~0); 36101#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34909#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34776#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34777#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35376#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35377#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34952#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34953#L1436-3 assume !(1 == ~T8_E~0); 34539#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34540#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36129#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35460#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35113#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 35114#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36391#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35053#L1476-3 assume !(1 == ~E_3~0); 35054#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35454#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35081#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35082#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35494#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35495#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35921#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35911#L1516-3 assume !(1 == ~E_11~0); 35912#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35611#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35612#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36006#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34888#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35781#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35422#L1911 assume !(0 == start_simulation_~tmp~3#1); 35423#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35945#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35013#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35883#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34717#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34718#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34947#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34948#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35132#L1892-2 [2022-02-21 04:24:35,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:35,532 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2022-02-21 04:24:35,532 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:35,532 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193228377] [2022-02-21 04:24:35,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:35,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:35,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:35,560 INFO L290 TraceCheckUtils]: 0: Hoare triple {40253#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {40253#true} is VALID [2022-02-21 04:24:35,560 INFO L290 TraceCheckUtils]: 1: Hoare triple {40253#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {40255#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:35,560 INFO L290 TraceCheckUtils]: 2: Hoare triple {40255#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {40255#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:35,560 INFO L290 TraceCheckUtils]: 3: Hoare triple {40255#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {40255#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:35,561 INFO L290 TraceCheckUtils]: 4: Hoare triple {40255#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {40255#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:35,561 INFO L290 TraceCheckUtils]: 5: Hoare triple {40255#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {40255#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:35,561 INFO L290 TraceCheckUtils]: 6: Hoare triple {40255#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {40255#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:35,561 INFO L290 TraceCheckUtils]: 7: Hoare triple {40255#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {40255#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 8: Hoare triple {40255#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {40255#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 9: Hoare triple {40255#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 10: Hoare triple {40254#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 11: Hoare triple {40254#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 12: Hoare triple {40254#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 13: Hoare triple {40254#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 14: Hoare triple {40254#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 15: Hoare triple {40254#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 16: Hoare triple {40254#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 17: Hoare triple {40254#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 18: Hoare triple {40254#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {40254#false} is VALID [2022-02-21 04:24:35,562 INFO L290 TraceCheckUtils]: 19: Hoare triple {40254#false} assume 0 == ~M_E~0;~M_E~0 := 1; {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 20: Hoare triple {40254#false} assume !(0 == ~T1_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 21: Hoare triple {40254#false} assume !(0 == ~T2_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 22: Hoare triple {40254#false} assume !(0 == ~T3_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 23: Hoare triple {40254#false} assume !(0 == ~T4_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 24: Hoare triple {40254#false} assume !(0 == ~T5_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 25: Hoare triple {40254#false} assume !(0 == ~T6_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 26: Hoare triple {40254#false} assume !(0 == ~T7_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 27: Hoare triple {40254#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 28: Hoare triple {40254#false} assume !(0 == ~T9_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 29: Hoare triple {40254#false} assume !(0 == ~T10_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 30: Hoare triple {40254#false} assume !(0 == ~T11_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 31: Hoare triple {40254#false} assume !(0 == ~T12_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 32: Hoare triple {40254#false} assume !(0 == ~T13_E~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 33: Hoare triple {40254#false} assume !(0 == ~E_1~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 34: Hoare triple {40254#false} assume !(0 == ~E_2~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 35: Hoare triple {40254#false} assume 0 == ~E_3~0;~E_3~0 := 1; {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 36: Hoare triple {40254#false} assume !(0 == ~E_4~0); {40254#false} is VALID [2022-02-21 04:24:35,563 INFO L290 TraceCheckUtils]: 37: Hoare triple {40254#false} assume !(0 == ~E_5~0); {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 38: Hoare triple {40254#false} assume !(0 == ~E_6~0); {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 39: Hoare triple {40254#false} assume !(0 == ~E_7~0); {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 40: Hoare triple {40254#false} assume !(0 == ~E_8~0); {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 41: Hoare triple {40254#false} assume !(0 == ~E_9~0); {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 42: Hoare triple {40254#false} assume !(0 == ~E_10~0); {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 43: Hoare triple {40254#false} assume 0 == ~E_11~0;~E_11~0 := 1; {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 44: Hoare triple {40254#false} assume !(0 == ~E_12~0); {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 45: Hoare triple {40254#false} assume !(0 == ~E_13~0); {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 46: Hoare triple {40254#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 47: Hoare triple {40254#false} assume 1 == ~m_pc~0; {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 48: Hoare triple {40254#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 49: Hoare triple {40254#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 50: Hoare triple {40254#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 51: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp~1#1); {40254#false} is VALID [2022-02-21 04:24:35,564 INFO L290 TraceCheckUtils]: 52: Hoare triple {40254#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 53: Hoare triple {40254#false} assume !(1 == ~t1_pc~0); {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 54: Hoare triple {40254#false} is_transmit1_triggered_~__retres1~1#1 := 0; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 55: Hoare triple {40254#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 56: Hoare triple {40254#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 57: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___0~0#1); {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 58: Hoare triple {40254#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 59: Hoare triple {40254#false} assume 1 == ~t2_pc~0; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 60: Hoare triple {40254#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 61: Hoare triple {40254#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 62: Hoare triple {40254#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 63: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___1~0#1); {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 64: Hoare triple {40254#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 65: Hoare triple {40254#false} assume 1 == ~t3_pc~0; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 66: Hoare triple {40254#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 67: Hoare triple {40254#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40254#false} is VALID [2022-02-21 04:24:35,565 INFO L290 TraceCheckUtils]: 68: Hoare triple {40254#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 69: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___2~0#1); {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 70: Hoare triple {40254#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 71: Hoare triple {40254#false} assume !(1 == ~t4_pc~0); {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 72: Hoare triple {40254#false} is_transmit4_triggered_~__retres1~4#1 := 0; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 73: Hoare triple {40254#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 74: Hoare triple {40254#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 75: Hoare triple {40254#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 76: Hoare triple {40254#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 77: Hoare triple {40254#false} assume 1 == ~t5_pc~0; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 78: Hoare triple {40254#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 79: Hoare triple {40254#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 80: Hoare triple {40254#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 81: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___4~0#1); {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 82: Hoare triple {40254#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 83: Hoare triple {40254#false} assume !(1 == ~t6_pc~0); {40254#false} is VALID [2022-02-21 04:24:35,566 INFO L290 TraceCheckUtils]: 84: Hoare triple {40254#false} is_transmit6_triggered_~__retres1~6#1 := 0; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 85: Hoare triple {40254#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 86: Hoare triple {40254#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 87: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___5~0#1); {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 88: Hoare triple {40254#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 89: Hoare triple {40254#false} assume 1 == ~t7_pc~0; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 90: Hoare triple {40254#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 91: Hoare triple {40254#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 92: Hoare triple {40254#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 93: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___6~0#1); {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 94: Hoare triple {40254#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 95: Hoare triple {40254#false} assume !(1 == ~t8_pc~0); {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 96: Hoare triple {40254#false} is_transmit8_triggered_~__retres1~8#1 := 0; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 97: Hoare triple {40254#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 98: Hoare triple {40254#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 99: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___7~0#1); {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 100: Hoare triple {40254#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 101: Hoare triple {40254#false} assume 1 == ~t9_pc~0; {40254#false} is VALID [2022-02-21 04:24:35,567 INFO L290 TraceCheckUtils]: 102: Hoare triple {40254#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 103: Hoare triple {40254#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 104: Hoare triple {40254#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 105: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___8~0#1); {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 106: Hoare triple {40254#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 107: Hoare triple {40254#false} assume !(1 == ~t10_pc~0); {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 108: Hoare triple {40254#false} is_transmit10_triggered_~__retres1~10#1 := 0; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 109: Hoare triple {40254#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 110: Hoare triple {40254#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 111: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___9~0#1); {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 112: Hoare triple {40254#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 113: Hoare triple {40254#false} assume 1 == ~t11_pc~0; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 114: Hoare triple {40254#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 115: Hoare triple {40254#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 116: Hoare triple {40254#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 117: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___10~0#1); {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 118: Hoare triple {40254#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 119: Hoare triple {40254#false} assume 1 == ~t12_pc~0; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 120: Hoare triple {40254#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {40254#false} is VALID [2022-02-21 04:24:35,568 INFO L290 TraceCheckUtils]: 121: Hoare triple {40254#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 122: Hoare triple {40254#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 123: Hoare triple {40254#false} assume !(0 != activate_threads_~tmp___11~0#1); {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 124: Hoare triple {40254#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 125: Hoare triple {40254#false} assume !(1 == ~t13_pc~0); {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 126: Hoare triple {40254#false} is_transmit13_triggered_~__retres1~13#1 := 0; {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 127: Hoare triple {40254#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 128: Hoare triple {40254#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 129: Hoare triple {40254#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 130: Hoare triple {40254#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 131: Hoare triple {40254#false} assume !(1 == ~M_E~0); {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 132: Hoare triple {40254#false} assume !(1 == ~T1_E~0); {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 133: Hoare triple {40254#false} assume !(1 == ~T2_E~0); {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 134: Hoare triple {40254#false} assume !(1 == ~T3_E~0); {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 135: Hoare triple {40254#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 136: Hoare triple {40254#false} assume !(1 == ~T5_E~0); {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 137: Hoare triple {40254#false} assume !(1 == ~T6_E~0); {40254#false} is VALID [2022-02-21 04:24:35,569 INFO L290 TraceCheckUtils]: 138: Hoare triple {40254#false} assume !(1 == ~T7_E~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 139: Hoare triple {40254#false} assume !(1 == ~T8_E~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 140: Hoare triple {40254#false} assume !(1 == ~T9_E~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 141: Hoare triple {40254#false} assume !(1 == ~T10_E~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 142: Hoare triple {40254#false} assume !(1 == ~T11_E~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 143: Hoare triple {40254#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 144: Hoare triple {40254#false} assume !(1 == ~T13_E~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 145: Hoare triple {40254#false} assume !(1 == ~E_1~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 146: Hoare triple {40254#false} assume !(1 == ~E_2~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 147: Hoare triple {40254#false} assume !(1 == ~E_3~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 148: Hoare triple {40254#false} assume !(1 == ~E_4~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 149: Hoare triple {40254#false} assume !(1 == ~E_5~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 150: Hoare triple {40254#false} assume !(1 == ~E_6~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 151: Hoare triple {40254#false} assume 1 == ~E_7~0;~E_7~0 := 2; {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 152: Hoare triple {40254#false} assume !(1 == ~E_8~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 153: Hoare triple {40254#false} assume !(1 == ~E_9~0); {40254#false} is VALID [2022-02-21 04:24:35,570 INFO L290 TraceCheckUtils]: 154: Hoare triple {40254#false} assume !(1 == ~E_10~0); {40254#false} is VALID [2022-02-21 04:24:35,571 INFO L290 TraceCheckUtils]: 155: Hoare triple {40254#false} assume !(1 == ~E_11~0); {40254#false} is VALID [2022-02-21 04:24:35,571 INFO L290 TraceCheckUtils]: 156: Hoare triple {40254#false} assume !(1 == ~E_12~0); {40254#false} is VALID [2022-02-21 04:24:35,571 INFO L290 TraceCheckUtils]: 157: Hoare triple {40254#false} assume !(1 == ~E_13~0); {40254#false} is VALID [2022-02-21 04:24:35,571 INFO L290 TraceCheckUtils]: 158: Hoare triple {40254#false} assume { :end_inline_reset_delta_events } true; {40254#false} is VALID [2022-02-21 04:24:35,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:35,571 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:35,571 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193228377] [2022-02-21 04:24:35,571 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193228377] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:35,571 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:35,571 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:35,571 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [470081842] [2022-02-21 04:24:35,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:35,572 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:35,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:35,572 INFO L85 PathProgramCache]: Analyzing trace with hash 863431474, now seen corresponding path program 1 times [2022-02-21 04:24:35,572 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:35,576 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461403711] [2022-02-21 04:24:35,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:35,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:35,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:35,614 INFO L290 TraceCheckUtils]: 0: Hoare triple {40256#true} assume !false; {40256#true} is VALID [2022-02-21 04:24:35,614 INFO L290 TraceCheckUtils]: 1: Hoare triple {40256#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {40256#true} is VALID [2022-02-21 04:24:35,614 INFO L290 TraceCheckUtils]: 2: Hoare triple {40256#true} assume !false; {40256#true} is VALID [2022-02-21 04:24:35,614 INFO L290 TraceCheckUtils]: 3: Hoare triple {40256#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {40256#true} is VALID [2022-02-21 04:24:35,614 INFO L290 TraceCheckUtils]: 4: Hoare triple {40256#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {40256#true} is VALID [2022-02-21 04:24:35,614 INFO L290 TraceCheckUtils]: 5: Hoare triple {40256#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {40256#true} is VALID [2022-02-21 04:24:35,614 INFO L290 TraceCheckUtils]: 6: Hoare triple {40256#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {40256#true} is VALID [2022-02-21 04:24:35,614 INFO L290 TraceCheckUtils]: 7: Hoare triple {40256#true} assume !(0 != eval_~tmp~0#1); {40256#true} is VALID [2022-02-21 04:24:35,614 INFO L290 TraceCheckUtils]: 8: Hoare triple {40256#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {40256#true} is VALID [2022-02-21 04:24:35,615 INFO L290 TraceCheckUtils]: 9: Hoare triple {40256#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {40256#true} is VALID [2022-02-21 04:24:35,615 INFO L290 TraceCheckUtils]: 10: Hoare triple {40256#true} assume 0 == ~M_E~0;~M_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,615 INFO L290 TraceCheckUtils]: 11: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,615 INFO L290 TraceCheckUtils]: 12: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,616 INFO L290 TraceCheckUtils]: 13: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,616 INFO L290 TraceCheckUtils]: 14: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,616 INFO L290 TraceCheckUtils]: 15: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,616 INFO L290 TraceCheckUtils]: 16: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,617 INFO L290 TraceCheckUtils]: 17: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,617 INFO L290 TraceCheckUtils]: 18: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,617 INFO L290 TraceCheckUtils]: 19: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,617 INFO L290 TraceCheckUtils]: 20: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,618 INFO L290 TraceCheckUtils]: 21: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,618 INFO L290 TraceCheckUtils]: 22: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,618 INFO L290 TraceCheckUtils]: 23: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,619 INFO L290 TraceCheckUtils]: 24: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,619 INFO L290 TraceCheckUtils]: 25: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,619 INFO L290 TraceCheckUtils]: 26: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,619 INFO L290 TraceCheckUtils]: 27: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,620 INFO L290 TraceCheckUtils]: 28: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,620 INFO L290 TraceCheckUtils]: 29: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,620 INFO L290 TraceCheckUtils]: 30: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,620 INFO L290 TraceCheckUtils]: 31: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,621 INFO L290 TraceCheckUtils]: 32: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,621 INFO L290 TraceCheckUtils]: 33: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,621 INFO L290 TraceCheckUtils]: 34: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,621 INFO L290 TraceCheckUtils]: 35: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,622 INFO L290 TraceCheckUtils]: 36: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,622 INFO L290 TraceCheckUtils]: 37: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,622 INFO L290 TraceCheckUtils]: 38: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,622 INFO L290 TraceCheckUtils]: 39: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,622 INFO L290 TraceCheckUtils]: 40: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,623 INFO L290 TraceCheckUtils]: 41: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,623 INFO L290 TraceCheckUtils]: 42: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,623 INFO L290 TraceCheckUtils]: 43: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,623 INFO L290 TraceCheckUtils]: 44: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,624 INFO L290 TraceCheckUtils]: 45: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,624 INFO L290 TraceCheckUtils]: 46: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,624 INFO L290 TraceCheckUtils]: 47: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,624 INFO L290 TraceCheckUtils]: 48: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,625 INFO L290 TraceCheckUtils]: 49: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,625 INFO L290 TraceCheckUtils]: 50: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,625 INFO L290 TraceCheckUtils]: 51: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,625 INFO L290 TraceCheckUtils]: 52: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,626 INFO L290 TraceCheckUtils]: 53: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,626 INFO L290 TraceCheckUtils]: 54: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,626 INFO L290 TraceCheckUtils]: 55: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,626 INFO L290 TraceCheckUtils]: 56: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,627 INFO L290 TraceCheckUtils]: 57: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,627 INFO L290 TraceCheckUtils]: 58: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,627 INFO L290 TraceCheckUtils]: 59: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,627 INFO L290 TraceCheckUtils]: 60: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,628 INFO L290 TraceCheckUtils]: 61: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,628 INFO L290 TraceCheckUtils]: 62: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,628 INFO L290 TraceCheckUtils]: 63: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,628 INFO L290 TraceCheckUtils]: 64: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,629 INFO L290 TraceCheckUtils]: 65: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,629 INFO L290 TraceCheckUtils]: 66: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,629 INFO L290 TraceCheckUtils]: 67: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,629 INFO L290 TraceCheckUtils]: 68: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,630 INFO L290 TraceCheckUtils]: 69: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,630 INFO L290 TraceCheckUtils]: 70: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,630 INFO L290 TraceCheckUtils]: 71: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,630 INFO L290 TraceCheckUtils]: 72: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,631 INFO L290 TraceCheckUtils]: 73: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,631 INFO L290 TraceCheckUtils]: 74: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,631 INFO L290 TraceCheckUtils]: 75: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,631 INFO L290 TraceCheckUtils]: 76: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,632 INFO L290 TraceCheckUtils]: 77: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,632 INFO L290 TraceCheckUtils]: 78: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,632 INFO L290 TraceCheckUtils]: 79: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,632 INFO L290 TraceCheckUtils]: 80: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,633 INFO L290 TraceCheckUtils]: 81: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,633 INFO L290 TraceCheckUtils]: 82: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,633 INFO L290 TraceCheckUtils]: 83: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,633 INFO L290 TraceCheckUtils]: 84: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,634 INFO L290 TraceCheckUtils]: 85: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,634 INFO L290 TraceCheckUtils]: 86: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,634 INFO L290 TraceCheckUtils]: 87: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,634 INFO L290 TraceCheckUtils]: 88: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,635 INFO L290 TraceCheckUtils]: 89: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,635 INFO L290 TraceCheckUtils]: 90: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,635 INFO L290 TraceCheckUtils]: 91: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,635 INFO L290 TraceCheckUtils]: 92: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,636 INFO L290 TraceCheckUtils]: 93: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,636 INFO L290 TraceCheckUtils]: 94: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,636 INFO L290 TraceCheckUtils]: 95: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,636 INFO L290 TraceCheckUtils]: 96: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,637 INFO L290 TraceCheckUtils]: 97: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,637 INFO L290 TraceCheckUtils]: 98: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,637 INFO L290 TraceCheckUtils]: 99: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,637 INFO L290 TraceCheckUtils]: 100: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,638 INFO L290 TraceCheckUtils]: 101: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,638 INFO L290 TraceCheckUtils]: 102: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,638 INFO L290 TraceCheckUtils]: 103: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,638 INFO L290 TraceCheckUtils]: 104: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,639 INFO L290 TraceCheckUtils]: 105: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,639 INFO L290 TraceCheckUtils]: 106: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,639 INFO L290 TraceCheckUtils]: 107: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,639 INFO L290 TraceCheckUtils]: 108: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,640 INFO L290 TraceCheckUtils]: 109: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,640 INFO L290 TraceCheckUtils]: 110: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,640 INFO L290 TraceCheckUtils]: 111: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,640 INFO L290 TraceCheckUtils]: 112: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,641 INFO L290 TraceCheckUtils]: 113: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,641 INFO L290 TraceCheckUtils]: 114: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,641 INFO L290 TraceCheckUtils]: 115: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,641 INFO L290 TraceCheckUtils]: 116: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,642 INFO L290 TraceCheckUtils]: 117: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,642 INFO L290 TraceCheckUtils]: 118: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,642 INFO L290 TraceCheckUtils]: 119: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 120: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 121: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40258#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 122: Hoare triple {40258#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {40257#false} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 123: Hoare triple {40257#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 124: Hoare triple {40257#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 125: Hoare triple {40257#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 126: Hoare triple {40257#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 127: Hoare triple {40257#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 128: Hoare triple {40257#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,643 INFO L290 TraceCheckUtils]: 129: Hoare triple {40257#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 130: Hoare triple {40257#false} assume !(1 == ~T8_E~0); {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 131: Hoare triple {40257#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 132: Hoare triple {40257#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 133: Hoare triple {40257#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 134: Hoare triple {40257#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 135: Hoare triple {40257#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 136: Hoare triple {40257#false} assume 1 == ~E_1~0;~E_1~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 137: Hoare triple {40257#false} assume 1 == ~E_2~0;~E_2~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 138: Hoare triple {40257#false} assume !(1 == ~E_3~0); {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 139: Hoare triple {40257#false} assume 1 == ~E_4~0;~E_4~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 140: Hoare triple {40257#false} assume 1 == ~E_5~0;~E_5~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 141: Hoare triple {40257#false} assume 1 == ~E_6~0;~E_6~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 142: Hoare triple {40257#false} assume 1 == ~E_7~0;~E_7~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 143: Hoare triple {40257#false} assume 1 == ~E_8~0;~E_8~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 144: Hoare triple {40257#false} assume 1 == ~E_9~0;~E_9~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 145: Hoare triple {40257#false} assume 1 == ~E_10~0;~E_10~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 146: Hoare triple {40257#false} assume !(1 == ~E_11~0); {40257#false} is VALID [2022-02-21 04:24:35,644 INFO L290 TraceCheckUtils]: 147: Hoare triple {40257#false} assume 1 == ~E_12~0;~E_12~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 148: Hoare triple {40257#false} assume 1 == ~E_13~0;~E_13~0 := 2; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 149: Hoare triple {40257#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 150: Hoare triple {40257#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 151: Hoare triple {40257#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 152: Hoare triple {40257#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 153: Hoare triple {40257#false} assume !(0 == start_simulation_~tmp~3#1); {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 154: Hoare triple {40257#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 155: Hoare triple {40257#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 156: Hoare triple {40257#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 157: Hoare triple {40257#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 158: Hoare triple {40257#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 159: Hoare triple {40257#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 160: Hoare triple {40257#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {40257#false} is VALID [2022-02-21 04:24:35,645 INFO L290 TraceCheckUtils]: 161: Hoare triple {40257#false} assume !(0 != start_simulation_~tmp___0~1#1); {40257#false} is VALID [2022-02-21 04:24:35,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:35,646 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:35,646 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1461403711] [2022-02-21 04:24:35,646 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1461403711] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:35,646 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:35,646 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:35,646 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805393076] [2022-02-21 04:24:35,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:35,647 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:35,647 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:35,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:35,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:35,648 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:37,050 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-02-21 04:24:37,050 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:37,050 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,156 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:37,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:37,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:37,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-02-21 04:24:37,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:37,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:37,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:37,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:37,329 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-02-21 04:24:37,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:37,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:37,349 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:37,351 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2830 transitions. Second operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,352 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2830 transitions. Second operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,353 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. Second operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:37,430 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-02-21 04:24:37,430 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:37,431 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:37,431 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:37,434 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2830 transitions. [2022-02-21 04:24:37,435 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2830 transitions. [2022-02-21 04:24:37,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:37,512 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-02-21 04:24:37,512 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:37,513 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:37,513 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:37,513 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:37,513 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:37,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-02-21 04:24:37,590 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-02-21 04:24:37,590 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-02-21 04:24:37,590 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:37,590 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:37,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:37,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:37,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:37,595 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:37,595 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:37,595 INFO L791 eck$LassoCheckResult]: Stem: 43034#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 43035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42854#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42570#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42571#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43747#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43748#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42706#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42707#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43165#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42996#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 42997#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 42773#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 42774#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43172#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 43349#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 43503#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43540#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42786#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42787#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43960#L1258-2 assume !(0 == ~T1_E~0); 43079#L1263-1 assume !(0 == ~T2_E~0); 43080#L1268-1 assume !(0 == ~T3_E~0); 43383#L1273-1 assume !(0 == ~T4_E~0); 43942#L1278-1 assume !(0 == ~T5_E~0); 43803#L1283-1 assume !(0 == ~T6_E~0); 43804#L1288-1 assume !(0 == ~T7_E~0); 44040#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44028#L1298-1 assume !(0 == ~T9_E~0); 43954#L1303-1 assume !(0 == ~T10_E~0); 42599#L1308-1 assume !(0 == ~T11_E~0); 42541#L1313-1 assume !(0 == ~T12_E~0); 42542#L1318-1 assume !(0 == ~T13_E~0); 42550#L1323-1 assume !(0 == ~E_1~0); 42551#L1328-1 assume !(0 == ~E_2~0); 42716#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43675#L1338-1 assume !(0 == ~E_4~0); 43676#L1343-1 assume !(0 == ~E_5~0); 43777#L1348-1 assume !(0 == ~E_6~0); 44063#L1353-1 assume !(0 == ~E_7~0); 43402#L1358-1 assume !(0 == ~E_8~0); 43403#L1363-1 assume !(0 == ~E_9~0); 43693#L1368-1 assume !(0 == ~E_10~0); 42378#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42379#L1378-1 assume !(0 == ~E_12~0); 42667#L1383-1 assume !(0 == ~E_13~0); 42668#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43409#L607 assume 1 == ~m_pc~0; 43410#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42736#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43775#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43329#L1560 assume !(0 != activate_threads_~tmp~1#1); 43330#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42561#L626 assume !(1 == ~t1_pc~0); 42562#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42830#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42831#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43002#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42463#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42464#L645 assume 1 == ~t2_pc~0; 42578#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42535#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43215#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43216#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43305#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43306#L664 assume 1 == ~t3_pc~0; 44062#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42306#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42307#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42961#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42962#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43970#L683 assume !(1 == ~t4_pc~0); 43525#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43477#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43478#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43512#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43636#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43259#L702 assume 1 == ~t5_pc~0; 43260#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43182#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43631#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43930#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43871#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42350#L721 assume !(1 == ~t6_pc~0); 42324#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42325#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42488#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42970#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42971#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43572#L740 assume 1 == ~t7_pc~0; 42399#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42212#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42213#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42202#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42203#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42907#L759 assume !(1 == ~t8_pc~0); 42908#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42936#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43629#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43630#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43761#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44039#L778 assume 1 == ~t9_pc~0; 43926#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42377#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42317#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42246#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42247#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42575#L797 assume !(1 == ~t10_pc~0); 42576#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42693#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43827#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43077#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43078#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43367#L816 assume 1 == ~t11_pc~0; 42282#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42283#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43040#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42977#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 42978#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43502#L835 assume 1 == ~t12_pc~0; 43380#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42446#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42468#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42609#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43134#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43135#L854 assume !(1 == ~t13_pc~0); 42775#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42776#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42826#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42486#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42487#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43866#L1401 assume !(1 == ~M_E~0); 42965#L1401-2 assume !(1 == ~T1_E~0); 42966#L1406-1 assume !(1 == ~T2_E~0); 43561#L1411-1 assume !(1 == ~T3_E~0); 43562#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43228#L1421-1 assume !(1 == ~T5_E~0); 42771#L1426-1 assume !(1 == ~T6_E~0); 42772#L1431-1 assume !(1 == ~T7_E~0); 42320#L1436-1 assume !(1 == ~T8_E~0); 42321#L1441-1 assume !(1 == ~T9_E~0); 43070#L1446-1 assume !(1 == ~T10_E~0); 43071#L1451-1 assume !(1 == ~T11_E~0); 43774#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43428#L1461-1 assume !(1 == ~T13_E~0); 42989#L1466-1 assume !(1 == ~E_1~0); 42990#L1471-1 assume !(1 == ~E_2~0); 43759#L1476-1 assume !(1 == ~E_3~0); 43760#L1481-1 assume !(1 == ~E_4~0); 43908#L1486-1 assume !(1 == ~E_5~0); 42614#L1491-1 assume !(1 == ~E_6~0); 42254#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42255#L1501-1 assume !(1 == ~E_8~0); 43066#L1506-1 assume !(1 == ~E_9~0); 43067#L1511-1 assume !(1 == ~E_10~0); 43023#L1516-1 assume !(1 == ~E_11~0); 42200#L1521-1 assume !(1 == ~E_12~0); 42201#L1526-1 assume !(1 == ~E_13~0); 42253#L1531-1 assume { :end_inline_reset_delta_events } true; 42796#L1892-2 [2022-02-21 04:24:37,595 INFO L793 eck$LassoCheckResult]: Loop: 42796#L1892-2 assume !false; 43819#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44017#L1233 assume !false; 44000#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43332#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43312#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43470#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42296#L1046 assume !(0 != eval_~tmp~0#1); 42298#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42332#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43504#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44061#L1258-5 assume !(0 == ~T1_E~0); 42476#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42477#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44053#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44059#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44060#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42700#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42701#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43816#L1298-3 assume !(0 == ~T9_E~0); 43817#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43976#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43815#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43316#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42478#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42479#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43900#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42619#L1338-3 assume !(0 == ~E_4~0); 42620#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43732#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43906#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43907#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43274#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42832#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42833#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43589#L1378-3 assume !(0 == ~E_12~0); 43590#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43771#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43772#L607-42 assume 1 == ~m_pc~0; 43387#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43113#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43114#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42846#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42847#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43368#L626-42 assume 1 == ~t1_pc~0; 42930#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42931#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43235#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43236#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42510#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42511#L645-42 assume 1 == ~t2_pc~0; 43969#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43710#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43876#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42717#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42224#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42225#L664-42 assume 1 == ~t3_pc~0; 43027#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42752#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44003#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43538#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43539#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43704#L683-42 assume !(1 == ~t4_pc~0); 43412#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43413#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43544#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43965#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43966#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43810#L702-42 assume 1 == ~t5_pc~0; 43298#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42923#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43219#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43892#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 42240#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42241#L721-42 assume 1 == ~t6_pc~0; 42394#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42414#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42878#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44045#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43050#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42896#L740-42 assume 1 == ~t7_pc~0; 42897#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42634#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43175#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43030#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43031#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43304#L759-42 assume 1 == ~t8_pc~0; 43153#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43085#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43086#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43163#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43164#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43258#L778-42 assume 1 == ~t9_pc~0; 43097#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43099#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43508#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43414#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43415#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43472#L797-42 assume !(1 == ~t10_pc~0); 42641#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 42640#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43641#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43950#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43510#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43511#L816-42 assume 1 == ~t11_pc~0; 42188#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42189#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42731#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42732#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42811#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42812#L835-42 assume !(1 == ~t12_pc~0); 43105#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 43106#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42784#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42785#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43869#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43653#L854-42 assume 1 == ~t13_pc~0; 43654#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42728#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42340#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42341#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42987#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42988#L1401-3 assume !(1 == ~M_E~0); 43766#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42574#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42441#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42442#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43041#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43042#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42617#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42618#L1436-3 assume !(1 == ~T8_E~0); 42204#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42205#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43794#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43125#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42778#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42779#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44056#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42718#L1476-3 assume !(1 == ~E_3~0); 42719#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43119#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42746#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42747#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43158#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43159#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43586#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43576#L1516-3 assume !(1 == ~E_11~0); 43577#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43276#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43277#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43671#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42553#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43446#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43087#L1911 assume !(0 == start_simulation_~tmp~3#1); 43088#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43610#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42678#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43548#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42382#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42383#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42612#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 42613#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42796#L1892-2 [2022-02-21 04:24:37,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:37,596 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2022-02-21 04:24:37,596 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:37,596 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854934946] [2022-02-21 04:24:37,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:37,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:37,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:37,620 INFO L290 TraceCheckUtils]: 0: Hoare triple {47918#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {47918#true} is VALID [2022-02-21 04:24:37,621 INFO L290 TraceCheckUtils]: 1: Hoare triple {47918#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {47920#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:37,621 INFO L290 TraceCheckUtils]: 2: Hoare triple {47920#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {47920#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:37,621 INFO L290 TraceCheckUtils]: 3: Hoare triple {47920#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {47920#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:37,621 INFO L290 TraceCheckUtils]: 4: Hoare triple {47920#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {47920#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:37,622 INFO L290 TraceCheckUtils]: 5: Hoare triple {47920#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {47920#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:37,622 INFO L290 TraceCheckUtils]: 6: Hoare triple {47920#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {47920#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:37,622 INFO L290 TraceCheckUtils]: 7: Hoare triple {47920#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {47920#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:37,623 INFO L290 TraceCheckUtils]: 8: Hoare triple {47920#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {47920#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:37,623 INFO L290 TraceCheckUtils]: 9: Hoare triple {47920#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {47920#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:37,623 INFO L290 TraceCheckUtils]: 10: Hoare triple {47920#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,623 INFO L290 TraceCheckUtils]: 11: Hoare triple {47919#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,623 INFO L290 TraceCheckUtils]: 12: Hoare triple {47919#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,624 INFO L290 TraceCheckUtils]: 13: Hoare triple {47919#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {47919#false} is VALID [2022-02-21 04:24:37,624 INFO L290 TraceCheckUtils]: 14: Hoare triple {47919#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,624 INFO L290 TraceCheckUtils]: 15: Hoare triple {47919#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,624 INFO L290 TraceCheckUtils]: 16: Hoare triple {47919#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,624 INFO L290 TraceCheckUtils]: 17: Hoare triple {47919#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,624 INFO L290 TraceCheckUtils]: 18: Hoare triple {47919#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {47919#false} is VALID [2022-02-21 04:24:37,624 INFO L290 TraceCheckUtils]: 19: Hoare triple {47919#false} assume 0 == ~M_E~0;~M_E~0 := 1; {47919#false} is VALID [2022-02-21 04:24:37,624 INFO L290 TraceCheckUtils]: 20: Hoare triple {47919#false} assume !(0 == ~T1_E~0); {47919#false} is VALID [2022-02-21 04:24:37,624 INFO L290 TraceCheckUtils]: 21: Hoare triple {47919#false} assume !(0 == ~T2_E~0); {47919#false} is VALID [2022-02-21 04:24:37,625 INFO L290 TraceCheckUtils]: 22: Hoare triple {47919#false} assume !(0 == ~T3_E~0); {47919#false} is VALID [2022-02-21 04:24:37,625 INFO L290 TraceCheckUtils]: 23: Hoare triple {47919#false} assume !(0 == ~T4_E~0); {47919#false} is VALID [2022-02-21 04:24:37,625 INFO L290 TraceCheckUtils]: 24: Hoare triple {47919#false} assume !(0 == ~T5_E~0); {47919#false} is VALID [2022-02-21 04:24:37,625 INFO L290 TraceCheckUtils]: 25: Hoare triple {47919#false} assume !(0 == ~T6_E~0); {47919#false} is VALID [2022-02-21 04:24:37,625 INFO L290 TraceCheckUtils]: 26: Hoare triple {47919#false} assume !(0 == ~T7_E~0); {47919#false} is VALID [2022-02-21 04:24:37,625 INFO L290 TraceCheckUtils]: 27: Hoare triple {47919#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {47919#false} is VALID [2022-02-21 04:24:37,625 INFO L290 TraceCheckUtils]: 28: Hoare triple {47919#false} assume !(0 == ~T9_E~0); {47919#false} is VALID [2022-02-21 04:24:37,625 INFO L290 TraceCheckUtils]: 29: Hoare triple {47919#false} assume !(0 == ~T10_E~0); {47919#false} is VALID [2022-02-21 04:24:37,625 INFO L290 TraceCheckUtils]: 30: Hoare triple {47919#false} assume !(0 == ~T11_E~0); {47919#false} is VALID [2022-02-21 04:24:37,626 INFO L290 TraceCheckUtils]: 31: Hoare triple {47919#false} assume !(0 == ~T12_E~0); {47919#false} is VALID [2022-02-21 04:24:37,626 INFO L290 TraceCheckUtils]: 32: Hoare triple {47919#false} assume !(0 == ~T13_E~0); {47919#false} is VALID [2022-02-21 04:24:37,626 INFO L290 TraceCheckUtils]: 33: Hoare triple {47919#false} assume !(0 == ~E_1~0); {47919#false} is VALID [2022-02-21 04:24:37,626 INFO L290 TraceCheckUtils]: 34: Hoare triple {47919#false} assume !(0 == ~E_2~0); {47919#false} is VALID [2022-02-21 04:24:37,626 INFO L290 TraceCheckUtils]: 35: Hoare triple {47919#false} assume 0 == ~E_3~0;~E_3~0 := 1; {47919#false} is VALID [2022-02-21 04:24:37,626 INFO L290 TraceCheckUtils]: 36: Hoare triple {47919#false} assume !(0 == ~E_4~0); {47919#false} is VALID [2022-02-21 04:24:37,626 INFO L290 TraceCheckUtils]: 37: Hoare triple {47919#false} assume !(0 == ~E_5~0); {47919#false} is VALID [2022-02-21 04:24:37,626 INFO L290 TraceCheckUtils]: 38: Hoare triple {47919#false} assume !(0 == ~E_6~0); {47919#false} is VALID [2022-02-21 04:24:37,626 INFO L290 TraceCheckUtils]: 39: Hoare triple {47919#false} assume !(0 == ~E_7~0); {47919#false} is VALID [2022-02-21 04:24:37,627 INFO L290 TraceCheckUtils]: 40: Hoare triple {47919#false} assume !(0 == ~E_8~0); {47919#false} is VALID [2022-02-21 04:24:37,627 INFO L290 TraceCheckUtils]: 41: Hoare triple {47919#false} assume !(0 == ~E_9~0); {47919#false} is VALID [2022-02-21 04:24:37,627 INFO L290 TraceCheckUtils]: 42: Hoare triple {47919#false} assume !(0 == ~E_10~0); {47919#false} is VALID [2022-02-21 04:24:37,627 INFO L290 TraceCheckUtils]: 43: Hoare triple {47919#false} assume 0 == ~E_11~0;~E_11~0 := 1; {47919#false} is VALID [2022-02-21 04:24:37,627 INFO L290 TraceCheckUtils]: 44: Hoare triple {47919#false} assume !(0 == ~E_12~0); {47919#false} is VALID [2022-02-21 04:24:37,627 INFO L290 TraceCheckUtils]: 45: Hoare triple {47919#false} assume !(0 == ~E_13~0); {47919#false} is VALID [2022-02-21 04:24:37,627 INFO L290 TraceCheckUtils]: 46: Hoare triple {47919#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {47919#false} is VALID [2022-02-21 04:24:37,627 INFO L290 TraceCheckUtils]: 47: Hoare triple {47919#false} assume 1 == ~m_pc~0; {47919#false} is VALID [2022-02-21 04:24:37,627 INFO L290 TraceCheckUtils]: 48: Hoare triple {47919#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {47919#false} is VALID [2022-02-21 04:24:37,628 INFO L290 TraceCheckUtils]: 49: Hoare triple {47919#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {47919#false} is VALID [2022-02-21 04:24:37,628 INFO L290 TraceCheckUtils]: 50: Hoare triple {47919#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {47919#false} is VALID [2022-02-21 04:24:37,628 INFO L290 TraceCheckUtils]: 51: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp~1#1); {47919#false} is VALID [2022-02-21 04:24:37,628 INFO L290 TraceCheckUtils]: 52: Hoare triple {47919#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {47919#false} is VALID [2022-02-21 04:24:37,628 INFO L290 TraceCheckUtils]: 53: Hoare triple {47919#false} assume !(1 == ~t1_pc~0); {47919#false} is VALID [2022-02-21 04:24:37,628 INFO L290 TraceCheckUtils]: 54: Hoare triple {47919#false} is_transmit1_triggered_~__retres1~1#1 := 0; {47919#false} is VALID [2022-02-21 04:24:37,628 INFO L290 TraceCheckUtils]: 55: Hoare triple {47919#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {47919#false} is VALID [2022-02-21 04:24:37,628 INFO L290 TraceCheckUtils]: 56: Hoare triple {47919#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {47919#false} is VALID [2022-02-21 04:24:37,628 INFO L290 TraceCheckUtils]: 57: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___0~0#1); {47919#false} is VALID [2022-02-21 04:24:37,629 INFO L290 TraceCheckUtils]: 58: Hoare triple {47919#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {47919#false} is VALID [2022-02-21 04:24:37,629 INFO L290 TraceCheckUtils]: 59: Hoare triple {47919#false} assume 1 == ~t2_pc~0; {47919#false} is VALID [2022-02-21 04:24:37,629 INFO L290 TraceCheckUtils]: 60: Hoare triple {47919#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {47919#false} is VALID [2022-02-21 04:24:37,629 INFO L290 TraceCheckUtils]: 61: Hoare triple {47919#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {47919#false} is VALID [2022-02-21 04:24:37,629 INFO L290 TraceCheckUtils]: 62: Hoare triple {47919#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {47919#false} is VALID [2022-02-21 04:24:37,629 INFO L290 TraceCheckUtils]: 63: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___1~0#1); {47919#false} is VALID [2022-02-21 04:24:37,629 INFO L290 TraceCheckUtils]: 64: Hoare triple {47919#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {47919#false} is VALID [2022-02-21 04:24:37,629 INFO L290 TraceCheckUtils]: 65: Hoare triple {47919#false} assume 1 == ~t3_pc~0; {47919#false} is VALID [2022-02-21 04:24:37,629 INFO L290 TraceCheckUtils]: 66: Hoare triple {47919#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {47919#false} is VALID [2022-02-21 04:24:37,630 INFO L290 TraceCheckUtils]: 67: Hoare triple {47919#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {47919#false} is VALID [2022-02-21 04:24:37,630 INFO L290 TraceCheckUtils]: 68: Hoare triple {47919#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {47919#false} is VALID [2022-02-21 04:24:37,630 INFO L290 TraceCheckUtils]: 69: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___2~0#1); {47919#false} is VALID [2022-02-21 04:24:37,630 INFO L290 TraceCheckUtils]: 70: Hoare triple {47919#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {47919#false} is VALID [2022-02-21 04:24:37,630 INFO L290 TraceCheckUtils]: 71: Hoare triple {47919#false} assume !(1 == ~t4_pc~0); {47919#false} is VALID [2022-02-21 04:24:37,630 INFO L290 TraceCheckUtils]: 72: Hoare triple {47919#false} is_transmit4_triggered_~__retres1~4#1 := 0; {47919#false} is VALID [2022-02-21 04:24:37,630 INFO L290 TraceCheckUtils]: 73: Hoare triple {47919#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {47919#false} is VALID [2022-02-21 04:24:37,630 INFO L290 TraceCheckUtils]: 74: Hoare triple {47919#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {47919#false} is VALID [2022-02-21 04:24:37,630 INFO L290 TraceCheckUtils]: 75: Hoare triple {47919#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {47919#false} is VALID [2022-02-21 04:24:37,631 INFO L290 TraceCheckUtils]: 76: Hoare triple {47919#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {47919#false} is VALID [2022-02-21 04:24:37,631 INFO L290 TraceCheckUtils]: 77: Hoare triple {47919#false} assume 1 == ~t5_pc~0; {47919#false} is VALID [2022-02-21 04:24:37,631 INFO L290 TraceCheckUtils]: 78: Hoare triple {47919#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {47919#false} is VALID [2022-02-21 04:24:37,631 INFO L290 TraceCheckUtils]: 79: Hoare triple {47919#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {47919#false} is VALID [2022-02-21 04:24:37,631 INFO L290 TraceCheckUtils]: 80: Hoare triple {47919#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {47919#false} is VALID [2022-02-21 04:24:37,631 INFO L290 TraceCheckUtils]: 81: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___4~0#1); {47919#false} is VALID [2022-02-21 04:24:37,631 INFO L290 TraceCheckUtils]: 82: Hoare triple {47919#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {47919#false} is VALID [2022-02-21 04:24:37,631 INFO L290 TraceCheckUtils]: 83: Hoare triple {47919#false} assume !(1 == ~t6_pc~0); {47919#false} is VALID [2022-02-21 04:24:37,631 INFO L290 TraceCheckUtils]: 84: Hoare triple {47919#false} is_transmit6_triggered_~__retres1~6#1 := 0; {47919#false} is VALID [2022-02-21 04:24:37,632 INFO L290 TraceCheckUtils]: 85: Hoare triple {47919#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {47919#false} is VALID [2022-02-21 04:24:37,632 INFO L290 TraceCheckUtils]: 86: Hoare triple {47919#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {47919#false} is VALID [2022-02-21 04:24:37,632 INFO L290 TraceCheckUtils]: 87: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___5~0#1); {47919#false} is VALID [2022-02-21 04:24:37,632 INFO L290 TraceCheckUtils]: 88: Hoare triple {47919#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {47919#false} is VALID [2022-02-21 04:24:37,632 INFO L290 TraceCheckUtils]: 89: Hoare triple {47919#false} assume 1 == ~t7_pc~0; {47919#false} is VALID [2022-02-21 04:24:37,632 INFO L290 TraceCheckUtils]: 90: Hoare triple {47919#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {47919#false} is VALID [2022-02-21 04:24:37,632 INFO L290 TraceCheckUtils]: 91: Hoare triple {47919#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {47919#false} is VALID [2022-02-21 04:24:37,632 INFO L290 TraceCheckUtils]: 92: Hoare triple {47919#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {47919#false} is VALID [2022-02-21 04:24:37,632 INFO L290 TraceCheckUtils]: 93: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___6~0#1); {47919#false} is VALID [2022-02-21 04:24:37,633 INFO L290 TraceCheckUtils]: 94: Hoare triple {47919#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {47919#false} is VALID [2022-02-21 04:24:37,633 INFO L290 TraceCheckUtils]: 95: Hoare triple {47919#false} assume !(1 == ~t8_pc~0); {47919#false} is VALID [2022-02-21 04:24:37,633 INFO L290 TraceCheckUtils]: 96: Hoare triple {47919#false} is_transmit8_triggered_~__retres1~8#1 := 0; {47919#false} is VALID [2022-02-21 04:24:37,633 INFO L290 TraceCheckUtils]: 97: Hoare triple {47919#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {47919#false} is VALID [2022-02-21 04:24:37,633 INFO L290 TraceCheckUtils]: 98: Hoare triple {47919#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {47919#false} is VALID [2022-02-21 04:24:37,633 INFO L290 TraceCheckUtils]: 99: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___7~0#1); {47919#false} is VALID [2022-02-21 04:24:37,633 INFO L290 TraceCheckUtils]: 100: Hoare triple {47919#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {47919#false} is VALID [2022-02-21 04:24:37,633 INFO L290 TraceCheckUtils]: 101: Hoare triple {47919#false} assume 1 == ~t9_pc~0; {47919#false} is VALID [2022-02-21 04:24:37,633 INFO L290 TraceCheckUtils]: 102: Hoare triple {47919#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {47919#false} is VALID [2022-02-21 04:24:37,634 INFO L290 TraceCheckUtils]: 103: Hoare triple {47919#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {47919#false} is VALID [2022-02-21 04:24:37,634 INFO L290 TraceCheckUtils]: 104: Hoare triple {47919#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {47919#false} is VALID [2022-02-21 04:24:37,634 INFO L290 TraceCheckUtils]: 105: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___8~0#1); {47919#false} is VALID [2022-02-21 04:24:37,634 INFO L290 TraceCheckUtils]: 106: Hoare triple {47919#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {47919#false} is VALID [2022-02-21 04:24:37,634 INFO L290 TraceCheckUtils]: 107: Hoare triple {47919#false} assume !(1 == ~t10_pc~0); {47919#false} is VALID [2022-02-21 04:24:37,634 INFO L290 TraceCheckUtils]: 108: Hoare triple {47919#false} is_transmit10_triggered_~__retres1~10#1 := 0; {47919#false} is VALID [2022-02-21 04:24:37,634 INFO L290 TraceCheckUtils]: 109: Hoare triple {47919#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {47919#false} is VALID [2022-02-21 04:24:37,634 INFO L290 TraceCheckUtils]: 110: Hoare triple {47919#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {47919#false} is VALID [2022-02-21 04:24:37,634 INFO L290 TraceCheckUtils]: 111: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___9~0#1); {47919#false} is VALID [2022-02-21 04:24:37,635 INFO L290 TraceCheckUtils]: 112: Hoare triple {47919#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {47919#false} is VALID [2022-02-21 04:24:37,635 INFO L290 TraceCheckUtils]: 113: Hoare triple {47919#false} assume 1 == ~t11_pc~0; {47919#false} is VALID [2022-02-21 04:24:37,635 INFO L290 TraceCheckUtils]: 114: Hoare triple {47919#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {47919#false} is VALID [2022-02-21 04:24:37,635 INFO L290 TraceCheckUtils]: 115: Hoare triple {47919#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {47919#false} is VALID [2022-02-21 04:24:37,635 INFO L290 TraceCheckUtils]: 116: Hoare triple {47919#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {47919#false} is VALID [2022-02-21 04:24:37,635 INFO L290 TraceCheckUtils]: 117: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___10~0#1); {47919#false} is VALID [2022-02-21 04:24:37,635 INFO L290 TraceCheckUtils]: 118: Hoare triple {47919#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {47919#false} is VALID [2022-02-21 04:24:37,635 INFO L290 TraceCheckUtils]: 119: Hoare triple {47919#false} assume 1 == ~t12_pc~0; {47919#false} is VALID [2022-02-21 04:24:37,635 INFO L290 TraceCheckUtils]: 120: Hoare triple {47919#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {47919#false} is VALID [2022-02-21 04:24:37,636 INFO L290 TraceCheckUtils]: 121: Hoare triple {47919#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {47919#false} is VALID [2022-02-21 04:24:37,636 INFO L290 TraceCheckUtils]: 122: Hoare triple {47919#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {47919#false} is VALID [2022-02-21 04:24:37,636 INFO L290 TraceCheckUtils]: 123: Hoare triple {47919#false} assume !(0 != activate_threads_~tmp___11~0#1); {47919#false} is VALID [2022-02-21 04:24:37,636 INFO L290 TraceCheckUtils]: 124: Hoare triple {47919#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {47919#false} is VALID [2022-02-21 04:24:37,636 INFO L290 TraceCheckUtils]: 125: Hoare triple {47919#false} assume !(1 == ~t13_pc~0); {47919#false} is VALID [2022-02-21 04:24:37,636 INFO L290 TraceCheckUtils]: 126: Hoare triple {47919#false} is_transmit13_triggered_~__retres1~13#1 := 0; {47919#false} is VALID [2022-02-21 04:24:37,636 INFO L290 TraceCheckUtils]: 127: Hoare triple {47919#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {47919#false} is VALID [2022-02-21 04:24:37,636 INFO L290 TraceCheckUtils]: 128: Hoare triple {47919#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {47919#false} is VALID [2022-02-21 04:24:37,636 INFO L290 TraceCheckUtils]: 129: Hoare triple {47919#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {47919#false} is VALID [2022-02-21 04:24:37,637 INFO L290 TraceCheckUtils]: 130: Hoare triple {47919#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {47919#false} is VALID [2022-02-21 04:24:37,637 INFO L290 TraceCheckUtils]: 131: Hoare triple {47919#false} assume !(1 == ~M_E~0); {47919#false} is VALID [2022-02-21 04:24:37,637 INFO L290 TraceCheckUtils]: 132: Hoare triple {47919#false} assume !(1 == ~T1_E~0); {47919#false} is VALID [2022-02-21 04:24:37,637 INFO L290 TraceCheckUtils]: 133: Hoare triple {47919#false} assume !(1 == ~T2_E~0); {47919#false} is VALID [2022-02-21 04:24:37,637 INFO L290 TraceCheckUtils]: 134: Hoare triple {47919#false} assume !(1 == ~T3_E~0); {47919#false} is VALID [2022-02-21 04:24:37,637 INFO L290 TraceCheckUtils]: 135: Hoare triple {47919#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,637 INFO L290 TraceCheckUtils]: 136: Hoare triple {47919#false} assume !(1 == ~T5_E~0); {47919#false} is VALID [2022-02-21 04:24:37,637 INFO L290 TraceCheckUtils]: 137: Hoare triple {47919#false} assume !(1 == ~T6_E~0); {47919#false} is VALID [2022-02-21 04:24:37,637 INFO L290 TraceCheckUtils]: 138: Hoare triple {47919#false} assume !(1 == ~T7_E~0); {47919#false} is VALID [2022-02-21 04:24:37,638 INFO L290 TraceCheckUtils]: 139: Hoare triple {47919#false} assume !(1 == ~T8_E~0); {47919#false} is VALID [2022-02-21 04:24:37,638 INFO L290 TraceCheckUtils]: 140: Hoare triple {47919#false} assume !(1 == ~T9_E~0); {47919#false} is VALID [2022-02-21 04:24:37,638 INFO L290 TraceCheckUtils]: 141: Hoare triple {47919#false} assume !(1 == ~T10_E~0); {47919#false} is VALID [2022-02-21 04:24:37,638 INFO L290 TraceCheckUtils]: 142: Hoare triple {47919#false} assume !(1 == ~T11_E~0); {47919#false} is VALID [2022-02-21 04:24:37,638 INFO L290 TraceCheckUtils]: 143: Hoare triple {47919#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,638 INFO L290 TraceCheckUtils]: 144: Hoare triple {47919#false} assume !(1 == ~T13_E~0); {47919#false} is VALID [2022-02-21 04:24:37,638 INFO L290 TraceCheckUtils]: 145: Hoare triple {47919#false} assume !(1 == ~E_1~0); {47919#false} is VALID [2022-02-21 04:24:37,638 INFO L290 TraceCheckUtils]: 146: Hoare triple {47919#false} assume !(1 == ~E_2~0); {47919#false} is VALID [2022-02-21 04:24:37,638 INFO L290 TraceCheckUtils]: 147: Hoare triple {47919#false} assume !(1 == ~E_3~0); {47919#false} is VALID [2022-02-21 04:24:37,639 INFO L290 TraceCheckUtils]: 148: Hoare triple {47919#false} assume !(1 == ~E_4~0); {47919#false} is VALID [2022-02-21 04:24:37,639 INFO L290 TraceCheckUtils]: 149: Hoare triple {47919#false} assume !(1 == ~E_5~0); {47919#false} is VALID [2022-02-21 04:24:37,639 INFO L290 TraceCheckUtils]: 150: Hoare triple {47919#false} assume !(1 == ~E_6~0); {47919#false} is VALID [2022-02-21 04:24:37,639 INFO L290 TraceCheckUtils]: 151: Hoare triple {47919#false} assume 1 == ~E_7~0;~E_7~0 := 2; {47919#false} is VALID [2022-02-21 04:24:37,639 INFO L290 TraceCheckUtils]: 152: Hoare triple {47919#false} assume !(1 == ~E_8~0); {47919#false} is VALID [2022-02-21 04:24:37,639 INFO L290 TraceCheckUtils]: 153: Hoare triple {47919#false} assume !(1 == ~E_9~0); {47919#false} is VALID [2022-02-21 04:24:37,639 INFO L290 TraceCheckUtils]: 154: Hoare triple {47919#false} assume !(1 == ~E_10~0); {47919#false} is VALID [2022-02-21 04:24:37,639 INFO L290 TraceCheckUtils]: 155: Hoare triple {47919#false} assume !(1 == ~E_11~0); {47919#false} is VALID [2022-02-21 04:24:37,639 INFO L290 TraceCheckUtils]: 156: Hoare triple {47919#false} assume !(1 == ~E_12~0); {47919#false} is VALID [2022-02-21 04:24:37,640 INFO L290 TraceCheckUtils]: 157: Hoare triple {47919#false} assume !(1 == ~E_13~0); {47919#false} is VALID [2022-02-21 04:24:37,640 INFO L290 TraceCheckUtils]: 158: Hoare triple {47919#false} assume { :end_inline_reset_delta_events } true; {47919#false} is VALID [2022-02-21 04:24:37,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:37,640 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:37,640 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854934946] [2022-02-21 04:24:37,640 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854934946] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:37,641 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:37,641 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:37,641 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920903440] [2022-02-21 04:24:37,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:37,641 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:37,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:37,642 INFO L85 PathProgramCache]: Analyzing trace with hash 863431474, now seen corresponding path program 2 times [2022-02-21 04:24:37,642 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:37,642 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017231729] [2022-02-21 04:24:37,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:37,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:37,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:37,686 INFO L290 TraceCheckUtils]: 0: Hoare triple {47921#true} assume !false; {47921#true} is VALID [2022-02-21 04:24:37,686 INFO L290 TraceCheckUtils]: 1: Hoare triple {47921#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {47921#true} is VALID [2022-02-21 04:24:37,686 INFO L290 TraceCheckUtils]: 2: Hoare triple {47921#true} assume !false; {47921#true} is VALID [2022-02-21 04:24:37,686 INFO L290 TraceCheckUtils]: 3: Hoare triple {47921#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {47921#true} is VALID [2022-02-21 04:24:37,686 INFO L290 TraceCheckUtils]: 4: Hoare triple {47921#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {47921#true} is VALID [2022-02-21 04:24:37,687 INFO L290 TraceCheckUtils]: 5: Hoare triple {47921#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {47921#true} is VALID [2022-02-21 04:24:37,687 INFO L290 TraceCheckUtils]: 6: Hoare triple {47921#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {47921#true} is VALID [2022-02-21 04:24:37,687 INFO L290 TraceCheckUtils]: 7: Hoare triple {47921#true} assume !(0 != eval_~tmp~0#1); {47921#true} is VALID [2022-02-21 04:24:37,687 INFO L290 TraceCheckUtils]: 8: Hoare triple {47921#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {47921#true} is VALID [2022-02-21 04:24:37,687 INFO L290 TraceCheckUtils]: 9: Hoare triple {47921#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {47921#true} is VALID [2022-02-21 04:24:37,687 INFO L290 TraceCheckUtils]: 10: Hoare triple {47921#true} assume 0 == ~M_E~0;~M_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,688 INFO L290 TraceCheckUtils]: 11: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,688 INFO L290 TraceCheckUtils]: 12: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,688 INFO L290 TraceCheckUtils]: 13: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,689 INFO L290 TraceCheckUtils]: 14: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,689 INFO L290 TraceCheckUtils]: 15: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,689 INFO L290 TraceCheckUtils]: 16: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,690 INFO L290 TraceCheckUtils]: 17: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,690 INFO L290 TraceCheckUtils]: 18: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,690 INFO L290 TraceCheckUtils]: 19: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,690 INFO L290 TraceCheckUtils]: 20: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,691 INFO L290 TraceCheckUtils]: 21: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,691 INFO L290 TraceCheckUtils]: 22: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,691 INFO L290 TraceCheckUtils]: 23: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,691 INFO L290 TraceCheckUtils]: 24: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,692 INFO L290 TraceCheckUtils]: 25: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,692 INFO L290 TraceCheckUtils]: 26: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,692 INFO L290 TraceCheckUtils]: 27: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,693 INFO L290 TraceCheckUtils]: 28: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,693 INFO L290 TraceCheckUtils]: 29: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,693 INFO L290 TraceCheckUtils]: 30: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,693 INFO L290 TraceCheckUtils]: 31: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,694 INFO L290 TraceCheckUtils]: 32: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,694 INFO L290 TraceCheckUtils]: 33: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,694 INFO L290 TraceCheckUtils]: 34: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,695 INFO L290 TraceCheckUtils]: 35: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,695 INFO L290 TraceCheckUtils]: 36: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,695 INFO L290 TraceCheckUtils]: 37: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,695 INFO L290 TraceCheckUtils]: 38: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,696 INFO L290 TraceCheckUtils]: 39: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,696 INFO L290 TraceCheckUtils]: 40: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,696 INFO L290 TraceCheckUtils]: 41: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,697 INFO L290 TraceCheckUtils]: 42: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,697 INFO L290 TraceCheckUtils]: 43: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,697 INFO L290 TraceCheckUtils]: 44: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,697 INFO L290 TraceCheckUtils]: 45: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,698 INFO L290 TraceCheckUtils]: 46: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,698 INFO L290 TraceCheckUtils]: 47: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,698 INFO L290 TraceCheckUtils]: 48: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,699 INFO L290 TraceCheckUtils]: 49: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,699 INFO L290 TraceCheckUtils]: 50: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,699 INFO L290 TraceCheckUtils]: 51: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,699 INFO L290 TraceCheckUtils]: 52: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,700 INFO L290 TraceCheckUtils]: 53: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,700 INFO L290 TraceCheckUtils]: 54: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,700 INFO L290 TraceCheckUtils]: 55: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,701 INFO L290 TraceCheckUtils]: 56: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,701 INFO L290 TraceCheckUtils]: 57: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,701 INFO L290 TraceCheckUtils]: 58: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,702 INFO L290 TraceCheckUtils]: 59: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,702 INFO L290 TraceCheckUtils]: 60: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,702 INFO L290 TraceCheckUtils]: 61: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,702 INFO L290 TraceCheckUtils]: 62: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,703 INFO L290 TraceCheckUtils]: 63: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,703 INFO L290 TraceCheckUtils]: 64: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,703 INFO L290 TraceCheckUtils]: 65: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,704 INFO L290 TraceCheckUtils]: 66: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,704 INFO L290 TraceCheckUtils]: 67: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,704 INFO L290 TraceCheckUtils]: 68: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,704 INFO L290 TraceCheckUtils]: 69: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,705 INFO L290 TraceCheckUtils]: 70: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,705 INFO L290 TraceCheckUtils]: 71: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,705 INFO L290 TraceCheckUtils]: 72: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,706 INFO L290 TraceCheckUtils]: 73: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,706 INFO L290 TraceCheckUtils]: 74: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,706 INFO L290 TraceCheckUtils]: 75: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,706 INFO L290 TraceCheckUtils]: 76: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,707 INFO L290 TraceCheckUtils]: 77: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,707 INFO L290 TraceCheckUtils]: 78: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,707 INFO L290 TraceCheckUtils]: 79: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,708 INFO L290 TraceCheckUtils]: 80: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,708 INFO L290 TraceCheckUtils]: 81: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,708 INFO L290 TraceCheckUtils]: 82: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,708 INFO L290 TraceCheckUtils]: 83: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,709 INFO L290 TraceCheckUtils]: 84: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,709 INFO L290 TraceCheckUtils]: 85: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,709 INFO L290 TraceCheckUtils]: 86: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,710 INFO L290 TraceCheckUtils]: 87: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,710 INFO L290 TraceCheckUtils]: 88: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,710 INFO L290 TraceCheckUtils]: 89: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,710 INFO L290 TraceCheckUtils]: 90: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,711 INFO L290 TraceCheckUtils]: 91: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,711 INFO L290 TraceCheckUtils]: 92: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,711 INFO L290 TraceCheckUtils]: 93: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,712 INFO L290 TraceCheckUtils]: 94: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,712 INFO L290 TraceCheckUtils]: 95: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,712 INFO L290 TraceCheckUtils]: 96: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,712 INFO L290 TraceCheckUtils]: 97: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,713 INFO L290 TraceCheckUtils]: 98: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,713 INFO L290 TraceCheckUtils]: 99: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,713 INFO L290 TraceCheckUtils]: 100: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,714 INFO L290 TraceCheckUtils]: 101: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,714 INFO L290 TraceCheckUtils]: 102: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,714 INFO L290 TraceCheckUtils]: 103: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,714 INFO L290 TraceCheckUtils]: 104: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,715 INFO L290 TraceCheckUtils]: 105: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,715 INFO L290 TraceCheckUtils]: 106: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,715 INFO L290 TraceCheckUtils]: 107: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,716 INFO L290 TraceCheckUtils]: 108: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,716 INFO L290 TraceCheckUtils]: 109: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,716 INFO L290 TraceCheckUtils]: 110: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,716 INFO L290 TraceCheckUtils]: 111: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,717 INFO L290 TraceCheckUtils]: 112: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,717 INFO L290 TraceCheckUtils]: 113: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,717 INFO L290 TraceCheckUtils]: 114: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,718 INFO L290 TraceCheckUtils]: 115: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,718 INFO L290 TraceCheckUtils]: 116: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,718 INFO L290 TraceCheckUtils]: 117: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,718 INFO L290 TraceCheckUtils]: 118: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,719 INFO L290 TraceCheckUtils]: 119: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,719 INFO L290 TraceCheckUtils]: 120: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,719 INFO L290 TraceCheckUtils]: 121: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {47923#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:37,720 INFO L290 TraceCheckUtils]: 122: Hoare triple {47923#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {47922#false} is VALID [2022-02-21 04:24:37,720 INFO L290 TraceCheckUtils]: 123: Hoare triple {47922#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,720 INFO L290 TraceCheckUtils]: 124: Hoare triple {47922#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,720 INFO L290 TraceCheckUtils]: 125: Hoare triple {47922#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,720 INFO L290 TraceCheckUtils]: 126: Hoare triple {47922#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,720 INFO L290 TraceCheckUtils]: 127: Hoare triple {47922#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,720 INFO L290 TraceCheckUtils]: 128: Hoare triple {47922#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,720 INFO L290 TraceCheckUtils]: 129: Hoare triple {47922#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,721 INFO L290 TraceCheckUtils]: 130: Hoare triple {47922#false} assume !(1 == ~T8_E~0); {47922#false} is VALID [2022-02-21 04:24:37,721 INFO L290 TraceCheckUtils]: 131: Hoare triple {47922#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,721 INFO L290 TraceCheckUtils]: 132: Hoare triple {47922#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,721 INFO L290 TraceCheckUtils]: 133: Hoare triple {47922#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,721 INFO L290 TraceCheckUtils]: 134: Hoare triple {47922#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,721 INFO L290 TraceCheckUtils]: 135: Hoare triple {47922#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,721 INFO L290 TraceCheckUtils]: 136: Hoare triple {47922#false} assume 1 == ~E_1~0;~E_1~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,721 INFO L290 TraceCheckUtils]: 137: Hoare triple {47922#false} assume 1 == ~E_2~0;~E_2~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,721 INFO L290 TraceCheckUtils]: 138: Hoare triple {47922#false} assume !(1 == ~E_3~0); {47922#false} is VALID [2022-02-21 04:24:37,722 INFO L290 TraceCheckUtils]: 139: Hoare triple {47922#false} assume 1 == ~E_4~0;~E_4~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,722 INFO L290 TraceCheckUtils]: 140: Hoare triple {47922#false} assume 1 == ~E_5~0;~E_5~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,722 INFO L290 TraceCheckUtils]: 141: Hoare triple {47922#false} assume 1 == ~E_6~0;~E_6~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,722 INFO L290 TraceCheckUtils]: 142: Hoare triple {47922#false} assume 1 == ~E_7~0;~E_7~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,722 INFO L290 TraceCheckUtils]: 143: Hoare triple {47922#false} assume 1 == ~E_8~0;~E_8~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,722 INFO L290 TraceCheckUtils]: 144: Hoare triple {47922#false} assume 1 == ~E_9~0;~E_9~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,722 INFO L290 TraceCheckUtils]: 145: Hoare triple {47922#false} assume 1 == ~E_10~0;~E_10~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,722 INFO L290 TraceCheckUtils]: 146: Hoare triple {47922#false} assume !(1 == ~E_11~0); {47922#false} is VALID [2022-02-21 04:24:37,722 INFO L290 TraceCheckUtils]: 147: Hoare triple {47922#false} assume 1 == ~E_12~0;~E_12~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,723 INFO L290 TraceCheckUtils]: 148: Hoare triple {47922#false} assume 1 == ~E_13~0;~E_13~0 := 2; {47922#false} is VALID [2022-02-21 04:24:37,723 INFO L290 TraceCheckUtils]: 149: Hoare triple {47922#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {47922#false} is VALID [2022-02-21 04:24:37,723 INFO L290 TraceCheckUtils]: 150: Hoare triple {47922#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {47922#false} is VALID [2022-02-21 04:24:37,723 INFO L290 TraceCheckUtils]: 151: Hoare triple {47922#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {47922#false} is VALID [2022-02-21 04:24:37,723 INFO L290 TraceCheckUtils]: 152: Hoare triple {47922#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {47922#false} is VALID [2022-02-21 04:24:37,723 INFO L290 TraceCheckUtils]: 153: Hoare triple {47922#false} assume !(0 == start_simulation_~tmp~3#1); {47922#false} is VALID [2022-02-21 04:24:37,723 INFO L290 TraceCheckUtils]: 154: Hoare triple {47922#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {47922#false} is VALID [2022-02-21 04:24:37,723 INFO L290 TraceCheckUtils]: 155: Hoare triple {47922#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {47922#false} is VALID [2022-02-21 04:24:37,723 INFO L290 TraceCheckUtils]: 156: Hoare triple {47922#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {47922#false} is VALID [2022-02-21 04:24:37,724 INFO L290 TraceCheckUtils]: 157: Hoare triple {47922#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {47922#false} is VALID [2022-02-21 04:24:37,724 INFO L290 TraceCheckUtils]: 158: Hoare triple {47922#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {47922#false} is VALID [2022-02-21 04:24:37,724 INFO L290 TraceCheckUtils]: 159: Hoare triple {47922#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {47922#false} is VALID [2022-02-21 04:24:37,724 INFO L290 TraceCheckUtils]: 160: Hoare triple {47922#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {47922#false} is VALID [2022-02-21 04:24:37,724 INFO L290 TraceCheckUtils]: 161: Hoare triple {47922#false} assume !(0 != start_simulation_~tmp___0~1#1); {47922#false} is VALID [2022-02-21 04:24:37,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:37,725 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:37,725 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1017231729] [2022-02-21 04:24:37,725 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1017231729] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:37,725 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:37,725 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:37,725 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229058889] [2022-02-21 04:24:37,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:37,726 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:37,726 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:37,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:37,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:37,727 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:38,857 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-02-21 04:24:38,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:38,857 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,919 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:38,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:39,001 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:39,079 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-02-21 04:24:39,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:39,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:39,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:39,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:39,082 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-02-21 04:24:39,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:39,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:39,099 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:39,101 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2829 transitions. Second operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,102 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2829 transitions. Second operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,104 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. Second operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:39,180 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-02-21 04:24:39,180 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:39,181 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:39,181 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:39,184 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2829 transitions. [2022-02-21 04:24:39,185 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2829 transitions. [2022-02-21 04:24:39,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:39,262 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-02-21 04:24:39,262 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:39,264 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:39,264 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:39,264 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:39,264 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:39,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-02-21 04:24:39,342 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-02-21 04:24:39,342 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-02-21 04:24:39,342 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:39,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:39,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:39,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:39,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:39,347 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:39,347 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:39,347 INFO L791 eck$LassoCheckResult]: Stem: 50699#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50700#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50519#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50235#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50236#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51412#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51413#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50371#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50372#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50828#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50661#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50662#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 50438#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 50439#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50837#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 51014#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 51168#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 51205#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50451#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50452#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51625#L1258-2 assume !(0 == ~T1_E~0); 50744#L1263-1 assume !(0 == ~T2_E~0); 50745#L1268-1 assume !(0 == ~T3_E~0); 51048#L1273-1 assume !(0 == ~T4_E~0); 51607#L1278-1 assume !(0 == ~T5_E~0); 51468#L1283-1 assume !(0 == ~T6_E~0); 51469#L1288-1 assume !(0 == ~T7_E~0); 51705#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51693#L1298-1 assume !(0 == ~T9_E~0); 51619#L1303-1 assume !(0 == ~T10_E~0); 50264#L1308-1 assume !(0 == ~T11_E~0); 50206#L1313-1 assume !(0 == ~T12_E~0); 50207#L1318-1 assume !(0 == ~T13_E~0); 50215#L1323-1 assume !(0 == ~E_1~0); 50216#L1328-1 assume !(0 == ~E_2~0); 50381#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51340#L1338-1 assume !(0 == ~E_4~0); 51341#L1343-1 assume !(0 == ~E_5~0); 51442#L1348-1 assume !(0 == ~E_6~0); 51728#L1353-1 assume !(0 == ~E_7~0); 51067#L1358-1 assume !(0 == ~E_8~0); 51068#L1363-1 assume !(0 == ~E_9~0); 51358#L1368-1 assume !(0 == ~E_10~0); 50043#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50044#L1378-1 assume !(0 == ~E_12~0); 50332#L1383-1 assume !(0 == ~E_13~0); 50333#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51074#L607 assume 1 == ~m_pc~0; 51075#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50401#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51440#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50994#L1560 assume !(0 != activate_threads_~tmp~1#1); 50995#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50226#L626 assume !(1 == ~t1_pc~0); 50227#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50495#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50496#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50665#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50126#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50127#L645 assume 1 == ~t2_pc~0; 50243#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50200#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50880#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50881#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 50970#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50971#L664 assume 1 == ~t3_pc~0; 51727#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49967#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49968#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50626#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50627#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51635#L683 assume !(1 == ~t4_pc~0); 51190#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51142#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51143#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51177#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51301#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50921#L702 assume 1 == ~t5_pc~0; 50922#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50846#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51296#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51595#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51536#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50015#L721 assume !(1 == ~t6_pc~0); 49989#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49990#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50153#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50635#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50636#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51237#L740 assume 1 == ~t7_pc~0; 50064#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49877#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49878#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49867#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49868#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50572#L759 assume !(1 == ~t8_pc~0); 50573#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50601#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51294#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51295#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51426#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51704#L778 assume 1 == ~t9_pc~0; 51591#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50042#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49982#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49911#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49912#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50240#L797 assume !(1 == ~t10_pc~0); 50241#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50358#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51492#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50742#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50743#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51032#L816 assume 1 == ~t11_pc~0; 49947#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49948#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50705#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50642#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50643#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51167#L835 assume 1 == ~t12_pc~0; 51045#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50111#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50133#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50274#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50799#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50800#L854 assume !(1 == ~t13_pc~0); 50440#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50441#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50491#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50151#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50152#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51531#L1401 assume !(1 == ~M_E~0); 50630#L1401-2 assume !(1 == ~T1_E~0); 50631#L1406-1 assume !(1 == ~T2_E~0); 51226#L1411-1 assume !(1 == ~T3_E~0); 51227#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50893#L1421-1 assume !(1 == ~T5_E~0); 50436#L1426-1 assume !(1 == ~T6_E~0); 50437#L1431-1 assume !(1 == ~T7_E~0); 49985#L1436-1 assume !(1 == ~T8_E~0); 49986#L1441-1 assume !(1 == ~T9_E~0); 50735#L1446-1 assume !(1 == ~T10_E~0); 50736#L1451-1 assume !(1 == ~T11_E~0); 51439#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51093#L1461-1 assume !(1 == ~T13_E~0); 50654#L1466-1 assume !(1 == ~E_1~0); 50655#L1471-1 assume !(1 == ~E_2~0); 51424#L1476-1 assume !(1 == ~E_3~0); 51425#L1481-1 assume !(1 == ~E_4~0); 51573#L1486-1 assume !(1 == ~E_5~0); 50279#L1491-1 assume !(1 == ~E_6~0); 49919#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49920#L1501-1 assume !(1 == ~E_8~0); 50731#L1506-1 assume !(1 == ~E_9~0); 50732#L1511-1 assume !(1 == ~E_10~0); 50688#L1516-1 assume !(1 == ~E_11~0); 49863#L1521-1 assume !(1 == ~E_12~0); 49864#L1526-1 assume !(1 == ~E_13~0); 49918#L1531-1 assume { :end_inline_reset_delta_events } true; 50461#L1892-2 [2022-02-21 04:24:39,347 INFO L793 eck$LassoCheckResult]: Loop: 50461#L1892-2 assume !false; 51484#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51682#L1233 assume !false; 51665#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50997#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50977#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51135#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49961#L1046 assume !(0 != eval_~tmp~0#1); 49963#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49997#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51169#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51726#L1258-5 assume !(0 == ~T1_E~0); 50139#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50140#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51718#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51724#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51725#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50363#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50364#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51481#L1298-3 assume !(0 == ~T9_E~0); 51482#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51641#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51480#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50981#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50141#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50142#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51565#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50284#L1338-3 assume !(0 == ~E_4~0); 50285#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51397#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51571#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51572#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50939#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50497#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50498#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51254#L1378-3 assume !(0 == ~E_12~0); 51255#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51436#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51437#L607-42 assume 1 == ~m_pc~0; 51052#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50778#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50779#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50511#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50512#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51036#L626-42 assume 1 == ~t1_pc~0; 50598#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50599#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50900#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50901#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50175#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50176#L645-42 assume 1 == ~t2_pc~0; 51634#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51376#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51541#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50382#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49889#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49890#L664-42 assume !(1 == ~t3_pc~0); 50417#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 50418#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51668#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51203#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51204#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51369#L683-42 assume 1 == ~t4_pc~0; 51734#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51080#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51210#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51630#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51631#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51478#L702-42 assume 1 == ~t5_pc~0; 50966#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50588#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50886#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51557#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 49905#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49906#L721-42 assume 1 == ~t6_pc~0; 50058#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50079#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50543#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51710#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50715#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50559#L740-42 assume 1 == ~t7_pc~0; 50560#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50296#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50840#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50695#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50696#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50969#L759-42 assume 1 == ~t8_pc~0; 50818#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50750#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50751#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50826#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50827#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50920#L778-42 assume 1 == ~t9_pc~0; 50762#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50764#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51172#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51076#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51077#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51137#L797-42 assume 1 == ~t10_pc~0; 50304#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50305#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51306#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51615#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51175#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51176#L816-42 assume 1 == ~t11_pc~0; 49853#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49854#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50396#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50397#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50476#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50477#L835-42 assume !(1 == ~t12_pc~0); 50770#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50771#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50449#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50450#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51534#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51318#L854-42 assume 1 == ~t13_pc~0; 51319#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50393#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50005#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50006#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50652#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50653#L1401-3 assume !(1 == ~M_E~0); 51431#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50239#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50106#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50107#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50706#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50707#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50282#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50283#L1436-3 assume !(1 == ~T8_E~0); 49869#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49870#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51459#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50790#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50443#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50444#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51721#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50383#L1476-3 assume !(1 == ~E_3~0); 50384#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50784#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50411#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50412#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50823#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50824#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51251#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51240#L1516-3 assume !(1 == ~E_11~0); 51241#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50941#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50942#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51336#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50218#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51111#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50752#L1911 assume !(0 == start_simulation_~tmp~3#1); 50753#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51275#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50343#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51213#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50047#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50048#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50277#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 50278#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50461#L1892-2 [2022-02-21 04:24:39,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:39,348 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2022-02-21 04:24:39,348 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:39,348 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805952411] [2022-02-21 04:24:39,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:39,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:39,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:39,368 INFO L290 TraceCheckUtils]: 0: Hoare triple {55583#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {55583#true} is VALID [2022-02-21 04:24:39,368 INFO L290 TraceCheckUtils]: 1: Hoare triple {55583#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,369 INFO L290 TraceCheckUtils]: 2: Hoare triple {55585#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,369 INFO L290 TraceCheckUtils]: 3: Hoare triple {55585#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,369 INFO L290 TraceCheckUtils]: 4: Hoare triple {55585#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,369 INFO L290 TraceCheckUtils]: 5: Hoare triple {55585#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,370 INFO L290 TraceCheckUtils]: 6: Hoare triple {55585#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,370 INFO L290 TraceCheckUtils]: 7: Hoare triple {55585#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,370 INFO L290 TraceCheckUtils]: 8: Hoare triple {55585#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,370 INFO L290 TraceCheckUtils]: 9: Hoare triple {55585#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,371 INFO L290 TraceCheckUtils]: 10: Hoare triple {55585#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {55585#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:39,371 INFO L290 TraceCheckUtils]: 11: Hoare triple {55585#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {55584#false} is VALID [2022-02-21 04:24:39,371 INFO L290 TraceCheckUtils]: 12: Hoare triple {55584#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {55584#false} is VALID [2022-02-21 04:24:39,371 INFO L290 TraceCheckUtils]: 13: Hoare triple {55584#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {55584#false} is VALID [2022-02-21 04:24:39,371 INFO L290 TraceCheckUtils]: 14: Hoare triple {55584#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {55584#false} is VALID [2022-02-21 04:24:39,371 INFO L290 TraceCheckUtils]: 15: Hoare triple {55584#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {55584#false} is VALID [2022-02-21 04:24:39,372 INFO L290 TraceCheckUtils]: 16: Hoare triple {55584#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {55584#false} is VALID [2022-02-21 04:24:39,372 INFO L290 TraceCheckUtils]: 17: Hoare triple {55584#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {55584#false} is VALID [2022-02-21 04:24:39,372 INFO L290 TraceCheckUtils]: 18: Hoare triple {55584#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {55584#false} is VALID [2022-02-21 04:24:39,372 INFO L290 TraceCheckUtils]: 19: Hoare triple {55584#false} assume 0 == ~M_E~0;~M_E~0 := 1; {55584#false} is VALID [2022-02-21 04:24:39,372 INFO L290 TraceCheckUtils]: 20: Hoare triple {55584#false} assume !(0 == ~T1_E~0); {55584#false} is VALID [2022-02-21 04:24:39,372 INFO L290 TraceCheckUtils]: 21: Hoare triple {55584#false} assume !(0 == ~T2_E~0); {55584#false} is VALID [2022-02-21 04:24:39,372 INFO L290 TraceCheckUtils]: 22: Hoare triple {55584#false} assume !(0 == ~T3_E~0); {55584#false} is VALID [2022-02-21 04:24:39,372 INFO L290 TraceCheckUtils]: 23: Hoare triple {55584#false} assume !(0 == ~T4_E~0); {55584#false} is VALID [2022-02-21 04:24:39,373 INFO L290 TraceCheckUtils]: 24: Hoare triple {55584#false} assume !(0 == ~T5_E~0); {55584#false} is VALID [2022-02-21 04:24:39,373 INFO L290 TraceCheckUtils]: 25: Hoare triple {55584#false} assume !(0 == ~T6_E~0); {55584#false} is VALID [2022-02-21 04:24:39,373 INFO L290 TraceCheckUtils]: 26: Hoare triple {55584#false} assume !(0 == ~T7_E~0); {55584#false} is VALID [2022-02-21 04:24:39,373 INFO L290 TraceCheckUtils]: 27: Hoare triple {55584#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {55584#false} is VALID [2022-02-21 04:24:39,373 INFO L290 TraceCheckUtils]: 28: Hoare triple {55584#false} assume !(0 == ~T9_E~0); {55584#false} is VALID [2022-02-21 04:24:39,373 INFO L290 TraceCheckUtils]: 29: Hoare triple {55584#false} assume !(0 == ~T10_E~0); {55584#false} is VALID [2022-02-21 04:24:39,373 INFO L290 TraceCheckUtils]: 30: Hoare triple {55584#false} assume !(0 == ~T11_E~0); {55584#false} is VALID [2022-02-21 04:24:39,373 INFO L290 TraceCheckUtils]: 31: Hoare triple {55584#false} assume !(0 == ~T12_E~0); {55584#false} is VALID [2022-02-21 04:24:39,373 INFO L290 TraceCheckUtils]: 32: Hoare triple {55584#false} assume !(0 == ~T13_E~0); {55584#false} is VALID [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 33: Hoare triple {55584#false} assume !(0 == ~E_1~0); {55584#false} is VALID [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 34: Hoare triple {55584#false} assume !(0 == ~E_2~0); {55584#false} is VALID [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 35: Hoare triple {55584#false} assume 0 == ~E_3~0;~E_3~0 := 1; {55584#false} is VALID [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 36: Hoare triple {55584#false} assume !(0 == ~E_4~0); {55584#false} is VALID [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 37: Hoare triple {55584#false} assume !(0 == ~E_5~0); {55584#false} is VALID [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 38: Hoare triple {55584#false} assume !(0 == ~E_6~0); {55584#false} is VALID [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 39: Hoare triple {55584#false} assume !(0 == ~E_7~0); {55584#false} is VALID [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 40: Hoare triple {55584#false} assume !(0 == ~E_8~0); {55584#false} is VALID [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 41: Hoare triple {55584#false} assume !(0 == ~E_9~0); {55584#false} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 42: Hoare triple {55584#false} assume !(0 == ~E_10~0); {55584#false} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 43: Hoare triple {55584#false} assume 0 == ~E_11~0;~E_11~0 := 1; {55584#false} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 44: Hoare triple {55584#false} assume !(0 == ~E_12~0); {55584#false} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 45: Hoare triple {55584#false} assume !(0 == ~E_13~0); {55584#false} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 46: Hoare triple {55584#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55584#false} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 47: Hoare triple {55584#false} assume 1 == ~m_pc~0; {55584#false} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 48: Hoare triple {55584#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {55584#false} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 49: Hoare triple {55584#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55584#false} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 50: Hoare triple {55584#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {55584#false} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 51: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp~1#1); {55584#false} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 52: Hoare triple {55584#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55584#false} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 53: Hoare triple {55584#false} assume !(1 == ~t1_pc~0); {55584#false} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 54: Hoare triple {55584#false} is_transmit1_triggered_~__retres1~1#1 := 0; {55584#false} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 55: Hoare triple {55584#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55584#false} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 56: Hoare triple {55584#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {55584#false} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 57: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___0~0#1); {55584#false} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 58: Hoare triple {55584#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55584#false} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 59: Hoare triple {55584#false} assume 1 == ~t2_pc~0; {55584#false} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 60: Hoare triple {55584#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {55584#false} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 61: Hoare triple {55584#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55584#false} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 62: Hoare triple {55584#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {55584#false} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 63: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___1~0#1); {55584#false} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 64: Hoare triple {55584#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55584#false} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 65: Hoare triple {55584#false} assume 1 == ~t3_pc~0; {55584#false} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 66: Hoare triple {55584#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {55584#false} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 67: Hoare triple {55584#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55584#false} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 68: Hoare triple {55584#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {55584#false} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 69: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___2~0#1); {55584#false} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 70: Hoare triple {55584#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55584#false} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 71: Hoare triple {55584#false} assume !(1 == ~t4_pc~0); {55584#false} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 72: Hoare triple {55584#false} is_transmit4_triggered_~__retres1~4#1 := 0; {55584#false} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 73: Hoare triple {55584#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55584#false} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 74: Hoare triple {55584#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {55584#false} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 75: Hoare triple {55584#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {55584#false} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 76: Hoare triple {55584#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {55584#false} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 77: Hoare triple {55584#false} assume 1 == ~t5_pc~0; {55584#false} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 78: Hoare triple {55584#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {55584#false} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 79: Hoare triple {55584#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {55584#false} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 80: Hoare triple {55584#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {55584#false} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 81: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___4~0#1); {55584#false} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 82: Hoare triple {55584#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {55584#false} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 83: Hoare triple {55584#false} assume !(1 == ~t6_pc~0); {55584#false} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 84: Hoare triple {55584#false} is_transmit6_triggered_~__retres1~6#1 := 0; {55584#false} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 85: Hoare triple {55584#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {55584#false} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 86: Hoare triple {55584#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {55584#false} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 87: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___5~0#1); {55584#false} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 88: Hoare triple {55584#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {55584#false} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 89: Hoare triple {55584#false} assume 1 == ~t7_pc~0; {55584#false} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 90: Hoare triple {55584#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {55584#false} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 91: Hoare triple {55584#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {55584#false} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 92: Hoare triple {55584#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {55584#false} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 93: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___6~0#1); {55584#false} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 94: Hoare triple {55584#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {55584#false} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 95: Hoare triple {55584#false} assume !(1 == ~t8_pc~0); {55584#false} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 96: Hoare triple {55584#false} is_transmit8_triggered_~__retres1~8#1 := 0; {55584#false} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 97: Hoare triple {55584#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {55584#false} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 98: Hoare triple {55584#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {55584#false} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 99: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___7~0#1); {55584#false} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 100: Hoare triple {55584#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {55584#false} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 101: Hoare triple {55584#false} assume 1 == ~t9_pc~0; {55584#false} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 102: Hoare triple {55584#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {55584#false} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 103: Hoare triple {55584#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {55584#false} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 104: Hoare triple {55584#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {55584#false} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 105: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___8~0#1); {55584#false} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 106: Hoare triple {55584#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {55584#false} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 107: Hoare triple {55584#false} assume !(1 == ~t10_pc~0); {55584#false} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 108: Hoare triple {55584#false} is_transmit10_triggered_~__retres1~10#1 := 0; {55584#false} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 109: Hoare triple {55584#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {55584#false} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 110: Hoare triple {55584#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {55584#false} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 111: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___9~0#1); {55584#false} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 112: Hoare triple {55584#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {55584#false} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 113: Hoare triple {55584#false} assume 1 == ~t11_pc~0; {55584#false} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 114: Hoare triple {55584#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {55584#false} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 115: Hoare triple {55584#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {55584#false} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 116: Hoare triple {55584#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {55584#false} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 117: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___10~0#1); {55584#false} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 118: Hoare triple {55584#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {55584#false} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 119: Hoare triple {55584#false} assume 1 == ~t12_pc~0; {55584#false} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 120: Hoare triple {55584#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {55584#false} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 121: Hoare triple {55584#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {55584#false} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 122: Hoare triple {55584#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {55584#false} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 123: Hoare triple {55584#false} assume !(0 != activate_threads_~tmp___11~0#1); {55584#false} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 124: Hoare triple {55584#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {55584#false} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 125: Hoare triple {55584#false} assume !(1 == ~t13_pc~0); {55584#false} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 126: Hoare triple {55584#false} is_transmit13_triggered_~__retres1~13#1 := 0; {55584#false} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 127: Hoare triple {55584#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {55584#false} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 128: Hoare triple {55584#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {55584#false} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 129: Hoare triple {55584#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {55584#false} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 130: Hoare triple {55584#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55584#false} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 131: Hoare triple {55584#false} assume !(1 == ~M_E~0); {55584#false} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 132: Hoare triple {55584#false} assume !(1 == ~T1_E~0); {55584#false} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 133: Hoare triple {55584#false} assume !(1 == ~T2_E~0); {55584#false} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 134: Hoare triple {55584#false} assume !(1 == ~T3_E~0); {55584#false} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 135: Hoare triple {55584#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {55584#false} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 136: Hoare triple {55584#false} assume !(1 == ~T5_E~0); {55584#false} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 137: Hoare triple {55584#false} assume !(1 == ~T6_E~0); {55584#false} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 138: Hoare triple {55584#false} assume !(1 == ~T7_E~0); {55584#false} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 139: Hoare triple {55584#false} assume !(1 == ~T8_E~0); {55584#false} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 140: Hoare triple {55584#false} assume !(1 == ~T9_E~0); {55584#false} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 141: Hoare triple {55584#false} assume !(1 == ~T10_E~0); {55584#false} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 142: Hoare triple {55584#false} assume !(1 == ~T11_E~0); {55584#false} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 143: Hoare triple {55584#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {55584#false} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 144: Hoare triple {55584#false} assume !(1 == ~T13_E~0); {55584#false} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 145: Hoare triple {55584#false} assume !(1 == ~E_1~0); {55584#false} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 146: Hoare triple {55584#false} assume !(1 == ~E_2~0); {55584#false} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 147: Hoare triple {55584#false} assume !(1 == ~E_3~0); {55584#false} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 148: Hoare triple {55584#false} assume !(1 == ~E_4~0); {55584#false} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 149: Hoare triple {55584#false} assume !(1 == ~E_5~0); {55584#false} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 150: Hoare triple {55584#false} assume !(1 == ~E_6~0); {55584#false} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 151: Hoare triple {55584#false} assume 1 == ~E_7~0;~E_7~0 := 2; {55584#false} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 152: Hoare triple {55584#false} assume !(1 == ~E_8~0); {55584#false} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 153: Hoare triple {55584#false} assume !(1 == ~E_9~0); {55584#false} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 154: Hoare triple {55584#false} assume !(1 == ~E_10~0); {55584#false} is VALID [2022-02-21 04:24:39,388 INFO L290 TraceCheckUtils]: 155: Hoare triple {55584#false} assume !(1 == ~E_11~0); {55584#false} is VALID [2022-02-21 04:24:39,388 INFO L290 TraceCheckUtils]: 156: Hoare triple {55584#false} assume !(1 == ~E_12~0); {55584#false} is VALID [2022-02-21 04:24:39,388 INFO L290 TraceCheckUtils]: 157: Hoare triple {55584#false} assume !(1 == ~E_13~0); {55584#false} is VALID [2022-02-21 04:24:39,388 INFO L290 TraceCheckUtils]: 158: Hoare triple {55584#false} assume { :end_inline_reset_delta_events } true; {55584#false} is VALID [2022-02-21 04:24:39,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:39,388 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:39,389 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1805952411] [2022-02-21 04:24:39,389 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1805952411] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:39,389 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:39,389 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:39,389 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563851044] [2022-02-21 04:24:39,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:39,390 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:39,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:39,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1482892115, now seen corresponding path program 1 times [2022-02-21 04:24:39,390 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:39,390 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098558208] [2022-02-21 04:24:39,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:39,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:39,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:39,416 INFO L290 TraceCheckUtils]: 0: Hoare triple {55586#true} assume !false; {55586#true} is VALID [2022-02-21 04:24:39,416 INFO L290 TraceCheckUtils]: 1: Hoare triple {55586#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {55586#true} is VALID [2022-02-21 04:24:39,416 INFO L290 TraceCheckUtils]: 2: Hoare triple {55586#true} assume !false; {55586#true} is VALID [2022-02-21 04:24:39,416 INFO L290 TraceCheckUtils]: 3: Hoare triple {55586#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {55586#true} is VALID [2022-02-21 04:24:39,416 INFO L290 TraceCheckUtils]: 4: Hoare triple {55586#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {55586#true} is VALID [2022-02-21 04:24:39,417 INFO L290 TraceCheckUtils]: 5: Hoare triple {55586#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {55586#true} is VALID [2022-02-21 04:24:39,417 INFO L290 TraceCheckUtils]: 6: Hoare triple {55586#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {55586#true} is VALID [2022-02-21 04:24:39,417 INFO L290 TraceCheckUtils]: 7: Hoare triple {55586#true} assume !(0 != eval_~tmp~0#1); {55586#true} is VALID [2022-02-21 04:24:39,417 INFO L290 TraceCheckUtils]: 8: Hoare triple {55586#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {55586#true} is VALID [2022-02-21 04:24:39,417 INFO L290 TraceCheckUtils]: 9: Hoare triple {55586#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {55586#true} is VALID [2022-02-21 04:24:39,417 INFO L290 TraceCheckUtils]: 10: Hoare triple {55586#true} assume 0 == ~M_E~0;~M_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,418 INFO L290 TraceCheckUtils]: 11: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,418 INFO L290 TraceCheckUtils]: 12: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,418 INFO L290 TraceCheckUtils]: 13: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,418 INFO L290 TraceCheckUtils]: 14: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,419 INFO L290 TraceCheckUtils]: 15: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,419 INFO L290 TraceCheckUtils]: 16: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,419 INFO L290 TraceCheckUtils]: 17: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,420 INFO L290 TraceCheckUtils]: 18: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,420 INFO L290 TraceCheckUtils]: 19: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,420 INFO L290 TraceCheckUtils]: 20: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,420 INFO L290 TraceCheckUtils]: 21: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,421 INFO L290 TraceCheckUtils]: 22: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,421 INFO L290 TraceCheckUtils]: 23: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,421 INFO L290 TraceCheckUtils]: 24: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,421 INFO L290 TraceCheckUtils]: 25: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,422 INFO L290 TraceCheckUtils]: 26: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,422 INFO L290 TraceCheckUtils]: 27: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,422 INFO L290 TraceCheckUtils]: 28: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,422 INFO L290 TraceCheckUtils]: 29: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,423 INFO L290 TraceCheckUtils]: 30: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,423 INFO L290 TraceCheckUtils]: 31: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,423 INFO L290 TraceCheckUtils]: 32: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,424 INFO L290 TraceCheckUtils]: 33: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,424 INFO L290 TraceCheckUtils]: 34: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,424 INFO L290 TraceCheckUtils]: 35: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,424 INFO L290 TraceCheckUtils]: 36: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,425 INFO L290 TraceCheckUtils]: 37: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,425 INFO L290 TraceCheckUtils]: 38: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,425 INFO L290 TraceCheckUtils]: 39: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,425 INFO L290 TraceCheckUtils]: 40: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,426 INFO L290 TraceCheckUtils]: 41: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,426 INFO L290 TraceCheckUtils]: 42: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,426 INFO L290 TraceCheckUtils]: 43: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,426 INFO L290 TraceCheckUtils]: 44: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,427 INFO L290 TraceCheckUtils]: 45: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,427 INFO L290 TraceCheckUtils]: 46: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,427 INFO L290 TraceCheckUtils]: 47: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,428 INFO L290 TraceCheckUtils]: 48: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,428 INFO L290 TraceCheckUtils]: 49: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,428 INFO L290 TraceCheckUtils]: 50: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,428 INFO L290 TraceCheckUtils]: 51: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,429 INFO L290 TraceCheckUtils]: 52: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,429 INFO L290 TraceCheckUtils]: 53: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,429 INFO L290 TraceCheckUtils]: 54: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,429 INFO L290 TraceCheckUtils]: 55: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,430 INFO L290 TraceCheckUtils]: 56: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,430 INFO L290 TraceCheckUtils]: 57: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,430 INFO L290 TraceCheckUtils]: 58: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,430 INFO L290 TraceCheckUtils]: 59: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,431 INFO L290 TraceCheckUtils]: 60: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,431 INFO L290 TraceCheckUtils]: 61: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,431 INFO L290 TraceCheckUtils]: 62: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,432 INFO L290 TraceCheckUtils]: 63: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,432 INFO L290 TraceCheckUtils]: 64: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,432 INFO L290 TraceCheckUtils]: 65: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,432 INFO L290 TraceCheckUtils]: 66: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,433 INFO L290 TraceCheckUtils]: 67: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,433 INFO L290 TraceCheckUtils]: 68: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,433 INFO L290 TraceCheckUtils]: 69: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,433 INFO L290 TraceCheckUtils]: 70: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,434 INFO L290 TraceCheckUtils]: 71: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,434 INFO L290 TraceCheckUtils]: 72: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,434 INFO L290 TraceCheckUtils]: 73: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,434 INFO L290 TraceCheckUtils]: 74: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,435 INFO L290 TraceCheckUtils]: 75: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,435 INFO L290 TraceCheckUtils]: 76: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,435 INFO L290 TraceCheckUtils]: 77: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,435 INFO L290 TraceCheckUtils]: 78: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,436 INFO L290 TraceCheckUtils]: 79: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,436 INFO L290 TraceCheckUtils]: 80: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,436 INFO L290 TraceCheckUtils]: 81: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,437 INFO L290 TraceCheckUtils]: 82: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,437 INFO L290 TraceCheckUtils]: 83: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,437 INFO L290 TraceCheckUtils]: 84: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,437 INFO L290 TraceCheckUtils]: 85: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,438 INFO L290 TraceCheckUtils]: 86: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,438 INFO L290 TraceCheckUtils]: 87: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,438 INFO L290 TraceCheckUtils]: 88: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,438 INFO L290 TraceCheckUtils]: 89: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,439 INFO L290 TraceCheckUtils]: 90: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,439 INFO L290 TraceCheckUtils]: 91: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,439 INFO L290 TraceCheckUtils]: 92: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,439 INFO L290 TraceCheckUtils]: 93: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,440 INFO L290 TraceCheckUtils]: 94: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,440 INFO L290 TraceCheckUtils]: 95: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,440 INFO L290 TraceCheckUtils]: 96: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,440 INFO L290 TraceCheckUtils]: 97: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,441 INFO L290 TraceCheckUtils]: 98: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,441 INFO L290 TraceCheckUtils]: 99: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,441 INFO L290 TraceCheckUtils]: 100: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,441 INFO L290 TraceCheckUtils]: 101: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,442 INFO L290 TraceCheckUtils]: 102: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,442 INFO L290 TraceCheckUtils]: 103: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,442 INFO L290 TraceCheckUtils]: 104: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,443 INFO L290 TraceCheckUtils]: 105: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,443 INFO L290 TraceCheckUtils]: 106: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,443 INFO L290 TraceCheckUtils]: 107: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,443 INFO L290 TraceCheckUtils]: 108: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,444 INFO L290 TraceCheckUtils]: 109: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,444 INFO L290 TraceCheckUtils]: 110: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,444 INFO L290 TraceCheckUtils]: 111: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,444 INFO L290 TraceCheckUtils]: 112: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,445 INFO L290 TraceCheckUtils]: 113: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,445 INFO L290 TraceCheckUtils]: 114: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,445 INFO L290 TraceCheckUtils]: 115: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,445 INFO L290 TraceCheckUtils]: 116: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,446 INFO L290 TraceCheckUtils]: 117: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,446 INFO L290 TraceCheckUtils]: 118: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,446 INFO L290 TraceCheckUtils]: 119: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,446 INFO L290 TraceCheckUtils]: 120: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,447 INFO L290 TraceCheckUtils]: 121: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55588#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:39,447 INFO L290 TraceCheckUtils]: 122: Hoare triple {55588#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {55587#false} is VALID [2022-02-21 04:24:39,447 INFO L290 TraceCheckUtils]: 123: Hoare triple {55587#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,447 INFO L290 TraceCheckUtils]: 124: Hoare triple {55587#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,447 INFO L290 TraceCheckUtils]: 125: Hoare triple {55587#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 126: Hoare triple {55587#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 127: Hoare triple {55587#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 128: Hoare triple {55587#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 129: Hoare triple {55587#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 130: Hoare triple {55587#false} assume !(1 == ~T8_E~0); {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 131: Hoare triple {55587#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 132: Hoare triple {55587#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 133: Hoare triple {55587#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 134: Hoare triple {55587#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,448 INFO L290 TraceCheckUtils]: 135: Hoare triple {55587#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,449 INFO L290 TraceCheckUtils]: 136: Hoare triple {55587#false} assume 1 == ~E_1~0;~E_1~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,449 INFO L290 TraceCheckUtils]: 137: Hoare triple {55587#false} assume 1 == ~E_2~0;~E_2~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,449 INFO L290 TraceCheckUtils]: 138: Hoare triple {55587#false} assume !(1 == ~E_3~0); {55587#false} is VALID [2022-02-21 04:24:39,449 INFO L290 TraceCheckUtils]: 139: Hoare triple {55587#false} assume 1 == ~E_4~0;~E_4~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,449 INFO L290 TraceCheckUtils]: 140: Hoare triple {55587#false} assume 1 == ~E_5~0;~E_5~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,449 INFO L290 TraceCheckUtils]: 141: Hoare triple {55587#false} assume 1 == ~E_6~0;~E_6~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,449 INFO L290 TraceCheckUtils]: 142: Hoare triple {55587#false} assume 1 == ~E_7~0;~E_7~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,449 INFO L290 TraceCheckUtils]: 143: Hoare triple {55587#false} assume 1 == ~E_8~0;~E_8~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,449 INFO L290 TraceCheckUtils]: 144: Hoare triple {55587#false} assume 1 == ~E_9~0;~E_9~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,450 INFO L290 TraceCheckUtils]: 145: Hoare triple {55587#false} assume 1 == ~E_10~0;~E_10~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,450 INFO L290 TraceCheckUtils]: 146: Hoare triple {55587#false} assume !(1 == ~E_11~0); {55587#false} is VALID [2022-02-21 04:24:39,450 INFO L290 TraceCheckUtils]: 147: Hoare triple {55587#false} assume 1 == ~E_12~0;~E_12~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,450 INFO L290 TraceCheckUtils]: 148: Hoare triple {55587#false} assume 1 == ~E_13~0;~E_13~0 := 2; {55587#false} is VALID [2022-02-21 04:24:39,450 INFO L290 TraceCheckUtils]: 149: Hoare triple {55587#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {55587#false} is VALID [2022-02-21 04:24:39,450 INFO L290 TraceCheckUtils]: 150: Hoare triple {55587#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {55587#false} is VALID [2022-02-21 04:24:39,450 INFO L290 TraceCheckUtils]: 151: Hoare triple {55587#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {55587#false} is VALID [2022-02-21 04:24:39,450 INFO L290 TraceCheckUtils]: 152: Hoare triple {55587#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {55587#false} is VALID [2022-02-21 04:24:39,451 INFO L290 TraceCheckUtils]: 153: Hoare triple {55587#false} assume !(0 == start_simulation_~tmp~3#1); {55587#false} is VALID [2022-02-21 04:24:39,451 INFO L290 TraceCheckUtils]: 154: Hoare triple {55587#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {55587#false} is VALID [2022-02-21 04:24:39,451 INFO L290 TraceCheckUtils]: 155: Hoare triple {55587#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {55587#false} is VALID [2022-02-21 04:24:39,451 INFO L290 TraceCheckUtils]: 156: Hoare triple {55587#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {55587#false} is VALID [2022-02-21 04:24:39,451 INFO L290 TraceCheckUtils]: 157: Hoare triple {55587#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {55587#false} is VALID [2022-02-21 04:24:39,451 INFO L290 TraceCheckUtils]: 158: Hoare triple {55587#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {55587#false} is VALID [2022-02-21 04:24:39,451 INFO L290 TraceCheckUtils]: 159: Hoare triple {55587#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {55587#false} is VALID [2022-02-21 04:24:39,451 INFO L290 TraceCheckUtils]: 160: Hoare triple {55587#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {55587#false} is VALID [2022-02-21 04:24:39,451 INFO L290 TraceCheckUtils]: 161: Hoare triple {55587#false} assume !(0 != start_simulation_~tmp___0~1#1); {55587#false} is VALID [2022-02-21 04:24:39,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:39,452 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:39,454 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1098558208] [2022-02-21 04:24:39,456 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1098558208] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:39,456 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:39,456 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:39,456 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315334596] [2022-02-21 04:24:39,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:39,457 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:39,457 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:39,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:39,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:39,458 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:40,880 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-02-21 04:24:40,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:40,881 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,982 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:40,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:41,073 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:41,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-02-21 04:24:41,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:41,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:41,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:41,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:41,161 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-02-21 04:24:41,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:41,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:41,176 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:41,177 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2828 transitions. Second operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,178 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2828 transitions. Second operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,179 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. Second operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:41,275 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-02-21 04:24:41,275 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:41,276 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:41,277 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:41,279 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2828 transitions. [2022-02-21 04:24:41,280 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2828 transitions. [2022-02-21 04:24:41,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:41,364 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-02-21 04:24:41,365 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:41,366 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:41,366 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:41,366 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:41,367 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:41,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-02-21 04:24:41,457 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-02-21 04:24:41,458 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-02-21 04:24:41,458 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:41,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:41,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:41,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:41,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:41,462 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:41,462 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:41,463 INFO L791 eck$LassoCheckResult]: Stem: 58364#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 58365#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 58184#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57900#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57901#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 59077#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59078#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58036#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58037#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58491#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58326#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58327#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 58103#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 58104#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58502#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 58679#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 58833#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 58870#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 58114#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58115#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 59290#L1258-2 assume !(0 == ~T1_E~0); 58409#L1263-1 assume !(0 == ~T2_E~0); 58410#L1268-1 assume !(0 == ~T3_E~0); 58713#L1273-1 assume !(0 == ~T4_E~0); 59272#L1278-1 assume !(0 == ~T5_E~0); 59133#L1283-1 assume !(0 == ~T6_E~0); 59134#L1288-1 assume !(0 == ~T7_E~0); 59370#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59358#L1298-1 assume !(0 == ~T9_E~0); 59284#L1303-1 assume !(0 == ~T10_E~0); 57929#L1308-1 assume !(0 == ~T11_E~0); 57871#L1313-1 assume !(0 == ~T12_E~0); 57872#L1318-1 assume !(0 == ~T13_E~0); 57878#L1323-1 assume !(0 == ~E_1~0); 57879#L1328-1 assume !(0 == ~E_2~0); 58046#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 59005#L1338-1 assume !(0 == ~E_4~0); 59006#L1343-1 assume !(0 == ~E_5~0); 59107#L1348-1 assume !(0 == ~E_6~0); 59393#L1353-1 assume !(0 == ~E_7~0); 58732#L1358-1 assume !(0 == ~E_8~0); 58733#L1363-1 assume !(0 == ~E_9~0); 59023#L1368-1 assume !(0 == ~E_10~0); 57708#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 57709#L1378-1 assume !(0 == ~E_12~0); 57995#L1383-1 assume !(0 == ~E_13~0); 57996#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58739#L607 assume 1 == ~m_pc~0; 58740#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58066#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59105#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58659#L1560 assume !(0 != activate_threads_~tmp~1#1); 58660#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57891#L626 assume !(1 == ~t1_pc~0); 57892#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58160#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58161#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58330#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 57791#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57792#L645 assume 1 == ~t2_pc~0; 57908#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 57865#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58542#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58543#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 58635#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58636#L664 assume 1 == ~t3_pc~0; 59392#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57632#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57633#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58291#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 58292#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59300#L683 assume !(1 == ~t4_pc~0); 58855#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 58807#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58808#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58842#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58966#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58585#L702 assume 1 == ~t5_pc~0; 58586#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58511#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58961#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59259#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 59200#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57680#L721 assume !(1 == ~t6_pc~0); 57654#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 57655#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57818#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58300#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 58301#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58902#L740 assume 1 == ~t7_pc~0; 57729#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57542#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57543#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57532#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 57533#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58236#L759 assume !(1 == ~t8_pc~0); 58237#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 58266#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58959#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58960#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 59091#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59369#L778 assume 1 == ~t9_pc~0; 59256#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57707#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57647#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57576#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 57577#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57904#L797 assume !(1 == ~t10_pc~0); 57905#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58023#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59157#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58407#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 58408#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58697#L816 assume 1 == ~t11_pc~0; 57612#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57613#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58368#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58307#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 58308#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58832#L835 assume 1 == ~t12_pc~0; 58710#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 57776#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57798#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 57939#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 58464#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58465#L854 assume !(1 == ~t13_pc~0); 58105#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 58106#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58156#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57816#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 57817#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59196#L1401 assume !(1 == ~M_E~0); 58295#L1401-2 assume !(1 == ~T1_E~0); 58296#L1406-1 assume !(1 == ~T2_E~0); 58891#L1411-1 assume !(1 == ~T3_E~0); 58892#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58558#L1421-1 assume !(1 == ~T5_E~0); 58101#L1426-1 assume !(1 == ~T6_E~0); 58102#L1431-1 assume !(1 == ~T7_E~0); 57650#L1436-1 assume !(1 == ~T8_E~0); 57651#L1441-1 assume !(1 == ~T9_E~0); 58398#L1446-1 assume !(1 == ~T10_E~0); 58399#L1451-1 assume !(1 == ~T11_E~0); 59104#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58758#L1461-1 assume !(1 == ~T13_E~0); 58319#L1466-1 assume !(1 == ~E_1~0); 58320#L1471-1 assume !(1 == ~E_2~0); 59089#L1476-1 assume !(1 == ~E_3~0); 59090#L1481-1 assume !(1 == ~E_4~0); 59238#L1486-1 assume !(1 == ~E_5~0); 57944#L1491-1 assume !(1 == ~E_6~0); 57584#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 57585#L1501-1 assume !(1 == ~E_8~0); 58396#L1506-1 assume !(1 == ~E_9~0); 58397#L1511-1 assume !(1 == ~E_10~0); 58353#L1516-1 assume !(1 == ~E_11~0); 57528#L1521-1 assume !(1 == ~E_12~0); 57529#L1526-1 assume !(1 == ~E_13~0); 57583#L1531-1 assume { :end_inline_reset_delta_events } true; 58126#L1892-2 [2022-02-21 04:24:41,463 INFO L793 eck$LassoCheckResult]: Loop: 58126#L1892-2 assume !false; 59149#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59347#L1233 assume !false; 59330#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58662#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58642#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58800#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57626#L1046 assume !(0 != eval_~tmp~0#1); 57628#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57662#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58834#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 59391#L1258-5 assume !(0 == ~T1_E~0); 57804#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57805#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59383#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59389#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59390#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58028#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58029#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59146#L1298-3 assume !(0 == ~T9_E~0); 59147#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 59306#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59145#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 58646#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 57806#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57807#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59230#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57949#L1338-3 assume !(0 == ~E_4~0); 57950#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59062#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59235#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59236#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58602#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 58162#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 58163#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 58919#L1378-3 assume !(0 == ~E_12~0); 58920#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59101#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59102#L607-42 assume 1 == ~m_pc~0; 58717#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58443#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58444#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58176#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58177#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58698#L626-42 assume 1 == ~t1_pc~0; 58263#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58264#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58565#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58566#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57840#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57841#L645-42 assume !(1 == ~t2_pc~0); 59040#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 59041#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59206#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58047#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57554#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57555#L664-42 assume !(1 == ~t3_pc~0); 58081#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 58082#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59333#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58868#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58869#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59034#L683-42 assume !(1 == ~t4_pc~0); 58742#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 58743#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58875#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59295#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59296#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59141#L702-42 assume 1 == ~t5_pc~0; 58631#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58253#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58549#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59222#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 57570#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57571#L721-42 assume 1 == ~t6_pc~0; 57724#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57747#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58208#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59375#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58380#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58226#L740-42 assume 1 == ~t7_pc~0; 58227#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57964#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58505#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58360#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58361#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58634#L759-42 assume 1 == ~t8_pc~0; 58485#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58415#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58416#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58494#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58495#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58590#L778-42 assume 1 == ~t9_pc~0; 58430#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58432#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58839#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58744#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58745#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58802#L797-42 assume 1 == ~t10_pc~0; 57972#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 57973#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58971#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59280#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58840#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58841#L816-42 assume 1 == ~t11_pc~0; 57521#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57522#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58063#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58064#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58141#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58142#L835-42 assume 1 == ~t12_pc~0; 58546#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58439#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58116#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58117#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 59199#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58983#L854-42 assume 1 == ~t13_pc~0; 58984#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 58060#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 57670#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57671#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58317#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58318#L1401-3 assume !(1 == ~M_E~0); 59096#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57907#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57773#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57774#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58371#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58372#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57947#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57948#L1436-3 assume !(1 == ~T8_E~0); 57534#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57535#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59125#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58455#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58108#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58109#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59386#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58048#L1476-3 assume !(1 == ~E_3~0); 58049#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58449#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58076#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58077#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58489#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58490#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 58916#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58906#L1516-3 assume !(1 == ~E_11~0); 58907#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58606#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58607#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59003#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57883#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58778#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 58417#L1911 assume !(0 == start_simulation_~tmp~3#1); 58418#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58940#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58008#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58878#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 57712#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57713#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57942#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57943#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 58126#L1892-2 [2022-02-21 04:24:41,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:41,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2022-02-21 04:24:41,464 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:41,464 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78239889] [2022-02-21 04:24:41,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:41,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:41,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:41,483 INFO L290 TraceCheckUtils]: 0: Hoare triple {63248#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {63248#true} is VALID [2022-02-21 04:24:41,483 INFO L290 TraceCheckUtils]: 1: Hoare triple {63248#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,484 INFO L290 TraceCheckUtils]: 2: Hoare triple {63250#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,484 INFO L290 TraceCheckUtils]: 3: Hoare triple {63250#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,484 INFO L290 TraceCheckUtils]: 4: Hoare triple {63250#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,485 INFO L290 TraceCheckUtils]: 5: Hoare triple {63250#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,485 INFO L290 TraceCheckUtils]: 6: Hoare triple {63250#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,485 INFO L290 TraceCheckUtils]: 7: Hoare triple {63250#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,485 INFO L290 TraceCheckUtils]: 8: Hoare triple {63250#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,486 INFO L290 TraceCheckUtils]: 9: Hoare triple {63250#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,486 INFO L290 TraceCheckUtils]: 10: Hoare triple {63250#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,486 INFO L290 TraceCheckUtils]: 11: Hoare triple {63250#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {63250#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:41,487 INFO L290 TraceCheckUtils]: 12: Hoare triple {63250#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {63249#false} is VALID [2022-02-21 04:24:41,487 INFO L290 TraceCheckUtils]: 13: Hoare triple {63249#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {63249#false} is VALID [2022-02-21 04:24:41,487 INFO L290 TraceCheckUtils]: 14: Hoare triple {63249#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {63249#false} is VALID [2022-02-21 04:24:41,487 INFO L290 TraceCheckUtils]: 15: Hoare triple {63249#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {63249#false} is VALID [2022-02-21 04:24:41,487 INFO L290 TraceCheckUtils]: 16: Hoare triple {63249#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {63249#false} is VALID [2022-02-21 04:24:41,487 INFO L290 TraceCheckUtils]: 17: Hoare triple {63249#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {63249#false} is VALID [2022-02-21 04:24:41,487 INFO L290 TraceCheckUtils]: 18: Hoare triple {63249#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {63249#false} is VALID [2022-02-21 04:24:41,487 INFO L290 TraceCheckUtils]: 19: Hoare triple {63249#false} assume 0 == ~M_E~0;~M_E~0 := 1; {63249#false} is VALID [2022-02-21 04:24:41,487 INFO L290 TraceCheckUtils]: 20: Hoare triple {63249#false} assume !(0 == ~T1_E~0); {63249#false} is VALID [2022-02-21 04:24:41,488 INFO L290 TraceCheckUtils]: 21: Hoare triple {63249#false} assume !(0 == ~T2_E~0); {63249#false} is VALID [2022-02-21 04:24:41,488 INFO L290 TraceCheckUtils]: 22: Hoare triple {63249#false} assume !(0 == ~T3_E~0); {63249#false} is VALID [2022-02-21 04:24:41,488 INFO L290 TraceCheckUtils]: 23: Hoare triple {63249#false} assume !(0 == ~T4_E~0); {63249#false} is VALID [2022-02-21 04:24:41,488 INFO L290 TraceCheckUtils]: 24: Hoare triple {63249#false} assume !(0 == ~T5_E~0); {63249#false} is VALID [2022-02-21 04:24:41,488 INFO L290 TraceCheckUtils]: 25: Hoare triple {63249#false} assume !(0 == ~T6_E~0); {63249#false} is VALID [2022-02-21 04:24:41,488 INFO L290 TraceCheckUtils]: 26: Hoare triple {63249#false} assume !(0 == ~T7_E~0); {63249#false} is VALID [2022-02-21 04:24:41,488 INFO L290 TraceCheckUtils]: 27: Hoare triple {63249#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {63249#false} is VALID [2022-02-21 04:24:41,488 INFO L290 TraceCheckUtils]: 28: Hoare triple {63249#false} assume !(0 == ~T9_E~0); {63249#false} is VALID [2022-02-21 04:24:41,489 INFO L290 TraceCheckUtils]: 29: Hoare triple {63249#false} assume !(0 == ~T10_E~0); {63249#false} is VALID [2022-02-21 04:24:41,489 INFO L290 TraceCheckUtils]: 30: Hoare triple {63249#false} assume !(0 == ~T11_E~0); {63249#false} is VALID [2022-02-21 04:24:41,489 INFO L290 TraceCheckUtils]: 31: Hoare triple {63249#false} assume !(0 == ~T12_E~0); {63249#false} is VALID [2022-02-21 04:24:41,489 INFO L290 TraceCheckUtils]: 32: Hoare triple {63249#false} assume !(0 == ~T13_E~0); {63249#false} is VALID [2022-02-21 04:24:41,489 INFO L290 TraceCheckUtils]: 33: Hoare triple {63249#false} assume !(0 == ~E_1~0); {63249#false} is VALID [2022-02-21 04:24:41,489 INFO L290 TraceCheckUtils]: 34: Hoare triple {63249#false} assume !(0 == ~E_2~0); {63249#false} is VALID [2022-02-21 04:24:41,489 INFO L290 TraceCheckUtils]: 35: Hoare triple {63249#false} assume 0 == ~E_3~0;~E_3~0 := 1; {63249#false} is VALID [2022-02-21 04:24:41,489 INFO L290 TraceCheckUtils]: 36: Hoare triple {63249#false} assume !(0 == ~E_4~0); {63249#false} is VALID [2022-02-21 04:24:41,490 INFO L290 TraceCheckUtils]: 37: Hoare triple {63249#false} assume !(0 == ~E_5~0); {63249#false} is VALID [2022-02-21 04:24:41,490 INFO L290 TraceCheckUtils]: 38: Hoare triple {63249#false} assume !(0 == ~E_6~0); {63249#false} is VALID [2022-02-21 04:24:41,490 INFO L290 TraceCheckUtils]: 39: Hoare triple {63249#false} assume !(0 == ~E_7~0); {63249#false} is VALID [2022-02-21 04:24:41,490 INFO L290 TraceCheckUtils]: 40: Hoare triple {63249#false} assume !(0 == ~E_8~0); {63249#false} is VALID [2022-02-21 04:24:41,490 INFO L290 TraceCheckUtils]: 41: Hoare triple {63249#false} assume !(0 == ~E_9~0); {63249#false} is VALID [2022-02-21 04:24:41,490 INFO L290 TraceCheckUtils]: 42: Hoare triple {63249#false} assume !(0 == ~E_10~0); {63249#false} is VALID [2022-02-21 04:24:41,490 INFO L290 TraceCheckUtils]: 43: Hoare triple {63249#false} assume 0 == ~E_11~0;~E_11~0 := 1; {63249#false} is VALID [2022-02-21 04:24:41,490 INFO L290 TraceCheckUtils]: 44: Hoare triple {63249#false} assume !(0 == ~E_12~0); {63249#false} is VALID [2022-02-21 04:24:41,490 INFO L290 TraceCheckUtils]: 45: Hoare triple {63249#false} assume !(0 == ~E_13~0); {63249#false} is VALID [2022-02-21 04:24:41,491 INFO L290 TraceCheckUtils]: 46: Hoare triple {63249#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {63249#false} is VALID [2022-02-21 04:24:41,491 INFO L290 TraceCheckUtils]: 47: Hoare triple {63249#false} assume 1 == ~m_pc~0; {63249#false} is VALID [2022-02-21 04:24:41,491 INFO L290 TraceCheckUtils]: 48: Hoare triple {63249#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {63249#false} is VALID [2022-02-21 04:24:41,491 INFO L290 TraceCheckUtils]: 49: Hoare triple {63249#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {63249#false} is VALID [2022-02-21 04:24:41,491 INFO L290 TraceCheckUtils]: 50: Hoare triple {63249#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {63249#false} is VALID [2022-02-21 04:24:41,491 INFO L290 TraceCheckUtils]: 51: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp~1#1); {63249#false} is VALID [2022-02-21 04:24:41,491 INFO L290 TraceCheckUtils]: 52: Hoare triple {63249#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {63249#false} is VALID [2022-02-21 04:24:41,491 INFO L290 TraceCheckUtils]: 53: Hoare triple {63249#false} assume !(1 == ~t1_pc~0); {63249#false} is VALID [2022-02-21 04:24:41,491 INFO L290 TraceCheckUtils]: 54: Hoare triple {63249#false} is_transmit1_triggered_~__retres1~1#1 := 0; {63249#false} is VALID [2022-02-21 04:24:41,492 INFO L290 TraceCheckUtils]: 55: Hoare triple {63249#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {63249#false} is VALID [2022-02-21 04:24:41,492 INFO L290 TraceCheckUtils]: 56: Hoare triple {63249#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {63249#false} is VALID [2022-02-21 04:24:41,492 INFO L290 TraceCheckUtils]: 57: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___0~0#1); {63249#false} is VALID [2022-02-21 04:24:41,492 INFO L290 TraceCheckUtils]: 58: Hoare triple {63249#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {63249#false} is VALID [2022-02-21 04:24:41,492 INFO L290 TraceCheckUtils]: 59: Hoare triple {63249#false} assume 1 == ~t2_pc~0; {63249#false} is VALID [2022-02-21 04:24:41,492 INFO L290 TraceCheckUtils]: 60: Hoare triple {63249#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {63249#false} is VALID [2022-02-21 04:24:41,492 INFO L290 TraceCheckUtils]: 61: Hoare triple {63249#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {63249#false} is VALID [2022-02-21 04:24:41,492 INFO L290 TraceCheckUtils]: 62: Hoare triple {63249#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {63249#false} is VALID [2022-02-21 04:24:41,493 INFO L290 TraceCheckUtils]: 63: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___1~0#1); {63249#false} is VALID [2022-02-21 04:24:41,493 INFO L290 TraceCheckUtils]: 64: Hoare triple {63249#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {63249#false} is VALID [2022-02-21 04:24:41,493 INFO L290 TraceCheckUtils]: 65: Hoare triple {63249#false} assume 1 == ~t3_pc~0; {63249#false} is VALID [2022-02-21 04:24:41,493 INFO L290 TraceCheckUtils]: 66: Hoare triple {63249#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {63249#false} is VALID [2022-02-21 04:24:41,493 INFO L290 TraceCheckUtils]: 67: Hoare triple {63249#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {63249#false} is VALID [2022-02-21 04:24:41,493 INFO L290 TraceCheckUtils]: 68: Hoare triple {63249#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {63249#false} is VALID [2022-02-21 04:24:41,493 INFO L290 TraceCheckUtils]: 69: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___2~0#1); {63249#false} is VALID [2022-02-21 04:24:41,493 INFO L290 TraceCheckUtils]: 70: Hoare triple {63249#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {63249#false} is VALID [2022-02-21 04:24:41,493 INFO L290 TraceCheckUtils]: 71: Hoare triple {63249#false} assume !(1 == ~t4_pc~0); {63249#false} is VALID [2022-02-21 04:24:41,494 INFO L290 TraceCheckUtils]: 72: Hoare triple {63249#false} is_transmit4_triggered_~__retres1~4#1 := 0; {63249#false} is VALID [2022-02-21 04:24:41,494 INFO L290 TraceCheckUtils]: 73: Hoare triple {63249#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {63249#false} is VALID [2022-02-21 04:24:41,494 INFO L290 TraceCheckUtils]: 74: Hoare triple {63249#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {63249#false} is VALID [2022-02-21 04:24:41,494 INFO L290 TraceCheckUtils]: 75: Hoare triple {63249#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {63249#false} is VALID [2022-02-21 04:24:41,494 INFO L290 TraceCheckUtils]: 76: Hoare triple {63249#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {63249#false} is VALID [2022-02-21 04:24:41,494 INFO L290 TraceCheckUtils]: 77: Hoare triple {63249#false} assume 1 == ~t5_pc~0; {63249#false} is VALID [2022-02-21 04:24:41,494 INFO L290 TraceCheckUtils]: 78: Hoare triple {63249#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {63249#false} is VALID [2022-02-21 04:24:41,494 INFO L290 TraceCheckUtils]: 79: Hoare triple {63249#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {63249#false} is VALID [2022-02-21 04:24:41,494 INFO L290 TraceCheckUtils]: 80: Hoare triple {63249#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {63249#false} is VALID [2022-02-21 04:24:41,495 INFO L290 TraceCheckUtils]: 81: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___4~0#1); {63249#false} is VALID [2022-02-21 04:24:41,495 INFO L290 TraceCheckUtils]: 82: Hoare triple {63249#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {63249#false} is VALID [2022-02-21 04:24:41,495 INFO L290 TraceCheckUtils]: 83: Hoare triple {63249#false} assume !(1 == ~t6_pc~0); {63249#false} is VALID [2022-02-21 04:24:41,495 INFO L290 TraceCheckUtils]: 84: Hoare triple {63249#false} is_transmit6_triggered_~__retres1~6#1 := 0; {63249#false} is VALID [2022-02-21 04:24:41,495 INFO L290 TraceCheckUtils]: 85: Hoare triple {63249#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {63249#false} is VALID [2022-02-21 04:24:41,495 INFO L290 TraceCheckUtils]: 86: Hoare triple {63249#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {63249#false} is VALID [2022-02-21 04:24:41,495 INFO L290 TraceCheckUtils]: 87: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___5~0#1); {63249#false} is VALID [2022-02-21 04:24:41,495 INFO L290 TraceCheckUtils]: 88: Hoare triple {63249#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {63249#false} is VALID [2022-02-21 04:24:41,495 INFO L290 TraceCheckUtils]: 89: Hoare triple {63249#false} assume 1 == ~t7_pc~0; {63249#false} is VALID [2022-02-21 04:24:41,496 INFO L290 TraceCheckUtils]: 90: Hoare triple {63249#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {63249#false} is VALID [2022-02-21 04:24:41,496 INFO L290 TraceCheckUtils]: 91: Hoare triple {63249#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {63249#false} is VALID [2022-02-21 04:24:41,496 INFO L290 TraceCheckUtils]: 92: Hoare triple {63249#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {63249#false} is VALID [2022-02-21 04:24:41,496 INFO L290 TraceCheckUtils]: 93: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___6~0#1); {63249#false} is VALID [2022-02-21 04:24:41,496 INFO L290 TraceCheckUtils]: 94: Hoare triple {63249#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {63249#false} is VALID [2022-02-21 04:24:41,496 INFO L290 TraceCheckUtils]: 95: Hoare triple {63249#false} assume !(1 == ~t8_pc~0); {63249#false} is VALID [2022-02-21 04:24:41,496 INFO L290 TraceCheckUtils]: 96: Hoare triple {63249#false} is_transmit8_triggered_~__retres1~8#1 := 0; {63249#false} is VALID [2022-02-21 04:24:41,496 INFO L290 TraceCheckUtils]: 97: Hoare triple {63249#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {63249#false} is VALID [2022-02-21 04:24:41,497 INFO L290 TraceCheckUtils]: 98: Hoare triple {63249#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {63249#false} is VALID [2022-02-21 04:24:41,497 INFO L290 TraceCheckUtils]: 99: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___7~0#1); {63249#false} is VALID [2022-02-21 04:24:41,497 INFO L290 TraceCheckUtils]: 100: Hoare triple {63249#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {63249#false} is VALID [2022-02-21 04:24:41,497 INFO L290 TraceCheckUtils]: 101: Hoare triple {63249#false} assume 1 == ~t9_pc~0; {63249#false} is VALID [2022-02-21 04:24:41,497 INFO L290 TraceCheckUtils]: 102: Hoare triple {63249#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {63249#false} is VALID [2022-02-21 04:24:41,497 INFO L290 TraceCheckUtils]: 103: Hoare triple {63249#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {63249#false} is VALID [2022-02-21 04:24:41,497 INFO L290 TraceCheckUtils]: 104: Hoare triple {63249#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {63249#false} is VALID [2022-02-21 04:24:41,497 INFO L290 TraceCheckUtils]: 105: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___8~0#1); {63249#false} is VALID [2022-02-21 04:24:41,497 INFO L290 TraceCheckUtils]: 106: Hoare triple {63249#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {63249#false} is VALID [2022-02-21 04:24:41,498 INFO L290 TraceCheckUtils]: 107: Hoare triple {63249#false} assume !(1 == ~t10_pc~0); {63249#false} is VALID [2022-02-21 04:24:41,498 INFO L290 TraceCheckUtils]: 108: Hoare triple {63249#false} is_transmit10_triggered_~__retres1~10#1 := 0; {63249#false} is VALID [2022-02-21 04:24:41,498 INFO L290 TraceCheckUtils]: 109: Hoare triple {63249#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {63249#false} is VALID [2022-02-21 04:24:41,498 INFO L290 TraceCheckUtils]: 110: Hoare triple {63249#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {63249#false} is VALID [2022-02-21 04:24:41,498 INFO L290 TraceCheckUtils]: 111: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___9~0#1); {63249#false} is VALID [2022-02-21 04:24:41,498 INFO L290 TraceCheckUtils]: 112: Hoare triple {63249#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {63249#false} is VALID [2022-02-21 04:24:41,498 INFO L290 TraceCheckUtils]: 113: Hoare triple {63249#false} assume 1 == ~t11_pc~0; {63249#false} is VALID [2022-02-21 04:24:41,498 INFO L290 TraceCheckUtils]: 114: Hoare triple {63249#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {63249#false} is VALID [2022-02-21 04:24:41,498 INFO L290 TraceCheckUtils]: 115: Hoare triple {63249#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {63249#false} is VALID [2022-02-21 04:24:41,499 INFO L290 TraceCheckUtils]: 116: Hoare triple {63249#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {63249#false} is VALID [2022-02-21 04:24:41,499 INFO L290 TraceCheckUtils]: 117: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___10~0#1); {63249#false} is VALID [2022-02-21 04:24:41,499 INFO L290 TraceCheckUtils]: 118: Hoare triple {63249#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {63249#false} is VALID [2022-02-21 04:24:41,499 INFO L290 TraceCheckUtils]: 119: Hoare triple {63249#false} assume 1 == ~t12_pc~0; {63249#false} is VALID [2022-02-21 04:24:41,499 INFO L290 TraceCheckUtils]: 120: Hoare triple {63249#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {63249#false} is VALID [2022-02-21 04:24:41,499 INFO L290 TraceCheckUtils]: 121: Hoare triple {63249#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {63249#false} is VALID [2022-02-21 04:24:41,499 INFO L290 TraceCheckUtils]: 122: Hoare triple {63249#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {63249#false} is VALID [2022-02-21 04:24:41,499 INFO L290 TraceCheckUtils]: 123: Hoare triple {63249#false} assume !(0 != activate_threads_~tmp___11~0#1); {63249#false} is VALID [2022-02-21 04:24:41,499 INFO L290 TraceCheckUtils]: 124: Hoare triple {63249#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {63249#false} is VALID [2022-02-21 04:24:41,500 INFO L290 TraceCheckUtils]: 125: Hoare triple {63249#false} assume !(1 == ~t13_pc~0); {63249#false} is VALID [2022-02-21 04:24:41,500 INFO L290 TraceCheckUtils]: 126: Hoare triple {63249#false} is_transmit13_triggered_~__retres1~13#1 := 0; {63249#false} is VALID [2022-02-21 04:24:41,500 INFO L290 TraceCheckUtils]: 127: Hoare triple {63249#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {63249#false} is VALID [2022-02-21 04:24:41,500 INFO L290 TraceCheckUtils]: 128: Hoare triple {63249#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {63249#false} is VALID [2022-02-21 04:24:41,500 INFO L290 TraceCheckUtils]: 129: Hoare triple {63249#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {63249#false} is VALID [2022-02-21 04:24:41,500 INFO L290 TraceCheckUtils]: 130: Hoare triple {63249#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {63249#false} is VALID [2022-02-21 04:24:41,500 INFO L290 TraceCheckUtils]: 131: Hoare triple {63249#false} assume !(1 == ~M_E~0); {63249#false} is VALID [2022-02-21 04:24:41,500 INFO L290 TraceCheckUtils]: 132: Hoare triple {63249#false} assume !(1 == ~T1_E~0); {63249#false} is VALID [2022-02-21 04:24:41,501 INFO L290 TraceCheckUtils]: 133: Hoare triple {63249#false} assume !(1 == ~T2_E~0); {63249#false} is VALID [2022-02-21 04:24:41,501 INFO L290 TraceCheckUtils]: 134: Hoare triple {63249#false} assume !(1 == ~T3_E~0); {63249#false} is VALID [2022-02-21 04:24:41,501 INFO L290 TraceCheckUtils]: 135: Hoare triple {63249#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {63249#false} is VALID [2022-02-21 04:24:41,501 INFO L290 TraceCheckUtils]: 136: Hoare triple {63249#false} assume !(1 == ~T5_E~0); {63249#false} is VALID [2022-02-21 04:24:41,501 INFO L290 TraceCheckUtils]: 137: Hoare triple {63249#false} assume !(1 == ~T6_E~0); {63249#false} is VALID [2022-02-21 04:24:41,501 INFO L290 TraceCheckUtils]: 138: Hoare triple {63249#false} assume !(1 == ~T7_E~0); {63249#false} is VALID [2022-02-21 04:24:41,501 INFO L290 TraceCheckUtils]: 139: Hoare triple {63249#false} assume !(1 == ~T8_E~0); {63249#false} is VALID [2022-02-21 04:24:41,501 INFO L290 TraceCheckUtils]: 140: Hoare triple {63249#false} assume !(1 == ~T9_E~0); {63249#false} is VALID [2022-02-21 04:24:41,501 INFO L290 TraceCheckUtils]: 141: Hoare triple {63249#false} assume !(1 == ~T10_E~0); {63249#false} is VALID [2022-02-21 04:24:41,502 INFO L290 TraceCheckUtils]: 142: Hoare triple {63249#false} assume !(1 == ~T11_E~0); {63249#false} is VALID [2022-02-21 04:24:41,502 INFO L290 TraceCheckUtils]: 143: Hoare triple {63249#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {63249#false} is VALID [2022-02-21 04:24:41,502 INFO L290 TraceCheckUtils]: 144: Hoare triple {63249#false} assume !(1 == ~T13_E~0); {63249#false} is VALID [2022-02-21 04:24:41,502 INFO L290 TraceCheckUtils]: 145: Hoare triple {63249#false} assume !(1 == ~E_1~0); {63249#false} is VALID [2022-02-21 04:24:41,502 INFO L290 TraceCheckUtils]: 146: Hoare triple {63249#false} assume !(1 == ~E_2~0); {63249#false} is VALID [2022-02-21 04:24:41,502 INFO L290 TraceCheckUtils]: 147: Hoare triple {63249#false} assume !(1 == ~E_3~0); {63249#false} is VALID [2022-02-21 04:24:41,502 INFO L290 TraceCheckUtils]: 148: Hoare triple {63249#false} assume !(1 == ~E_4~0); {63249#false} is VALID [2022-02-21 04:24:41,502 INFO L290 TraceCheckUtils]: 149: Hoare triple {63249#false} assume !(1 == ~E_5~0); {63249#false} is VALID [2022-02-21 04:24:41,502 INFO L290 TraceCheckUtils]: 150: Hoare triple {63249#false} assume !(1 == ~E_6~0); {63249#false} is VALID [2022-02-21 04:24:41,503 INFO L290 TraceCheckUtils]: 151: Hoare triple {63249#false} assume 1 == ~E_7~0;~E_7~0 := 2; {63249#false} is VALID [2022-02-21 04:24:41,503 INFO L290 TraceCheckUtils]: 152: Hoare triple {63249#false} assume !(1 == ~E_8~0); {63249#false} is VALID [2022-02-21 04:24:41,503 INFO L290 TraceCheckUtils]: 153: Hoare triple {63249#false} assume !(1 == ~E_9~0); {63249#false} is VALID [2022-02-21 04:24:41,503 INFO L290 TraceCheckUtils]: 154: Hoare triple {63249#false} assume !(1 == ~E_10~0); {63249#false} is VALID [2022-02-21 04:24:41,503 INFO L290 TraceCheckUtils]: 155: Hoare triple {63249#false} assume !(1 == ~E_11~0); {63249#false} is VALID [2022-02-21 04:24:41,503 INFO L290 TraceCheckUtils]: 156: Hoare triple {63249#false} assume !(1 == ~E_12~0); {63249#false} is VALID [2022-02-21 04:24:41,503 INFO L290 TraceCheckUtils]: 157: Hoare triple {63249#false} assume !(1 == ~E_13~0); {63249#false} is VALID [2022-02-21 04:24:41,503 INFO L290 TraceCheckUtils]: 158: Hoare triple {63249#false} assume { :end_inline_reset_delta_events } true; {63249#false} is VALID [2022-02-21 04:24:41,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:41,504 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:41,504 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78239889] [2022-02-21 04:24:41,504 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [78239889] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:41,504 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:41,504 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:41,504 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818318369] [2022-02-21 04:24:41,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:41,505 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:41,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:41,505 INFO L85 PathProgramCache]: Analyzing trace with hash -2110938126, now seen corresponding path program 1 times [2022-02-21 04:24:41,505 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:41,506 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696305780] [2022-02-21 04:24:41,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:41,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:41,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:41,529 INFO L290 TraceCheckUtils]: 0: Hoare triple {63251#true} assume !false; {63251#true} is VALID [2022-02-21 04:24:41,530 INFO L290 TraceCheckUtils]: 1: Hoare triple {63251#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {63251#true} is VALID [2022-02-21 04:24:41,530 INFO L290 TraceCheckUtils]: 2: Hoare triple {63251#true} assume !false; {63251#true} is VALID [2022-02-21 04:24:41,530 INFO L290 TraceCheckUtils]: 3: Hoare triple {63251#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {63251#true} is VALID [2022-02-21 04:24:41,530 INFO L290 TraceCheckUtils]: 4: Hoare triple {63251#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {63251#true} is VALID [2022-02-21 04:24:41,530 INFO L290 TraceCheckUtils]: 5: Hoare triple {63251#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {63251#true} is VALID [2022-02-21 04:24:41,530 INFO L290 TraceCheckUtils]: 6: Hoare triple {63251#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {63251#true} is VALID [2022-02-21 04:24:41,530 INFO L290 TraceCheckUtils]: 7: Hoare triple {63251#true} assume !(0 != eval_~tmp~0#1); {63251#true} is VALID [2022-02-21 04:24:41,530 INFO L290 TraceCheckUtils]: 8: Hoare triple {63251#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {63251#true} is VALID [2022-02-21 04:24:41,531 INFO L290 TraceCheckUtils]: 9: Hoare triple {63251#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {63251#true} is VALID [2022-02-21 04:24:41,531 INFO L290 TraceCheckUtils]: 10: Hoare triple {63251#true} assume 0 == ~M_E~0;~M_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,531 INFO L290 TraceCheckUtils]: 11: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,531 INFO L290 TraceCheckUtils]: 12: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,532 INFO L290 TraceCheckUtils]: 13: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,532 INFO L290 TraceCheckUtils]: 14: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,532 INFO L290 TraceCheckUtils]: 15: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,533 INFO L290 TraceCheckUtils]: 16: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,533 INFO L290 TraceCheckUtils]: 17: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,533 INFO L290 TraceCheckUtils]: 18: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,533 INFO L290 TraceCheckUtils]: 19: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,534 INFO L290 TraceCheckUtils]: 20: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,534 INFO L290 TraceCheckUtils]: 21: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,534 INFO L290 TraceCheckUtils]: 22: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,535 INFO L290 TraceCheckUtils]: 23: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,535 INFO L290 TraceCheckUtils]: 24: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,535 INFO L290 TraceCheckUtils]: 25: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,535 INFO L290 TraceCheckUtils]: 26: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,536 INFO L290 TraceCheckUtils]: 27: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,536 INFO L290 TraceCheckUtils]: 28: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,536 INFO L290 TraceCheckUtils]: 29: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,536 INFO L290 TraceCheckUtils]: 30: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,537 INFO L290 TraceCheckUtils]: 31: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,537 INFO L290 TraceCheckUtils]: 32: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,537 INFO L290 TraceCheckUtils]: 33: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,538 INFO L290 TraceCheckUtils]: 34: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,538 INFO L290 TraceCheckUtils]: 35: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,538 INFO L290 TraceCheckUtils]: 36: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,538 INFO L290 TraceCheckUtils]: 37: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,539 INFO L290 TraceCheckUtils]: 38: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,539 INFO L290 TraceCheckUtils]: 39: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,539 INFO L290 TraceCheckUtils]: 40: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,539 INFO L290 TraceCheckUtils]: 41: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,540 INFO L290 TraceCheckUtils]: 42: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,540 INFO L290 TraceCheckUtils]: 43: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,540 INFO L290 TraceCheckUtils]: 44: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,541 INFO L290 TraceCheckUtils]: 45: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,541 INFO L290 TraceCheckUtils]: 46: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,541 INFO L290 TraceCheckUtils]: 47: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,541 INFO L290 TraceCheckUtils]: 48: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,542 INFO L290 TraceCheckUtils]: 49: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,542 INFO L290 TraceCheckUtils]: 50: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,542 INFO L290 TraceCheckUtils]: 51: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,542 INFO L290 TraceCheckUtils]: 52: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,543 INFO L290 TraceCheckUtils]: 53: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,543 INFO L290 TraceCheckUtils]: 54: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,543 INFO L290 TraceCheckUtils]: 55: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,544 INFO L290 TraceCheckUtils]: 56: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,544 INFO L290 TraceCheckUtils]: 57: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,544 INFO L290 TraceCheckUtils]: 58: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,544 INFO L290 TraceCheckUtils]: 59: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,545 INFO L290 TraceCheckUtils]: 60: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,545 INFO L290 TraceCheckUtils]: 61: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,545 INFO L290 TraceCheckUtils]: 62: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,546 INFO L290 TraceCheckUtils]: 63: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,546 INFO L290 TraceCheckUtils]: 64: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,546 INFO L290 TraceCheckUtils]: 65: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,546 INFO L290 TraceCheckUtils]: 66: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,547 INFO L290 TraceCheckUtils]: 67: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,547 INFO L290 TraceCheckUtils]: 68: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,547 INFO L290 TraceCheckUtils]: 69: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,548 INFO L290 TraceCheckUtils]: 70: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,548 INFO L290 TraceCheckUtils]: 71: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,548 INFO L290 TraceCheckUtils]: 72: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,548 INFO L290 TraceCheckUtils]: 73: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,549 INFO L290 TraceCheckUtils]: 74: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,549 INFO L290 TraceCheckUtils]: 75: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,549 INFO L290 TraceCheckUtils]: 76: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,549 INFO L290 TraceCheckUtils]: 77: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,550 INFO L290 TraceCheckUtils]: 78: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,550 INFO L290 TraceCheckUtils]: 79: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,550 INFO L290 TraceCheckUtils]: 80: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,551 INFO L290 TraceCheckUtils]: 81: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,551 INFO L290 TraceCheckUtils]: 82: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,551 INFO L290 TraceCheckUtils]: 83: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,551 INFO L290 TraceCheckUtils]: 84: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,552 INFO L290 TraceCheckUtils]: 85: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,552 INFO L290 TraceCheckUtils]: 86: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,552 INFO L290 TraceCheckUtils]: 87: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,553 INFO L290 TraceCheckUtils]: 88: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,553 INFO L290 TraceCheckUtils]: 89: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,553 INFO L290 TraceCheckUtils]: 90: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,553 INFO L290 TraceCheckUtils]: 91: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,554 INFO L290 TraceCheckUtils]: 92: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,554 INFO L290 TraceCheckUtils]: 93: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,554 INFO L290 TraceCheckUtils]: 94: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,554 INFO L290 TraceCheckUtils]: 95: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,555 INFO L290 TraceCheckUtils]: 96: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,555 INFO L290 TraceCheckUtils]: 97: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,555 INFO L290 TraceCheckUtils]: 98: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,556 INFO L290 TraceCheckUtils]: 99: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,556 INFO L290 TraceCheckUtils]: 100: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,556 INFO L290 TraceCheckUtils]: 101: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,556 INFO L290 TraceCheckUtils]: 102: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,557 INFO L290 TraceCheckUtils]: 103: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,557 INFO L290 TraceCheckUtils]: 104: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,557 INFO L290 TraceCheckUtils]: 105: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,558 INFO L290 TraceCheckUtils]: 106: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,558 INFO L290 TraceCheckUtils]: 107: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,558 INFO L290 TraceCheckUtils]: 108: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,558 INFO L290 TraceCheckUtils]: 109: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,559 INFO L290 TraceCheckUtils]: 110: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,559 INFO L290 TraceCheckUtils]: 111: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,559 INFO L290 TraceCheckUtils]: 112: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,559 INFO L290 TraceCheckUtils]: 113: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,560 INFO L290 TraceCheckUtils]: 114: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,560 INFO L290 TraceCheckUtils]: 115: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,560 INFO L290 TraceCheckUtils]: 116: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,561 INFO L290 TraceCheckUtils]: 117: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,561 INFO L290 TraceCheckUtils]: 118: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,561 INFO L290 TraceCheckUtils]: 119: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,561 INFO L290 TraceCheckUtils]: 120: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,562 INFO L290 TraceCheckUtils]: 121: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {63253#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,562 INFO L290 TraceCheckUtils]: 122: Hoare triple {63253#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {63252#false} is VALID [2022-02-21 04:24:41,562 INFO L290 TraceCheckUtils]: 123: Hoare triple {63252#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,562 INFO L290 TraceCheckUtils]: 124: Hoare triple {63252#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,562 INFO L290 TraceCheckUtils]: 125: Hoare triple {63252#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,562 INFO L290 TraceCheckUtils]: 126: Hoare triple {63252#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,563 INFO L290 TraceCheckUtils]: 127: Hoare triple {63252#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,563 INFO L290 TraceCheckUtils]: 128: Hoare triple {63252#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,563 INFO L290 TraceCheckUtils]: 129: Hoare triple {63252#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,563 INFO L290 TraceCheckUtils]: 130: Hoare triple {63252#false} assume !(1 == ~T8_E~0); {63252#false} is VALID [2022-02-21 04:24:41,563 INFO L290 TraceCheckUtils]: 131: Hoare triple {63252#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,563 INFO L290 TraceCheckUtils]: 132: Hoare triple {63252#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,563 INFO L290 TraceCheckUtils]: 133: Hoare triple {63252#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,563 INFO L290 TraceCheckUtils]: 134: Hoare triple {63252#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,563 INFO L290 TraceCheckUtils]: 135: Hoare triple {63252#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,564 INFO L290 TraceCheckUtils]: 136: Hoare triple {63252#false} assume 1 == ~E_1~0;~E_1~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,564 INFO L290 TraceCheckUtils]: 137: Hoare triple {63252#false} assume 1 == ~E_2~0;~E_2~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,564 INFO L290 TraceCheckUtils]: 138: Hoare triple {63252#false} assume !(1 == ~E_3~0); {63252#false} is VALID [2022-02-21 04:24:41,564 INFO L290 TraceCheckUtils]: 139: Hoare triple {63252#false} assume 1 == ~E_4~0;~E_4~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,564 INFO L290 TraceCheckUtils]: 140: Hoare triple {63252#false} assume 1 == ~E_5~0;~E_5~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,564 INFO L290 TraceCheckUtils]: 141: Hoare triple {63252#false} assume 1 == ~E_6~0;~E_6~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,564 INFO L290 TraceCheckUtils]: 142: Hoare triple {63252#false} assume 1 == ~E_7~0;~E_7~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,564 INFO L290 TraceCheckUtils]: 143: Hoare triple {63252#false} assume 1 == ~E_8~0;~E_8~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,565 INFO L290 TraceCheckUtils]: 144: Hoare triple {63252#false} assume 1 == ~E_9~0;~E_9~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,565 INFO L290 TraceCheckUtils]: 145: Hoare triple {63252#false} assume 1 == ~E_10~0;~E_10~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,565 INFO L290 TraceCheckUtils]: 146: Hoare triple {63252#false} assume !(1 == ~E_11~0); {63252#false} is VALID [2022-02-21 04:24:41,565 INFO L290 TraceCheckUtils]: 147: Hoare triple {63252#false} assume 1 == ~E_12~0;~E_12~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,565 INFO L290 TraceCheckUtils]: 148: Hoare triple {63252#false} assume 1 == ~E_13~0;~E_13~0 := 2; {63252#false} is VALID [2022-02-21 04:24:41,565 INFO L290 TraceCheckUtils]: 149: Hoare triple {63252#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {63252#false} is VALID [2022-02-21 04:24:41,565 INFO L290 TraceCheckUtils]: 150: Hoare triple {63252#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {63252#false} is VALID [2022-02-21 04:24:41,565 INFO L290 TraceCheckUtils]: 151: Hoare triple {63252#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {63252#false} is VALID [2022-02-21 04:24:41,565 INFO L290 TraceCheckUtils]: 152: Hoare triple {63252#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {63252#false} is VALID [2022-02-21 04:24:41,566 INFO L290 TraceCheckUtils]: 153: Hoare triple {63252#false} assume !(0 == start_simulation_~tmp~3#1); {63252#false} is VALID [2022-02-21 04:24:41,566 INFO L290 TraceCheckUtils]: 154: Hoare triple {63252#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {63252#false} is VALID [2022-02-21 04:24:41,566 INFO L290 TraceCheckUtils]: 155: Hoare triple {63252#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {63252#false} is VALID [2022-02-21 04:24:41,566 INFO L290 TraceCheckUtils]: 156: Hoare triple {63252#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {63252#false} is VALID [2022-02-21 04:24:41,566 INFO L290 TraceCheckUtils]: 157: Hoare triple {63252#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {63252#false} is VALID [2022-02-21 04:24:41,566 INFO L290 TraceCheckUtils]: 158: Hoare triple {63252#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {63252#false} is VALID [2022-02-21 04:24:41,566 INFO L290 TraceCheckUtils]: 159: Hoare triple {63252#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {63252#false} is VALID [2022-02-21 04:24:41,566 INFO L290 TraceCheckUtils]: 160: Hoare triple {63252#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {63252#false} is VALID [2022-02-21 04:24:41,566 INFO L290 TraceCheckUtils]: 161: Hoare triple {63252#false} assume !(0 != start_simulation_~tmp___0~1#1); {63252#false} is VALID [2022-02-21 04:24:41,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:41,567 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:41,567 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696305780] [2022-02-21 04:24:41,567 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [696305780] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:41,567 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:41,568 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:41,568 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094344001] [2022-02-21 04:24:41,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:41,568 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:41,568 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:41,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:41,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:41,569 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:42,950 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-02-21 04:24:42,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:42,950 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,013 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:43,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:43,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:43,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-02-21 04:24:43,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:43,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:43,180 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:43,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:43,181 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-02-21 04:24:43,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:43,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:43,196 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:43,197 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2827 transitions. Second operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,198 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2827 transitions. Second operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,199 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. Second operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:43,273 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-02-21 04:24:43,273 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:43,275 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:43,275 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:43,276 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2827 transitions. [2022-02-21 04:24:43,277 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2827 transitions. [2022-02-21 04:24:43,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:43,352 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-02-21 04:24:43,352 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:43,354 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:43,354 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:43,354 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:43,354 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:43,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-02-21 04:24:43,430 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-02-21 04:24:43,430 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-02-21 04:24:43,430 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:43,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:43,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:43,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:43,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:43,434 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:43,434 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:43,435 INFO L791 eck$LassoCheckResult]: Stem: 66029#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66030#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 65849#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65565#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65566#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 66742#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66743#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65701#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65702#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66156#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65991#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65992#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65768#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65769#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66167#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 66344#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 66498#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 66535#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 65779#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65780#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 66955#L1258-2 assume !(0 == ~T1_E~0); 66074#L1263-1 assume !(0 == ~T2_E~0); 66075#L1268-1 assume !(0 == ~T3_E~0); 66378#L1273-1 assume !(0 == ~T4_E~0); 66937#L1278-1 assume !(0 == ~T5_E~0); 66798#L1283-1 assume !(0 == ~T6_E~0); 66799#L1288-1 assume !(0 == ~T7_E~0); 67035#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67023#L1298-1 assume !(0 == ~T9_E~0); 66949#L1303-1 assume !(0 == ~T10_E~0); 65594#L1308-1 assume !(0 == ~T11_E~0); 65536#L1313-1 assume !(0 == ~T12_E~0); 65537#L1318-1 assume !(0 == ~T13_E~0); 65543#L1323-1 assume !(0 == ~E_1~0); 65544#L1328-1 assume !(0 == ~E_2~0); 65711#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 66670#L1338-1 assume !(0 == ~E_4~0); 66671#L1343-1 assume !(0 == ~E_5~0); 66772#L1348-1 assume !(0 == ~E_6~0); 67058#L1353-1 assume !(0 == ~E_7~0); 66397#L1358-1 assume !(0 == ~E_8~0); 66398#L1363-1 assume !(0 == ~E_9~0); 66688#L1368-1 assume !(0 == ~E_10~0); 65373#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 65374#L1378-1 assume !(0 == ~E_12~0); 65660#L1383-1 assume !(0 == ~E_13~0); 65661#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66404#L607 assume 1 == ~m_pc~0; 66405#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 65731#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66770#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66324#L1560 assume !(0 != activate_threads_~tmp~1#1); 66325#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65556#L626 assume !(1 == ~t1_pc~0); 65557#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65825#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65826#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65995#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 65456#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65457#L645 assume 1 == ~t2_pc~0; 65573#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65530#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66207#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66208#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 66300#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66301#L664 assume 1 == ~t3_pc~0; 67057#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65297#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65298#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65956#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 65957#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66965#L683 assume !(1 == ~t4_pc~0); 66520#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 66472#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66473#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66507#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66631#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66250#L702 assume 1 == ~t5_pc~0; 66251#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66176#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66626#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66924#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 66865#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65345#L721 assume !(1 == ~t6_pc~0); 65319#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 65320#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65483#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65965#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 65966#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66567#L740 assume 1 == ~t7_pc~0; 65394#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65207#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65208#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65197#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 65198#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65901#L759 assume !(1 == ~t8_pc~0); 65902#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 65931#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66624#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66625#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 66756#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67034#L778 assume 1 == ~t9_pc~0; 66921#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 65372#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65312#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65241#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 65242#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65569#L797 assume !(1 == ~t10_pc~0); 65570#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 65688#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66822#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66072#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 66073#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66362#L816 assume 1 == ~t11_pc~0; 65277#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65278#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66033#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65972#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 65973#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 66497#L835 assume 1 == ~t12_pc~0; 66375#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 65441#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65463#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65604#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 66129#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66130#L854 assume !(1 == ~t13_pc~0); 65770#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 65771#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 65821#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65481#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 65482#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66861#L1401 assume !(1 == ~M_E~0); 65960#L1401-2 assume !(1 == ~T1_E~0); 65961#L1406-1 assume !(1 == ~T2_E~0); 66556#L1411-1 assume !(1 == ~T3_E~0); 66557#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66223#L1421-1 assume !(1 == ~T5_E~0); 65766#L1426-1 assume !(1 == ~T6_E~0); 65767#L1431-1 assume !(1 == ~T7_E~0); 65315#L1436-1 assume !(1 == ~T8_E~0); 65316#L1441-1 assume !(1 == ~T9_E~0); 66063#L1446-1 assume !(1 == ~T10_E~0); 66064#L1451-1 assume !(1 == ~T11_E~0); 66769#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 66423#L1461-1 assume !(1 == ~T13_E~0); 65984#L1466-1 assume !(1 == ~E_1~0); 65985#L1471-1 assume !(1 == ~E_2~0); 66754#L1476-1 assume !(1 == ~E_3~0); 66755#L1481-1 assume !(1 == ~E_4~0); 66903#L1486-1 assume !(1 == ~E_5~0); 65609#L1491-1 assume !(1 == ~E_6~0); 65249#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 65250#L1501-1 assume !(1 == ~E_8~0); 66061#L1506-1 assume !(1 == ~E_9~0); 66062#L1511-1 assume !(1 == ~E_10~0); 66018#L1516-1 assume !(1 == ~E_11~0); 65193#L1521-1 assume !(1 == ~E_12~0); 65194#L1526-1 assume !(1 == ~E_13~0); 65248#L1531-1 assume { :end_inline_reset_delta_events } true; 65791#L1892-2 [2022-02-21 04:24:43,435 INFO L793 eck$LassoCheckResult]: Loop: 65791#L1892-2 assume !false; 66814#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67012#L1233 assume !false; 66995#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 66327#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 66307#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 66465#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65291#L1046 assume !(0 != eval_~tmp~0#1); 65293#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65327#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66499#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 67056#L1258-5 assume !(0 == ~T1_E~0); 65469#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65470#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67048#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67054#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67055#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65693#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 65694#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 66811#L1298-3 assume !(0 == ~T9_E~0); 66812#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 66971#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 66810#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 66311#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 65471#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65472#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66895#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65614#L1338-3 assume !(0 == ~E_4~0); 65615#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66727#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 66900#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 66901#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66267#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65827#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65828#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 66584#L1378-3 assume !(0 == ~E_12~0); 66585#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 66766#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66767#L607-42 assume !(1 == ~m_pc~0); 66381#L607-44 is_master_triggered_~__retres1~0#1 := 0; 66108#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66109#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65841#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65842#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66363#L626-42 assume 1 == ~t1_pc~0; 65925#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65926#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66230#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66231#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65505#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65506#L645-42 assume !(1 == ~t2_pc~0); 66705#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 66706#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66871#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65712#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65219#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65220#L664-42 assume !(1 == ~t3_pc~0); 65746#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 65747#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66998#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66533#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66534#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66699#L683-42 assume !(1 == ~t4_pc~0); 66407#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 66408#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66540#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66960#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66961#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66805#L702-42 assume 1 == ~t5_pc~0; 66293#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65918#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66214#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66887#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 65235#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65236#L721-42 assume 1 == ~t6_pc~0; 65389#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65409#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65873#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67040#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66045#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65891#L740-42 assume 1 == ~t7_pc~0; 65892#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65629#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66170#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66025#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66026#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66299#L759-42 assume !(1 == ~t8_pc~0); 66149#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 66080#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66081#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66159#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66160#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66255#L778-42 assume !(1 == ~t9_pc~0); 66093#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 66094#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66504#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66409#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66410#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66467#L797-42 assume 1 == ~t10_pc~0; 65634#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 65635#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66636#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66945#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66505#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66506#L816-42 assume !(1 == ~t11_pc~0); 65185#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 65184#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65726#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65727#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65806#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65807#L835-42 assume 1 == ~t12_pc~0; 66211#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66104#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65781#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65782#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 66864#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66648#L854-42 assume 1 == ~t13_pc~0; 66649#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 65725#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 65335#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65336#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 65982#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65983#L1401-3 assume !(1 == ~M_E~0); 66761#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65572#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65436#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65437#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66036#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66037#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65612#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65613#L1436-3 assume !(1 == ~T8_E~0); 65199#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65200#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 66789#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 66120#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 65773#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 65774#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67051#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65713#L1476-3 assume !(1 == ~E_3~0); 65714#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66114#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65741#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65742#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66154#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 66155#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 66581#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 66571#L1516-3 assume !(1 == ~E_11~0); 66572#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 66271#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 66272#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 66666#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 65548#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 66441#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 66082#L1911 assume !(0 == start_simulation_~tmp~3#1); 66083#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 66605#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 65673#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 66543#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 65377#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65378#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65607#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 65608#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 65791#L1892-2 [2022-02-21 04:24:43,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:43,436 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2022-02-21 04:24:43,436 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:43,436 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885948596] [2022-02-21 04:24:43,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:43,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:43,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:43,454 INFO L290 TraceCheckUtils]: 0: Hoare triple {70913#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {70913#true} is VALID [2022-02-21 04:24:43,454 INFO L290 TraceCheckUtils]: 1: Hoare triple {70913#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,455 INFO L290 TraceCheckUtils]: 2: Hoare triple {70915#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,455 INFO L290 TraceCheckUtils]: 3: Hoare triple {70915#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,455 INFO L290 TraceCheckUtils]: 4: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,456 INFO L290 TraceCheckUtils]: 5: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,456 INFO L290 TraceCheckUtils]: 6: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,456 INFO L290 TraceCheckUtils]: 7: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,456 INFO L290 TraceCheckUtils]: 8: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,457 INFO L290 TraceCheckUtils]: 9: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,457 INFO L290 TraceCheckUtils]: 10: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,457 INFO L290 TraceCheckUtils]: 11: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,457 INFO L290 TraceCheckUtils]: 12: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,458 INFO L290 TraceCheckUtils]: 13: Hoare triple {70915#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {70915#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:43,458 INFO L290 TraceCheckUtils]: 14: Hoare triple {70915#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {70914#false} is VALID [2022-02-21 04:24:43,458 INFO L290 TraceCheckUtils]: 15: Hoare triple {70914#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {70914#false} is VALID [2022-02-21 04:24:43,458 INFO L290 TraceCheckUtils]: 16: Hoare triple {70914#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {70914#false} is VALID [2022-02-21 04:24:43,458 INFO L290 TraceCheckUtils]: 17: Hoare triple {70914#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {70914#false} is VALID [2022-02-21 04:24:43,458 INFO L290 TraceCheckUtils]: 18: Hoare triple {70914#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {70914#false} is VALID [2022-02-21 04:24:43,458 INFO L290 TraceCheckUtils]: 19: Hoare triple {70914#false} assume 0 == ~M_E~0;~M_E~0 := 1; {70914#false} is VALID [2022-02-21 04:24:43,459 INFO L290 TraceCheckUtils]: 20: Hoare triple {70914#false} assume !(0 == ~T1_E~0); {70914#false} is VALID [2022-02-21 04:24:43,459 INFO L290 TraceCheckUtils]: 21: Hoare triple {70914#false} assume !(0 == ~T2_E~0); {70914#false} is VALID [2022-02-21 04:24:43,459 INFO L290 TraceCheckUtils]: 22: Hoare triple {70914#false} assume !(0 == ~T3_E~0); {70914#false} is VALID [2022-02-21 04:24:43,459 INFO L290 TraceCheckUtils]: 23: Hoare triple {70914#false} assume !(0 == ~T4_E~0); {70914#false} is VALID [2022-02-21 04:24:43,459 INFO L290 TraceCheckUtils]: 24: Hoare triple {70914#false} assume !(0 == ~T5_E~0); {70914#false} is VALID [2022-02-21 04:24:43,459 INFO L290 TraceCheckUtils]: 25: Hoare triple {70914#false} assume !(0 == ~T6_E~0); {70914#false} is VALID [2022-02-21 04:24:43,459 INFO L290 TraceCheckUtils]: 26: Hoare triple {70914#false} assume !(0 == ~T7_E~0); {70914#false} is VALID [2022-02-21 04:24:43,459 INFO L290 TraceCheckUtils]: 27: Hoare triple {70914#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {70914#false} is VALID [2022-02-21 04:24:43,459 INFO L290 TraceCheckUtils]: 28: Hoare triple {70914#false} assume !(0 == ~T9_E~0); {70914#false} is VALID [2022-02-21 04:24:43,460 INFO L290 TraceCheckUtils]: 29: Hoare triple {70914#false} assume !(0 == ~T10_E~0); {70914#false} is VALID [2022-02-21 04:24:43,460 INFO L290 TraceCheckUtils]: 30: Hoare triple {70914#false} assume !(0 == ~T11_E~0); {70914#false} is VALID [2022-02-21 04:24:43,460 INFO L290 TraceCheckUtils]: 31: Hoare triple {70914#false} assume !(0 == ~T12_E~0); {70914#false} is VALID [2022-02-21 04:24:43,460 INFO L290 TraceCheckUtils]: 32: Hoare triple {70914#false} assume !(0 == ~T13_E~0); {70914#false} is VALID [2022-02-21 04:24:43,460 INFO L290 TraceCheckUtils]: 33: Hoare triple {70914#false} assume !(0 == ~E_1~0); {70914#false} is VALID [2022-02-21 04:24:43,460 INFO L290 TraceCheckUtils]: 34: Hoare triple {70914#false} assume !(0 == ~E_2~0); {70914#false} is VALID [2022-02-21 04:24:43,460 INFO L290 TraceCheckUtils]: 35: Hoare triple {70914#false} assume 0 == ~E_3~0;~E_3~0 := 1; {70914#false} is VALID [2022-02-21 04:24:43,460 INFO L290 TraceCheckUtils]: 36: Hoare triple {70914#false} assume !(0 == ~E_4~0); {70914#false} is VALID [2022-02-21 04:24:43,460 INFO L290 TraceCheckUtils]: 37: Hoare triple {70914#false} assume !(0 == ~E_5~0); {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 38: Hoare triple {70914#false} assume !(0 == ~E_6~0); {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 39: Hoare triple {70914#false} assume !(0 == ~E_7~0); {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 40: Hoare triple {70914#false} assume !(0 == ~E_8~0); {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 41: Hoare triple {70914#false} assume !(0 == ~E_9~0); {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 42: Hoare triple {70914#false} assume !(0 == ~E_10~0); {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 43: Hoare triple {70914#false} assume 0 == ~E_11~0;~E_11~0 := 1; {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 44: Hoare triple {70914#false} assume !(0 == ~E_12~0); {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 45: Hoare triple {70914#false} assume !(0 == ~E_13~0); {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 46: Hoare triple {70914#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70914#false} is VALID [2022-02-21 04:24:43,461 INFO L290 TraceCheckUtils]: 47: Hoare triple {70914#false} assume 1 == ~m_pc~0; {70914#false} is VALID [2022-02-21 04:24:43,462 INFO L290 TraceCheckUtils]: 48: Hoare triple {70914#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {70914#false} is VALID [2022-02-21 04:24:43,462 INFO L290 TraceCheckUtils]: 49: Hoare triple {70914#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70914#false} is VALID [2022-02-21 04:24:43,462 INFO L290 TraceCheckUtils]: 50: Hoare triple {70914#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70914#false} is VALID [2022-02-21 04:24:43,462 INFO L290 TraceCheckUtils]: 51: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp~1#1); {70914#false} is VALID [2022-02-21 04:24:43,462 INFO L290 TraceCheckUtils]: 52: Hoare triple {70914#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70914#false} is VALID [2022-02-21 04:24:43,462 INFO L290 TraceCheckUtils]: 53: Hoare triple {70914#false} assume !(1 == ~t1_pc~0); {70914#false} is VALID [2022-02-21 04:24:43,462 INFO L290 TraceCheckUtils]: 54: Hoare triple {70914#false} is_transmit1_triggered_~__retres1~1#1 := 0; {70914#false} is VALID [2022-02-21 04:24:43,462 INFO L290 TraceCheckUtils]: 55: Hoare triple {70914#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70914#false} is VALID [2022-02-21 04:24:43,462 INFO L290 TraceCheckUtils]: 56: Hoare triple {70914#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70914#false} is VALID [2022-02-21 04:24:43,463 INFO L290 TraceCheckUtils]: 57: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___0~0#1); {70914#false} is VALID [2022-02-21 04:24:43,463 INFO L290 TraceCheckUtils]: 58: Hoare triple {70914#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70914#false} is VALID [2022-02-21 04:24:43,463 INFO L290 TraceCheckUtils]: 59: Hoare triple {70914#false} assume 1 == ~t2_pc~0; {70914#false} is VALID [2022-02-21 04:24:43,463 INFO L290 TraceCheckUtils]: 60: Hoare triple {70914#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {70914#false} is VALID [2022-02-21 04:24:43,463 INFO L290 TraceCheckUtils]: 61: Hoare triple {70914#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70914#false} is VALID [2022-02-21 04:24:43,463 INFO L290 TraceCheckUtils]: 62: Hoare triple {70914#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70914#false} is VALID [2022-02-21 04:24:43,463 INFO L290 TraceCheckUtils]: 63: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___1~0#1); {70914#false} is VALID [2022-02-21 04:24:43,463 INFO L290 TraceCheckUtils]: 64: Hoare triple {70914#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70914#false} is VALID [2022-02-21 04:24:43,463 INFO L290 TraceCheckUtils]: 65: Hoare triple {70914#false} assume 1 == ~t3_pc~0; {70914#false} is VALID [2022-02-21 04:24:43,464 INFO L290 TraceCheckUtils]: 66: Hoare triple {70914#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {70914#false} is VALID [2022-02-21 04:24:43,464 INFO L290 TraceCheckUtils]: 67: Hoare triple {70914#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70914#false} is VALID [2022-02-21 04:24:43,464 INFO L290 TraceCheckUtils]: 68: Hoare triple {70914#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {70914#false} is VALID [2022-02-21 04:24:43,464 INFO L290 TraceCheckUtils]: 69: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___2~0#1); {70914#false} is VALID [2022-02-21 04:24:43,464 INFO L290 TraceCheckUtils]: 70: Hoare triple {70914#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70914#false} is VALID [2022-02-21 04:24:43,464 INFO L290 TraceCheckUtils]: 71: Hoare triple {70914#false} assume !(1 == ~t4_pc~0); {70914#false} is VALID [2022-02-21 04:24:43,464 INFO L290 TraceCheckUtils]: 72: Hoare triple {70914#false} is_transmit4_triggered_~__retres1~4#1 := 0; {70914#false} is VALID [2022-02-21 04:24:43,464 INFO L290 TraceCheckUtils]: 73: Hoare triple {70914#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70914#false} is VALID [2022-02-21 04:24:43,464 INFO L290 TraceCheckUtils]: 74: Hoare triple {70914#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {70914#false} is VALID [2022-02-21 04:24:43,465 INFO L290 TraceCheckUtils]: 75: Hoare triple {70914#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {70914#false} is VALID [2022-02-21 04:24:43,465 INFO L290 TraceCheckUtils]: 76: Hoare triple {70914#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70914#false} is VALID [2022-02-21 04:24:43,465 INFO L290 TraceCheckUtils]: 77: Hoare triple {70914#false} assume 1 == ~t5_pc~0; {70914#false} is VALID [2022-02-21 04:24:43,465 INFO L290 TraceCheckUtils]: 78: Hoare triple {70914#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70914#false} is VALID [2022-02-21 04:24:43,465 INFO L290 TraceCheckUtils]: 79: Hoare triple {70914#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70914#false} is VALID [2022-02-21 04:24:43,465 INFO L290 TraceCheckUtils]: 80: Hoare triple {70914#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {70914#false} is VALID [2022-02-21 04:24:43,465 INFO L290 TraceCheckUtils]: 81: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___4~0#1); {70914#false} is VALID [2022-02-21 04:24:43,465 INFO L290 TraceCheckUtils]: 82: Hoare triple {70914#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70914#false} is VALID [2022-02-21 04:24:43,465 INFO L290 TraceCheckUtils]: 83: Hoare triple {70914#false} assume !(1 == ~t6_pc~0); {70914#false} is VALID [2022-02-21 04:24:43,466 INFO L290 TraceCheckUtils]: 84: Hoare triple {70914#false} is_transmit6_triggered_~__retres1~6#1 := 0; {70914#false} is VALID [2022-02-21 04:24:43,466 INFO L290 TraceCheckUtils]: 85: Hoare triple {70914#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70914#false} is VALID [2022-02-21 04:24:43,466 INFO L290 TraceCheckUtils]: 86: Hoare triple {70914#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {70914#false} is VALID [2022-02-21 04:24:43,466 INFO L290 TraceCheckUtils]: 87: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___5~0#1); {70914#false} is VALID [2022-02-21 04:24:43,466 INFO L290 TraceCheckUtils]: 88: Hoare triple {70914#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70914#false} is VALID [2022-02-21 04:24:43,466 INFO L290 TraceCheckUtils]: 89: Hoare triple {70914#false} assume 1 == ~t7_pc~0; {70914#false} is VALID [2022-02-21 04:24:43,466 INFO L290 TraceCheckUtils]: 90: Hoare triple {70914#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {70914#false} is VALID [2022-02-21 04:24:43,466 INFO L290 TraceCheckUtils]: 91: Hoare triple {70914#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70914#false} is VALID [2022-02-21 04:24:43,466 INFO L290 TraceCheckUtils]: 92: Hoare triple {70914#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {70914#false} is VALID [2022-02-21 04:24:43,467 INFO L290 TraceCheckUtils]: 93: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___6~0#1); {70914#false} is VALID [2022-02-21 04:24:43,467 INFO L290 TraceCheckUtils]: 94: Hoare triple {70914#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {70914#false} is VALID [2022-02-21 04:24:43,467 INFO L290 TraceCheckUtils]: 95: Hoare triple {70914#false} assume !(1 == ~t8_pc~0); {70914#false} is VALID [2022-02-21 04:24:43,467 INFO L290 TraceCheckUtils]: 96: Hoare triple {70914#false} is_transmit8_triggered_~__retres1~8#1 := 0; {70914#false} is VALID [2022-02-21 04:24:43,467 INFO L290 TraceCheckUtils]: 97: Hoare triple {70914#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {70914#false} is VALID [2022-02-21 04:24:43,467 INFO L290 TraceCheckUtils]: 98: Hoare triple {70914#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {70914#false} is VALID [2022-02-21 04:24:43,467 INFO L290 TraceCheckUtils]: 99: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___7~0#1); {70914#false} is VALID [2022-02-21 04:24:43,467 INFO L290 TraceCheckUtils]: 100: Hoare triple {70914#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {70914#false} is VALID [2022-02-21 04:24:43,467 INFO L290 TraceCheckUtils]: 101: Hoare triple {70914#false} assume 1 == ~t9_pc~0; {70914#false} is VALID [2022-02-21 04:24:43,468 INFO L290 TraceCheckUtils]: 102: Hoare triple {70914#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {70914#false} is VALID [2022-02-21 04:24:43,468 INFO L290 TraceCheckUtils]: 103: Hoare triple {70914#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {70914#false} is VALID [2022-02-21 04:24:43,468 INFO L290 TraceCheckUtils]: 104: Hoare triple {70914#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {70914#false} is VALID [2022-02-21 04:24:43,468 INFO L290 TraceCheckUtils]: 105: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___8~0#1); {70914#false} is VALID [2022-02-21 04:24:43,468 INFO L290 TraceCheckUtils]: 106: Hoare triple {70914#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {70914#false} is VALID [2022-02-21 04:24:43,468 INFO L290 TraceCheckUtils]: 107: Hoare triple {70914#false} assume !(1 == ~t10_pc~0); {70914#false} is VALID [2022-02-21 04:24:43,468 INFO L290 TraceCheckUtils]: 108: Hoare triple {70914#false} is_transmit10_triggered_~__retres1~10#1 := 0; {70914#false} is VALID [2022-02-21 04:24:43,468 INFO L290 TraceCheckUtils]: 109: Hoare triple {70914#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {70914#false} is VALID [2022-02-21 04:24:43,468 INFO L290 TraceCheckUtils]: 110: Hoare triple {70914#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {70914#false} is VALID [2022-02-21 04:24:43,469 INFO L290 TraceCheckUtils]: 111: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___9~0#1); {70914#false} is VALID [2022-02-21 04:24:43,469 INFO L290 TraceCheckUtils]: 112: Hoare triple {70914#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {70914#false} is VALID [2022-02-21 04:24:43,469 INFO L290 TraceCheckUtils]: 113: Hoare triple {70914#false} assume 1 == ~t11_pc~0; {70914#false} is VALID [2022-02-21 04:24:43,469 INFO L290 TraceCheckUtils]: 114: Hoare triple {70914#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {70914#false} is VALID [2022-02-21 04:24:43,469 INFO L290 TraceCheckUtils]: 115: Hoare triple {70914#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {70914#false} is VALID [2022-02-21 04:24:43,469 INFO L290 TraceCheckUtils]: 116: Hoare triple {70914#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {70914#false} is VALID [2022-02-21 04:24:43,469 INFO L290 TraceCheckUtils]: 117: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___10~0#1); {70914#false} is VALID [2022-02-21 04:24:43,469 INFO L290 TraceCheckUtils]: 118: Hoare triple {70914#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {70914#false} is VALID [2022-02-21 04:24:43,469 INFO L290 TraceCheckUtils]: 119: Hoare triple {70914#false} assume 1 == ~t12_pc~0; {70914#false} is VALID [2022-02-21 04:24:43,470 INFO L290 TraceCheckUtils]: 120: Hoare triple {70914#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {70914#false} is VALID [2022-02-21 04:24:43,470 INFO L290 TraceCheckUtils]: 121: Hoare triple {70914#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {70914#false} is VALID [2022-02-21 04:24:43,470 INFO L290 TraceCheckUtils]: 122: Hoare triple {70914#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {70914#false} is VALID [2022-02-21 04:24:43,470 INFO L290 TraceCheckUtils]: 123: Hoare triple {70914#false} assume !(0 != activate_threads_~tmp___11~0#1); {70914#false} is VALID [2022-02-21 04:24:43,470 INFO L290 TraceCheckUtils]: 124: Hoare triple {70914#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {70914#false} is VALID [2022-02-21 04:24:43,470 INFO L290 TraceCheckUtils]: 125: Hoare triple {70914#false} assume !(1 == ~t13_pc~0); {70914#false} is VALID [2022-02-21 04:24:43,470 INFO L290 TraceCheckUtils]: 126: Hoare triple {70914#false} is_transmit13_triggered_~__retres1~13#1 := 0; {70914#false} is VALID [2022-02-21 04:24:43,470 INFO L290 TraceCheckUtils]: 127: Hoare triple {70914#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {70914#false} is VALID [2022-02-21 04:24:43,470 INFO L290 TraceCheckUtils]: 128: Hoare triple {70914#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {70914#false} is VALID [2022-02-21 04:24:43,471 INFO L290 TraceCheckUtils]: 129: Hoare triple {70914#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {70914#false} is VALID [2022-02-21 04:24:43,471 INFO L290 TraceCheckUtils]: 130: Hoare triple {70914#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70914#false} is VALID [2022-02-21 04:24:43,471 INFO L290 TraceCheckUtils]: 131: Hoare triple {70914#false} assume !(1 == ~M_E~0); {70914#false} is VALID [2022-02-21 04:24:43,471 INFO L290 TraceCheckUtils]: 132: Hoare triple {70914#false} assume !(1 == ~T1_E~0); {70914#false} is VALID [2022-02-21 04:24:43,471 INFO L290 TraceCheckUtils]: 133: Hoare triple {70914#false} assume !(1 == ~T2_E~0); {70914#false} is VALID [2022-02-21 04:24:43,471 INFO L290 TraceCheckUtils]: 134: Hoare triple {70914#false} assume !(1 == ~T3_E~0); {70914#false} is VALID [2022-02-21 04:24:43,471 INFO L290 TraceCheckUtils]: 135: Hoare triple {70914#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {70914#false} is VALID [2022-02-21 04:24:43,471 INFO L290 TraceCheckUtils]: 136: Hoare triple {70914#false} assume !(1 == ~T5_E~0); {70914#false} is VALID [2022-02-21 04:24:43,471 INFO L290 TraceCheckUtils]: 137: Hoare triple {70914#false} assume !(1 == ~T6_E~0); {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 138: Hoare triple {70914#false} assume !(1 == ~T7_E~0); {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 139: Hoare triple {70914#false} assume !(1 == ~T8_E~0); {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 140: Hoare triple {70914#false} assume !(1 == ~T9_E~0); {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 141: Hoare triple {70914#false} assume !(1 == ~T10_E~0); {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 142: Hoare triple {70914#false} assume !(1 == ~T11_E~0); {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 143: Hoare triple {70914#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 144: Hoare triple {70914#false} assume !(1 == ~T13_E~0); {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 145: Hoare triple {70914#false} assume !(1 == ~E_1~0); {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 146: Hoare triple {70914#false} assume !(1 == ~E_2~0); {70914#false} is VALID [2022-02-21 04:24:43,472 INFO L290 TraceCheckUtils]: 147: Hoare triple {70914#false} assume !(1 == ~E_3~0); {70914#false} is VALID [2022-02-21 04:24:43,473 INFO L290 TraceCheckUtils]: 148: Hoare triple {70914#false} assume !(1 == ~E_4~0); {70914#false} is VALID [2022-02-21 04:24:43,473 INFO L290 TraceCheckUtils]: 149: Hoare triple {70914#false} assume !(1 == ~E_5~0); {70914#false} is VALID [2022-02-21 04:24:43,473 INFO L290 TraceCheckUtils]: 150: Hoare triple {70914#false} assume !(1 == ~E_6~0); {70914#false} is VALID [2022-02-21 04:24:43,473 INFO L290 TraceCheckUtils]: 151: Hoare triple {70914#false} assume 1 == ~E_7~0;~E_7~0 := 2; {70914#false} is VALID [2022-02-21 04:24:43,473 INFO L290 TraceCheckUtils]: 152: Hoare triple {70914#false} assume !(1 == ~E_8~0); {70914#false} is VALID [2022-02-21 04:24:43,473 INFO L290 TraceCheckUtils]: 153: Hoare triple {70914#false} assume !(1 == ~E_9~0); {70914#false} is VALID [2022-02-21 04:24:43,473 INFO L290 TraceCheckUtils]: 154: Hoare triple {70914#false} assume !(1 == ~E_10~0); {70914#false} is VALID [2022-02-21 04:24:43,473 INFO L290 TraceCheckUtils]: 155: Hoare triple {70914#false} assume !(1 == ~E_11~0); {70914#false} is VALID [2022-02-21 04:24:43,473 INFO L290 TraceCheckUtils]: 156: Hoare triple {70914#false} assume !(1 == ~E_12~0); {70914#false} is VALID [2022-02-21 04:24:43,474 INFO L290 TraceCheckUtils]: 157: Hoare triple {70914#false} assume !(1 == ~E_13~0); {70914#false} is VALID [2022-02-21 04:24:43,474 INFO L290 TraceCheckUtils]: 158: Hoare triple {70914#false} assume { :end_inline_reset_delta_events } true; {70914#false} is VALID [2022-02-21 04:24:43,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:43,474 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:43,474 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1885948596] [2022-02-21 04:24:43,474 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1885948596] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:43,475 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:43,475 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:43,475 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300018730] [2022-02-21 04:24:43,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:43,475 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:43,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:43,476 INFO L85 PathProgramCache]: Analyzing trace with hash -661545106, now seen corresponding path program 1 times [2022-02-21 04:24:43,476 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:43,476 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301025427] [2022-02-21 04:24:43,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:43,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:43,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:43,499 INFO L290 TraceCheckUtils]: 0: Hoare triple {70916#true} assume !false; {70916#true} is VALID [2022-02-21 04:24:43,500 INFO L290 TraceCheckUtils]: 1: Hoare triple {70916#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {70916#true} is VALID [2022-02-21 04:24:43,500 INFO L290 TraceCheckUtils]: 2: Hoare triple {70916#true} assume !false; {70916#true} is VALID [2022-02-21 04:24:43,500 INFO L290 TraceCheckUtils]: 3: Hoare triple {70916#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {70916#true} is VALID [2022-02-21 04:24:43,500 INFO L290 TraceCheckUtils]: 4: Hoare triple {70916#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {70916#true} is VALID [2022-02-21 04:24:43,500 INFO L290 TraceCheckUtils]: 5: Hoare triple {70916#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {70916#true} is VALID [2022-02-21 04:24:43,500 INFO L290 TraceCheckUtils]: 6: Hoare triple {70916#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {70916#true} is VALID [2022-02-21 04:24:43,500 INFO L290 TraceCheckUtils]: 7: Hoare triple {70916#true} assume !(0 != eval_~tmp~0#1); {70916#true} is VALID [2022-02-21 04:24:43,500 INFO L290 TraceCheckUtils]: 8: Hoare triple {70916#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {70916#true} is VALID [2022-02-21 04:24:43,501 INFO L290 TraceCheckUtils]: 9: Hoare triple {70916#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {70916#true} is VALID [2022-02-21 04:24:43,501 INFO L290 TraceCheckUtils]: 10: Hoare triple {70916#true} assume 0 == ~M_E~0;~M_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,501 INFO L290 TraceCheckUtils]: 11: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,501 INFO L290 TraceCheckUtils]: 12: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,502 INFO L290 TraceCheckUtils]: 13: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,502 INFO L290 TraceCheckUtils]: 14: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,502 INFO L290 TraceCheckUtils]: 15: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,503 INFO L290 TraceCheckUtils]: 16: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,504 INFO L290 TraceCheckUtils]: 17: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,505 INFO L290 TraceCheckUtils]: 18: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,505 INFO L290 TraceCheckUtils]: 19: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,506 INFO L290 TraceCheckUtils]: 20: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,507 INFO L290 TraceCheckUtils]: 21: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,507 INFO L290 TraceCheckUtils]: 22: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,507 INFO L290 TraceCheckUtils]: 23: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,507 INFO L290 TraceCheckUtils]: 24: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,508 INFO L290 TraceCheckUtils]: 25: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,508 INFO L290 TraceCheckUtils]: 26: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,508 INFO L290 TraceCheckUtils]: 27: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,509 INFO L290 TraceCheckUtils]: 28: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,509 INFO L290 TraceCheckUtils]: 29: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,509 INFO L290 TraceCheckUtils]: 30: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,510 INFO L290 TraceCheckUtils]: 31: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,510 INFO L290 TraceCheckUtils]: 32: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,510 INFO L290 TraceCheckUtils]: 33: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,511 INFO L290 TraceCheckUtils]: 34: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,511 INFO L290 TraceCheckUtils]: 35: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,511 INFO L290 TraceCheckUtils]: 36: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,511 INFO L290 TraceCheckUtils]: 37: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,512 INFO L290 TraceCheckUtils]: 38: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,512 INFO L290 TraceCheckUtils]: 39: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,512 INFO L290 TraceCheckUtils]: 40: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,513 INFO L290 TraceCheckUtils]: 41: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,513 INFO L290 TraceCheckUtils]: 42: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,513 INFO L290 TraceCheckUtils]: 43: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,514 INFO L290 TraceCheckUtils]: 44: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,514 INFO L290 TraceCheckUtils]: 45: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,514 INFO L290 TraceCheckUtils]: 46: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,514 INFO L290 TraceCheckUtils]: 47: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,515 INFO L290 TraceCheckUtils]: 48: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,515 INFO L290 TraceCheckUtils]: 49: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,515 INFO L290 TraceCheckUtils]: 50: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,516 INFO L290 TraceCheckUtils]: 51: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,516 INFO L290 TraceCheckUtils]: 52: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,516 INFO L290 TraceCheckUtils]: 53: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,517 INFO L290 TraceCheckUtils]: 54: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,517 INFO L290 TraceCheckUtils]: 55: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,517 INFO L290 TraceCheckUtils]: 56: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,518 INFO L290 TraceCheckUtils]: 57: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,518 INFO L290 TraceCheckUtils]: 58: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,518 INFO L290 TraceCheckUtils]: 59: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,518 INFO L290 TraceCheckUtils]: 60: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,519 INFO L290 TraceCheckUtils]: 61: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,519 INFO L290 TraceCheckUtils]: 62: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,519 INFO L290 TraceCheckUtils]: 63: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,520 INFO L290 TraceCheckUtils]: 64: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,520 INFO L290 TraceCheckUtils]: 65: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,520 INFO L290 TraceCheckUtils]: 66: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,521 INFO L290 TraceCheckUtils]: 67: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,521 INFO L290 TraceCheckUtils]: 68: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,521 INFO L290 TraceCheckUtils]: 69: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,521 INFO L290 TraceCheckUtils]: 70: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,522 INFO L290 TraceCheckUtils]: 71: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,522 INFO L290 TraceCheckUtils]: 72: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,522 INFO L290 TraceCheckUtils]: 73: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,522 INFO L290 TraceCheckUtils]: 74: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,523 INFO L290 TraceCheckUtils]: 75: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,523 INFO L290 TraceCheckUtils]: 76: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,523 INFO L290 TraceCheckUtils]: 77: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,524 INFO L290 TraceCheckUtils]: 78: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,524 INFO L290 TraceCheckUtils]: 79: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,524 INFO L290 TraceCheckUtils]: 80: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,524 INFO L290 TraceCheckUtils]: 81: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,525 INFO L290 TraceCheckUtils]: 82: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,525 INFO L290 TraceCheckUtils]: 83: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,525 INFO L290 TraceCheckUtils]: 84: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,525 INFO L290 TraceCheckUtils]: 85: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,526 INFO L290 TraceCheckUtils]: 86: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,526 INFO L290 TraceCheckUtils]: 87: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,526 INFO L290 TraceCheckUtils]: 88: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,526 INFO L290 TraceCheckUtils]: 89: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,527 INFO L290 TraceCheckUtils]: 90: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,527 INFO L290 TraceCheckUtils]: 91: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,527 INFO L290 TraceCheckUtils]: 92: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,528 INFO L290 TraceCheckUtils]: 93: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,528 INFO L290 TraceCheckUtils]: 94: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,528 INFO L290 TraceCheckUtils]: 95: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,528 INFO L290 TraceCheckUtils]: 96: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,529 INFO L290 TraceCheckUtils]: 97: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,529 INFO L290 TraceCheckUtils]: 98: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,529 INFO L290 TraceCheckUtils]: 99: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,529 INFO L290 TraceCheckUtils]: 100: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,530 INFO L290 TraceCheckUtils]: 101: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,530 INFO L290 TraceCheckUtils]: 102: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,530 INFO L290 TraceCheckUtils]: 103: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,530 INFO L290 TraceCheckUtils]: 104: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,530 INFO L290 TraceCheckUtils]: 105: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,531 INFO L290 TraceCheckUtils]: 106: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,531 INFO L290 TraceCheckUtils]: 107: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,531 INFO L290 TraceCheckUtils]: 108: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,532 INFO L290 TraceCheckUtils]: 109: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,533 INFO L290 TraceCheckUtils]: 110: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,535 INFO L290 TraceCheckUtils]: 111: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,536 INFO L290 TraceCheckUtils]: 112: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,536 INFO L290 TraceCheckUtils]: 113: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,537 INFO L290 TraceCheckUtils]: 114: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,537 INFO L290 TraceCheckUtils]: 115: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,537 INFO L290 TraceCheckUtils]: 116: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,538 INFO L290 TraceCheckUtils]: 117: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,539 INFO L290 TraceCheckUtils]: 118: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,541 INFO L290 TraceCheckUtils]: 119: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,542 INFO L290 TraceCheckUtils]: 120: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,542 INFO L290 TraceCheckUtils]: 121: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70918#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:43,545 INFO L290 TraceCheckUtils]: 122: Hoare triple {70918#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {70917#false} is VALID [2022-02-21 04:24:43,545 INFO L290 TraceCheckUtils]: 123: Hoare triple {70917#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,545 INFO L290 TraceCheckUtils]: 124: Hoare triple {70917#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,546 INFO L290 TraceCheckUtils]: 125: Hoare triple {70917#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,546 INFO L290 TraceCheckUtils]: 126: Hoare triple {70917#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,546 INFO L290 TraceCheckUtils]: 127: Hoare triple {70917#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,546 INFO L290 TraceCheckUtils]: 128: Hoare triple {70917#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,546 INFO L290 TraceCheckUtils]: 129: Hoare triple {70917#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,546 INFO L290 TraceCheckUtils]: 130: Hoare triple {70917#false} assume !(1 == ~T8_E~0); {70917#false} is VALID [2022-02-21 04:24:43,546 INFO L290 TraceCheckUtils]: 131: Hoare triple {70917#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,546 INFO L290 TraceCheckUtils]: 132: Hoare triple {70917#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,547 INFO L290 TraceCheckUtils]: 133: Hoare triple {70917#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,547 INFO L290 TraceCheckUtils]: 134: Hoare triple {70917#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,547 INFO L290 TraceCheckUtils]: 135: Hoare triple {70917#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,547 INFO L290 TraceCheckUtils]: 136: Hoare triple {70917#false} assume 1 == ~E_1~0;~E_1~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,547 INFO L290 TraceCheckUtils]: 137: Hoare triple {70917#false} assume 1 == ~E_2~0;~E_2~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,547 INFO L290 TraceCheckUtils]: 138: Hoare triple {70917#false} assume !(1 == ~E_3~0); {70917#false} is VALID [2022-02-21 04:24:43,547 INFO L290 TraceCheckUtils]: 139: Hoare triple {70917#false} assume 1 == ~E_4~0;~E_4~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,548 INFO L290 TraceCheckUtils]: 140: Hoare triple {70917#false} assume 1 == ~E_5~0;~E_5~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,548 INFO L290 TraceCheckUtils]: 141: Hoare triple {70917#false} assume 1 == ~E_6~0;~E_6~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,548 INFO L290 TraceCheckUtils]: 142: Hoare triple {70917#false} assume 1 == ~E_7~0;~E_7~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,548 INFO L290 TraceCheckUtils]: 143: Hoare triple {70917#false} assume 1 == ~E_8~0;~E_8~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,548 INFO L290 TraceCheckUtils]: 144: Hoare triple {70917#false} assume 1 == ~E_9~0;~E_9~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,548 INFO L290 TraceCheckUtils]: 145: Hoare triple {70917#false} assume 1 == ~E_10~0;~E_10~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,548 INFO L290 TraceCheckUtils]: 146: Hoare triple {70917#false} assume !(1 == ~E_11~0); {70917#false} is VALID [2022-02-21 04:24:43,548 INFO L290 TraceCheckUtils]: 147: Hoare triple {70917#false} assume 1 == ~E_12~0;~E_12~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,549 INFO L290 TraceCheckUtils]: 148: Hoare triple {70917#false} assume 1 == ~E_13~0;~E_13~0 := 2; {70917#false} is VALID [2022-02-21 04:24:43,549 INFO L290 TraceCheckUtils]: 149: Hoare triple {70917#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {70917#false} is VALID [2022-02-21 04:24:43,549 INFO L290 TraceCheckUtils]: 150: Hoare triple {70917#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {70917#false} is VALID [2022-02-21 04:24:43,549 INFO L290 TraceCheckUtils]: 151: Hoare triple {70917#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {70917#false} is VALID [2022-02-21 04:24:43,549 INFO L290 TraceCheckUtils]: 152: Hoare triple {70917#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {70917#false} is VALID [2022-02-21 04:24:43,549 INFO L290 TraceCheckUtils]: 153: Hoare triple {70917#false} assume !(0 == start_simulation_~tmp~3#1); {70917#false} is VALID [2022-02-21 04:24:43,550 INFO L290 TraceCheckUtils]: 154: Hoare triple {70917#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {70917#false} is VALID [2022-02-21 04:24:43,550 INFO L290 TraceCheckUtils]: 155: Hoare triple {70917#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {70917#false} is VALID [2022-02-21 04:24:43,550 INFO L290 TraceCheckUtils]: 156: Hoare triple {70917#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {70917#false} is VALID [2022-02-21 04:24:43,550 INFO L290 TraceCheckUtils]: 157: Hoare triple {70917#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {70917#false} is VALID [2022-02-21 04:24:43,550 INFO L290 TraceCheckUtils]: 158: Hoare triple {70917#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {70917#false} is VALID [2022-02-21 04:24:43,550 INFO L290 TraceCheckUtils]: 159: Hoare triple {70917#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {70917#false} is VALID [2022-02-21 04:24:43,550 INFO L290 TraceCheckUtils]: 160: Hoare triple {70917#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {70917#false} is VALID [2022-02-21 04:24:43,551 INFO L290 TraceCheckUtils]: 161: Hoare triple {70917#false} assume !(0 != start_simulation_~tmp___0~1#1); {70917#false} is VALID [2022-02-21 04:24:43,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:43,553 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:43,553 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301025427] [2022-02-21 04:24:43,553 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301025427] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:43,553 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:43,553 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:43,553 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879866976] [2022-02-21 04:24:43,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:43,554 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:43,554 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:43,554 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:43,554 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:43,555 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:44,810 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-02-21 04:24:44,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:44,810 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,906 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:44,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:44,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:45,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-02-21 04:24:45,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:45,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:45,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:45,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:45,077 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-02-21 04:24:45,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:45,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:45,092 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:45,093 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2826 transitions. Second operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,094 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2826 transitions. Second operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,096 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. Second operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:45,181 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-02-21 04:24:45,182 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:45,183 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:45,183 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:45,186 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2826 transitions. [2022-02-21 04:24:45,187 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2826 transitions. [2022-02-21 04:24:45,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:45,268 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-02-21 04:24:45,268 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:45,270 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:45,270 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:45,270 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:45,270 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:45,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-02-21 04:24:45,352 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-02-21 04:24:45,352 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-02-21 04:24:45,352 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:45,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:45,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:45,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:45,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:45,357 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:45,357 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:45,357 INFO L791 eck$LassoCheckResult]: Stem: 73694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 73695#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 73514#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73230#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73231#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 74407#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74408#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73366#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73367#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73821#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73656#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 73657#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 73433#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 73434#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 73832#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74009#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 74163#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 74200#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 73444#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73445#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 74620#L1258-2 assume !(0 == ~T1_E~0); 73739#L1263-1 assume !(0 == ~T2_E~0); 73740#L1268-1 assume !(0 == ~T3_E~0); 74043#L1273-1 assume !(0 == ~T4_E~0); 74602#L1278-1 assume !(0 == ~T5_E~0); 74463#L1283-1 assume !(0 == ~T6_E~0); 74464#L1288-1 assume !(0 == ~T7_E~0); 74700#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 74688#L1298-1 assume !(0 == ~T9_E~0); 74614#L1303-1 assume !(0 == ~T10_E~0); 73259#L1308-1 assume !(0 == ~T11_E~0); 73201#L1313-1 assume !(0 == ~T12_E~0); 73202#L1318-1 assume !(0 == ~T13_E~0); 73208#L1323-1 assume !(0 == ~E_1~0); 73209#L1328-1 assume !(0 == ~E_2~0); 73376#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 74335#L1338-1 assume !(0 == ~E_4~0); 74336#L1343-1 assume !(0 == ~E_5~0); 74437#L1348-1 assume !(0 == ~E_6~0); 74723#L1353-1 assume !(0 == ~E_7~0); 74062#L1358-1 assume !(0 == ~E_8~0); 74063#L1363-1 assume !(0 == ~E_9~0); 74353#L1368-1 assume !(0 == ~E_10~0); 73038#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 73039#L1378-1 assume !(0 == ~E_12~0); 73325#L1383-1 assume !(0 == ~E_13~0); 73326#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74069#L607 assume 1 == ~m_pc~0; 74070#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 73396#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74435#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73989#L1560 assume !(0 != activate_threads_~tmp~1#1); 73990#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73221#L626 assume !(1 == ~t1_pc~0); 73222#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73490#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73491#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73660#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 73121#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73122#L645 assume 1 == ~t2_pc~0; 73238#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 73195#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73872#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73873#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 73965#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73966#L664 assume 1 == ~t3_pc~0; 74722#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 72962#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72963#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73621#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 73622#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74630#L683 assume !(1 == ~t4_pc~0); 74185#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74137#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74138#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74172#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74296#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73915#L702 assume 1 == ~t5_pc~0; 73916#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73841#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74291#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74589#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 74530#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73010#L721 assume !(1 == ~t6_pc~0); 72984#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 72985#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73148#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 73630#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 73631#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74232#L740 assume 1 == ~t7_pc~0; 73059#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72872#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72873#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 72862#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 72863#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73566#L759 assume !(1 == ~t8_pc~0); 73567#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 73596#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74289#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74290#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 74421#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74699#L778 assume 1 == ~t9_pc~0; 74586#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 73037#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72977#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72906#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 72907#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 73234#L797 assume !(1 == ~t10_pc~0); 73235#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 73353#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74487#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73737#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 73738#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74027#L816 assume 1 == ~t11_pc~0; 72942#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72943#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 73698#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73637#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 73638#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 74162#L835 assume 1 == ~t12_pc~0; 74040#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 73106#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73128#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73269#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 73794#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 73795#L854 assume !(1 == ~t13_pc~0); 73435#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 73436#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 73486#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 73146#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 73147#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74526#L1401 assume !(1 == ~M_E~0); 73625#L1401-2 assume !(1 == ~T1_E~0); 73626#L1406-1 assume !(1 == ~T2_E~0); 74221#L1411-1 assume !(1 == ~T3_E~0); 74222#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73888#L1421-1 assume !(1 == ~T5_E~0); 73431#L1426-1 assume !(1 == ~T6_E~0); 73432#L1431-1 assume !(1 == ~T7_E~0); 72980#L1436-1 assume !(1 == ~T8_E~0); 72981#L1441-1 assume !(1 == ~T9_E~0); 73728#L1446-1 assume !(1 == ~T10_E~0); 73729#L1451-1 assume !(1 == ~T11_E~0); 74434#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 74088#L1461-1 assume !(1 == ~T13_E~0); 73649#L1466-1 assume !(1 == ~E_1~0); 73650#L1471-1 assume !(1 == ~E_2~0); 74419#L1476-1 assume !(1 == ~E_3~0); 74420#L1481-1 assume !(1 == ~E_4~0); 74568#L1486-1 assume !(1 == ~E_5~0); 73274#L1491-1 assume !(1 == ~E_6~0); 72914#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 72915#L1501-1 assume !(1 == ~E_8~0); 73726#L1506-1 assume !(1 == ~E_9~0); 73727#L1511-1 assume !(1 == ~E_10~0); 73683#L1516-1 assume !(1 == ~E_11~0); 72858#L1521-1 assume !(1 == ~E_12~0); 72859#L1526-1 assume !(1 == ~E_13~0); 72913#L1531-1 assume { :end_inline_reset_delta_events } true; 73456#L1892-2 [2022-02-21 04:24:45,358 INFO L793 eck$LassoCheckResult]: Loop: 73456#L1892-2 assume !false; 74479#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74677#L1233 assume !false; 74660#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 73992#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73972#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74130#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 72956#L1046 assume !(0 != eval_~tmp~0#1); 72958#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72992#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74164#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 74721#L1258-5 assume !(0 == ~T1_E~0); 73134#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73135#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74713#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74719#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 74720#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 73358#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 73359#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 74476#L1298-3 assume !(0 == ~T9_E~0); 74477#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 74636#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 74475#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 73976#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 73136#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73137#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 74560#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 73279#L1338-3 assume !(0 == ~E_4~0); 73280#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 74392#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74565#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 74566#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 73932#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 73492#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 73493#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 74249#L1378-3 assume !(0 == ~E_12~0); 74250#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 74431#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74432#L607-42 assume 1 == ~m_pc~0; 74045#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 73773#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73774#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73506#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 73507#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74028#L626-42 assume 1 == ~t1_pc~0; 73590#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 73591#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73895#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73896#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 73170#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73171#L645-42 assume !(1 == ~t2_pc~0); 74370#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 74371#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74536#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73377#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72884#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72885#L664-42 assume !(1 == ~t3_pc~0); 73411#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 73412#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74663#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74198#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74199#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74364#L683-42 assume 1 == ~t4_pc~0; 74729#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 74073#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74205#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74625#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74626#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74470#L702-42 assume 1 == ~t5_pc~0; 73958#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73583#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73879#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74552#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 72900#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72901#L721-42 assume !(1 == ~t6_pc~0); 73055#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 73074#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73538#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74705#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73710#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73556#L740-42 assume 1 == ~t7_pc~0; 73557#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 73294#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73835#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 73690#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73691#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73964#L759-42 assume 1 == ~t8_pc~0; 73813#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 73745#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 73746#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 73824#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 73825#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 73920#L778-42 assume 1 == ~t9_pc~0; 73757#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 73759#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74169#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74074#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 74075#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74132#L797-42 assume 1 == ~t10_pc~0; 73299#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 73300#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74301#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74610#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 74170#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74171#L816-42 assume 1 == ~t11_pc~0; 72848#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72849#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 73391#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73392#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 73471#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 73472#L835-42 assume 1 == ~t12_pc~0; 73876#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 73769#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73446#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73447#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 74529#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 74313#L854-42 assume 1 == ~t13_pc~0; 74314#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 73390#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 73000#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 73001#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 73647#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73648#L1401-3 assume !(1 == ~M_E~0); 74426#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73237#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73101#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73102#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73701#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 73702#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 73277#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 73278#L1436-3 assume !(1 == ~T8_E~0); 72864#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 72865#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 74454#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 73785#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 73438#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 73439#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 74716#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73378#L1476-3 assume !(1 == ~E_3~0); 73379#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73779#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 73406#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 73407#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73819#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 73820#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 74246#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 74236#L1516-3 assume !(1 == ~E_11~0); 74237#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 73936#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 73937#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74331#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73213#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74106#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 73747#L1911 assume !(0 == start_simulation_~tmp~3#1); 73748#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74270#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73338#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74208#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 73042#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 73043#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73272#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 73273#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 73456#L1892-2 [2022-02-21 04:24:45,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:45,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2022-02-21 04:24:45,358 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:45,358 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338700189] [2022-02-21 04:24:45,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:45,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:45,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:45,378 INFO L290 TraceCheckUtils]: 0: Hoare triple {78578#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {78578#true} is VALID [2022-02-21 04:24:45,378 INFO L290 TraceCheckUtils]: 1: Hoare triple {78578#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,378 INFO L290 TraceCheckUtils]: 2: Hoare triple {78580#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,379 INFO L290 TraceCheckUtils]: 3: Hoare triple {78580#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,391 INFO L290 TraceCheckUtils]: 4: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,392 INFO L290 TraceCheckUtils]: 5: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,392 INFO L290 TraceCheckUtils]: 6: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,392 INFO L290 TraceCheckUtils]: 7: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,392 INFO L290 TraceCheckUtils]: 8: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,393 INFO L290 TraceCheckUtils]: 9: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,393 INFO L290 TraceCheckUtils]: 10: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,393 INFO L290 TraceCheckUtils]: 11: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,393 INFO L290 TraceCheckUtils]: 12: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,394 INFO L290 TraceCheckUtils]: 13: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,394 INFO L290 TraceCheckUtils]: 14: Hoare triple {78580#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {78580#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:45,394 INFO L290 TraceCheckUtils]: 15: Hoare triple {78580#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {78579#false} is VALID [2022-02-21 04:24:45,394 INFO L290 TraceCheckUtils]: 16: Hoare triple {78579#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {78579#false} is VALID [2022-02-21 04:24:45,394 INFO L290 TraceCheckUtils]: 17: Hoare triple {78579#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 18: Hoare triple {78579#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 19: Hoare triple {78579#false} assume 0 == ~M_E~0;~M_E~0 := 1; {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 20: Hoare triple {78579#false} assume !(0 == ~T1_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 21: Hoare triple {78579#false} assume !(0 == ~T2_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 22: Hoare triple {78579#false} assume !(0 == ~T3_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 23: Hoare triple {78579#false} assume !(0 == ~T4_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 24: Hoare triple {78579#false} assume !(0 == ~T5_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 25: Hoare triple {78579#false} assume !(0 == ~T6_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 26: Hoare triple {78579#false} assume !(0 == ~T7_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 27: Hoare triple {78579#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 28: Hoare triple {78579#false} assume !(0 == ~T9_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 29: Hoare triple {78579#false} assume !(0 == ~T10_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 30: Hoare triple {78579#false} assume !(0 == ~T11_E~0); {78579#false} is VALID [2022-02-21 04:24:45,395 INFO L290 TraceCheckUtils]: 31: Hoare triple {78579#false} assume !(0 == ~T12_E~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 32: Hoare triple {78579#false} assume !(0 == ~T13_E~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 33: Hoare triple {78579#false} assume !(0 == ~E_1~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 34: Hoare triple {78579#false} assume !(0 == ~E_2~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 35: Hoare triple {78579#false} assume 0 == ~E_3~0;~E_3~0 := 1; {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 36: Hoare triple {78579#false} assume !(0 == ~E_4~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 37: Hoare triple {78579#false} assume !(0 == ~E_5~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 38: Hoare triple {78579#false} assume !(0 == ~E_6~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 39: Hoare triple {78579#false} assume !(0 == ~E_7~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 40: Hoare triple {78579#false} assume !(0 == ~E_8~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 41: Hoare triple {78579#false} assume !(0 == ~E_9~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 42: Hoare triple {78579#false} assume !(0 == ~E_10~0); {78579#false} is VALID [2022-02-21 04:24:45,396 INFO L290 TraceCheckUtils]: 43: Hoare triple {78579#false} assume 0 == ~E_11~0;~E_11~0 := 1; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 44: Hoare triple {78579#false} assume !(0 == ~E_12~0); {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 45: Hoare triple {78579#false} assume !(0 == ~E_13~0); {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 46: Hoare triple {78579#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 47: Hoare triple {78579#false} assume 1 == ~m_pc~0; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 48: Hoare triple {78579#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 49: Hoare triple {78579#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 50: Hoare triple {78579#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 51: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp~1#1); {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 52: Hoare triple {78579#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 53: Hoare triple {78579#false} assume !(1 == ~t1_pc~0); {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 54: Hoare triple {78579#false} is_transmit1_triggered_~__retres1~1#1 := 0; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 55: Hoare triple {78579#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 56: Hoare triple {78579#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 57: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___0~0#1); {78579#false} is VALID [2022-02-21 04:24:45,397 INFO L290 TraceCheckUtils]: 58: Hoare triple {78579#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 59: Hoare triple {78579#false} assume 1 == ~t2_pc~0; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 60: Hoare triple {78579#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 61: Hoare triple {78579#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 62: Hoare triple {78579#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 63: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___1~0#1); {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 64: Hoare triple {78579#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 65: Hoare triple {78579#false} assume 1 == ~t3_pc~0; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 66: Hoare triple {78579#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 67: Hoare triple {78579#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 68: Hoare triple {78579#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 69: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___2~0#1); {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 70: Hoare triple {78579#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 71: Hoare triple {78579#false} assume !(1 == ~t4_pc~0); {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 72: Hoare triple {78579#false} is_transmit4_triggered_~__retres1~4#1 := 0; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 73: Hoare triple {78579#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {78579#false} is VALID [2022-02-21 04:24:45,398 INFO L290 TraceCheckUtils]: 74: Hoare triple {78579#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 75: Hoare triple {78579#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 76: Hoare triple {78579#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 77: Hoare triple {78579#false} assume 1 == ~t5_pc~0; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 78: Hoare triple {78579#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 79: Hoare triple {78579#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 80: Hoare triple {78579#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 81: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___4~0#1); {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 82: Hoare triple {78579#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 83: Hoare triple {78579#false} assume !(1 == ~t6_pc~0); {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 84: Hoare triple {78579#false} is_transmit6_triggered_~__retres1~6#1 := 0; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 85: Hoare triple {78579#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 86: Hoare triple {78579#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 87: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___5~0#1); {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 88: Hoare triple {78579#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 89: Hoare triple {78579#false} assume 1 == ~t7_pc~0; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 90: Hoare triple {78579#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 91: Hoare triple {78579#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {78579#false} is VALID [2022-02-21 04:24:45,399 INFO L290 TraceCheckUtils]: 92: Hoare triple {78579#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 93: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___6~0#1); {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 94: Hoare triple {78579#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 95: Hoare triple {78579#false} assume !(1 == ~t8_pc~0); {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 96: Hoare triple {78579#false} is_transmit8_triggered_~__retres1~8#1 := 0; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 97: Hoare triple {78579#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 98: Hoare triple {78579#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 99: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___7~0#1); {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 100: Hoare triple {78579#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 101: Hoare triple {78579#false} assume 1 == ~t9_pc~0; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 102: Hoare triple {78579#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 103: Hoare triple {78579#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 104: Hoare triple {78579#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 105: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___8~0#1); {78579#false} is VALID [2022-02-21 04:24:45,402 INFO L290 TraceCheckUtils]: 106: Hoare triple {78579#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {78579#false} is VALID [2022-02-21 04:24:45,403 INFO L290 TraceCheckUtils]: 107: Hoare triple {78579#false} assume !(1 == ~t10_pc~0); {78579#false} is VALID [2022-02-21 04:24:45,403 INFO L290 TraceCheckUtils]: 108: Hoare triple {78579#false} is_transmit10_triggered_~__retres1~10#1 := 0; {78579#false} is VALID [2022-02-21 04:24:45,403 INFO L290 TraceCheckUtils]: 109: Hoare triple {78579#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {78579#false} is VALID [2022-02-21 04:24:45,403 INFO L290 TraceCheckUtils]: 110: Hoare triple {78579#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {78579#false} is VALID [2022-02-21 04:24:45,403 INFO L290 TraceCheckUtils]: 111: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___9~0#1); {78579#false} is VALID [2022-02-21 04:24:45,403 INFO L290 TraceCheckUtils]: 112: Hoare triple {78579#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {78579#false} is VALID [2022-02-21 04:24:45,403 INFO L290 TraceCheckUtils]: 113: Hoare triple {78579#false} assume 1 == ~t11_pc~0; {78579#false} is VALID [2022-02-21 04:24:45,403 INFO L290 TraceCheckUtils]: 114: Hoare triple {78579#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {78579#false} is VALID [2022-02-21 04:24:45,403 INFO L290 TraceCheckUtils]: 115: Hoare triple {78579#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {78579#false} is VALID [2022-02-21 04:24:45,404 INFO L290 TraceCheckUtils]: 116: Hoare triple {78579#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {78579#false} is VALID [2022-02-21 04:24:45,404 INFO L290 TraceCheckUtils]: 117: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___10~0#1); {78579#false} is VALID [2022-02-21 04:24:45,404 INFO L290 TraceCheckUtils]: 118: Hoare triple {78579#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {78579#false} is VALID [2022-02-21 04:24:45,404 INFO L290 TraceCheckUtils]: 119: Hoare triple {78579#false} assume 1 == ~t12_pc~0; {78579#false} is VALID [2022-02-21 04:24:45,404 INFO L290 TraceCheckUtils]: 120: Hoare triple {78579#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {78579#false} is VALID [2022-02-21 04:24:45,404 INFO L290 TraceCheckUtils]: 121: Hoare triple {78579#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {78579#false} is VALID [2022-02-21 04:24:45,404 INFO L290 TraceCheckUtils]: 122: Hoare triple {78579#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {78579#false} is VALID [2022-02-21 04:24:45,404 INFO L290 TraceCheckUtils]: 123: Hoare triple {78579#false} assume !(0 != activate_threads_~tmp___11~0#1); {78579#false} is VALID [2022-02-21 04:24:45,404 INFO L290 TraceCheckUtils]: 124: Hoare triple {78579#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {78579#false} is VALID [2022-02-21 04:24:45,405 INFO L290 TraceCheckUtils]: 125: Hoare triple {78579#false} assume !(1 == ~t13_pc~0); {78579#false} is VALID [2022-02-21 04:24:45,405 INFO L290 TraceCheckUtils]: 126: Hoare triple {78579#false} is_transmit13_triggered_~__retres1~13#1 := 0; {78579#false} is VALID [2022-02-21 04:24:45,405 INFO L290 TraceCheckUtils]: 127: Hoare triple {78579#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {78579#false} is VALID [2022-02-21 04:24:45,405 INFO L290 TraceCheckUtils]: 128: Hoare triple {78579#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {78579#false} is VALID [2022-02-21 04:24:45,405 INFO L290 TraceCheckUtils]: 129: Hoare triple {78579#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {78579#false} is VALID [2022-02-21 04:24:45,405 INFO L290 TraceCheckUtils]: 130: Hoare triple {78579#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {78579#false} is VALID [2022-02-21 04:24:45,405 INFO L290 TraceCheckUtils]: 131: Hoare triple {78579#false} assume !(1 == ~M_E~0); {78579#false} is VALID [2022-02-21 04:24:45,405 INFO L290 TraceCheckUtils]: 132: Hoare triple {78579#false} assume !(1 == ~T1_E~0); {78579#false} is VALID [2022-02-21 04:24:45,405 INFO L290 TraceCheckUtils]: 133: Hoare triple {78579#false} assume !(1 == ~T2_E~0); {78579#false} is VALID [2022-02-21 04:24:45,406 INFO L290 TraceCheckUtils]: 134: Hoare triple {78579#false} assume !(1 == ~T3_E~0); {78579#false} is VALID [2022-02-21 04:24:45,406 INFO L290 TraceCheckUtils]: 135: Hoare triple {78579#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {78579#false} is VALID [2022-02-21 04:24:45,406 INFO L290 TraceCheckUtils]: 136: Hoare triple {78579#false} assume !(1 == ~T5_E~0); {78579#false} is VALID [2022-02-21 04:24:45,406 INFO L290 TraceCheckUtils]: 137: Hoare triple {78579#false} assume !(1 == ~T6_E~0); {78579#false} is VALID [2022-02-21 04:24:45,406 INFO L290 TraceCheckUtils]: 138: Hoare triple {78579#false} assume !(1 == ~T7_E~0); {78579#false} is VALID [2022-02-21 04:24:45,406 INFO L290 TraceCheckUtils]: 139: Hoare triple {78579#false} assume !(1 == ~T8_E~0); {78579#false} is VALID [2022-02-21 04:24:45,406 INFO L290 TraceCheckUtils]: 140: Hoare triple {78579#false} assume !(1 == ~T9_E~0); {78579#false} is VALID [2022-02-21 04:24:45,406 INFO L290 TraceCheckUtils]: 141: Hoare triple {78579#false} assume !(1 == ~T10_E~0); {78579#false} is VALID [2022-02-21 04:24:45,406 INFO L290 TraceCheckUtils]: 142: Hoare triple {78579#false} assume !(1 == ~T11_E~0); {78579#false} is VALID [2022-02-21 04:24:45,407 INFO L290 TraceCheckUtils]: 143: Hoare triple {78579#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {78579#false} is VALID [2022-02-21 04:24:45,407 INFO L290 TraceCheckUtils]: 144: Hoare triple {78579#false} assume !(1 == ~T13_E~0); {78579#false} is VALID [2022-02-21 04:24:45,407 INFO L290 TraceCheckUtils]: 145: Hoare triple {78579#false} assume !(1 == ~E_1~0); {78579#false} is VALID [2022-02-21 04:24:45,407 INFO L290 TraceCheckUtils]: 146: Hoare triple {78579#false} assume !(1 == ~E_2~0); {78579#false} is VALID [2022-02-21 04:24:45,407 INFO L290 TraceCheckUtils]: 147: Hoare triple {78579#false} assume !(1 == ~E_3~0); {78579#false} is VALID [2022-02-21 04:24:45,407 INFO L290 TraceCheckUtils]: 148: Hoare triple {78579#false} assume !(1 == ~E_4~0); {78579#false} is VALID [2022-02-21 04:24:45,407 INFO L290 TraceCheckUtils]: 149: Hoare triple {78579#false} assume !(1 == ~E_5~0); {78579#false} is VALID [2022-02-21 04:24:45,407 INFO L290 TraceCheckUtils]: 150: Hoare triple {78579#false} assume !(1 == ~E_6~0); {78579#false} is VALID [2022-02-21 04:24:45,407 INFO L290 TraceCheckUtils]: 151: Hoare triple {78579#false} assume 1 == ~E_7~0;~E_7~0 := 2; {78579#false} is VALID [2022-02-21 04:24:45,408 INFO L290 TraceCheckUtils]: 152: Hoare triple {78579#false} assume !(1 == ~E_8~0); {78579#false} is VALID [2022-02-21 04:24:45,408 INFO L290 TraceCheckUtils]: 153: Hoare triple {78579#false} assume !(1 == ~E_9~0); {78579#false} is VALID [2022-02-21 04:24:45,408 INFO L290 TraceCheckUtils]: 154: Hoare triple {78579#false} assume !(1 == ~E_10~0); {78579#false} is VALID [2022-02-21 04:24:45,408 INFO L290 TraceCheckUtils]: 155: Hoare triple {78579#false} assume !(1 == ~E_11~0); {78579#false} is VALID [2022-02-21 04:24:45,408 INFO L290 TraceCheckUtils]: 156: Hoare triple {78579#false} assume !(1 == ~E_12~0); {78579#false} is VALID [2022-02-21 04:24:45,408 INFO L290 TraceCheckUtils]: 157: Hoare triple {78579#false} assume !(1 == ~E_13~0); {78579#false} is VALID [2022-02-21 04:24:45,408 INFO L290 TraceCheckUtils]: 158: Hoare triple {78579#false} assume { :end_inline_reset_delta_events } true; {78579#false} is VALID [2022-02-21 04:24:45,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:45,409 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:45,409 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338700189] [2022-02-21 04:24:45,409 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338700189] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:45,409 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:45,409 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:45,409 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131899716] [2022-02-21 04:24:45,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:45,410 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:45,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:45,410 INFO L85 PathProgramCache]: Analyzing trace with hash 94313074, now seen corresponding path program 1 times [2022-02-21 04:24:45,410 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:45,410 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674900980] [2022-02-21 04:24:45,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:45,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:45,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:45,463 INFO L290 TraceCheckUtils]: 0: Hoare triple {78581#true} assume !false; {78581#true} is VALID [2022-02-21 04:24:45,463 INFO L290 TraceCheckUtils]: 1: Hoare triple {78581#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {78581#true} is VALID [2022-02-21 04:24:45,463 INFO L290 TraceCheckUtils]: 2: Hoare triple {78581#true} assume !false; {78581#true} is VALID [2022-02-21 04:24:45,464 INFO L290 TraceCheckUtils]: 3: Hoare triple {78581#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {78581#true} is VALID [2022-02-21 04:24:45,464 INFO L290 TraceCheckUtils]: 4: Hoare triple {78581#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {78581#true} is VALID [2022-02-21 04:24:45,464 INFO L290 TraceCheckUtils]: 5: Hoare triple {78581#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {78581#true} is VALID [2022-02-21 04:24:45,464 INFO L290 TraceCheckUtils]: 6: Hoare triple {78581#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {78581#true} is VALID [2022-02-21 04:24:45,464 INFO L290 TraceCheckUtils]: 7: Hoare triple {78581#true} assume !(0 != eval_~tmp~0#1); {78581#true} is VALID [2022-02-21 04:24:45,464 INFO L290 TraceCheckUtils]: 8: Hoare triple {78581#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {78581#true} is VALID [2022-02-21 04:24:45,464 INFO L290 TraceCheckUtils]: 9: Hoare triple {78581#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {78581#true} is VALID [2022-02-21 04:24:45,465 INFO L290 TraceCheckUtils]: 10: Hoare triple {78581#true} assume 0 == ~M_E~0;~M_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,465 INFO L290 TraceCheckUtils]: 11: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,465 INFO L290 TraceCheckUtils]: 12: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,465 INFO L290 TraceCheckUtils]: 13: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,466 INFO L290 TraceCheckUtils]: 14: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,466 INFO L290 TraceCheckUtils]: 15: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,466 INFO L290 TraceCheckUtils]: 16: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,467 INFO L290 TraceCheckUtils]: 17: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,467 INFO L290 TraceCheckUtils]: 18: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,467 INFO L290 TraceCheckUtils]: 19: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,467 INFO L290 TraceCheckUtils]: 20: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,468 INFO L290 TraceCheckUtils]: 21: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,468 INFO L290 TraceCheckUtils]: 22: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,468 INFO L290 TraceCheckUtils]: 23: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,468 INFO L290 TraceCheckUtils]: 24: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,469 INFO L290 TraceCheckUtils]: 25: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,469 INFO L290 TraceCheckUtils]: 26: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,469 INFO L290 TraceCheckUtils]: 27: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,470 INFO L290 TraceCheckUtils]: 28: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,470 INFO L290 TraceCheckUtils]: 29: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,470 INFO L290 TraceCheckUtils]: 30: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,470 INFO L290 TraceCheckUtils]: 31: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,471 INFO L290 TraceCheckUtils]: 32: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,471 INFO L290 TraceCheckUtils]: 33: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,471 INFO L290 TraceCheckUtils]: 34: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,472 INFO L290 TraceCheckUtils]: 35: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,472 INFO L290 TraceCheckUtils]: 36: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,472 INFO L290 TraceCheckUtils]: 37: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,472 INFO L290 TraceCheckUtils]: 38: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,473 INFO L290 TraceCheckUtils]: 39: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,473 INFO L290 TraceCheckUtils]: 40: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,473 INFO L290 TraceCheckUtils]: 41: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,474 INFO L290 TraceCheckUtils]: 42: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,474 INFO L290 TraceCheckUtils]: 43: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,474 INFO L290 TraceCheckUtils]: 44: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,475 INFO L290 TraceCheckUtils]: 45: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,475 INFO L290 TraceCheckUtils]: 46: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,475 INFO L290 TraceCheckUtils]: 47: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,476 INFO L290 TraceCheckUtils]: 48: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,476 INFO L290 TraceCheckUtils]: 49: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,476 INFO L290 TraceCheckUtils]: 50: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,476 INFO L290 TraceCheckUtils]: 51: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,477 INFO L290 TraceCheckUtils]: 52: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,477 INFO L290 TraceCheckUtils]: 53: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,477 INFO L290 TraceCheckUtils]: 54: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,478 INFO L290 TraceCheckUtils]: 55: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,478 INFO L290 TraceCheckUtils]: 56: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,478 INFO L290 TraceCheckUtils]: 57: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,478 INFO L290 TraceCheckUtils]: 58: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,479 INFO L290 TraceCheckUtils]: 59: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,479 INFO L290 TraceCheckUtils]: 60: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,479 INFO L290 TraceCheckUtils]: 61: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,480 INFO L290 TraceCheckUtils]: 62: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,480 INFO L290 TraceCheckUtils]: 63: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,480 INFO L290 TraceCheckUtils]: 64: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,480 INFO L290 TraceCheckUtils]: 65: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,481 INFO L290 TraceCheckUtils]: 66: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,481 INFO L290 TraceCheckUtils]: 67: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,481 INFO L290 TraceCheckUtils]: 68: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,481 INFO L290 TraceCheckUtils]: 69: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,482 INFO L290 TraceCheckUtils]: 70: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,482 INFO L290 TraceCheckUtils]: 71: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,482 INFO L290 TraceCheckUtils]: 72: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,483 INFO L290 TraceCheckUtils]: 73: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,483 INFO L290 TraceCheckUtils]: 74: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,483 INFO L290 TraceCheckUtils]: 75: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,484 INFO L290 TraceCheckUtils]: 76: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,484 INFO L290 TraceCheckUtils]: 77: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,484 INFO L290 TraceCheckUtils]: 78: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,485 INFO L290 TraceCheckUtils]: 79: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,485 INFO L290 TraceCheckUtils]: 80: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,485 INFO L290 TraceCheckUtils]: 81: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,485 INFO L290 TraceCheckUtils]: 82: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,486 INFO L290 TraceCheckUtils]: 83: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,486 INFO L290 TraceCheckUtils]: 84: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,486 INFO L290 TraceCheckUtils]: 85: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,487 INFO L290 TraceCheckUtils]: 86: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,487 INFO L290 TraceCheckUtils]: 87: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,487 INFO L290 TraceCheckUtils]: 88: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,488 INFO L290 TraceCheckUtils]: 89: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,488 INFO L290 TraceCheckUtils]: 90: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,488 INFO L290 TraceCheckUtils]: 91: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,489 INFO L290 TraceCheckUtils]: 92: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,490 INFO L290 TraceCheckUtils]: 93: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,490 INFO L290 TraceCheckUtils]: 94: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,490 INFO L290 TraceCheckUtils]: 95: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,491 INFO L290 TraceCheckUtils]: 96: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,492 INFO L290 TraceCheckUtils]: 97: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,492 INFO L290 TraceCheckUtils]: 98: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,492 INFO L290 TraceCheckUtils]: 99: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,492 INFO L290 TraceCheckUtils]: 100: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,493 INFO L290 TraceCheckUtils]: 101: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,494 INFO L290 TraceCheckUtils]: 102: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,494 INFO L290 TraceCheckUtils]: 103: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,495 INFO L290 TraceCheckUtils]: 104: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,495 INFO L290 TraceCheckUtils]: 105: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,495 INFO L290 TraceCheckUtils]: 106: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,496 INFO L290 TraceCheckUtils]: 107: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,496 INFO L290 TraceCheckUtils]: 108: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,496 INFO L290 TraceCheckUtils]: 109: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,496 INFO L290 TraceCheckUtils]: 110: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,497 INFO L290 TraceCheckUtils]: 111: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,497 INFO L290 TraceCheckUtils]: 112: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,497 INFO L290 TraceCheckUtils]: 113: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,498 INFO L290 TraceCheckUtils]: 114: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,498 INFO L290 TraceCheckUtils]: 115: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,498 INFO L290 TraceCheckUtils]: 116: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,499 INFO L290 TraceCheckUtils]: 117: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,499 INFO L290 TraceCheckUtils]: 118: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,499 INFO L290 TraceCheckUtils]: 119: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,499 INFO L290 TraceCheckUtils]: 120: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,500 INFO L290 TraceCheckUtils]: 121: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {78583#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,500 INFO L290 TraceCheckUtils]: 122: Hoare triple {78583#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {78582#false} is VALID [2022-02-21 04:24:45,500 INFO L290 TraceCheckUtils]: 123: Hoare triple {78582#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,500 INFO L290 TraceCheckUtils]: 124: Hoare triple {78582#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,500 INFO L290 TraceCheckUtils]: 125: Hoare triple {78582#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,501 INFO L290 TraceCheckUtils]: 126: Hoare triple {78582#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,501 INFO L290 TraceCheckUtils]: 127: Hoare triple {78582#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,501 INFO L290 TraceCheckUtils]: 128: Hoare triple {78582#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,501 INFO L290 TraceCheckUtils]: 129: Hoare triple {78582#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,501 INFO L290 TraceCheckUtils]: 130: Hoare triple {78582#false} assume !(1 == ~T8_E~0); {78582#false} is VALID [2022-02-21 04:24:45,501 INFO L290 TraceCheckUtils]: 131: Hoare triple {78582#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,501 INFO L290 TraceCheckUtils]: 132: Hoare triple {78582#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,501 INFO L290 TraceCheckUtils]: 133: Hoare triple {78582#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,501 INFO L290 TraceCheckUtils]: 134: Hoare triple {78582#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,502 INFO L290 TraceCheckUtils]: 135: Hoare triple {78582#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,502 INFO L290 TraceCheckUtils]: 136: Hoare triple {78582#false} assume 1 == ~E_1~0;~E_1~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,502 INFO L290 TraceCheckUtils]: 137: Hoare triple {78582#false} assume 1 == ~E_2~0;~E_2~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,502 INFO L290 TraceCheckUtils]: 138: Hoare triple {78582#false} assume !(1 == ~E_3~0); {78582#false} is VALID [2022-02-21 04:24:45,502 INFO L290 TraceCheckUtils]: 139: Hoare triple {78582#false} assume 1 == ~E_4~0;~E_4~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,502 INFO L290 TraceCheckUtils]: 140: Hoare triple {78582#false} assume 1 == ~E_5~0;~E_5~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,502 INFO L290 TraceCheckUtils]: 141: Hoare triple {78582#false} assume 1 == ~E_6~0;~E_6~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,502 INFO L290 TraceCheckUtils]: 142: Hoare triple {78582#false} assume 1 == ~E_7~0;~E_7~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,502 INFO L290 TraceCheckUtils]: 143: Hoare triple {78582#false} assume 1 == ~E_8~0;~E_8~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,503 INFO L290 TraceCheckUtils]: 144: Hoare triple {78582#false} assume 1 == ~E_9~0;~E_9~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,503 INFO L290 TraceCheckUtils]: 145: Hoare triple {78582#false} assume 1 == ~E_10~0;~E_10~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,503 INFO L290 TraceCheckUtils]: 146: Hoare triple {78582#false} assume !(1 == ~E_11~0); {78582#false} is VALID [2022-02-21 04:24:45,503 INFO L290 TraceCheckUtils]: 147: Hoare triple {78582#false} assume 1 == ~E_12~0;~E_12~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,503 INFO L290 TraceCheckUtils]: 148: Hoare triple {78582#false} assume 1 == ~E_13~0;~E_13~0 := 2; {78582#false} is VALID [2022-02-21 04:24:45,503 INFO L290 TraceCheckUtils]: 149: Hoare triple {78582#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {78582#false} is VALID [2022-02-21 04:24:45,503 INFO L290 TraceCheckUtils]: 150: Hoare triple {78582#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {78582#false} is VALID [2022-02-21 04:24:45,503 INFO L290 TraceCheckUtils]: 151: Hoare triple {78582#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {78582#false} is VALID [2022-02-21 04:24:45,503 INFO L290 TraceCheckUtils]: 152: Hoare triple {78582#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {78582#false} is VALID [2022-02-21 04:24:45,504 INFO L290 TraceCheckUtils]: 153: Hoare triple {78582#false} assume !(0 == start_simulation_~tmp~3#1); {78582#false} is VALID [2022-02-21 04:24:45,504 INFO L290 TraceCheckUtils]: 154: Hoare triple {78582#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {78582#false} is VALID [2022-02-21 04:24:45,504 INFO L290 TraceCheckUtils]: 155: Hoare triple {78582#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {78582#false} is VALID [2022-02-21 04:24:45,504 INFO L290 TraceCheckUtils]: 156: Hoare triple {78582#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {78582#false} is VALID [2022-02-21 04:24:45,504 INFO L290 TraceCheckUtils]: 157: Hoare triple {78582#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {78582#false} is VALID [2022-02-21 04:24:45,504 INFO L290 TraceCheckUtils]: 158: Hoare triple {78582#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {78582#false} is VALID [2022-02-21 04:24:45,504 INFO L290 TraceCheckUtils]: 159: Hoare triple {78582#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {78582#false} is VALID [2022-02-21 04:24:45,504 INFO L290 TraceCheckUtils]: 160: Hoare triple {78582#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {78582#false} is VALID [2022-02-21 04:24:45,505 INFO L290 TraceCheckUtils]: 161: Hoare triple {78582#false} assume !(0 != start_simulation_~tmp___0~1#1); {78582#false} is VALID [2022-02-21 04:24:45,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:45,505 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:45,506 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [674900980] [2022-02-21 04:24:45,506 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [674900980] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:45,506 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:45,506 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:45,506 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189271278] [2022-02-21 04:24:45,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:45,507 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:45,507 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:45,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:45,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:45,508 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:46,697 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-02-21 04:24:46,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:46,697 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,774 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:46,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:46,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:46,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-02-21 04:24:46,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:46,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:46,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:46,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:46,946 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-02-21 04:24:46,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:46,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:46,985 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:46,986 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2825 transitions. Second operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,987 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2825 transitions. Second operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,988 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. Second operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,065 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-02-21 04:24:47,065 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:47,066 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:47,066 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:47,068 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2825 transitions. [2022-02-21 04:24:47,069 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2825 transitions. [2022-02-21 04:24:47,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,147 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-02-21 04:24:47,147 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:47,149 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:47,149 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:47,149 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:47,149 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:47,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-02-21 04:24:47,226 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-02-21 04:24:47,226 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-02-21 04:24:47,226 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:47,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:47,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:47,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:47,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:47,231 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:47,231 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:47,231 INFO L791 eck$LassoCheckResult]: Stem: 81359#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 81360#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 81179#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80895#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80896#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 82072#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82073#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81031#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81032#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81486#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81321#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 81322#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81098#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81099#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81497#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 81674#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 81828#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 81865#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 81109#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81110#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 82285#L1258-2 assume !(0 == ~T1_E~0); 81404#L1263-1 assume !(0 == ~T2_E~0); 81405#L1268-1 assume !(0 == ~T3_E~0); 81708#L1273-1 assume !(0 == ~T4_E~0); 82267#L1278-1 assume !(0 == ~T5_E~0); 82128#L1283-1 assume !(0 == ~T6_E~0); 82129#L1288-1 assume !(0 == ~T7_E~0); 82365#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 82353#L1298-1 assume !(0 == ~T9_E~0); 82279#L1303-1 assume !(0 == ~T10_E~0); 80924#L1308-1 assume !(0 == ~T11_E~0); 80866#L1313-1 assume !(0 == ~T12_E~0); 80867#L1318-1 assume !(0 == ~T13_E~0); 80873#L1323-1 assume !(0 == ~E_1~0); 80874#L1328-1 assume !(0 == ~E_2~0); 81041#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 82000#L1338-1 assume !(0 == ~E_4~0); 82001#L1343-1 assume !(0 == ~E_5~0); 82102#L1348-1 assume !(0 == ~E_6~0); 82388#L1353-1 assume !(0 == ~E_7~0); 81727#L1358-1 assume !(0 == ~E_8~0); 81728#L1363-1 assume !(0 == ~E_9~0); 82018#L1368-1 assume !(0 == ~E_10~0); 80703#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 80704#L1378-1 assume !(0 == ~E_12~0); 80990#L1383-1 assume !(0 == ~E_13~0); 80991#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81734#L607 assume 1 == ~m_pc~0; 81735#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 81061#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82100#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81654#L1560 assume !(0 != activate_threads_~tmp~1#1); 81655#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80886#L626 assume !(1 == ~t1_pc~0); 80887#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81155#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81156#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81325#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 80786#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80787#L645 assume 1 == ~t2_pc~0; 80903#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 80860#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81537#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81538#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 81630#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81631#L664 assume 1 == ~t3_pc~0; 82387#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 80627#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80628#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81286#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 81287#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82295#L683 assume !(1 == ~t4_pc~0); 81850#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81802#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81803#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81837#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81961#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81580#L702 assume 1 == ~t5_pc~0; 81581#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 81506#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81956#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82254#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 82195#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80675#L721 assume !(1 == ~t6_pc~0); 80649#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 80650#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80813#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81295#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 81296#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81897#L740 assume 1 == ~t7_pc~0; 80724#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 80537#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80538#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80527#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 80528#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81231#L759 assume !(1 == ~t8_pc~0); 81232#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 81261#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81954#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81955#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 82086#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82364#L778 assume 1 == ~t9_pc~0; 82251#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 80702#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 80642#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80571#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 80572#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80899#L797 assume !(1 == ~t10_pc~0); 80900#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 81018#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82152#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 81402#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 81403#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 81692#L816 assume 1 == ~t11_pc~0; 80607#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80608#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81363#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81302#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 81303#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81827#L835 assume 1 == ~t12_pc~0; 81705#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 80771#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 80793#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 80934#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 81459#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 81460#L854 assume !(1 == ~t13_pc~0); 81100#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 81101#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 81151#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 80811#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 80812#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82191#L1401 assume !(1 == ~M_E~0); 81290#L1401-2 assume !(1 == ~T1_E~0); 81291#L1406-1 assume !(1 == ~T2_E~0); 81886#L1411-1 assume !(1 == ~T3_E~0); 81887#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81553#L1421-1 assume !(1 == ~T5_E~0); 81096#L1426-1 assume !(1 == ~T6_E~0); 81097#L1431-1 assume !(1 == ~T7_E~0); 80645#L1436-1 assume !(1 == ~T8_E~0); 80646#L1441-1 assume !(1 == ~T9_E~0); 81393#L1446-1 assume !(1 == ~T10_E~0); 81394#L1451-1 assume !(1 == ~T11_E~0); 82099#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 81753#L1461-1 assume !(1 == ~T13_E~0); 81314#L1466-1 assume !(1 == ~E_1~0); 81315#L1471-1 assume !(1 == ~E_2~0); 82084#L1476-1 assume !(1 == ~E_3~0); 82085#L1481-1 assume !(1 == ~E_4~0); 82233#L1486-1 assume !(1 == ~E_5~0); 80939#L1491-1 assume !(1 == ~E_6~0); 80579#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 80580#L1501-1 assume !(1 == ~E_8~0); 81391#L1506-1 assume !(1 == ~E_9~0); 81392#L1511-1 assume !(1 == ~E_10~0); 81348#L1516-1 assume !(1 == ~E_11~0); 80523#L1521-1 assume !(1 == ~E_12~0); 80524#L1526-1 assume !(1 == ~E_13~0); 80578#L1531-1 assume { :end_inline_reset_delta_events } true; 81121#L1892-2 [2022-02-21 04:24:47,232 INFO L793 eck$LassoCheckResult]: Loop: 81121#L1892-2 assume !false; 82144#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82342#L1233 assume !false; 82325#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 81657#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 81637#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 81795#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 80621#L1046 assume !(0 != eval_~tmp~0#1); 80623#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80657#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81829#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 82386#L1258-5 assume !(0 == ~T1_E~0); 80799#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 80800#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82378#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82384#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82385#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81023#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 81024#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 82141#L1298-3 assume !(0 == ~T9_E~0); 82142#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 82301#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 82140#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 81641#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 80801#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 80802#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 82225#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80944#L1338-3 assume !(0 == ~E_4~0); 80945#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82057#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 82230#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 82231#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 81597#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 81157#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 81158#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 81914#L1378-3 assume !(0 == ~E_12~0); 81915#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 82096#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82097#L607-42 assume !(1 == ~m_pc~0); 81711#L607-44 is_master_triggered_~__retres1~0#1 := 0; 81438#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81439#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81171#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81172#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81693#L626-42 assume 1 == ~t1_pc~0; 81255#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 81256#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81560#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81561#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80835#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80836#L645-42 assume !(1 == ~t2_pc~0); 82035#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 82036#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82201#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81042#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80549#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80550#L664-42 assume !(1 == ~t3_pc~0); 81076#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 81077#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82328#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81863#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81864#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82029#L683-42 assume !(1 == ~t4_pc~0); 81737#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 81738#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81870#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82290#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82291#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82135#L702-42 assume 1 == ~t5_pc~0; 81623#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 81248#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81544#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82217#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 80565#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80566#L721-42 assume !(1 == ~t6_pc~0); 80720#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 80739#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81203#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82370#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 81375#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81221#L740-42 assume 1 == ~t7_pc~0; 81222#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 80959#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81500#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81355#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 81356#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81629#L759-42 assume !(1 == ~t8_pc~0); 81479#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 81410#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81411#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81489#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 81490#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81585#L778-42 assume !(1 == ~t9_pc~0); 81423#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 81424#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81834#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81739#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 81740#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81797#L797-42 assume 1 == ~t10_pc~0; 80964#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 80965#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81966#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82275#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 81835#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 81836#L816-42 assume 1 == ~t11_pc~0; 80513#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80514#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81056#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81057#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 81136#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81137#L835-42 assume 1 == ~t12_pc~0; 81541#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 81434#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81111#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81112#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 82194#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 81978#L854-42 assume 1 == ~t13_pc~0; 81979#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 81055#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 80665#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 80666#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 81312#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81313#L1401-3 assume !(1 == ~M_E~0); 82091#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80902#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80766#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 80767#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81366#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81367#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 80942#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 80943#L1436-3 assume !(1 == ~T8_E~0); 80529#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 80530#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 82119#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 81450#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 81103#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 81104#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 82381#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81043#L1476-3 assume !(1 == ~E_3~0); 81044#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81444#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81071#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81072#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81484#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 81485#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 81911#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 81901#L1516-3 assume !(1 == ~E_11~0); 81902#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 81601#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 81602#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 81996#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 80878#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 81771#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 81412#L1911 assume !(0 == start_simulation_~tmp~3#1); 81413#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 81935#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 81003#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 81873#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 80707#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80708#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80937#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 80938#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 81121#L1892-2 [2022-02-21 04:24:47,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:47,232 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2022-02-21 04:24:47,232 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:47,233 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835565638] [2022-02-21 04:24:47,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:47,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:47,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:47,251 INFO L290 TraceCheckUtils]: 0: Hoare triple {86243#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {86243#true} is VALID [2022-02-21 04:24:47,251 INFO L290 TraceCheckUtils]: 1: Hoare triple {86243#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,251 INFO L290 TraceCheckUtils]: 2: Hoare triple {86245#(= ~t12_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,252 INFO L290 TraceCheckUtils]: 3: Hoare triple {86245#(= ~t12_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,252 INFO L290 TraceCheckUtils]: 4: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,252 INFO L290 TraceCheckUtils]: 5: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,252 INFO L290 TraceCheckUtils]: 6: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,253 INFO L290 TraceCheckUtils]: 7: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,253 INFO L290 TraceCheckUtils]: 8: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,253 INFO L290 TraceCheckUtils]: 9: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,254 INFO L290 TraceCheckUtils]: 10: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,254 INFO L290 TraceCheckUtils]: 11: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,254 INFO L290 TraceCheckUtils]: 12: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,254 INFO L290 TraceCheckUtils]: 13: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,255 INFO L290 TraceCheckUtils]: 14: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,255 INFO L290 TraceCheckUtils]: 15: Hoare triple {86245#(= ~t12_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {86245#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:47,255 INFO L290 TraceCheckUtils]: 16: Hoare triple {86245#(= ~t12_i~0 1)} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {86244#false} is VALID [2022-02-21 04:24:47,255 INFO L290 TraceCheckUtils]: 17: Hoare triple {86244#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {86244#false} is VALID [2022-02-21 04:24:47,255 INFO L290 TraceCheckUtils]: 18: Hoare triple {86244#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {86244#false} is VALID [2022-02-21 04:24:47,255 INFO L290 TraceCheckUtils]: 19: Hoare triple {86244#false} assume 0 == ~M_E~0;~M_E~0 := 1; {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 20: Hoare triple {86244#false} assume !(0 == ~T1_E~0); {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 21: Hoare triple {86244#false} assume !(0 == ~T2_E~0); {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 22: Hoare triple {86244#false} assume !(0 == ~T3_E~0); {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 23: Hoare triple {86244#false} assume !(0 == ~T4_E~0); {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 24: Hoare triple {86244#false} assume !(0 == ~T5_E~0); {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 25: Hoare triple {86244#false} assume !(0 == ~T6_E~0); {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 26: Hoare triple {86244#false} assume !(0 == ~T7_E~0); {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 27: Hoare triple {86244#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 28: Hoare triple {86244#false} assume !(0 == ~T9_E~0); {86244#false} is VALID [2022-02-21 04:24:47,256 INFO L290 TraceCheckUtils]: 29: Hoare triple {86244#false} assume !(0 == ~T10_E~0); {86244#false} is VALID [2022-02-21 04:24:47,257 INFO L290 TraceCheckUtils]: 30: Hoare triple {86244#false} assume !(0 == ~T11_E~0); {86244#false} is VALID [2022-02-21 04:24:47,257 INFO L290 TraceCheckUtils]: 31: Hoare triple {86244#false} assume !(0 == ~T12_E~0); {86244#false} is VALID [2022-02-21 04:24:47,257 INFO L290 TraceCheckUtils]: 32: Hoare triple {86244#false} assume !(0 == ~T13_E~0); {86244#false} is VALID [2022-02-21 04:24:47,257 INFO L290 TraceCheckUtils]: 33: Hoare triple {86244#false} assume !(0 == ~E_1~0); {86244#false} is VALID [2022-02-21 04:24:47,257 INFO L290 TraceCheckUtils]: 34: Hoare triple {86244#false} assume !(0 == ~E_2~0); {86244#false} is VALID [2022-02-21 04:24:47,257 INFO L290 TraceCheckUtils]: 35: Hoare triple {86244#false} assume 0 == ~E_3~0;~E_3~0 := 1; {86244#false} is VALID [2022-02-21 04:24:47,257 INFO L290 TraceCheckUtils]: 36: Hoare triple {86244#false} assume !(0 == ~E_4~0); {86244#false} is VALID [2022-02-21 04:24:47,257 INFO L290 TraceCheckUtils]: 37: Hoare triple {86244#false} assume !(0 == ~E_5~0); {86244#false} is VALID [2022-02-21 04:24:47,257 INFO L290 TraceCheckUtils]: 38: Hoare triple {86244#false} assume !(0 == ~E_6~0); {86244#false} is VALID [2022-02-21 04:24:47,258 INFO L290 TraceCheckUtils]: 39: Hoare triple {86244#false} assume !(0 == ~E_7~0); {86244#false} is VALID [2022-02-21 04:24:47,258 INFO L290 TraceCheckUtils]: 40: Hoare triple {86244#false} assume !(0 == ~E_8~0); {86244#false} is VALID [2022-02-21 04:24:47,258 INFO L290 TraceCheckUtils]: 41: Hoare triple {86244#false} assume !(0 == ~E_9~0); {86244#false} is VALID [2022-02-21 04:24:47,258 INFO L290 TraceCheckUtils]: 42: Hoare triple {86244#false} assume !(0 == ~E_10~0); {86244#false} is VALID [2022-02-21 04:24:47,258 INFO L290 TraceCheckUtils]: 43: Hoare triple {86244#false} assume 0 == ~E_11~0;~E_11~0 := 1; {86244#false} is VALID [2022-02-21 04:24:47,258 INFO L290 TraceCheckUtils]: 44: Hoare triple {86244#false} assume !(0 == ~E_12~0); {86244#false} is VALID [2022-02-21 04:24:47,258 INFO L290 TraceCheckUtils]: 45: Hoare triple {86244#false} assume !(0 == ~E_13~0); {86244#false} is VALID [2022-02-21 04:24:47,258 INFO L290 TraceCheckUtils]: 46: Hoare triple {86244#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {86244#false} is VALID [2022-02-21 04:24:47,258 INFO L290 TraceCheckUtils]: 47: Hoare triple {86244#false} assume 1 == ~m_pc~0; {86244#false} is VALID [2022-02-21 04:24:47,259 INFO L290 TraceCheckUtils]: 48: Hoare triple {86244#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {86244#false} is VALID [2022-02-21 04:24:47,259 INFO L290 TraceCheckUtils]: 49: Hoare triple {86244#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {86244#false} is VALID [2022-02-21 04:24:47,259 INFO L290 TraceCheckUtils]: 50: Hoare triple {86244#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {86244#false} is VALID [2022-02-21 04:24:47,259 INFO L290 TraceCheckUtils]: 51: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp~1#1); {86244#false} is VALID [2022-02-21 04:24:47,259 INFO L290 TraceCheckUtils]: 52: Hoare triple {86244#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {86244#false} is VALID [2022-02-21 04:24:47,259 INFO L290 TraceCheckUtils]: 53: Hoare triple {86244#false} assume !(1 == ~t1_pc~0); {86244#false} is VALID [2022-02-21 04:24:47,259 INFO L290 TraceCheckUtils]: 54: Hoare triple {86244#false} is_transmit1_triggered_~__retres1~1#1 := 0; {86244#false} is VALID [2022-02-21 04:24:47,259 INFO L290 TraceCheckUtils]: 55: Hoare triple {86244#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {86244#false} is VALID [2022-02-21 04:24:47,259 INFO L290 TraceCheckUtils]: 56: Hoare triple {86244#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {86244#false} is VALID [2022-02-21 04:24:47,260 INFO L290 TraceCheckUtils]: 57: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___0~0#1); {86244#false} is VALID [2022-02-21 04:24:47,260 INFO L290 TraceCheckUtils]: 58: Hoare triple {86244#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {86244#false} is VALID [2022-02-21 04:24:47,260 INFO L290 TraceCheckUtils]: 59: Hoare triple {86244#false} assume 1 == ~t2_pc~0; {86244#false} is VALID [2022-02-21 04:24:47,260 INFO L290 TraceCheckUtils]: 60: Hoare triple {86244#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {86244#false} is VALID [2022-02-21 04:24:47,260 INFO L290 TraceCheckUtils]: 61: Hoare triple {86244#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {86244#false} is VALID [2022-02-21 04:24:47,260 INFO L290 TraceCheckUtils]: 62: Hoare triple {86244#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {86244#false} is VALID [2022-02-21 04:24:47,260 INFO L290 TraceCheckUtils]: 63: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___1~0#1); {86244#false} is VALID [2022-02-21 04:24:47,260 INFO L290 TraceCheckUtils]: 64: Hoare triple {86244#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {86244#false} is VALID [2022-02-21 04:24:47,260 INFO L290 TraceCheckUtils]: 65: Hoare triple {86244#false} assume 1 == ~t3_pc~0; {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 66: Hoare triple {86244#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 67: Hoare triple {86244#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 68: Hoare triple {86244#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 69: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___2~0#1); {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 70: Hoare triple {86244#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 71: Hoare triple {86244#false} assume !(1 == ~t4_pc~0); {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 72: Hoare triple {86244#false} is_transmit4_triggered_~__retres1~4#1 := 0; {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 73: Hoare triple {86244#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 74: Hoare triple {86244#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {86244#false} is VALID [2022-02-21 04:24:47,261 INFO L290 TraceCheckUtils]: 75: Hoare triple {86244#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {86244#false} is VALID [2022-02-21 04:24:47,262 INFO L290 TraceCheckUtils]: 76: Hoare triple {86244#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {86244#false} is VALID [2022-02-21 04:24:47,262 INFO L290 TraceCheckUtils]: 77: Hoare triple {86244#false} assume 1 == ~t5_pc~0; {86244#false} is VALID [2022-02-21 04:24:47,262 INFO L290 TraceCheckUtils]: 78: Hoare triple {86244#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {86244#false} is VALID [2022-02-21 04:24:47,262 INFO L290 TraceCheckUtils]: 79: Hoare triple {86244#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {86244#false} is VALID [2022-02-21 04:24:47,262 INFO L290 TraceCheckUtils]: 80: Hoare triple {86244#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {86244#false} is VALID [2022-02-21 04:24:47,262 INFO L290 TraceCheckUtils]: 81: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___4~0#1); {86244#false} is VALID [2022-02-21 04:24:47,262 INFO L290 TraceCheckUtils]: 82: Hoare triple {86244#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {86244#false} is VALID [2022-02-21 04:24:47,262 INFO L290 TraceCheckUtils]: 83: Hoare triple {86244#false} assume !(1 == ~t6_pc~0); {86244#false} is VALID [2022-02-21 04:24:47,262 INFO L290 TraceCheckUtils]: 84: Hoare triple {86244#false} is_transmit6_triggered_~__retres1~6#1 := 0; {86244#false} is VALID [2022-02-21 04:24:47,263 INFO L290 TraceCheckUtils]: 85: Hoare triple {86244#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {86244#false} is VALID [2022-02-21 04:24:47,263 INFO L290 TraceCheckUtils]: 86: Hoare triple {86244#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {86244#false} is VALID [2022-02-21 04:24:47,263 INFO L290 TraceCheckUtils]: 87: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___5~0#1); {86244#false} is VALID [2022-02-21 04:24:47,263 INFO L290 TraceCheckUtils]: 88: Hoare triple {86244#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {86244#false} is VALID [2022-02-21 04:24:47,263 INFO L290 TraceCheckUtils]: 89: Hoare triple {86244#false} assume 1 == ~t7_pc~0; {86244#false} is VALID [2022-02-21 04:24:47,263 INFO L290 TraceCheckUtils]: 90: Hoare triple {86244#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {86244#false} is VALID [2022-02-21 04:24:47,263 INFO L290 TraceCheckUtils]: 91: Hoare triple {86244#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {86244#false} is VALID [2022-02-21 04:24:47,263 INFO L290 TraceCheckUtils]: 92: Hoare triple {86244#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {86244#false} is VALID [2022-02-21 04:24:47,264 INFO L290 TraceCheckUtils]: 93: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___6~0#1); {86244#false} is VALID [2022-02-21 04:24:47,264 INFO L290 TraceCheckUtils]: 94: Hoare triple {86244#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {86244#false} is VALID [2022-02-21 04:24:47,264 INFO L290 TraceCheckUtils]: 95: Hoare triple {86244#false} assume !(1 == ~t8_pc~0); {86244#false} is VALID [2022-02-21 04:24:47,264 INFO L290 TraceCheckUtils]: 96: Hoare triple {86244#false} is_transmit8_triggered_~__retres1~8#1 := 0; {86244#false} is VALID [2022-02-21 04:24:47,264 INFO L290 TraceCheckUtils]: 97: Hoare triple {86244#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {86244#false} is VALID [2022-02-21 04:24:47,264 INFO L290 TraceCheckUtils]: 98: Hoare triple {86244#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {86244#false} is VALID [2022-02-21 04:24:47,264 INFO L290 TraceCheckUtils]: 99: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___7~0#1); {86244#false} is VALID [2022-02-21 04:24:47,264 INFO L290 TraceCheckUtils]: 100: Hoare triple {86244#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {86244#false} is VALID [2022-02-21 04:24:47,264 INFO L290 TraceCheckUtils]: 101: Hoare triple {86244#false} assume 1 == ~t9_pc~0; {86244#false} is VALID [2022-02-21 04:24:47,265 INFO L290 TraceCheckUtils]: 102: Hoare triple {86244#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {86244#false} is VALID [2022-02-21 04:24:47,265 INFO L290 TraceCheckUtils]: 103: Hoare triple {86244#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {86244#false} is VALID [2022-02-21 04:24:47,265 INFO L290 TraceCheckUtils]: 104: Hoare triple {86244#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {86244#false} is VALID [2022-02-21 04:24:47,265 INFO L290 TraceCheckUtils]: 105: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___8~0#1); {86244#false} is VALID [2022-02-21 04:24:47,265 INFO L290 TraceCheckUtils]: 106: Hoare triple {86244#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {86244#false} is VALID [2022-02-21 04:24:47,265 INFO L290 TraceCheckUtils]: 107: Hoare triple {86244#false} assume !(1 == ~t10_pc~0); {86244#false} is VALID [2022-02-21 04:24:47,265 INFO L290 TraceCheckUtils]: 108: Hoare triple {86244#false} is_transmit10_triggered_~__retres1~10#1 := 0; {86244#false} is VALID [2022-02-21 04:24:47,265 INFO L290 TraceCheckUtils]: 109: Hoare triple {86244#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {86244#false} is VALID [2022-02-21 04:24:47,265 INFO L290 TraceCheckUtils]: 110: Hoare triple {86244#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {86244#false} is VALID [2022-02-21 04:24:47,266 INFO L290 TraceCheckUtils]: 111: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___9~0#1); {86244#false} is VALID [2022-02-21 04:24:47,266 INFO L290 TraceCheckUtils]: 112: Hoare triple {86244#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {86244#false} is VALID [2022-02-21 04:24:47,266 INFO L290 TraceCheckUtils]: 113: Hoare triple {86244#false} assume 1 == ~t11_pc~0; {86244#false} is VALID [2022-02-21 04:24:47,266 INFO L290 TraceCheckUtils]: 114: Hoare triple {86244#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {86244#false} is VALID [2022-02-21 04:24:47,266 INFO L290 TraceCheckUtils]: 115: Hoare triple {86244#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {86244#false} is VALID [2022-02-21 04:24:47,266 INFO L290 TraceCheckUtils]: 116: Hoare triple {86244#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {86244#false} is VALID [2022-02-21 04:24:47,266 INFO L290 TraceCheckUtils]: 117: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___10~0#1); {86244#false} is VALID [2022-02-21 04:24:47,266 INFO L290 TraceCheckUtils]: 118: Hoare triple {86244#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {86244#false} is VALID [2022-02-21 04:24:47,266 INFO L290 TraceCheckUtils]: 119: Hoare triple {86244#false} assume 1 == ~t12_pc~0; {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 120: Hoare triple {86244#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 121: Hoare triple {86244#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 122: Hoare triple {86244#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 123: Hoare triple {86244#false} assume !(0 != activate_threads_~tmp___11~0#1); {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 124: Hoare triple {86244#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 125: Hoare triple {86244#false} assume !(1 == ~t13_pc~0); {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 126: Hoare triple {86244#false} is_transmit13_triggered_~__retres1~13#1 := 0; {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 127: Hoare triple {86244#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 128: Hoare triple {86244#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {86244#false} is VALID [2022-02-21 04:24:47,267 INFO L290 TraceCheckUtils]: 129: Hoare triple {86244#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {86244#false} is VALID [2022-02-21 04:24:47,268 INFO L290 TraceCheckUtils]: 130: Hoare triple {86244#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {86244#false} is VALID [2022-02-21 04:24:47,268 INFO L290 TraceCheckUtils]: 131: Hoare triple {86244#false} assume !(1 == ~M_E~0); {86244#false} is VALID [2022-02-21 04:24:47,268 INFO L290 TraceCheckUtils]: 132: Hoare triple {86244#false} assume !(1 == ~T1_E~0); {86244#false} is VALID [2022-02-21 04:24:47,268 INFO L290 TraceCheckUtils]: 133: Hoare triple {86244#false} assume !(1 == ~T2_E~0); {86244#false} is VALID [2022-02-21 04:24:47,268 INFO L290 TraceCheckUtils]: 134: Hoare triple {86244#false} assume !(1 == ~T3_E~0); {86244#false} is VALID [2022-02-21 04:24:47,268 INFO L290 TraceCheckUtils]: 135: Hoare triple {86244#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {86244#false} is VALID [2022-02-21 04:24:47,268 INFO L290 TraceCheckUtils]: 136: Hoare triple {86244#false} assume !(1 == ~T5_E~0); {86244#false} is VALID [2022-02-21 04:24:47,268 INFO L290 TraceCheckUtils]: 137: Hoare triple {86244#false} assume !(1 == ~T6_E~0); {86244#false} is VALID [2022-02-21 04:24:47,268 INFO L290 TraceCheckUtils]: 138: Hoare triple {86244#false} assume !(1 == ~T7_E~0); {86244#false} is VALID [2022-02-21 04:24:47,269 INFO L290 TraceCheckUtils]: 139: Hoare triple {86244#false} assume !(1 == ~T8_E~0); {86244#false} is VALID [2022-02-21 04:24:47,269 INFO L290 TraceCheckUtils]: 140: Hoare triple {86244#false} assume !(1 == ~T9_E~0); {86244#false} is VALID [2022-02-21 04:24:47,269 INFO L290 TraceCheckUtils]: 141: Hoare triple {86244#false} assume !(1 == ~T10_E~0); {86244#false} is VALID [2022-02-21 04:24:47,269 INFO L290 TraceCheckUtils]: 142: Hoare triple {86244#false} assume !(1 == ~T11_E~0); {86244#false} is VALID [2022-02-21 04:24:47,269 INFO L290 TraceCheckUtils]: 143: Hoare triple {86244#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {86244#false} is VALID [2022-02-21 04:24:47,269 INFO L290 TraceCheckUtils]: 144: Hoare triple {86244#false} assume !(1 == ~T13_E~0); {86244#false} is VALID [2022-02-21 04:24:47,269 INFO L290 TraceCheckUtils]: 145: Hoare triple {86244#false} assume !(1 == ~E_1~0); {86244#false} is VALID [2022-02-21 04:24:47,269 INFO L290 TraceCheckUtils]: 146: Hoare triple {86244#false} assume !(1 == ~E_2~0); {86244#false} is VALID [2022-02-21 04:24:47,269 INFO L290 TraceCheckUtils]: 147: Hoare triple {86244#false} assume !(1 == ~E_3~0); {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 148: Hoare triple {86244#false} assume !(1 == ~E_4~0); {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 149: Hoare triple {86244#false} assume !(1 == ~E_5~0); {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 150: Hoare triple {86244#false} assume !(1 == ~E_6~0); {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 151: Hoare triple {86244#false} assume 1 == ~E_7~0;~E_7~0 := 2; {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 152: Hoare triple {86244#false} assume !(1 == ~E_8~0); {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 153: Hoare triple {86244#false} assume !(1 == ~E_9~0); {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 154: Hoare triple {86244#false} assume !(1 == ~E_10~0); {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 155: Hoare triple {86244#false} assume !(1 == ~E_11~0); {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 156: Hoare triple {86244#false} assume !(1 == ~E_12~0); {86244#false} is VALID [2022-02-21 04:24:47,270 INFO L290 TraceCheckUtils]: 157: Hoare triple {86244#false} assume !(1 == ~E_13~0); {86244#false} is VALID [2022-02-21 04:24:47,271 INFO L290 TraceCheckUtils]: 158: Hoare triple {86244#false} assume { :end_inline_reset_delta_events } true; {86244#false} is VALID [2022-02-21 04:24:47,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:47,271 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:47,271 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [835565638] [2022-02-21 04:24:47,271 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [835565638] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:47,271 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:47,272 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:47,272 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329724897] [2022-02-21 04:24:47,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:47,272 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:47,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:47,273 INFO L85 PathProgramCache]: Analyzing trace with hash 1682296622, now seen corresponding path program 1 times [2022-02-21 04:24:47,273 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:47,273 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811915908] [2022-02-21 04:24:47,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:47,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:47,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:47,294 INFO L290 TraceCheckUtils]: 0: Hoare triple {86246#true} assume !false; {86246#true} is VALID [2022-02-21 04:24:47,294 INFO L290 TraceCheckUtils]: 1: Hoare triple {86246#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {86246#true} is VALID [2022-02-21 04:24:47,294 INFO L290 TraceCheckUtils]: 2: Hoare triple {86246#true} assume !false; {86246#true} is VALID [2022-02-21 04:24:47,294 INFO L290 TraceCheckUtils]: 3: Hoare triple {86246#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {86246#true} is VALID [2022-02-21 04:24:47,294 INFO L290 TraceCheckUtils]: 4: Hoare triple {86246#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {86246#true} is VALID [2022-02-21 04:24:47,295 INFO L290 TraceCheckUtils]: 5: Hoare triple {86246#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {86246#true} is VALID [2022-02-21 04:24:47,295 INFO L290 TraceCheckUtils]: 6: Hoare triple {86246#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {86246#true} is VALID [2022-02-21 04:24:47,295 INFO L290 TraceCheckUtils]: 7: Hoare triple {86246#true} assume !(0 != eval_~tmp~0#1); {86246#true} is VALID [2022-02-21 04:24:47,295 INFO L290 TraceCheckUtils]: 8: Hoare triple {86246#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {86246#true} is VALID [2022-02-21 04:24:47,295 INFO L290 TraceCheckUtils]: 9: Hoare triple {86246#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {86246#true} is VALID [2022-02-21 04:24:47,295 INFO L290 TraceCheckUtils]: 10: Hoare triple {86246#true} assume 0 == ~M_E~0;~M_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,296 INFO L290 TraceCheckUtils]: 11: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,296 INFO L290 TraceCheckUtils]: 12: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,296 INFO L290 TraceCheckUtils]: 13: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,296 INFO L290 TraceCheckUtils]: 14: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,297 INFO L290 TraceCheckUtils]: 15: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,297 INFO L290 TraceCheckUtils]: 16: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,297 INFO L290 TraceCheckUtils]: 17: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,297 INFO L290 TraceCheckUtils]: 18: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,298 INFO L290 TraceCheckUtils]: 19: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,298 INFO L290 TraceCheckUtils]: 20: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,298 INFO L290 TraceCheckUtils]: 21: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,298 INFO L290 TraceCheckUtils]: 22: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,299 INFO L290 TraceCheckUtils]: 23: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,299 INFO L290 TraceCheckUtils]: 24: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,299 INFO L290 TraceCheckUtils]: 25: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,299 INFO L290 TraceCheckUtils]: 26: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,300 INFO L290 TraceCheckUtils]: 27: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,300 INFO L290 TraceCheckUtils]: 28: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,300 INFO L290 TraceCheckUtils]: 29: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,300 INFO L290 TraceCheckUtils]: 30: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,301 INFO L290 TraceCheckUtils]: 31: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,301 INFO L290 TraceCheckUtils]: 32: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,301 INFO L290 TraceCheckUtils]: 33: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,302 INFO L290 TraceCheckUtils]: 34: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,302 INFO L290 TraceCheckUtils]: 35: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,302 INFO L290 TraceCheckUtils]: 36: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,302 INFO L290 TraceCheckUtils]: 37: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,303 INFO L290 TraceCheckUtils]: 38: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,303 INFO L290 TraceCheckUtils]: 39: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,303 INFO L290 TraceCheckUtils]: 40: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,303 INFO L290 TraceCheckUtils]: 41: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,304 INFO L290 TraceCheckUtils]: 42: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,304 INFO L290 TraceCheckUtils]: 43: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,304 INFO L290 TraceCheckUtils]: 44: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,304 INFO L290 TraceCheckUtils]: 45: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,305 INFO L290 TraceCheckUtils]: 46: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,305 INFO L290 TraceCheckUtils]: 47: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,305 INFO L290 TraceCheckUtils]: 48: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,305 INFO L290 TraceCheckUtils]: 49: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,306 INFO L290 TraceCheckUtils]: 50: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,306 INFO L290 TraceCheckUtils]: 51: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,306 INFO L290 TraceCheckUtils]: 52: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,306 INFO L290 TraceCheckUtils]: 53: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,307 INFO L290 TraceCheckUtils]: 54: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,307 INFO L290 TraceCheckUtils]: 55: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,307 INFO L290 TraceCheckUtils]: 56: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,308 INFO L290 TraceCheckUtils]: 57: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,308 INFO L290 TraceCheckUtils]: 58: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,308 INFO L290 TraceCheckUtils]: 59: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,308 INFO L290 TraceCheckUtils]: 60: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,309 INFO L290 TraceCheckUtils]: 61: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,309 INFO L290 TraceCheckUtils]: 62: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,309 INFO L290 TraceCheckUtils]: 63: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,309 INFO L290 TraceCheckUtils]: 64: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,310 INFO L290 TraceCheckUtils]: 65: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,310 INFO L290 TraceCheckUtils]: 66: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,310 INFO L290 TraceCheckUtils]: 67: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,310 INFO L290 TraceCheckUtils]: 68: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,311 INFO L290 TraceCheckUtils]: 69: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,311 INFO L290 TraceCheckUtils]: 70: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,311 INFO L290 TraceCheckUtils]: 71: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,311 INFO L290 TraceCheckUtils]: 72: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,312 INFO L290 TraceCheckUtils]: 73: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,312 INFO L290 TraceCheckUtils]: 74: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,312 INFO L290 TraceCheckUtils]: 75: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,313 INFO L290 TraceCheckUtils]: 76: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,313 INFO L290 TraceCheckUtils]: 77: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,313 INFO L290 TraceCheckUtils]: 78: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,313 INFO L290 TraceCheckUtils]: 79: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,314 INFO L290 TraceCheckUtils]: 80: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,314 INFO L290 TraceCheckUtils]: 81: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,314 INFO L290 TraceCheckUtils]: 82: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,314 INFO L290 TraceCheckUtils]: 83: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,315 INFO L290 TraceCheckUtils]: 84: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,315 INFO L290 TraceCheckUtils]: 85: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,315 INFO L290 TraceCheckUtils]: 86: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,315 INFO L290 TraceCheckUtils]: 87: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,316 INFO L290 TraceCheckUtils]: 88: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,316 INFO L290 TraceCheckUtils]: 89: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,316 INFO L290 TraceCheckUtils]: 90: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,316 INFO L290 TraceCheckUtils]: 91: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,317 INFO L290 TraceCheckUtils]: 92: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,317 INFO L290 TraceCheckUtils]: 93: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,317 INFO L290 TraceCheckUtils]: 94: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,317 INFO L290 TraceCheckUtils]: 95: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,318 INFO L290 TraceCheckUtils]: 96: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,318 INFO L290 TraceCheckUtils]: 97: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,318 INFO L290 TraceCheckUtils]: 98: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,318 INFO L290 TraceCheckUtils]: 99: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,319 INFO L290 TraceCheckUtils]: 100: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,319 INFO L290 TraceCheckUtils]: 101: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,319 INFO L290 TraceCheckUtils]: 102: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,320 INFO L290 TraceCheckUtils]: 103: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,320 INFO L290 TraceCheckUtils]: 104: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,320 INFO L290 TraceCheckUtils]: 105: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,320 INFO L290 TraceCheckUtils]: 106: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,321 INFO L290 TraceCheckUtils]: 107: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,321 INFO L290 TraceCheckUtils]: 108: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,321 INFO L290 TraceCheckUtils]: 109: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,321 INFO L290 TraceCheckUtils]: 110: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,322 INFO L290 TraceCheckUtils]: 111: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,322 INFO L290 TraceCheckUtils]: 112: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,322 INFO L290 TraceCheckUtils]: 113: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,323 INFO L290 TraceCheckUtils]: 114: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,323 INFO L290 TraceCheckUtils]: 115: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,323 INFO L290 TraceCheckUtils]: 116: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,323 INFO L290 TraceCheckUtils]: 117: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,324 INFO L290 TraceCheckUtils]: 118: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,324 INFO L290 TraceCheckUtils]: 119: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,324 INFO L290 TraceCheckUtils]: 120: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,324 INFO L290 TraceCheckUtils]: 121: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {86248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,325 INFO L290 TraceCheckUtils]: 122: Hoare triple {86248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {86247#false} is VALID [2022-02-21 04:24:47,325 INFO L290 TraceCheckUtils]: 123: Hoare triple {86247#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,325 INFO L290 TraceCheckUtils]: 124: Hoare triple {86247#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,325 INFO L290 TraceCheckUtils]: 125: Hoare triple {86247#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,325 INFO L290 TraceCheckUtils]: 126: Hoare triple {86247#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,325 INFO L290 TraceCheckUtils]: 127: Hoare triple {86247#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,325 INFO L290 TraceCheckUtils]: 128: Hoare triple {86247#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,326 INFO L290 TraceCheckUtils]: 129: Hoare triple {86247#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,326 INFO L290 TraceCheckUtils]: 130: Hoare triple {86247#false} assume !(1 == ~T8_E~0); {86247#false} is VALID [2022-02-21 04:24:47,326 INFO L290 TraceCheckUtils]: 131: Hoare triple {86247#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,326 INFO L290 TraceCheckUtils]: 132: Hoare triple {86247#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,326 INFO L290 TraceCheckUtils]: 133: Hoare triple {86247#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,326 INFO L290 TraceCheckUtils]: 134: Hoare triple {86247#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,326 INFO L290 TraceCheckUtils]: 135: Hoare triple {86247#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,326 INFO L290 TraceCheckUtils]: 136: Hoare triple {86247#false} assume 1 == ~E_1~0;~E_1~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,326 INFO L290 TraceCheckUtils]: 137: Hoare triple {86247#false} assume 1 == ~E_2~0;~E_2~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 138: Hoare triple {86247#false} assume !(1 == ~E_3~0); {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 139: Hoare triple {86247#false} assume 1 == ~E_4~0;~E_4~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 140: Hoare triple {86247#false} assume 1 == ~E_5~0;~E_5~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 141: Hoare triple {86247#false} assume 1 == ~E_6~0;~E_6~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 142: Hoare triple {86247#false} assume 1 == ~E_7~0;~E_7~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 143: Hoare triple {86247#false} assume 1 == ~E_8~0;~E_8~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 144: Hoare triple {86247#false} assume 1 == ~E_9~0;~E_9~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 145: Hoare triple {86247#false} assume 1 == ~E_10~0;~E_10~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 146: Hoare triple {86247#false} assume !(1 == ~E_11~0); {86247#false} is VALID [2022-02-21 04:24:47,327 INFO L290 TraceCheckUtils]: 147: Hoare triple {86247#false} assume 1 == ~E_12~0;~E_12~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,328 INFO L290 TraceCheckUtils]: 148: Hoare triple {86247#false} assume 1 == ~E_13~0;~E_13~0 := 2; {86247#false} is VALID [2022-02-21 04:24:47,328 INFO L290 TraceCheckUtils]: 149: Hoare triple {86247#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {86247#false} is VALID [2022-02-21 04:24:47,328 INFO L290 TraceCheckUtils]: 150: Hoare triple {86247#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {86247#false} is VALID [2022-02-21 04:24:47,328 INFO L290 TraceCheckUtils]: 151: Hoare triple {86247#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {86247#false} is VALID [2022-02-21 04:24:47,328 INFO L290 TraceCheckUtils]: 152: Hoare triple {86247#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {86247#false} is VALID [2022-02-21 04:24:47,328 INFO L290 TraceCheckUtils]: 153: Hoare triple {86247#false} assume !(0 == start_simulation_~tmp~3#1); {86247#false} is VALID [2022-02-21 04:24:47,328 INFO L290 TraceCheckUtils]: 154: Hoare triple {86247#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {86247#false} is VALID [2022-02-21 04:24:47,328 INFO L290 TraceCheckUtils]: 155: Hoare triple {86247#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {86247#false} is VALID [2022-02-21 04:24:47,328 INFO L290 TraceCheckUtils]: 156: Hoare triple {86247#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {86247#false} is VALID [2022-02-21 04:24:47,329 INFO L290 TraceCheckUtils]: 157: Hoare triple {86247#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {86247#false} is VALID [2022-02-21 04:24:47,329 INFO L290 TraceCheckUtils]: 158: Hoare triple {86247#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {86247#false} is VALID [2022-02-21 04:24:47,329 INFO L290 TraceCheckUtils]: 159: Hoare triple {86247#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {86247#false} is VALID [2022-02-21 04:24:47,329 INFO L290 TraceCheckUtils]: 160: Hoare triple {86247#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {86247#false} is VALID [2022-02-21 04:24:47,329 INFO L290 TraceCheckUtils]: 161: Hoare triple {86247#false} assume !(0 != start_simulation_~tmp___0~1#1); {86247#false} is VALID [2022-02-21 04:24:47,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:47,330 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:47,330 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1811915908] [2022-02-21 04:24:47,330 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1811915908] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:47,330 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:47,330 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:47,330 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680096428] [2022-02-21 04:24:47,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:47,331 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:47,331 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:47,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:47,331 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:47,331 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:48,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:48,739 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-02-21 04:24:48,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:48,740 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:48,837 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:48,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:48,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:49,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-02-21 04:24:49,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:49,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:49,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:49,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:49,014 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-02-21 04:24:49,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:49,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:49,032 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:49,033 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2824 transitions. Second operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,035 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2824 transitions. Second operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,036 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. Second operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:49,117 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-02-21 04:24:49,117 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:49,119 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:49,119 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:49,121 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2824 transitions. [2022-02-21 04:24:49,122 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2824 transitions. [2022-02-21 04:24:49,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:49,202 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-02-21 04:24:49,202 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:49,204 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:49,204 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:49,204 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:49,205 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:49,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-02-21 04:24:49,294 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-02-21 04:24:49,294 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-02-21 04:24:49,294 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:24:49,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:49,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:49,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:49,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:49,299 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:49,299 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:49,299 INFO L791 eck$LassoCheckResult]: Stem: 89024#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 89025#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 88844#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88560#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88561#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 89737#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89738#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88696#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88697#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89151#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88986#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88987#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 88763#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 88764#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 89162#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 89339#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 89493#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 89530#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 88774#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88775#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 89950#L1258-2 assume !(0 == ~T1_E~0); 89069#L1263-1 assume !(0 == ~T2_E~0); 89070#L1268-1 assume !(0 == ~T3_E~0); 89373#L1273-1 assume !(0 == ~T4_E~0); 89932#L1278-1 assume !(0 == ~T5_E~0); 89793#L1283-1 assume !(0 == ~T6_E~0); 89794#L1288-1 assume !(0 == ~T7_E~0); 90030#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 90018#L1298-1 assume !(0 == ~T9_E~0); 89944#L1303-1 assume !(0 == ~T10_E~0); 88589#L1308-1 assume !(0 == ~T11_E~0); 88531#L1313-1 assume !(0 == ~T12_E~0); 88532#L1318-1 assume !(0 == ~T13_E~0); 88538#L1323-1 assume !(0 == ~E_1~0); 88539#L1328-1 assume !(0 == ~E_2~0); 88706#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 89665#L1338-1 assume !(0 == ~E_4~0); 89666#L1343-1 assume !(0 == ~E_5~0); 89767#L1348-1 assume !(0 == ~E_6~0); 90053#L1353-1 assume !(0 == ~E_7~0); 89392#L1358-1 assume !(0 == ~E_8~0); 89393#L1363-1 assume !(0 == ~E_9~0); 89683#L1368-1 assume !(0 == ~E_10~0); 88368#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 88369#L1378-1 assume !(0 == ~E_12~0); 88655#L1383-1 assume !(0 == ~E_13~0); 88656#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89399#L607 assume 1 == ~m_pc~0; 89400#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 88726#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89765#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 89319#L1560 assume !(0 != activate_threads_~tmp~1#1); 89320#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88551#L626 assume !(1 == ~t1_pc~0); 88552#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88820#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88821#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88990#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 88451#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88452#L645 assume 1 == ~t2_pc~0; 88568#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 88525#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89202#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89203#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 89295#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89296#L664 assume 1 == ~t3_pc~0; 90052#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88292#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88293#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88951#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 88952#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89960#L683 assume !(1 == ~t4_pc~0); 89515#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89467#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89468#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89502#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89626#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89245#L702 assume 1 == ~t5_pc~0; 89246#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89171#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89621#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89919#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 89860#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88340#L721 assume !(1 == ~t6_pc~0); 88314#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 88315#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88478#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88960#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 88961#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89562#L740 assume 1 == ~t7_pc~0; 88389#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88202#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88203#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88192#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 88193#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88896#L759 assume !(1 == ~t8_pc~0); 88897#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 88926#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89619#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 89620#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 89751#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 90029#L778 assume 1 == ~t9_pc~0; 89916#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88367#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88307#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88236#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 88237#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88564#L797 assume !(1 == ~t10_pc~0); 88565#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 88683#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89817#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 89067#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 89068#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 89357#L816 assume 1 == ~t11_pc~0; 88272#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 88273#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 89028#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 88967#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 88968#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 89492#L835 assume 1 == ~t12_pc~0; 89370#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 88436#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 88458#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 88599#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 89124#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 89125#L854 assume !(1 == ~t13_pc~0); 88765#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 88766#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 88816#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 88476#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 88477#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89856#L1401 assume !(1 == ~M_E~0); 88955#L1401-2 assume !(1 == ~T1_E~0); 88956#L1406-1 assume !(1 == ~T2_E~0); 89551#L1411-1 assume !(1 == ~T3_E~0); 89552#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89218#L1421-1 assume !(1 == ~T5_E~0); 88761#L1426-1 assume !(1 == ~T6_E~0); 88762#L1431-1 assume !(1 == ~T7_E~0); 88310#L1436-1 assume !(1 == ~T8_E~0); 88311#L1441-1 assume !(1 == ~T9_E~0); 89058#L1446-1 assume !(1 == ~T10_E~0); 89059#L1451-1 assume !(1 == ~T11_E~0); 89764#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 89418#L1461-1 assume !(1 == ~T13_E~0); 88979#L1466-1 assume !(1 == ~E_1~0); 88980#L1471-1 assume !(1 == ~E_2~0); 89749#L1476-1 assume !(1 == ~E_3~0); 89750#L1481-1 assume !(1 == ~E_4~0); 89898#L1486-1 assume !(1 == ~E_5~0); 88604#L1491-1 assume !(1 == ~E_6~0); 88244#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 88245#L1501-1 assume !(1 == ~E_8~0); 89056#L1506-1 assume !(1 == ~E_9~0); 89057#L1511-1 assume !(1 == ~E_10~0); 89013#L1516-1 assume !(1 == ~E_11~0); 88188#L1521-1 assume !(1 == ~E_12~0); 88189#L1526-1 assume !(1 == ~E_13~0); 88243#L1531-1 assume { :end_inline_reset_delta_events } true; 88786#L1892-2 [2022-02-21 04:24:49,300 INFO L793 eck$LassoCheckResult]: Loop: 88786#L1892-2 assume !false; 89809#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 90007#L1233 assume !false; 89990#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89322#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 89302#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89460#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 88286#L1046 assume !(0 != eval_~tmp~0#1); 88288#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88322#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89494#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 90051#L1258-5 assume !(0 == ~T1_E~0); 88464#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88465#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 90043#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90049#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 90050#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88688#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88689#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 89806#L1298-3 assume !(0 == ~T9_E~0); 89807#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 89966#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 89805#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 89306#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 88466#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 88467#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 89890#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88609#L1338-3 assume !(0 == ~E_4~0); 88610#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 89722#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 89895#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 89896#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 89262#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 88822#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88823#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 89579#L1378-3 assume !(0 == ~E_12~0); 89580#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 89761#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89762#L607-42 assume !(1 == ~m_pc~0); 89376#L607-44 is_master_triggered_~__retres1~0#1 := 0; 89103#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89104#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88836#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88837#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89358#L626-42 assume 1 == ~t1_pc~0; 88920#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 88921#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89225#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89226#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88500#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88501#L645-42 assume !(1 == ~t2_pc~0); 89700#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 89701#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89866#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88707#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88214#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88215#L664-42 assume !(1 == ~t3_pc~0); 88741#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 88742#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89993#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89528#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89529#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89694#L683-42 assume 1 == ~t4_pc~0; 90059#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 89403#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89535#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89955#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89956#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89800#L702-42 assume !(1 == ~t5_pc~0); 88912#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 88913#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89209#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89882#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 88230#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88231#L721-42 assume !(1 == ~t6_pc~0); 88385#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 88404#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88868#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 90035#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 89040#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88886#L740-42 assume 1 == ~t7_pc~0; 88887#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88624#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89165#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89020#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 89021#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89294#L759-42 assume 1 == ~t8_pc~0; 89143#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 89075#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89076#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 89154#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 89155#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89250#L778-42 assume !(1 == ~t9_pc~0); 89088#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 89089#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89499#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 89404#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 89405#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 89462#L797-42 assume 1 == ~t10_pc~0; 88629#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 88630#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89631#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 89940#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 89500#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 89501#L816-42 assume 1 == ~t11_pc~0; 88178#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 88179#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 88721#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 88722#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 88801#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 88802#L835-42 assume 1 == ~t12_pc~0; 89206#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 89099#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 88776#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 88777#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 89859#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 89643#L854-42 assume 1 == ~t13_pc~0; 89644#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 88720#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 88330#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 88331#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 88977#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88978#L1401-3 assume !(1 == ~M_E~0); 89756#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88567#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88431#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88432#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89031#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89032#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 88607#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 88608#L1436-3 assume !(1 == ~T8_E~0); 88194#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 88195#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 89784#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 89115#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 88768#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 88769#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 90046#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 88708#L1476-3 assume !(1 == ~E_3~0); 88709#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89109#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88736#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 88737#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89149#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 89150#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 89576#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 89566#L1516-3 assume !(1 == ~E_11~0); 89567#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 89266#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 89267#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89661#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 88543#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89436#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 89077#L1911 assume !(0 == start_simulation_~tmp~3#1); 89078#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89600#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 88668#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89538#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 88372#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88373#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88602#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 88603#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 88786#L1892-2 [2022-02-21 04:24:49,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:49,300 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2022-02-21 04:24:49,300 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:49,301 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716656947] [2022-02-21 04:24:49,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:49,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:49,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:49,336 INFO L290 TraceCheckUtils]: 0: Hoare triple {93908#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {93908#true} is VALID [2022-02-21 04:24:49,336 INFO L290 TraceCheckUtils]: 1: Hoare triple {93908#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,336 INFO L290 TraceCheckUtils]: 2: Hoare triple {93910#(= ~t13_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,337 INFO L290 TraceCheckUtils]: 3: Hoare triple {93910#(= ~t13_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,337 INFO L290 TraceCheckUtils]: 4: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,337 INFO L290 TraceCheckUtils]: 5: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,337 INFO L290 TraceCheckUtils]: 6: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,338 INFO L290 TraceCheckUtils]: 7: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,338 INFO L290 TraceCheckUtils]: 8: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,338 INFO L290 TraceCheckUtils]: 9: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,338 INFO L290 TraceCheckUtils]: 10: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,339 INFO L290 TraceCheckUtils]: 11: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,339 INFO L290 TraceCheckUtils]: 12: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,339 INFO L290 TraceCheckUtils]: 13: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,339 INFO L290 TraceCheckUtils]: 14: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,340 INFO L290 TraceCheckUtils]: 15: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,340 INFO L290 TraceCheckUtils]: 16: Hoare triple {93910#(= ~t13_i~0 1)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {93910#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:49,340 INFO L290 TraceCheckUtils]: 17: Hoare triple {93910#(= ~t13_i~0 1)} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {93909#false} is VALID [2022-02-21 04:24:49,340 INFO L290 TraceCheckUtils]: 18: Hoare triple {93909#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {93909#false} is VALID [2022-02-21 04:24:49,340 INFO L290 TraceCheckUtils]: 19: Hoare triple {93909#false} assume 0 == ~M_E~0;~M_E~0 := 1; {93909#false} is VALID [2022-02-21 04:24:49,340 INFO L290 TraceCheckUtils]: 20: Hoare triple {93909#false} assume !(0 == ~T1_E~0); {93909#false} is VALID [2022-02-21 04:24:49,341 INFO L290 TraceCheckUtils]: 21: Hoare triple {93909#false} assume !(0 == ~T2_E~0); {93909#false} is VALID [2022-02-21 04:24:49,341 INFO L290 TraceCheckUtils]: 22: Hoare triple {93909#false} assume !(0 == ~T3_E~0); {93909#false} is VALID [2022-02-21 04:24:49,341 INFO L290 TraceCheckUtils]: 23: Hoare triple {93909#false} assume !(0 == ~T4_E~0); {93909#false} is VALID [2022-02-21 04:24:49,341 INFO L290 TraceCheckUtils]: 24: Hoare triple {93909#false} assume !(0 == ~T5_E~0); {93909#false} is VALID [2022-02-21 04:24:49,341 INFO L290 TraceCheckUtils]: 25: Hoare triple {93909#false} assume !(0 == ~T6_E~0); {93909#false} is VALID [2022-02-21 04:24:49,341 INFO L290 TraceCheckUtils]: 26: Hoare triple {93909#false} assume !(0 == ~T7_E~0); {93909#false} is VALID [2022-02-21 04:24:49,341 INFO L290 TraceCheckUtils]: 27: Hoare triple {93909#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {93909#false} is VALID [2022-02-21 04:24:49,341 INFO L290 TraceCheckUtils]: 28: Hoare triple {93909#false} assume !(0 == ~T9_E~0); {93909#false} is VALID [2022-02-21 04:24:49,342 INFO L290 TraceCheckUtils]: 29: Hoare triple {93909#false} assume !(0 == ~T10_E~0); {93909#false} is VALID [2022-02-21 04:24:49,342 INFO L290 TraceCheckUtils]: 30: Hoare triple {93909#false} assume !(0 == ~T11_E~0); {93909#false} is VALID [2022-02-21 04:24:49,342 INFO L290 TraceCheckUtils]: 31: Hoare triple {93909#false} assume !(0 == ~T12_E~0); {93909#false} is VALID [2022-02-21 04:24:49,342 INFO L290 TraceCheckUtils]: 32: Hoare triple {93909#false} assume !(0 == ~T13_E~0); {93909#false} is VALID [2022-02-21 04:24:49,342 INFO L290 TraceCheckUtils]: 33: Hoare triple {93909#false} assume !(0 == ~E_1~0); {93909#false} is VALID [2022-02-21 04:24:49,342 INFO L290 TraceCheckUtils]: 34: Hoare triple {93909#false} assume !(0 == ~E_2~0); {93909#false} is VALID [2022-02-21 04:24:49,342 INFO L290 TraceCheckUtils]: 35: Hoare triple {93909#false} assume 0 == ~E_3~0;~E_3~0 := 1; {93909#false} is VALID [2022-02-21 04:24:49,342 INFO L290 TraceCheckUtils]: 36: Hoare triple {93909#false} assume !(0 == ~E_4~0); {93909#false} is VALID [2022-02-21 04:24:49,342 INFO L290 TraceCheckUtils]: 37: Hoare triple {93909#false} assume !(0 == ~E_5~0); {93909#false} is VALID [2022-02-21 04:24:49,343 INFO L290 TraceCheckUtils]: 38: Hoare triple {93909#false} assume !(0 == ~E_6~0); {93909#false} is VALID [2022-02-21 04:24:49,343 INFO L290 TraceCheckUtils]: 39: Hoare triple {93909#false} assume !(0 == ~E_7~0); {93909#false} is VALID [2022-02-21 04:24:49,343 INFO L290 TraceCheckUtils]: 40: Hoare triple {93909#false} assume !(0 == ~E_8~0); {93909#false} is VALID [2022-02-21 04:24:49,343 INFO L290 TraceCheckUtils]: 41: Hoare triple {93909#false} assume !(0 == ~E_9~0); {93909#false} is VALID [2022-02-21 04:24:49,343 INFO L290 TraceCheckUtils]: 42: Hoare triple {93909#false} assume !(0 == ~E_10~0); {93909#false} is VALID [2022-02-21 04:24:49,343 INFO L290 TraceCheckUtils]: 43: Hoare triple {93909#false} assume 0 == ~E_11~0;~E_11~0 := 1; {93909#false} is VALID [2022-02-21 04:24:49,343 INFO L290 TraceCheckUtils]: 44: Hoare triple {93909#false} assume !(0 == ~E_12~0); {93909#false} is VALID [2022-02-21 04:24:49,343 INFO L290 TraceCheckUtils]: 45: Hoare triple {93909#false} assume !(0 == ~E_13~0); {93909#false} is VALID [2022-02-21 04:24:49,343 INFO L290 TraceCheckUtils]: 46: Hoare triple {93909#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {93909#false} is VALID [2022-02-21 04:24:49,344 INFO L290 TraceCheckUtils]: 47: Hoare triple {93909#false} assume 1 == ~m_pc~0; {93909#false} is VALID [2022-02-21 04:24:49,344 INFO L290 TraceCheckUtils]: 48: Hoare triple {93909#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {93909#false} is VALID [2022-02-21 04:24:49,359 INFO L290 TraceCheckUtils]: 49: Hoare triple {93909#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {93909#false} is VALID [2022-02-21 04:24:49,359 INFO L290 TraceCheckUtils]: 50: Hoare triple {93909#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {93909#false} is VALID [2022-02-21 04:24:49,359 INFO L290 TraceCheckUtils]: 51: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp~1#1); {93909#false} is VALID [2022-02-21 04:24:49,359 INFO L290 TraceCheckUtils]: 52: Hoare triple {93909#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {93909#false} is VALID [2022-02-21 04:24:49,359 INFO L290 TraceCheckUtils]: 53: Hoare triple {93909#false} assume !(1 == ~t1_pc~0); {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 54: Hoare triple {93909#false} is_transmit1_triggered_~__retres1~1#1 := 0; {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 55: Hoare triple {93909#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 56: Hoare triple {93909#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 57: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___0~0#1); {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 58: Hoare triple {93909#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 59: Hoare triple {93909#false} assume 1 == ~t2_pc~0; {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 60: Hoare triple {93909#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 61: Hoare triple {93909#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 62: Hoare triple {93909#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {93909#false} is VALID [2022-02-21 04:24:49,360 INFO L290 TraceCheckUtils]: 63: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___1~0#1); {93909#false} is VALID [2022-02-21 04:24:49,361 INFO L290 TraceCheckUtils]: 64: Hoare triple {93909#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {93909#false} is VALID [2022-02-21 04:24:49,361 INFO L290 TraceCheckUtils]: 65: Hoare triple {93909#false} assume 1 == ~t3_pc~0; {93909#false} is VALID [2022-02-21 04:24:49,361 INFO L290 TraceCheckUtils]: 66: Hoare triple {93909#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {93909#false} is VALID [2022-02-21 04:24:49,361 INFO L290 TraceCheckUtils]: 67: Hoare triple {93909#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {93909#false} is VALID [2022-02-21 04:24:49,361 INFO L290 TraceCheckUtils]: 68: Hoare triple {93909#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {93909#false} is VALID [2022-02-21 04:24:49,361 INFO L290 TraceCheckUtils]: 69: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___2~0#1); {93909#false} is VALID [2022-02-21 04:24:49,361 INFO L290 TraceCheckUtils]: 70: Hoare triple {93909#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {93909#false} is VALID [2022-02-21 04:24:49,361 INFO L290 TraceCheckUtils]: 71: Hoare triple {93909#false} assume !(1 == ~t4_pc~0); {93909#false} is VALID [2022-02-21 04:24:49,361 INFO L290 TraceCheckUtils]: 72: Hoare triple {93909#false} is_transmit4_triggered_~__retres1~4#1 := 0; {93909#false} is VALID [2022-02-21 04:24:49,362 INFO L290 TraceCheckUtils]: 73: Hoare triple {93909#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {93909#false} is VALID [2022-02-21 04:24:49,362 INFO L290 TraceCheckUtils]: 74: Hoare triple {93909#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {93909#false} is VALID [2022-02-21 04:24:49,362 INFO L290 TraceCheckUtils]: 75: Hoare triple {93909#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {93909#false} is VALID [2022-02-21 04:24:49,362 INFO L290 TraceCheckUtils]: 76: Hoare triple {93909#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {93909#false} is VALID [2022-02-21 04:24:49,362 INFO L290 TraceCheckUtils]: 77: Hoare triple {93909#false} assume 1 == ~t5_pc~0; {93909#false} is VALID [2022-02-21 04:24:49,362 INFO L290 TraceCheckUtils]: 78: Hoare triple {93909#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {93909#false} is VALID [2022-02-21 04:24:49,362 INFO L290 TraceCheckUtils]: 79: Hoare triple {93909#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {93909#false} is VALID [2022-02-21 04:24:49,362 INFO L290 TraceCheckUtils]: 80: Hoare triple {93909#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {93909#false} is VALID [2022-02-21 04:24:49,362 INFO L290 TraceCheckUtils]: 81: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___4~0#1); {93909#false} is VALID [2022-02-21 04:24:49,363 INFO L290 TraceCheckUtils]: 82: Hoare triple {93909#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {93909#false} is VALID [2022-02-21 04:24:49,363 INFO L290 TraceCheckUtils]: 83: Hoare triple {93909#false} assume !(1 == ~t6_pc~0); {93909#false} is VALID [2022-02-21 04:24:49,363 INFO L290 TraceCheckUtils]: 84: Hoare triple {93909#false} is_transmit6_triggered_~__retres1~6#1 := 0; {93909#false} is VALID [2022-02-21 04:24:49,363 INFO L290 TraceCheckUtils]: 85: Hoare triple {93909#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {93909#false} is VALID [2022-02-21 04:24:49,363 INFO L290 TraceCheckUtils]: 86: Hoare triple {93909#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {93909#false} is VALID [2022-02-21 04:24:49,363 INFO L290 TraceCheckUtils]: 87: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___5~0#1); {93909#false} is VALID [2022-02-21 04:24:49,363 INFO L290 TraceCheckUtils]: 88: Hoare triple {93909#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {93909#false} is VALID [2022-02-21 04:24:49,363 INFO L290 TraceCheckUtils]: 89: Hoare triple {93909#false} assume 1 == ~t7_pc~0; {93909#false} is VALID [2022-02-21 04:24:49,363 INFO L290 TraceCheckUtils]: 90: Hoare triple {93909#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {93909#false} is VALID [2022-02-21 04:24:49,364 INFO L290 TraceCheckUtils]: 91: Hoare triple {93909#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {93909#false} is VALID [2022-02-21 04:24:49,364 INFO L290 TraceCheckUtils]: 92: Hoare triple {93909#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {93909#false} is VALID [2022-02-21 04:24:49,364 INFO L290 TraceCheckUtils]: 93: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___6~0#1); {93909#false} is VALID [2022-02-21 04:24:49,364 INFO L290 TraceCheckUtils]: 94: Hoare triple {93909#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {93909#false} is VALID [2022-02-21 04:24:49,364 INFO L290 TraceCheckUtils]: 95: Hoare triple {93909#false} assume !(1 == ~t8_pc~0); {93909#false} is VALID [2022-02-21 04:24:49,364 INFO L290 TraceCheckUtils]: 96: Hoare triple {93909#false} is_transmit8_triggered_~__retres1~8#1 := 0; {93909#false} is VALID [2022-02-21 04:24:49,364 INFO L290 TraceCheckUtils]: 97: Hoare triple {93909#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {93909#false} is VALID [2022-02-21 04:24:49,364 INFO L290 TraceCheckUtils]: 98: Hoare triple {93909#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {93909#false} is VALID [2022-02-21 04:24:49,364 INFO L290 TraceCheckUtils]: 99: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___7~0#1); {93909#false} is VALID [2022-02-21 04:24:49,365 INFO L290 TraceCheckUtils]: 100: Hoare triple {93909#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {93909#false} is VALID [2022-02-21 04:24:49,365 INFO L290 TraceCheckUtils]: 101: Hoare triple {93909#false} assume 1 == ~t9_pc~0; {93909#false} is VALID [2022-02-21 04:24:49,365 INFO L290 TraceCheckUtils]: 102: Hoare triple {93909#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {93909#false} is VALID [2022-02-21 04:24:49,365 INFO L290 TraceCheckUtils]: 103: Hoare triple {93909#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {93909#false} is VALID [2022-02-21 04:24:49,365 INFO L290 TraceCheckUtils]: 104: Hoare triple {93909#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {93909#false} is VALID [2022-02-21 04:24:49,365 INFO L290 TraceCheckUtils]: 105: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___8~0#1); {93909#false} is VALID [2022-02-21 04:24:49,365 INFO L290 TraceCheckUtils]: 106: Hoare triple {93909#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {93909#false} is VALID [2022-02-21 04:24:49,365 INFO L290 TraceCheckUtils]: 107: Hoare triple {93909#false} assume !(1 == ~t10_pc~0); {93909#false} is VALID [2022-02-21 04:24:49,365 INFO L290 TraceCheckUtils]: 108: Hoare triple {93909#false} is_transmit10_triggered_~__retres1~10#1 := 0; {93909#false} is VALID [2022-02-21 04:24:49,366 INFO L290 TraceCheckUtils]: 109: Hoare triple {93909#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {93909#false} is VALID [2022-02-21 04:24:49,366 INFO L290 TraceCheckUtils]: 110: Hoare triple {93909#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {93909#false} is VALID [2022-02-21 04:24:49,366 INFO L290 TraceCheckUtils]: 111: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___9~0#1); {93909#false} is VALID [2022-02-21 04:24:49,366 INFO L290 TraceCheckUtils]: 112: Hoare triple {93909#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {93909#false} is VALID [2022-02-21 04:24:49,366 INFO L290 TraceCheckUtils]: 113: Hoare triple {93909#false} assume 1 == ~t11_pc~0; {93909#false} is VALID [2022-02-21 04:24:49,366 INFO L290 TraceCheckUtils]: 114: Hoare triple {93909#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {93909#false} is VALID [2022-02-21 04:24:49,366 INFO L290 TraceCheckUtils]: 115: Hoare triple {93909#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {93909#false} is VALID [2022-02-21 04:24:49,366 INFO L290 TraceCheckUtils]: 116: Hoare triple {93909#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {93909#false} is VALID [2022-02-21 04:24:49,366 INFO L290 TraceCheckUtils]: 117: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___10~0#1); {93909#false} is VALID [2022-02-21 04:24:49,367 INFO L290 TraceCheckUtils]: 118: Hoare triple {93909#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {93909#false} is VALID [2022-02-21 04:24:49,367 INFO L290 TraceCheckUtils]: 119: Hoare triple {93909#false} assume 1 == ~t12_pc~0; {93909#false} is VALID [2022-02-21 04:24:49,367 INFO L290 TraceCheckUtils]: 120: Hoare triple {93909#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {93909#false} is VALID [2022-02-21 04:24:49,367 INFO L290 TraceCheckUtils]: 121: Hoare triple {93909#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {93909#false} is VALID [2022-02-21 04:24:49,367 INFO L290 TraceCheckUtils]: 122: Hoare triple {93909#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {93909#false} is VALID [2022-02-21 04:24:49,367 INFO L290 TraceCheckUtils]: 123: Hoare triple {93909#false} assume !(0 != activate_threads_~tmp___11~0#1); {93909#false} is VALID [2022-02-21 04:24:49,367 INFO L290 TraceCheckUtils]: 124: Hoare triple {93909#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {93909#false} is VALID [2022-02-21 04:24:49,367 INFO L290 TraceCheckUtils]: 125: Hoare triple {93909#false} assume !(1 == ~t13_pc~0); {93909#false} is VALID [2022-02-21 04:24:49,367 INFO L290 TraceCheckUtils]: 126: Hoare triple {93909#false} is_transmit13_triggered_~__retres1~13#1 := 0; {93909#false} is VALID [2022-02-21 04:24:49,368 INFO L290 TraceCheckUtils]: 127: Hoare triple {93909#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {93909#false} is VALID [2022-02-21 04:24:49,368 INFO L290 TraceCheckUtils]: 128: Hoare triple {93909#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {93909#false} is VALID [2022-02-21 04:24:49,368 INFO L290 TraceCheckUtils]: 129: Hoare triple {93909#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {93909#false} is VALID [2022-02-21 04:24:49,368 INFO L290 TraceCheckUtils]: 130: Hoare triple {93909#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {93909#false} is VALID [2022-02-21 04:24:49,368 INFO L290 TraceCheckUtils]: 131: Hoare triple {93909#false} assume !(1 == ~M_E~0); {93909#false} is VALID [2022-02-21 04:24:49,368 INFO L290 TraceCheckUtils]: 132: Hoare triple {93909#false} assume !(1 == ~T1_E~0); {93909#false} is VALID [2022-02-21 04:24:49,368 INFO L290 TraceCheckUtils]: 133: Hoare triple {93909#false} assume !(1 == ~T2_E~0); {93909#false} is VALID [2022-02-21 04:24:49,368 INFO L290 TraceCheckUtils]: 134: Hoare triple {93909#false} assume !(1 == ~T3_E~0); {93909#false} is VALID [2022-02-21 04:24:49,368 INFO L290 TraceCheckUtils]: 135: Hoare triple {93909#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 136: Hoare triple {93909#false} assume !(1 == ~T5_E~0); {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 137: Hoare triple {93909#false} assume !(1 == ~T6_E~0); {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 138: Hoare triple {93909#false} assume !(1 == ~T7_E~0); {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 139: Hoare triple {93909#false} assume !(1 == ~T8_E~0); {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 140: Hoare triple {93909#false} assume !(1 == ~T9_E~0); {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 141: Hoare triple {93909#false} assume !(1 == ~T10_E~0); {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 142: Hoare triple {93909#false} assume !(1 == ~T11_E~0); {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 143: Hoare triple {93909#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 144: Hoare triple {93909#false} assume !(1 == ~T13_E~0); {93909#false} is VALID [2022-02-21 04:24:49,369 INFO L290 TraceCheckUtils]: 145: Hoare triple {93909#false} assume !(1 == ~E_1~0); {93909#false} is VALID [2022-02-21 04:24:49,370 INFO L290 TraceCheckUtils]: 146: Hoare triple {93909#false} assume !(1 == ~E_2~0); {93909#false} is VALID [2022-02-21 04:24:49,370 INFO L290 TraceCheckUtils]: 147: Hoare triple {93909#false} assume !(1 == ~E_3~0); {93909#false} is VALID [2022-02-21 04:24:49,370 INFO L290 TraceCheckUtils]: 148: Hoare triple {93909#false} assume !(1 == ~E_4~0); {93909#false} is VALID [2022-02-21 04:24:49,370 INFO L290 TraceCheckUtils]: 149: Hoare triple {93909#false} assume !(1 == ~E_5~0); {93909#false} is VALID [2022-02-21 04:24:49,370 INFO L290 TraceCheckUtils]: 150: Hoare triple {93909#false} assume !(1 == ~E_6~0); {93909#false} is VALID [2022-02-21 04:24:49,370 INFO L290 TraceCheckUtils]: 151: Hoare triple {93909#false} assume 1 == ~E_7~0;~E_7~0 := 2; {93909#false} is VALID [2022-02-21 04:24:49,370 INFO L290 TraceCheckUtils]: 152: Hoare triple {93909#false} assume !(1 == ~E_8~0); {93909#false} is VALID [2022-02-21 04:24:49,370 INFO L290 TraceCheckUtils]: 153: Hoare triple {93909#false} assume !(1 == ~E_9~0); {93909#false} is VALID [2022-02-21 04:24:49,370 INFO L290 TraceCheckUtils]: 154: Hoare triple {93909#false} assume !(1 == ~E_10~0); {93909#false} is VALID [2022-02-21 04:24:49,371 INFO L290 TraceCheckUtils]: 155: Hoare triple {93909#false} assume !(1 == ~E_11~0); {93909#false} is VALID [2022-02-21 04:24:49,371 INFO L290 TraceCheckUtils]: 156: Hoare triple {93909#false} assume !(1 == ~E_12~0); {93909#false} is VALID [2022-02-21 04:24:49,371 INFO L290 TraceCheckUtils]: 157: Hoare triple {93909#false} assume !(1 == ~E_13~0); {93909#false} is VALID [2022-02-21 04:24:49,371 INFO L290 TraceCheckUtils]: 158: Hoare triple {93909#false} assume { :end_inline_reset_delta_events } true; {93909#false} is VALID [2022-02-21 04:24:49,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:49,372 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:49,372 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716656947] [2022-02-21 04:24:49,372 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716656947] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:49,372 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:49,372 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:49,372 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331690268] [2022-02-21 04:24:49,372 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:49,373 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:49,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:49,373 INFO L85 PathProgramCache]: Analyzing trace with hash -1415736241, now seen corresponding path program 1 times [2022-02-21 04:24:49,373 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:49,373 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137277060] [2022-02-21 04:24:49,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:49,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:49,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:49,397 INFO L290 TraceCheckUtils]: 0: Hoare triple {93911#true} assume !false; {93911#true} is VALID [2022-02-21 04:24:49,397 INFO L290 TraceCheckUtils]: 1: Hoare triple {93911#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {93911#true} is VALID [2022-02-21 04:24:49,397 INFO L290 TraceCheckUtils]: 2: Hoare triple {93911#true} assume !false; {93911#true} is VALID [2022-02-21 04:24:49,397 INFO L290 TraceCheckUtils]: 3: Hoare triple {93911#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {93911#true} is VALID [2022-02-21 04:24:49,397 INFO L290 TraceCheckUtils]: 4: Hoare triple {93911#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {93911#true} is VALID [2022-02-21 04:24:49,398 INFO L290 TraceCheckUtils]: 5: Hoare triple {93911#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {93911#true} is VALID [2022-02-21 04:24:49,398 INFO L290 TraceCheckUtils]: 6: Hoare triple {93911#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {93911#true} is VALID [2022-02-21 04:24:49,398 INFO L290 TraceCheckUtils]: 7: Hoare triple {93911#true} assume !(0 != eval_~tmp~0#1); {93911#true} is VALID [2022-02-21 04:24:49,398 INFO L290 TraceCheckUtils]: 8: Hoare triple {93911#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {93911#true} is VALID [2022-02-21 04:24:49,398 INFO L290 TraceCheckUtils]: 9: Hoare triple {93911#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {93911#true} is VALID [2022-02-21 04:24:49,398 INFO L290 TraceCheckUtils]: 10: Hoare triple {93911#true} assume 0 == ~M_E~0;~M_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,399 INFO L290 TraceCheckUtils]: 11: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,399 INFO L290 TraceCheckUtils]: 12: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,399 INFO L290 TraceCheckUtils]: 13: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,399 INFO L290 TraceCheckUtils]: 14: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,400 INFO L290 TraceCheckUtils]: 15: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,400 INFO L290 TraceCheckUtils]: 16: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,400 INFO L290 TraceCheckUtils]: 17: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,401 INFO L290 TraceCheckUtils]: 18: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,401 INFO L290 TraceCheckUtils]: 19: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,401 INFO L290 TraceCheckUtils]: 20: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,401 INFO L290 TraceCheckUtils]: 21: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,402 INFO L290 TraceCheckUtils]: 22: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,402 INFO L290 TraceCheckUtils]: 23: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,402 INFO L290 TraceCheckUtils]: 24: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,403 INFO L290 TraceCheckUtils]: 25: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,403 INFO L290 TraceCheckUtils]: 26: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,403 INFO L290 TraceCheckUtils]: 27: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,403 INFO L290 TraceCheckUtils]: 28: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,404 INFO L290 TraceCheckUtils]: 29: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,404 INFO L290 TraceCheckUtils]: 30: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,404 INFO L290 TraceCheckUtils]: 31: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,404 INFO L290 TraceCheckUtils]: 32: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,405 INFO L290 TraceCheckUtils]: 33: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,405 INFO L290 TraceCheckUtils]: 34: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,405 INFO L290 TraceCheckUtils]: 35: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,405 INFO L290 TraceCheckUtils]: 36: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,406 INFO L290 TraceCheckUtils]: 37: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,406 INFO L290 TraceCheckUtils]: 38: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,406 INFO L290 TraceCheckUtils]: 39: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,406 INFO L290 TraceCheckUtils]: 40: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,407 INFO L290 TraceCheckUtils]: 41: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,407 INFO L290 TraceCheckUtils]: 42: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,407 INFO L290 TraceCheckUtils]: 43: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,408 INFO L290 TraceCheckUtils]: 44: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,408 INFO L290 TraceCheckUtils]: 45: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,408 INFO L290 TraceCheckUtils]: 46: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,408 INFO L290 TraceCheckUtils]: 47: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,409 INFO L290 TraceCheckUtils]: 48: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,409 INFO L290 TraceCheckUtils]: 49: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,409 INFO L290 TraceCheckUtils]: 50: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,409 INFO L290 TraceCheckUtils]: 51: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,410 INFO L290 TraceCheckUtils]: 52: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,410 INFO L290 TraceCheckUtils]: 53: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,410 INFO L290 TraceCheckUtils]: 54: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,410 INFO L290 TraceCheckUtils]: 55: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,411 INFO L290 TraceCheckUtils]: 56: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,411 INFO L290 TraceCheckUtils]: 57: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,411 INFO L290 TraceCheckUtils]: 58: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,412 INFO L290 TraceCheckUtils]: 59: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,412 INFO L290 TraceCheckUtils]: 60: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,412 INFO L290 TraceCheckUtils]: 61: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,412 INFO L290 TraceCheckUtils]: 62: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,413 INFO L290 TraceCheckUtils]: 63: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,413 INFO L290 TraceCheckUtils]: 64: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,413 INFO L290 TraceCheckUtils]: 65: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,413 INFO L290 TraceCheckUtils]: 66: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,414 INFO L290 TraceCheckUtils]: 67: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,414 INFO L290 TraceCheckUtils]: 68: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,414 INFO L290 TraceCheckUtils]: 69: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,415 INFO L290 TraceCheckUtils]: 70: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,415 INFO L290 TraceCheckUtils]: 71: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,415 INFO L290 TraceCheckUtils]: 72: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,416 INFO L290 TraceCheckUtils]: 73: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,416 INFO L290 TraceCheckUtils]: 74: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,416 INFO L290 TraceCheckUtils]: 75: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,416 INFO L290 TraceCheckUtils]: 76: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,417 INFO L290 TraceCheckUtils]: 77: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,417 INFO L290 TraceCheckUtils]: 78: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,417 INFO L290 TraceCheckUtils]: 79: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,417 INFO L290 TraceCheckUtils]: 80: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,418 INFO L290 TraceCheckUtils]: 81: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,418 INFO L290 TraceCheckUtils]: 82: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,418 INFO L290 TraceCheckUtils]: 83: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,419 INFO L290 TraceCheckUtils]: 84: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,419 INFO L290 TraceCheckUtils]: 85: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,419 INFO L290 TraceCheckUtils]: 86: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,420 INFO L290 TraceCheckUtils]: 87: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,420 INFO L290 TraceCheckUtils]: 88: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,420 INFO L290 TraceCheckUtils]: 89: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,421 INFO L290 TraceCheckUtils]: 90: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,421 INFO L290 TraceCheckUtils]: 91: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,421 INFO L290 TraceCheckUtils]: 92: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,422 INFO L290 TraceCheckUtils]: 93: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,422 INFO L290 TraceCheckUtils]: 94: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,422 INFO L290 TraceCheckUtils]: 95: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,422 INFO L290 TraceCheckUtils]: 96: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,423 INFO L290 TraceCheckUtils]: 97: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,423 INFO L290 TraceCheckUtils]: 98: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,423 INFO L290 TraceCheckUtils]: 99: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,424 INFO L290 TraceCheckUtils]: 100: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,424 INFO L290 TraceCheckUtils]: 101: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,428 INFO L290 TraceCheckUtils]: 102: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,429 INFO L290 TraceCheckUtils]: 103: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,429 INFO L290 TraceCheckUtils]: 104: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,429 INFO L290 TraceCheckUtils]: 105: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,430 INFO L290 TraceCheckUtils]: 106: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,430 INFO L290 TraceCheckUtils]: 107: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,430 INFO L290 TraceCheckUtils]: 108: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,431 INFO L290 TraceCheckUtils]: 109: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,431 INFO L290 TraceCheckUtils]: 110: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,431 INFO L290 TraceCheckUtils]: 111: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,432 INFO L290 TraceCheckUtils]: 112: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,432 INFO L290 TraceCheckUtils]: 113: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,432 INFO L290 TraceCheckUtils]: 114: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,432 INFO L290 TraceCheckUtils]: 115: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,433 INFO L290 TraceCheckUtils]: 116: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,433 INFO L290 TraceCheckUtils]: 117: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,433 INFO L290 TraceCheckUtils]: 118: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,434 INFO L290 TraceCheckUtils]: 119: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,434 INFO L290 TraceCheckUtils]: 120: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,434 INFO L290 TraceCheckUtils]: 121: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {93913#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:49,435 INFO L290 TraceCheckUtils]: 122: Hoare triple {93913#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {93912#false} is VALID [2022-02-21 04:24:49,435 INFO L290 TraceCheckUtils]: 123: Hoare triple {93912#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,435 INFO L290 TraceCheckUtils]: 124: Hoare triple {93912#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,435 INFO L290 TraceCheckUtils]: 125: Hoare triple {93912#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,435 INFO L290 TraceCheckUtils]: 126: Hoare triple {93912#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,435 INFO L290 TraceCheckUtils]: 127: Hoare triple {93912#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,435 INFO L290 TraceCheckUtils]: 128: Hoare triple {93912#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,435 INFO L290 TraceCheckUtils]: 129: Hoare triple {93912#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,435 INFO L290 TraceCheckUtils]: 130: Hoare triple {93912#false} assume !(1 == ~T8_E~0); {93912#false} is VALID [2022-02-21 04:24:49,436 INFO L290 TraceCheckUtils]: 131: Hoare triple {93912#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,436 INFO L290 TraceCheckUtils]: 132: Hoare triple {93912#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,436 INFO L290 TraceCheckUtils]: 133: Hoare triple {93912#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,436 INFO L290 TraceCheckUtils]: 134: Hoare triple {93912#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,436 INFO L290 TraceCheckUtils]: 135: Hoare triple {93912#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,436 INFO L290 TraceCheckUtils]: 136: Hoare triple {93912#false} assume 1 == ~E_1~0;~E_1~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,436 INFO L290 TraceCheckUtils]: 137: Hoare triple {93912#false} assume 1 == ~E_2~0;~E_2~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,436 INFO L290 TraceCheckUtils]: 138: Hoare triple {93912#false} assume !(1 == ~E_3~0); {93912#false} is VALID [2022-02-21 04:24:49,436 INFO L290 TraceCheckUtils]: 139: Hoare triple {93912#false} assume 1 == ~E_4~0;~E_4~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,437 INFO L290 TraceCheckUtils]: 140: Hoare triple {93912#false} assume 1 == ~E_5~0;~E_5~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,437 INFO L290 TraceCheckUtils]: 141: Hoare triple {93912#false} assume 1 == ~E_6~0;~E_6~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,437 INFO L290 TraceCheckUtils]: 142: Hoare triple {93912#false} assume 1 == ~E_7~0;~E_7~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,437 INFO L290 TraceCheckUtils]: 143: Hoare triple {93912#false} assume 1 == ~E_8~0;~E_8~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,437 INFO L290 TraceCheckUtils]: 144: Hoare triple {93912#false} assume 1 == ~E_9~0;~E_9~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,437 INFO L290 TraceCheckUtils]: 145: Hoare triple {93912#false} assume 1 == ~E_10~0;~E_10~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,437 INFO L290 TraceCheckUtils]: 146: Hoare triple {93912#false} assume !(1 == ~E_11~0); {93912#false} is VALID [2022-02-21 04:24:49,437 INFO L290 TraceCheckUtils]: 147: Hoare triple {93912#false} assume 1 == ~E_12~0;~E_12~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,437 INFO L290 TraceCheckUtils]: 148: Hoare triple {93912#false} assume 1 == ~E_13~0;~E_13~0 := 2; {93912#false} is VALID [2022-02-21 04:24:49,438 INFO L290 TraceCheckUtils]: 149: Hoare triple {93912#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {93912#false} is VALID [2022-02-21 04:24:49,438 INFO L290 TraceCheckUtils]: 150: Hoare triple {93912#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {93912#false} is VALID [2022-02-21 04:24:49,438 INFO L290 TraceCheckUtils]: 151: Hoare triple {93912#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {93912#false} is VALID [2022-02-21 04:24:49,438 INFO L290 TraceCheckUtils]: 152: Hoare triple {93912#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {93912#false} is VALID [2022-02-21 04:24:49,438 INFO L290 TraceCheckUtils]: 153: Hoare triple {93912#false} assume !(0 == start_simulation_~tmp~3#1); {93912#false} is VALID [2022-02-21 04:24:49,438 INFO L290 TraceCheckUtils]: 154: Hoare triple {93912#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {93912#false} is VALID [2022-02-21 04:24:49,438 INFO L290 TraceCheckUtils]: 155: Hoare triple {93912#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {93912#false} is VALID [2022-02-21 04:24:49,438 INFO L290 TraceCheckUtils]: 156: Hoare triple {93912#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {93912#false} is VALID [2022-02-21 04:24:49,438 INFO L290 TraceCheckUtils]: 157: Hoare triple {93912#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {93912#false} is VALID [2022-02-21 04:24:49,439 INFO L290 TraceCheckUtils]: 158: Hoare triple {93912#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {93912#false} is VALID [2022-02-21 04:24:49,439 INFO L290 TraceCheckUtils]: 159: Hoare triple {93912#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {93912#false} is VALID [2022-02-21 04:24:49,439 INFO L290 TraceCheckUtils]: 160: Hoare triple {93912#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {93912#false} is VALID [2022-02-21 04:24:49,439 INFO L290 TraceCheckUtils]: 161: Hoare triple {93912#false} assume !(0 != start_simulation_~tmp___0~1#1); {93912#false} is VALID [2022-02-21 04:24:49,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:49,440 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:49,440 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137277060] [2022-02-21 04:24:49,440 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137277060] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:49,440 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:49,440 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:49,440 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842097988] [2022-02-21 04:24:49,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:49,441 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:49,441 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:49,441 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:49,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:49,442 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:50,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:50,870 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-02-21 04:24:50,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:50,870 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:50,973 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:50,974 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:51,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:51,159 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-02-21 04:24:51,160 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:51,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:51,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:51,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:51,162 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-02-21 04:24:51,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:51,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:51,180 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:51,182 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2823 transitions. Second operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,184 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2823 transitions. Second operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,185 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. Second operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:51,265 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-02-21 04:24:51,265 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:51,267 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:51,267 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:51,269 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2823 transitions. [2022-02-21 04:24:51,270 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2823 transitions. [2022-02-21 04:24:51,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:51,346 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-02-21 04:24:51,346 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:51,348 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:51,348 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:51,348 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:51,348 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:51,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-02-21 04:24:51,430 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-02-21 04:24:51,430 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-02-21 04:24:51,430 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:24:51,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:51,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:51,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:51,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:51,434 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:51,434 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:51,435 INFO L791 eck$LassoCheckResult]: Stem: 96689#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 96690#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 96509#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96225#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96226#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 97402#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97403#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96361#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96362#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96820#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96651#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96652#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96428#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96429#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 96827#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97004#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97158#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 97195#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 96441#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96442#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 97615#L1258-2 assume !(0 == ~T1_E~0); 96734#L1263-1 assume !(0 == ~T2_E~0); 96735#L1268-1 assume !(0 == ~T3_E~0); 97038#L1273-1 assume !(0 == ~T4_E~0); 97597#L1278-1 assume !(0 == ~T5_E~0); 97458#L1283-1 assume !(0 == ~T6_E~0); 97459#L1288-1 assume !(0 == ~T7_E~0); 97696#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 97683#L1298-1 assume !(0 == ~T9_E~0); 97609#L1303-1 assume !(0 == ~T10_E~0); 96254#L1308-1 assume !(0 == ~T11_E~0); 96196#L1313-1 assume !(0 == ~T12_E~0); 96197#L1318-1 assume !(0 == ~T13_E~0); 96205#L1323-1 assume !(0 == ~E_1~0); 96206#L1328-1 assume !(0 == ~E_2~0); 96371#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 97330#L1338-1 assume !(0 == ~E_4~0); 97331#L1343-1 assume !(0 == ~E_5~0); 97432#L1348-1 assume !(0 == ~E_6~0); 97718#L1353-1 assume !(0 == ~E_7~0); 97057#L1358-1 assume !(0 == ~E_8~0); 97058#L1363-1 assume !(0 == ~E_9~0); 97349#L1368-1 assume !(0 == ~E_10~0); 96033#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 96034#L1378-1 assume !(0 == ~E_12~0); 96322#L1383-1 assume !(0 == ~E_13~0); 96323#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97064#L607 assume 1 == ~m_pc~0; 97065#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 96391#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97430#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96984#L1560 assume !(0 != activate_threads_~tmp~1#1); 96985#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96216#L626 assume !(1 == ~t1_pc~0); 96217#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 96487#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96488#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96657#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 96119#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96120#L645 assume 1 == ~t2_pc~0; 96233#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 96190#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96870#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96871#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 96960#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96961#L664 assume 1 == ~t3_pc~0; 97717#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95961#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95962#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96616#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 96617#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97625#L683 assume !(1 == ~t4_pc~0); 97180#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 97132#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97133#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97167#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97291#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96914#L702 assume 1 == ~t5_pc~0; 96915#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 96837#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97286#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97585#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 97526#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96005#L721 assume !(1 == ~t6_pc~0); 95979#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95980#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96143#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96625#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 96626#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97227#L740 assume 1 == ~t7_pc~0; 96054#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95867#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95868#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 95857#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 95858#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96562#L759 assume !(1 == ~t8_pc~0); 96563#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 96591#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97284#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97285#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 97416#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97694#L778 assume 1 == ~t9_pc~0; 97583#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 96032#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95972#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95901#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 95902#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96230#L797 assume !(1 == ~t10_pc~0); 96231#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 96348#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97482#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96732#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 96733#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97022#L816 assume 1 == ~t11_pc~0; 95937#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95938#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96695#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96632#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 96633#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97157#L835 assume 1 == ~t12_pc~0; 97035#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 96101#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 96123#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 96264#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 96789#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96790#L854 assume !(1 == ~t13_pc~0); 96430#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 96431#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 96483#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 96141#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 96142#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97521#L1401 assume !(1 == ~M_E~0); 96620#L1401-2 assume !(1 == ~T1_E~0); 96621#L1406-1 assume !(1 == ~T2_E~0); 97216#L1411-1 assume !(1 == ~T3_E~0); 97217#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96883#L1421-1 assume !(1 == ~T5_E~0); 96426#L1426-1 assume !(1 == ~T6_E~0); 96427#L1431-1 assume !(1 == ~T7_E~0); 95975#L1436-1 assume !(1 == ~T8_E~0); 95976#L1441-1 assume !(1 == ~T9_E~0); 96725#L1446-1 assume !(1 == ~T10_E~0); 96726#L1451-1 assume !(1 == ~T11_E~0); 97429#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 97083#L1461-1 assume !(1 == ~T13_E~0); 96644#L1466-1 assume !(1 == ~E_1~0); 96645#L1471-1 assume !(1 == ~E_2~0); 97414#L1476-1 assume !(1 == ~E_3~0); 97415#L1481-1 assume !(1 == ~E_4~0); 97563#L1486-1 assume !(1 == ~E_5~0); 96271#L1491-1 assume !(1 == ~E_6~0); 95909#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 95910#L1501-1 assume !(1 == ~E_8~0); 96721#L1506-1 assume !(1 == ~E_9~0); 96722#L1511-1 assume !(1 == ~E_10~0); 96678#L1516-1 assume !(1 == ~E_11~0); 95855#L1521-1 assume !(1 == ~E_12~0); 95856#L1526-1 assume !(1 == ~E_13~0); 95908#L1531-1 assume { :end_inline_reset_delta_events } true; 96451#L1892-2 [2022-02-21 04:24:51,435 INFO L793 eck$LassoCheckResult]: Loop: 96451#L1892-2 assume !false; 97474#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97672#L1233 assume !false; 97655#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 96987#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96967#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 97125#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95951#L1046 assume !(0 != eval_~tmp~0#1); 95953#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 95987#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97159#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 97716#L1258-5 assume !(0 == ~T1_E~0); 96133#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 96134#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 97708#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 97714#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 97715#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 96355#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 96356#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 97471#L1298-3 assume !(0 == ~T9_E~0); 97472#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 97631#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 97470#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 96971#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 96129#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96130#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 97555#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96274#L1338-3 assume !(0 == ~E_4~0); 96275#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 97387#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 97560#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 97561#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 96927#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 96485#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 96486#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 97244#L1378-3 assume !(0 == ~E_12~0); 97245#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 97426#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97427#L607-42 assume !(1 == ~m_pc~0); 97041#L607-44 is_master_triggered_~__retres1~0#1 := 0; 96768#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96769#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96501#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96502#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97023#L626-42 assume 1 == ~t1_pc~0; 96585#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 96586#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96890#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96891#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96165#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96166#L645-42 assume !(1 == ~t2_pc~0); 97365#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 97366#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97531#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96372#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95879#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95880#L664-42 assume !(1 == ~t3_pc~0); 96406#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 96407#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97658#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97193#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97194#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97359#L683-42 assume !(1 == ~t4_pc~0); 97067#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 97068#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97200#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97620#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97621#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97465#L702-42 assume !(1 == ~t5_pc~0); 96577#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 96578#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96874#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97547#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 95895#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95896#L721-42 assume 1 == ~t6_pc~0; 96049#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 96069#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96533#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97700#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96705#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96551#L740-42 assume !(1 == ~t7_pc~0); 96288#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 96289#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96830#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96685#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 96686#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96959#L759-42 assume !(1 == ~t8_pc~0); 96809#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 96740#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96741#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96818#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 96819#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96913#L778-42 assume !(1 == ~t9_pc~0); 96753#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 96754#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97163#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97069#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 97070#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97127#L797-42 assume 1 == ~t10_pc~0; 96294#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 96295#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97296#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97605#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 97165#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97166#L816-42 assume 1 == ~t11_pc~0; 95843#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95844#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96386#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96387#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 96466#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 96467#L835-42 assume 1 == ~t12_pc~0; 96869#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 96764#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 96439#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 96440#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 97524#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 97308#L854-42 assume 1 == ~t13_pc~0; 97309#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 96383#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 95995#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 95996#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 96642#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96643#L1401-3 assume !(1 == ~M_E~0); 97421#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 96229#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 96096#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96097#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96696#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 96697#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 96272#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 96273#L1436-3 assume !(1 == ~T8_E~0); 95859#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 95860#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 97449#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 96780#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 96433#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 96434#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97711#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 96373#L1476-3 assume !(1 == ~E_3~0); 96374#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96774#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 96401#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 96402#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 96814#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 96815#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 97241#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 97231#L1516-3 assume !(1 == ~E_11~0); 97232#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 96931#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 96932#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 97326#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96208#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 97101#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 96742#L1911 assume !(0 == start_simulation_~tmp~3#1); 96743#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 97265#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96333#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 97203#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 96037#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 96038#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 96267#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 96268#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 96451#L1892-2 [2022-02-21 04:24:51,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:51,436 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2022-02-21 04:24:51,436 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:51,436 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211679941] [2022-02-21 04:24:51,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:51,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:51,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:51,460 INFO L290 TraceCheckUtils]: 0: Hoare triple {101573#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,461 INFO L290 TraceCheckUtils]: 1: Hoare triple {101575#(<= 2 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,461 INFO L290 TraceCheckUtils]: 2: Hoare triple {101575#(<= 2 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,461 INFO L290 TraceCheckUtils]: 3: Hoare triple {101575#(<= 2 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,462 INFO L290 TraceCheckUtils]: 4: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,462 INFO L290 TraceCheckUtils]: 5: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,462 INFO L290 TraceCheckUtils]: 6: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,463 INFO L290 TraceCheckUtils]: 7: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,463 INFO L290 TraceCheckUtils]: 8: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,463 INFO L290 TraceCheckUtils]: 9: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,463 INFO L290 TraceCheckUtils]: 10: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,464 INFO L290 TraceCheckUtils]: 11: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,464 INFO L290 TraceCheckUtils]: 12: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,464 INFO L290 TraceCheckUtils]: 13: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,465 INFO L290 TraceCheckUtils]: 14: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,465 INFO L290 TraceCheckUtils]: 15: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,465 INFO L290 TraceCheckUtils]: 16: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,465 INFO L290 TraceCheckUtils]: 17: Hoare triple {101575#(<= 2 ~M_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,466 INFO L290 TraceCheckUtils]: 18: Hoare triple {101575#(<= 2 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {101575#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:51,466 INFO L290 TraceCheckUtils]: 19: Hoare triple {101575#(<= 2 ~M_E~0)} assume 0 == ~M_E~0;~M_E~0 := 1; {101574#false} is VALID [2022-02-21 04:24:51,466 INFO L290 TraceCheckUtils]: 20: Hoare triple {101574#false} assume !(0 == ~T1_E~0); {101574#false} is VALID [2022-02-21 04:24:51,466 INFO L290 TraceCheckUtils]: 21: Hoare triple {101574#false} assume !(0 == ~T2_E~0); {101574#false} is VALID [2022-02-21 04:24:51,466 INFO L290 TraceCheckUtils]: 22: Hoare triple {101574#false} assume !(0 == ~T3_E~0); {101574#false} is VALID [2022-02-21 04:24:51,466 INFO L290 TraceCheckUtils]: 23: Hoare triple {101574#false} assume !(0 == ~T4_E~0); {101574#false} is VALID [2022-02-21 04:24:51,466 INFO L290 TraceCheckUtils]: 24: Hoare triple {101574#false} assume !(0 == ~T5_E~0); {101574#false} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 25: Hoare triple {101574#false} assume !(0 == ~T6_E~0); {101574#false} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 26: Hoare triple {101574#false} assume !(0 == ~T7_E~0); {101574#false} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 27: Hoare triple {101574#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {101574#false} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 28: Hoare triple {101574#false} assume !(0 == ~T9_E~0); {101574#false} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 29: Hoare triple {101574#false} assume !(0 == ~T10_E~0); {101574#false} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 30: Hoare triple {101574#false} assume !(0 == ~T11_E~0); {101574#false} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 31: Hoare triple {101574#false} assume !(0 == ~T12_E~0); {101574#false} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 32: Hoare triple {101574#false} assume !(0 == ~T13_E~0); {101574#false} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 33: Hoare triple {101574#false} assume !(0 == ~E_1~0); {101574#false} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 34: Hoare triple {101574#false} assume !(0 == ~E_2~0); {101574#false} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 35: Hoare triple {101574#false} assume 0 == ~E_3~0;~E_3~0 := 1; {101574#false} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 36: Hoare triple {101574#false} assume !(0 == ~E_4~0); {101574#false} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 37: Hoare triple {101574#false} assume !(0 == ~E_5~0); {101574#false} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 38: Hoare triple {101574#false} assume !(0 == ~E_6~0); {101574#false} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 39: Hoare triple {101574#false} assume !(0 == ~E_7~0); {101574#false} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 40: Hoare triple {101574#false} assume !(0 == ~E_8~0); {101574#false} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 41: Hoare triple {101574#false} assume !(0 == ~E_9~0); {101574#false} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 42: Hoare triple {101574#false} assume !(0 == ~E_10~0); {101574#false} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 43: Hoare triple {101574#false} assume 0 == ~E_11~0;~E_11~0 := 1; {101574#false} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 44: Hoare triple {101574#false} assume !(0 == ~E_12~0); {101574#false} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 45: Hoare triple {101574#false} assume !(0 == ~E_13~0); {101574#false} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 46: Hoare triple {101574#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {101574#false} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 47: Hoare triple {101574#false} assume 1 == ~m_pc~0; {101574#false} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 48: Hoare triple {101574#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {101574#false} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 49: Hoare triple {101574#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {101574#false} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 50: Hoare triple {101574#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {101574#false} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 51: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp~1#1); {101574#false} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 52: Hoare triple {101574#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {101574#false} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 53: Hoare triple {101574#false} assume !(1 == ~t1_pc~0); {101574#false} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 54: Hoare triple {101574#false} is_transmit1_triggered_~__retres1~1#1 := 0; {101574#false} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 55: Hoare triple {101574#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {101574#false} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 56: Hoare triple {101574#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {101574#false} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 57: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___0~0#1); {101574#false} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 58: Hoare triple {101574#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {101574#false} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 59: Hoare triple {101574#false} assume 1 == ~t2_pc~0; {101574#false} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 60: Hoare triple {101574#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {101574#false} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 61: Hoare triple {101574#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {101574#false} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 62: Hoare triple {101574#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {101574#false} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 63: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___1~0#1); {101574#false} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 64: Hoare triple {101574#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {101574#false} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 65: Hoare triple {101574#false} assume 1 == ~t3_pc~0; {101574#false} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 66: Hoare triple {101574#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {101574#false} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 67: Hoare triple {101574#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {101574#false} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 68: Hoare triple {101574#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {101574#false} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 69: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___2~0#1); {101574#false} is VALID [2022-02-21 04:24:51,472 INFO L290 TraceCheckUtils]: 70: Hoare triple {101574#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {101574#false} is VALID [2022-02-21 04:24:51,472 INFO L290 TraceCheckUtils]: 71: Hoare triple {101574#false} assume !(1 == ~t4_pc~0); {101574#false} is VALID [2022-02-21 04:24:51,472 INFO L290 TraceCheckUtils]: 72: Hoare triple {101574#false} is_transmit4_triggered_~__retres1~4#1 := 0; {101574#false} is VALID [2022-02-21 04:24:51,472 INFO L290 TraceCheckUtils]: 73: Hoare triple {101574#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {101574#false} is VALID [2022-02-21 04:24:51,472 INFO L290 TraceCheckUtils]: 74: Hoare triple {101574#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {101574#false} is VALID [2022-02-21 04:24:51,472 INFO L290 TraceCheckUtils]: 75: Hoare triple {101574#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {101574#false} is VALID [2022-02-21 04:24:51,472 INFO L290 TraceCheckUtils]: 76: Hoare triple {101574#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {101574#false} is VALID [2022-02-21 04:24:51,472 INFO L290 TraceCheckUtils]: 77: Hoare triple {101574#false} assume 1 == ~t5_pc~0; {101574#false} is VALID [2022-02-21 04:24:51,472 INFO L290 TraceCheckUtils]: 78: Hoare triple {101574#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {101574#false} is VALID [2022-02-21 04:24:51,473 INFO L290 TraceCheckUtils]: 79: Hoare triple {101574#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {101574#false} is VALID [2022-02-21 04:24:51,473 INFO L290 TraceCheckUtils]: 80: Hoare triple {101574#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {101574#false} is VALID [2022-02-21 04:24:51,473 INFO L290 TraceCheckUtils]: 81: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___4~0#1); {101574#false} is VALID [2022-02-21 04:24:51,473 INFO L290 TraceCheckUtils]: 82: Hoare triple {101574#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {101574#false} is VALID [2022-02-21 04:24:51,473 INFO L290 TraceCheckUtils]: 83: Hoare triple {101574#false} assume !(1 == ~t6_pc~0); {101574#false} is VALID [2022-02-21 04:24:51,473 INFO L290 TraceCheckUtils]: 84: Hoare triple {101574#false} is_transmit6_triggered_~__retres1~6#1 := 0; {101574#false} is VALID [2022-02-21 04:24:51,473 INFO L290 TraceCheckUtils]: 85: Hoare triple {101574#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {101574#false} is VALID [2022-02-21 04:24:51,473 INFO L290 TraceCheckUtils]: 86: Hoare triple {101574#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {101574#false} is VALID [2022-02-21 04:24:51,473 INFO L290 TraceCheckUtils]: 87: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___5~0#1); {101574#false} is VALID [2022-02-21 04:24:51,474 INFO L290 TraceCheckUtils]: 88: Hoare triple {101574#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {101574#false} is VALID [2022-02-21 04:24:51,474 INFO L290 TraceCheckUtils]: 89: Hoare triple {101574#false} assume 1 == ~t7_pc~0; {101574#false} is VALID [2022-02-21 04:24:51,474 INFO L290 TraceCheckUtils]: 90: Hoare triple {101574#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {101574#false} is VALID [2022-02-21 04:24:51,474 INFO L290 TraceCheckUtils]: 91: Hoare triple {101574#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {101574#false} is VALID [2022-02-21 04:24:51,474 INFO L290 TraceCheckUtils]: 92: Hoare triple {101574#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {101574#false} is VALID [2022-02-21 04:24:51,474 INFO L290 TraceCheckUtils]: 93: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___6~0#1); {101574#false} is VALID [2022-02-21 04:24:51,474 INFO L290 TraceCheckUtils]: 94: Hoare triple {101574#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {101574#false} is VALID [2022-02-21 04:24:51,474 INFO L290 TraceCheckUtils]: 95: Hoare triple {101574#false} assume !(1 == ~t8_pc~0); {101574#false} is VALID [2022-02-21 04:24:51,474 INFO L290 TraceCheckUtils]: 96: Hoare triple {101574#false} is_transmit8_triggered_~__retres1~8#1 := 0; {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 97: Hoare triple {101574#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 98: Hoare triple {101574#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 99: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___7~0#1); {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 100: Hoare triple {101574#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 101: Hoare triple {101574#false} assume 1 == ~t9_pc~0; {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 102: Hoare triple {101574#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 103: Hoare triple {101574#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 104: Hoare triple {101574#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 105: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___8~0#1); {101574#false} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 106: Hoare triple {101574#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {101574#false} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 107: Hoare triple {101574#false} assume !(1 == ~t10_pc~0); {101574#false} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 108: Hoare triple {101574#false} is_transmit10_triggered_~__retres1~10#1 := 0; {101574#false} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 109: Hoare triple {101574#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {101574#false} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 110: Hoare triple {101574#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {101574#false} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 111: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___9~0#1); {101574#false} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 112: Hoare triple {101574#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {101574#false} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 113: Hoare triple {101574#false} assume 1 == ~t11_pc~0; {101574#false} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 114: Hoare triple {101574#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {101574#false} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 115: Hoare triple {101574#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {101574#false} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 116: Hoare triple {101574#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {101574#false} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 117: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___10~0#1); {101574#false} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 118: Hoare triple {101574#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {101574#false} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 119: Hoare triple {101574#false} assume 1 == ~t12_pc~0; {101574#false} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 120: Hoare triple {101574#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {101574#false} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 121: Hoare triple {101574#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {101574#false} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 122: Hoare triple {101574#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {101574#false} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 123: Hoare triple {101574#false} assume !(0 != activate_threads_~tmp___11~0#1); {101574#false} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 124: Hoare triple {101574#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {101574#false} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 125: Hoare triple {101574#false} assume !(1 == ~t13_pc~0); {101574#false} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 126: Hoare triple {101574#false} is_transmit13_triggered_~__retres1~13#1 := 0; {101574#false} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 127: Hoare triple {101574#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {101574#false} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 128: Hoare triple {101574#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {101574#false} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 129: Hoare triple {101574#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {101574#false} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 130: Hoare triple {101574#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {101574#false} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 131: Hoare triple {101574#false} assume !(1 == ~M_E~0); {101574#false} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 132: Hoare triple {101574#false} assume !(1 == ~T1_E~0); {101574#false} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 133: Hoare triple {101574#false} assume !(1 == ~T2_E~0); {101574#false} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 134: Hoare triple {101574#false} assume !(1 == ~T3_E~0); {101574#false} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 135: Hoare triple {101574#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {101574#false} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 136: Hoare triple {101574#false} assume !(1 == ~T5_E~0); {101574#false} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 137: Hoare triple {101574#false} assume !(1 == ~T6_E~0); {101574#false} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 138: Hoare triple {101574#false} assume !(1 == ~T7_E~0); {101574#false} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 139: Hoare triple {101574#false} assume !(1 == ~T8_E~0); {101574#false} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 140: Hoare triple {101574#false} assume !(1 == ~T9_E~0); {101574#false} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 141: Hoare triple {101574#false} assume !(1 == ~T10_E~0); {101574#false} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 142: Hoare triple {101574#false} assume !(1 == ~T11_E~0); {101574#false} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 143: Hoare triple {101574#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {101574#false} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 144: Hoare triple {101574#false} assume !(1 == ~T13_E~0); {101574#false} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 145: Hoare triple {101574#false} assume !(1 == ~E_1~0); {101574#false} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 146: Hoare triple {101574#false} assume !(1 == ~E_2~0); {101574#false} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 147: Hoare triple {101574#false} assume !(1 == ~E_3~0); {101574#false} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 148: Hoare triple {101574#false} assume !(1 == ~E_4~0); {101574#false} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 149: Hoare triple {101574#false} assume !(1 == ~E_5~0); {101574#false} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 150: Hoare triple {101574#false} assume !(1 == ~E_6~0); {101574#false} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 151: Hoare triple {101574#false} assume 1 == ~E_7~0;~E_7~0 := 2; {101574#false} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 152: Hoare triple {101574#false} assume !(1 == ~E_8~0); {101574#false} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 153: Hoare triple {101574#false} assume !(1 == ~E_9~0); {101574#false} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 154: Hoare triple {101574#false} assume !(1 == ~E_10~0); {101574#false} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 155: Hoare triple {101574#false} assume !(1 == ~E_11~0); {101574#false} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 156: Hoare triple {101574#false} assume !(1 == ~E_12~0); {101574#false} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 157: Hoare triple {101574#false} assume !(1 == ~E_13~0); {101574#false} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 158: Hoare triple {101574#false} assume { :end_inline_reset_delta_events } true; {101574#false} is VALID [2022-02-21 04:24:51,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:51,482 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:51,482 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211679941] [2022-02-21 04:24:51,482 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211679941] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:51,482 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:51,482 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:51,482 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404121877] [2022-02-21 04:24:51,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:51,483 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:51,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:51,483 INFO L85 PathProgramCache]: Analyzing trace with hash -1231730995, now seen corresponding path program 1 times [2022-02-21 04:24:51,483 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:51,483 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296982581] [2022-02-21 04:24:51,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:51,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:51,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:51,507 INFO L290 TraceCheckUtils]: 0: Hoare triple {101576#true} assume !false; {101576#true} is VALID [2022-02-21 04:24:51,507 INFO L290 TraceCheckUtils]: 1: Hoare triple {101576#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {101576#true} is VALID [2022-02-21 04:24:51,508 INFO L290 TraceCheckUtils]: 2: Hoare triple {101576#true} assume !false; {101576#true} is VALID [2022-02-21 04:24:51,508 INFO L290 TraceCheckUtils]: 3: Hoare triple {101576#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {101576#true} is VALID [2022-02-21 04:24:51,508 INFO L290 TraceCheckUtils]: 4: Hoare triple {101576#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {101576#true} is VALID [2022-02-21 04:24:51,508 INFO L290 TraceCheckUtils]: 5: Hoare triple {101576#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {101576#true} is VALID [2022-02-21 04:24:51,508 INFO L290 TraceCheckUtils]: 6: Hoare triple {101576#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {101576#true} is VALID [2022-02-21 04:24:51,508 INFO L290 TraceCheckUtils]: 7: Hoare triple {101576#true} assume !(0 != eval_~tmp~0#1); {101576#true} is VALID [2022-02-21 04:24:51,508 INFO L290 TraceCheckUtils]: 8: Hoare triple {101576#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {101576#true} is VALID [2022-02-21 04:24:51,508 INFO L290 TraceCheckUtils]: 9: Hoare triple {101576#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {101576#true} is VALID [2022-02-21 04:24:51,509 INFO L290 TraceCheckUtils]: 10: Hoare triple {101576#true} assume 0 == ~M_E~0;~M_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,509 INFO L290 TraceCheckUtils]: 11: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,509 INFO L290 TraceCheckUtils]: 12: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,509 INFO L290 TraceCheckUtils]: 13: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,510 INFO L290 TraceCheckUtils]: 14: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,510 INFO L290 TraceCheckUtils]: 15: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,510 INFO L290 TraceCheckUtils]: 16: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,511 INFO L290 TraceCheckUtils]: 17: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,511 INFO L290 TraceCheckUtils]: 18: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,511 INFO L290 TraceCheckUtils]: 19: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T9_E~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,511 INFO L290 TraceCheckUtils]: 20: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,512 INFO L290 TraceCheckUtils]: 21: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,512 INFO L290 TraceCheckUtils]: 22: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,512 INFO L290 TraceCheckUtils]: 23: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,512 INFO L290 TraceCheckUtils]: 24: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,513 INFO L290 TraceCheckUtils]: 25: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,513 INFO L290 TraceCheckUtils]: 26: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,513 INFO L290 TraceCheckUtils]: 27: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_4~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,514 INFO L290 TraceCheckUtils]: 28: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,514 INFO L290 TraceCheckUtils]: 29: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,514 INFO L290 TraceCheckUtils]: 30: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,514 INFO L290 TraceCheckUtils]: 31: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,515 INFO L290 TraceCheckUtils]: 32: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,515 INFO L290 TraceCheckUtils]: 33: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,515 INFO L290 TraceCheckUtils]: 34: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,515 INFO L290 TraceCheckUtils]: 35: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_12~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,516 INFO L290 TraceCheckUtils]: 36: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,516 INFO L290 TraceCheckUtils]: 37: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,516 INFO L290 TraceCheckUtils]: 38: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,517 INFO L290 TraceCheckUtils]: 39: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,517 INFO L290 TraceCheckUtils]: 40: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,517 INFO L290 TraceCheckUtils]: 41: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,517 INFO L290 TraceCheckUtils]: 42: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,518 INFO L290 TraceCheckUtils]: 43: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,518 INFO L290 TraceCheckUtils]: 44: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,518 INFO L290 TraceCheckUtils]: 45: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,519 INFO L290 TraceCheckUtils]: 46: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,519 INFO L290 TraceCheckUtils]: 47: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,519 INFO L290 TraceCheckUtils]: 48: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,519 INFO L290 TraceCheckUtils]: 49: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,520 INFO L290 TraceCheckUtils]: 50: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,520 INFO L290 TraceCheckUtils]: 51: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,520 INFO L290 TraceCheckUtils]: 52: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,520 INFO L290 TraceCheckUtils]: 53: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,521 INFO L290 TraceCheckUtils]: 54: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,521 INFO L290 TraceCheckUtils]: 55: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,521 INFO L290 TraceCheckUtils]: 56: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,522 INFO L290 TraceCheckUtils]: 57: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,522 INFO L290 TraceCheckUtils]: 58: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,522 INFO L290 TraceCheckUtils]: 59: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,522 INFO L290 TraceCheckUtils]: 60: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,523 INFO L290 TraceCheckUtils]: 61: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,523 INFO L290 TraceCheckUtils]: 62: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,523 INFO L290 TraceCheckUtils]: 63: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,523 INFO L290 TraceCheckUtils]: 64: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,524 INFO L290 TraceCheckUtils]: 65: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,524 INFO L290 TraceCheckUtils]: 66: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,524 INFO L290 TraceCheckUtils]: 67: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,525 INFO L290 TraceCheckUtils]: 68: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,525 INFO L290 TraceCheckUtils]: 69: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,525 INFO L290 TraceCheckUtils]: 70: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,525 INFO L290 TraceCheckUtils]: 71: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,526 INFO L290 TraceCheckUtils]: 72: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,526 INFO L290 TraceCheckUtils]: 73: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,526 INFO L290 TraceCheckUtils]: 74: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,526 INFO L290 TraceCheckUtils]: 75: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,527 INFO L290 TraceCheckUtils]: 76: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,527 INFO L290 TraceCheckUtils]: 77: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,527 INFO L290 TraceCheckUtils]: 78: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,528 INFO L290 TraceCheckUtils]: 79: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,528 INFO L290 TraceCheckUtils]: 80: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,528 INFO L290 TraceCheckUtils]: 81: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,529 INFO L290 TraceCheckUtils]: 82: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,529 INFO L290 TraceCheckUtils]: 83: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,529 INFO L290 TraceCheckUtils]: 84: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,530 INFO L290 TraceCheckUtils]: 85: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,530 INFO L290 TraceCheckUtils]: 86: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,530 INFO L290 TraceCheckUtils]: 87: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,531 INFO L290 TraceCheckUtils]: 88: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,531 INFO L290 TraceCheckUtils]: 89: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,531 INFO L290 TraceCheckUtils]: 90: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,532 INFO L290 TraceCheckUtils]: 91: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,532 INFO L290 TraceCheckUtils]: 92: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,532 INFO L290 TraceCheckUtils]: 93: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,533 INFO L290 TraceCheckUtils]: 94: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,533 INFO L290 TraceCheckUtils]: 95: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,533 INFO L290 TraceCheckUtils]: 96: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,534 INFO L290 TraceCheckUtils]: 97: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,534 INFO L290 TraceCheckUtils]: 98: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,534 INFO L290 TraceCheckUtils]: 99: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,534 INFO L290 TraceCheckUtils]: 100: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,535 INFO L290 TraceCheckUtils]: 101: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,535 INFO L290 TraceCheckUtils]: 102: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,535 INFO L290 TraceCheckUtils]: 103: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,536 INFO L290 TraceCheckUtils]: 104: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,536 INFO L290 TraceCheckUtils]: 105: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,536 INFO L290 TraceCheckUtils]: 106: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,537 INFO L290 TraceCheckUtils]: 107: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,537 INFO L290 TraceCheckUtils]: 108: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,537 INFO L290 TraceCheckUtils]: 109: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,538 INFO L290 TraceCheckUtils]: 110: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,538 INFO L290 TraceCheckUtils]: 111: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,538 INFO L290 TraceCheckUtils]: 112: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,539 INFO L290 TraceCheckUtils]: 113: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,539 INFO L290 TraceCheckUtils]: 114: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,539 INFO L290 TraceCheckUtils]: 115: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,540 INFO L290 TraceCheckUtils]: 116: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,540 INFO L290 TraceCheckUtils]: 117: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,540 INFO L290 TraceCheckUtils]: 118: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,541 INFO L290 TraceCheckUtils]: 119: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,541 INFO L290 TraceCheckUtils]: 120: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,541 INFO L290 TraceCheckUtils]: 121: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {101578#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:51,542 INFO L290 TraceCheckUtils]: 122: Hoare triple {101578#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {101577#false} is VALID [2022-02-21 04:24:51,542 INFO L290 TraceCheckUtils]: 123: Hoare triple {101577#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,542 INFO L290 TraceCheckUtils]: 124: Hoare triple {101577#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,542 INFO L290 TraceCheckUtils]: 125: Hoare triple {101577#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,542 INFO L290 TraceCheckUtils]: 126: Hoare triple {101577#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,542 INFO L290 TraceCheckUtils]: 127: Hoare triple {101577#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,542 INFO L290 TraceCheckUtils]: 128: Hoare triple {101577#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,542 INFO L290 TraceCheckUtils]: 129: Hoare triple {101577#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,542 INFO L290 TraceCheckUtils]: 130: Hoare triple {101577#false} assume !(1 == ~T8_E~0); {101577#false} is VALID [2022-02-21 04:24:51,543 INFO L290 TraceCheckUtils]: 131: Hoare triple {101577#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,543 INFO L290 TraceCheckUtils]: 132: Hoare triple {101577#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,543 INFO L290 TraceCheckUtils]: 133: Hoare triple {101577#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,543 INFO L290 TraceCheckUtils]: 134: Hoare triple {101577#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,543 INFO L290 TraceCheckUtils]: 135: Hoare triple {101577#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,543 INFO L290 TraceCheckUtils]: 136: Hoare triple {101577#false} assume 1 == ~E_1~0;~E_1~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,543 INFO L290 TraceCheckUtils]: 137: Hoare triple {101577#false} assume 1 == ~E_2~0;~E_2~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,543 INFO L290 TraceCheckUtils]: 138: Hoare triple {101577#false} assume !(1 == ~E_3~0); {101577#false} is VALID [2022-02-21 04:24:51,544 INFO L290 TraceCheckUtils]: 139: Hoare triple {101577#false} assume 1 == ~E_4~0;~E_4~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,544 INFO L290 TraceCheckUtils]: 140: Hoare triple {101577#false} assume 1 == ~E_5~0;~E_5~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,544 INFO L290 TraceCheckUtils]: 141: Hoare triple {101577#false} assume 1 == ~E_6~0;~E_6~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,544 INFO L290 TraceCheckUtils]: 142: Hoare triple {101577#false} assume 1 == ~E_7~0;~E_7~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,544 INFO L290 TraceCheckUtils]: 143: Hoare triple {101577#false} assume 1 == ~E_8~0;~E_8~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,544 INFO L290 TraceCheckUtils]: 144: Hoare triple {101577#false} assume 1 == ~E_9~0;~E_9~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,544 INFO L290 TraceCheckUtils]: 145: Hoare triple {101577#false} assume 1 == ~E_10~0;~E_10~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,544 INFO L290 TraceCheckUtils]: 146: Hoare triple {101577#false} assume !(1 == ~E_11~0); {101577#false} is VALID [2022-02-21 04:24:51,544 INFO L290 TraceCheckUtils]: 147: Hoare triple {101577#false} assume 1 == ~E_12~0;~E_12~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,545 INFO L290 TraceCheckUtils]: 148: Hoare triple {101577#false} assume 1 == ~E_13~0;~E_13~0 := 2; {101577#false} is VALID [2022-02-21 04:24:51,545 INFO L290 TraceCheckUtils]: 149: Hoare triple {101577#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {101577#false} is VALID [2022-02-21 04:24:51,545 INFO L290 TraceCheckUtils]: 150: Hoare triple {101577#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {101577#false} is VALID [2022-02-21 04:24:51,545 INFO L290 TraceCheckUtils]: 151: Hoare triple {101577#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {101577#false} is VALID [2022-02-21 04:24:51,545 INFO L290 TraceCheckUtils]: 152: Hoare triple {101577#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {101577#false} is VALID [2022-02-21 04:24:51,545 INFO L290 TraceCheckUtils]: 153: Hoare triple {101577#false} assume !(0 == start_simulation_~tmp~3#1); {101577#false} is VALID [2022-02-21 04:24:51,545 INFO L290 TraceCheckUtils]: 154: Hoare triple {101577#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {101577#false} is VALID [2022-02-21 04:24:51,545 INFO L290 TraceCheckUtils]: 155: Hoare triple {101577#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {101577#false} is VALID [2022-02-21 04:24:51,545 INFO L290 TraceCheckUtils]: 156: Hoare triple {101577#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {101577#false} is VALID [2022-02-21 04:24:51,546 INFO L290 TraceCheckUtils]: 157: Hoare triple {101577#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {101577#false} is VALID [2022-02-21 04:24:51,546 INFO L290 TraceCheckUtils]: 158: Hoare triple {101577#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {101577#false} is VALID [2022-02-21 04:24:51,546 INFO L290 TraceCheckUtils]: 159: Hoare triple {101577#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {101577#false} is VALID [2022-02-21 04:24:51,546 INFO L290 TraceCheckUtils]: 160: Hoare triple {101577#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {101577#false} is VALID [2022-02-21 04:24:51,546 INFO L290 TraceCheckUtils]: 161: Hoare triple {101577#false} assume !(0 != start_simulation_~tmp___0~1#1); {101577#false} is VALID [2022-02-21 04:24:51,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:51,547 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:51,547 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296982581] [2022-02-21 04:24:51,547 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296982581] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:51,547 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:51,547 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:51,547 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204443768] [2022-02-21 04:24:51,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:51,548 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:51,548 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:51,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:51,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:51,549 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:54,081 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-02-21 04:24:54,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:54,082 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,180 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:54,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:54,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-02-21 04:24:54,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-02-21 04:24:54,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2022-02-21 04:24:54,891 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2022-02-21 04:24:54,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:54,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:54,895 INFO L681 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-02-21 04:24:54,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:54,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2022-02-21 04:24:54,936 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:54,939 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3555 states and 5213 transitions. Second operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,941 INFO L74 IsIncluded]: Start isIncluded. First operand 3555 states and 5213 transitions. Second operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,944 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. Second operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:55,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:55,252 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-02-21 04:24:55,252 INFO L276 IsEmpty]: Start isEmpty. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:55,256 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:55,256 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:55,260 INFO L74 IsIncluded]: Start isIncluded. First operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3555 states and 5213 transitions. [2022-02-21 04:24:55,262 INFO L87 Difference]: Start difference. First operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3555 states and 5213 transitions. [2022-02-21 04:24:55,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:55,547 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-02-21 04:24:55,547 INFO L276 IsEmpty]: Start isEmpty. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:55,551 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:55,551 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:55,551 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:55,551 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:55,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:55,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-02-21 04:24:55,855 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-02-21 04:24:55,855 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-02-21 04:24:55,855 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:24:55,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:55,861 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-02-21 04:24:55,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:55,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:55,862 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:55,863 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:55,863 INFO L791 eck$LassoCheckResult]: Stem: 105998#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 105999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 105817#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105531#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105532#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 106730#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106731#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105668#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105669#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 106127#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105960#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 105961#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 105736#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 105737#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 106138#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 106321#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 106473#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 106512#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 105747#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105748#L1258 assume !(0 == ~M_E~0); 106963#L1258-2 assume !(0 == ~T1_E~0); 106044#L1263-1 assume !(0 == ~T2_E~0); 106045#L1268-1 assume !(0 == ~T3_E~0); 106355#L1273-1 assume !(0 == ~T4_E~0); 106942#L1278-1 assume !(0 == ~T5_E~0); 106790#L1283-1 assume !(0 == ~T6_E~0); 106791#L1288-1 assume !(0 == ~T7_E~0); 107057#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 107045#L1298-1 assume !(0 == ~T9_E~0); 106955#L1303-1 assume !(0 == ~T10_E~0); 105560#L1308-1 assume !(0 == ~T11_E~0); 105502#L1313-1 assume !(0 == ~T12_E~0); 105503#L1318-1 assume !(0 == ~T13_E~0); 105509#L1323-1 assume !(0 == ~E_1~0); 105510#L1328-1 assume !(0 == ~E_2~0); 105679#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 106653#L1338-1 assume !(0 == ~E_4~0); 106654#L1343-1 assume !(0 == ~E_5~0); 106762#L1348-1 assume !(0 == ~E_6~0); 107085#L1353-1 assume !(0 == ~E_7~0); 106374#L1358-1 assume !(0 == ~E_8~0); 106375#L1363-1 assume !(0 == ~E_9~0); 106672#L1368-1 assume !(0 == ~E_10~0); 105339#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 105340#L1378-1 assume !(0 == ~E_12~0); 105627#L1383-1 assume !(0 == ~E_13~0); 105628#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106380#L607 assume !(1 == ~m_pc~0); 105698#L607-2 is_master_triggered_~__retres1~0#1 := 0; 105699#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106760#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 106299#L1560 assume !(0 != activate_threads_~tmp~1#1); 106300#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105522#L626 assume !(1 == ~t1_pc~0); 105523#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105793#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105794#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 105964#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 105422#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105423#L645 assume 1 == ~t2_pc~0; 105539#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 105496#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106179#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 106180#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 106275#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106276#L664 assume 1 == ~t3_pc~0; 107083#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 105263#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105264#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 105925#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 105926#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106973#L683 assume !(1 == ~t4_pc~0); 106497#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 106447#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106448#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 106483#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106612#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106222#L702 assume 1 == ~t5_pc~0; 106223#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 106148#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106607#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106927#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 106862#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105311#L721 assume !(1 == ~t6_pc~0); 105285#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 105286#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105449#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 105934#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 105935#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 106545#L740 assume 1 == ~t7_pc~0; 105360#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 105173#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 105174#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 105163#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 105164#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 105869#L759 assume !(1 == ~t8_pc~0); 105870#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 105900#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 106605#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 106606#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 106745#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 107056#L778 assume 1 == ~t9_pc~0; 106924#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 105338#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 105278#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 105207#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 105208#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 105535#L797 assume !(1 == ~t10_pc~0); 105536#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 105655#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 106817#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 106042#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 106043#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 106339#L816 assume 1 == ~t11_pc~0; 105243#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 105244#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 106002#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 105941#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 105942#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 106472#L835 assume 1 == ~t12_pc~0; 106352#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 105407#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 105429#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 105570#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 106100#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 106101#L854 assume !(1 == ~t13_pc~0); 105738#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 105739#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 105789#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 105447#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 105448#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106857#L1401 assume !(1 == ~M_E~0); 105929#L1401-2 assume !(1 == ~T1_E~0); 105930#L1406-1 assume !(1 == ~T2_E~0); 106534#L1411-1 assume !(1 == ~T3_E~0); 106535#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106195#L1421-1 assume !(1 == ~T5_E~0); 105734#L1426-1 assume !(1 == ~T6_E~0); 105735#L1431-1 assume !(1 == ~T7_E~0); 105281#L1436-1 assume !(1 == ~T8_E~0); 105282#L1441-1 assume !(1 == ~T9_E~0); 106033#L1446-1 assume !(1 == ~T10_E~0); 106034#L1451-1 assume !(1 == ~T11_E~0); 106759#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 106399#L1461-1 assume !(1 == ~T13_E~0); 105953#L1466-1 assume !(1 == ~E_1~0); 105954#L1471-1 assume !(1 == ~E_2~0); 106743#L1476-1 assume !(1 == ~E_3~0); 106744#L1481-1 assume !(1 == ~E_4~0); 106905#L1486-1 assume !(1 == ~E_5~0); 105575#L1491-1 assume !(1 == ~E_6~0); 105215#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 105216#L1501-1 assume !(1 == ~E_8~0); 106031#L1506-1 assume !(1 == ~E_9~0); 106032#L1511-1 assume !(1 == ~E_10~0); 105987#L1516-1 assume !(1 == ~E_11~0); 105159#L1521-1 assume !(1 == ~E_12~0); 105160#L1526-1 assume !(1 == ~E_13~0); 105214#L1531-1 assume { :end_inline_reset_delta_events } true; 105759#L1892-2 [2022-02-21 04:24:55,863 INFO L793 eck$LassoCheckResult]: Loop: 105759#L1892-2 assume !false; 107176#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 107174#L1233 assume !false; 107008#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 106302#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 106282#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 106440#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 105257#L1046 assume !(0 != eval_~tmp~0#1); 105259#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 108383#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 108382#L1258-3 assume !(0 == ~M_E~0); 107123#L1258-5 assume !(0 == ~T1_E~0); 105435#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 105436#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 107071#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 107078#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 107079#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 105660#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 105661#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 106803#L1298-3 assume !(0 == ~T9_E~0); 106804#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 106980#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 106802#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 106286#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 105437#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 105438#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 106896#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 105580#L1338-3 assume !(0 == ~E_4~0); 105581#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106713#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 106902#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 106903#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 106240#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 105795#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 105796#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 106565#L1378-3 assume !(0 == ~E_12~0); 106566#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 106756#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106757#L607-42 assume !(1 == ~m_pc~0); 106358#L607-44 is_master_triggered_~__retres1~0#1 := 0; 108202#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108201#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 108200#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 108199#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108198#L626-42 assume !(1 == ~t1_pc~0); 108197#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 108195#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108194#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 108193#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 108192#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108191#L645-42 assume !(1 == ~t2_pc~0); 108189#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 108188#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108187#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 108186#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 108185#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108184#L664-42 assume !(1 == ~t3_pc~0); 108183#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 108181#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108180#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 108179#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 108178#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108177#L683-42 assume 1 == ~t4_pc~0; 108176#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 108174#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108173#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108172#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108171#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108170#L702-42 assume !(1 == ~t5_pc~0); 108169#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 108167#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108166#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 108165#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 108164#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 108163#L721-42 assume 1 == ~t6_pc~0; 108161#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 108160#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 108159#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 108158#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 108157#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 108156#L740-42 assume !(1 == ~t7_pc~0); 108155#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 108153#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108152#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 108151#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 108150#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108149#L759-42 assume 1 == ~t8_pc~0; 108147#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 108146#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108145#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 108144#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 108143#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 108142#L778-42 assume !(1 == ~t9_pc~0); 106063#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 106064#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 108140#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 108138#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 108135#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 108133#L797-42 assume !(1 == ~t10_pc~0); 108131#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 106617#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 106618#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 106951#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 107121#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 108117#L816-42 assume !(1 == ~t11_pc~0); 108113#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 108111#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 108110#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 108109#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 108108#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 108107#L835-42 assume 1 == ~t12_pc~0; 108105#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 108104#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 108103#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 108102#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 108101#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 108100#L854-42 assume 1 == ~t13_pc~0; 108099#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 108097#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 108096#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 108095#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 108094#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107116#L1401-3 assume !(1 == ~M_E~0); 107117#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 108595#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 107886#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 107885#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 107883#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 107880#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107878#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 107876#L1436-3 assume !(1 == ~T8_E~0); 107874#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 107872#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 107870#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 107867#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 107865#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 107863#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 107861#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107860#L1476-3 assume !(1 == ~E_3~0); 107859#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 107858#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107857#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107856#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107855#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 107854#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 107853#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 107852#L1516-3 assume !(1 == ~E_11~0); 107851#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 107850#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 107849#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 107657#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 107122#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 106416#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 106052#L1911 assume !(0 == start_simulation_~tmp~3#1); 106053#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 107263#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 107248#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 107245#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 107243#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 107241#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 107239#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 107237#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 105759#L1892-2 [2022-02-21 04:24:55,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:55,864 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2022-02-21 04:24:55,864 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:55,864 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83749951] [2022-02-21 04:24:55,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:55,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:55,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:55,895 INFO L290 TraceCheckUtils]: 0: Hoare triple {115802#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,895 INFO L290 TraceCheckUtils]: 1: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,896 INFO L290 TraceCheckUtils]: 2: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,896 INFO L290 TraceCheckUtils]: 3: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,896 INFO L290 TraceCheckUtils]: 4: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,897 INFO L290 TraceCheckUtils]: 5: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,897 INFO L290 TraceCheckUtils]: 6: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,897 INFO L290 TraceCheckUtils]: 7: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,898 INFO L290 TraceCheckUtils]: 8: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,898 INFO L290 TraceCheckUtils]: 9: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,898 INFO L290 TraceCheckUtils]: 10: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,899 INFO L290 TraceCheckUtils]: 11: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,899 INFO L290 TraceCheckUtils]: 12: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,899 INFO L290 TraceCheckUtils]: 13: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,899 INFO L290 TraceCheckUtils]: 14: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,900 INFO L290 TraceCheckUtils]: 15: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,900 INFO L290 TraceCheckUtils]: 16: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,900 INFO L290 TraceCheckUtils]: 17: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,901 INFO L290 TraceCheckUtils]: 18: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,901 INFO L290 TraceCheckUtils]: 19: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume !(0 == ~M_E~0); {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,901 INFO L290 TraceCheckUtils]: 20: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume !(0 == ~T1_E~0); {115804#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:55,901 INFO L290 TraceCheckUtils]: 21: Hoare triple {115804#(= ~T2_E~0 ~T8_E~0)} assume !(0 == ~T2_E~0); {115805#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:55,902 INFO L290 TraceCheckUtils]: 22: Hoare triple {115805#(not (= ~T8_E~0 0))} assume !(0 == ~T3_E~0); {115805#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:55,902 INFO L290 TraceCheckUtils]: 23: Hoare triple {115805#(not (= ~T8_E~0 0))} assume !(0 == ~T4_E~0); {115805#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:55,902 INFO L290 TraceCheckUtils]: 24: Hoare triple {115805#(not (= ~T8_E~0 0))} assume !(0 == ~T5_E~0); {115805#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:55,903 INFO L290 TraceCheckUtils]: 25: Hoare triple {115805#(not (= ~T8_E~0 0))} assume !(0 == ~T6_E~0); {115805#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:55,903 INFO L290 TraceCheckUtils]: 26: Hoare triple {115805#(not (= ~T8_E~0 0))} assume !(0 == ~T7_E~0); {115805#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:55,903 INFO L290 TraceCheckUtils]: 27: Hoare triple {115805#(not (= ~T8_E~0 0))} assume 0 == ~T8_E~0;~T8_E~0 := 1; {115803#false} is VALID [2022-02-21 04:24:55,903 INFO L290 TraceCheckUtils]: 28: Hoare triple {115803#false} assume !(0 == ~T9_E~0); {115803#false} is VALID [2022-02-21 04:24:55,903 INFO L290 TraceCheckUtils]: 29: Hoare triple {115803#false} assume !(0 == ~T10_E~0); {115803#false} is VALID [2022-02-21 04:24:55,904 INFO L290 TraceCheckUtils]: 30: Hoare triple {115803#false} assume !(0 == ~T11_E~0); {115803#false} is VALID [2022-02-21 04:24:55,904 INFO L290 TraceCheckUtils]: 31: Hoare triple {115803#false} assume !(0 == ~T12_E~0); {115803#false} is VALID [2022-02-21 04:24:55,904 INFO L290 TraceCheckUtils]: 32: Hoare triple {115803#false} assume !(0 == ~T13_E~0); {115803#false} is VALID [2022-02-21 04:24:55,904 INFO L290 TraceCheckUtils]: 33: Hoare triple {115803#false} assume !(0 == ~E_1~0); {115803#false} is VALID [2022-02-21 04:24:55,904 INFO L290 TraceCheckUtils]: 34: Hoare triple {115803#false} assume !(0 == ~E_2~0); {115803#false} is VALID [2022-02-21 04:24:55,904 INFO L290 TraceCheckUtils]: 35: Hoare triple {115803#false} assume 0 == ~E_3~0;~E_3~0 := 1; {115803#false} is VALID [2022-02-21 04:24:55,904 INFO L290 TraceCheckUtils]: 36: Hoare triple {115803#false} assume !(0 == ~E_4~0); {115803#false} is VALID [2022-02-21 04:24:55,905 INFO L290 TraceCheckUtils]: 37: Hoare triple {115803#false} assume !(0 == ~E_5~0); {115803#false} is VALID [2022-02-21 04:24:55,905 INFO L290 TraceCheckUtils]: 38: Hoare triple {115803#false} assume !(0 == ~E_6~0); {115803#false} is VALID [2022-02-21 04:24:55,905 INFO L290 TraceCheckUtils]: 39: Hoare triple {115803#false} assume !(0 == ~E_7~0); {115803#false} is VALID [2022-02-21 04:24:55,905 INFO L290 TraceCheckUtils]: 40: Hoare triple {115803#false} assume !(0 == ~E_8~0); {115803#false} is VALID [2022-02-21 04:24:55,905 INFO L290 TraceCheckUtils]: 41: Hoare triple {115803#false} assume !(0 == ~E_9~0); {115803#false} is VALID [2022-02-21 04:24:55,905 INFO L290 TraceCheckUtils]: 42: Hoare triple {115803#false} assume !(0 == ~E_10~0); {115803#false} is VALID [2022-02-21 04:24:55,905 INFO L290 TraceCheckUtils]: 43: Hoare triple {115803#false} assume 0 == ~E_11~0;~E_11~0 := 1; {115803#false} is VALID [2022-02-21 04:24:55,905 INFO L290 TraceCheckUtils]: 44: Hoare triple {115803#false} assume !(0 == ~E_12~0); {115803#false} is VALID [2022-02-21 04:24:55,905 INFO L290 TraceCheckUtils]: 45: Hoare triple {115803#false} assume !(0 == ~E_13~0); {115803#false} is VALID [2022-02-21 04:24:55,906 INFO L290 TraceCheckUtils]: 46: Hoare triple {115803#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {115803#false} is VALID [2022-02-21 04:24:55,906 INFO L290 TraceCheckUtils]: 47: Hoare triple {115803#false} assume !(1 == ~m_pc~0); {115803#false} is VALID [2022-02-21 04:24:55,906 INFO L290 TraceCheckUtils]: 48: Hoare triple {115803#false} is_master_triggered_~__retres1~0#1 := 0; {115803#false} is VALID [2022-02-21 04:24:55,906 INFO L290 TraceCheckUtils]: 49: Hoare triple {115803#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {115803#false} is VALID [2022-02-21 04:24:55,906 INFO L290 TraceCheckUtils]: 50: Hoare triple {115803#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {115803#false} is VALID [2022-02-21 04:24:55,906 INFO L290 TraceCheckUtils]: 51: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp~1#1); {115803#false} is VALID [2022-02-21 04:24:55,906 INFO L290 TraceCheckUtils]: 52: Hoare triple {115803#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {115803#false} is VALID [2022-02-21 04:24:55,906 INFO L290 TraceCheckUtils]: 53: Hoare triple {115803#false} assume !(1 == ~t1_pc~0); {115803#false} is VALID [2022-02-21 04:24:55,906 INFO L290 TraceCheckUtils]: 54: Hoare triple {115803#false} is_transmit1_triggered_~__retres1~1#1 := 0; {115803#false} is VALID [2022-02-21 04:24:55,907 INFO L290 TraceCheckUtils]: 55: Hoare triple {115803#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {115803#false} is VALID [2022-02-21 04:24:55,907 INFO L290 TraceCheckUtils]: 56: Hoare triple {115803#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {115803#false} is VALID [2022-02-21 04:24:55,907 INFO L290 TraceCheckUtils]: 57: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___0~0#1); {115803#false} is VALID [2022-02-21 04:24:55,907 INFO L290 TraceCheckUtils]: 58: Hoare triple {115803#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {115803#false} is VALID [2022-02-21 04:24:55,907 INFO L290 TraceCheckUtils]: 59: Hoare triple {115803#false} assume 1 == ~t2_pc~0; {115803#false} is VALID [2022-02-21 04:24:55,907 INFO L290 TraceCheckUtils]: 60: Hoare triple {115803#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {115803#false} is VALID [2022-02-21 04:24:55,907 INFO L290 TraceCheckUtils]: 61: Hoare triple {115803#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {115803#false} is VALID [2022-02-21 04:24:55,908 INFO L290 TraceCheckUtils]: 62: Hoare triple {115803#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {115803#false} is VALID [2022-02-21 04:24:55,908 INFO L290 TraceCheckUtils]: 63: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___1~0#1); {115803#false} is VALID [2022-02-21 04:24:55,908 INFO L290 TraceCheckUtils]: 64: Hoare triple {115803#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {115803#false} is VALID [2022-02-21 04:24:55,908 INFO L290 TraceCheckUtils]: 65: Hoare triple {115803#false} assume 1 == ~t3_pc~0; {115803#false} is VALID [2022-02-21 04:24:55,908 INFO L290 TraceCheckUtils]: 66: Hoare triple {115803#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {115803#false} is VALID [2022-02-21 04:24:55,908 INFO L290 TraceCheckUtils]: 67: Hoare triple {115803#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {115803#false} is VALID [2022-02-21 04:24:55,908 INFO L290 TraceCheckUtils]: 68: Hoare triple {115803#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {115803#false} is VALID [2022-02-21 04:24:55,908 INFO L290 TraceCheckUtils]: 69: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___2~0#1); {115803#false} is VALID [2022-02-21 04:24:55,909 INFO L290 TraceCheckUtils]: 70: Hoare triple {115803#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {115803#false} is VALID [2022-02-21 04:24:55,909 INFO L290 TraceCheckUtils]: 71: Hoare triple {115803#false} assume !(1 == ~t4_pc~0); {115803#false} is VALID [2022-02-21 04:24:55,909 INFO L290 TraceCheckUtils]: 72: Hoare triple {115803#false} is_transmit4_triggered_~__retres1~4#1 := 0; {115803#false} is VALID [2022-02-21 04:24:55,909 INFO L290 TraceCheckUtils]: 73: Hoare triple {115803#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {115803#false} is VALID [2022-02-21 04:24:55,909 INFO L290 TraceCheckUtils]: 74: Hoare triple {115803#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {115803#false} is VALID [2022-02-21 04:24:55,909 INFO L290 TraceCheckUtils]: 75: Hoare triple {115803#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {115803#false} is VALID [2022-02-21 04:24:55,909 INFO L290 TraceCheckUtils]: 76: Hoare triple {115803#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {115803#false} is VALID [2022-02-21 04:24:55,909 INFO L290 TraceCheckUtils]: 77: Hoare triple {115803#false} assume 1 == ~t5_pc~0; {115803#false} is VALID [2022-02-21 04:24:55,910 INFO L290 TraceCheckUtils]: 78: Hoare triple {115803#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {115803#false} is VALID [2022-02-21 04:24:55,910 INFO L290 TraceCheckUtils]: 79: Hoare triple {115803#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {115803#false} is VALID [2022-02-21 04:24:55,910 INFO L290 TraceCheckUtils]: 80: Hoare triple {115803#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {115803#false} is VALID [2022-02-21 04:24:55,910 INFO L290 TraceCheckUtils]: 81: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___4~0#1); {115803#false} is VALID [2022-02-21 04:24:55,910 INFO L290 TraceCheckUtils]: 82: Hoare triple {115803#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {115803#false} is VALID [2022-02-21 04:24:55,910 INFO L290 TraceCheckUtils]: 83: Hoare triple {115803#false} assume !(1 == ~t6_pc~0); {115803#false} is VALID [2022-02-21 04:24:55,910 INFO L290 TraceCheckUtils]: 84: Hoare triple {115803#false} is_transmit6_triggered_~__retres1~6#1 := 0; {115803#false} is VALID [2022-02-21 04:24:55,910 INFO L290 TraceCheckUtils]: 85: Hoare triple {115803#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {115803#false} is VALID [2022-02-21 04:24:55,911 INFO L290 TraceCheckUtils]: 86: Hoare triple {115803#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {115803#false} is VALID [2022-02-21 04:24:55,911 INFO L290 TraceCheckUtils]: 87: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___5~0#1); {115803#false} is VALID [2022-02-21 04:24:55,911 INFO L290 TraceCheckUtils]: 88: Hoare triple {115803#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {115803#false} is VALID [2022-02-21 04:24:55,911 INFO L290 TraceCheckUtils]: 89: Hoare triple {115803#false} assume 1 == ~t7_pc~0; {115803#false} is VALID [2022-02-21 04:24:55,911 INFO L290 TraceCheckUtils]: 90: Hoare triple {115803#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {115803#false} is VALID [2022-02-21 04:24:55,911 INFO L290 TraceCheckUtils]: 91: Hoare triple {115803#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {115803#false} is VALID [2022-02-21 04:24:55,911 INFO L290 TraceCheckUtils]: 92: Hoare triple {115803#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {115803#false} is VALID [2022-02-21 04:24:55,911 INFO L290 TraceCheckUtils]: 93: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___6~0#1); {115803#false} is VALID [2022-02-21 04:24:55,911 INFO L290 TraceCheckUtils]: 94: Hoare triple {115803#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {115803#false} is VALID [2022-02-21 04:24:55,912 INFO L290 TraceCheckUtils]: 95: Hoare triple {115803#false} assume !(1 == ~t8_pc~0); {115803#false} is VALID [2022-02-21 04:24:55,912 INFO L290 TraceCheckUtils]: 96: Hoare triple {115803#false} is_transmit8_triggered_~__retres1~8#1 := 0; {115803#false} is VALID [2022-02-21 04:24:55,912 INFO L290 TraceCheckUtils]: 97: Hoare triple {115803#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {115803#false} is VALID [2022-02-21 04:24:55,912 INFO L290 TraceCheckUtils]: 98: Hoare triple {115803#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {115803#false} is VALID [2022-02-21 04:24:55,912 INFO L290 TraceCheckUtils]: 99: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___7~0#1); {115803#false} is VALID [2022-02-21 04:24:55,912 INFO L290 TraceCheckUtils]: 100: Hoare triple {115803#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {115803#false} is VALID [2022-02-21 04:24:55,912 INFO L290 TraceCheckUtils]: 101: Hoare triple {115803#false} assume 1 == ~t9_pc~0; {115803#false} is VALID [2022-02-21 04:24:55,912 INFO L290 TraceCheckUtils]: 102: Hoare triple {115803#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {115803#false} is VALID [2022-02-21 04:24:55,912 INFO L290 TraceCheckUtils]: 103: Hoare triple {115803#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {115803#false} is VALID [2022-02-21 04:24:55,913 INFO L290 TraceCheckUtils]: 104: Hoare triple {115803#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {115803#false} is VALID [2022-02-21 04:24:55,913 INFO L290 TraceCheckUtils]: 105: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___8~0#1); {115803#false} is VALID [2022-02-21 04:24:55,913 INFO L290 TraceCheckUtils]: 106: Hoare triple {115803#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {115803#false} is VALID [2022-02-21 04:24:55,913 INFO L290 TraceCheckUtils]: 107: Hoare triple {115803#false} assume !(1 == ~t10_pc~0); {115803#false} is VALID [2022-02-21 04:24:55,913 INFO L290 TraceCheckUtils]: 108: Hoare triple {115803#false} is_transmit10_triggered_~__retres1~10#1 := 0; {115803#false} is VALID [2022-02-21 04:24:55,913 INFO L290 TraceCheckUtils]: 109: Hoare triple {115803#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {115803#false} is VALID [2022-02-21 04:24:55,913 INFO L290 TraceCheckUtils]: 110: Hoare triple {115803#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {115803#false} is VALID [2022-02-21 04:24:55,913 INFO L290 TraceCheckUtils]: 111: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___9~0#1); {115803#false} is VALID [2022-02-21 04:24:55,913 INFO L290 TraceCheckUtils]: 112: Hoare triple {115803#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {115803#false} is VALID [2022-02-21 04:24:55,914 INFO L290 TraceCheckUtils]: 113: Hoare triple {115803#false} assume 1 == ~t11_pc~0; {115803#false} is VALID [2022-02-21 04:24:55,914 INFO L290 TraceCheckUtils]: 114: Hoare triple {115803#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {115803#false} is VALID [2022-02-21 04:24:55,914 INFO L290 TraceCheckUtils]: 115: Hoare triple {115803#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {115803#false} is VALID [2022-02-21 04:24:55,914 INFO L290 TraceCheckUtils]: 116: Hoare triple {115803#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {115803#false} is VALID [2022-02-21 04:24:55,914 INFO L290 TraceCheckUtils]: 117: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___10~0#1); {115803#false} is VALID [2022-02-21 04:24:55,914 INFO L290 TraceCheckUtils]: 118: Hoare triple {115803#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {115803#false} is VALID [2022-02-21 04:24:55,914 INFO L290 TraceCheckUtils]: 119: Hoare triple {115803#false} assume 1 == ~t12_pc~0; {115803#false} is VALID [2022-02-21 04:24:55,914 INFO L290 TraceCheckUtils]: 120: Hoare triple {115803#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {115803#false} is VALID [2022-02-21 04:24:55,914 INFO L290 TraceCheckUtils]: 121: Hoare triple {115803#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {115803#false} is VALID [2022-02-21 04:24:55,915 INFO L290 TraceCheckUtils]: 122: Hoare triple {115803#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {115803#false} is VALID [2022-02-21 04:24:55,915 INFO L290 TraceCheckUtils]: 123: Hoare triple {115803#false} assume !(0 != activate_threads_~tmp___11~0#1); {115803#false} is VALID [2022-02-21 04:24:55,915 INFO L290 TraceCheckUtils]: 124: Hoare triple {115803#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {115803#false} is VALID [2022-02-21 04:24:55,915 INFO L290 TraceCheckUtils]: 125: Hoare triple {115803#false} assume !(1 == ~t13_pc~0); {115803#false} is VALID [2022-02-21 04:24:55,915 INFO L290 TraceCheckUtils]: 126: Hoare triple {115803#false} is_transmit13_triggered_~__retres1~13#1 := 0; {115803#false} is VALID [2022-02-21 04:24:55,915 INFO L290 TraceCheckUtils]: 127: Hoare triple {115803#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {115803#false} is VALID [2022-02-21 04:24:55,915 INFO L290 TraceCheckUtils]: 128: Hoare triple {115803#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {115803#false} is VALID [2022-02-21 04:24:55,915 INFO L290 TraceCheckUtils]: 129: Hoare triple {115803#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {115803#false} is VALID [2022-02-21 04:24:55,915 INFO L290 TraceCheckUtils]: 130: Hoare triple {115803#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {115803#false} is VALID [2022-02-21 04:24:55,916 INFO L290 TraceCheckUtils]: 131: Hoare triple {115803#false} assume !(1 == ~M_E~0); {115803#false} is VALID [2022-02-21 04:24:55,916 INFO L290 TraceCheckUtils]: 132: Hoare triple {115803#false} assume !(1 == ~T1_E~0); {115803#false} is VALID [2022-02-21 04:24:55,916 INFO L290 TraceCheckUtils]: 133: Hoare triple {115803#false} assume !(1 == ~T2_E~0); {115803#false} is VALID [2022-02-21 04:24:55,916 INFO L290 TraceCheckUtils]: 134: Hoare triple {115803#false} assume !(1 == ~T3_E~0); {115803#false} is VALID [2022-02-21 04:24:55,916 INFO L290 TraceCheckUtils]: 135: Hoare triple {115803#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {115803#false} is VALID [2022-02-21 04:24:55,916 INFO L290 TraceCheckUtils]: 136: Hoare triple {115803#false} assume !(1 == ~T5_E~0); {115803#false} is VALID [2022-02-21 04:24:55,916 INFO L290 TraceCheckUtils]: 137: Hoare triple {115803#false} assume !(1 == ~T6_E~0); {115803#false} is VALID [2022-02-21 04:24:55,916 INFO L290 TraceCheckUtils]: 138: Hoare triple {115803#false} assume !(1 == ~T7_E~0); {115803#false} is VALID [2022-02-21 04:24:55,916 INFO L290 TraceCheckUtils]: 139: Hoare triple {115803#false} assume !(1 == ~T8_E~0); {115803#false} is VALID [2022-02-21 04:24:55,917 INFO L290 TraceCheckUtils]: 140: Hoare triple {115803#false} assume !(1 == ~T9_E~0); {115803#false} is VALID [2022-02-21 04:24:55,917 INFO L290 TraceCheckUtils]: 141: Hoare triple {115803#false} assume !(1 == ~T10_E~0); {115803#false} is VALID [2022-02-21 04:24:55,917 INFO L290 TraceCheckUtils]: 142: Hoare triple {115803#false} assume !(1 == ~T11_E~0); {115803#false} is VALID [2022-02-21 04:24:55,917 INFO L290 TraceCheckUtils]: 143: Hoare triple {115803#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {115803#false} is VALID [2022-02-21 04:24:55,917 INFO L290 TraceCheckUtils]: 144: Hoare triple {115803#false} assume !(1 == ~T13_E~0); {115803#false} is VALID [2022-02-21 04:24:55,917 INFO L290 TraceCheckUtils]: 145: Hoare triple {115803#false} assume !(1 == ~E_1~0); {115803#false} is VALID [2022-02-21 04:24:55,917 INFO L290 TraceCheckUtils]: 146: Hoare triple {115803#false} assume !(1 == ~E_2~0); {115803#false} is VALID [2022-02-21 04:24:55,917 INFO L290 TraceCheckUtils]: 147: Hoare triple {115803#false} assume !(1 == ~E_3~0); {115803#false} is VALID [2022-02-21 04:24:55,917 INFO L290 TraceCheckUtils]: 148: Hoare triple {115803#false} assume !(1 == ~E_4~0); {115803#false} is VALID [2022-02-21 04:24:55,918 INFO L290 TraceCheckUtils]: 149: Hoare triple {115803#false} assume !(1 == ~E_5~0); {115803#false} is VALID [2022-02-21 04:24:55,918 INFO L290 TraceCheckUtils]: 150: Hoare triple {115803#false} assume !(1 == ~E_6~0); {115803#false} is VALID [2022-02-21 04:24:55,918 INFO L290 TraceCheckUtils]: 151: Hoare triple {115803#false} assume 1 == ~E_7~0;~E_7~0 := 2; {115803#false} is VALID [2022-02-21 04:24:55,918 INFO L290 TraceCheckUtils]: 152: Hoare triple {115803#false} assume !(1 == ~E_8~0); {115803#false} is VALID [2022-02-21 04:24:55,918 INFO L290 TraceCheckUtils]: 153: Hoare triple {115803#false} assume !(1 == ~E_9~0); {115803#false} is VALID [2022-02-21 04:24:55,918 INFO L290 TraceCheckUtils]: 154: Hoare triple {115803#false} assume !(1 == ~E_10~0); {115803#false} is VALID [2022-02-21 04:24:55,918 INFO L290 TraceCheckUtils]: 155: Hoare triple {115803#false} assume !(1 == ~E_11~0); {115803#false} is VALID [2022-02-21 04:24:55,918 INFO L290 TraceCheckUtils]: 156: Hoare triple {115803#false} assume !(1 == ~E_12~0); {115803#false} is VALID [2022-02-21 04:24:55,918 INFO L290 TraceCheckUtils]: 157: Hoare triple {115803#false} assume !(1 == ~E_13~0); {115803#false} is VALID [2022-02-21 04:24:55,919 INFO L290 TraceCheckUtils]: 158: Hoare triple {115803#false} assume { :end_inline_reset_delta_events } true; {115803#false} is VALID [2022-02-21 04:24:55,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:55,919 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:55,919 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83749951] [2022-02-21 04:24:55,919 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83749951] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:55,920 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:55,920 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:55,920 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328881927] [2022-02-21 04:24:55,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:55,920 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:55,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:55,921 INFO L85 PathProgramCache]: Analyzing trace with hash 272558378, now seen corresponding path program 1 times [2022-02-21 04:24:55,921 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:55,921 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555351977] [2022-02-21 04:24:55,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:55,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:55,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:55,968 INFO L290 TraceCheckUtils]: 0: Hoare triple {115806#true} assume !false; {115806#true} is VALID [2022-02-21 04:24:55,968 INFO L290 TraceCheckUtils]: 1: Hoare triple {115806#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {115806#true} is VALID [2022-02-21 04:24:55,968 INFO L290 TraceCheckUtils]: 2: Hoare triple {115806#true} assume !false; {115806#true} is VALID [2022-02-21 04:24:55,969 INFO L290 TraceCheckUtils]: 3: Hoare triple {115806#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {115806#true} is VALID [2022-02-21 04:24:55,969 INFO L290 TraceCheckUtils]: 4: Hoare triple {115806#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {115806#true} is VALID [2022-02-21 04:24:55,969 INFO L290 TraceCheckUtils]: 5: Hoare triple {115806#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {115806#true} is VALID [2022-02-21 04:24:55,969 INFO L290 TraceCheckUtils]: 6: Hoare triple {115806#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {115806#true} is VALID [2022-02-21 04:24:55,969 INFO L290 TraceCheckUtils]: 7: Hoare triple {115806#true} assume !(0 != eval_~tmp~0#1); {115806#true} is VALID [2022-02-21 04:24:55,969 INFO L290 TraceCheckUtils]: 8: Hoare triple {115806#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {115806#true} is VALID [2022-02-21 04:24:55,969 INFO L290 TraceCheckUtils]: 9: Hoare triple {115806#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {115806#true} is VALID [2022-02-21 04:24:55,969 INFO L290 TraceCheckUtils]: 10: Hoare triple {115806#true} assume !(0 == ~M_E~0); {115806#true} is VALID [2022-02-21 04:24:55,969 INFO L290 TraceCheckUtils]: 11: Hoare triple {115806#true} assume !(0 == ~T1_E~0); {115806#true} is VALID [2022-02-21 04:24:55,970 INFO L290 TraceCheckUtils]: 12: Hoare triple {115806#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {115806#true} is VALID [2022-02-21 04:24:55,970 INFO L290 TraceCheckUtils]: 13: Hoare triple {115806#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {115806#true} is VALID [2022-02-21 04:24:55,970 INFO L290 TraceCheckUtils]: 14: Hoare triple {115806#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {115806#true} is VALID [2022-02-21 04:24:55,970 INFO L290 TraceCheckUtils]: 15: Hoare triple {115806#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {115806#true} is VALID [2022-02-21 04:24:55,970 INFO L290 TraceCheckUtils]: 16: Hoare triple {115806#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {115806#true} is VALID [2022-02-21 04:24:55,970 INFO L290 TraceCheckUtils]: 17: Hoare triple {115806#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {115806#true} is VALID [2022-02-21 04:24:55,970 INFO L290 TraceCheckUtils]: 18: Hoare triple {115806#true} assume 0 == ~T8_E~0;~T8_E~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,971 INFO L290 TraceCheckUtils]: 19: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(0 == ~T9_E~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,971 INFO L290 TraceCheckUtils]: 20: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,971 INFO L290 TraceCheckUtils]: 21: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,972 INFO L290 TraceCheckUtils]: 22: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,972 INFO L290 TraceCheckUtils]: 23: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,972 INFO L290 TraceCheckUtils]: 24: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,972 INFO L290 TraceCheckUtils]: 25: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,973 INFO L290 TraceCheckUtils]: 26: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,973 INFO L290 TraceCheckUtils]: 27: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(0 == ~E_4~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,973 INFO L290 TraceCheckUtils]: 28: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,974 INFO L290 TraceCheckUtils]: 29: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,974 INFO L290 TraceCheckUtils]: 30: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,974 INFO L290 TraceCheckUtils]: 31: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,974 INFO L290 TraceCheckUtils]: 32: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,975 INFO L290 TraceCheckUtils]: 33: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,975 INFO L290 TraceCheckUtils]: 34: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,975 INFO L290 TraceCheckUtils]: 35: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(0 == ~E_12~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,976 INFO L290 TraceCheckUtils]: 36: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,976 INFO L290 TraceCheckUtils]: 37: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,976 INFO L290 TraceCheckUtils]: 38: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~m_pc~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,976 INFO L290 TraceCheckUtils]: 39: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,977 INFO L290 TraceCheckUtils]: 40: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,977 INFO L290 TraceCheckUtils]: 41: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,977 INFO L290 TraceCheckUtils]: 42: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,977 INFO L290 TraceCheckUtils]: 43: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,978 INFO L290 TraceCheckUtils]: 44: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t1_pc~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,978 INFO L290 TraceCheckUtils]: 45: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,978 INFO L290 TraceCheckUtils]: 46: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,979 INFO L290 TraceCheckUtils]: 47: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,979 INFO L290 TraceCheckUtils]: 48: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,979 INFO L290 TraceCheckUtils]: 49: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,979 INFO L290 TraceCheckUtils]: 50: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t2_pc~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,980 INFO L290 TraceCheckUtils]: 51: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,980 INFO L290 TraceCheckUtils]: 52: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,980 INFO L290 TraceCheckUtils]: 53: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,980 INFO L290 TraceCheckUtils]: 54: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,981 INFO L290 TraceCheckUtils]: 55: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,981 INFO L290 TraceCheckUtils]: 56: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t3_pc~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,981 INFO L290 TraceCheckUtils]: 57: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,982 INFO L290 TraceCheckUtils]: 58: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,982 INFO L290 TraceCheckUtils]: 59: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,982 INFO L290 TraceCheckUtils]: 60: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,982 INFO L290 TraceCheckUtils]: 61: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,983 INFO L290 TraceCheckUtils]: 62: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t4_pc~0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,983 INFO L290 TraceCheckUtils]: 63: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,983 INFO L290 TraceCheckUtils]: 64: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,984 INFO L290 TraceCheckUtils]: 65: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,984 INFO L290 TraceCheckUtils]: 66: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,984 INFO L290 TraceCheckUtils]: 67: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,984 INFO L290 TraceCheckUtils]: 68: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t5_pc~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,985 INFO L290 TraceCheckUtils]: 69: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,985 INFO L290 TraceCheckUtils]: 70: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,985 INFO L290 TraceCheckUtils]: 71: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,985 INFO L290 TraceCheckUtils]: 72: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,986 INFO L290 TraceCheckUtils]: 73: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,986 INFO L290 TraceCheckUtils]: 74: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t6_pc~0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,986 INFO L290 TraceCheckUtils]: 75: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,987 INFO L290 TraceCheckUtils]: 76: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,987 INFO L290 TraceCheckUtils]: 77: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,987 INFO L290 TraceCheckUtils]: 78: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,987 INFO L290 TraceCheckUtils]: 79: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,988 INFO L290 TraceCheckUtils]: 80: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t7_pc~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,988 INFO L290 TraceCheckUtils]: 81: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,988 INFO L290 TraceCheckUtils]: 82: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,988 INFO L290 TraceCheckUtils]: 83: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,989 INFO L290 TraceCheckUtils]: 84: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,989 INFO L290 TraceCheckUtils]: 85: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,989 INFO L290 TraceCheckUtils]: 86: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t8_pc~0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,990 INFO L290 TraceCheckUtils]: 87: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,990 INFO L290 TraceCheckUtils]: 88: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,990 INFO L290 TraceCheckUtils]: 89: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,990 INFO L290 TraceCheckUtils]: 90: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,991 INFO L290 TraceCheckUtils]: 91: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,991 INFO L290 TraceCheckUtils]: 92: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t9_pc~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,991 INFO L290 TraceCheckUtils]: 93: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,992 INFO L290 TraceCheckUtils]: 94: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,992 INFO L290 TraceCheckUtils]: 95: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,992 INFO L290 TraceCheckUtils]: 96: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,992 INFO L290 TraceCheckUtils]: 97: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,993 INFO L290 TraceCheckUtils]: 98: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t10_pc~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,993 INFO L290 TraceCheckUtils]: 99: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,993 INFO L290 TraceCheckUtils]: 100: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,993 INFO L290 TraceCheckUtils]: 101: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,994 INFO L290 TraceCheckUtils]: 102: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,994 INFO L290 TraceCheckUtils]: 103: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,994 INFO L290 TraceCheckUtils]: 104: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~t11_pc~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,995 INFO L290 TraceCheckUtils]: 105: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,995 INFO L290 TraceCheckUtils]: 106: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,995 INFO L290 TraceCheckUtils]: 107: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,995 INFO L290 TraceCheckUtils]: 108: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,996 INFO L290 TraceCheckUtils]: 109: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,996 INFO L290 TraceCheckUtils]: 110: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t12_pc~0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,996 INFO L290 TraceCheckUtils]: 111: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,996 INFO L290 TraceCheckUtils]: 112: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,997 INFO L290 TraceCheckUtils]: 113: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,997 INFO L290 TraceCheckUtils]: 114: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,997 INFO L290 TraceCheckUtils]: 115: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,998 INFO L290 TraceCheckUtils]: 116: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~t13_pc~0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,998 INFO L290 TraceCheckUtils]: 117: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,998 INFO L290 TraceCheckUtils]: 118: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,998 INFO L290 TraceCheckUtils]: 119: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,999 INFO L290 TraceCheckUtils]: 120: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,999 INFO L290 TraceCheckUtils]: 121: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,999 INFO L290 TraceCheckUtils]: 122: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~M_E~0); {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:55,999 INFO L290 TraceCheckUtils]: 123: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:56,000 INFO L290 TraceCheckUtils]: 124: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:56,000 INFO L290 TraceCheckUtils]: 125: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:56,000 INFO L290 TraceCheckUtils]: 126: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:56,001 INFO L290 TraceCheckUtils]: 127: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:56,001 INFO L290 TraceCheckUtils]: 128: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:56,001 INFO L290 TraceCheckUtils]: 129: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {115808#(= (+ (- 1) ~T8_E~0) 0)} is VALID [2022-02-21 04:24:56,002 INFO L290 TraceCheckUtils]: 130: Hoare triple {115808#(= (+ (- 1) ~T8_E~0) 0)} assume !(1 == ~T8_E~0); {115807#false} is VALID [2022-02-21 04:24:56,002 INFO L290 TraceCheckUtils]: 131: Hoare triple {115807#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,002 INFO L290 TraceCheckUtils]: 132: Hoare triple {115807#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,002 INFO L290 TraceCheckUtils]: 133: Hoare triple {115807#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,002 INFO L290 TraceCheckUtils]: 134: Hoare triple {115807#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,003 INFO L290 TraceCheckUtils]: 135: Hoare triple {115807#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,003 INFO L290 TraceCheckUtils]: 136: Hoare triple {115807#false} assume 1 == ~E_1~0;~E_1~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,003 INFO L290 TraceCheckUtils]: 137: Hoare triple {115807#false} assume 1 == ~E_2~0;~E_2~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,003 INFO L290 TraceCheckUtils]: 138: Hoare triple {115807#false} assume !(1 == ~E_3~0); {115807#false} is VALID [2022-02-21 04:24:56,003 INFO L290 TraceCheckUtils]: 139: Hoare triple {115807#false} assume 1 == ~E_4~0;~E_4~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,003 INFO L290 TraceCheckUtils]: 140: Hoare triple {115807#false} assume 1 == ~E_5~0;~E_5~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,003 INFO L290 TraceCheckUtils]: 141: Hoare triple {115807#false} assume 1 == ~E_6~0;~E_6~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,003 INFO L290 TraceCheckUtils]: 142: Hoare triple {115807#false} assume 1 == ~E_7~0;~E_7~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,004 INFO L290 TraceCheckUtils]: 143: Hoare triple {115807#false} assume 1 == ~E_8~0;~E_8~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,004 INFO L290 TraceCheckUtils]: 144: Hoare triple {115807#false} assume 1 == ~E_9~0;~E_9~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,004 INFO L290 TraceCheckUtils]: 145: Hoare triple {115807#false} assume 1 == ~E_10~0;~E_10~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,004 INFO L290 TraceCheckUtils]: 146: Hoare triple {115807#false} assume !(1 == ~E_11~0); {115807#false} is VALID [2022-02-21 04:24:56,004 INFO L290 TraceCheckUtils]: 147: Hoare triple {115807#false} assume 1 == ~E_12~0;~E_12~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,004 INFO L290 TraceCheckUtils]: 148: Hoare triple {115807#false} assume 1 == ~E_13~0;~E_13~0 := 2; {115807#false} is VALID [2022-02-21 04:24:56,004 INFO L290 TraceCheckUtils]: 149: Hoare triple {115807#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {115807#false} is VALID [2022-02-21 04:24:56,004 INFO L290 TraceCheckUtils]: 150: Hoare triple {115807#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {115807#false} is VALID [2022-02-21 04:24:56,004 INFO L290 TraceCheckUtils]: 151: Hoare triple {115807#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {115807#false} is VALID [2022-02-21 04:24:56,005 INFO L290 TraceCheckUtils]: 152: Hoare triple {115807#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {115807#false} is VALID [2022-02-21 04:24:56,005 INFO L290 TraceCheckUtils]: 153: Hoare triple {115807#false} assume !(0 == start_simulation_~tmp~3#1); {115807#false} is VALID [2022-02-21 04:24:56,005 INFO L290 TraceCheckUtils]: 154: Hoare triple {115807#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {115807#false} is VALID [2022-02-21 04:24:56,005 INFO L290 TraceCheckUtils]: 155: Hoare triple {115807#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {115807#false} is VALID [2022-02-21 04:24:56,005 INFO L290 TraceCheckUtils]: 156: Hoare triple {115807#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {115807#false} is VALID [2022-02-21 04:24:56,005 INFO L290 TraceCheckUtils]: 157: Hoare triple {115807#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {115807#false} is VALID [2022-02-21 04:24:56,005 INFO L290 TraceCheckUtils]: 158: Hoare triple {115807#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {115807#false} is VALID [2022-02-21 04:24:56,005 INFO L290 TraceCheckUtils]: 159: Hoare triple {115807#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {115807#false} is VALID [2022-02-21 04:24:56,005 INFO L290 TraceCheckUtils]: 160: Hoare triple {115807#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {115807#false} is VALID [2022-02-21 04:24:56,006 INFO L290 TraceCheckUtils]: 161: Hoare triple {115807#false} assume !(0 != start_simulation_~tmp___0~1#1); {115807#false} is VALID [2022-02-21 04:24:56,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:56,006 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:56,006 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1555351977] [2022-02-21 04:24:56,007 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1555351977] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:56,007 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:56,007 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:56,007 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442195412] [2022-02-21 04:24:56,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:56,007 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:56,007 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:56,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:56,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:56,008 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:00,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:00,230 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-02-21 04:25:00,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:25:00,230 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:00,352 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:00,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:01,533 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-02-21 04:25:02,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-02-21 04:25:02,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6962 [2022-02-21 04:25:02,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6962 [2022-02-21 04:25:02,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:02,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:02,697 INFO L681 BuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-02-21 04:25:02,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:02,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6962 to 6962. [2022-02-21 04:25:02,766 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:02,772 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6962 states and 10199 transitions. Second operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:02,779 INFO L74 IsIncluded]: Start isIncluded. First operand 6962 states and 10199 transitions. Second operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:02,787 INFO L87 Difference]: Start difference. First operand 6962 states and 10199 transitions. Second operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:03,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:03,885 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-02-21 04:25:03,885 INFO L276 IsEmpty]: Start isEmpty. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:03,892 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:03,892 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:03,900 INFO L74 IsIncluded]: Start isIncluded. First operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6962 states and 10199 transitions. [2022-02-21 04:25:03,907 INFO L87 Difference]: Start difference. First operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6962 states and 10199 transitions. [2022-02-21 04:25:04,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:04,993 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-02-21 04:25:04,994 INFO L276 IsEmpty]: Start isEmpty. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:04,999 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:04,999 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:04,999 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:04,999 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:05,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:06,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-02-21 04:25:06,182 INFO L704 BuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-02-21 04:25:06,182 INFO L587 BuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-02-21 04:25:06,182 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:25:06,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:06,192 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-02-21 04:25:06,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:06,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:06,193 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:06,193 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:06,194 INFO L791 eck$LassoCheckResult]: Stem: 123642#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 123643#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 123460#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 123172#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 123173#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 124363#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 124364#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 123310#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 123311#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123770#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 123602#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123603#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 123379#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 123380#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 123781#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 123958#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 124112#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 124149#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 123390#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 123391#L1258 assume !(0 == ~M_E~0); 124591#L1258-2 assume !(0 == ~T1_E~0); 123687#L1263-1 assume !(0 == ~T2_E~0); 123688#L1268-1 assume !(0 == ~T3_E~0); 123993#L1273-1 assume !(0 == ~T4_E~0); 124569#L1278-1 assume !(0 == ~T5_E~0); 124419#L1283-1 assume !(0 == ~T6_E~0); 124420#L1288-1 assume !(0 == ~T7_E~0); 124673#L1293-1 assume !(0 == ~T8_E~0); 124661#L1298-1 assume !(0 == ~T9_E~0); 124584#L1303-1 assume !(0 == ~T10_E~0); 123202#L1308-1 assume !(0 == ~T11_E~0); 123143#L1313-1 assume !(0 == ~T12_E~0); 123144#L1318-1 assume !(0 == ~T13_E~0); 123150#L1323-1 assume !(0 == ~E_1~0); 123151#L1328-1 assume !(0 == ~E_2~0); 123320#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 124288#L1338-1 assume !(0 == ~E_4~0); 124289#L1343-1 assume !(0 == ~E_5~0); 124393#L1348-1 assume !(0 == ~E_6~0); 124700#L1353-1 assume !(0 == ~E_7~0); 124012#L1358-1 assume !(0 == ~E_8~0); 124013#L1363-1 assume !(0 == ~E_9~0); 124307#L1368-1 assume !(0 == ~E_10~0); 122979#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 122980#L1378-1 assume !(0 == ~E_12~0); 123269#L1383-1 assume !(0 == ~E_13~0); 123270#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124018#L607 assume !(1 == ~m_pc~0); 123339#L607-2 is_master_triggered_~__retres1~0#1 := 0; 123340#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124391#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123938#L1560 assume !(0 != activate_threads_~tmp~1#1); 123939#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123163#L626 assume !(1 == ~t1_pc~0); 123164#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123436#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123437#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123606#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 123062#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123063#L645 assume 1 == ~t2_pc~0; 123181#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 123137#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123821#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123822#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 123914#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123915#L664 assume 1 == ~t3_pc~0; 124698#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 122903#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122904#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123567#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 123568#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124601#L683 assume !(1 == ~t4_pc~0); 124134#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 124085#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124086#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124121#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124249#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123864#L702 assume 1 == ~t5_pc~0; 123865#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 123790#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124244#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124556#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 124491#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122951#L721 assume !(1 == ~t6_pc~0); 122926#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 122927#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123090#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 123576#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 123577#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124183#L740 assume 1 == ~t7_pc~0; 123000#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 122812#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 122813#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 122802#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 122803#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 123512#L759 assume !(1 == ~t8_pc~0); 123513#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 123542#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124242#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124243#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 124377#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124672#L778 assume 1 == ~t9_pc~0; 124553#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 122978#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 122918#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 122846#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 122847#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 123176#L797 assume !(1 == ~t10_pc~0); 123177#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 123297#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124445#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 123685#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 123686#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 123977#L816 assume 1 == ~t11_pc~0; 122883#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 122884#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 123646#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 123583#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 123584#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 124111#L835 assume 1 == ~t12_pc~0; 123990#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 123047#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 123070#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 123212#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 123743#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 123744#L854 assume !(1 == ~t13_pc~0); 123381#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 123382#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 123432#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 123088#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 123089#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124486#L1401 assume !(1 == ~M_E~0); 123571#L1401-2 assume !(1 == ~T1_E~0); 123572#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124494#L1411-1 assume !(1 == ~T3_E~0); 124897#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 124896#L1421-1 assume !(1 == ~T5_E~0); 124895#L1426-1 assume !(1 == ~T6_E~0); 124894#L1431-1 assume !(1 == ~T7_E~0); 124893#L1436-1 assume !(1 == ~T8_E~0); 122922#L1441-1 assume !(1 == ~T9_E~0); 124892#L1446-1 assume !(1 == ~T10_E~0); 124891#L1451-1 assume !(1 == ~T11_E~0); 124890#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 124889#L1461-1 assume !(1 == ~T13_E~0); 124888#L1466-1 assume !(1 == ~E_1~0); 124887#L1471-1 assume !(1 == ~E_2~0); 124886#L1476-1 assume !(1 == ~E_3~0); 124885#L1481-1 assume !(1 == ~E_4~0); 124884#L1486-1 assume !(1 == ~E_5~0); 124883#L1491-1 assume !(1 == ~E_6~0); 124882#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 124881#L1501-1 assume !(1 == ~E_8~0); 124880#L1506-1 assume !(1 == ~E_9~0); 124879#L1511-1 assume !(1 == ~E_10~0); 124878#L1516-1 assume !(1 == ~E_11~0); 122798#L1521-1 assume !(1 == ~E_12~0); 122799#L1526-1 assume !(1 == ~E_13~0); 124821#L1531-1 assume { :end_inline_reset_delta_events } true; 124807#L1892-2 [2022-02-21 04:25:06,194 INFO L793 eck$LassoCheckResult]: Loop: 124807#L1892-2 assume !false; 124796#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 124790#L1233 assume !false; 124789#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 124773#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 124758#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 124756#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 124753#L1046 assume !(0 != eval_~tmp~0#1); 124750#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124748#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 124746#L1258-3 assume !(0 == ~M_E~0); 124743#L1258-5 assume !(0 == ~T1_E~0); 124742#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 124688#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 124689#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 124695#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 124696#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 123302#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 123303#L1293-3 assume !(0 == ~T8_E~0); 124434#L1298-3 assume !(0 == ~T9_E~0); 124435#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 124607#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 124433#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 123925#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 123078#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 123079#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 124525#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123222#L1338-3 assume !(0 == ~E_4~0); 123223#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 124348#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 124531#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 124532#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 123881#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 123438#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 123439#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 124201#L1378-3 assume !(0 == ~E_12~0); 124202#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 124387#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124388#L607-42 assume !(1 == ~m_pc~0); 123996#L607-44 is_master_triggered_~__retres1~0#1 := 0; 129734#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129733#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 129732#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 129731#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129730#L626-42 assume !(1 == ~t1_pc~0); 129729#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 129658#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123844#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123845#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123112#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123113#L645-42 assume !(1 == ~t2_pc~0); 124324#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 124325#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124499#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123321#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 122824#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122825#L664-42 assume 1 == ~t3_pc~0; 123635#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 123358#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124635#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124147#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 124148#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124318#L683-42 assume 1 == ~t4_pc~0; 124707#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 124022#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124154#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124596#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124597#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124739#L702-42 assume 1 == ~t5_pc~0; 123907#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 123529#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123828#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124516#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 122840#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122841#L721-42 assume 1 == ~t6_pc~0; 122995#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 123015#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123484#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124678#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 123658#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 123502#L740-42 assume !(1 == ~t7_pc~0); 123237#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 123238#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123784#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123638#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 123639#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 123913#L759-42 assume !(1 == ~t8_pc~0); 123763#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 123693#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 123694#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 123773#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 123774#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123869#L778-42 assume 1 == ~t9_pc~0; 123705#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123707#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 124118#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 124023#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 124024#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 124080#L797-42 assume 1 == ~t10_pc~0; 123243#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 123244#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124254#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 124578#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 124119#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 124120#L816-42 assume 1 == ~t11_pc~0; 128807#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 128804#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128802#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 128800#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 128798#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 128795#L835-42 assume !(1 == ~t12_pc~0); 128793#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 128790#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 128788#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 128786#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 128784#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 127463#L854-42 assume 1 == ~t13_pc~0; 125664#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 125660#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125658#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125656#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 125654#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 125652#L1401-3 assume !(1 == ~M_E~0); 124736#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 125648#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 125646#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 125644#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 125642#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 125640#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 125638#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 125635#L1436-3 assume !(1 == ~T8_E~0); 125634#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 125632#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 125630#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 125628#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 125626#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 125623#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 125621#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 125619#L1476-3 assume !(1 == ~E_3~0); 125617#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 125615#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 125613#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 125610#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 125608#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 125606#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 125604#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 125602#L1516-3 assume !(1 == ~E_11~0); 125600#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 125599#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 125598#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 125311#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 125307#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 125304#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 125301#L1911 assume !(0 == start_simulation_~tmp~3#1); 125298#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 124877#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 124860#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 124858#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 124856#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 124855#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 124854#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 124820#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 124807#L1892-2 [2022-02-21 04:25:06,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:06,195 INFO L85 PathProgramCache]: Analyzing trace with hash -1259435077, now seen corresponding path program 1 times [2022-02-21 04:25:06,195 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:06,195 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789708589] [2022-02-21 04:25:06,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:06,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:06,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:06,233 INFO L290 TraceCheckUtils]: 0: Hoare triple {143662#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,233 INFO L290 TraceCheckUtils]: 1: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,234 INFO L290 TraceCheckUtils]: 2: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,234 INFO L290 TraceCheckUtils]: 3: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,234 INFO L290 TraceCheckUtils]: 4: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,235 INFO L290 TraceCheckUtils]: 5: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,235 INFO L290 TraceCheckUtils]: 6: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,235 INFO L290 TraceCheckUtils]: 7: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,236 INFO L290 TraceCheckUtils]: 8: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,236 INFO L290 TraceCheckUtils]: 9: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,236 INFO L290 TraceCheckUtils]: 10: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,237 INFO L290 TraceCheckUtils]: 11: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,237 INFO L290 TraceCheckUtils]: 12: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,237 INFO L290 TraceCheckUtils]: 13: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,238 INFO L290 TraceCheckUtils]: 14: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,238 INFO L290 TraceCheckUtils]: 15: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,238 INFO L290 TraceCheckUtils]: 16: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,239 INFO L290 TraceCheckUtils]: 17: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,239 INFO L290 TraceCheckUtils]: 18: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,239 INFO L290 TraceCheckUtils]: 19: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~M_E~0); {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,239 INFO L290 TraceCheckUtils]: 20: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T1_E~0); {143664#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:06,240 INFO L290 TraceCheckUtils]: 21: Hoare triple {143664#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T2_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,240 INFO L290 TraceCheckUtils]: 22: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T3_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,240 INFO L290 TraceCheckUtils]: 23: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T4_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,241 INFO L290 TraceCheckUtils]: 24: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T5_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,241 INFO L290 TraceCheckUtils]: 25: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T6_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,241 INFO L290 TraceCheckUtils]: 26: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T7_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,241 INFO L290 TraceCheckUtils]: 27: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T8_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,242 INFO L290 TraceCheckUtils]: 28: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T9_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,242 INFO L290 TraceCheckUtils]: 29: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T10_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,242 INFO L290 TraceCheckUtils]: 30: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T11_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,242 INFO L290 TraceCheckUtils]: 31: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T12_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,243 INFO L290 TraceCheckUtils]: 32: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~T13_E~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,243 INFO L290 TraceCheckUtils]: 33: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~E_1~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,243 INFO L290 TraceCheckUtils]: 34: Hoare triple {143665#(not (= ~E_3~0 0))} assume !(0 == ~E_2~0); {143665#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:06,244 INFO L290 TraceCheckUtils]: 35: Hoare triple {143665#(not (= ~E_3~0 0))} assume 0 == ~E_3~0;~E_3~0 := 1; {143663#false} is VALID [2022-02-21 04:25:06,244 INFO L290 TraceCheckUtils]: 36: Hoare triple {143663#false} assume !(0 == ~E_4~0); {143663#false} is VALID [2022-02-21 04:25:06,244 INFO L290 TraceCheckUtils]: 37: Hoare triple {143663#false} assume !(0 == ~E_5~0); {143663#false} is VALID [2022-02-21 04:25:06,244 INFO L290 TraceCheckUtils]: 38: Hoare triple {143663#false} assume !(0 == ~E_6~0); {143663#false} is VALID [2022-02-21 04:25:06,244 INFO L290 TraceCheckUtils]: 39: Hoare triple {143663#false} assume !(0 == ~E_7~0); {143663#false} is VALID [2022-02-21 04:25:06,244 INFO L290 TraceCheckUtils]: 40: Hoare triple {143663#false} assume !(0 == ~E_8~0); {143663#false} is VALID [2022-02-21 04:25:06,244 INFO L290 TraceCheckUtils]: 41: Hoare triple {143663#false} assume !(0 == ~E_9~0); {143663#false} is VALID [2022-02-21 04:25:06,244 INFO L290 TraceCheckUtils]: 42: Hoare triple {143663#false} assume !(0 == ~E_10~0); {143663#false} is VALID [2022-02-21 04:25:06,244 INFO L290 TraceCheckUtils]: 43: Hoare triple {143663#false} assume 0 == ~E_11~0;~E_11~0 := 1; {143663#false} is VALID [2022-02-21 04:25:06,245 INFO L290 TraceCheckUtils]: 44: Hoare triple {143663#false} assume !(0 == ~E_12~0); {143663#false} is VALID [2022-02-21 04:25:06,245 INFO L290 TraceCheckUtils]: 45: Hoare triple {143663#false} assume !(0 == ~E_13~0); {143663#false} is VALID [2022-02-21 04:25:06,245 INFO L290 TraceCheckUtils]: 46: Hoare triple {143663#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {143663#false} is VALID [2022-02-21 04:25:06,245 INFO L290 TraceCheckUtils]: 47: Hoare triple {143663#false} assume !(1 == ~m_pc~0); {143663#false} is VALID [2022-02-21 04:25:06,245 INFO L290 TraceCheckUtils]: 48: Hoare triple {143663#false} is_master_triggered_~__retres1~0#1 := 0; {143663#false} is VALID [2022-02-21 04:25:06,245 INFO L290 TraceCheckUtils]: 49: Hoare triple {143663#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {143663#false} is VALID [2022-02-21 04:25:06,245 INFO L290 TraceCheckUtils]: 50: Hoare triple {143663#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {143663#false} is VALID [2022-02-21 04:25:06,245 INFO L290 TraceCheckUtils]: 51: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp~1#1); {143663#false} is VALID [2022-02-21 04:25:06,245 INFO L290 TraceCheckUtils]: 52: Hoare triple {143663#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {143663#false} is VALID [2022-02-21 04:25:06,246 INFO L290 TraceCheckUtils]: 53: Hoare triple {143663#false} assume !(1 == ~t1_pc~0); {143663#false} is VALID [2022-02-21 04:25:06,246 INFO L290 TraceCheckUtils]: 54: Hoare triple {143663#false} is_transmit1_triggered_~__retres1~1#1 := 0; {143663#false} is VALID [2022-02-21 04:25:06,246 INFO L290 TraceCheckUtils]: 55: Hoare triple {143663#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {143663#false} is VALID [2022-02-21 04:25:06,246 INFO L290 TraceCheckUtils]: 56: Hoare triple {143663#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {143663#false} is VALID [2022-02-21 04:25:06,246 INFO L290 TraceCheckUtils]: 57: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___0~0#1); {143663#false} is VALID [2022-02-21 04:25:06,246 INFO L290 TraceCheckUtils]: 58: Hoare triple {143663#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {143663#false} is VALID [2022-02-21 04:25:06,246 INFO L290 TraceCheckUtils]: 59: Hoare triple {143663#false} assume 1 == ~t2_pc~0; {143663#false} is VALID [2022-02-21 04:25:06,246 INFO L290 TraceCheckUtils]: 60: Hoare triple {143663#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {143663#false} is VALID [2022-02-21 04:25:06,246 INFO L290 TraceCheckUtils]: 61: Hoare triple {143663#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {143663#false} is VALID [2022-02-21 04:25:06,247 INFO L290 TraceCheckUtils]: 62: Hoare triple {143663#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {143663#false} is VALID [2022-02-21 04:25:06,247 INFO L290 TraceCheckUtils]: 63: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___1~0#1); {143663#false} is VALID [2022-02-21 04:25:06,247 INFO L290 TraceCheckUtils]: 64: Hoare triple {143663#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {143663#false} is VALID [2022-02-21 04:25:06,247 INFO L290 TraceCheckUtils]: 65: Hoare triple {143663#false} assume 1 == ~t3_pc~0; {143663#false} is VALID [2022-02-21 04:25:06,247 INFO L290 TraceCheckUtils]: 66: Hoare triple {143663#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {143663#false} is VALID [2022-02-21 04:25:06,247 INFO L290 TraceCheckUtils]: 67: Hoare triple {143663#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {143663#false} is VALID [2022-02-21 04:25:06,247 INFO L290 TraceCheckUtils]: 68: Hoare triple {143663#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {143663#false} is VALID [2022-02-21 04:25:06,247 INFO L290 TraceCheckUtils]: 69: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___2~0#1); {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 70: Hoare triple {143663#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 71: Hoare triple {143663#false} assume !(1 == ~t4_pc~0); {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 72: Hoare triple {143663#false} is_transmit4_triggered_~__retres1~4#1 := 0; {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 73: Hoare triple {143663#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 74: Hoare triple {143663#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 75: Hoare triple {143663#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 76: Hoare triple {143663#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 77: Hoare triple {143663#false} assume 1 == ~t5_pc~0; {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 78: Hoare triple {143663#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {143663#false} is VALID [2022-02-21 04:25:06,248 INFO L290 TraceCheckUtils]: 79: Hoare triple {143663#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {143663#false} is VALID [2022-02-21 04:25:06,249 INFO L290 TraceCheckUtils]: 80: Hoare triple {143663#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {143663#false} is VALID [2022-02-21 04:25:06,249 INFO L290 TraceCheckUtils]: 81: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___4~0#1); {143663#false} is VALID [2022-02-21 04:25:06,249 INFO L290 TraceCheckUtils]: 82: Hoare triple {143663#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {143663#false} is VALID [2022-02-21 04:25:06,249 INFO L290 TraceCheckUtils]: 83: Hoare triple {143663#false} assume !(1 == ~t6_pc~0); {143663#false} is VALID [2022-02-21 04:25:06,249 INFO L290 TraceCheckUtils]: 84: Hoare triple {143663#false} is_transmit6_triggered_~__retres1~6#1 := 0; {143663#false} is VALID [2022-02-21 04:25:06,249 INFO L290 TraceCheckUtils]: 85: Hoare triple {143663#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {143663#false} is VALID [2022-02-21 04:25:06,249 INFO L290 TraceCheckUtils]: 86: Hoare triple {143663#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {143663#false} is VALID [2022-02-21 04:25:06,249 INFO L290 TraceCheckUtils]: 87: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___5~0#1); {143663#false} is VALID [2022-02-21 04:25:06,249 INFO L290 TraceCheckUtils]: 88: Hoare triple {143663#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {143663#false} is VALID [2022-02-21 04:25:06,250 INFO L290 TraceCheckUtils]: 89: Hoare triple {143663#false} assume 1 == ~t7_pc~0; {143663#false} is VALID [2022-02-21 04:25:06,250 INFO L290 TraceCheckUtils]: 90: Hoare triple {143663#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {143663#false} is VALID [2022-02-21 04:25:06,250 INFO L290 TraceCheckUtils]: 91: Hoare triple {143663#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {143663#false} is VALID [2022-02-21 04:25:06,250 INFO L290 TraceCheckUtils]: 92: Hoare triple {143663#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {143663#false} is VALID [2022-02-21 04:25:06,250 INFO L290 TraceCheckUtils]: 93: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___6~0#1); {143663#false} is VALID [2022-02-21 04:25:06,250 INFO L290 TraceCheckUtils]: 94: Hoare triple {143663#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {143663#false} is VALID [2022-02-21 04:25:06,250 INFO L290 TraceCheckUtils]: 95: Hoare triple {143663#false} assume !(1 == ~t8_pc~0); {143663#false} is VALID [2022-02-21 04:25:06,250 INFO L290 TraceCheckUtils]: 96: Hoare triple {143663#false} is_transmit8_triggered_~__retres1~8#1 := 0; {143663#false} is VALID [2022-02-21 04:25:06,250 INFO L290 TraceCheckUtils]: 97: Hoare triple {143663#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {143663#false} is VALID [2022-02-21 04:25:06,251 INFO L290 TraceCheckUtils]: 98: Hoare triple {143663#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {143663#false} is VALID [2022-02-21 04:25:06,251 INFO L290 TraceCheckUtils]: 99: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___7~0#1); {143663#false} is VALID [2022-02-21 04:25:06,251 INFO L290 TraceCheckUtils]: 100: Hoare triple {143663#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {143663#false} is VALID [2022-02-21 04:25:06,251 INFO L290 TraceCheckUtils]: 101: Hoare triple {143663#false} assume 1 == ~t9_pc~0; {143663#false} is VALID [2022-02-21 04:25:06,251 INFO L290 TraceCheckUtils]: 102: Hoare triple {143663#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {143663#false} is VALID [2022-02-21 04:25:06,251 INFO L290 TraceCheckUtils]: 103: Hoare triple {143663#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {143663#false} is VALID [2022-02-21 04:25:06,251 INFO L290 TraceCheckUtils]: 104: Hoare triple {143663#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {143663#false} is VALID [2022-02-21 04:25:06,251 INFO L290 TraceCheckUtils]: 105: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___8~0#1); {143663#false} is VALID [2022-02-21 04:25:06,251 INFO L290 TraceCheckUtils]: 106: Hoare triple {143663#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 107: Hoare triple {143663#false} assume !(1 == ~t10_pc~0); {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 108: Hoare triple {143663#false} is_transmit10_triggered_~__retres1~10#1 := 0; {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 109: Hoare triple {143663#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 110: Hoare triple {143663#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 111: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___9~0#1); {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 112: Hoare triple {143663#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 113: Hoare triple {143663#false} assume 1 == ~t11_pc~0; {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 114: Hoare triple {143663#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 115: Hoare triple {143663#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {143663#false} is VALID [2022-02-21 04:25:06,252 INFO L290 TraceCheckUtils]: 116: Hoare triple {143663#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {143663#false} is VALID [2022-02-21 04:25:06,253 INFO L290 TraceCheckUtils]: 117: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___10~0#1); {143663#false} is VALID [2022-02-21 04:25:06,253 INFO L290 TraceCheckUtils]: 118: Hoare triple {143663#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {143663#false} is VALID [2022-02-21 04:25:06,253 INFO L290 TraceCheckUtils]: 119: Hoare triple {143663#false} assume 1 == ~t12_pc~0; {143663#false} is VALID [2022-02-21 04:25:06,253 INFO L290 TraceCheckUtils]: 120: Hoare triple {143663#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {143663#false} is VALID [2022-02-21 04:25:06,253 INFO L290 TraceCheckUtils]: 121: Hoare triple {143663#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {143663#false} is VALID [2022-02-21 04:25:06,253 INFO L290 TraceCheckUtils]: 122: Hoare triple {143663#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {143663#false} is VALID [2022-02-21 04:25:06,253 INFO L290 TraceCheckUtils]: 123: Hoare triple {143663#false} assume !(0 != activate_threads_~tmp___11~0#1); {143663#false} is VALID [2022-02-21 04:25:06,253 INFO L290 TraceCheckUtils]: 124: Hoare triple {143663#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {143663#false} is VALID [2022-02-21 04:25:06,253 INFO L290 TraceCheckUtils]: 125: Hoare triple {143663#false} assume !(1 == ~t13_pc~0); {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 126: Hoare triple {143663#false} is_transmit13_triggered_~__retres1~13#1 := 0; {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 127: Hoare triple {143663#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 128: Hoare triple {143663#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 129: Hoare triple {143663#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 130: Hoare triple {143663#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 131: Hoare triple {143663#false} assume !(1 == ~M_E~0); {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 132: Hoare triple {143663#false} assume !(1 == ~T1_E~0); {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 133: Hoare triple {143663#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 134: Hoare triple {143663#false} assume !(1 == ~T3_E~0); {143663#false} is VALID [2022-02-21 04:25:06,254 INFO L290 TraceCheckUtils]: 135: Hoare triple {143663#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {143663#false} is VALID [2022-02-21 04:25:06,255 INFO L290 TraceCheckUtils]: 136: Hoare triple {143663#false} assume !(1 == ~T5_E~0); {143663#false} is VALID [2022-02-21 04:25:06,255 INFO L290 TraceCheckUtils]: 137: Hoare triple {143663#false} assume !(1 == ~T6_E~0); {143663#false} is VALID [2022-02-21 04:25:06,255 INFO L290 TraceCheckUtils]: 138: Hoare triple {143663#false} assume !(1 == ~T7_E~0); {143663#false} is VALID [2022-02-21 04:25:06,255 INFO L290 TraceCheckUtils]: 139: Hoare triple {143663#false} assume !(1 == ~T8_E~0); {143663#false} is VALID [2022-02-21 04:25:06,255 INFO L290 TraceCheckUtils]: 140: Hoare triple {143663#false} assume !(1 == ~T9_E~0); {143663#false} is VALID [2022-02-21 04:25:06,255 INFO L290 TraceCheckUtils]: 141: Hoare triple {143663#false} assume !(1 == ~T10_E~0); {143663#false} is VALID [2022-02-21 04:25:06,255 INFO L290 TraceCheckUtils]: 142: Hoare triple {143663#false} assume !(1 == ~T11_E~0); {143663#false} is VALID [2022-02-21 04:25:06,255 INFO L290 TraceCheckUtils]: 143: Hoare triple {143663#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {143663#false} is VALID [2022-02-21 04:25:06,255 INFO L290 TraceCheckUtils]: 144: Hoare triple {143663#false} assume !(1 == ~T13_E~0); {143663#false} is VALID [2022-02-21 04:25:06,256 INFO L290 TraceCheckUtils]: 145: Hoare triple {143663#false} assume !(1 == ~E_1~0); {143663#false} is VALID [2022-02-21 04:25:06,256 INFO L290 TraceCheckUtils]: 146: Hoare triple {143663#false} assume !(1 == ~E_2~0); {143663#false} is VALID [2022-02-21 04:25:06,256 INFO L290 TraceCheckUtils]: 147: Hoare triple {143663#false} assume !(1 == ~E_3~0); {143663#false} is VALID [2022-02-21 04:25:06,256 INFO L290 TraceCheckUtils]: 148: Hoare triple {143663#false} assume !(1 == ~E_4~0); {143663#false} is VALID [2022-02-21 04:25:06,256 INFO L290 TraceCheckUtils]: 149: Hoare triple {143663#false} assume !(1 == ~E_5~0); {143663#false} is VALID [2022-02-21 04:25:06,256 INFO L290 TraceCheckUtils]: 150: Hoare triple {143663#false} assume !(1 == ~E_6~0); {143663#false} is VALID [2022-02-21 04:25:06,256 INFO L290 TraceCheckUtils]: 151: Hoare triple {143663#false} assume 1 == ~E_7~0;~E_7~0 := 2; {143663#false} is VALID [2022-02-21 04:25:06,256 INFO L290 TraceCheckUtils]: 152: Hoare triple {143663#false} assume !(1 == ~E_8~0); {143663#false} is VALID [2022-02-21 04:25:06,256 INFO L290 TraceCheckUtils]: 153: Hoare triple {143663#false} assume !(1 == ~E_9~0); {143663#false} is VALID [2022-02-21 04:25:06,257 INFO L290 TraceCheckUtils]: 154: Hoare triple {143663#false} assume !(1 == ~E_10~0); {143663#false} is VALID [2022-02-21 04:25:06,257 INFO L290 TraceCheckUtils]: 155: Hoare triple {143663#false} assume !(1 == ~E_11~0); {143663#false} is VALID [2022-02-21 04:25:06,257 INFO L290 TraceCheckUtils]: 156: Hoare triple {143663#false} assume !(1 == ~E_12~0); {143663#false} is VALID [2022-02-21 04:25:06,257 INFO L290 TraceCheckUtils]: 157: Hoare triple {143663#false} assume !(1 == ~E_13~0); {143663#false} is VALID [2022-02-21 04:25:06,257 INFO L290 TraceCheckUtils]: 158: Hoare triple {143663#false} assume { :end_inline_reset_delta_events } true; {143663#false} is VALID [2022-02-21 04:25:06,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:06,258 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:06,258 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789708589] [2022-02-21 04:25:06,258 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789708589] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:06,258 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:06,258 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:06,258 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329559607] [2022-02-21 04:25:06,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:06,259 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:06,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:06,259 INFO L85 PathProgramCache]: Analyzing trace with hash -1075950069, now seen corresponding path program 1 times [2022-02-21 04:25:06,259 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:06,259 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306221395] [2022-02-21 04:25:06,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:06,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:06,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:06,292 INFO L290 TraceCheckUtils]: 0: Hoare triple {143666#true} assume !false; {143666#true} is VALID [2022-02-21 04:25:06,292 INFO L290 TraceCheckUtils]: 1: Hoare triple {143666#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {143666#true} is VALID [2022-02-21 04:25:06,292 INFO L290 TraceCheckUtils]: 2: Hoare triple {143666#true} assume !false; {143666#true} is VALID [2022-02-21 04:25:06,292 INFO L290 TraceCheckUtils]: 3: Hoare triple {143666#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {143666#true} is VALID [2022-02-21 04:25:06,292 INFO L290 TraceCheckUtils]: 4: Hoare triple {143666#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {143666#true} is VALID [2022-02-21 04:25:06,292 INFO L290 TraceCheckUtils]: 5: Hoare triple {143666#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {143666#true} is VALID [2022-02-21 04:25:06,292 INFO L290 TraceCheckUtils]: 6: Hoare triple {143666#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {143666#true} is VALID [2022-02-21 04:25:06,292 INFO L290 TraceCheckUtils]: 7: Hoare triple {143666#true} assume !(0 != eval_~tmp~0#1); {143666#true} is VALID [2022-02-21 04:25:06,293 INFO L290 TraceCheckUtils]: 8: Hoare triple {143666#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {143666#true} is VALID [2022-02-21 04:25:06,293 INFO L290 TraceCheckUtils]: 9: Hoare triple {143666#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {143666#true} is VALID [2022-02-21 04:25:06,293 INFO L290 TraceCheckUtils]: 10: Hoare triple {143666#true} assume !(0 == ~M_E~0); {143666#true} is VALID [2022-02-21 04:25:06,293 INFO L290 TraceCheckUtils]: 11: Hoare triple {143666#true} assume !(0 == ~T1_E~0); {143666#true} is VALID [2022-02-21 04:25:06,293 INFO L290 TraceCheckUtils]: 12: Hoare triple {143666#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,293 INFO L290 TraceCheckUtils]: 13: Hoare triple {143666#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,293 INFO L290 TraceCheckUtils]: 14: Hoare triple {143666#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,293 INFO L290 TraceCheckUtils]: 15: Hoare triple {143666#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,293 INFO L290 TraceCheckUtils]: 16: Hoare triple {143666#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,294 INFO L290 TraceCheckUtils]: 17: Hoare triple {143666#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,294 INFO L290 TraceCheckUtils]: 18: Hoare triple {143666#true} assume !(0 == ~T8_E~0); {143666#true} is VALID [2022-02-21 04:25:06,294 INFO L290 TraceCheckUtils]: 19: Hoare triple {143666#true} assume !(0 == ~T9_E~0); {143666#true} is VALID [2022-02-21 04:25:06,294 INFO L290 TraceCheckUtils]: 20: Hoare triple {143666#true} assume 0 == ~T10_E~0;~T10_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,294 INFO L290 TraceCheckUtils]: 21: Hoare triple {143666#true} assume 0 == ~T11_E~0;~T11_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,294 INFO L290 TraceCheckUtils]: 22: Hoare triple {143666#true} assume 0 == ~T12_E~0;~T12_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,294 INFO L290 TraceCheckUtils]: 23: Hoare triple {143666#true} assume 0 == ~T13_E~0;~T13_E~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,294 INFO L290 TraceCheckUtils]: 24: Hoare triple {143666#true} assume 0 == ~E_1~0;~E_1~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,294 INFO L290 TraceCheckUtils]: 25: Hoare triple {143666#true} assume 0 == ~E_2~0;~E_2~0 := 1; {143666#true} is VALID [2022-02-21 04:25:06,295 INFO L290 TraceCheckUtils]: 26: Hoare triple {143666#true} assume 0 == ~E_3~0;~E_3~0 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,295 INFO L290 TraceCheckUtils]: 27: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(0 == ~E_4~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,295 INFO L290 TraceCheckUtils]: 28: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,296 INFO L290 TraceCheckUtils]: 29: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,296 INFO L290 TraceCheckUtils]: 30: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,296 INFO L290 TraceCheckUtils]: 31: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,296 INFO L290 TraceCheckUtils]: 32: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,297 INFO L290 TraceCheckUtils]: 33: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,297 INFO L290 TraceCheckUtils]: 34: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,297 INFO L290 TraceCheckUtils]: 35: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(0 == ~E_12~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,298 INFO L290 TraceCheckUtils]: 36: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,298 INFO L290 TraceCheckUtils]: 37: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,298 INFO L290 TraceCheckUtils]: 38: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(1 == ~m_pc~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,299 INFO L290 TraceCheckUtils]: 39: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,299 INFO L290 TraceCheckUtils]: 40: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,299 INFO L290 TraceCheckUtils]: 41: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,300 INFO L290 TraceCheckUtils]: 42: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,300 INFO L290 TraceCheckUtils]: 43: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,300 INFO L290 TraceCheckUtils]: 44: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(1 == ~t1_pc~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,300 INFO L290 TraceCheckUtils]: 45: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,301 INFO L290 TraceCheckUtils]: 46: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,301 INFO L290 TraceCheckUtils]: 47: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,301 INFO L290 TraceCheckUtils]: 48: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,302 INFO L290 TraceCheckUtils]: 49: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,302 INFO L290 TraceCheckUtils]: 50: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(1 == ~t2_pc~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,302 INFO L290 TraceCheckUtils]: 51: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,303 INFO L290 TraceCheckUtils]: 52: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,303 INFO L290 TraceCheckUtils]: 53: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,303 INFO L290 TraceCheckUtils]: 54: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,303 INFO L290 TraceCheckUtils]: 55: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,304 INFO L290 TraceCheckUtils]: 56: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~t3_pc~0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,304 INFO L290 TraceCheckUtils]: 57: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,304 INFO L290 TraceCheckUtils]: 58: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,305 INFO L290 TraceCheckUtils]: 59: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,305 INFO L290 TraceCheckUtils]: 60: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,305 INFO L290 TraceCheckUtils]: 61: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,306 INFO L290 TraceCheckUtils]: 62: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~t4_pc~0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,306 INFO L290 TraceCheckUtils]: 63: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,306 INFO L290 TraceCheckUtils]: 64: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,306 INFO L290 TraceCheckUtils]: 65: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,307 INFO L290 TraceCheckUtils]: 66: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,307 INFO L290 TraceCheckUtils]: 67: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,307 INFO L290 TraceCheckUtils]: 68: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~t5_pc~0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,308 INFO L290 TraceCheckUtils]: 69: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,308 INFO L290 TraceCheckUtils]: 70: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,308 INFO L290 TraceCheckUtils]: 71: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,309 INFO L290 TraceCheckUtils]: 72: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,309 INFO L290 TraceCheckUtils]: 73: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,309 INFO L290 TraceCheckUtils]: 74: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~t6_pc~0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,309 INFO L290 TraceCheckUtils]: 75: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,310 INFO L290 TraceCheckUtils]: 76: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,310 INFO L290 TraceCheckUtils]: 77: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,310 INFO L290 TraceCheckUtils]: 78: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,311 INFO L290 TraceCheckUtils]: 79: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,311 INFO L290 TraceCheckUtils]: 80: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(1 == ~t7_pc~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,311 INFO L290 TraceCheckUtils]: 81: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,312 INFO L290 TraceCheckUtils]: 82: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,312 INFO L290 TraceCheckUtils]: 83: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,312 INFO L290 TraceCheckUtils]: 84: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,313 INFO L290 TraceCheckUtils]: 85: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,313 INFO L290 TraceCheckUtils]: 86: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(1 == ~t8_pc~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,313 INFO L290 TraceCheckUtils]: 87: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,314 INFO L290 TraceCheckUtils]: 88: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,314 INFO L290 TraceCheckUtils]: 89: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,314 INFO L290 TraceCheckUtils]: 90: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,314 INFO L290 TraceCheckUtils]: 91: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,315 INFO L290 TraceCheckUtils]: 92: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~t9_pc~0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,315 INFO L290 TraceCheckUtils]: 93: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,315 INFO L290 TraceCheckUtils]: 94: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,316 INFO L290 TraceCheckUtils]: 95: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,316 INFO L290 TraceCheckUtils]: 96: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,316 INFO L290 TraceCheckUtils]: 97: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,317 INFO L290 TraceCheckUtils]: 98: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~t10_pc~0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,317 INFO L290 TraceCheckUtils]: 99: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,317 INFO L290 TraceCheckUtils]: 100: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,318 INFO L290 TraceCheckUtils]: 101: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,318 INFO L290 TraceCheckUtils]: 102: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,319 INFO L290 TraceCheckUtils]: 103: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,319 INFO L290 TraceCheckUtils]: 104: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~t11_pc~0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,319 INFO L290 TraceCheckUtils]: 105: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,320 INFO L290 TraceCheckUtils]: 106: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,320 INFO L290 TraceCheckUtils]: 107: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,320 INFO L290 TraceCheckUtils]: 108: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,321 INFO L290 TraceCheckUtils]: 109: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,321 INFO L290 TraceCheckUtils]: 110: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(1 == ~t12_pc~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,321 INFO L290 TraceCheckUtils]: 111: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,322 INFO L290 TraceCheckUtils]: 112: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,322 INFO L290 TraceCheckUtils]: 113: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,323 INFO L290 TraceCheckUtils]: 114: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,323 INFO L290 TraceCheckUtils]: 115: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,323 INFO L290 TraceCheckUtils]: 116: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~t13_pc~0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,324 INFO L290 TraceCheckUtils]: 117: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,324 INFO L290 TraceCheckUtils]: 118: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,324 INFO L290 TraceCheckUtils]: 119: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,325 INFO L290 TraceCheckUtils]: 120: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,325 INFO L290 TraceCheckUtils]: 121: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,325 INFO L290 TraceCheckUtils]: 122: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(1 == ~M_E~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,326 INFO L290 TraceCheckUtils]: 123: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,326 INFO L290 TraceCheckUtils]: 124: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,326 INFO L290 TraceCheckUtils]: 125: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,327 INFO L290 TraceCheckUtils]: 126: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,327 INFO L290 TraceCheckUtils]: 127: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,328 INFO L290 TraceCheckUtils]: 128: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,328 INFO L290 TraceCheckUtils]: 129: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T7_E~0;~T7_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,328 INFO L290 TraceCheckUtils]: 130: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(1 == ~T8_E~0); {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,329 INFO L290 TraceCheckUtils]: 131: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T9_E~0;~T9_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,329 INFO L290 TraceCheckUtils]: 132: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T10_E~0;~T10_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,329 INFO L290 TraceCheckUtils]: 133: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T11_E~0;~T11_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,330 INFO L290 TraceCheckUtils]: 134: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T12_E~0;~T12_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,330 INFO L290 TraceCheckUtils]: 135: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~T13_E~0;~T13_E~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,330 INFO L290 TraceCheckUtils]: 136: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,331 INFO L290 TraceCheckUtils]: 137: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {143668#(= (+ (- 1) ~E_3~0) 0)} is VALID [2022-02-21 04:25:06,332 INFO L290 TraceCheckUtils]: 138: Hoare triple {143668#(= (+ (- 1) ~E_3~0) 0)} assume !(1 == ~E_3~0); {143667#false} is VALID [2022-02-21 04:25:06,332 INFO L290 TraceCheckUtils]: 139: Hoare triple {143667#false} assume 1 == ~E_4~0;~E_4~0 := 2; {143667#false} is VALID [2022-02-21 04:25:06,332 INFO L290 TraceCheckUtils]: 140: Hoare triple {143667#false} assume 1 == ~E_5~0;~E_5~0 := 2; {143667#false} is VALID [2022-02-21 04:25:06,332 INFO L290 TraceCheckUtils]: 141: Hoare triple {143667#false} assume 1 == ~E_6~0;~E_6~0 := 2; {143667#false} is VALID [2022-02-21 04:25:06,333 INFO L290 TraceCheckUtils]: 142: Hoare triple {143667#false} assume 1 == ~E_7~0;~E_7~0 := 2; {143667#false} is VALID [2022-02-21 04:25:06,337 INFO L290 TraceCheckUtils]: 143: Hoare triple {143667#false} assume 1 == ~E_8~0;~E_8~0 := 2; {143667#false} is VALID [2022-02-21 04:25:06,337 INFO L290 TraceCheckUtils]: 144: Hoare triple {143667#false} assume 1 == ~E_9~0;~E_9~0 := 2; {143667#false} is VALID [2022-02-21 04:25:06,338 INFO L290 TraceCheckUtils]: 145: Hoare triple {143667#false} assume 1 == ~E_10~0;~E_10~0 := 2; {143667#false} is VALID [2022-02-21 04:25:06,339 INFO L290 TraceCheckUtils]: 146: Hoare triple {143667#false} assume !(1 == ~E_11~0); {143667#false} is VALID [2022-02-21 04:25:06,339 INFO L290 TraceCheckUtils]: 147: Hoare triple {143667#false} assume 1 == ~E_12~0;~E_12~0 := 2; {143667#false} is VALID [2022-02-21 04:25:06,340 INFO L290 TraceCheckUtils]: 148: Hoare triple {143667#false} assume 1 == ~E_13~0;~E_13~0 := 2; {143667#false} is VALID [2022-02-21 04:25:06,340 INFO L290 TraceCheckUtils]: 149: Hoare triple {143667#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {143667#false} is VALID [2022-02-21 04:25:06,340 INFO L290 TraceCheckUtils]: 150: Hoare triple {143667#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {143667#false} is VALID [2022-02-21 04:25:06,340 INFO L290 TraceCheckUtils]: 151: Hoare triple {143667#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 152: Hoare triple {143667#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 153: Hoare triple {143667#false} assume !(0 == start_simulation_~tmp~3#1); {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 154: Hoare triple {143667#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 155: Hoare triple {143667#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 156: Hoare triple {143667#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 157: Hoare triple {143667#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 158: Hoare triple {143667#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 159: Hoare triple {143667#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 160: Hoare triple {143667#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {143667#false} is VALID [2022-02-21 04:25:06,341 INFO L290 TraceCheckUtils]: 161: Hoare triple {143667#false} assume !(0 != start_simulation_~tmp___0~1#1); {143667#false} is VALID [2022-02-21 04:25:06,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:06,343 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:06,343 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1306221395] [2022-02-21 04:25:06,343 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1306221395] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:06,343 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:06,343 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:06,343 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017994772] [2022-02-21 04:25:06,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:06,344 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:06,344 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:06,344 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:25:06,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:25:06,345 INFO L87 Difference]: Start difference. First operand 6962 states and 10199 transitions. cyclomatic complexity: 3239 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:14,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:14,352 INFO L93 Difference]: Finished difference Result 13360 states and 19568 transitions. [2022-02-21 04:25:14,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:25:14,352 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:14,433 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:14,434 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13360 states and 19568 transitions. [2022-02-21 04:25:19,068 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2022-02-21 04:25:23,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13360 states to 13360 states and 19568 transitions. [2022-02-21 04:25:23,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13360 [2022-02-21 04:25:23,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13360 [2022-02-21 04:25:23,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13360 states and 19568 transitions. [2022-02-21 04:25:23,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:23,208 INFO L681 BuchiCegarLoop]: Abstraction has 13360 states and 19568 transitions. [2022-02-21 04:25:23,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13360 states and 19568 transitions. [2022-02-21 04:25:23,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13360 to 13356. [2022-02-21 04:25:23,363 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:23,377 INFO L82 GeneralOperation]: Start isEquivalent. First operand 13360 states and 19568 transitions. Second operand has 13356 states, 13356 states have (on average 1.4648098233003894) internal successors, (19564), 13355 states have internal predecessors, (19564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:23,393 INFO L74 IsIncluded]: Start isIncluded. First operand 13360 states and 19568 transitions. Second operand has 13356 states, 13356 states have (on average 1.4648098233003894) internal successors, (19564), 13355 states have internal predecessors, (19564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:23,407 INFO L87 Difference]: Start difference. First operand 13360 states and 19568 transitions. Second operand has 13356 states, 13356 states have (on average 1.4648098233003894) internal successors, (19564), 13355 states have internal predecessors, (19564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:27,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:27,630 INFO L93 Difference]: Finished difference Result 13360 states and 19568 transitions. [2022-02-21 04:25:27,630 INFO L276 IsEmpty]: Start isEmpty. Operand 13360 states and 19568 transitions. [2022-02-21 04:25:27,643 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:27,643 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:27,662 INFO L74 IsIncluded]: Start isIncluded. First operand has 13356 states, 13356 states have (on average 1.4648098233003894) internal successors, (19564), 13355 states have internal predecessors, (19564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 13360 states and 19568 transitions. [2022-02-21 04:25:27,679 INFO L87 Difference]: Start difference. First operand has 13356 states, 13356 states have (on average 1.4648098233003894) internal successors, (19564), 13355 states have internal predecessors, (19564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 13360 states and 19568 transitions.