./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:36,275 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:36,285 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:36,332 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:36,333 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:36,336 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:36,337 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:36,340 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:36,342 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:36,347 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:36,348 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:36,349 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:36,350 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:36,352 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:36,353 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:36,357 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:36,359 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:36,360 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:36,361 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:36,363 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:36,367 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:36,369 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:36,370 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:36,371 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:36,375 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:36,375 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:36,375 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:36,377 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:36,377 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:36,378 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:36,378 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:36,379 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:36,381 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:36,382 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:36,383 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:36,383 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:36,384 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:36,384 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:36,384 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:36,385 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:36,386 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:36,386 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:36,432 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:36,433 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:36,433 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:36,433 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:36,434 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:36,434 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:36,434 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:36,434 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:36,435 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:36,435 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:36,435 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:36,435 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:36,435 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:36,435 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:36,436 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:36,436 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:36,436 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:36,436 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:36,436 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:36,436 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:36,436 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:36,438 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:36,438 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:36,438 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:36,438 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:36,438 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:36,439 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:36,439 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:36,439 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:36,439 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:36,439 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:36,441 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:36,441 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2022-02-21 04:24:36,627 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:36,649 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:36,651 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:36,652 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:36,652 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:36,653 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.16.cil.c [2022-02-21 04:24:36,731 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ecb756887/a05a930b88764dc69a5e108d1ed98af3/FLAGec61cf87f [2022-02-21 04:24:37,113 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:37,114 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c [2022-02-21 04:24:37,122 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ecb756887/a05a930b88764dc69a5e108d1ed98af3/FLAGec61cf87f [2022-02-21 04:24:37,132 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ecb756887/a05a930b88764dc69a5e108d1ed98af3 [2022-02-21 04:24:37,134 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:37,135 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:37,136 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:37,136 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:37,138 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:37,139 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,140 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@49f89607 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37, skipping insertion in model container [2022-02-21 04:24:37,140 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,144 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:37,180 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:37,294 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2022-02-21 04:24:37,436 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:37,443 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:37,455 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2022-02-21 04:24:37,503 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:37,532 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:37,532 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37 WrapperNode [2022-02-21 04:24:37,533 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:37,534 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:37,534 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:37,534 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:37,539 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,561 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,654 INFO L137 Inliner]: procedures = 56, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4715 [2022-02-21 04:24:37,654 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:37,655 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:37,655 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:37,655 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:37,661 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,661 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,673 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,673 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,716 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,742 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,747 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,761 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:37,765 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:37,765 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:37,765 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:37,766 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (1/1) ... [2022-02-21 04:24:37,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:37,778 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:37,800 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:37,819 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:37,830 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:37,830 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:37,830 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:37,830 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:37,908 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:37,909 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:39,687 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:39,706 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:39,707 INFO L299 CfgBuilder]: Removed 18 assume(true) statements. [2022-02-21 04:24:39,709 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:39 BoogieIcfgContainer [2022-02-21 04:24:39,709 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:39,710 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:39,710 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:39,712 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:39,713 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:39,713 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:37" (1/3) ... [2022-02-21 04:24:39,714 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@44460d34 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:39, skipping insertion in model container [2022-02-21 04:24:39,714 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:39,715 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:37" (2/3) ... [2022-02-21 04:24:39,715 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@44460d34 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:39, skipping insertion in model container [2022-02-21 04:24:39,715 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:39,715 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:39" (3/3) ... [2022-02-21 04:24:39,716 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.16.cil.c [2022-02-21 04:24:39,745 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:39,745 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:39,745 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:39,745 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:39,746 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:39,746 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:39,746 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:39,746 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:39,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2022-02-21 04:24:40,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:40,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:40,134 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:40,134 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:40,134 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:40,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2022-02-21 04:24:40,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:40,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:40,323 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:40,324 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:40,330 INFO L791 eck$LassoCheckResult]: Stem: 490#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1963#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 967#L1980true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 327#L932true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1919#L939true assume !(1 == ~m_i~0);~m_st~0 := 2; 471#L939-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1669#L944-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 311#L949-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1324#L954-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1969#L959-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 680#L964-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1176#L969-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1779#L974-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 615#L979-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 952#L984-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 257#L989-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 449#L994-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1206#L999-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 580#L1004-1true assume !(1 == ~t14_i~0);~t14_st~0 := 2; 48#L1009-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127#L1342true assume !(0 == ~M_E~0); 429#L1342-2true assume !(0 == ~T1_E~0); 1614#L1347-1true assume !(0 == ~T2_E~0); 1304#L1352-1true assume !(0 == ~T3_E~0); 1073#L1357-1true assume !(0 == ~T4_E~0); 445#L1362-1true assume !(0 == ~T5_E~0); 1387#L1367-1true assume !(0 == ~T6_E~0); 215#L1372-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 568#L1377-1true assume !(0 == ~T8_E~0); 401#L1382-1true assume !(0 == ~T9_E~0); 946#L1387-1true assume !(0 == ~T10_E~0); 1525#L1392-1true assume !(0 == ~T11_E~0); 420#L1397-1true assume !(0 == ~T12_E~0); 1682#L1402-1true assume !(0 == ~T13_E~0); 224#L1407-1true assume !(0 == ~T14_E~0); 1860#L1412-1true assume 0 == ~E_1~0;~E_1~0 := 1; 1201#L1417-1true assume !(0 == ~E_2~0); 2053#L1422-1true assume !(0 == ~E_3~0); 1681#L1427-1true assume !(0 == ~E_4~0); 331#L1432-1true assume !(0 == ~E_5~0); 1532#L1437-1true assume !(0 == ~E_6~0); 1118#L1442-1true assume !(0 == ~E_7~0); 1459#L1447-1true assume !(0 == ~E_8~0); 942#L1452-1true assume 0 == ~E_9~0;~E_9~0 := 1; 113#L1457-1true assume !(0 == ~E_10~0); 1154#L1462-1true assume !(0 == ~E_11~0); 1857#L1467-1true assume !(0 == ~E_12~0); 1172#L1472-1true assume !(0 == ~E_13~0); 1360#L1477-1true assume !(0 == ~E_14~0); 894#L1482-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210#L646true assume 1 == ~m_pc~0; 624#L647true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 632#L657true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 663#L658true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 258#L1666true assume !(0 != activate_threads_~tmp~1#1); 1984#L1666-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1747#L665true assume !(1 == ~t1_pc~0); 541#L665-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1200#L676true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 262#L677true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1708#L1674true assume !(0 != activate_threads_~tmp___0~0#1); 779#L1674-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 890#L684true assume 1 == ~t2_pc~0; 1868#L685true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 881#L695true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1693#L696true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1308#L1682true assume !(0 != activate_threads_~tmp___1~0#1); 1813#L1682-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1789#L703true assume !(1 == ~t3_pc~0); 342#L703-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1403#L714true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 771#L715true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35#L1690true assume !(0 != activate_threads_~tmp___2~0#1); 274#L1690-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1322#L722true assume 1 == ~t4_pc~0; 752#L723true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 603#L733true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1105#L734true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1623#L1698true assume !(0 != activate_threads_~tmp___3~0#1); 649#L1698-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128#L741true assume 1 == ~t5_pc~0; 288#L742true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 806#L752true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 374#L753true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 860#L1706true assume !(0 != activate_threads_~tmp___4~0#1); 1385#L1706-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 430#L760true assume !(1 == ~t6_pc~0); 739#L760-2true is_transmit6_triggered_~__retres1~6#1 := 0; 986#L771true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 259#L772true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1660#L1714true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 719#L1714-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1402#L779true assume 1 == ~t7_pc~0; 148#L780true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76#L790true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 281#L791true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1377#L1722true assume !(0 != activate_threads_~tmp___6~0#1); 295#L1722-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1691#L798true assume !(1 == ~t8_pc~0); 1935#L798-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1262#L809true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 149#L810true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1749#L1730true assume !(0 != activate_threads_~tmp___7~0#1); 1907#L1730-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66#L817true assume 1 == ~t9_pc~0; 828#L818true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 495#L828true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 899#L829true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1862#L1738true assume !(0 != activate_threads_~tmp___8~0#1); 265#L1738-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 773#L836true assume !(1 == ~t10_pc~0); 276#L836-2true is_transmit10_triggered_~__retres1~10#1 := 0; 238#L847true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1563#L848true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 377#L1746true assume !(0 != activate_threads_~tmp___9~0#1); 1276#L1746-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1277#L855true assume 1 == ~t11_pc~0; 630#L856true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1147#L866true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1245#L867true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 939#L1754true assume !(0 != activate_threads_~tmp___10~0#1); 784#L1754-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 208#L874true assume !(1 == ~t12_pc~0); 1641#L874-2true is_transmit12_triggered_~__retres1~12#1 := 0; 300#L885true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 378#L886true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1987#L1762true assume !(0 != activate_threads_~tmp___11~0#1); 52#L1762-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1861#L893true assume 1 == ~t13_pc~0; 1545#L894true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 400#L904true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1386#L905true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1560#L1770true assume !(0 != activate_threads_~tmp___12~0#1); 1396#L1770-2true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1767#L912true assume 1 == ~t14_pc~0; 1123#L913true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 2023#L923true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 209#L924true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 174#L1778true assume !(0 != activate_threads_~tmp___13~0#1); 643#L1778-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1342#L1495true assume 1 == ~M_E~0;~M_E~0 := 2; 1001#L1495-2true assume !(1 == ~T1_E~0); 1674#L1500-1true assume !(1 == ~T2_E~0); 716#L1505-1true assume !(1 == ~T3_E~0); 1914#L1510-1true assume !(1 == ~T4_E~0); 759#L1515-1true assume !(1 == ~T5_E~0); 1727#L1520-1true assume !(1 == ~T6_E~0); 1394#L1525-1true assume !(1 == ~T7_E~0); 1031#L1530-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 263#L1535-1true assume !(1 == ~T9_E~0); 1837#L1540-1true assume !(1 == ~T10_E~0); 17#L1545-1true assume !(1 == ~T11_E~0); 1973#L1550-1true assume !(1 == ~T12_E~0); 132#L1555-1true assume !(1 == ~T13_E~0); 289#L1560-1true assume !(1 == ~T14_E~0); 1706#L1565-1true assume !(1 == ~E_1~0); 1928#L1570-1true assume 1 == ~E_2~0;~E_2~0 := 2; 913#L1575-1true assume !(1 == ~E_3~0); 446#L1580-1true assume !(1 == ~E_4~0); 774#L1585-1true assume !(1 == ~E_5~0); 1045#L1590-1true assume !(1 == ~E_6~0); 468#L1595-1true assume !(1 == ~E_7~0); 1895#L1600-1true assume !(1 == ~E_8~0); 723#L1605-1true assume !(1 == ~E_9~0); 1649#L1610-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1240#L1615-1true assume !(1 == ~E_11~0); 365#L1620-1true assume !(1 == ~E_12~0); 1103#L1625-1true assume !(1 == ~E_13~0); 943#L1630-1true assume !(1 == ~E_14~0); 467#L1635-1true assume { :end_inline_reset_delta_events } true; 431#L2017-2true [2022-02-21 04:24:40,333 INFO L793 eck$LassoCheckResult]: Loop: 431#L2017-2true assume !false; 50#L2018true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 882#L1316true assume !true; 1267#L1332true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 502#L932-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 629#L1342-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1078#L1342-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1167#L1347-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 751#L1352-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1355#L1357-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 2038#L1362-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1880#L1367-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1847#L1372-3true assume !(0 == ~T7_E~0); 42#L1377-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 491#L1382-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 388#L1387-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1124#L1392-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1948#L1397-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1666#L1402-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 708#L1407-3true assume 0 == ~T14_E~0;~T14_E~0 := 1; 188#L1412-3true assume !(0 == ~E_1~0); 1397#L1417-3true assume 0 == ~E_2~0;~E_2~0 := 1; 654#L1422-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1347#L1427-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1534#L1432-3true assume 0 == ~E_5~0;~E_5~0 := 1; 976#L1437-3true assume 0 == ~E_6~0;~E_6~0 := 1; 720#L1442-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1000#L1447-3true assume 0 == ~E_8~0;~E_8~0 := 1; 73#L1452-3true assume !(0 == ~E_9~0); 1999#L1457-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1258#L1462-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1689#L1467-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1048#L1472-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1714#L1477-3true assume 0 == ~E_14~0;~E_14~0 := 1; 187#L1482-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 523#L646-42true assume 1 == ~m_pc~0; 1978#L647-14true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1306#L657-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1676#L658-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1619#L1666-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1711#L1666-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1216#L665-42true assume !(1 == ~t1_pc~0); 1456#L665-44true is_transmit1_triggered_~__retres1~1#1 := 0; 1538#L676-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1463#L677-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 277#L1674-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1883#L1674-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1879#L684-42true assume !(1 == ~t2_pc~0); 1793#L684-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1893#L695-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1808#L696-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 678#L1682-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 766#L1682-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1741#L703-42true assume 1 == ~t3_pc~0; 950#L704-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1851#L714-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 434#L715-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1630#L1690-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1052#L1690-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 698#L722-42true assume 1 == ~t4_pc~0; 1091#L723-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1719#L733-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 464#L734-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 357#L1698-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1920#L1698-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1730#L741-42true assume 1 == ~t5_pc~0; 1548#L742-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 606#L752-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1965#L753-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1898#L1706-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 536#L1706-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 636#L760-42true assume 1 == ~t6_pc~0; 1763#L761-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 730#L771-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1114#L772-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1638#L1714-42true assume !(0 != activate_threads_~tmp___5~0#1); 506#L1714-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1315#L779-42true assume 1 == ~t7_pc~0; 1242#L780-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1870#L790-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 319#L791-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1701#L1722-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 237#L1722-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 500#L798-42true assume 1 == ~t8_pc~0; 1924#L799-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1432#L809-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1330#L810-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 747#L1730-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 150#L1730-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1370#L817-42true assume !(1 == ~t9_pc~0); 1149#L817-44true is_transmit9_triggered_~__retres1~9#1 := 0; 303#L828-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 372#L829-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1186#L1738-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 974#L1738-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1515#L836-42true assume !(1 == ~t10_pc~0); 1817#L836-44true is_transmit10_triggered_~__retres1~10#1 := 0; 326#L847-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1842#L848-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1553#L1746-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1697#L1746-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2046#L855-42true assume 1 == ~t11_pc~0; 1722#L856-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 92#L866-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 503#L867-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1169#L1754-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2048#L1754-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 418#L874-42true assume 1 == ~t12_pc~0; 575#L875-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1487#L885-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51#L886-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 892#L1762-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 171#L1762-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1982#L893-42true assume 1 == ~t13_pc~0; 1007#L894-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1836#L904-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 808#L905-14true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 728#L1770-42true assume !(0 != activate_threads_~tmp___12~0#1); 375#L1770-44true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1849#L912-42true assume !(1 == ~t14_pc~0); 981#L912-44true is_transmit14_triggered_~__retres1~14#1 := 0; 27#L923-14true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1089#L924-14true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1219#L1778-42true assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 233#L1778-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 611#L1495-3true assume !(1 == ~M_E~0); 966#L1495-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1574#L1500-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1070#L1505-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 360#L1510-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 343#L1515-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 783#L1520-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 997#L1525-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1580#L1530-3true assume !(1 == ~T8_E~0); 254#L1535-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 275#L1540-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1289#L1545-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1533#L1550-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1513#L1555-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 516#L1560-3true assume 1 == ~T14_E~0;~T14_E~0 := 2; 1025#L1565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1874#L1570-3true assume !(1 == ~E_2~0); 970#L1575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1421#L1580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1522#L1585-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1759#L1590-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1663#L1595-3true assume 1 == ~E_7~0;~E_7~0 := 2; 803#L1600-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1309#L1605-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1398#L1610-3true assume !(1 == ~E_10~0); 366#L1615-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1912#L1620-3true assume 1 == ~E_12~0;~E_12~0 := 2; 776#L1625-3true assume 1 == ~E_13~0;~E_13~0 := 2; 2041#L1630-3true assume 1 == ~E_14~0;~E_14~0 := 2; 700#L1635-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 336#L1022-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 539#L1100-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1967#L1101-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 999#L2036true assume !(0 == start_simulation_~tmp~3#1); 1175#L2036-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1631#L1022-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1422#L1100-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1927#L1101-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 733#L1991true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1734#L1998true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1704#L1999true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1807#L2049true assume !(0 != start_simulation_~tmp___0~1#1); 431#L2017-2true [2022-02-21 04:24:40,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:40,339 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 1 times [2022-02-21 04:24:40,346 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:40,347 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267935269] [2022-02-21 04:24:40,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:40,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:40,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:40,525 INFO L290 TraceCheckUtils]: 0: Hoare triple {2057#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {2057#true} is VALID [2022-02-21 04:24:40,526 INFO L290 TraceCheckUtils]: 1: Hoare triple {2057#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {2059#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:40,528 INFO L290 TraceCheckUtils]: 2: Hoare triple {2059#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {2059#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:40,529 INFO L290 TraceCheckUtils]: 3: Hoare triple {2059#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {2059#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:40,529 INFO L290 TraceCheckUtils]: 4: Hoare triple {2059#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,530 INFO L290 TraceCheckUtils]: 5: Hoare triple {2058#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {2058#false} is VALID [2022-02-21 04:24:40,530 INFO L290 TraceCheckUtils]: 6: Hoare triple {2058#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,530 INFO L290 TraceCheckUtils]: 7: Hoare triple {2058#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,530 INFO L290 TraceCheckUtils]: 8: Hoare triple {2058#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,530 INFO L290 TraceCheckUtils]: 9: Hoare triple {2058#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,531 INFO L290 TraceCheckUtils]: 10: Hoare triple {2058#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,531 INFO L290 TraceCheckUtils]: 11: Hoare triple {2058#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,531 INFO L290 TraceCheckUtils]: 12: Hoare triple {2058#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,531 INFO L290 TraceCheckUtils]: 13: Hoare triple {2058#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {2058#false} is VALID [2022-02-21 04:24:40,532 INFO L290 TraceCheckUtils]: 14: Hoare triple {2058#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,532 INFO L290 TraceCheckUtils]: 15: Hoare triple {2058#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,532 INFO L290 TraceCheckUtils]: 16: Hoare triple {2058#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,532 INFO L290 TraceCheckUtils]: 17: Hoare triple {2058#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,532 INFO L290 TraceCheckUtils]: 18: Hoare triple {2058#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,533 INFO L290 TraceCheckUtils]: 19: Hoare triple {2058#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {2058#false} is VALID [2022-02-21 04:24:40,533 INFO L290 TraceCheckUtils]: 20: Hoare triple {2058#false} assume !(0 == ~M_E~0); {2058#false} is VALID [2022-02-21 04:24:40,534 INFO L290 TraceCheckUtils]: 21: Hoare triple {2058#false} assume !(0 == ~T1_E~0); {2058#false} is VALID [2022-02-21 04:24:40,534 INFO L290 TraceCheckUtils]: 22: Hoare triple {2058#false} assume !(0 == ~T2_E~0); {2058#false} is VALID [2022-02-21 04:24:40,534 INFO L290 TraceCheckUtils]: 23: Hoare triple {2058#false} assume !(0 == ~T3_E~0); {2058#false} is VALID [2022-02-21 04:24:40,534 INFO L290 TraceCheckUtils]: 24: Hoare triple {2058#false} assume !(0 == ~T4_E~0); {2058#false} is VALID [2022-02-21 04:24:40,535 INFO L290 TraceCheckUtils]: 25: Hoare triple {2058#false} assume !(0 == ~T5_E~0); {2058#false} is VALID [2022-02-21 04:24:40,535 INFO L290 TraceCheckUtils]: 26: Hoare triple {2058#false} assume !(0 == ~T6_E~0); {2058#false} is VALID [2022-02-21 04:24:40,535 INFO L290 TraceCheckUtils]: 27: Hoare triple {2058#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {2058#false} is VALID [2022-02-21 04:24:40,535 INFO L290 TraceCheckUtils]: 28: Hoare triple {2058#false} assume !(0 == ~T8_E~0); {2058#false} is VALID [2022-02-21 04:24:40,536 INFO L290 TraceCheckUtils]: 29: Hoare triple {2058#false} assume !(0 == ~T9_E~0); {2058#false} is VALID [2022-02-21 04:24:40,536 INFO L290 TraceCheckUtils]: 30: Hoare triple {2058#false} assume !(0 == ~T10_E~0); {2058#false} is VALID [2022-02-21 04:24:40,536 INFO L290 TraceCheckUtils]: 31: Hoare triple {2058#false} assume !(0 == ~T11_E~0); {2058#false} is VALID [2022-02-21 04:24:40,536 INFO L290 TraceCheckUtils]: 32: Hoare triple {2058#false} assume !(0 == ~T12_E~0); {2058#false} is VALID [2022-02-21 04:24:40,536 INFO L290 TraceCheckUtils]: 33: Hoare triple {2058#false} assume !(0 == ~T13_E~0); {2058#false} is VALID [2022-02-21 04:24:40,537 INFO L290 TraceCheckUtils]: 34: Hoare triple {2058#false} assume !(0 == ~T14_E~0); {2058#false} is VALID [2022-02-21 04:24:40,537 INFO L290 TraceCheckUtils]: 35: Hoare triple {2058#false} assume 0 == ~E_1~0;~E_1~0 := 1; {2058#false} is VALID [2022-02-21 04:24:40,537 INFO L290 TraceCheckUtils]: 36: Hoare triple {2058#false} assume !(0 == ~E_2~0); {2058#false} is VALID [2022-02-21 04:24:40,537 INFO L290 TraceCheckUtils]: 37: Hoare triple {2058#false} assume !(0 == ~E_3~0); {2058#false} is VALID [2022-02-21 04:24:40,538 INFO L290 TraceCheckUtils]: 38: Hoare triple {2058#false} assume !(0 == ~E_4~0); {2058#false} is VALID [2022-02-21 04:24:40,538 INFO L290 TraceCheckUtils]: 39: Hoare triple {2058#false} assume !(0 == ~E_5~0); {2058#false} is VALID [2022-02-21 04:24:40,538 INFO L290 TraceCheckUtils]: 40: Hoare triple {2058#false} assume !(0 == ~E_6~0); {2058#false} is VALID [2022-02-21 04:24:40,538 INFO L290 TraceCheckUtils]: 41: Hoare triple {2058#false} assume !(0 == ~E_7~0); {2058#false} is VALID [2022-02-21 04:24:40,539 INFO L290 TraceCheckUtils]: 42: Hoare triple {2058#false} assume !(0 == ~E_8~0); {2058#false} is VALID [2022-02-21 04:24:40,539 INFO L290 TraceCheckUtils]: 43: Hoare triple {2058#false} assume 0 == ~E_9~0;~E_9~0 := 1; {2058#false} is VALID [2022-02-21 04:24:40,539 INFO L290 TraceCheckUtils]: 44: Hoare triple {2058#false} assume !(0 == ~E_10~0); {2058#false} is VALID [2022-02-21 04:24:40,540 INFO L290 TraceCheckUtils]: 45: Hoare triple {2058#false} assume !(0 == ~E_11~0); {2058#false} is VALID [2022-02-21 04:24:40,540 INFO L290 TraceCheckUtils]: 46: Hoare triple {2058#false} assume !(0 == ~E_12~0); {2058#false} is VALID [2022-02-21 04:24:40,540 INFO L290 TraceCheckUtils]: 47: Hoare triple {2058#false} assume !(0 == ~E_13~0); {2058#false} is VALID [2022-02-21 04:24:40,540 INFO L290 TraceCheckUtils]: 48: Hoare triple {2058#false} assume !(0 == ~E_14~0); {2058#false} is VALID [2022-02-21 04:24:40,543 INFO L290 TraceCheckUtils]: 49: Hoare triple {2058#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2058#false} is VALID [2022-02-21 04:24:40,544 INFO L290 TraceCheckUtils]: 50: Hoare triple {2058#false} assume 1 == ~m_pc~0; {2058#false} is VALID [2022-02-21 04:24:40,544 INFO L290 TraceCheckUtils]: 51: Hoare triple {2058#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {2058#false} is VALID [2022-02-21 04:24:40,546 INFO L290 TraceCheckUtils]: 52: Hoare triple {2058#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2058#false} is VALID [2022-02-21 04:24:40,546 INFO L290 TraceCheckUtils]: 53: Hoare triple {2058#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {2058#false} is VALID [2022-02-21 04:24:40,546 INFO L290 TraceCheckUtils]: 54: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp~1#1); {2058#false} is VALID [2022-02-21 04:24:40,547 INFO L290 TraceCheckUtils]: 55: Hoare triple {2058#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2058#false} is VALID [2022-02-21 04:24:40,547 INFO L290 TraceCheckUtils]: 56: Hoare triple {2058#false} assume !(1 == ~t1_pc~0); {2058#false} is VALID [2022-02-21 04:24:40,547 INFO L290 TraceCheckUtils]: 57: Hoare triple {2058#false} is_transmit1_triggered_~__retres1~1#1 := 0; {2058#false} is VALID [2022-02-21 04:24:40,547 INFO L290 TraceCheckUtils]: 58: Hoare triple {2058#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2058#false} is VALID [2022-02-21 04:24:40,548 INFO L290 TraceCheckUtils]: 59: Hoare triple {2058#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {2058#false} is VALID [2022-02-21 04:24:40,548 INFO L290 TraceCheckUtils]: 60: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___0~0#1); {2058#false} is VALID [2022-02-21 04:24:40,548 INFO L290 TraceCheckUtils]: 61: Hoare triple {2058#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2058#false} is VALID [2022-02-21 04:24:40,549 INFO L290 TraceCheckUtils]: 62: Hoare triple {2058#false} assume 1 == ~t2_pc~0; {2058#false} is VALID [2022-02-21 04:24:40,549 INFO L290 TraceCheckUtils]: 63: Hoare triple {2058#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2058#false} is VALID [2022-02-21 04:24:40,549 INFO L290 TraceCheckUtils]: 64: Hoare triple {2058#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2058#false} is VALID [2022-02-21 04:24:40,551 INFO L290 TraceCheckUtils]: 65: Hoare triple {2058#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {2058#false} is VALID [2022-02-21 04:24:40,552 INFO L290 TraceCheckUtils]: 66: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___1~0#1); {2058#false} is VALID [2022-02-21 04:24:40,552 INFO L290 TraceCheckUtils]: 67: Hoare triple {2058#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2058#false} is VALID [2022-02-21 04:24:40,552 INFO L290 TraceCheckUtils]: 68: Hoare triple {2058#false} assume !(1 == ~t3_pc~0); {2058#false} is VALID [2022-02-21 04:24:40,553 INFO L290 TraceCheckUtils]: 69: Hoare triple {2058#false} is_transmit3_triggered_~__retres1~3#1 := 0; {2058#false} is VALID [2022-02-21 04:24:40,553 INFO L290 TraceCheckUtils]: 70: Hoare triple {2058#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2058#false} is VALID [2022-02-21 04:24:40,554 INFO L290 TraceCheckUtils]: 71: Hoare triple {2058#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {2058#false} is VALID [2022-02-21 04:24:40,554 INFO L290 TraceCheckUtils]: 72: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___2~0#1); {2058#false} is VALID [2022-02-21 04:24:40,554 INFO L290 TraceCheckUtils]: 73: Hoare triple {2058#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2058#false} is VALID [2022-02-21 04:24:40,559 INFO L290 TraceCheckUtils]: 74: Hoare triple {2058#false} assume 1 == ~t4_pc~0; {2058#false} is VALID [2022-02-21 04:24:40,559 INFO L290 TraceCheckUtils]: 75: Hoare triple {2058#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2058#false} is VALID [2022-02-21 04:24:40,559 INFO L290 TraceCheckUtils]: 76: Hoare triple {2058#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2058#false} is VALID [2022-02-21 04:24:40,559 INFO L290 TraceCheckUtils]: 77: Hoare triple {2058#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {2058#false} is VALID [2022-02-21 04:24:40,559 INFO L290 TraceCheckUtils]: 78: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___3~0#1); {2058#false} is VALID [2022-02-21 04:24:40,560 INFO L290 TraceCheckUtils]: 79: Hoare triple {2058#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2058#false} is VALID [2022-02-21 04:24:40,560 INFO L290 TraceCheckUtils]: 80: Hoare triple {2058#false} assume 1 == ~t5_pc~0; {2058#false} is VALID [2022-02-21 04:24:40,560 INFO L290 TraceCheckUtils]: 81: Hoare triple {2058#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {2058#false} is VALID [2022-02-21 04:24:40,560 INFO L290 TraceCheckUtils]: 82: Hoare triple {2058#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2058#false} is VALID [2022-02-21 04:24:40,560 INFO L290 TraceCheckUtils]: 83: Hoare triple {2058#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {2058#false} is VALID [2022-02-21 04:24:40,561 INFO L290 TraceCheckUtils]: 84: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___4~0#1); {2058#false} is VALID [2022-02-21 04:24:40,561 INFO L290 TraceCheckUtils]: 85: Hoare triple {2058#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {2058#false} is VALID [2022-02-21 04:24:40,561 INFO L290 TraceCheckUtils]: 86: Hoare triple {2058#false} assume !(1 == ~t6_pc~0); {2058#false} is VALID [2022-02-21 04:24:40,561 INFO L290 TraceCheckUtils]: 87: Hoare triple {2058#false} is_transmit6_triggered_~__retres1~6#1 := 0; {2058#false} is VALID [2022-02-21 04:24:40,562 INFO L290 TraceCheckUtils]: 88: Hoare triple {2058#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {2058#false} is VALID [2022-02-21 04:24:40,562 INFO L290 TraceCheckUtils]: 89: Hoare triple {2058#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {2058#false} is VALID [2022-02-21 04:24:40,562 INFO L290 TraceCheckUtils]: 90: Hoare triple {2058#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {2058#false} is VALID [2022-02-21 04:24:40,562 INFO L290 TraceCheckUtils]: 91: Hoare triple {2058#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {2058#false} is VALID [2022-02-21 04:24:40,562 INFO L290 TraceCheckUtils]: 92: Hoare triple {2058#false} assume 1 == ~t7_pc~0; {2058#false} is VALID [2022-02-21 04:24:40,563 INFO L290 TraceCheckUtils]: 93: Hoare triple {2058#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {2058#false} is VALID [2022-02-21 04:24:40,563 INFO L290 TraceCheckUtils]: 94: Hoare triple {2058#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {2058#false} is VALID [2022-02-21 04:24:40,563 INFO L290 TraceCheckUtils]: 95: Hoare triple {2058#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {2058#false} is VALID [2022-02-21 04:24:40,563 INFO L290 TraceCheckUtils]: 96: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___6~0#1); {2058#false} is VALID [2022-02-21 04:24:40,563 INFO L290 TraceCheckUtils]: 97: Hoare triple {2058#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {2058#false} is VALID [2022-02-21 04:24:40,564 INFO L290 TraceCheckUtils]: 98: Hoare triple {2058#false} assume !(1 == ~t8_pc~0); {2058#false} is VALID [2022-02-21 04:24:40,564 INFO L290 TraceCheckUtils]: 99: Hoare triple {2058#false} is_transmit8_triggered_~__retres1~8#1 := 0; {2058#false} is VALID [2022-02-21 04:24:40,564 INFO L290 TraceCheckUtils]: 100: Hoare triple {2058#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {2058#false} is VALID [2022-02-21 04:24:40,564 INFO L290 TraceCheckUtils]: 101: Hoare triple {2058#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {2058#false} is VALID [2022-02-21 04:24:40,564 INFO L290 TraceCheckUtils]: 102: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___7~0#1); {2058#false} is VALID [2022-02-21 04:24:40,565 INFO L290 TraceCheckUtils]: 103: Hoare triple {2058#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {2058#false} is VALID [2022-02-21 04:24:40,565 INFO L290 TraceCheckUtils]: 104: Hoare triple {2058#false} assume 1 == ~t9_pc~0; {2058#false} is VALID [2022-02-21 04:24:40,567 INFO L290 TraceCheckUtils]: 105: Hoare triple {2058#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {2058#false} is VALID [2022-02-21 04:24:40,567 INFO L290 TraceCheckUtils]: 106: Hoare triple {2058#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {2058#false} is VALID [2022-02-21 04:24:40,567 INFO L290 TraceCheckUtils]: 107: Hoare triple {2058#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {2058#false} is VALID [2022-02-21 04:24:40,568 INFO L290 TraceCheckUtils]: 108: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___8~0#1); {2058#false} is VALID [2022-02-21 04:24:40,568 INFO L290 TraceCheckUtils]: 109: Hoare triple {2058#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {2058#false} is VALID [2022-02-21 04:24:40,568 INFO L290 TraceCheckUtils]: 110: Hoare triple {2058#false} assume !(1 == ~t10_pc~0); {2058#false} is VALID [2022-02-21 04:24:40,569 INFO L290 TraceCheckUtils]: 111: Hoare triple {2058#false} is_transmit10_triggered_~__retres1~10#1 := 0; {2058#false} is VALID [2022-02-21 04:24:40,569 INFO L290 TraceCheckUtils]: 112: Hoare triple {2058#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {2058#false} is VALID [2022-02-21 04:24:40,570 INFO L290 TraceCheckUtils]: 113: Hoare triple {2058#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {2058#false} is VALID [2022-02-21 04:24:40,571 INFO L290 TraceCheckUtils]: 114: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___9~0#1); {2058#false} is VALID [2022-02-21 04:24:40,571 INFO L290 TraceCheckUtils]: 115: Hoare triple {2058#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {2058#false} is VALID [2022-02-21 04:24:40,573 INFO L290 TraceCheckUtils]: 116: Hoare triple {2058#false} assume 1 == ~t11_pc~0; {2058#false} is VALID [2022-02-21 04:24:40,582 INFO L290 TraceCheckUtils]: 117: Hoare triple {2058#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {2058#false} is VALID [2022-02-21 04:24:40,582 INFO L290 TraceCheckUtils]: 118: Hoare triple {2058#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {2058#false} is VALID [2022-02-21 04:24:40,582 INFO L290 TraceCheckUtils]: 119: Hoare triple {2058#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {2058#false} is VALID [2022-02-21 04:24:40,583 INFO L290 TraceCheckUtils]: 120: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___10~0#1); {2058#false} is VALID [2022-02-21 04:24:40,583 INFO L290 TraceCheckUtils]: 121: Hoare triple {2058#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {2058#false} is VALID [2022-02-21 04:24:40,583 INFO L290 TraceCheckUtils]: 122: Hoare triple {2058#false} assume !(1 == ~t12_pc~0); {2058#false} is VALID [2022-02-21 04:24:40,583 INFO L290 TraceCheckUtils]: 123: Hoare triple {2058#false} is_transmit12_triggered_~__retres1~12#1 := 0; {2058#false} is VALID [2022-02-21 04:24:40,583 INFO L290 TraceCheckUtils]: 124: Hoare triple {2058#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {2058#false} is VALID [2022-02-21 04:24:40,583 INFO L290 TraceCheckUtils]: 125: Hoare triple {2058#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {2058#false} is VALID [2022-02-21 04:24:40,584 INFO L290 TraceCheckUtils]: 126: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___11~0#1); {2058#false} is VALID [2022-02-21 04:24:40,584 INFO L290 TraceCheckUtils]: 127: Hoare triple {2058#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {2058#false} is VALID [2022-02-21 04:24:40,584 INFO L290 TraceCheckUtils]: 128: Hoare triple {2058#false} assume 1 == ~t13_pc~0; {2058#false} is VALID [2022-02-21 04:24:40,584 INFO L290 TraceCheckUtils]: 129: Hoare triple {2058#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {2058#false} is VALID [2022-02-21 04:24:40,584 INFO L290 TraceCheckUtils]: 130: Hoare triple {2058#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {2058#false} is VALID [2022-02-21 04:24:40,584 INFO L290 TraceCheckUtils]: 131: Hoare triple {2058#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {2058#false} is VALID [2022-02-21 04:24:40,585 INFO L290 TraceCheckUtils]: 132: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___12~0#1); {2058#false} is VALID [2022-02-21 04:24:40,585 INFO L290 TraceCheckUtils]: 133: Hoare triple {2058#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {2058#false} is VALID [2022-02-21 04:24:40,585 INFO L290 TraceCheckUtils]: 134: Hoare triple {2058#false} assume 1 == ~t14_pc~0; {2058#false} is VALID [2022-02-21 04:24:40,585 INFO L290 TraceCheckUtils]: 135: Hoare triple {2058#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {2058#false} is VALID [2022-02-21 04:24:40,585 INFO L290 TraceCheckUtils]: 136: Hoare triple {2058#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {2058#false} is VALID [2022-02-21 04:24:40,586 INFO L290 TraceCheckUtils]: 137: Hoare triple {2058#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {2058#false} is VALID [2022-02-21 04:24:40,586 INFO L290 TraceCheckUtils]: 138: Hoare triple {2058#false} assume !(0 != activate_threads_~tmp___13~0#1); {2058#false} is VALID [2022-02-21 04:24:40,586 INFO L290 TraceCheckUtils]: 139: Hoare triple {2058#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2058#false} is VALID [2022-02-21 04:24:40,586 INFO L290 TraceCheckUtils]: 140: Hoare triple {2058#false} assume 1 == ~M_E~0;~M_E~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,586 INFO L290 TraceCheckUtils]: 141: Hoare triple {2058#false} assume !(1 == ~T1_E~0); {2058#false} is VALID [2022-02-21 04:24:40,586 INFO L290 TraceCheckUtils]: 142: Hoare triple {2058#false} assume !(1 == ~T2_E~0); {2058#false} is VALID [2022-02-21 04:24:40,587 INFO L290 TraceCheckUtils]: 143: Hoare triple {2058#false} assume !(1 == ~T3_E~0); {2058#false} is VALID [2022-02-21 04:24:40,587 INFO L290 TraceCheckUtils]: 144: Hoare triple {2058#false} assume !(1 == ~T4_E~0); {2058#false} is VALID [2022-02-21 04:24:40,590 INFO L290 TraceCheckUtils]: 145: Hoare triple {2058#false} assume !(1 == ~T5_E~0); {2058#false} is VALID [2022-02-21 04:24:40,590 INFO L290 TraceCheckUtils]: 146: Hoare triple {2058#false} assume !(1 == ~T6_E~0); {2058#false} is VALID [2022-02-21 04:24:40,590 INFO L290 TraceCheckUtils]: 147: Hoare triple {2058#false} assume !(1 == ~T7_E~0); {2058#false} is VALID [2022-02-21 04:24:40,590 INFO L290 TraceCheckUtils]: 148: Hoare triple {2058#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,590 INFO L290 TraceCheckUtils]: 149: Hoare triple {2058#false} assume !(1 == ~T9_E~0); {2058#false} is VALID [2022-02-21 04:24:40,590 INFO L290 TraceCheckUtils]: 150: Hoare triple {2058#false} assume !(1 == ~T10_E~0); {2058#false} is VALID [2022-02-21 04:24:40,591 INFO L290 TraceCheckUtils]: 151: Hoare triple {2058#false} assume !(1 == ~T11_E~0); {2058#false} is VALID [2022-02-21 04:24:40,591 INFO L290 TraceCheckUtils]: 152: Hoare triple {2058#false} assume !(1 == ~T12_E~0); {2058#false} is VALID [2022-02-21 04:24:40,591 INFO L290 TraceCheckUtils]: 153: Hoare triple {2058#false} assume !(1 == ~T13_E~0); {2058#false} is VALID [2022-02-21 04:24:40,591 INFO L290 TraceCheckUtils]: 154: Hoare triple {2058#false} assume !(1 == ~T14_E~0); {2058#false} is VALID [2022-02-21 04:24:40,591 INFO L290 TraceCheckUtils]: 155: Hoare triple {2058#false} assume !(1 == ~E_1~0); {2058#false} is VALID [2022-02-21 04:24:40,591 INFO L290 TraceCheckUtils]: 156: Hoare triple {2058#false} assume 1 == ~E_2~0;~E_2~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,592 INFO L290 TraceCheckUtils]: 157: Hoare triple {2058#false} assume !(1 == ~E_3~0); {2058#false} is VALID [2022-02-21 04:24:40,592 INFO L290 TraceCheckUtils]: 158: Hoare triple {2058#false} assume !(1 == ~E_4~0); {2058#false} is VALID [2022-02-21 04:24:40,592 INFO L290 TraceCheckUtils]: 159: Hoare triple {2058#false} assume !(1 == ~E_5~0); {2058#false} is VALID [2022-02-21 04:24:40,592 INFO L290 TraceCheckUtils]: 160: Hoare triple {2058#false} assume !(1 == ~E_6~0); {2058#false} is VALID [2022-02-21 04:24:40,592 INFO L290 TraceCheckUtils]: 161: Hoare triple {2058#false} assume !(1 == ~E_7~0); {2058#false} is VALID [2022-02-21 04:24:40,593 INFO L290 TraceCheckUtils]: 162: Hoare triple {2058#false} assume !(1 == ~E_8~0); {2058#false} is VALID [2022-02-21 04:24:40,593 INFO L290 TraceCheckUtils]: 163: Hoare triple {2058#false} assume !(1 == ~E_9~0); {2058#false} is VALID [2022-02-21 04:24:40,593 INFO L290 TraceCheckUtils]: 164: Hoare triple {2058#false} assume 1 == ~E_10~0;~E_10~0 := 2; {2058#false} is VALID [2022-02-21 04:24:40,593 INFO L290 TraceCheckUtils]: 165: Hoare triple {2058#false} assume !(1 == ~E_11~0); {2058#false} is VALID [2022-02-21 04:24:40,593 INFO L290 TraceCheckUtils]: 166: Hoare triple {2058#false} assume !(1 == ~E_12~0); {2058#false} is VALID [2022-02-21 04:24:40,593 INFO L290 TraceCheckUtils]: 167: Hoare triple {2058#false} assume !(1 == ~E_13~0); {2058#false} is VALID [2022-02-21 04:24:40,594 INFO L290 TraceCheckUtils]: 168: Hoare triple {2058#false} assume !(1 == ~E_14~0); {2058#false} is VALID [2022-02-21 04:24:40,594 INFO L290 TraceCheckUtils]: 169: Hoare triple {2058#false} assume { :end_inline_reset_delta_events } true; {2058#false} is VALID [2022-02-21 04:24:40,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:40,595 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:40,596 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267935269] [2022-02-21 04:24:40,596 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267935269] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:40,597 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:40,597 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:40,598 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [684600518] [2022-02-21 04:24:40,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:40,602 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:40,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:40,604 INFO L85 PathProgramCache]: Analyzing trace with hash 1941229649, now seen corresponding path program 1 times [2022-02-21 04:24:40,604 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:40,604 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803034598] [2022-02-21 04:24:40,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:40,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:40,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:40,674 INFO L290 TraceCheckUtils]: 0: Hoare triple {2060#true} assume !false; {2060#true} is VALID [2022-02-21 04:24:40,675 INFO L290 TraceCheckUtils]: 1: Hoare triple {2060#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {2060#true} is VALID [2022-02-21 04:24:40,675 INFO L290 TraceCheckUtils]: 2: Hoare triple {2060#true} assume !true; {2061#false} is VALID [2022-02-21 04:24:40,675 INFO L290 TraceCheckUtils]: 3: Hoare triple {2061#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {2061#false} is VALID [2022-02-21 04:24:40,676 INFO L290 TraceCheckUtils]: 4: Hoare triple {2061#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {2061#false} is VALID [2022-02-21 04:24:40,676 INFO L290 TraceCheckUtils]: 5: Hoare triple {2061#false} assume 0 == ~M_E~0;~M_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,676 INFO L290 TraceCheckUtils]: 6: Hoare triple {2061#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,676 INFO L290 TraceCheckUtils]: 7: Hoare triple {2061#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,676 INFO L290 TraceCheckUtils]: 8: Hoare triple {2061#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,676 INFO L290 TraceCheckUtils]: 9: Hoare triple {2061#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,676 INFO L290 TraceCheckUtils]: 10: Hoare triple {2061#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,677 INFO L290 TraceCheckUtils]: 11: Hoare triple {2061#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,677 INFO L290 TraceCheckUtils]: 12: Hoare triple {2061#false} assume !(0 == ~T7_E~0); {2061#false} is VALID [2022-02-21 04:24:40,677 INFO L290 TraceCheckUtils]: 13: Hoare triple {2061#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,677 INFO L290 TraceCheckUtils]: 14: Hoare triple {2061#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,677 INFO L290 TraceCheckUtils]: 15: Hoare triple {2061#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,677 INFO L290 TraceCheckUtils]: 16: Hoare triple {2061#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,678 INFO L290 TraceCheckUtils]: 17: Hoare triple {2061#false} assume 0 == ~T12_E~0;~T12_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,678 INFO L290 TraceCheckUtils]: 18: Hoare triple {2061#false} assume 0 == ~T13_E~0;~T13_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,678 INFO L290 TraceCheckUtils]: 19: Hoare triple {2061#false} assume 0 == ~T14_E~0;~T14_E~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,678 INFO L290 TraceCheckUtils]: 20: Hoare triple {2061#false} assume !(0 == ~E_1~0); {2061#false} is VALID [2022-02-21 04:24:40,678 INFO L290 TraceCheckUtils]: 21: Hoare triple {2061#false} assume 0 == ~E_2~0;~E_2~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,678 INFO L290 TraceCheckUtils]: 22: Hoare triple {2061#false} assume 0 == ~E_3~0;~E_3~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,678 INFO L290 TraceCheckUtils]: 23: Hoare triple {2061#false} assume 0 == ~E_4~0;~E_4~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,679 INFO L290 TraceCheckUtils]: 24: Hoare triple {2061#false} assume 0 == ~E_5~0;~E_5~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,679 INFO L290 TraceCheckUtils]: 25: Hoare triple {2061#false} assume 0 == ~E_6~0;~E_6~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,679 INFO L290 TraceCheckUtils]: 26: Hoare triple {2061#false} assume 0 == ~E_7~0;~E_7~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,679 INFO L290 TraceCheckUtils]: 27: Hoare triple {2061#false} assume 0 == ~E_8~0;~E_8~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,679 INFO L290 TraceCheckUtils]: 28: Hoare triple {2061#false} assume !(0 == ~E_9~0); {2061#false} is VALID [2022-02-21 04:24:40,679 INFO L290 TraceCheckUtils]: 29: Hoare triple {2061#false} assume 0 == ~E_10~0;~E_10~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,679 INFO L290 TraceCheckUtils]: 30: Hoare triple {2061#false} assume 0 == ~E_11~0;~E_11~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,680 INFO L290 TraceCheckUtils]: 31: Hoare triple {2061#false} assume 0 == ~E_12~0;~E_12~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,680 INFO L290 TraceCheckUtils]: 32: Hoare triple {2061#false} assume 0 == ~E_13~0;~E_13~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,680 INFO L290 TraceCheckUtils]: 33: Hoare triple {2061#false} assume 0 == ~E_14~0;~E_14~0 := 1; {2061#false} is VALID [2022-02-21 04:24:40,680 INFO L290 TraceCheckUtils]: 34: Hoare triple {2061#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2061#false} is VALID [2022-02-21 04:24:40,680 INFO L290 TraceCheckUtils]: 35: Hoare triple {2061#false} assume 1 == ~m_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,680 INFO L290 TraceCheckUtils]: 36: Hoare triple {2061#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,681 INFO L290 TraceCheckUtils]: 37: Hoare triple {2061#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2061#false} is VALID [2022-02-21 04:24:40,681 INFO L290 TraceCheckUtils]: 38: Hoare triple {2061#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {2061#false} is VALID [2022-02-21 04:24:40,681 INFO L290 TraceCheckUtils]: 39: Hoare triple {2061#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,681 INFO L290 TraceCheckUtils]: 40: Hoare triple {2061#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2061#false} is VALID [2022-02-21 04:24:40,681 INFO L290 TraceCheckUtils]: 41: Hoare triple {2061#false} assume !(1 == ~t1_pc~0); {2061#false} is VALID [2022-02-21 04:24:40,681 INFO L290 TraceCheckUtils]: 42: Hoare triple {2061#false} is_transmit1_triggered_~__retres1~1#1 := 0; {2061#false} is VALID [2022-02-21 04:24:40,681 INFO L290 TraceCheckUtils]: 43: Hoare triple {2061#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2061#false} is VALID [2022-02-21 04:24:40,682 INFO L290 TraceCheckUtils]: 44: Hoare triple {2061#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {2061#false} is VALID [2022-02-21 04:24:40,682 INFO L290 TraceCheckUtils]: 45: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,682 INFO L290 TraceCheckUtils]: 46: Hoare triple {2061#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2061#false} is VALID [2022-02-21 04:24:40,682 INFO L290 TraceCheckUtils]: 47: Hoare triple {2061#false} assume !(1 == ~t2_pc~0); {2061#false} is VALID [2022-02-21 04:24:40,682 INFO L290 TraceCheckUtils]: 48: Hoare triple {2061#false} is_transmit2_triggered_~__retres1~2#1 := 0; {2061#false} is VALID [2022-02-21 04:24:40,682 INFO L290 TraceCheckUtils]: 49: Hoare triple {2061#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2061#false} is VALID [2022-02-21 04:24:40,683 INFO L290 TraceCheckUtils]: 50: Hoare triple {2061#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {2061#false} is VALID [2022-02-21 04:24:40,683 INFO L290 TraceCheckUtils]: 51: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,683 INFO L290 TraceCheckUtils]: 52: Hoare triple {2061#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2061#false} is VALID [2022-02-21 04:24:40,683 INFO L290 TraceCheckUtils]: 53: Hoare triple {2061#false} assume 1 == ~t3_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,683 INFO L290 TraceCheckUtils]: 54: Hoare triple {2061#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,683 INFO L290 TraceCheckUtils]: 55: Hoare triple {2061#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2061#false} is VALID [2022-02-21 04:24:40,686 INFO L290 TraceCheckUtils]: 56: Hoare triple {2061#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {2061#false} is VALID [2022-02-21 04:24:40,686 INFO L290 TraceCheckUtils]: 57: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,687 INFO L290 TraceCheckUtils]: 58: Hoare triple {2061#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2061#false} is VALID [2022-02-21 04:24:40,687 INFO L290 TraceCheckUtils]: 59: Hoare triple {2061#false} assume 1 == ~t4_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,687 INFO L290 TraceCheckUtils]: 60: Hoare triple {2061#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,687 INFO L290 TraceCheckUtils]: 61: Hoare triple {2061#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2061#false} is VALID [2022-02-21 04:24:40,687 INFO L290 TraceCheckUtils]: 62: Hoare triple {2061#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {2061#false} is VALID [2022-02-21 04:24:40,687 INFO L290 TraceCheckUtils]: 63: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,687 INFO L290 TraceCheckUtils]: 64: Hoare triple {2061#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2061#false} is VALID [2022-02-21 04:24:40,688 INFO L290 TraceCheckUtils]: 65: Hoare triple {2061#false} assume 1 == ~t5_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,688 INFO L290 TraceCheckUtils]: 66: Hoare triple {2061#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,688 INFO L290 TraceCheckUtils]: 67: Hoare triple {2061#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2061#false} is VALID [2022-02-21 04:24:40,688 INFO L290 TraceCheckUtils]: 68: Hoare triple {2061#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {2061#false} is VALID [2022-02-21 04:24:40,688 INFO L290 TraceCheckUtils]: 69: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,688 INFO L290 TraceCheckUtils]: 70: Hoare triple {2061#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {2061#false} is VALID [2022-02-21 04:24:40,689 INFO L290 TraceCheckUtils]: 71: Hoare triple {2061#false} assume 1 == ~t6_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,689 INFO L290 TraceCheckUtils]: 72: Hoare triple {2061#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,689 INFO L290 TraceCheckUtils]: 73: Hoare triple {2061#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {2061#false} is VALID [2022-02-21 04:24:40,689 INFO L290 TraceCheckUtils]: 74: Hoare triple {2061#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {2061#false} is VALID [2022-02-21 04:24:40,689 INFO L290 TraceCheckUtils]: 75: Hoare triple {2061#false} assume !(0 != activate_threads_~tmp___5~0#1); {2061#false} is VALID [2022-02-21 04:24:40,689 INFO L290 TraceCheckUtils]: 76: Hoare triple {2061#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {2061#false} is VALID [2022-02-21 04:24:40,689 INFO L290 TraceCheckUtils]: 77: Hoare triple {2061#false} assume 1 == ~t7_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,690 INFO L290 TraceCheckUtils]: 78: Hoare triple {2061#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,694 INFO L290 TraceCheckUtils]: 79: Hoare triple {2061#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {2061#false} is VALID [2022-02-21 04:24:40,694 INFO L290 TraceCheckUtils]: 80: Hoare triple {2061#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {2061#false} is VALID [2022-02-21 04:24:40,695 INFO L290 TraceCheckUtils]: 81: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,695 INFO L290 TraceCheckUtils]: 82: Hoare triple {2061#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {2061#false} is VALID [2022-02-21 04:24:40,695 INFO L290 TraceCheckUtils]: 83: Hoare triple {2061#false} assume 1 == ~t8_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,695 INFO L290 TraceCheckUtils]: 84: Hoare triple {2061#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,695 INFO L290 TraceCheckUtils]: 85: Hoare triple {2061#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {2061#false} is VALID [2022-02-21 04:24:40,695 INFO L290 TraceCheckUtils]: 86: Hoare triple {2061#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {2061#false} is VALID [2022-02-21 04:24:40,696 INFO L290 TraceCheckUtils]: 87: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,696 INFO L290 TraceCheckUtils]: 88: Hoare triple {2061#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {2061#false} is VALID [2022-02-21 04:24:40,696 INFO L290 TraceCheckUtils]: 89: Hoare triple {2061#false} assume !(1 == ~t9_pc~0); {2061#false} is VALID [2022-02-21 04:24:40,696 INFO L290 TraceCheckUtils]: 90: Hoare triple {2061#false} is_transmit9_triggered_~__retres1~9#1 := 0; {2061#false} is VALID [2022-02-21 04:24:40,696 INFO L290 TraceCheckUtils]: 91: Hoare triple {2061#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {2061#false} is VALID [2022-02-21 04:24:40,696 INFO L290 TraceCheckUtils]: 92: Hoare triple {2061#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {2061#false} is VALID [2022-02-21 04:24:40,696 INFO L290 TraceCheckUtils]: 93: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,697 INFO L290 TraceCheckUtils]: 94: Hoare triple {2061#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {2061#false} is VALID [2022-02-21 04:24:40,697 INFO L290 TraceCheckUtils]: 95: Hoare triple {2061#false} assume !(1 == ~t10_pc~0); {2061#false} is VALID [2022-02-21 04:24:40,697 INFO L290 TraceCheckUtils]: 96: Hoare triple {2061#false} is_transmit10_triggered_~__retres1~10#1 := 0; {2061#false} is VALID [2022-02-21 04:24:40,697 INFO L290 TraceCheckUtils]: 97: Hoare triple {2061#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {2061#false} is VALID [2022-02-21 04:24:40,697 INFO L290 TraceCheckUtils]: 98: Hoare triple {2061#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {2061#false} is VALID [2022-02-21 04:24:40,697 INFO L290 TraceCheckUtils]: 99: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,697 INFO L290 TraceCheckUtils]: 100: Hoare triple {2061#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {2061#false} is VALID [2022-02-21 04:24:40,700 INFO L290 TraceCheckUtils]: 101: Hoare triple {2061#false} assume 1 == ~t11_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,703 INFO L290 TraceCheckUtils]: 102: Hoare triple {2061#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,703 INFO L290 TraceCheckUtils]: 103: Hoare triple {2061#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {2061#false} is VALID [2022-02-21 04:24:40,703 INFO L290 TraceCheckUtils]: 104: Hoare triple {2061#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {2061#false} is VALID [2022-02-21 04:24:40,703 INFO L290 TraceCheckUtils]: 105: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,703 INFO L290 TraceCheckUtils]: 106: Hoare triple {2061#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {2061#false} is VALID [2022-02-21 04:24:40,704 INFO L290 TraceCheckUtils]: 107: Hoare triple {2061#false} assume 1 == ~t12_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,704 INFO L290 TraceCheckUtils]: 108: Hoare triple {2061#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,704 INFO L290 TraceCheckUtils]: 109: Hoare triple {2061#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {2061#false} is VALID [2022-02-21 04:24:40,704 INFO L290 TraceCheckUtils]: 110: Hoare triple {2061#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {2061#false} is VALID [2022-02-21 04:24:40,704 INFO L290 TraceCheckUtils]: 111: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,704 INFO L290 TraceCheckUtils]: 112: Hoare triple {2061#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {2061#false} is VALID [2022-02-21 04:24:40,705 INFO L290 TraceCheckUtils]: 113: Hoare triple {2061#false} assume 1 == ~t13_pc~0; {2061#false} is VALID [2022-02-21 04:24:40,705 INFO L290 TraceCheckUtils]: 114: Hoare triple {2061#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,705 INFO L290 TraceCheckUtils]: 115: Hoare triple {2061#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {2061#false} is VALID [2022-02-21 04:24:40,705 INFO L290 TraceCheckUtils]: 116: Hoare triple {2061#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {2061#false} is VALID [2022-02-21 04:24:40,705 INFO L290 TraceCheckUtils]: 117: Hoare triple {2061#false} assume !(0 != activate_threads_~tmp___12~0#1); {2061#false} is VALID [2022-02-21 04:24:40,705 INFO L290 TraceCheckUtils]: 118: Hoare triple {2061#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {2061#false} is VALID [2022-02-21 04:24:40,705 INFO L290 TraceCheckUtils]: 119: Hoare triple {2061#false} assume !(1 == ~t14_pc~0); {2061#false} is VALID [2022-02-21 04:24:40,706 INFO L290 TraceCheckUtils]: 120: Hoare triple {2061#false} is_transmit14_triggered_~__retres1~14#1 := 0; {2061#false} is VALID [2022-02-21 04:24:40,706 INFO L290 TraceCheckUtils]: 121: Hoare triple {2061#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {2061#false} is VALID [2022-02-21 04:24:40,706 INFO L290 TraceCheckUtils]: 122: Hoare triple {2061#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {2061#false} is VALID [2022-02-21 04:24:40,706 INFO L290 TraceCheckUtils]: 123: Hoare triple {2061#false} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {2061#false} is VALID [2022-02-21 04:24:40,706 INFO L290 TraceCheckUtils]: 124: Hoare triple {2061#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2061#false} is VALID [2022-02-21 04:24:40,706 INFO L290 TraceCheckUtils]: 125: Hoare triple {2061#false} assume !(1 == ~M_E~0); {2061#false} is VALID [2022-02-21 04:24:40,706 INFO L290 TraceCheckUtils]: 126: Hoare triple {2061#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,707 INFO L290 TraceCheckUtils]: 127: Hoare triple {2061#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,707 INFO L290 TraceCheckUtils]: 128: Hoare triple {2061#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,707 INFO L290 TraceCheckUtils]: 129: Hoare triple {2061#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,707 INFO L290 TraceCheckUtils]: 130: Hoare triple {2061#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,707 INFO L290 TraceCheckUtils]: 131: Hoare triple {2061#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,707 INFO L290 TraceCheckUtils]: 132: Hoare triple {2061#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,707 INFO L290 TraceCheckUtils]: 133: Hoare triple {2061#false} assume !(1 == ~T8_E~0); {2061#false} is VALID [2022-02-21 04:24:40,708 INFO L290 TraceCheckUtils]: 134: Hoare triple {2061#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,708 INFO L290 TraceCheckUtils]: 135: Hoare triple {2061#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,708 INFO L290 TraceCheckUtils]: 136: Hoare triple {2061#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,708 INFO L290 TraceCheckUtils]: 137: Hoare triple {2061#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,708 INFO L290 TraceCheckUtils]: 138: Hoare triple {2061#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,708 INFO L290 TraceCheckUtils]: 139: Hoare triple {2061#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,708 INFO L290 TraceCheckUtils]: 140: Hoare triple {2061#false} assume 1 == ~E_1~0;~E_1~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,709 INFO L290 TraceCheckUtils]: 141: Hoare triple {2061#false} assume !(1 == ~E_2~0); {2061#false} is VALID [2022-02-21 04:24:40,709 INFO L290 TraceCheckUtils]: 142: Hoare triple {2061#false} assume 1 == ~E_3~0;~E_3~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,709 INFO L290 TraceCheckUtils]: 143: Hoare triple {2061#false} assume 1 == ~E_4~0;~E_4~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,709 INFO L290 TraceCheckUtils]: 144: Hoare triple {2061#false} assume 1 == ~E_5~0;~E_5~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,709 INFO L290 TraceCheckUtils]: 145: Hoare triple {2061#false} assume 1 == ~E_6~0;~E_6~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,713 INFO L290 TraceCheckUtils]: 146: Hoare triple {2061#false} assume 1 == ~E_7~0;~E_7~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,714 INFO L290 TraceCheckUtils]: 147: Hoare triple {2061#false} assume 1 == ~E_8~0;~E_8~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,714 INFO L290 TraceCheckUtils]: 148: Hoare triple {2061#false} assume 1 == ~E_9~0;~E_9~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,714 INFO L290 TraceCheckUtils]: 149: Hoare triple {2061#false} assume !(1 == ~E_10~0); {2061#false} is VALID [2022-02-21 04:24:40,714 INFO L290 TraceCheckUtils]: 150: Hoare triple {2061#false} assume 1 == ~E_11~0;~E_11~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,714 INFO L290 TraceCheckUtils]: 151: Hoare triple {2061#false} assume 1 == ~E_12~0;~E_12~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,714 INFO L290 TraceCheckUtils]: 152: Hoare triple {2061#false} assume 1 == ~E_13~0;~E_13~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,715 INFO L290 TraceCheckUtils]: 153: Hoare triple {2061#false} assume 1 == ~E_14~0;~E_14~0 := 2; {2061#false} is VALID [2022-02-21 04:24:40,715 INFO L290 TraceCheckUtils]: 154: Hoare triple {2061#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {2061#false} is VALID [2022-02-21 04:24:40,715 INFO L290 TraceCheckUtils]: 155: Hoare triple {2061#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,715 INFO L290 TraceCheckUtils]: 156: Hoare triple {2061#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {2061#false} is VALID [2022-02-21 04:24:40,715 INFO L290 TraceCheckUtils]: 157: Hoare triple {2061#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {2061#false} is VALID [2022-02-21 04:24:40,715 INFO L290 TraceCheckUtils]: 158: Hoare triple {2061#false} assume !(0 == start_simulation_~tmp~3#1); {2061#false} is VALID [2022-02-21 04:24:40,715 INFO L290 TraceCheckUtils]: 159: Hoare triple {2061#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {2061#false} is VALID [2022-02-21 04:24:40,716 INFO L290 TraceCheckUtils]: 160: Hoare triple {2061#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,716 INFO L290 TraceCheckUtils]: 161: Hoare triple {2061#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {2061#false} is VALID [2022-02-21 04:24:40,716 INFO L290 TraceCheckUtils]: 162: Hoare triple {2061#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {2061#false} is VALID [2022-02-21 04:24:40,716 INFO L290 TraceCheckUtils]: 163: Hoare triple {2061#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {2061#false} is VALID [2022-02-21 04:24:40,716 INFO L290 TraceCheckUtils]: 164: Hoare triple {2061#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {2061#false} is VALID [2022-02-21 04:24:40,716 INFO L290 TraceCheckUtils]: 165: Hoare triple {2061#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {2061#false} is VALID [2022-02-21 04:24:40,716 INFO L290 TraceCheckUtils]: 166: Hoare triple {2061#false} assume !(0 != start_simulation_~tmp___0~1#1); {2061#false} is VALID [2022-02-21 04:24:40,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:40,717 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:40,717 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803034598] [2022-02-21 04:24:40,717 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1803034598] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:40,718 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:40,718 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:40,718 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404130687] [2022-02-21 04:24:40,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:40,721 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:40,722 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:40,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:24:40,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:24:40,750 INFO L87 Difference]: Start difference. First operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 83.5) internal successors, (167), 2 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:41,828 INFO L93 Difference]: Finished difference Result 2052 states and 3039 transitions. [2022-02-21 04:24:41,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:24:41,830 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 83.5) internal successors, (167), 2 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,958 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 167 edges. 167 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:41,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2052 states and 3039 transitions. [2022-02-21 04:24:42,096 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:42,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2052 states to 2047 states and 3034 transitions. [2022-02-21 04:24:42,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:24:42,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:24:42,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3034 transitions. [2022-02-21 04:24:42,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:42,236 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2022-02-21 04:24:42,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3034 transitions. [2022-02-21 04:24:42,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:24:42,306 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:42,312 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3034 transitions. Second operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,318 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3034 transitions. Second operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,322 INFO L87 Difference]: Start difference. First operand 2047 states and 3034 transitions. Second operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:42,419 INFO L93 Difference]: Finished difference Result 2047 states and 3034 transitions. [2022-02-21 04:24:42,419 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3034 transitions. [2022-02-21 04:24:42,423 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:42,423 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:42,427 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3034 transitions. [2022-02-21 04:24:42,430 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3034 transitions. [2022-02-21 04:24:42,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:42,530 INFO L93 Difference]: Finished difference Result 2047 states and 3034 transitions. [2022-02-21 04:24:42,530 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3034 transitions. [2022-02-21 04:24:42,533 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:42,533 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:42,533 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:42,534 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:42,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3034 transitions. [2022-02-21 04:24:42,640 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2022-02-21 04:24:42,640 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2022-02-21 04:24:42,640 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:42,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3034 transitions. [2022-02-21 04:24:42,666 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:42,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:42,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:42,669 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:42,669 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:42,669 INFO L791 eck$LassoCheckResult]: Stem: 5040#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 5041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 5643#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4760#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4761#L939 assume !(1 == ~m_i~0);~m_st~0 := 2; 5006#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5007#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4734#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4735#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5958#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5310#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5311#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5828#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5220#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5221#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4641#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4642#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4973#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5171#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 4218#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4219#L1342 assume !(0 == ~M_E~0); 4384#L1342-2 assume !(0 == ~T1_E~0); 4940#L1347-1 assume !(0 == ~T2_E~0); 5941#L1352-1 assume !(0 == ~T3_E~0); 5737#L1357-1 assume !(0 == ~T4_E~0); 4965#L1362-1 assume !(0 == ~T5_E~0); 4966#L1367-1 assume !(0 == ~T6_E~0); 4563#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4564#L1377-1 assume !(0 == ~T8_E~0); 4894#L1382-1 assume !(0 == ~T9_E~0); 4895#L1387-1 assume !(0 == ~T10_E~0); 5622#L1392-1 assume !(0 == ~T11_E~0); 4926#L1397-1 assume !(0 == ~T12_E~0); 4927#L1402-1 assume !(0 == ~T13_E~0); 4579#L1407-1 assume !(0 == ~T14_E~0); 4580#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5858#L1417-1 assume !(0 == ~E_2~0); 5859#L1422-1 assume !(0 == ~E_3~0); 6100#L1427-1 assume !(0 == ~E_4~0); 4767#L1432-1 assume !(0 == ~E_5~0); 4768#L1437-1 assume !(0 == ~E_6~0); 5776#L1442-1 assume !(0 == ~E_7~0); 5777#L1447-1 assume !(0 == ~E_8~0); 5619#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 4354#L1457-1 assume !(0 == ~E_10~0); 4355#L1462-1 assume !(0 == ~E_11~0); 5811#L1467-1 assume !(0 == ~E_12~0); 5823#L1472-1 assume !(0 == ~E_13~0); 5824#L1477-1 assume !(0 == ~E_14~0); 5566#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4553#L646 assume 1 == ~m_pc~0; 4554#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5230#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5245#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4643#L1666 assume !(0 != activate_threads_~tmp~1#1); 4644#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6121#L665 assume !(1 == ~t1_pc~0); 5119#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5120#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4652#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4653#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 5443#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5444#L684 assume 1 == ~t2_pc~0; 5561#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5485#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5550#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5945#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 5946#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6134#L703 assume !(1 == ~t3_pc~0); 4789#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4790#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5436#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4188#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 4189#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4674#L722 assume 1 == ~t4_pc~0; 5412#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4855#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5200#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5760#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 5267#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4385#L741 assume 1 == ~t5_pc~0; 4386#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4696#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4850#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4851#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 5530#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4941#L760 assume !(1 == ~t6_pc~0); 4788#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4787#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4645#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4646#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5367#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5368#L779 assume 1 == ~t7_pc~0; 4430#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4276#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4277#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4685#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 4708#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4709#L798 assume !(1 == ~t8_pc~0); 5990#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5913#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4432#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4433#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 6123#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4253#L817 assume 1 == ~t9_pc~0; 4254#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5048#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5049#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5571#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 4659#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4660#L836 assume !(1 == ~t10_pc~0); 4676#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4607#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4608#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4856#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 4857#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5923#L855 assume 1 == ~t11_pc~0; 5241#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5242#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5806#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5615#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 5450#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4549#L874 assume !(1 == ~t12_pc~0); 4550#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4717#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4718#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4858#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 4226#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4227#L893 assume 1 == ~t13_pc~0; 6057#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4582#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4893#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5984#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 5992#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 5993#L912 assume 1 == ~t14_pc~0; 5783#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 5784#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4552#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4484#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 4485#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5260#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 5676#L1495-2 assume !(1 == ~T1_E~0); 5677#L1500-1 assume !(1 == ~T2_E~0); 5363#L1505-1 assume !(1 == ~T3_E~0); 5364#L1510-1 assume !(1 == ~T4_E~0); 5421#L1515-1 assume !(1 == ~T5_E~0); 5422#L1520-1 assume !(1 == ~T6_E~0); 5991#L1525-1 assume !(1 == ~T7_E~0); 5701#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4654#L1535-1 assume !(1 == ~T9_E~0); 4655#L1540-1 assume !(1 == ~T10_E~0); 4147#L1545-1 assume !(1 == ~T11_E~0); 4148#L1550-1 assume !(1 == ~T12_E~0); 4396#L1555-1 assume !(1 == ~T13_E~0); 4397#L1560-1 assume !(1 == ~T14_E~0); 4697#L1565-1 assume !(1 == ~E_1~0); 6110#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5588#L1575-1 assume !(1 == ~E_3~0); 4967#L1580-1 assume !(1 == ~E_4~0); 4968#L1585-1 assume !(1 == ~E_5~0); 5438#L1590-1 assume !(1 == ~E_6~0); 5002#L1595-1 assume !(1 == ~E_7~0); 5003#L1600-1 assume !(1 == ~E_8~0); 5375#L1605-1 assume !(1 == ~E_9~0); 5376#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5893#L1615-1 assume !(1 == ~E_11~0); 4832#L1620-1 assume !(1 == ~E_12~0); 4833#L1625-1 assume !(1 == ~E_13~0); 5620#L1630-1 assume !(1 == ~E_14~0); 5001#L1635-1 assume { :end_inline_reset_delta_events } true; 4942#L2017-2 [2022-02-21 04:24:42,670 INFO L793 eck$LassoCheckResult]: Loop: 4942#L2017-2 assume !false; 4222#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4223#L1316 assume !false; 5551#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5613#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4160#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4302#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4303#L1115 assume !(0 != eval_~tmp~0#1); 5636#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5057#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5058#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5240#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5741#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5410#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5411#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5973#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6148#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6143#L1372-3 assume !(0 == ~T7_E~0); 4204#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4205#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4874#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4875#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5786#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 6096#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5354#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 4510#L1412-3 assume !(0 == ~E_1~0); 4511#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5275#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5276#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5970#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5657#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5369#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5370#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4270#L1452-3 assume !(0 == ~E_9~0); 4271#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5909#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5910#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5714#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5715#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 4508#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4509#L646-42 assume 1 == ~m_pc~0; 5094#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5942#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5943#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6081#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6082#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5874#L665-42 assume 1 == ~t1_pc~0; 5835#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5837#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6023#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4677#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4678#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6147#L684-42 assume 1 == ~t2_pc~0; 5526#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5527#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6137#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5306#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5307#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5429#L703-42 assume 1 == ~t3_pc~0; 5627#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5628#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4946#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4947#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5721#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5341#L722-42 assume 1 == ~t4_pc~0; 5342#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5752#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4995#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4822#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4823#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6117#L741-42 assume !(1 == ~t5_pc~0); 5734#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 5204#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5205#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6150#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5112#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5113#L760-42 assume 1 == ~t6_pc~0; 5248#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5382#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5383#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5771#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 5064#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5065#L779-42 assume !(1 == ~t7_pc~0); 5841#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 5842#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4749#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4750#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4605#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4606#L798-42 assume 1 == ~t8_pc~0; 5056#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4217#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5960#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5406#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4436#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4437#L817-42 assume 1 == ~t9_pc~0; 5210#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4720#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4721#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4847#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5652#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5653#L836-42 assume 1 == ~t10_pc~0; 5745#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4758#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4759#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6060#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6061#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6102#L855-42 assume 1 == ~t11_pc~0; 6115#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4309#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4310#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5059#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5822#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4923#L874-42 assume 1 == ~t12_pc~0; 4924#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 5163#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4224#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4225#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4478#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4479#L893-42 assume 1 == ~t13_pc~0; 5681#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5463#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5478#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5380#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 4852#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 4853#L912-42 assume 1 == ~t14_pc~0; 6097#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 4170#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4171#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5751#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 4598#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4599#L1495-3 assume !(1 == ~M_E~0); 5214#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5642#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5735#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4828#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4791#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4792#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5449#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5672#L1530-3 assume !(1 == ~T8_E~0); 4637#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4638#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4675#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5932#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 6041#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5081#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 5082#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5697#L1570-3 assume !(1 == ~E_2~0); 5648#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5649#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6004#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6048#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6094#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5471#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5472#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5947#L1610-3 assume !(1 == ~E_10~0); 4834#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4835#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5439#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5440#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 5344#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4775#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4380#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 5118#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5674#L2036 assume !(0 == start_simulation_~tmp~3#1); 5675#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5827#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4987#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 6005#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5387#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5388#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6108#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 6109#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 4942#L2017-2 [2022-02-21 04:24:42,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:42,671 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 2 times [2022-02-21 04:24:42,671 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:42,671 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [758875275] [2022-02-21 04:24:42,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:42,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:42,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:42,712 INFO L290 TraceCheckUtils]: 0: Hoare triple {10258#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {10258#true} is VALID [2022-02-21 04:24:42,713 INFO L290 TraceCheckUtils]: 1: Hoare triple {10258#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {10260#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:42,713 INFO L290 TraceCheckUtils]: 2: Hoare triple {10260#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10260#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:42,713 INFO L290 TraceCheckUtils]: 3: Hoare triple {10260#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10260#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:42,714 INFO L290 TraceCheckUtils]: 4: Hoare triple {10260#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,714 INFO L290 TraceCheckUtils]: 5: Hoare triple {10259#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10259#false} is VALID [2022-02-21 04:24:42,714 INFO L290 TraceCheckUtils]: 6: Hoare triple {10259#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,714 INFO L290 TraceCheckUtils]: 7: Hoare triple {10259#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,714 INFO L290 TraceCheckUtils]: 8: Hoare triple {10259#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,714 INFO L290 TraceCheckUtils]: 9: Hoare triple {10259#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,714 INFO L290 TraceCheckUtils]: 10: Hoare triple {10259#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,714 INFO L290 TraceCheckUtils]: 11: Hoare triple {10259#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,715 INFO L290 TraceCheckUtils]: 12: Hoare triple {10259#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,715 INFO L290 TraceCheckUtils]: 13: Hoare triple {10259#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {10259#false} is VALID [2022-02-21 04:24:42,715 INFO L290 TraceCheckUtils]: 14: Hoare triple {10259#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,715 INFO L290 TraceCheckUtils]: 15: Hoare triple {10259#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,715 INFO L290 TraceCheckUtils]: 16: Hoare triple {10259#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,715 INFO L290 TraceCheckUtils]: 17: Hoare triple {10259#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,715 INFO L290 TraceCheckUtils]: 18: Hoare triple {10259#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,716 INFO L290 TraceCheckUtils]: 19: Hoare triple {10259#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10259#false} is VALID [2022-02-21 04:24:42,716 INFO L290 TraceCheckUtils]: 20: Hoare triple {10259#false} assume !(0 == ~M_E~0); {10259#false} is VALID [2022-02-21 04:24:42,716 INFO L290 TraceCheckUtils]: 21: Hoare triple {10259#false} assume !(0 == ~T1_E~0); {10259#false} is VALID [2022-02-21 04:24:42,716 INFO L290 TraceCheckUtils]: 22: Hoare triple {10259#false} assume !(0 == ~T2_E~0); {10259#false} is VALID [2022-02-21 04:24:42,716 INFO L290 TraceCheckUtils]: 23: Hoare triple {10259#false} assume !(0 == ~T3_E~0); {10259#false} is VALID [2022-02-21 04:24:42,716 INFO L290 TraceCheckUtils]: 24: Hoare triple {10259#false} assume !(0 == ~T4_E~0); {10259#false} is VALID [2022-02-21 04:24:42,716 INFO L290 TraceCheckUtils]: 25: Hoare triple {10259#false} assume !(0 == ~T5_E~0); {10259#false} is VALID [2022-02-21 04:24:42,716 INFO L290 TraceCheckUtils]: 26: Hoare triple {10259#false} assume !(0 == ~T6_E~0); {10259#false} is VALID [2022-02-21 04:24:42,717 INFO L290 TraceCheckUtils]: 27: Hoare triple {10259#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {10259#false} is VALID [2022-02-21 04:24:42,717 INFO L290 TraceCheckUtils]: 28: Hoare triple {10259#false} assume !(0 == ~T8_E~0); {10259#false} is VALID [2022-02-21 04:24:42,717 INFO L290 TraceCheckUtils]: 29: Hoare triple {10259#false} assume !(0 == ~T9_E~0); {10259#false} is VALID [2022-02-21 04:24:42,717 INFO L290 TraceCheckUtils]: 30: Hoare triple {10259#false} assume !(0 == ~T10_E~0); {10259#false} is VALID [2022-02-21 04:24:42,717 INFO L290 TraceCheckUtils]: 31: Hoare triple {10259#false} assume !(0 == ~T11_E~0); {10259#false} is VALID [2022-02-21 04:24:42,717 INFO L290 TraceCheckUtils]: 32: Hoare triple {10259#false} assume !(0 == ~T12_E~0); {10259#false} is VALID [2022-02-21 04:24:42,717 INFO L290 TraceCheckUtils]: 33: Hoare triple {10259#false} assume !(0 == ~T13_E~0); {10259#false} is VALID [2022-02-21 04:24:42,718 INFO L290 TraceCheckUtils]: 34: Hoare triple {10259#false} assume !(0 == ~T14_E~0); {10259#false} is VALID [2022-02-21 04:24:42,718 INFO L290 TraceCheckUtils]: 35: Hoare triple {10259#false} assume 0 == ~E_1~0;~E_1~0 := 1; {10259#false} is VALID [2022-02-21 04:24:42,718 INFO L290 TraceCheckUtils]: 36: Hoare triple {10259#false} assume !(0 == ~E_2~0); {10259#false} is VALID [2022-02-21 04:24:42,718 INFO L290 TraceCheckUtils]: 37: Hoare triple {10259#false} assume !(0 == ~E_3~0); {10259#false} is VALID [2022-02-21 04:24:42,718 INFO L290 TraceCheckUtils]: 38: Hoare triple {10259#false} assume !(0 == ~E_4~0); {10259#false} is VALID [2022-02-21 04:24:42,718 INFO L290 TraceCheckUtils]: 39: Hoare triple {10259#false} assume !(0 == ~E_5~0); {10259#false} is VALID [2022-02-21 04:24:42,718 INFO L290 TraceCheckUtils]: 40: Hoare triple {10259#false} assume !(0 == ~E_6~0); {10259#false} is VALID [2022-02-21 04:24:42,718 INFO L290 TraceCheckUtils]: 41: Hoare triple {10259#false} assume !(0 == ~E_7~0); {10259#false} is VALID [2022-02-21 04:24:42,719 INFO L290 TraceCheckUtils]: 42: Hoare triple {10259#false} assume !(0 == ~E_8~0); {10259#false} is VALID [2022-02-21 04:24:42,719 INFO L290 TraceCheckUtils]: 43: Hoare triple {10259#false} assume 0 == ~E_9~0;~E_9~0 := 1; {10259#false} is VALID [2022-02-21 04:24:42,719 INFO L290 TraceCheckUtils]: 44: Hoare triple {10259#false} assume !(0 == ~E_10~0); {10259#false} is VALID [2022-02-21 04:24:42,719 INFO L290 TraceCheckUtils]: 45: Hoare triple {10259#false} assume !(0 == ~E_11~0); {10259#false} is VALID [2022-02-21 04:24:42,719 INFO L290 TraceCheckUtils]: 46: Hoare triple {10259#false} assume !(0 == ~E_12~0); {10259#false} is VALID [2022-02-21 04:24:42,719 INFO L290 TraceCheckUtils]: 47: Hoare triple {10259#false} assume !(0 == ~E_13~0); {10259#false} is VALID [2022-02-21 04:24:42,719 INFO L290 TraceCheckUtils]: 48: Hoare triple {10259#false} assume !(0 == ~E_14~0); {10259#false} is VALID [2022-02-21 04:24:42,720 INFO L290 TraceCheckUtils]: 49: Hoare triple {10259#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10259#false} is VALID [2022-02-21 04:24:42,720 INFO L290 TraceCheckUtils]: 50: Hoare triple {10259#false} assume 1 == ~m_pc~0; {10259#false} is VALID [2022-02-21 04:24:42,720 INFO L290 TraceCheckUtils]: 51: Hoare triple {10259#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {10259#false} is VALID [2022-02-21 04:24:42,720 INFO L290 TraceCheckUtils]: 52: Hoare triple {10259#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10259#false} is VALID [2022-02-21 04:24:42,720 INFO L290 TraceCheckUtils]: 53: Hoare triple {10259#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10259#false} is VALID [2022-02-21 04:24:42,720 INFO L290 TraceCheckUtils]: 54: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp~1#1); {10259#false} is VALID [2022-02-21 04:24:42,720 INFO L290 TraceCheckUtils]: 55: Hoare triple {10259#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10259#false} is VALID [2022-02-21 04:24:42,721 INFO L290 TraceCheckUtils]: 56: Hoare triple {10259#false} assume !(1 == ~t1_pc~0); {10259#false} is VALID [2022-02-21 04:24:42,721 INFO L290 TraceCheckUtils]: 57: Hoare triple {10259#false} is_transmit1_triggered_~__retres1~1#1 := 0; {10259#false} is VALID [2022-02-21 04:24:42,721 INFO L290 TraceCheckUtils]: 58: Hoare triple {10259#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10259#false} is VALID [2022-02-21 04:24:42,721 INFO L290 TraceCheckUtils]: 59: Hoare triple {10259#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10259#false} is VALID [2022-02-21 04:24:42,721 INFO L290 TraceCheckUtils]: 60: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___0~0#1); {10259#false} is VALID [2022-02-21 04:24:42,721 INFO L290 TraceCheckUtils]: 61: Hoare triple {10259#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10259#false} is VALID [2022-02-21 04:24:42,721 INFO L290 TraceCheckUtils]: 62: Hoare triple {10259#false} assume 1 == ~t2_pc~0; {10259#false} is VALID [2022-02-21 04:24:42,721 INFO L290 TraceCheckUtils]: 63: Hoare triple {10259#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10259#false} is VALID [2022-02-21 04:24:42,722 INFO L290 TraceCheckUtils]: 64: Hoare triple {10259#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10259#false} is VALID [2022-02-21 04:24:42,722 INFO L290 TraceCheckUtils]: 65: Hoare triple {10259#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10259#false} is VALID [2022-02-21 04:24:42,722 INFO L290 TraceCheckUtils]: 66: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___1~0#1); {10259#false} is VALID [2022-02-21 04:24:42,722 INFO L290 TraceCheckUtils]: 67: Hoare triple {10259#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10259#false} is VALID [2022-02-21 04:24:42,722 INFO L290 TraceCheckUtils]: 68: Hoare triple {10259#false} assume !(1 == ~t3_pc~0); {10259#false} is VALID [2022-02-21 04:24:42,722 INFO L290 TraceCheckUtils]: 69: Hoare triple {10259#false} is_transmit3_triggered_~__retres1~3#1 := 0; {10259#false} is VALID [2022-02-21 04:24:42,722 INFO L290 TraceCheckUtils]: 70: Hoare triple {10259#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10259#false} is VALID [2022-02-21 04:24:42,723 INFO L290 TraceCheckUtils]: 71: Hoare triple {10259#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10259#false} is VALID [2022-02-21 04:24:42,723 INFO L290 TraceCheckUtils]: 72: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___2~0#1); {10259#false} is VALID [2022-02-21 04:24:42,723 INFO L290 TraceCheckUtils]: 73: Hoare triple {10259#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10259#false} is VALID [2022-02-21 04:24:42,723 INFO L290 TraceCheckUtils]: 74: Hoare triple {10259#false} assume 1 == ~t4_pc~0; {10259#false} is VALID [2022-02-21 04:24:42,723 INFO L290 TraceCheckUtils]: 75: Hoare triple {10259#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10259#false} is VALID [2022-02-21 04:24:42,723 INFO L290 TraceCheckUtils]: 76: Hoare triple {10259#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10259#false} is VALID [2022-02-21 04:24:42,723 INFO L290 TraceCheckUtils]: 77: Hoare triple {10259#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10259#false} is VALID [2022-02-21 04:24:42,723 INFO L290 TraceCheckUtils]: 78: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___3~0#1); {10259#false} is VALID [2022-02-21 04:24:42,724 INFO L290 TraceCheckUtils]: 79: Hoare triple {10259#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10259#false} is VALID [2022-02-21 04:24:42,724 INFO L290 TraceCheckUtils]: 80: Hoare triple {10259#false} assume 1 == ~t5_pc~0; {10259#false} is VALID [2022-02-21 04:24:42,724 INFO L290 TraceCheckUtils]: 81: Hoare triple {10259#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10259#false} is VALID [2022-02-21 04:24:42,724 INFO L290 TraceCheckUtils]: 82: Hoare triple {10259#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10259#false} is VALID [2022-02-21 04:24:42,724 INFO L290 TraceCheckUtils]: 83: Hoare triple {10259#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10259#false} is VALID [2022-02-21 04:24:42,724 INFO L290 TraceCheckUtils]: 84: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___4~0#1); {10259#false} is VALID [2022-02-21 04:24:42,724 INFO L290 TraceCheckUtils]: 85: Hoare triple {10259#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10259#false} is VALID [2022-02-21 04:24:42,725 INFO L290 TraceCheckUtils]: 86: Hoare triple {10259#false} assume !(1 == ~t6_pc~0); {10259#false} is VALID [2022-02-21 04:24:42,725 INFO L290 TraceCheckUtils]: 87: Hoare triple {10259#false} is_transmit6_triggered_~__retres1~6#1 := 0; {10259#false} is VALID [2022-02-21 04:24:42,725 INFO L290 TraceCheckUtils]: 88: Hoare triple {10259#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10259#false} is VALID [2022-02-21 04:24:42,725 INFO L290 TraceCheckUtils]: 89: Hoare triple {10259#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {10259#false} is VALID [2022-02-21 04:24:42,725 INFO L290 TraceCheckUtils]: 90: Hoare triple {10259#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {10259#false} is VALID [2022-02-21 04:24:42,725 INFO L290 TraceCheckUtils]: 91: Hoare triple {10259#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10259#false} is VALID [2022-02-21 04:24:42,725 INFO L290 TraceCheckUtils]: 92: Hoare triple {10259#false} assume 1 == ~t7_pc~0; {10259#false} is VALID [2022-02-21 04:24:42,725 INFO L290 TraceCheckUtils]: 93: Hoare triple {10259#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {10259#false} is VALID [2022-02-21 04:24:42,726 INFO L290 TraceCheckUtils]: 94: Hoare triple {10259#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10259#false} is VALID [2022-02-21 04:24:42,726 INFO L290 TraceCheckUtils]: 95: Hoare triple {10259#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {10259#false} is VALID [2022-02-21 04:24:42,726 INFO L290 TraceCheckUtils]: 96: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___6~0#1); {10259#false} is VALID [2022-02-21 04:24:42,726 INFO L290 TraceCheckUtils]: 97: Hoare triple {10259#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10259#false} is VALID [2022-02-21 04:24:42,726 INFO L290 TraceCheckUtils]: 98: Hoare triple {10259#false} assume !(1 == ~t8_pc~0); {10259#false} is VALID [2022-02-21 04:24:42,726 INFO L290 TraceCheckUtils]: 99: Hoare triple {10259#false} is_transmit8_triggered_~__retres1~8#1 := 0; {10259#false} is VALID [2022-02-21 04:24:42,726 INFO L290 TraceCheckUtils]: 100: Hoare triple {10259#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10259#false} is VALID [2022-02-21 04:24:42,727 INFO L290 TraceCheckUtils]: 101: Hoare triple {10259#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {10259#false} is VALID [2022-02-21 04:24:42,727 INFO L290 TraceCheckUtils]: 102: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___7~0#1); {10259#false} is VALID [2022-02-21 04:24:42,727 INFO L290 TraceCheckUtils]: 103: Hoare triple {10259#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10259#false} is VALID [2022-02-21 04:24:42,727 INFO L290 TraceCheckUtils]: 104: Hoare triple {10259#false} assume 1 == ~t9_pc~0; {10259#false} is VALID [2022-02-21 04:24:42,727 INFO L290 TraceCheckUtils]: 105: Hoare triple {10259#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {10259#false} is VALID [2022-02-21 04:24:42,727 INFO L290 TraceCheckUtils]: 106: Hoare triple {10259#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10259#false} is VALID [2022-02-21 04:24:42,727 INFO L290 TraceCheckUtils]: 107: Hoare triple {10259#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {10259#false} is VALID [2022-02-21 04:24:42,727 INFO L290 TraceCheckUtils]: 108: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___8~0#1); {10259#false} is VALID [2022-02-21 04:24:42,728 INFO L290 TraceCheckUtils]: 109: Hoare triple {10259#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {10259#false} is VALID [2022-02-21 04:24:42,728 INFO L290 TraceCheckUtils]: 110: Hoare triple {10259#false} assume !(1 == ~t10_pc~0); {10259#false} is VALID [2022-02-21 04:24:42,728 INFO L290 TraceCheckUtils]: 111: Hoare triple {10259#false} is_transmit10_triggered_~__retres1~10#1 := 0; {10259#false} is VALID [2022-02-21 04:24:42,728 INFO L290 TraceCheckUtils]: 112: Hoare triple {10259#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {10259#false} is VALID [2022-02-21 04:24:42,728 INFO L290 TraceCheckUtils]: 113: Hoare triple {10259#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {10259#false} is VALID [2022-02-21 04:24:42,728 INFO L290 TraceCheckUtils]: 114: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___9~0#1); {10259#false} is VALID [2022-02-21 04:24:42,728 INFO L290 TraceCheckUtils]: 115: Hoare triple {10259#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {10259#false} is VALID [2022-02-21 04:24:42,729 INFO L290 TraceCheckUtils]: 116: Hoare triple {10259#false} assume 1 == ~t11_pc~0; {10259#false} is VALID [2022-02-21 04:24:42,729 INFO L290 TraceCheckUtils]: 117: Hoare triple {10259#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {10259#false} is VALID [2022-02-21 04:24:42,729 INFO L290 TraceCheckUtils]: 118: Hoare triple {10259#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {10259#false} is VALID [2022-02-21 04:24:42,729 INFO L290 TraceCheckUtils]: 119: Hoare triple {10259#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {10259#false} is VALID [2022-02-21 04:24:42,729 INFO L290 TraceCheckUtils]: 120: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___10~0#1); {10259#false} is VALID [2022-02-21 04:24:42,729 INFO L290 TraceCheckUtils]: 121: Hoare triple {10259#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {10259#false} is VALID [2022-02-21 04:24:42,729 INFO L290 TraceCheckUtils]: 122: Hoare triple {10259#false} assume !(1 == ~t12_pc~0); {10259#false} is VALID [2022-02-21 04:24:42,730 INFO L290 TraceCheckUtils]: 123: Hoare triple {10259#false} is_transmit12_triggered_~__retres1~12#1 := 0; {10259#false} is VALID [2022-02-21 04:24:42,730 INFO L290 TraceCheckUtils]: 124: Hoare triple {10259#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {10259#false} is VALID [2022-02-21 04:24:42,730 INFO L290 TraceCheckUtils]: 125: Hoare triple {10259#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {10259#false} is VALID [2022-02-21 04:24:42,730 INFO L290 TraceCheckUtils]: 126: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___11~0#1); {10259#false} is VALID [2022-02-21 04:24:42,730 INFO L290 TraceCheckUtils]: 127: Hoare triple {10259#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {10259#false} is VALID [2022-02-21 04:24:42,730 INFO L290 TraceCheckUtils]: 128: Hoare triple {10259#false} assume 1 == ~t13_pc~0; {10259#false} is VALID [2022-02-21 04:24:42,730 INFO L290 TraceCheckUtils]: 129: Hoare triple {10259#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {10259#false} is VALID [2022-02-21 04:24:42,730 INFO L290 TraceCheckUtils]: 130: Hoare triple {10259#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {10259#false} is VALID [2022-02-21 04:24:42,731 INFO L290 TraceCheckUtils]: 131: Hoare triple {10259#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {10259#false} is VALID [2022-02-21 04:24:42,731 INFO L290 TraceCheckUtils]: 132: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___12~0#1); {10259#false} is VALID [2022-02-21 04:24:42,731 INFO L290 TraceCheckUtils]: 133: Hoare triple {10259#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {10259#false} is VALID [2022-02-21 04:24:42,731 INFO L290 TraceCheckUtils]: 134: Hoare triple {10259#false} assume 1 == ~t14_pc~0; {10259#false} is VALID [2022-02-21 04:24:42,731 INFO L290 TraceCheckUtils]: 135: Hoare triple {10259#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {10259#false} is VALID [2022-02-21 04:24:42,731 INFO L290 TraceCheckUtils]: 136: Hoare triple {10259#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {10259#false} is VALID [2022-02-21 04:24:42,731 INFO L290 TraceCheckUtils]: 137: Hoare triple {10259#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {10259#false} is VALID [2022-02-21 04:24:42,732 INFO L290 TraceCheckUtils]: 138: Hoare triple {10259#false} assume !(0 != activate_threads_~tmp___13~0#1); {10259#false} is VALID [2022-02-21 04:24:42,732 INFO L290 TraceCheckUtils]: 139: Hoare triple {10259#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10259#false} is VALID [2022-02-21 04:24:42,732 INFO L290 TraceCheckUtils]: 140: Hoare triple {10259#false} assume 1 == ~M_E~0;~M_E~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,732 INFO L290 TraceCheckUtils]: 141: Hoare triple {10259#false} assume !(1 == ~T1_E~0); {10259#false} is VALID [2022-02-21 04:24:42,732 INFO L290 TraceCheckUtils]: 142: Hoare triple {10259#false} assume !(1 == ~T2_E~0); {10259#false} is VALID [2022-02-21 04:24:42,732 INFO L290 TraceCheckUtils]: 143: Hoare triple {10259#false} assume !(1 == ~T3_E~0); {10259#false} is VALID [2022-02-21 04:24:42,732 INFO L290 TraceCheckUtils]: 144: Hoare triple {10259#false} assume !(1 == ~T4_E~0); {10259#false} is VALID [2022-02-21 04:24:42,732 INFO L290 TraceCheckUtils]: 145: Hoare triple {10259#false} assume !(1 == ~T5_E~0); {10259#false} is VALID [2022-02-21 04:24:42,733 INFO L290 TraceCheckUtils]: 146: Hoare triple {10259#false} assume !(1 == ~T6_E~0); {10259#false} is VALID [2022-02-21 04:24:42,733 INFO L290 TraceCheckUtils]: 147: Hoare triple {10259#false} assume !(1 == ~T7_E~0); {10259#false} is VALID [2022-02-21 04:24:42,733 INFO L290 TraceCheckUtils]: 148: Hoare triple {10259#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,733 INFO L290 TraceCheckUtils]: 149: Hoare triple {10259#false} assume !(1 == ~T9_E~0); {10259#false} is VALID [2022-02-21 04:24:42,733 INFO L290 TraceCheckUtils]: 150: Hoare triple {10259#false} assume !(1 == ~T10_E~0); {10259#false} is VALID [2022-02-21 04:24:42,733 INFO L290 TraceCheckUtils]: 151: Hoare triple {10259#false} assume !(1 == ~T11_E~0); {10259#false} is VALID [2022-02-21 04:24:42,733 INFO L290 TraceCheckUtils]: 152: Hoare triple {10259#false} assume !(1 == ~T12_E~0); {10259#false} is VALID [2022-02-21 04:24:42,734 INFO L290 TraceCheckUtils]: 153: Hoare triple {10259#false} assume !(1 == ~T13_E~0); {10259#false} is VALID [2022-02-21 04:24:42,734 INFO L290 TraceCheckUtils]: 154: Hoare triple {10259#false} assume !(1 == ~T14_E~0); {10259#false} is VALID [2022-02-21 04:24:42,734 INFO L290 TraceCheckUtils]: 155: Hoare triple {10259#false} assume !(1 == ~E_1~0); {10259#false} is VALID [2022-02-21 04:24:42,734 INFO L290 TraceCheckUtils]: 156: Hoare triple {10259#false} assume 1 == ~E_2~0;~E_2~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,734 INFO L290 TraceCheckUtils]: 157: Hoare triple {10259#false} assume !(1 == ~E_3~0); {10259#false} is VALID [2022-02-21 04:24:42,734 INFO L290 TraceCheckUtils]: 158: Hoare triple {10259#false} assume !(1 == ~E_4~0); {10259#false} is VALID [2022-02-21 04:24:42,734 INFO L290 TraceCheckUtils]: 159: Hoare triple {10259#false} assume !(1 == ~E_5~0); {10259#false} is VALID [2022-02-21 04:24:42,735 INFO L290 TraceCheckUtils]: 160: Hoare triple {10259#false} assume !(1 == ~E_6~0); {10259#false} is VALID [2022-02-21 04:24:42,735 INFO L290 TraceCheckUtils]: 161: Hoare triple {10259#false} assume !(1 == ~E_7~0); {10259#false} is VALID [2022-02-21 04:24:42,735 INFO L290 TraceCheckUtils]: 162: Hoare triple {10259#false} assume !(1 == ~E_8~0); {10259#false} is VALID [2022-02-21 04:24:42,735 INFO L290 TraceCheckUtils]: 163: Hoare triple {10259#false} assume !(1 == ~E_9~0); {10259#false} is VALID [2022-02-21 04:24:42,735 INFO L290 TraceCheckUtils]: 164: Hoare triple {10259#false} assume 1 == ~E_10~0;~E_10~0 := 2; {10259#false} is VALID [2022-02-21 04:24:42,735 INFO L290 TraceCheckUtils]: 165: Hoare triple {10259#false} assume !(1 == ~E_11~0); {10259#false} is VALID [2022-02-21 04:24:42,735 INFO L290 TraceCheckUtils]: 166: Hoare triple {10259#false} assume !(1 == ~E_12~0); {10259#false} is VALID [2022-02-21 04:24:42,736 INFO L290 TraceCheckUtils]: 167: Hoare triple {10259#false} assume !(1 == ~E_13~0); {10259#false} is VALID [2022-02-21 04:24:42,736 INFO L290 TraceCheckUtils]: 168: Hoare triple {10259#false} assume !(1 == ~E_14~0); {10259#false} is VALID [2022-02-21 04:24:42,736 INFO L290 TraceCheckUtils]: 169: Hoare triple {10259#false} assume { :end_inline_reset_delta_events } true; {10259#false} is VALID [2022-02-21 04:24:42,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:42,737 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:42,737 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [758875275] [2022-02-21 04:24:42,737 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [758875275] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:42,737 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:42,737 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:42,737 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661727498] [2022-02-21 04:24:42,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:42,738 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:42,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:42,738 INFO L85 PathProgramCache]: Analyzing trace with hash 1105916303, now seen corresponding path program 1 times [2022-02-21 04:24:42,738 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:42,739 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056937745] [2022-02-21 04:24:42,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:42,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:42,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:42,807 INFO L290 TraceCheckUtils]: 0: Hoare triple {10261#true} assume !false; {10261#true} is VALID [2022-02-21 04:24:42,808 INFO L290 TraceCheckUtils]: 1: Hoare triple {10261#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10261#true} is VALID [2022-02-21 04:24:42,808 INFO L290 TraceCheckUtils]: 2: Hoare triple {10261#true} assume !false; {10261#true} is VALID [2022-02-21 04:24:42,808 INFO L290 TraceCheckUtils]: 3: Hoare triple {10261#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {10261#true} is VALID [2022-02-21 04:24:42,808 INFO L290 TraceCheckUtils]: 4: Hoare triple {10261#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {10261#true} is VALID [2022-02-21 04:24:42,808 INFO L290 TraceCheckUtils]: 5: Hoare triple {10261#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {10261#true} is VALID [2022-02-21 04:24:42,808 INFO L290 TraceCheckUtils]: 6: Hoare triple {10261#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {10261#true} is VALID [2022-02-21 04:24:42,809 INFO L290 TraceCheckUtils]: 7: Hoare triple {10261#true} assume !(0 != eval_~tmp~0#1); {10261#true} is VALID [2022-02-21 04:24:42,809 INFO L290 TraceCheckUtils]: 8: Hoare triple {10261#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10261#true} is VALID [2022-02-21 04:24:42,809 INFO L290 TraceCheckUtils]: 9: Hoare triple {10261#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10261#true} is VALID [2022-02-21 04:24:42,809 INFO L290 TraceCheckUtils]: 10: Hoare triple {10261#true} assume 0 == ~M_E~0;~M_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,810 INFO L290 TraceCheckUtils]: 11: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,810 INFO L290 TraceCheckUtils]: 12: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,810 INFO L290 TraceCheckUtils]: 13: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,810 INFO L290 TraceCheckUtils]: 14: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,811 INFO L290 TraceCheckUtils]: 15: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,811 INFO L290 TraceCheckUtils]: 16: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,811 INFO L290 TraceCheckUtils]: 17: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,812 INFO L290 TraceCheckUtils]: 18: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,812 INFO L290 TraceCheckUtils]: 19: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,812 INFO L290 TraceCheckUtils]: 20: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,812 INFO L290 TraceCheckUtils]: 21: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,813 INFO L290 TraceCheckUtils]: 22: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,813 INFO L290 TraceCheckUtils]: 23: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,813 INFO L290 TraceCheckUtils]: 24: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,814 INFO L290 TraceCheckUtils]: 25: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,814 INFO L290 TraceCheckUtils]: 26: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,814 INFO L290 TraceCheckUtils]: 27: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,815 INFO L290 TraceCheckUtils]: 28: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,815 INFO L290 TraceCheckUtils]: 29: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,815 INFO L290 TraceCheckUtils]: 30: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,815 INFO L290 TraceCheckUtils]: 31: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,816 INFO L290 TraceCheckUtils]: 32: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,816 INFO L290 TraceCheckUtils]: 33: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,816 INFO L290 TraceCheckUtils]: 34: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,817 INFO L290 TraceCheckUtils]: 35: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,817 INFO L290 TraceCheckUtils]: 36: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,817 INFO L290 TraceCheckUtils]: 37: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,817 INFO L290 TraceCheckUtils]: 38: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,818 INFO L290 TraceCheckUtils]: 39: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,818 INFO L290 TraceCheckUtils]: 40: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,818 INFO L290 TraceCheckUtils]: 41: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,819 INFO L290 TraceCheckUtils]: 42: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,819 INFO L290 TraceCheckUtils]: 43: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,819 INFO L290 TraceCheckUtils]: 44: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,819 INFO L290 TraceCheckUtils]: 45: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,820 INFO L290 TraceCheckUtils]: 46: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,820 INFO L290 TraceCheckUtils]: 47: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,820 INFO L290 TraceCheckUtils]: 48: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,821 INFO L290 TraceCheckUtils]: 49: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,821 INFO L290 TraceCheckUtils]: 50: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,821 INFO L290 TraceCheckUtils]: 51: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,821 INFO L290 TraceCheckUtils]: 52: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,822 INFO L290 TraceCheckUtils]: 53: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,823 INFO L290 TraceCheckUtils]: 54: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,823 INFO L290 TraceCheckUtils]: 55: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,823 INFO L290 TraceCheckUtils]: 56: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,824 INFO L290 TraceCheckUtils]: 57: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,824 INFO L290 TraceCheckUtils]: 58: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,824 INFO L290 TraceCheckUtils]: 59: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,825 INFO L290 TraceCheckUtils]: 60: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,825 INFO L290 TraceCheckUtils]: 61: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,825 INFO L290 TraceCheckUtils]: 62: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,825 INFO L290 TraceCheckUtils]: 63: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,826 INFO L290 TraceCheckUtils]: 64: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,826 INFO L290 TraceCheckUtils]: 65: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,826 INFO L290 TraceCheckUtils]: 66: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,827 INFO L290 TraceCheckUtils]: 67: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,827 INFO L290 TraceCheckUtils]: 68: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,827 INFO L290 TraceCheckUtils]: 69: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,828 INFO L290 TraceCheckUtils]: 70: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,828 INFO L290 TraceCheckUtils]: 71: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,828 INFO L290 TraceCheckUtils]: 72: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,828 INFO L290 TraceCheckUtils]: 73: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,829 INFO L290 TraceCheckUtils]: 74: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,829 INFO L290 TraceCheckUtils]: 75: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,829 INFO L290 TraceCheckUtils]: 76: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,830 INFO L290 TraceCheckUtils]: 77: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,830 INFO L290 TraceCheckUtils]: 78: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,830 INFO L290 TraceCheckUtils]: 79: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,830 INFO L290 TraceCheckUtils]: 80: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,831 INFO L290 TraceCheckUtils]: 81: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,831 INFO L290 TraceCheckUtils]: 82: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,831 INFO L290 TraceCheckUtils]: 83: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,832 INFO L290 TraceCheckUtils]: 84: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,832 INFO L290 TraceCheckUtils]: 85: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,832 INFO L290 TraceCheckUtils]: 86: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,832 INFO L290 TraceCheckUtils]: 87: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,833 INFO L290 TraceCheckUtils]: 88: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,833 INFO L290 TraceCheckUtils]: 89: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,833 INFO L290 TraceCheckUtils]: 90: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,834 INFO L290 TraceCheckUtils]: 91: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,834 INFO L290 TraceCheckUtils]: 92: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,834 INFO L290 TraceCheckUtils]: 93: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,834 INFO L290 TraceCheckUtils]: 94: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,835 INFO L290 TraceCheckUtils]: 95: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,835 INFO L290 TraceCheckUtils]: 96: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,835 INFO L290 TraceCheckUtils]: 97: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,836 INFO L290 TraceCheckUtils]: 98: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,836 INFO L290 TraceCheckUtils]: 99: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,836 INFO L290 TraceCheckUtils]: 100: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,836 INFO L290 TraceCheckUtils]: 101: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,837 INFO L290 TraceCheckUtils]: 102: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,837 INFO L290 TraceCheckUtils]: 103: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,837 INFO L290 TraceCheckUtils]: 104: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,838 INFO L290 TraceCheckUtils]: 105: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,838 INFO L290 TraceCheckUtils]: 106: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,838 INFO L290 TraceCheckUtils]: 107: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,838 INFO L290 TraceCheckUtils]: 108: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,839 INFO L290 TraceCheckUtils]: 109: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,839 INFO L290 TraceCheckUtils]: 110: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,839 INFO L290 TraceCheckUtils]: 111: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,840 INFO L290 TraceCheckUtils]: 112: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,840 INFO L290 TraceCheckUtils]: 113: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,840 INFO L290 TraceCheckUtils]: 114: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,840 INFO L290 TraceCheckUtils]: 115: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,841 INFO L290 TraceCheckUtils]: 116: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,841 INFO L290 TraceCheckUtils]: 117: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,841 INFO L290 TraceCheckUtils]: 118: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,842 INFO L290 TraceCheckUtils]: 119: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,842 INFO L290 TraceCheckUtils]: 120: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,842 INFO L290 TraceCheckUtils]: 121: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,844 INFO L290 TraceCheckUtils]: 122: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,844 INFO L290 TraceCheckUtils]: 123: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,844 INFO L290 TraceCheckUtils]: 124: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t14_pc~0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,845 INFO L290 TraceCheckUtils]: 125: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,845 INFO L290 TraceCheckUtils]: 126: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,846 INFO L290 TraceCheckUtils]: 127: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,846 INFO L290 TraceCheckUtils]: 128: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,846 INFO L290 TraceCheckUtils]: 129: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10263#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:42,847 INFO L290 TraceCheckUtils]: 130: Hoare triple {10263#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {10262#false} is VALID [2022-02-21 04:24:42,847 INFO L290 TraceCheckUtils]: 131: Hoare triple {10262#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,847 INFO L290 TraceCheckUtils]: 132: Hoare triple {10262#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,847 INFO L290 TraceCheckUtils]: 133: Hoare triple {10262#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,847 INFO L290 TraceCheckUtils]: 134: Hoare triple {10262#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,847 INFO L290 TraceCheckUtils]: 135: Hoare triple {10262#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,847 INFO L290 TraceCheckUtils]: 136: Hoare triple {10262#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,848 INFO L290 TraceCheckUtils]: 137: Hoare triple {10262#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,848 INFO L290 TraceCheckUtils]: 138: Hoare triple {10262#false} assume !(1 == ~T8_E~0); {10262#false} is VALID [2022-02-21 04:24:42,848 INFO L290 TraceCheckUtils]: 139: Hoare triple {10262#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,848 INFO L290 TraceCheckUtils]: 140: Hoare triple {10262#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,848 INFO L290 TraceCheckUtils]: 141: Hoare triple {10262#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,848 INFO L290 TraceCheckUtils]: 142: Hoare triple {10262#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,848 INFO L290 TraceCheckUtils]: 143: Hoare triple {10262#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,848 INFO L290 TraceCheckUtils]: 144: Hoare triple {10262#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,849 INFO L290 TraceCheckUtils]: 145: Hoare triple {10262#false} assume 1 == ~E_1~0;~E_1~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,849 INFO L290 TraceCheckUtils]: 146: Hoare triple {10262#false} assume !(1 == ~E_2~0); {10262#false} is VALID [2022-02-21 04:24:42,849 INFO L290 TraceCheckUtils]: 147: Hoare triple {10262#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,849 INFO L290 TraceCheckUtils]: 148: Hoare triple {10262#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,849 INFO L290 TraceCheckUtils]: 149: Hoare triple {10262#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,849 INFO L290 TraceCheckUtils]: 150: Hoare triple {10262#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,849 INFO L290 TraceCheckUtils]: 151: Hoare triple {10262#false} assume 1 == ~E_7~0;~E_7~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,849 INFO L290 TraceCheckUtils]: 152: Hoare triple {10262#false} assume 1 == ~E_8~0;~E_8~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,850 INFO L290 TraceCheckUtils]: 153: Hoare triple {10262#false} assume 1 == ~E_9~0;~E_9~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,850 INFO L290 TraceCheckUtils]: 154: Hoare triple {10262#false} assume !(1 == ~E_10~0); {10262#false} is VALID [2022-02-21 04:24:42,850 INFO L290 TraceCheckUtils]: 155: Hoare triple {10262#false} assume 1 == ~E_11~0;~E_11~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,850 INFO L290 TraceCheckUtils]: 156: Hoare triple {10262#false} assume 1 == ~E_12~0;~E_12~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,850 INFO L290 TraceCheckUtils]: 157: Hoare triple {10262#false} assume 1 == ~E_13~0;~E_13~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,850 INFO L290 TraceCheckUtils]: 158: Hoare triple {10262#false} assume 1 == ~E_14~0;~E_14~0 := 2; {10262#false} is VALID [2022-02-21 04:24:42,850 INFO L290 TraceCheckUtils]: 159: Hoare triple {10262#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {10262#false} is VALID [2022-02-21 04:24:42,850 INFO L290 TraceCheckUtils]: 160: Hoare triple {10262#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {10262#false} is VALID [2022-02-21 04:24:42,851 INFO L290 TraceCheckUtils]: 161: Hoare triple {10262#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {10262#false} is VALID [2022-02-21 04:24:42,851 INFO L290 TraceCheckUtils]: 162: Hoare triple {10262#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {10262#false} is VALID [2022-02-21 04:24:42,851 INFO L290 TraceCheckUtils]: 163: Hoare triple {10262#false} assume !(0 == start_simulation_~tmp~3#1); {10262#false} is VALID [2022-02-21 04:24:42,851 INFO L290 TraceCheckUtils]: 164: Hoare triple {10262#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {10262#false} is VALID [2022-02-21 04:24:42,851 INFO L290 TraceCheckUtils]: 165: Hoare triple {10262#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {10262#false} is VALID [2022-02-21 04:24:42,851 INFO L290 TraceCheckUtils]: 166: Hoare triple {10262#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {10262#false} is VALID [2022-02-21 04:24:42,851 INFO L290 TraceCheckUtils]: 167: Hoare triple {10262#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {10262#false} is VALID [2022-02-21 04:24:42,851 INFO L290 TraceCheckUtils]: 168: Hoare triple {10262#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {10262#false} is VALID [2022-02-21 04:24:42,851 INFO L290 TraceCheckUtils]: 169: Hoare triple {10262#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10262#false} is VALID [2022-02-21 04:24:42,852 INFO L290 TraceCheckUtils]: 170: Hoare triple {10262#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {10262#false} is VALID [2022-02-21 04:24:42,852 INFO L290 TraceCheckUtils]: 171: Hoare triple {10262#false} assume !(0 != start_simulation_~tmp___0~1#1); {10262#false} is VALID [2022-02-21 04:24:42,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:42,853 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:42,853 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056937745] [2022-02-21 04:24:42,853 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056937745] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:42,853 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:42,853 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:42,854 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082460413] [2022-02-21 04:24:42,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:42,854 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:42,854 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:42,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:42,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:42,855 INFO L87 Difference]: Start difference. First operand 2047 states and 3034 transitions. cyclomatic complexity: 988 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:44,306 INFO L93 Difference]: Finished difference Result 2047 states and 3033 transitions. [2022-02-21 04:24:44,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:44,306 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,429 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:44,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3033 transitions. [2022-02-21 04:24:44,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:44,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3033 transitions. [2022-02-21 04:24:44,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:24:44,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:24:44,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3033 transitions. [2022-02-21 04:24:44,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:44,768 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2022-02-21 04:24:44,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3033 transitions. [2022-02-21 04:24:44,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:24:44,803 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:44,807 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3033 transitions. Second operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,810 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3033 transitions. Second operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,824 INFO L87 Difference]: Start difference. First operand 2047 states and 3033 transitions. Second operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:44,939 INFO L93 Difference]: Finished difference Result 2047 states and 3033 transitions. [2022-02-21 04:24:44,939 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3033 transitions. [2022-02-21 04:24:44,941 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:44,942 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:44,945 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3033 transitions. [2022-02-21 04:24:44,946 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3033 transitions. [2022-02-21 04:24:45,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:45,037 INFO L93 Difference]: Finished difference Result 2047 states and 3033 transitions. [2022-02-21 04:24:45,038 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3033 transitions. [2022-02-21 04:24:45,040 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:45,040 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:45,040 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:45,040 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:45,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3033 transitions. [2022-02-21 04:24:45,137 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2022-02-21 04:24:45,137 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2022-02-21 04:24:45,137 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:45,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3033 transitions. [2022-02-21 04:24:45,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:45,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:45,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:45,145 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:45,146 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:45,146 INFO L791 eck$LassoCheckResult]: Stem: 13237#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 13238#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 13840#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12957#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12958#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 13203#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13204#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 12931#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12932#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14155#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13507#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13508#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14025#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13417#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13418#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12838#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12839#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13170#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13368#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 12415#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12416#L1342 assume !(0 == ~M_E~0); 12581#L1342-2 assume !(0 == ~T1_E~0); 13137#L1347-1 assume !(0 == ~T2_E~0); 14138#L1352-1 assume !(0 == ~T3_E~0); 13934#L1357-1 assume !(0 == ~T4_E~0); 13162#L1362-1 assume !(0 == ~T5_E~0); 13163#L1367-1 assume !(0 == ~T6_E~0); 12760#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12761#L1377-1 assume !(0 == ~T8_E~0); 13091#L1382-1 assume !(0 == ~T9_E~0); 13092#L1387-1 assume !(0 == ~T10_E~0); 13819#L1392-1 assume !(0 == ~T11_E~0); 13123#L1397-1 assume !(0 == ~T12_E~0); 13124#L1402-1 assume !(0 == ~T13_E~0); 12776#L1407-1 assume !(0 == ~T14_E~0); 12777#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14055#L1417-1 assume !(0 == ~E_2~0); 14056#L1422-1 assume !(0 == ~E_3~0); 14297#L1427-1 assume !(0 == ~E_4~0); 12964#L1432-1 assume !(0 == ~E_5~0); 12965#L1437-1 assume !(0 == ~E_6~0); 13973#L1442-1 assume !(0 == ~E_7~0); 13974#L1447-1 assume !(0 == ~E_8~0); 13816#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 12551#L1457-1 assume !(0 == ~E_10~0); 12552#L1462-1 assume !(0 == ~E_11~0); 14008#L1467-1 assume !(0 == ~E_12~0); 14020#L1472-1 assume !(0 == ~E_13~0); 14021#L1477-1 assume !(0 == ~E_14~0); 13763#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12750#L646 assume 1 == ~m_pc~0; 12751#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13427#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13442#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12840#L1666 assume !(0 != activate_threads_~tmp~1#1); 12841#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14318#L665 assume !(1 == ~t1_pc~0); 13316#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13317#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12849#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12850#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 13640#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13641#L684 assume 1 == ~t2_pc~0; 13758#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13682#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13747#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14142#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 14143#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14331#L703 assume !(1 == ~t3_pc~0); 12986#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12987#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13633#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12385#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 12386#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12871#L722 assume 1 == ~t4_pc~0; 13609#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13052#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13397#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13957#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 13464#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12582#L741 assume 1 == ~t5_pc~0; 12583#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12893#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13047#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13048#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 13727#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13138#L760 assume !(1 == ~t6_pc~0); 12985#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12984#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12842#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12843#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13564#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13565#L779 assume 1 == ~t7_pc~0; 12627#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12473#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12474#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12882#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 12905#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12906#L798 assume !(1 == ~t8_pc~0); 14187#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14110#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12629#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12630#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 14320#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12450#L817 assume 1 == ~t9_pc~0; 12451#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13245#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13246#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13768#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 12856#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12857#L836 assume !(1 == ~t10_pc~0); 12873#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12804#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12805#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13053#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 13054#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14120#L855 assume 1 == ~t11_pc~0; 13438#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13439#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14003#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13812#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 13647#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12746#L874 assume !(1 == ~t12_pc~0); 12747#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12914#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12915#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13055#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 12423#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12424#L893 assume 1 == ~t13_pc~0; 14254#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12779#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13090#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14181#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 14189#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 14190#L912 assume 1 == ~t14_pc~0; 13980#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 13981#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12749#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12681#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 12682#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13457#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 13873#L1495-2 assume !(1 == ~T1_E~0); 13874#L1500-1 assume !(1 == ~T2_E~0); 13560#L1505-1 assume !(1 == ~T3_E~0); 13561#L1510-1 assume !(1 == ~T4_E~0); 13618#L1515-1 assume !(1 == ~T5_E~0); 13619#L1520-1 assume !(1 == ~T6_E~0); 14188#L1525-1 assume !(1 == ~T7_E~0); 13898#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12851#L1535-1 assume !(1 == ~T9_E~0); 12852#L1540-1 assume !(1 == ~T10_E~0); 12344#L1545-1 assume !(1 == ~T11_E~0); 12345#L1550-1 assume !(1 == ~T12_E~0); 12593#L1555-1 assume !(1 == ~T13_E~0); 12594#L1560-1 assume !(1 == ~T14_E~0); 12894#L1565-1 assume !(1 == ~E_1~0); 14307#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13785#L1575-1 assume !(1 == ~E_3~0); 13164#L1580-1 assume !(1 == ~E_4~0); 13165#L1585-1 assume !(1 == ~E_5~0); 13635#L1590-1 assume !(1 == ~E_6~0); 13199#L1595-1 assume !(1 == ~E_7~0); 13200#L1600-1 assume !(1 == ~E_8~0); 13572#L1605-1 assume !(1 == ~E_9~0); 13573#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14090#L1615-1 assume !(1 == ~E_11~0); 13029#L1620-1 assume !(1 == ~E_12~0); 13030#L1625-1 assume !(1 == ~E_13~0); 13817#L1630-1 assume !(1 == ~E_14~0); 13198#L1635-1 assume { :end_inline_reset_delta_events } true; 13139#L2017-2 [2022-02-21 04:24:45,147 INFO L793 eck$LassoCheckResult]: Loop: 13139#L2017-2 assume !false; 12419#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12420#L1316 assume !false; 13748#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13810#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12357#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12499#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12500#L1115 assume !(0 != eval_~tmp~0#1); 13833#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13254#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13255#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13437#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13938#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13607#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13608#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14170#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14345#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14340#L1372-3 assume !(0 == ~T7_E~0); 12401#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12402#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13071#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13072#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13983#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14293#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13551#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 12707#L1412-3 assume !(0 == ~E_1~0); 12708#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13472#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13473#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14167#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13854#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13566#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13567#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12467#L1452-3 assume !(0 == ~E_9~0); 12468#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14106#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14107#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 13911#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13912#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 12705#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12706#L646-42 assume 1 == ~m_pc~0; 13291#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14139#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14140#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14278#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14279#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14071#L665-42 assume 1 == ~t1_pc~0; 14032#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14034#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14220#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12874#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12875#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14344#L684-42 assume 1 == ~t2_pc~0; 13723#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13724#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14334#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13503#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13504#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13626#L703-42 assume 1 == ~t3_pc~0; 13824#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13825#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13143#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13144#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13918#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13538#L722-42 assume 1 == ~t4_pc~0; 13539#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13949#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13192#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13019#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13020#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14314#L741-42 assume 1 == ~t5_pc~0; 14256#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13401#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13402#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14347#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13309#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13310#L760-42 assume !(1 == ~t6_pc~0); 13444#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 13579#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13580#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13968#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 13261#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13262#L779-42 assume !(1 == ~t7_pc~0); 14038#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 14039#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12946#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12947#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12802#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12803#L798-42 assume 1 == ~t8_pc~0; 13253#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12414#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14157#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13603#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12633#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12634#L817-42 assume !(1 == ~t9_pc~0); 13408#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 12917#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12918#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13044#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13849#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13850#L836-42 assume 1 == ~t10_pc~0; 13942#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12955#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12956#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14257#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14258#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14299#L855-42 assume 1 == ~t11_pc~0; 14312#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12506#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12507#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13256#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14019#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13120#L874-42 assume 1 == ~t12_pc~0; 13121#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13360#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12421#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12422#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12675#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12676#L893-42 assume 1 == ~t13_pc~0; 13878#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13660#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13675#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13577#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 13049#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 13050#L912-42 assume !(1 == ~t14_pc~0); 13859#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 12367#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12368#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13948#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 12795#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12796#L1495-3 assume !(1 == ~M_E~0); 13411#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13839#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13932#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13025#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12988#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12989#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13646#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13869#L1530-3 assume !(1 == ~T8_E~0); 12834#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12835#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12872#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14129#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14238#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13278#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 13279#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13894#L1570-3 assume !(1 == ~E_2~0); 13845#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13846#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14201#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14245#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14291#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13668#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13669#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14144#L1610-3 assume !(1 == ~E_10~0); 13031#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13032#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13636#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13637#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 13541#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 12972#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12577#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 13315#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13871#L2036 assume !(0 == start_simulation_~tmp~3#1); 13872#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 14024#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 13184#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 14202#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13584#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13585#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14305#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14306#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 13139#L2017-2 [2022-02-21 04:24:45,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:45,147 INFO L85 PathProgramCache]: Analyzing trace with hash -1949208090, now seen corresponding path program 1 times [2022-02-21 04:24:45,147 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:45,148 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807372844] [2022-02-21 04:24:45,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:45,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:45,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:45,179 INFO L290 TraceCheckUtils]: 0: Hoare triple {18455#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {18455#true} is VALID [2022-02-21 04:24:45,179 INFO L290 TraceCheckUtils]: 1: Hoare triple {18455#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {18457#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 2: Hoare triple {18457#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {18457#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 3: Hoare triple {18457#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {18457#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 4: Hoare triple {18457#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {18457#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 5: Hoare triple {18457#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {18457#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 6: Hoare triple {18457#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 7: Hoare triple {18456#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 8: Hoare triple {18456#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 9: Hoare triple {18456#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 10: Hoare triple {18456#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 11: Hoare triple {18456#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 12: Hoare triple {18456#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 13: Hoare triple {18456#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {18456#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 14: Hoare triple {18456#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 15: Hoare triple {18456#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 16: Hoare triple {18456#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 17: Hoare triple {18456#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 18: Hoare triple {18456#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 19: Hoare triple {18456#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {18456#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 20: Hoare triple {18456#false} assume !(0 == ~M_E~0); {18456#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 21: Hoare triple {18456#false} assume !(0 == ~T1_E~0); {18456#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 22: Hoare triple {18456#false} assume !(0 == ~T2_E~0); {18456#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 23: Hoare triple {18456#false} assume !(0 == ~T3_E~0); {18456#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 24: Hoare triple {18456#false} assume !(0 == ~T4_E~0); {18456#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 25: Hoare triple {18456#false} assume !(0 == ~T5_E~0); {18456#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 26: Hoare triple {18456#false} assume !(0 == ~T6_E~0); {18456#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 27: Hoare triple {18456#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {18456#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 28: Hoare triple {18456#false} assume !(0 == ~T8_E~0); {18456#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 29: Hoare triple {18456#false} assume !(0 == ~T9_E~0); {18456#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 30: Hoare triple {18456#false} assume !(0 == ~T10_E~0); {18456#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 31: Hoare triple {18456#false} assume !(0 == ~T11_E~0); {18456#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 32: Hoare triple {18456#false} assume !(0 == ~T12_E~0); {18456#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 33: Hoare triple {18456#false} assume !(0 == ~T13_E~0); {18456#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 34: Hoare triple {18456#false} assume !(0 == ~T14_E~0); {18456#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 35: Hoare triple {18456#false} assume 0 == ~E_1~0;~E_1~0 := 1; {18456#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 36: Hoare triple {18456#false} assume !(0 == ~E_2~0); {18456#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 37: Hoare triple {18456#false} assume !(0 == ~E_3~0); {18456#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 38: Hoare triple {18456#false} assume !(0 == ~E_4~0); {18456#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 39: Hoare triple {18456#false} assume !(0 == ~E_5~0); {18456#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 40: Hoare triple {18456#false} assume !(0 == ~E_6~0); {18456#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 41: Hoare triple {18456#false} assume !(0 == ~E_7~0); {18456#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 42: Hoare triple {18456#false} assume !(0 == ~E_8~0); {18456#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 43: Hoare triple {18456#false} assume 0 == ~E_9~0;~E_9~0 := 1; {18456#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 44: Hoare triple {18456#false} assume !(0 == ~E_10~0); {18456#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 45: Hoare triple {18456#false} assume !(0 == ~E_11~0); {18456#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 46: Hoare triple {18456#false} assume !(0 == ~E_12~0); {18456#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 47: Hoare triple {18456#false} assume !(0 == ~E_13~0); {18456#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 48: Hoare triple {18456#false} assume !(0 == ~E_14~0); {18456#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 49: Hoare triple {18456#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18456#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 50: Hoare triple {18456#false} assume 1 == ~m_pc~0; {18456#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 51: Hoare triple {18456#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {18456#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 52: Hoare triple {18456#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18456#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 53: Hoare triple {18456#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {18456#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 54: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp~1#1); {18456#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 55: Hoare triple {18456#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18456#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 56: Hoare triple {18456#false} assume !(1 == ~t1_pc~0); {18456#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 57: Hoare triple {18456#false} is_transmit1_triggered_~__retres1~1#1 := 0; {18456#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 58: Hoare triple {18456#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18456#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 59: Hoare triple {18456#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18456#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 60: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___0~0#1); {18456#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 61: Hoare triple {18456#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18456#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 62: Hoare triple {18456#false} assume 1 == ~t2_pc~0; {18456#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 63: Hoare triple {18456#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {18456#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 64: Hoare triple {18456#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18456#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 65: Hoare triple {18456#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18456#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 66: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___1~0#1); {18456#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 67: Hoare triple {18456#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18456#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 68: Hoare triple {18456#false} assume !(1 == ~t3_pc~0); {18456#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 69: Hoare triple {18456#false} is_transmit3_triggered_~__retres1~3#1 := 0; {18456#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 70: Hoare triple {18456#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18456#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 71: Hoare triple {18456#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18456#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 72: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___2~0#1); {18456#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 73: Hoare triple {18456#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18456#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 74: Hoare triple {18456#false} assume 1 == ~t4_pc~0; {18456#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 75: Hoare triple {18456#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18456#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 76: Hoare triple {18456#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18456#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 77: Hoare triple {18456#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18456#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 78: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___3~0#1); {18456#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 79: Hoare triple {18456#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18456#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 80: Hoare triple {18456#false} assume 1 == ~t5_pc~0; {18456#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 81: Hoare triple {18456#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {18456#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 82: Hoare triple {18456#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18456#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 83: Hoare triple {18456#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {18456#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 84: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___4~0#1); {18456#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 85: Hoare triple {18456#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18456#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 86: Hoare triple {18456#false} assume !(1 == ~t6_pc~0); {18456#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 87: Hoare triple {18456#false} is_transmit6_triggered_~__retres1~6#1 := 0; {18456#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 88: Hoare triple {18456#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18456#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 89: Hoare triple {18456#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {18456#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 90: Hoare triple {18456#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {18456#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 91: Hoare triple {18456#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18456#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 92: Hoare triple {18456#false} assume 1 == ~t7_pc~0; {18456#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 93: Hoare triple {18456#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {18456#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 94: Hoare triple {18456#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18456#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 95: Hoare triple {18456#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {18456#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 96: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___6~0#1); {18456#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 97: Hoare triple {18456#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18456#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 98: Hoare triple {18456#false} assume !(1 == ~t8_pc~0); {18456#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 99: Hoare triple {18456#false} is_transmit8_triggered_~__retres1~8#1 := 0; {18456#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 100: Hoare triple {18456#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18456#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 101: Hoare triple {18456#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {18456#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 102: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___7~0#1); {18456#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 103: Hoare triple {18456#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18456#false} is VALID [2022-02-21 04:24:45,194 INFO L290 TraceCheckUtils]: 104: Hoare triple {18456#false} assume 1 == ~t9_pc~0; {18456#false} is VALID [2022-02-21 04:24:45,194 INFO L290 TraceCheckUtils]: 105: Hoare triple {18456#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {18456#false} is VALID [2022-02-21 04:24:45,194 INFO L290 TraceCheckUtils]: 106: Hoare triple {18456#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18456#false} is VALID [2022-02-21 04:24:45,194 INFO L290 TraceCheckUtils]: 107: Hoare triple {18456#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {18456#false} is VALID [2022-02-21 04:24:45,194 INFO L290 TraceCheckUtils]: 108: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___8~0#1); {18456#false} is VALID [2022-02-21 04:24:45,194 INFO L290 TraceCheckUtils]: 109: Hoare triple {18456#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {18456#false} is VALID [2022-02-21 04:24:45,194 INFO L290 TraceCheckUtils]: 110: Hoare triple {18456#false} assume !(1 == ~t10_pc~0); {18456#false} is VALID [2022-02-21 04:24:45,194 INFO L290 TraceCheckUtils]: 111: Hoare triple {18456#false} is_transmit10_triggered_~__retres1~10#1 := 0; {18456#false} is VALID [2022-02-21 04:24:45,195 INFO L290 TraceCheckUtils]: 112: Hoare triple {18456#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {18456#false} is VALID [2022-02-21 04:24:45,195 INFO L290 TraceCheckUtils]: 113: Hoare triple {18456#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {18456#false} is VALID [2022-02-21 04:24:45,195 INFO L290 TraceCheckUtils]: 114: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___9~0#1); {18456#false} is VALID [2022-02-21 04:24:45,195 INFO L290 TraceCheckUtils]: 115: Hoare triple {18456#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {18456#false} is VALID [2022-02-21 04:24:45,195 INFO L290 TraceCheckUtils]: 116: Hoare triple {18456#false} assume 1 == ~t11_pc~0; {18456#false} is VALID [2022-02-21 04:24:45,195 INFO L290 TraceCheckUtils]: 117: Hoare triple {18456#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {18456#false} is VALID [2022-02-21 04:24:45,195 INFO L290 TraceCheckUtils]: 118: Hoare triple {18456#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {18456#false} is VALID [2022-02-21 04:24:45,195 INFO L290 TraceCheckUtils]: 119: Hoare triple {18456#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {18456#false} is VALID [2022-02-21 04:24:45,196 INFO L290 TraceCheckUtils]: 120: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___10~0#1); {18456#false} is VALID [2022-02-21 04:24:45,196 INFO L290 TraceCheckUtils]: 121: Hoare triple {18456#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {18456#false} is VALID [2022-02-21 04:24:45,196 INFO L290 TraceCheckUtils]: 122: Hoare triple {18456#false} assume !(1 == ~t12_pc~0); {18456#false} is VALID [2022-02-21 04:24:45,196 INFO L290 TraceCheckUtils]: 123: Hoare triple {18456#false} is_transmit12_triggered_~__retres1~12#1 := 0; {18456#false} is VALID [2022-02-21 04:24:45,196 INFO L290 TraceCheckUtils]: 124: Hoare triple {18456#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {18456#false} is VALID [2022-02-21 04:24:45,196 INFO L290 TraceCheckUtils]: 125: Hoare triple {18456#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {18456#false} is VALID [2022-02-21 04:24:45,196 INFO L290 TraceCheckUtils]: 126: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___11~0#1); {18456#false} is VALID [2022-02-21 04:24:45,197 INFO L290 TraceCheckUtils]: 127: Hoare triple {18456#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {18456#false} is VALID [2022-02-21 04:24:45,197 INFO L290 TraceCheckUtils]: 128: Hoare triple {18456#false} assume 1 == ~t13_pc~0; {18456#false} is VALID [2022-02-21 04:24:45,197 INFO L290 TraceCheckUtils]: 129: Hoare triple {18456#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {18456#false} is VALID [2022-02-21 04:24:45,197 INFO L290 TraceCheckUtils]: 130: Hoare triple {18456#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {18456#false} is VALID [2022-02-21 04:24:45,197 INFO L290 TraceCheckUtils]: 131: Hoare triple {18456#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {18456#false} is VALID [2022-02-21 04:24:45,197 INFO L290 TraceCheckUtils]: 132: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___12~0#1); {18456#false} is VALID [2022-02-21 04:24:45,197 INFO L290 TraceCheckUtils]: 133: Hoare triple {18456#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {18456#false} is VALID [2022-02-21 04:24:45,197 INFO L290 TraceCheckUtils]: 134: Hoare triple {18456#false} assume 1 == ~t14_pc~0; {18456#false} is VALID [2022-02-21 04:24:45,198 INFO L290 TraceCheckUtils]: 135: Hoare triple {18456#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {18456#false} is VALID [2022-02-21 04:24:45,198 INFO L290 TraceCheckUtils]: 136: Hoare triple {18456#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {18456#false} is VALID [2022-02-21 04:24:45,198 INFO L290 TraceCheckUtils]: 137: Hoare triple {18456#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {18456#false} is VALID [2022-02-21 04:24:45,198 INFO L290 TraceCheckUtils]: 138: Hoare triple {18456#false} assume !(0 != activate_threads_~tmp___13~0#1); {18456#false} is VALID [2022-02-21 04:24:45,198 INFO L290 TraceCheckUtils]: 139: Hoare triple {18456#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18456#false} is VALID [2022-02-21 04:24:45,198 INFO L290 TraceCheckUtils]: 140: Hoare triple {18456#false} assume 1 == ~M_E~0;~M_E~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,198 INFO L290 TraceCheckUtils]: 141: Hoare triple {18456#false} assume !(1 == ~T1_E~0); {18456#false} is VALID [2022-02-21 04:24:45,198 INFO L290 TraceCheckUtils]: 142: Hoare triple {18456#false} assume !(1 == ~T2_E~0); {18456#false} is VALID [2022-02-21 04:24:45,199 INFO L290 TraceCheckUtils]: 143: Hoare triple {18456#false} assume !(1 == ~T3_E~0); {18456#false} is VALID [2022-02-21 04:24:45,199 INFO L290 TraceCheckUtils]: 144: Hoare triple {18456#false} assume !(1 == ~T4_E~0); {18456#false} is VALID [2022-02-21 04:24:45,199 INFO L290 TraceCheckUtils]: 145: Hoare triple {18456#false} assume !(1 == ~T5_E~0); {18456#false} is VALID [2022-02-21 04:24:45,199 INFO L290 TraceCheckUtils]: 146: Hoare triple {18456#false} assume !(1 == ~T6_E~0); {18456#false} is VALID [2022-02-21 04:24:45,199 INFO L290 TraceCheckUtils]: 147: Hoare triple {18456#false} assume !(1 == ~T7_E~0); {18456#false} is VALID [2022-02-21 04:24:45,199 INFO L290 TraceCheckUtils]: 148: Hoare triple {18456#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,199 INFO L290 TraceCheckUtils]: 149: Hoare triple {18456#false} assume !(1 == ~T9_E~0); {18456#false} is VALID [2022-02-21 04:24:45,199 INFO L290 TraceCheckUtils]: 150: Hoare triple {18456#false} assume !(1 == ~T10_E~0); {18456#false} is VALID [2022-02-21 04:24:45,200 INFO L290 TraceCheckUtils]: 151: Hoare triple {18456#false} assume !(1 == ~T11_E~0); {18456#false} is VALID [2022-02-21 04:24:45,200 INFO L290 TraceCheckUtils]: 152: Hoare triple {18456#false} assume !(1 == ~T12_E~0); {18456#false} is VALID [2022-02-21 04:24:45,200 INFO L290 TraceCheckUtils]: 153: Hoare triple {18456#false} assume !(1 == ~T13_E~0); {18456#false} is VALID [2022-02-21 04:24:45,200 INFO L290 TraceCheckUtils]: 154: Hoare triple {18456#false} assume !(1 == ~T14_E~0); {18456#false} is VALID [2022-02-21 04:24:45,200 INFO L290 TraceCheckUtils]: 155: Hoare triple {18456#false} assume !(1 == ~E_1~0); {18456#false} is VALID [2022-02-21 04:24:45,200 INFO L290 TraceCheckUtils]: 156: Hoare triple {18456#false} assume 1 == ~E_2~0;~E_2~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,200 INFO L290 TraceCheckUtils]: 157: Hoare triple {18456#false} assume !(1 == ~E_3~0); {18456#false} is VALID [2022-02-21 04:24:45,201 INFO L290 TraceCheckUtils]: 158: Hoare triple {18456#false} assume !(1 == ~E_4~0); {18456#false} is VALID [2022-02-21 04:24:45,201 INFO L290 TraceCheckUtils]: 159: Hoare triple {18456#false} assume !(1 == ~E_5~0); {18456#false} is VALID [2022-02-21 04:24:45,201 INFO L290 TraceCheckUtils]: 160: Hoare triple {18456#false} assume !(1 == ~E_6~0); {18456#false} is VALID [2022-02-21 04:24:45,201 INFO L290 TraceCheckUtils]: 161: Hoare triple {18456#false} assume !(1 == ~E_7~0); {18456#false} is VALID [2022-02-21 04:24:45,201 INFO L290 TraceCheckUtils]: 162: Hoare triple {18456#false} assume !(1 == ~E_8~0); {18456#false} is VALID [2022-02-21 04:24:45,201 INFO L290 TraceCheckUtils]: 163: Hoare triple {18456#false} assume !(1 == ~E_9~0); {18456#false} is VALID [2022-02-21 04:24:45,201 INFO L290 TraceCheckUtils]: 164: Hoare triple {18456#false} assume 1 == ~E_10~0;~E_10~0 := 2; {18456#false} is VALID [2022-02-21 04:24:45,201 INFO L290 TraceCheckUtils]: 165: Hoare triple {18456#false} assume !(1 == ~E_11~0); {18456#false} is VALID [2022-02-21 04:24:45,202 INFO L290 TraceCheckUtils]: 166: Hoare triple {18456#false} assume !(1 == ~E_12~0); {18456#false} is VALID [2022-02-21 04:24:45,202 INFO L290 TraceCheckUtils]: 167: Hoare triple {18456#false} assume !(1 == ~E_13~0); {18456#false} is VALID [2022-02-21 04:24:45,202 INFO L290 TraceCheckUtils]: 168: Hoare triple {18456#false} assume !(1 == ~E_14~0); {18456#false} is VALID [2022-02-21 04:24:45,202 INFO L290 TraceCheckUtils]: 169: Hoare triple {18456#false} assume { :end_inline_reset_delta_events } true; {18456#false} is VALID [2022-02-21 04:24:45,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:45,203 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:45,203 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807372844] [2022-02-21 04:24:45,203 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [807372844] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:45,203 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:45,203 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:45,203 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327809514] [2022-02-21 04:24:45,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:45,204 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:45,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:45,204 INFO L85 PathProgramCache]: Analyzing trace with hash -812799539, now seen corresponding path program 1 times [2022-02-21 04:24:45,205 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:45,205 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423189031] [2022-02-21 04:24:45,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:45,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:45,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:45,251 INFO L290 TraceCheckUtils]: 0: Hoare triple {18458#true} assume !false; {18458#true} is VALID [2022-02-21 04:24:45,252 INFO L290 TraceCheckUtils]: 1: Hoare triple {18458#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {18458#true} is VALID [2022-02-21 04:24:45,252 INFO L290 TraceCheckUtils]: 2: Hoare triple {18458#true} assume !false; {18458#true} is VALID [2022-02-21 04:24:45,252 INFO L290 TraceCheckUtils]: 3: Hoare triple {18458#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {18458#true} is VALID [2022-02-21 04:24:45,252 INFO L290 TraceCheckUtils]: 4: Hoare triple {18458#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {18458#true} is VALID [2022-02-21 04:24:45,252 INFO L290 TraceCheckUtils]: 5: Hoare triple {18458#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {18458#true} is VALID [2022-02-21 04:24:45,252 INFO L290 TraceCheckUtils]: 6: Hoare triple {18458#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {18458#true} is VALID [2022-02-21 04:24:45,253 INFO L290 TraceCheckUtils]: 7: Hoare triple {18458#true} assume !(0 != eval_~tmp~0#1); {18458#true} is VALID [2022-02-21 04:24:45,253 INFO L290 TraceCheckUtils]: 8: Hoare triple {18458#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {18458#true} is VALID [2022-02-21 04:24:45,253 INFO L290 TraceCheckUtils]: 9: Hoare triple {18458#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {18458#true} is VALID [2022-02-21 04:24:45,253 INFO L290 TraceCheckUtils]: 10: Hoare triple {18458#true} assume 0 == ~M_E~0;~M_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,254 INFO L290 TraceCheckUtils]: 11: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,254 INFO L290 TraceCheckUtils]: 12: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,254 INFO L290 TraceCheckUtils]: 13: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,254 INFO L290 TraceCheckUtils]: 14: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,255 INFO L290 TraceCheckUtils]: 15: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,255 INFO L290 TraceCheckUtils]: 16: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,255 INFO L290 TraceCheckUtils]: 17: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 18: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 19: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 20: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,257 INFO L290 TraceCheckUtils]: 21: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,257 INFO L290 TraceCheckUtils]: 22: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,266 INFO L290 TraceCheckUtils]: 23: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,266 INFO L290 TraceCheckUtils]: 24: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,267 INFO L290 TraceCheckUtils]: 25: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,267 INFO L290 TraceCheckUtils]: 26: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,267 INFO L290 TraceCheckUtils]: 27: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,268 INFO L290 TraceCheckUtils]: 28: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,268 INFO L290 TraceCheckUtils]: 29: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,268 INFO L290 TraceCheckUtils]: 30: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,268 INFO L290 TraceCheckUtils]: 31: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,269 INFO L290 TraceCheckUtils]: 32: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,269 INFO L290 TraceCheckUtils]: 33: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,269 INFO L290 TraceCheckUtils]: 34: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,270 INFO L290 TraceCheckUtils]: 35: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,270 INFO L290 TraceCheckUtils]: 36: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,270 INFO L290 TraceCheckUtils]: 37: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,271 INFO L290 TraceCheckUtils]: 38: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,271 INFO L290 TraceCheckUtils]: 39: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,271 INFO L290 TraceCheckUtils]: 40: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,272 INFO L290 TraceCheckUtils]: 41: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,272 INFO L290 TraceCheckUtils]: 42: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,272 INFO L290 TraceCheckUtils]: 43: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,272 INFO L290 TraceCheckUtils]: 44: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,273 INFO L290 TraceCheckUtils]: 45: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,273 INFO L290 TraceCheckUtils]: 46: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,273 INFO L290 TraceCheckUtils]: 47: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,274 INFO L290 TraceCheckUtils]: 48: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,274 INFO L290 TraceCheckUtils]: 49: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,274 INFO L290 TraceCheckUtils]: 50: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,275 INFO L290 TraceCheckUtils]: 51: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,275 INFO L290 TraceCheckUtils]: 52: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,275 INFO L290 TraceCheckUtils]: 53: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,276 INFO L290 TraceCheckUtils]: 54: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,276 INFO L290 TraceCheckUtils]: 55: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,276 INFO L290 TraceCheckUtils]: 56: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,276 INFO L290 TraceCheckUtils]: 57: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,277 INFO L290 TraceCheckUtils]: 58: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,277 INFO L290 TraceCheckUtils]: 59: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,277 INFO L290 TraceCheckUtils]: 60: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,278 INFO L290 TraceCheckUtils]: 61: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,278 INFO L290 TraceCheckUtils]: 62: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,278 INFO L290 TraceCheckUtils]: 63: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,279 INFO L290 TraceCheckUtils]: 64: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,279 INFO L290 TraceCheckUtils]: 65: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,279 INFO L290 TraceCheckUtils]: 66: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,279 INFO L290 TraceCheckUtils]: 67: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,280 INFO L290 TraceCheckUtils]: 68: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,280 INFO L290 TraceCheckUtils]: 69: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,280 INFO L290 TraceCheckUtils]: 70: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,281 INFO L290 TraceCheckUtils]: 71: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,281 INFO L290 TraceCheckUtils]: 72: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,281 INFO L290 TraceCheckUtils]: 73: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,282 INFO L290 TraceCheckUtils]: 74: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,282 INFO L290 TraceCheckUtils]: 75: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,282 INFO L290 TraceCheckUtils]: 76: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,283 INFO L290 TraceCheckUtils]: 77: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,283 INFO L290 TraceCheckUtils]: 78: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,283 INFO L290 TraceCheckUtils]: 79: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,283 INFO L290 TraceCheckUtils]: 80: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,284 INFO L290 TraceCheckUtils]: 81: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,284 INFO L290 TraceCheckUtils]: 82: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,284 INFO L290 TraceCheckUtils]: 83: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,285 INFO L290 TraceCheckUtils]: 84: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,285 INFO L290 TraceCheckUtils]: 85: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,285 INFO L290 TraceCheckUtils]: 86: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,286 INFO L290 TraceCheckUtils]: 87: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,286 INFO L290 TraceCheckUtils]: 88: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,286 INFO L290 TraceCheckUtils]: 89: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,286 INFO L290 TraceCheckUtils]: 90: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,287 INFO L290 TraceCheckUtils]: 91: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,287 INFO L290 TraceCheckUtils]: 92: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,287 INFO L290 TraceCheckUtils]: 93: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,288 INFO L290 TraceCheckUtils]: 94: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,288 INFO L290 TraceCheckUtils]: 95: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,288 INFO L290 TraceCheckUtils]: 96: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,288 INFO L290 TraceCheckUtils]: 97: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,289 INFO L290 TraceCheckUtils]: 98: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,289 INFO L290 TraceCheckUtils]: 99: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,289 INFO L290 TraceCheckUtils]: 100: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,289 INFO L290 TraceCheckUtils]: 101: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,290 INFO L290 TraceCheckUtils]: 102: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,290 INFO L290 TraceCheckUtils]: 103: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,290 INFO L290 TraceCheckUtils]: 104: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,291 INFO L290 TraceCheckUtils]: 105: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,291 INFO L290 TraceCheckUtils]: 106: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,291 INFO L290 TraceCheckUtils]: 107: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,292 INFO L290 TraceCheckUtils]: 108: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,292 INFO L290 TraceCheckUtils]: 109: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,292 INFO L290 TraceCheckUtils]: 110: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,292 INFO L290 TraceCheckUtils]: 111: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,293 INFO L290 TraceCheckUtils]: 112: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,293 INFO L290 TraceCheckUtils]: 113: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,293 INFO L290 TraceCheckUtils]: 114: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,294 INFO L290 TraceCheckUtils]: 115: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,294 INFO L290 TraceCheckUtils]: 116: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,294 INFO L290 TraceCheckUtils]: 117: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,294 INFO L290 TraceCheckUtils]: 118: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,295 INFO L290 TraceCheckUtils]: 119: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,295 INFO L290 TraceCheckUtils]: 120: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,295 INFO L290 TraceCheckUtils]: 121: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,296 INFO L290 TraceCheckUtils]: 122: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,296 INFO L290 TraceCheckUtils]: 123: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,296 INFO L290 TraceCheckUtils]: 124: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,296 INFO L290 TraceCheckUtils]: 125: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,297 INFO L290 TraceCheckUtils]: 126: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,297 INFO L290 TraceCheckUtils]: 127: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,297 INFO L290 TraceCheckUtils]: 128: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,297 INFO L290 TraceCheckUtils]: 129: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18460#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:45,298 INFO L290 TraceCheckUtils]: 130: Hoare triple {18460#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {18459#false} is VALID [2022-02-21 04:24:45,298 INFO L290 TraceCheckUtils]: 131: Hoare triple {18459#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,298 INFO L290 TraceCheckUtils]: 132: Hoare triple {18459#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,298 INFO L290 TraceCheckUtils]: 133: Hoare triple {18459#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,298 INFO L290 TraceCheckUtils]: 134: Hoare triple {18459#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,298 INFO L290 TraceCheckUtils]: 135: Hoare triple {18459#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,298 INFO L290 TraceCheckUtils]: 136: Hoare triple {18459#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 137: Hoare triple {18459#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 138: Hoare triple {18459#false} assume !(1 == ~T8_E~0); {18459#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 139: Hoare triple {18459#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 140: Hoare triple {18459#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 141: Hoare triple {18459#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 142: Hoare triple {18459#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 143: Hoare triple {18459#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 144: Hoare triple {18459#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 145: Hoare triple {18459#false} assume 1 == ~E_1~0;~E_1~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 146: Hoare triple {18459#false} assume !(1 == ~E_2~0); {18459#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 147: Hoare triple {18459#false} assume 1 == ~E_3~0;~E_3~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 148: Hoare triple {18459#false} assume 1 == ~E_4~0;~E_4~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 149: Hoare triple {18459#false} assume 1 == ~E_5~0;~E_5~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 150: Hoare triple {18459#false} assume 1 == ~E_6~0;~E_6~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 151: Hoare triple {18459#false} assume 1 == ~E_7~0;~E_7~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 152: Hoare triple {18459#false} assume 1 == ~E_8~0;~E_8~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 153: Hoare triple {18459#false} assume 1 == ~E_9~0;~E_9~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 154: Hoare triple {18459#false} assume !(1 == ~E_10~0); {18459#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 155: Hoare triple {18459#false} assume 1 == ~E_11~0;~E_11~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 156: Hoare triple {18459#false} assume 1 == ~E_12~0;~E_12~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 157: Hoare triple {18459#false} assume 1 == ~E_13~0;~E_13~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 158: Hoare triple {18459#false} assume 1 == ~E_14~0;~E_14~0 := 2; {18459#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 159: Hoare triple {18459#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {18459#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 160: Hoare triple {18459#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {18459#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 161: Hoare triple {18459#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {18459#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 162: Hoare triple {18459#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {18459#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 163: Hoare triple {18459#false} assume !(0 == start_simulation_~tmp~3#1); {18459#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 164: Hoare triple {18459#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {18459#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 165: Hoare triple {18459#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {18459#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 166: Hoare triple {18459#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {18459#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 167: Hoare triple {18459#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {18459#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 168: Hoare triple {18459#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {18459#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 169: Hoare triple {18459#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {18459#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 170: Hoare triple {18459#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {18459#false} is VALID [2022-02-21 04:24:45,303 INFO L290 TraceCheckUtils]: 171: Hoare triple {18459#false} assume !(0 != start_simulation_~tmp___0~1#1); {18459#false} is VALID [2022-02-21 04:24:45,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:45,303 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:45,303 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423189031] [2022-02-21 04:24:45,304 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423189031] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:45,304 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:45,304 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:45,304 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [793838488] [2022-02-21 04:24:45,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:45,304 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:45,304 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:45,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:45,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:45,305 INFO L87 Difference]: Start difference. First operand 2047 states and 3033 transitions. cyclomatic complexity: 987 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:46,754 INFO L93 Difference]: Finished difference Result 2047 states and 3032 transitions. [2022-02-21 04:24:46,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:46,754 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,874 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:46,876 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3032 transitions. [2022-02-21 04:24:47,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:47,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3032 transitions. [2022-02-21 04:24:47,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:24:47,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:24:47,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3032 transitions. [2022-02-21 04:24:47,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:47,114 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2022-02-21 04:24:47,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3032 transitions. [2022-02-21 04:24:47,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:24:47,133 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:47,136 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3032 transitions. Second operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,138 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3032 transitions. Second operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,140 INFO L87 Difference]: Start difference. First operand 2047 states and 3032 transitions. Second operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,253 INFO L93 Difference]: Finished difference Result 2047 states and 3032 transitions. [2022-02-21 04:24:47,253 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3032 transitions. [2022-02-21 04:24:47,256 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:47,256 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:47,260 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3032 transitions. [2022-02-21 04:24:47,264 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3032 transitions. [2022-02-21 04:24:47,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,373 INFO L93 Difference]: Finished difference Result 2047 states and 3032 transitions. [2022-02-21 04:24:47,373 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3032 transitions. [2022-02-21 04:24:47,377 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:47,377 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:47,377 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:47,377 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:47,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3032 transitions. [2022-02-21 04:24:47,497 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2022-02-21 04:24:47,497 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2022-02-21 04:24:47,497 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:47,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3032 transitions. [2022-02-21 04:24:47,505 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:47,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:47,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:47,507 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:47,507 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:47,508 INFO L791 eck$LassoCheckResult]: Stem: 21434#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 21435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 22037#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21154#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21155#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 21400#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21401#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21128#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 21129#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 22352#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21704#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21705#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22222#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21614#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21615#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21035#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21036#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21367#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21565#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 20612#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20613#L1342 assume !(0 == ~M_E~0); 20778#L1342-2 assume !(0 == ~T1_E~0); 21334#L1347-1 assume !(0 == ~T2_E~0); 22335#L1352-1 assume !(0 == ~T3_E~0); 22131#L1357-1 assume !(0 == ~T4_E~0); 21359#L1362-1 assume !(0 == ~T5_E~0); 21360#L1367-1 assume !(0 == ~T6_E~0); 20957#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20958#L1377-1 assume !(0 == ~T8_E~0); 21288#L1382-1 assume !(0 == ~T9_E~0); 21289#L1387-1 assume !(0 == ~T10_E~0); 22016#L1392-1 assume !(0 == ~T11_E~0); 21320#L1397-1 assume !(0 == ~T12_E~0); 21321#L1402-1 assume !(0 == ~T13_E~0); 20973#L1407-1 assume !(0 == ~T14_E~0); 20974#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 22252#L1417-1 assume !(0 == ~E_2~0); 22253#L1422-1 assume !(0 == ~E_3~0); 22494#L1427-1 assume !(0 == ~E_4~0); 21161#L1432-1 assume !(0 == ~E_5~0); 21162#L1437-1 assume !(0 == ~E_6~0); 22170#L1442-1 assume !(0 == ~E_7~0); 22171#L1447-1 assume !(0 == ~E_8~0); 22013#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 20748#L1457-1 assume !(0 == ~E_10~0); 20749#L1462-1 assume !(0 == ~E_11~0); 22205#L1467-1 assume !(0 == ~E_12~0); 22217#L1472-1 assume !(0 == ~E_13~0); 22218#L1477-1 assume !(0 == ~E_14~0); 21960#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20947#L646 assume 1 == ~m_pc~0; 20948#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21624#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21639#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21037#L1666 assume !(0 != activate_threads_~tmp~1#1); 21038#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22515#L665 assume !(1 == ~t1_pc~0); 21513#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21514#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21046#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21047#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 21837#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21838#L684 assume 1 == ~t2_pc~0; 21955#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21879#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21944#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22339#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 22340#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22528#L703 assume !(1 == ~t3_pc~0); 21183#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21184#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21830#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20582#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 20583#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21068#L722 assume 1 == ~t4_pc~0; 21806#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21249#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21594#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22154#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 21661#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20779#L741 assume 1 == ~t5_pc~0; 20780#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21090#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21244#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21245#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 21924#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21335#L760 assume !(1 == ~t6_pc~0); 21182#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21181#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21039#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21040#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21761#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21762#L779 assume 1 == ~t7_pc~0; 20824#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20670#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20671#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21079#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 21102#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21103#L798 assume !(1 == ~t8_pc~0); 22384#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22307#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20826#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20827#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 22517#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20647#L817 assume 1 == ~t9_pc~0; 20648#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21442#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21443#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21965#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 21053#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21054#L836 assume !(1 == ~t10_pc~0); 21070#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21001#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21002#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21250#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 21251#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22317#L855 assume 1 == ~t11_pc~0; 21635#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21636#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22200#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22009#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 21844#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20943#L874 assume !(1 == ~t12_pc~0); 20944#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21111#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21112#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21252#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 20620#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20621#L893 assume 1 == ~t13_pc~0; 22451#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20976#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21287#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22378#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 22386#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 22387#L912 assume 1 == ~t14_pc~0; 22177#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 22178#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20946#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 20878#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 20879#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21654#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 22070#L1495-2 assume !(1 == ~T1_E~0); 22071#L1500-1 assume !(1 == ~T2_E~0); 21757#L1505-1 assume !(1 == ~T3_E~0); 21758#L1510-1 assume !(1 == ~T4_E~0); 21815#L1515-1 assume !(1 == ~T5_E~0); 21816#L1520-1 assume !(1 == ~T6_E~0); 22385#L1525-1 assume !(1 == ~T7_E~0); 22095#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21048#L1535-1 assume !(1 == ~T9_E~0); 21049#L1540-1 assume !(1 == ~T10_E~0); 20541#L1545-1 assume !(1 == ~T11_E~0); 20542#L1550-1 assume !(1 == ~T12_E~0); 20790#L1555-1 assume !(1 == ~T13_E~0); 20791#L1560-1 assume !(1 == ~T14_E~0); 21091#L1565-1 assume !(1 == ~E_1~0); 22504#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21982#L1575-1 assume !(1 == ~E_3~0); 21361#L1580-1 assume !(1 == ~E_4~0); 21362#L1585-1 assume !(1 == ~E_5~0); 21832#L1590-1 assume !(1 == ~E_6~0); 21396#L1595-1 assume !(1 == ~E_7~0); 21397#L1600-1 assume !(1 == ~E_8~0); 21769#L1605-1 assume !(1 == ~E_9~0); 21770#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22287#L1615-1 assume !(1 == ~E_11~0); 21226#L1620-1 assume !(1 == ~E_12~0); 21227#L1625-1 assume !(1 == ~E_13~0); 22014#L1630-1 assume !(1 == ~E_14~0); 21395#L1635-1 assume { :end_inline_reset_delta_events } true; 21336#L2017-2 [2022-02-21 04:24:47,508 INFO L793 eck$LassoCheckResult]: Loop: 21336#L2017-2 assume !false; 20616#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20617#L1316 assume !false; 21945#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22007#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20554#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 20696#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20697#L1115 assume !(0 != eval_~tmp~0#1); 22030#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21451#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21452#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21634#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22135#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21804#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21805#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22367#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22542#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22537#L1372-3 assume !(0 == ~T7_E~0); 20598#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20599#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21268#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21269#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22180#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22490#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21748#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 20904#L1412-3 assume !(0 == ~E_1~0); 20905#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21669#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21670#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22364#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22051#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21763#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21764#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20664#L1452-3 assume !(0 == ~E_9~0); 20665#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22303#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22304#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22108#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22109#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 20902#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20903#L646-42 assume 1 == ~m_pc~0; 21488#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22336#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22337#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22475#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22476#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22268#L665-42 assume 1 == ~t1_pc~0; 22229#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22231#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22417#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21071#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21072#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22541#L684-42 assume 1 == ~t2_pc~0; 21920#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21921#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22531#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21700#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21701#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21823#L703-42 assume 1 == ~t3_pc~0; 22021#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22022#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21340#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21341#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22115#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21735#L722-42 assume 1 == ~t4_pc~0; 21736#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22146#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21389#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21216#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21217#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22511#L741-42 assume !(1 == ~t5_pc~0); 22128#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 21598#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21599#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22544#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21506#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21507#L760-42 assume !(1 == ~t6_pc~0); 21641#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 21776#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21777#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22165#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 21458#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21459#L779-42 assume 1 == ~t7_pc~0; 22288#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22236#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21143#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21144#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20999#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21000#L798-42 assume !(1 == ~t8_pc~0); 20610#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 20611#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22354#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21800#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20830#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20831#L817-42 assume 1 == ~t9_pc~0; 21604#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21114#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21115#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21241#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22046#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22047#L836-42 assume 1 == ~t10_pc~0; 22139#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21152#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21153#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22454#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22455#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22496#L855-42 assume 1 == ~t11_pc~0; 22509#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20703#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20704#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21453#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22216#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21317#L874-42 assume 1 == ~t12_pc~0; 21318#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21557#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20618#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20619#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20872#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20873#L893-42 assume !(1 == ~t13_pc~0); 21856#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 21857#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21872#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21774#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 21246#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 21247#L912-42 assume !(1 == ~t14_pc~0); 22056#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 20564#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20565#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22145#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 20992#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20993#L1495-3 assume !(1 == ~M_E~0); 21608#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22036#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22129#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21222#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21185#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21186#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21843#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22066#L1530-3 assume !(1 == ~T8_E~0); 21031#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21032#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21069#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22326#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22435#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21475#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 21476#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22091#L1570-3 assume !(1 == ~E_2~0); 22042#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22043#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22398#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22442#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22488#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21865#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21866#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22341#L1610-3 assume !(1 == ~E_10~0); 21228#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21229#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21833#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21834#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 21738#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 21169#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20774#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 21512#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 22068#L2036 assume !(0 == start_simulation_~tmp~3#1); 22069#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22221#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 21381#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 22399#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21781#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21782#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22502#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22503#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 21336#L2017-2 [2022-02-21 04:24:47,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:47,510 INFO L85 PathProgramCache]: Analyzing trace with hash -224599768, now seen corresponding path program 1 times [2022-02-21 04:24:47,510 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:47,510 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986359867] [2022-02-21 04:24:47,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:47,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:47,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:47,558 INFO L290 TraceCheckUtils]: 0: Hoare triple {26652#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {26652#true} is VALID [2022-02-21 04:24:47,559 INFO L290 TraceCheckUtils]: 1: Hoare triple {26652#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {26654#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:47,559 INFO L290 TraceCheckUtils]: 2: Hoare triple {26654#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {26654#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:47,560 INFO L290 TraceCheckUtils]: 3: Hoare triple {26654#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {26654#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:47,560 INFO L290 TraceCheckUtils]: 4: Hoare triple {26654#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {26654#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:47,560 INFO L290 TraceCheckUtils]: 5: Hoare triple {26654#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {26654#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:47,560 INFO L290 TraceCheckUtils]: 6: Hoare triple {26654#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {26654#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:47,561 INFO L290 TraceCheckUtils]: 7: Hoare triple {26654#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,561 INFO L290 TraceCheckUtils]: 8: Hoare triple {26653#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,561 INFO L290 TraceCheckUtils]: 9: Hoare triple {26653#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,561 INFO L290 TraceCheckUtils]: 10: Hoare triple {26653#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,565 INFO L290 TraceCheckUtils]: 11: Hoare triple {26653#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,565 INFO L290 TraceCheckUtils]: 12: Hoare triple {26653#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,565 INFO L290 TraceCheckUtils]: 13: Hoare triple {26653#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {26653#false} is VALID [2022-02-21 04:24:47,566 INFO L290 TraceCheckUtils]: 14: Hoare triple {26653#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,566 INFO L290 TraceCheckUtils]: 15: Hoare triple {26653#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,566 INFO L290 TraceCheckUtils]: 16: Hoare triple {26653#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,566 INFO L290 TraceCheckUtils]: 17: Hoare triple {26653#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,566 INFO L290 TraceCheckUtils]: 18: Hoare triple {26653#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,566 INFO L290 TraceCheckUtils]: 19: Hoare triple {26653#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {26653#false} is VALID [2022-02-21 04:24:47,566 INFO L290 TraceCheckUtils]: 20: Hoare triple {26653#false} assume !(0 == ~M_E~0); {26653#false} is VALID [2022-02-21 04:24:47,566 INFO L290 TraceCheckUtils]: 21: Hoare triple {26653#false} assume !(0 == ~T1_E~0); {26653#false} is VALID [2022-02-21 04:24:47,567 INFO L290 TraceCheckUtils]: 22: Hoare triple {26653#false} assume !(0 == ~T2_E~0); {26653#false} is VALID [2022-02-21 04:24:47,567 INFO L290 TraceCheckUtils]: 23: Hoare triple {26653#false} assume !(0 == ~T3_E~0); {26653#false} is VALID [2022-02-21 04:24:47,567 INFO L290 TraceCheckUtils]: 24: Hoare triple {26653#false} assume !(0 == ~T4_E~0); {26653#false} is VALID [2022-02-21 04:24:47,567 INFO L290 TraceCheckUtils]: 25: Hoare triple {26653#false} assume !(0 == ~T5_E~0); {26653#false} is VALID [2022-02-21 04:24:47,567 INFO L290 TraceCheckUtils]: 26: Hoare triple {26653#false} assume !(0 == ~T6_E~0); {26653#false} is VALID [2022-02-21 04:24:47,567 INFO L290 TraceCheckUtils]: 27: Hoare triple {26653#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {26653#false} is VALID [2022-02-21 04:24:47,567 INFO L290 TraceCheckUtils]: 28: Hoare triple {26653#false} assume !(0 == ~T8_E~0); {26653#false} is VALID [2022-02-21 04:24:47,567 INFO L290 TraceCheckUtils]: 29: Hoare triple {26653#false} assume !(0 == ~T9_E~0); {26653#false} is VALID [2022-02-21 04:24:47,567 INFO L290 TraceCheckUtils]: 30: Hoare triple {26653#false} assume !(0 == ~T10_E~0); {26653#false} is VALID [2022-02-21 04:24:47,568 INFO L290 TraceCheckUtils]: 31: Hoare triple {26653#false} assume !(0 == ~T11_E~0); {26653#false} is VALID [2022-02-21 04:24:47,568 INFO L290 TraceCheckUtils]: 32: Hoare triple {26653#false} assume !(0 == ~T12_E~0); {26653#false} is VALID [2022-02-21 04:24:47,568 INFO L290 TraceCheckUtils]: 33: Hoare triple {26653#false} assume !(0 == ~T13_E~0); {26653#false} is VALID [2022-02-21 04:24:47,568 INFO L290 TraceCheckUtils]: 34: Hoare triple {26653#false} assume !(0 == ~T14_E~0); {26653#false} is VALID [2022-02-21 04:24:47,568 INFO L290 TraceCheckUtils]: 35: Hoare triple {26653#false} assume 0 == ~E_1~0;~E_1~0 := 1; {26653#false} is VALID [2022-02-21 04:24:47,568 INFO L290 TraceCheckUtils]: 36: Hoare triple {26653#false} assume !(0 == ~E_2~0); {26653#false} is VALID [2022-02-21 04:24:47,568 INFO L290 TraceCheckUtils]: 37: Hoare triple {26653#false} assume !(0 == ~E_3~0); {26653#false} is VALID [2022-02-21 04:24:47,568 INFO L290 TraceCheckUtils]: 38: Hoare triple {26653#false} assume !(0 == ~E_4~0); {26653#false} is VALID [2022-02-21 04:24:47,568 INFO L290 TraceCheckUtils]: 39: Hoare triple {26653#false} assume !(0 == ~E_5~0); {26653#false} is VALID [2022-02-21 04:24:47,569 INFO L290 TraceCheckUtils]: 40: Hoare triple {26653#false} assume !(0 == ~E_6~0); {26653#false} is VALID [2022-02-21 04:24:47,569 INFO L290 TraceCheckUtils]: 41: Hoare triple {26653#false} assume !(0 == ~E_7~0); {26653#false} is VALID [2022-02-21 04:24:47,569 INFO L290 TraceCheckUtils]: 42: Hoare triple {26653#false} assume !(0 == ~E_8~0); {26653#false} is VALID [2022-02-21 04:24:47,569 INFO L290 TraceCheckUtils]: 43: Hoare triple {26653#false} assume 0 == ~E_9~0;~E_9~0 := 1; {26653#false} is VALID [2022-02-21 04:24:47,569 INFO L290 TraceCheckUtils]: 44: Hoare triple {26653#false} assume !(0 == ~E_10~0); {26653#false} is VALID [2022-02-21 04:24:47,569 INFO L290 TraceCheckUtils]: 45: Hoare triple {26653#false} assume !(0 == ~E_11~0); {26653#false} is VALID [2022-02-21 04:24:47,569 INFO L290 TraceCheckUtils]: 46: Hoare triple {26653#false} assume !(0 == ~E_12~0); {26653#false} is VALID [2022-02-21 04:24:47,569 INFO L290 TraceCheckUtils]: 47: Hoare triple {26653#false} assume !(0 == ~E_13~0); {26653#false} is VALID [2022-02-21 04:24:47,570 INFO L290 TraceCheckUtils]: 48: Hoare triple {26653#false} assume !(0 == ~E_14~0); {26653#false} is VALID [2022-02-21 04:24:47,570 INFO L290 TraceCheckUtils]: 49: Hoare triple {26653#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26653#false} is VALID [2022-02-21 04:24:47,570 INFO L290 TraceCheckUtils]: 50: Hoare triple {26653#false} assume 1 == ~m_pc~0; {26653#false} is VALID [2022-02-21 04:24:47,570 INFO L290 TraceCheckUtils]: 51: Hoare triple {26653#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {26653#false} is VALID [2022-02-21 04:24:47,570 INFO L290 TraceCheckUtils]: 52: Hoare triple {26653#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26653#false} is VALID [2022-02-21 04:24:47,570 INFO L290 TraceCheckUtils]: 53: Hoare triple {26653#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26653#false} is VALID [2022-02-21 04:24:47,570 INFO L290 TraceCheckUtils]: 54: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp~1#1); {26653#false} is VALID [2022-02-21 04:24:47,570 INFO L290 TraceCheckUtils]: 55: Hoare triple {26653#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26653#false} is VALID [2022-02-21 04:24:47,571 INFO L290 TraceCheckUtils]: 56: Hoare triple {26653#false} assume !(1 == ~t1_pc~0); {26653#false} is VALID [2022-02-21 04:24:47,571 INFO L290 TraceCheckUtils]: 57: Hoare triple {26653#false} is_transmit1_triggered_~__retres1~1#1 := 0; {26653#false} is VALID [2022-02-21 04:24:47,571 INFO L290 TraceCheckUtils]: 58: Hoare triple {26653#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26653#false} is VALID [2022-02-21 04:24:47,571 INFO L290 TraceCheckUtils]: 59: Hoare triple {26653#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26653#false} is VALID [2022-02-21 04:24:47,571 INFO L290 TraceCheckUtils]: 60: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___0~0#1); {26653#false} is VALID [2022-02-21 04:24:47,572 INFO L290 TraceCheckUtils]: 61: Hoare triple {26653#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26653#false} is VALID [2022-02-21 04:24:47,572 INFO L290 TraceCheckUtils]: 62: Hoare triple {26653#false} assume 1 == ~t2_pc~0; {26653#false} is VALID [2022-02-21 04:24:47,572 INFO L290 TraceCheckUtils]: 63: Hoare triple {26653#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26653#false} is VALID [2022-02-21 04:24:47,572 INFO L290 TraceCheckUtils]: 64: Hoare triple {26653#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26653#false} is VALID [2022-02-21 04:24:47,572 INFO L290 TraceCheckUtils]: 65: Hoare triple {26653#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26653#false} is VALID [2022-02-21 04:24:47,572 INFO L290 TraceCheckUtils]: 66: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___1~0#1); {26653#false} is VALID [2022-02-21 04:24:47,572 INFO L290 TraceCheckUtils]: 67: Hoare triple {26653#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26653#false} is VALID [2022-02-21 04:24:47,572 INFO L290 TraceCheckUtils]: 68: Hoare triple {26653#false} assume !(1 == ~t3_pc~0); {26653#false} is VALID [2022-02-21 04:24:47,572 INFO L290 TraceCheckUtils]: 69: Hoare triple {26653#false} is_transmit3_triggered_~__retres1~3#1 := 0; {26653#false} is VALID [2022-02-21 04:24:47,573 INFO L290 TraceCheckUtils]: 70: Hoare triple {26653#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26653#false} is VALID [2022-02-21 04:24:47,573 INFO L290 TraceCheckUtils]: 71: Hoare triple {26653#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26653#false} is VALID [2022-02-21 04:24:47,573 INFO L290 TraceCheckUtils]: 72: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___2~0#1); {26653#false} is VALID [2022-02-21 04:24:47,573 INFO L290 TraceCheckUtils]: 73: Hoare triple {26653#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26653#false} is VALID [2022-02-21 04:24:47,573 INFO L290 TraceCheckUtils]: 74: Hoare triple {26653#false} assume 1 == ~t4_pc~0; {26653#false} is VALID [2022-02-21 04:24:47,573 INFO L290 TraceCheckUtils]: 75: Hoare triple {26653#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26653#false} is VALID [2022-02-21 04:24:47,573 INFO L290 TraceCheckUtils]: 76: Hoare triple {26653#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26653#false} is VALID [2022-02-21 04:24:47,573 INFO L290 TraceCheckUtils]: 77: Hoare triple {26653#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26653#false} is VALID [2022-02-21 04:24:47,574 INFO L290 TraceCheckUtils]: 78: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___3~0#1); {26653#false} is VALID [2022-02-21 04:24:47,574 INFO L290 TraceCheckUtils]: 79: Hoare triple {26653#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26653#false} is VALID [2022-02-21 04:24:47,574 INFO L290 TraceCheckUtils]: 80: Hoare triple {26653#false} assume 1 == ~t5_pc~0; {26653#false} is VALID [2022-02-21 04:24:47,574 INFO L290 TraceCheckUtils]: 81: Hoare triple {26653#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {26653#false} is VALID [2022-02-21 04:24:47,574 INFO L290 TraceCheckUtils]: 82: Hoare triple {26653#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26653#false} is VALID [2022-02-21 04:24:47,574 INFO L290 TraceCheckUtils]: 83: Hoare triple {26653#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26653#false} is VALID [2022-02-21 04:24:47,574 INFO L290 TraceCheckUtils]: 84: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___4~0#1); {26653#false} is VALID [2022-02-21 04:24:47,575 INFO L290 TraceCheckUtils]: 85: Hoare triple {26653#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26653#false} is VALID [2022-02-21 04:24:47,575 INFO L290 TraceCheckUtils]: 86: Hoare triple {26653#false} assume !(1 == ~t6_pc~0); {26653#false} is VALID [2022-02-21 04:24:47,575 INFO L290 TraceCheckUtils]: 87: Hoare triple {26653#false} is_transmit6_triggered_~__retres1~6#1 := 0; {26653#false} is VALID [2022-02-21 04:24:47,575 INFO L290 TraceCheckUtils]: 88: Hoare triple {26653#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26653#false} is VALID [2022-02-21 04:24:47,575 INFO L290 TraceCheckUtils]: 89: Hoare triple {26653#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26653#false} is VALID [2022-02-21 04:24:47,575 INFO L290 TraceCheckUtils]: 90: Hoare triple {26653#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26653#false} is VALID [2022-02-21 04:24:47,575 INFO L290 TraceCheckUtils]: 91: Hoare triple {26653#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26653#false} is VALID [2022-02-21 04:24:47,576 INFO L290 TraceCheckUtils]: 92: Hoare triple {26653#false} assume 1 == ~t7_pc~0; {26653#false} is VALID [2022-02-21 04:24:47,576 INFO L290 TraceCheckUtils]: 93: Hoare triple {26653#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {26653#false} is VALID [2022-02-21 04:24:47,576 INFO L290 TraceCheckUtils]: 94: Hoare triple {26653#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26653#false} is VALID [2022-02-21 04:24:47,576 INFO L290 TraceCheckUtils]: 95: Hoare triple {26653#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26653#false} is VALID [2022-02-21 04:24:47,576 INFO L290 TraceCheckUtils]: 96: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___6~0#1); {26653#false} is VALID [2022-02-21 04:24:47,576 INFO L290 TraceCheckUtils]: 97: Hoare triple {26653#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26653#false} is VALID [2022-02-21 04:24:47,576 INFO L290 TraceCheckUtils]: 98: Hoare triple {26653#false} assume !(1 == ~t8_pc~0); {26653#false} is VALID [2022-02-21 04:24:47,577 INFO L290 TraceCheckUtils]: 99: Hoare triple {26653#false} is_transmit8_triggered_~__retres1~8#1 := 0; {26653#false} is VALID [2022-02-21 04:24:47,577 INFO L290 TraceCheckUtils]: 100: Hoare triple {26653#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26653#false} is VALID [2022-02-21 04:24:47,577 INFO L290 TraceCheckUtils]: 101: Hoare triple {26653#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26653#false} is VALID [2022-02-21 04:24:47,577 INFO L290 TraceCheckUtils]: 102: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___7~0#1); {26653#false} is VALID [2022-02-21 04:24:47,577 INFO L290 TraceCheckUtils]: 103: Hoare triple {26653#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26653#false} is VALID [2022-02-21 04:24:47,577 INFO L290 TraceCheckUtils]: 104: Hoare triple {26653#false} assume 1 == ~t9_pc~0; {26653#false} is VALID [2022-02-21 04:24:47,577 INFO L290 TraceCheckUtils]: 105: Hoare triple {26653#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26653#false} is VALID [2022-02-21 04:24:47,578 INFO L290 TraceCheckUtils]: 106: Hoare triple {26653#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26653#false} is VALID [2022-02-21 04:24:47,578 INFO L290 TraceCheckUtils]: 107: Hoare triple {26653#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26653#false} is VALID [2022-02-21 04:24:47,578 INFO L290 TraceCheckUtils]: 108: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___8~0#1); {26653#false} is VALID [2022-02-21 04:24:47,578 INFO L290 TraceCheckUtils]: 109: Hoare triple {26653#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26653#false} is VALID [2022-02-21 04:24:47,578 INFO L290 TraceCheckUtils]: 110: Hoare triple {26653#false} assume !(1 == ~t10_pc~0); {26653#false} is VALID [2022-02-21 04:24:47,578 INFO L290 TraceCheckUtils]: 111: Hoare triple {26653#false} is_transmit10_triggered_~__retres1~10#1 := 0; {26653#false} is VALID [2022-02-21 04:24:47,578 INFO L290 TraceCheckUtils]: 112: Hoare triple {26653#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26653#false} is VALID [2022-02-21 04:24:47,578 INFO L290 TraceCheckUtils]: 113: Hoare triple {26653#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {26653#false} is VALID [2022-02-21 04:24:47,579 INFO L290 TraceCheckUtils]: 114: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___9~0#1); {26653#false} is VALID [2022-02-21 04:24:47,579 INFO L290 TraceCheckUtils]: 115: Hoare triple {26653#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26653#false} is VALID [2022-02-21 04:24:47,579 INFO L290 TraceCheckUtils]: 116: Hoare triple {26653#false} assume 1 == ~t11_pc~0; {26653#false} is VALID [2022-02-21 04:24:47,579 INFO L290 TraceCheckUtils]: 117: Hoare triple {26653#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {26653#false} is VALID [2022-02-21 04:24:47,579 INFO L290 TraceCheckUtils]: 118: Hoare triple {26653#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26653#false} is VALID [2022-02-21 04:24:47,579 INFO L290 TraceCheckUtils]: 119: Hoare triple {26653#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {26653#false} is VALID [2022-02-21 04:24:47,579 INFO L290 TraceCheckUtils]: 120: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___10~0#1); {26653#false} is VALID [2022-02-21 04:24:47,580 INFO L290 TraceCheckUtils]: 121: Hoare triple {26653#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {26653#false} is VALID [2022-02-21 04:24:47,580 INFO L290 TraceCheckUtils]: 122: Hoare triple {26653#false} assume !(1 == ~t12_pc~0); {26653#false} is VALID [2022-02-21 04:24:47,580 INFO L290 TraceCheckUtils]: 123: Hoare triple {26653#false} is_transmit12_triggered_~__retres1~12#1 := 0; {26653#false} is VALID [2022-02-21 04:24:47,580 INFO L290 TraceCheckUtils]: 124: Hoare triple {26653#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {26653#false} is VALID [2022-02-21 04:24:47,580 INFO L290 TraceCheckUtils]: 125: Hoare triple {26653#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {26653#false} is VALID [2022-02-21 04:24:47,580 INFO L290 TraceCheckUtils]: 126: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___11~0#1); {26653#false} is VALID [2022-02-21 04:24:47,580 INFO L290 TraceCheckUtils]: 127: Hoare triple {26653#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {26653#false} is VALID [2022-02-21 04:24:47,580 INFO L290 TraceCheckUtils]: 128: Hoare triple {26653#false} assume 1 == ~t13_pc~0; {26653#false} is VALID [2022-02-21 04:24:47,581 INFO L290 TraceCheckUtils]: 129: Hoare triple {26653#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {26653#false} is VALID [2022-02-21 04:24:47,581 INFO L290 TraceCheckUtils]: 130: Hoare triple {26653#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {26653#false} is VALID [2022-02-21 04:24:47,581 INFO L290 TraceCheckUtils]: 131: Hoare triple {26653#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {26653#false} is VALID [2022-02-21 04:24:47,581 INFO L290 TraceCheckUtils]: 132: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___12~0#1); {26653#false} is VALID [2022-02-21 04:24:47,581 INFO L290 TraceCheckUtils]: 133: Hoare triple {26653#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {26653#false} is VALID [2022-02-21 04:24:47,581 INFO L290 TraceCheckUtils]: 134: Hoare triple {26653#false} assume 1 == ~t14_pc~0; {26653#false} is VALID [2022-02-21 04:24:47,581 INFO L290 TraceCheckUtils]: 135: Hoare triple {26653#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {26653#false} is VALID [2022-02-21 04:24:47,582 INFO L290 TraceCheckUtils]: 136: Hoare triple {26653#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {26653#false} is VALID [2022-02-21 04:24:47,582 INFO L290 TraceCheckUtils]: 137: Hoare triple {26653#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {26653#false} is VALID [2022-02-21 04:24:47,582 INFO L290 TraceCheckUtils]: 138: Hoare triple {26653#false} assume !(0 != activate_threads_~tmp___13~0#1); {26653#false} is VALID [2022-02-21 04:24:47,582 INFO L290 TraceCheckUtils]: 139: Hoare triple {26653#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26653#false} is VALID [2022-02-21 04:24:47,582 INFO L290 TraceCheckUtils]: 140: Hoare triple {26653#false} assume 1 == ~M_E~0;~M_E~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,582 INFO L290 TraceCheckUtils]: 141: Hoare triple {26653#false} assume !(1 == ~T1_E~0); {26653#false} is VALID [2022-02-21 04:24:47,582 INFO L290 TraceCheckUtils]: 142: Hoare triple {26653#false} assume !(1 == ~T2_E~0); {26653#false} is VALID [2022-02-21 04:24:47,583 INFO L290 TraceCheckUtils]: 143: Hoare triple {26653#false} assume !(1 == ~T3_E~0); {26653#false} is VALID [2022-02-21 04:24:47,583 INFO L290 TraceCheckUtils]: 144: Hoare triple {26653#false} assume !(1 == ~T4_E~0); {26653#false} is VALID [2022-02-21 04:24:47,583 INFO L290 TraceCheckUtils]: 145: Hoare triple {26653#false} assume !(1 == ~T5_E~0); {26653#false} is VALID [2022-02-21 04:24:47,583 INFO L290 TraceCheckUtils]: 146: Hoare triple {26653#false} assume !(1 == ~T6_E~0); {26653#false} is VALID [2022-02-21 04:24:47,583 INFO L290 TraceCheckUtils]: 147: Hoare triple {26653#false} assume !(1 == ~T7_E~0); {26653#false} is VALID [2022-02-21 04:24:47,583 INFO L290 TraceCheckUtils]: 148: Hoare triple {26653#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,583 INFO L290 TraceCheckUtils]: 149: Hoare triple {26653#false} assume !(1 == ~T9_E~0); {26653#false} is VALID [2022-02-21 04:24:47,584 INFO L290 TraceCheckUtils]: 150: Hoare triple {26653#false} assume !(1 == ~T10_E~0); {26653#false} is VALID [2022-02-21 04:24:47,584 INFO L290 TraceCheckUtils]: 151: Hoare triple {26653#false} assume !(1 == ~T11_E~0); {26653#false} is VALID [2022-02-21 04:24:47,584 INFO L290 TraceCheckUtils]: 152: Hoare triple {26653#false} assume !(1 == ~T12_E~0); {26653#false} is VALID [2022-02-21 04:24:47,584 INFO L290 TraceCheckUtils]: 153: Hoare triple {26653#false} assume !(1 == ~T13_E~0); {26653#false} is VALID [2022-02-21 04:24:47,584 INFO L290 TraceCheckUtils]: 154: Hoare triple {26653#false} assume !(1 == ~T14_E~0); {26653#false} is VALID [2022-02-21 04:24:47,584 INFO L290 TraceCheckUtils]: 155: Hoare triple {26653#false} assume !(1 == ~E_1~0); {26653#false} is VALID [2022-02-21 04:24:47,584 INFO L290 TraceCheckUtils]: 156: Hoare triple {26653#false} assume 1 == ~E_2~0;~E_2~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,585 INFO L290 TraceCheckUtils]: 157: Hoare triple {26653#false} assume !(1 == ~E_3~0); {26653#false} is VALID [2022-02-21 04:24:47,585 INFO L290 TraceCheckUtils]: 158: Hoare triple {26653#false} assume !(1 == ~E_4~0); {26653#false} is VALID [2022-02-21 04:24:47,585 INFO L290 TraceCheckUtils]: 159: Hoare triple {26653#false} assume !(1 == ~E_5~0); {26653#false} is VALID [2022-02-21 04:24:47,585 INFO L290 TraceCheckUtils]: 160: Hoare triple {26653#false} assume !(1 == ~E_6~0); {26653#false} is VALID [2022-02-21 04:24:47,585 INFO L290 TraceCheckUtils]: 161: Hoare triple {26653#false} assume !(1 == ~E_7~0); {26653#false} is VALID [2022-02-21 04:24:47,585 INFO L290 TraceCheckUtils]: 162: Hoare triple {26653#false} assume !(1 == ~E_8~0); {26653#false} is VALID [2022-02-21 04:24:47,585 INFO L290 TraceCheckUtils]: 163: Hoare triple {26653#false} assume !(1 == ~E_9~0); {26653#false} is VALID [2022-02-21 04:24:47,586 INFO L290 TraceCheckUtils]: 164: Hoare triple {26653#false} assume 1 == ~E_10~0;~E_10~0 := 2; {26653#false} is VALID [2022-02-21 04:24:47,586 INFO L290 TraceCheckUtils]: 165: Hoare triple {26653#false} assume !(1 == ~E_11~0); {26653#false} is VALID [2022-02-21 04:24:47,586 INFO L290 TraceCheckUtils]: 166: Hoare triple {26653#false} assume !(1 == ~E_12~0); {26653#false} is VALID [2022-02-21 04:24:47,586 INFO L290 TraceCheckUtils]: 167: Hoare triple {26653#false} assume !(1 == ~E_13~0); {26653#false} is VALID [2022-02-21 04:24:47,586 INFO L290 TraceCheckUtils]: 168: Hoare triple {26653#false} assume !(1 == ~E_14~0); {26653#false} is VALID [2022-02-21 04:24:47,586 INFO L290 TraceCheckUtils]: 169: Hoare triple {26653#false} assume { :end_inline_reset_delta_events } true; {26653#false} is VALID [2022-02-21 04:24:47,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:47,587 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:47,587 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986359867] [2022-02-21 04:24:47,588 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986359867] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:47,588 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:47,588 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:47,589 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054545961] [2022-02-21 04:24:47,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:47,589 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:47,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:47,590 INFO L85 PathProgramCache]: Analyzing trace with hash -1715277972, now seen corresponding path program 1 times [2022-02-21 04:24:47,590 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:47,593 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1567922687] [2022-02-21 04:24:47,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:47,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:47,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:47,675 INFO L290 TraceCheckUtils]: 0: Hoare triple {26655#true} assume !false; {26655#true} is VALID [2022-02-21 04:24:47,676 INFO L290 TraceCheckUtils]: 1: Hoare triple {26655#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {26655#true} is VALID [2022-02-21 04:24:47,676 INFO L290 TraceCheckUtils]: 2: Hoare triple {26655#true} assume !false; {26655#true} is VALID [2022-02-21 04:24:47,676 INFO L290 TraceCheckUtils]: 3: Hoare triple {26655#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {26655#true} is VALID [2022-02-21 04:24:47,676 INFO L290 TraceCheckUtils]: 4: Hoare triple {26655#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {26655#true} is VALID [2022-02-21 04:24:47,676 INFO L290 TraceCheckUtils]: 5: Hoare triple {26655#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {26655#true} is VALID [2022-02-21 04:24:47,676 INFO L290 TraceCheckUtils]: 6: Hoare triple {26655#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {26655#true} is VALID [2022-02-21 04:24:47,677 INFO L290 TraceCheckUtils]: 7: Hoare triple {26655#true} assume !(0 != eval_~tmp~0#1); {26655#true} is VALID [2022-02-21 04:24:47,677 INFO L290 TraceCheckUtils]: 8: Hoare triple {26655#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {26655#true} is VALID [2022-02-21 04:24:47,677 INFO L290 TraceCheckUtils]: 9: Hoare triple {26655#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {26655#true} is VALID [2022-02-21 04:24:47,677 INFO L290 TraceCheckUtils]: 10: Hoare triple {26655#true} assume 0 == ~M_E~0;~M_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,677 INFO L290 TraceCheckUtils]: 11: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,678 INFO L290 TraceCheckUtils]: 12: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,678 INFO L290 TraceCheckUtils]: 13: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,678 INFO L290 TraceCheckUtils]: 14: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,678 INFO L290 TraceCheckUtils]: 15: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,679 INFO L290 TraceCheckUtils]: 16: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,679 INFO L290 TraceCheckUtils]: 17: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,679 INFO L290 TraceCheckUtils]: 18: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,680 INFO L290 TraceCheckUtils]: 19: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,680 INFO L290 TraceCheckUtils]: 20: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,680 INFO L290 TraceCheckUtils]: 21: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,680 INFO L290 TraceCheckUtils]: 22: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,681 INFO L290 TraceCheckUtils]: 23: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,681 INFO L290 TraceCheckUtils]: 24: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,681 INFO L290 TraceCheckUtils]: 25: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,681 INFO L290 TraceCheckUtils]: 26: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,682 INFO L290 TraceCheckUtils]: 27: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,682 INFO L290 TraceCheckUtils]: 28: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,682 INFO L290 TraceCheckUtils]: 29: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,683 INFO L290 TraceCheckUtils]: 30: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,683 INFO L290 TraceCheckUtils]: 31: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,683 INFO L290 TraceCheckUtils]: 32: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,683 INFO L290 TraceCheckUtils]: 33: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,684 INFO L290 TraceCheckUtils]: 34: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,684 INFO L290 TraceCheckUtils]: 35: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,684 INFO L290 TraceCheckUtils]: 36: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,684 INFO L290 TraceCheckUtils]: 37: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,685 INFO L290 TraceCheckUtils]: 38: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,685 INFO L290 TraceCheckUtils]: 39: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,685 INFO L290 TraceCheckUtils]: 40: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,686 INFO L290 TraceCheckUtils]: 41: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,686 INFO L290 TraceCheckUtils]: 42: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,686 INFO L290 TraceCheckUtils]: 43: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,686 INFO L290 TraceCheckUtils]: 44: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,687 INFO L290 TraceCheckUtils]: 45: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,687 INFO L290 TraceCheckUtils]: 46: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,687 INFO L290 TraceCheckUtils]: 47: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,687 INFO L290 TraceCheckUtils]: 48: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,688 INFO L290 TraceCheckUtils]: 49: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,688 INFO L290 TraceCheckUtils]: 50: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,688 INFO L290 TraceCheckUtils]: 51: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,689 INFO L290 TraceCheckUtils]: 52: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,689 INFO L290 TraceCheckUtils]: 53: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,689 INFO L290 TraceCheckUtils]: 54: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,689 INFO L290 TraceCheckUtils]: 55: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,690 INFO L290 TraceCheckUtils]: 56: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,690 INFO L290 TraceCheckUtils]: 57: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,690 INFO L290 TraceCheckUtils]: 58: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,690 INFO L290 TraceCheckUtils]: 59: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,691 INFO L290 TraceCheckUtils]: 60: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,691 INFO L290 TraceCheckUtils]: 61: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,691 INFO L290 TraceCheckUtils]: 62: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,692 INFO L290 TraceCheckUtils]: 63: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,692 INFO L290 TraceCheckUtils]: 64: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,692 INFO L290 TraceCheckUtils]: 65: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,692 INFO L290 TraceCheckUtils]: 66: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,693 INFO L290 TraceCheckUtils]: 67: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,693 INFO L290 TraceCheckUtils]: 68: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,693 INFO L290 TraceCheckUtils]: 69: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,693 INFO L290 TraceCheckUtils]: 70: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,694 INFO L290 TraceCheckUtils]: 71: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,694 INFO L290 TraceCheckUtils]: 72: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,694 INFO L290 TraceCheckUtils]: 73: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,695 INFO L290 TraceCheckUtils]: 74: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,695 INFO L290 TraceCheckUtils]: 75: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,695 INFO L290 TraceCheckUtils]: 76: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,695 INFO L290 TraceCheckUtils]: 77: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,696 INFO L290 TraceCheckUtils]: 78: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,696 INFO L290 TraceCheckUtils]: 79: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,696 INFO L290 TraceCheckUtils]: 80: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,696 INFO L290 TraceCheckUtils]: 81: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,697 INFO L290 TraceCheckUtils]: 82: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,697 INFO L290 TraceCheckUtils]: 83: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,697 INFO L290 TraceCheckUtils]: 84: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,698 INFO L290 TraceCheckUtils]: 85: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,698 INFO L290 TraceCheckUtils]: 86: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,698 INFO L290 TraceCheckUtils]: 87: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,698 INFO L290 TraceCheckUtils]: 88: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,699 INFO L290 TraceCheckUtils]: 89: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,699 INFO L290 TraceCheckUtils]: 90: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,699 INFO L290 TraceCheckUtils]: 91: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,699 INFO L290 TraceCheckUtils]: 92: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,700 INFO L290 TraceCheckUtils]: 93: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,700 INFO L290 TraceCheckUtils]: 94: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,700 INFO L290 TraceCheckUtils]: 95: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,701 INFO L290 TraceCheckUtils]: 96: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,701 INFO L290 TraceCheckUtils]: 97: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,701 INFO L290 TraceCheckUtils]: 98: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,701 INFO L290 TraceCheckUtils]: 99: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,702 INFO L290 TraceCheckUtils]: 100: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,702 INFO L290 TraceCheckUtils]: 101: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,702 INFO L290 TraceCheckUtils]: 102: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,702 INFO L290 TraceCheckUtils]: 103: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,703 INFO L290 TraceCheckUtils]: 104: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,703 INFO L290 TraceCheckUtils]: 105: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,703 INFO L290 TraceCheckUtils]: 106: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,704 INFO L290 TraceCheckUtils]: 107: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,704 INFO L290 TraceCheckUtils]: 108: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,704 INFO L290 TraceCheckUtils]: 109: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,704 INFO L290 TraceCheckUtils]: 110: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,705 INFO L290 TraceCheckUtils]: 111: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,705 INFO L290 TraceCheckUtils]: 112: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,705 INFO L290 TraceCheckUtils]: 113: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,705 INFO L290 TraceCheckUtils]: 114: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,706 INFO L290 TraceCheckUtils]: 115: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,706 INFO L290 TraceCheckUtils]: 116: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,706 INFO L290 TraceCheckUtils]: 117: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,707 INFO L290 TraceCheckUtils]: 118: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t13_pc~0); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,707 INFO L290 TraceCheckUtils]: 119: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,707 INFO L290 TraceCheckUtils]: 120: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,707 INFO L290 TraceCheckUtils]: 121: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,708 INFO L290 TraceCheckUtils]: 122: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,708 INFO L290 TraceCheckUtils]: 123: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,708 INFO L290 TraceCheckUtils]: 124: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,708 INFO L290 TraceCheckUtils]: 125: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,709 INFO L290 TraceCheckUtils]: 126: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,709 INFO L290 TraceCheckUtils]: 127: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,709 INFO L290 TraceCheckUtils]: 128: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,710 INFO L290 TraceCheckUtils]: 129: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26657#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:47,710 INFO L290 TraceCheckUtils]: 130: Hoare triple {26657#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {26656#false} is VALID [2022-02-21 04:24:47,710 INFO L290 TraceCheckUtils]: 131: Hoare triple {26656#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,710 INFO L290 TraceCheckUtils]: 132: Hoare triple {26656#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,710 INFO L290 TraceCheckUtils]: 133: Hoare triple {26656#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,710 INFO L290 TraceCheckUtils]: 134: Hoare triple {26656#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,710 INFO L290 TraceCheckUtils]: 135: Hoare triple {26656#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,711 INFO L290 TraceCheckUtils]: 136: Hoare triple {26656#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,711 INFO L290 TraceCheckUtils]: 137: Hoare triple {26656#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,711 INFO L290 TraceCheckUtils]: 138: Hoare triple {26656#false} assume !(1 == ~T8_E~0); {26656#false} is VALID [2022-02-21 04:24:47,711 INFO L290 TraceCheckUtils]: 139: Hoare triple {26656#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,711 INFO L290 TraceCheckUtils]: 140: Hoare triple {26656#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,711 INFO L290 TraceCheckUtils]: 141: Hoare triple {26656#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,711 INFO L290 TraceCheckUtils]: 142: Hoare triple {26656#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,711 INFO L290 TraceCheckUtils]: 143: Hoare triple {26656#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,711 INFO L290 TraceCheckUtils]: 144: Hoare triple {26656#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,712 INFO L290 TraceCheckUtils]: 145: Hoare triple {26656#false} assume 1 == ~E_1~0;~E_1~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,712 INFO L290 TraceCheckUtils]: 146: Hoare triple {26656#false} assume !(1 == ~E_2~0); {26656#false} is VALID [2022-02-21 04:24:47,712 INFO L290 TraceCheckUtils]: 147: Hoare triple {26656#false} assume 1 == ~E_3~0;~E_3~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,712 INFO L290 TraceCheckUtils]: 148: Hoare triple {26656#false} assume 1 == ~E_4~0;~E_4~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,712 INFO L290 TraceCheckUtils]: 149: Hoare triple {26656#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,712 INFO L290 TraceCheckUtils]: 150: Hoare triple {26656#false} assume 1 == ~E_6~0;~E_6~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,712 INFO L290 TraceCheckUtils]: 151: Hoare triple {26656#false} assume 1 == ~E_7~0;~E_7~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,712 INFO L290 TraceCheckUtils]: 152: Hoare triple {26656#false} assume 1 == ~E_8~0;~E_8~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,712 INFO L290 TraceCheckUtils]: 153: Hoare triple {26656#false} assume 1 == ~E_9~0;~E_9~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,713 INFO L290 TraceCheckUtils]: 154: Hoare triple {26656#false} assume !(1 == ~E_10~0); {26656#false} is VALID [2022-02-21 04:24:47,713 INFO L290 TraceCheckUtils]: 155: Hoare triple {26656#false} assume 1 == ~E_11~0;~E_11~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,713 INFO L290 TraceCheckUtils]: 156: Hoare triple {26656#false} assume 1 == ~E_12~0;~E_12~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,713 INFO L290 TraceCheckUtils]: 157: Hoare triple {26656#false} assume 1 == ~E_13~0;~E_13~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,713 INFO L290 TraceCheckUtils]: 158: Hoare triple {26656#false} assume 1 == ~E_14~0;~E_14~0 := 2; {26656#false} is VALID [2022-02-21 04:24:47,713 INFO L290 TraceCheckUtils]: 159: Hoare triple {26656#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {26656#false} is VALID [2022-02-21 04:24:47,713 INFO L290 TraceCheckUtils]: 160: Hoare triple {26656#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {26656#false} is VALID [2022-02-21 04:24:47,713 INFO L290 TraceCheckUtils]: 161: Hoare triple {26656#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {26656#false} is VALID [2022-02-21 04:24:47,713 INFO L290 TraceCheckUtils]: 162: Hoare triple {26656#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {26656#false} is VALID [2022-02-21 04:24:47,714 INFO L290 TraceCheckUtils]: 163: Hoare triple {26656#false} assume !(0 == start_simulation_~tmp~3#1); {26656#false} is VALID [2022-02-21 04:24:47,714 INFO L290 TraceCheckUtils]: 164: Hoare triple {26656#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {26656#false} is VALID [2022-02-21 04:24:47,714 INFO L290 TraceCheckUtils]: 165: Hoare triple {26656#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {26656#false} is VALID [2022-02-21 04:24:47,714 INFO L290 TraceCheckUtils]: 166: Hoare triple {26656#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {26656#false} is VALID [2022-02-21 04:24:47,714 INFO L290 TraceCheckUtils]: 167: Hoare triple {26656#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {26656#false} is VALID [2022-02-21 04:24:47,714 INFO L290 TraceCheckUtils]: 168: Hoare triple {26656#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {26656#false} is VALID [2022-02-21 04:24:47,714 INFO L290 TraceCheckUtils]: 169: Hoare triple {26656#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {26656#false} is VALID [2022-02-21 04:24:47,714 INFO L290 TraceCheckUtils]: 170: Hoare triple {26656#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {26656#false} is VALID [2022-02-21 04:24:47,715 INFO L290 TraceCheckUtils]: 171: Hoare triple {26656#false} assume !(0 != start_simulation_~tmp___0~1#1); {26656#false} is VALID [2022-02-21 04:24:47,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:47,715 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:47,716 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1567922687] [2022-02-21 04:24:47,716 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1567922687] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:47,716 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:47,716 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:47,716 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885911297] [2022-02-21 04:24:47,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:47,717 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:47,717 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:47,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:47,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:47,717 INFO L87 Difference]: Start difference. First operand 2047 states and 3032 transitions. cyclomatic complexity: 986 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:49,159 INFO L93 Difference]: Finished difference Result 2047 states and 3031 transitions. [2022-02-21 04:24:49,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:49,159 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,266 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:49,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3031 transitions. [2022-02-21 04:24:49,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:49,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3031 transitions. [2022-02-21 04:24:49,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:24:49,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:24:49,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3031 transitions. [2022-02-21 04:24:49,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:49,623 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2022-02-21 04:24:49,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3031 transitions. [2022-02-21 04:24:49,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:24:49,666 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:49,668 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3031 transitions. Second operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,670 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3031 transitions. Second operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,672 INFO L87 Difference]: Start difference. First operand 2047 states and 3031 transitions. Second operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:49,759 INFO L93 Difference]: Finished difference Result 2047 states and 3031 transitions. [2022-02-21 04:24:49,759 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3031 transitions. [2022-02-21 04:24:49,760 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:49,761 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:49,763 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3031 transitions. [2022-02-21 04:24:49,765 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3031 transitions. [2022-02-21 04:24:49,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:49,875 INFO L93 Difference]: Finished difference Result 2047 states and 3031 transitions. [2022-02-21 04:24:49,875 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3031 transitions. [2022-02-21 04:24:49,877 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:49,877 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:49,877 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:49,878 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:49,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3031 transitions. [2022-02-21 04:24:49,992 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2022-02-21 04:24:49,992 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2022-02-21 04:24:49,992 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:49,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3031 transitions. [2022-02-21 04:24:49,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:49,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:49,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:49,999 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:49,999 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:50,000 INFO L791 eck$LassoCheckResult]: Stem: 29631#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 29632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 30234#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29351#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29352#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 29597#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29598#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29325#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29326#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 30549#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 29901#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 29902#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30419#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29811#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29812#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29232#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29233#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29564#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29762#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 28809#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28810#L1342 assume !(0 == ~M_E~0); 28975#L1342-2 assume !(0 == ~T1_E~0); 29531#L1347-1 assume !(0 == ~T2_E~0); 30532#L1352-1 assume !(0 == ~T3_E~0); 30328#L1357-1 assume !(0 == ~T4_E~0); 29556#L1362-1 assume !(0 == ~T5_E~0); 29557#L1367-1 assume !(0 == ~T6_E~0); 29154#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29155#L1377-1 assume !(0 == ~T8_E~0); 29485#L1382-1 assume !(0 == ~T9_E~0); 29486#L1387-1 assume !(0 == ~T10_E~0); 30213#L1392-1 assume !(0 == ~T11_E~0); 29517#L1397-1 assume !(0 == ~T12_E~0); 29518#L1402-1 assume !(0 == ~T13_E~0); 29170#L1407-1 assume !(0 == ~T14_E~0); 29171#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30449#L1417-1 assume !(0 == ~E_2~0); 30450#L1422-1 assume !(0 == ~E_3~0); 30691#L1427-1 assume !(0 == ~E_4~0); 29358#L1432-1 assume !(0 == ~E_5~0); 29359#L1437-1 assume !(0 == ~E_6~0); 30367#L1442-1 assume !(0 == ~E_7~0); 30368#L1447-1 assume !(0 == ~E_8~0); 30210#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28945#L1457-1 assume !(0 == ~E_10~0); 28946#L1462-1 assume !(0 == ~E_11~0); 30402#L1467-1 assume !(0 == ~E_12~0); 30414#L1472-1 assume !(0 == ~E_13~0); 30415#L1477-1 assume !(0 == ~E_14~0); 30157#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29144#L646 assume 1 == ~m_pc~0; 29145#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29821#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29836#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29234#L1666 assume !(0 != activate_threads_~tmp~1#1); 29235#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30712#L665 assume !(1 == ~t1_pc~0); 29710#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29711#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29243#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29244#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 30034#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30035#L684 assume 1 == ~t2_pc~0; 30152#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30076#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30141#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30536#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 30537#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30725#L703 assume !(1 == ~t3_pc~0); 29380#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29381#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30027#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28779#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 28780#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29265#L722 assume 1 == ~t4_pc~0; 30003#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29446#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29791#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30351#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 29858#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28976#L741 assume 1 == ~t5_pc~0; 28977#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29287#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29441#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29442#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 30121#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29532#L760 assume !(1 == ~t6_pc~0); 29379#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29378#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29236#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29237#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29958#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29959#L779 assume 1 == ~t7_pc~0; 29021#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28867#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28868#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29276#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 29299#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29300#L798 assume !(1 == ~t8_pc~0); 30581#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30504#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29023#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29024#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 30714#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28844#L817 assume 1 == ~t9_pc~0; 28845#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29639#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29640#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30162#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 29250#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29251#L836 assume !(1 == ~t10_pc~0); 29267#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29198#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29199#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29447#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 29448#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30514#L855 assume 1 == ~t11_pc~0; 29832#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29833#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30397#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30206#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 30041#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29140#L874 assume !(1 == ~t12_pc~0); 29141#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29308#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29309#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29449#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 28817#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28818#L893 assume 1 == ~t13_pc~0; 30648#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29173#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29484#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30575#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 30583#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 30584#L912 assume 1 == ~t14_pc~0; 30374#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 30375#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 29143#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29075#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 29076#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29851#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 30267#L1495-2 assume !(1 == ~T1_E~0); 30268#L1500-1 assume !(1 == ~T2_E~0); 29954#L1505-1 assume !(1 == ~T3_E~0); 29955#L1510-1 assume !(1 == ~T4_E~0); 30012#L1515-1 assume !(1 == ~T5_E~0); 30013#L1520-1 assume !(1 == ~T6_E~0); 30582#L1525-1 assume !(1 == ~T7_E~0); 30292#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29245#L1535-1 assume !(1 == ~T9_E~0); 29246#L1540-1 assume !(1 == ~T10_E~0); 28738#L1545-1 assume !(1 == ~T11_E~0); 28739#L1550-1 assume !(1 == ~T12_E~0); 28987#L1555-1 assume !(1 == ~T13_E~0); 28988#L1560-1 assume !(1 == ~T14_E~0); 29288#L1565-1 assume !(1 == ~E_1~0); 30701#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30179#L1575-1 assume !(1 == ~E_3~0); 29558#L1580-1 assume !(1 == ~E_4~0); 29559#L1585-1 assume !(1 == ~E_5~0); 30029#L1590-1 assume !(1 == ~E_6~0); 29593#L1595-1 assume !(1 == ~E_7~0); 29594#L1600-1 assume !(1 == ~E_8~0); 29966#L1605-1 assume !(1 == ~E_9~0); 29967#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30484#L1615-1 assume !(1 == ~E_11~0); 29423#L1620-1 assume !(1 == ~E_12~0); 29424#L1625-1 assume !(1 == ~E_13~0); 30211#L1630-1 assume !(1 == ~E_14~0); 29592#L1635-1 assume { :end_inline_reset_delta_events } true; 29533#L2017-2 [2022-02-21 04:24:50,000 INFO L793 eck$LassoCheckResult]: Loop: 29533#L2017-2 assume !false; 28813#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28814#L1316 assume !false; 30142#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30204#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28751#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 28893#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28894#L1115 assume !(0 != eval_~tmp~0#1); 30227#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29648#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29649#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29831#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30332#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30001#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30002#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30564#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30739#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30734#L1372-3 assume !(0 == ~T7_E~0); 28795#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28796#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29465#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29466#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30377#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 30687#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29945#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 29101#L1412-3 assume !(0 == ~E_1~0); 29102#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29866#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29867#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30561#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30248#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29960#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29961#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28861#L1452-3 assume !(0 == ~E_9~0); 28862#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30500#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30501#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 30305#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30306#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 29099#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29100#L646-42 assume 1 == ~m_pc~0; 29685#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30533#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30534#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30672#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30673#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30465#L665-42 assume 1 == ~t1_pc~0; 30426#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30428#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30614#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29268#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29269#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30738#L684-42 assume 1 == ~t2_pc~0; 30117#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30118#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30728#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29897#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29898#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30020#L703-42 assume 1 == ~t3_pc~0; 30218#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30219#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29537#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29538#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30312#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29932#L722-42 assume 1 == ~t4_pc~0; 29933#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30343#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29586#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29413#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29414#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30708#L741-42 assume !(1 == ~t5_pc~0); 30325#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 29795#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29796#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30741#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29703#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29704#L760-42 assume !(1 == ~t6_pc~0); 29838#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 29973#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29974#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30362#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 29655#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29656#L779-42 assume !(1 == ~t7_pc~0); 30432#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 30433#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29340#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29341#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29196#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29197#L798-42 assume !(1 == ~t8_pc~0); 28807#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 28808#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30551#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29997#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29027#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29028#L817-42 assume 1 == ~t9_pc~0; 29801#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29311#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29312#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29438#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30243#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30244#L836-42 assume 1 == ~t10_pc~0; 30336#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 29349#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29350#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30651#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30652#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30693#L855-42 assume 1 == ~t11_pc~0; 30706#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28900#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28901#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29650#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30413#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29514#L874-42 assume 1 == ~t12_pc~0; 29515#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29754#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28815#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28816#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29069#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29070#L893-42 assume 1 == ~t13_pc~0; 30272#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30054#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30069#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29971#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 29443#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 29444#L912-42 assume 1 == ~t14_pc~0; 30688#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 28761#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 28762#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30342#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 29189#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29190#L1495-3 assume !(1 == ~M_E~0); 29805#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30233#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30326#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29419#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29382#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29383#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30040#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30263#L1530-3 assume !(1 == ~T8_E~0); 29228#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29229#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29266#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30523#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30632#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29672#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 29673#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30288#L1570-3 assume !(1 == ~E_2~0); 30239#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30240#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30595#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30639#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30685#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30062#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30063#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30538#L1610-3 assume !(1 == ~E_10~0); 29425#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29426#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30030#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30031#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 29935#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 29366#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28971#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29709#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 30265#L2036 assume !(0 == start_simulation_~tmp~3#1); 30266#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30418#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29578#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 30596#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 29978#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 29979#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30699#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30700#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 29533#L2017-2 [2022-02-21 04:24:50,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:50,001 INFO L85 PathProgramCache]: Analyzing trace with hash -723156570, now seen corresponding path program 1 times [2022-02-21 04:24:50,001 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:50,001 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7676121] [2022-02-21 04:24:50,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:50,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:50,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:50,036 INFO L290 TraceCheckUtils]: 0: Hoare triple {34849#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {34849#true} is VALID [2022-02-21 04:24:50,036 INFO L290 TraceCheckUtils]: 1: Hoare triple {34849#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {34851#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:50,036 INFO L290 TraceCheckUtils]: 2: Hoare triple {34851#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {34851#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:50,037 INFO L290 TraceCheckUtils]: 3: Hoare triple {34851#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {34851#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:50,037 INFO L290 TraceCheckUtils]: 4: Hoare triple {34851#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {34851#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:50,037 INFO L290 TraceCheckUtils]: 5: Hoare triple {34851#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {34851#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:50,038 INFO L290 TraceCheckUtils]: 6: Hoare triple {34851#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {34851#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:50,038 INFO L290 TraceCheckUtils]: 7: Hoare triple {34851#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {34851#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:50,038 INFO L290 TraceCheckUtils]: 8: Hoare triple {34851#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,038 INFO L290 TraceCheckUtils]: 9: Hoare triple {34850#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,038 INFO L290 TraceCheckUtils]: 10: Hoare triple {34850#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,039 INFO L290 TraceCheckUtils]: 11: Hoare triple {34850#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,039 INFO L290 TraceCheckUtils]: 12: Hoare triple {34850#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,039 INFO L290 TraceCheckUtils]: 13: Hoare triple {34850#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {34850#false} is VALID [2022-02-21 04:24:50,039 INFO L290 TraceCheckUtils]: 14: Hoare triple {34850#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,039 INFO L290 TraceCheckUtils]: 15: Hoare triple {34850#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,039 INFO L290 TraceCheckUtils]: 16: Hoare triple {34850#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,039 INFO L290 TraceCheckUtils]: 17: Hoare triple {34850#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,040 INFO L290 TraceCheckUtils]: 18: Hoare triple {34850#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,040 INFO L290 TraceCheckUtils]: 19: Hoare triple {34850#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {34850#false} is VALID [2022-02-21 04:24:50,040 INFO L290 TraceCheckUtils]: 20: Hoare triple {34850#false} assume !(0 == ~M_E~0); {34850#false} is VALID [2022-02-21 04:24:50,040 INFO L290 TraceCheckUtils]: 21: Hoare triple {34850#false} assume !(0 == ~T1_E~0); {34850#false} is VALID [2022-02-21 04:24:50,040 INFO L290 TraceCheckUtils]: 22: Hoare triple {34850#false} assume !(0 == ~T2_E~0); {34850#false} is VALID [2022-02-21 04:24:50,040 INFO L290 TraceCheckUtils]: 23: Hoare triple {34850#false} assume !(0 == ~T3_E~0); {34850#false} is VALID [2022-02-21 04:24:50,040 INFO L290 TraceCheckUtils]: 24: Hoare triple {34850#false} assume !(0 == ~T4_E~0); {34850#false} is VALID [2022-02-21 04:24:50,041 INFO L290 TraceCheckUtils]: 25: Hoare triple {34850#false} assume !(0 == ~T5_E~0); {34850#false} is VALID [2022-02-21 04:24:50,041 INFO L290 TraceCheckUtils]: 26: Hoare triple {34850#false} assume !(0 == ~T6_E~0); {34850#false} is VALID [2022-02-21 04:24:50,041 INFO L290 TraceCheckUtils]: 27: Hoare triple {34850#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {34850#false} is VALID [2022-02-21 04:24:50,041 INFO L290 TraceCheckUtils]: 28: Hoare triple {34850#false} assume !(0 == ~T8_E~0); {34850#false} is VALID [2022-02-21 04:24:50,041 INFO L290 TraceCheckUtils]: 29: Hoare triple {34850#false} assume !(0 == ~T9_E~0); {34850#false} is VALID [2022-02-21 04:24:50,041 INFO L290 TraceCheckUtils]: 30: Hoare triple {34850#false} assume !(0 == ~T10_E~0); {34850#false} is VALID [2022-02-21 04:24:50,041 INFO L290 TraceCheckUtils]: 31: Hoare triple {34850#false} assume !(0 == ~T11_E~0); {34850#false} is VALID [2022-02-21 04:24:50,041 INFO L290 TraceCheckUtils]: 32: Hoare triple {34850#false} assume !(0 == ~T12_E~0); {34850#false} is VALID [2022-02-21 04:24:50,042 INFO L290 TraceCheckUtils]: 33: Hoare triple {34850#false} assume !(0 == ~T13_E~0); {34850#false} is VALID [2022-02-21 04:24:50,042 INFO L290 TraceCheckUtils]: 34: Hoare triple {34850#false} assume !(0 == ~T14_E~0); {34850#false} is VALID [2022-02-21 04:24:50,042 INFO L290 TraceCheckUtils]: 35: Hoare triple {34850#false} assume 0 == ~E_1~0;~E_1~0 := 1; {34850#false} is VALID [2022-02-21 04:24:50,042 INFO L290 TraceCheckUtils]: 36: Hoare triple {34850#false} assume !(0 == ~E_2~0); {34850#false} is VALID [2022-02-21 04:24:50,042 INFO L290 TraceCheckUtils]: 37: Hoare triple {34850#false} assume !(0 == ~E_3~0); {34850#false} is VALID [2022-02-21 04:24:50,042 INFO L290 TraceCheckUtils]: 38: Hoare triple {34850#false} assume !(0 == ~E_4~0); {34850#false} is VALID [2022-02-21 04:24:50,042 INFO L290 TraceCheckUtils]: 39: Hoare triple {34850#false} assume !(0 == ~E_5~0); {34850#false} is VALID [2022-02-21 04:24:50,043 INFO L290 TraceCheckUtils]: 40: Hoare triple {34850#false} assume !(0 == ~E_6~0); {34850#false} is VALID [2022-02-21 04:24:50,043 INFO L290 TraceCheckUtils]: 41: Hoare triple {34850#false} assume !(0 == ~E_7~0); {34850#false} is VALID [2022-02-21 04:24:50,043 INFO L290 TraceCheckUtils]: 42: Hoare triple {34850#false} assume !(0 == ~E_8~0); {34850#false} is VALID [2022-02-21 04:24:50,043 INFO L290 TraceCheckUtils]: 43: Hoare triple {34850#false} assume 0 == ~E_9~0;~E_9~0 := 1; {34850#false} is VALID [2022-02-21 04:24:50,043 INFO L290 TraceCheckUtils]: 44: Hoare triple {34850#false} assume !(0 == ~E_10~0); {34850#false} is VALID [2022-02-21 04:24:50,043 INFO L290 TraceCheckUtils]: 45: Hoare triple {34850#false} assume !(0 == ~E_11~0); {34850#false} is VALID [2022-02-21 04:24:50,043 INFO L290 TraceCheckUtils]: 46: Hoare triple {34850#false} assume !(0 == ~E_12~0); {34850#false} is VALID [2022-02-21 04:24:50,043 INFO L290 TraceCheckUtils]: 47: Hoare triple {34850#false} assume !(0 == ~E_13~0); {34850#false} is VALID [2022-02-21 04:24:50,044 INFO L290 TraceCheckUtils]: 48: Hoare triple {34850#false} assume !(0 == ~E_14~0); {34850#false} is VALID [2022-02-21 04:24:50,044 INFO L290 TraceCheckUtils]: 49: Hoare triple {34850#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34850#false} is VALID [2022-02-21 04:24:50,044 INFO L290 TraceCheckUtils]: 50: Hoare triple {34850#false} assume 1 == ~m_pc~0; {34850#false} is VALID [2022-02-21 04:24:50,044 INFO L290 TraceCheckUtils]: 51: Hoare triple {34850#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {34850#false} is VALID [2022-02-21 04:24:50,044 INFO L290 TraceCheckUtils]: 52: Hoare triple {34850#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34850#false} is VALID [2022-02-21 04:24:50,044 INFO L290 TraceCheckUtils]: 53: Hoare triple {34850#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34850#false} is VALID [2022-02-21 04:24:50,044 INFO L290 TraceCheckUtils]: 54: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp~1#1); {34850#false} is VALID [2022-02-21 04:24:50,045 INFO L290 TraceCheckUtils]: 55: Hoare triple {34850#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34850#false} is VALID [2022-02-21 04:24:50,045 INFO L290 TraceCheckUtils]: 56: Hoare triple {34850#false} assume !(1 == ~t1_pc~0); {34850#false} is VALID [2022-02-21 04:24:50,045 INFO L290 TraceCheckUtils]: 57: Hoare triple {34850#false} is_transmit1_triggered_~__retres1~1#1 := 0; {34850#false} is VALID [2022-02-21 04:24:50,045 INFO L290 TraceCheckUtils]: 58: Hoare triple {34850#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34850#false} is VALID [2022-02-21 04:24:50,045 INFO L290 TraceCheckUtils]: 59: Hoare triple {34850#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34850#false} is VALID [2022-02-21 04:24:50,045 INFO L290 TraceCheckUtils]: 60: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___0~0#1); {34850#false} is VALID [2022-02-21 04:24:50,045 INFO L290 TraceCheckUtils]: 61: Hoare triple {34850#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34850#false} is VALID [2022-02-21 04:24:50,045 INFO L290 TraceCheckUtils]: 62: Hoare triple {34850#false} assume 1 == ~t2_pc~0; {34850#false} is VALID [2022-02-21 04:24:50,046 INFO L290 TraceCheckUtils]: 63: Hoare triple {34850#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34850#false} is VALID [2022-02-21 04:24:50,046 INFO L290 TraceCheckUtils]: 64: Hoare triple {34850#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34850#false} is VALID [2022-02-21 04:24:50,046 INFO L290 TraceCheckUtils]: 65: Hoare triple {34850#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34850#false} is VALID [2022-02-21 04:24:50,046 INFO L290 TraceCheckUtils]: 66: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___1~0#1); {34850#false} is VALID [2022-02-21 04:24:50,046 INFO L290 TraceCheckUtils]: 67: Hoare triple {34850#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34850#false} is VALID [2022-02-21 04:24:50,046 INFO L290 TraceCheckUtils]: 68: Hoare triple {34850#false} assume !(1 == ~t3_pc~0); {34850#false} is VALID [2022-02-21 04:24:50,046 INFO L290 TraceCheckUtils]: 69: Hoare triple {34850#false} is_transmit3_triggered_~__retres1~3#1 := 0; {34850#false} is VALID [2022-02-21 04:24:50,047 INFO L290 TraceCheckUtils]: 70: Hoare triple {34850#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34850#false} is VALID [2022-02-21 04:24:50,047 INFO L290 TraceCheckUtils]: 71: Hoare triple {34850#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34850#false} is VALID [2022-02-21 04:24:50,047 INFO L290 TraceCheckUtils]: 72: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___2~0#1); {34850#false} is VALID [2022-02-21 04:24:50,047 INFO L290 TraceCheckUtils]: 73: Hoare triple {34850#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34850#false} is VALID [2022-02-21 04:24:50,047 INFO L290 TraceCheckUtils]: 74: Hoare triple {34850#false} assume 1 == ~t4_pc~0; {34850#false} is VALID [2022-02-21 04:24:50,047 INFO L290 TraceCheckUtils]: 75: Hoare triple {34850#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34850#false} is VALID [2022-02-21 04:24:50,047 INFO L290 TraceCheckUtils]: 76: Hoare triple {34850#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34850#false} is VALID [2022-02-21 04:24:50,047 INFO L290 TraceCheckUtils]: 77: Hoare triple {34850#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34850#false} is VALID [2022-02-21 04:24:50,048 INFO L290 TraceCheckUtils]: 78: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___3~0#1); {34850#false} is VALID [2022-02-21 04:24:50,048 INFO L290 TraceCheckUtils]: 79: Hoare triple {34850#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34850#false} is VALID [2022-02-21 04:24:50,048 INFO L290 TraceCheckUtils]: 80: Hoare triple {34850#false} assume 1 == ~t5_pc~0; {34850#false} is VALID [2022-02-21 04:24:50,048 INFO L290 TraceCheckUtils]: 81: Hoare triple {34850#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {34850#false} is VALID [2022-02-21 04:24:50,048 INFO L290 TraceCheckUtils]: 82: Hoare triple {34850#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34850#false} is VALID [2022-02-21 04:24:50,048 INFO L290 TraceCheckUtils]: 83: Hoare triple {34850#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34850#false} is VALID [2022-02-21 04:24:50,048 INFO L290 TraceCheckUtils]: 84: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___4~0#1); {34850#false} is VALID [2022-02-21 04:24:50,049 INFO L290 TraceCheckUtils]: 85: Hoare triple {34850#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34850#false} is VALID [2022-02-21 04:24:50,049 INFO L290 TraceCheckUtils]: 86: Hoare triple {34850#false} assume !(1 == ~t6_pc~0); {34850#false} is VALID [2022-02-21 04:24:50,049 INFO L290 TraceCheckUtils]: 87: Hoare triple {34850#false} is_transmit6_triggered_~__retres1~6#1 := 0; {34850#false} is VALID [2022-02-21 04:24:50,049 INFO L290 TraceCheckUtils]: 88: Hoare triple {34850#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34850#false} is VALID [2022-02-21 04:24:50,049 INFO L290 TraceCheckUtils]: 89: Hoare triple {34850#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34850#false} is VALID [2022-02-21 04:24:50,049 INFO L290 TraceCheckUtils]: 90: Hoare triple {34850#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {34850#false} is VALID [2022-02-21 04:24:50,049 INFO L290 TraceCheckUtils]: 91: Hoare triple {34850#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34850#false} is VALID [2022-02-21 04:24:50,050 INFO L290 TraceCheckUtils]: 92: Hoare triple {34850#false} assume 1 == ~t7_pc~0; {34850#false} is VALID [2022-02-21 04:24:50,050 INFO L290 TraceCheckUtils]: 93: Hoare triple {34850#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {34850#false} is VALID [2022-02-21 04:24:50,050 INFO L290 TraceCheckUtils]: 94: Hoare triple {34850#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34850#false} is VALID [2022-02-21 04:24:50,050 INFO L290 TraceCheckUtils]: 95: Hoare triple {34850#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34850#false} is VALID [2022-02-21 04:24:50,050 INFO L290 TraceCheckUtils]: 96: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___6~0#1); {34850#false} is VALID [2022-02-21 04:24:50,050 INFO L290 TraceCheckUtils]: 97: Hoare triple {34850#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34850#false} is VALID [2022-02-21 04:24:50,050 INFO L290 TraceCheckUtils]: 98: Hoare triple {34850#false} assume !(1 == ~t8_pc~0); {34850#false} is VALID [2022-02-21 04:24:50,051 INFO L290 TraceCheckUtils]: 99: Hoare triple {34850#false} is_transmit8_triggered_~__retres1~8#1 := 0; {34850#false} is VALID [2022-02-21 04:24:50,051 INFO L290 TraceCheckUtils]: 100: Hoare triple {34850#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34850#false} is VALID [2022-02-21 04:24:50,051 INFO L290 TraceCheckUtils]: 101: Hoare triple {34850#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34850#false} is VALID [2022-02-21 04:24:50,051 INFO L290 TraceCheckUtils]: 102: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___7~0#1); {34850#false} is VALID [2022-02-21 04:24:50,051 INFO L290 TraceCheckUtils]: 103: Hoare triple {34850#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34850#false} is VALID [2022-02-21 04:24:50,051 INFO L290 TraceCheckUtils]: 104: Hoare triple {34850#false} assume 1 == ~t9_pc~0; {34850#false} is VALID [2022-02-21 04:24:50,051 INFO L290 TraceCheckUtils]: 105: Hoare triple {34850#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34850#false} is VALID [2022-02-21 04:24:50,052 INFO L290 TraceCheckUtils]: 106: Hoare triple {34850#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34850#false} is VALID [2022-02-21 04:24:50,052 INFO L290 TraceCheckUtils]: 107: Hoare triple {34850#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {34850#false} is VALID [2022-02-21 04:24:50,052 INFO L290 TraceCheckUtils]: 108: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___8~0#1); {34850#false} is VALID [2022-02-21 04:24:50,052 INFO L290 TraceCheckUtils]: 109: Hoare triple {34850#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34850#false} is VALID [2022-02-21 04:24:50,052 INFO L290 TraceCheckUtils]: 110: Hoare triple {34850#false} assume !(1 == ~t10_pc~0); {34850#false} is VALID [2022-02-21 04:24:50,052 INFO L290 TraceCheckUtils]: 111: Hoare triple {34850#false} is_transmit10_triggered_~__retres1~10#1 := 0; {34850#false} is VALID [2022-02-21 04:24:50,052 INFO L290 TraceCheckUtils]: 112: Hoare triple {34850#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34850#false} is VALID [2022-02-21 04:24:50,052 INFO L290 TraceCheckUtils]: 113: Hoare triple {34850#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {34850#false} is VALID [2022-02-21 04:24:50,053 INFO L290 TraceCheckUtils]: 114: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___9~0#1); {34850#false} is VALID [2022-02-21 04:24:50,053 INFO L290 TraceCheckUtils]: 115: Hoare triple {34850#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {34850#false} is VALID [2022-02-21 04:24:50,053 INFO L290 TraceCheckUtils]: 116: Hoare triple {34850#false} assume 1 == ~t11_pc~0; {34850#false} is VALID [2022-02-21 04:24:50,053 INFO L290 TraceCheckUtils]: 117: Hoare triple {34850#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {34850#false} is VALID [2022-02-21 04:24:50,053 INFO L290 TraceCheckUtils]: 118: Hoare triple {34850#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {34850#false} is VALID [2022-02-21 04:24:50,053 INFO L290 TraceCheckUtils]: 119: Hoare triple {34850#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {34850#false} is VALID [2022-02-21 04:24:50,053 INFO L290 TraceCheckUtils]: 120: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___10~0#1); {34850#false} is VALID [2022-02-21 04:24:50,054 INFO L290 TraceCheckUtils]: 121: Hoare triple {34850#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {34850#false} is VALID [2022-02-21 04:24:50,054 INFO L290 TraceCheckUtils]: 122: Hoare triple {34850#false} assume !(1 == ~t12_pc~0); {34850#false} is VALID [2022-02-21 04:24:50,054 INFO L290 TraceCheckUtils]: 123: Hoare triple {34850#false} is_transmit12_triggered_~__retres1~12#1 := 0; {34850#false} is VALID [2022-02-21 04:24:50,054 INFO L290 TraceCheckUtils]: 124: Hoare triple {34850#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {34850#false} is VALID [2022-02-21 04:24:50,054 INFO L290 TraceCheckUtils]: 125: Hoare triple {34850#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {34850#false} is VALID [2022-02-21 04:24:50,054 INFO L290 TraceCheckUtils]: 126: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___11~0#1); {34850#false} is VALID [2022-02-21 04:24:50,054 INFO L290 TraceCheckUtils]: 127: Hoare triple {34850#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {34850#false} is VALID [2022-02-21 04:24:50,054 INFO L290 TraceCheckUtils]: 128: Hoare triple {34850#false} assume 1 == ~t13_pc~0; {34850#false} is VALID [2022-02-21 04:24:50,055 INFO L290 TraceCheckUtils]: 129: Hoare triple {34850#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {34850#false} is VALID [2022-02-21 04:24:50,055 INFO L290 TraceCheckUtils]: 130: Hoare triple {34850#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {34850#false} is VALID [2022-02-21 04:24:50,055 INFO L290 TraceCheckUtils]: 131: Hoare triple {34850#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {34850#false} is VALID [2022-02-21 04:24:50,055 INFO L290 TraceCheckUtils]: 132: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___12~0#1); {34850#false} is VALID [2022-02-21 04:24:50,055 INFO L290 TraceCheckUtils]: 133: Hoare triple {34850#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {34850#false} is VALID [2022-02-21 04:24:50,055 INFO L290 TraceCheckUtils]: 134: Hoare triple {34850#false} assume 1 == ~t14_pc~0; {34850#false} is VALID [2022-02-21 04:24:50,055 INFO L290 TraceCheckUtils]: 135: Hoare triple {34850#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {34850#false} is VALID [2022-02-21 04:24:50,055 INFO L290 TraceCheckUtils]: 136: Hoare triple {34850#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {34850#false} is VALID [2022-02-21 04:24:50,055 INFO L290 TraceCheckUtils]: 137: Hoare triple {34850#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {34850#false} is VALID [2022-02-21 04:24:50,056 INFO L290 TraceCheckUtils]: 138: Hoare triple {34850#false} assume !(0 != activate_threads_~tmp___13~0#1); {34850#false} is VALID [2022-02-21 04:24:50,056 INFO L290 TraceCheckUtils]: 139: Hoare triple {34850#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34850#false} is VALID [2022-02-21 04:24:50,056 INFO L290 TraceCheckUtils]: 140: Hoare triple {34850#false} assume 1 == ~M_E~0;~M_E~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,056 INFO L290 TraceCheckUtils]: 141: Hoare triple {34850#false} assume !(1 == ~T1_E~0); {34850#false} is VALID [2022-02-21 04:24:50,056 INFO L290 TraceCheckUtils]: 142: Hoare triple {34850#false} assume !(1 == ~T2_E~0); {34850#false} is VALID [2022-02-21 04:24:50,056 INFO L290 TraceCheckUtils]: 143: Hoare triple {34850#false} assume !(1 == ~T3_E~0); {34850#false} is VALID [2022-02-21 04:24:50,056 INFO L290 TraceCheckUtils]: 144: Hoare triple {34850#false} assume !(1 == ~T4_E~0); {34850#false} is VALID [2022-02-21 04:24:50,056 INFO L290 TraceCheckUtils]: 145: Hoare triple {34850#false} assume !(1 == ~T5_E~0); {34850#false} is VALID [2022-02-21 04:24:50,056 INFO L290 TraceCheckUtils]: 146: Hoare triple {34850#false} assume !(1 == ~T6_E~0); {34850#false} is VALID [2022-02-21 04:24:50,057 INFO L290 TraceCheckUtils]: 147: Hoare triple {34850#false} assume !(1 == ~T7_E~0); {34850#false} is VALID [2022-02-21 04:24:50,057 INFO L290 TraceCheckUtils]: 148: Hoare triple {34850#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,057 INFO L290 TraceCheckUtils]: 149: Hoare triple {34850#false} assume !(1 == ~T9_E~0); {34850#false} is VALID [2022-02-21 04:24:50,057 INFO L290 TraceCheckUtils]: 150: Hoare triple {34850#false} assume !(1 == ~T10_E~0); {34850#false} is VALID [2022-02-21 04:24:50,057 INFO L290 TraceCheckUtils]: 151: Hoare triple {34850#false} assume !(1 == ~T11_E~0); {34850#false} is VALID [2022-02-21 04:24:50,057 INFO L290 TraceCheckUtils]: 152: Hoare triple {34850#false} assume !(1 == ~T12_E~0); {34850#false} is VALID [2022-02-21 04:24:50,057 INFO L290 TraceCheckUtils]: 153: Hoare triple {34850#false} assume !(1 == ~T13_E~0); {34850#false} is VALID [2022-02-21 04:24:50,057 INFO L290 TraceCheckUtils]: 154: Hoare triple {34850#false} assume !(1 == ~T14_E~0); {34850#false} is VALID [2022-02-21 04:24:50,058 INFO L290 TraceCheckUtils]: 155: Hoare triple {34850#false} assume !(1 == ~E_1~0); {34850#false} is VALID [2022-02-21 04:24:50,058 INFO L290 TraceCheckUtils]: 156: Hoare triple {34850#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,058 INFO L290 TraceCheckUtils]: 157: Hoare triple {34850#false} assume !(1 == ~E_3~0); {34850#false} is VALID [2022-02-21 04:24:50,058 INFO L290 TraceCheckUtils]: 158: Hoare triple {34850#false} assume !(1 == ~E_4~0); {34850#false} is VALID [2022-02-21 04:24:50,058 INFO L290 TraceCheckUtils]: 159: Hoare triple {34850#false} assume !(1 == ~E_5~0); {34850#false} is VALID [2022-02-21 04:24:50,058 INFO L290 TraceCheckUtils]: 160: Hoare triple {34850#false} assume !(1 == ~E_6~0); {34850#false} is VALID [2022-02-21 04:24:50,058 INFO L290 TraceCheckUtils]: 161: Hoare triple {34850#false} assume !(1 == ~E_7~0); {34850#false} is VALID [2022-02-21 04:24:50,059 INFO L290 TraceCheckUtils]: 162: Hoare triple {34850#false} assume !(1 == ~E_8~0); {34850#false} is VALID [2022-02-21 04:24:50,059 INFO L290 TraceCheckUtils]: 163: Hoare triple {34850#false} assume !(1 == ~E_9~0); {34850#false} is VALID [2022-02-21 04:24:50,059 INFO L290 TraceCheckUtils]: 164: Hoare triple {34850#false} assume 1 == ~E_10~0;~E_10~0 := 2; {34850#false} is VALID [2022-02-21 04:24:50,059 INFO L290 TraceCheckUtils]: 165: Hoare triple {34850#false} assume !(1 == ~E_11~0); {34850#false} is VALID [2022-02-21 04:24:50,059 INFO L290 TraceCheckUtils]: 166: Hoare triple {34850#false} assume !(1 == ~E_12~0); {34850#false} is VALID [2022-02-21 04:24:50,059 INFO L290 TraceCheckUtils]: 167: Hoare triple {34850#false} assume !(1 == ~E_13~0); {34850#false} is VALID [2022-02-21 04:24:50,059 INFO L290 TraceCheckUtils]: 168: Hoare triple {34850#false} assume !(1 == ~E_14~0); {34850#false} is VALID [2022-02-21 04:24:50,060 INFO L290 TraceCheckUtils]: 169: Hoare triple {34850#false} assume { :end_inline_reset_delta_events } true; {34850#false} is VALID [2022-02-21 04:24:50,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:50,060 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:50,060 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7676121] [2022-02-21 04:24:50,061 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7676121] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:50,061 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:50,061 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:50,061 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644511468] [2022-02-21 04:24:50,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:50,062 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:50,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:50,062 INFO L85 PathProgramCache]: Analyzing trace with hash 1006606669, now seen corresponding path program 1 times [2022-02-21 04:24:50,062 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:50,062 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188500322] [2022-02-21 04:24:50,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:50,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:50,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:50,101 INFO L290 TraceCheckUtils]: 0: Hoare triple {34852#true} assume !false; {34852#true} is VALID [2022-02-21 04:24:50,101 INFO L290 TraceCheckUtils]: 1: Hoare triple {34852#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {34852#true} is VALID [2022-02-21 04:24:50,101 INFO L290 TraceCheckUtils]: 2: Hoare triple {34852#true} assume !false; {34852#true} is VALID [2022-02-21 04:24:50,101 INFO L290 TraceCheckUtils]: 3: Hoare triple {34852#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {34852#true} is VALID [2022-02-21 04:24:50,101 INFO L290 TraceCheckUtils]: 4: Hoare triple {34852#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {34852#true} is VALID [2022-02-21 04:24:50,102 INFO L290 TraceCheckUtils]: 5: Hoare triple {34852#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {34852#true} is VALID [2022-02-21 04:24:50,102 INFO L290 TraceCheckUtils]: 6: Hoare triple {34852#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {34852#true} is VALID [2022-02-21 04:24:50,102 INFO L290 TraceCheckUtils]: 7: Hoare triple {34852#true} assume !(0 != eval_~tmp~0#1); {34852#true} is VALID [2022-02-21 04:24:50,102 INFO L290 TraceCheckUtils]: 8: Hoare triple {34852#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {34852#true} is VALID [2022-02-21 04:24:50,102 INFO L290 TraceCheckUtils]: 9: Hoare triple {34852#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {34852#true} is VALID [2022-02-21 04:24:50,102 INFO L290 TraceCheckUtils]: 10: Hoare triple {34852#true} assume 0 == ~M_E~0;~M_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,103 INFO L290 TraceCheckUtils]: 11: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,103 INFO L290 TraceCheckUtils]: 12: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,103 INFO L290 TraceCheckUtils]: 13: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,103 INFO L290 TraceCheckUtils]: 14: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,104 INFO L290 TraceCheckUtils]: 15: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,104 INFO L290 TraceCheckUtils]: 16: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,104 INFO L290 TraceCheckUtils]: 17: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,104 INFO L290 TraceCheckUtils]: 18: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,105 INFO L290 TraceCheckUtils]: 19: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,105 INFO L290 TraceCheckUtils]: 20: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,105 INFO L290 TraceCheckUtils]: 21: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,106 INFO L290 TraceCheckUtils]: 22: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,106 INFO L290 TraceCheckUtils]: 23: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,106 INFO L290 TraceCheckUtils]: 24: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,106 INFO L290 TraceCheckUtils]: 25: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,107 INFO L290 TraceCheckUtils]: 26: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,107 INFO L290 TraceCheckUtils]: 27: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,107 INFO L290 TraceCheckUtils]: 28: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,107 INFO L290 TraceCheckUtils]: 29: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,108 INFO L290 TraceCheckUtils]: 30: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,108 INFO L290 TraceCheckUtils]: 31: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,108 INFO L290 TraceCheckUtils]: 32: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,108 INFO L290 TraceCheckUtils]: 33: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,109 INFO L290 TraceCheckUtils]: 34: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,109 INFO L290 TraceCheckUtils]: 35: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,109 INFO L290 TraceCheckUtils]: 36: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,110 INFO L290 TraceCheckUtils]: 37: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,110 INFO L290 TraceCheckUtils]: 38: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,110 INFO L290 TraceCheckUtils]: 39: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,110 INFO L290 TraceCheckUtils]: 40: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,111 INFO L290 TraceCheckUtils]: 41: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,111 INFO L290 TraceCheckUtils]: 42: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,111 INFO L290 TraceCheckUtils]: 43: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,111 INFO L290 TraceCheckUtils]: 44: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,112 INFO L290 TraceCheckUtils]: 45: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,112 INFO L290 TraceCheckUtils]: 46: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,112 INFO L290 TraceCheckUtils]: 47: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,112 INFO L290 TraceCheckUtils]: 48: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,113 INFO L290 TraceCheckUtils]: 49: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,113 INFO L290 TraceCheckUtils]: 50: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,113 INFO L290 TraceCheckUtils]: 51: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,114 INFO L290 TraceCheckUtils]: 52: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,114 INFO L290 TraceCheckUtils]: 53: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,114 INFO L290 TraceCheckUtils]: 54: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,114 INFO L290 TraceCheckUtils]: 55: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,115 INFO L290 TraceCheckUtils]: 56: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,115 INFO L290 TraceCheckUtils]: 57: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,115 INFO L290 TraceCheckUtils]: 58: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,115 INFO L290 TraceCheckUtils]: 59: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,116 INFO L290 TraceCheckUtils]: 60: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,116 INFO L290 TraceCheckUtils]: 61: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,116 INFO L290 TraceCheckUtils]: 62: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,117 INFO L290 TraceCheckUtils]: 63: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,117 INFO L290 TraceCheckUtils]: 64: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,117 INFO L290 TraceCheckUtils]: 65: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,117 INFO L290 TraceCheckUtils]: 66: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,118 INFO L290 TraceCheckUtils]: 67: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,118 INFO L290 TraceCheckUtils]: 68: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,118 INFO L290 TraceCheckUtils]: 69: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,119 INFO L290 TraceCheckUtils]: 70: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,119 INFO L290 TraceCheckUtils]: 71: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,119 INFO L290 TraceCheckUtils]: 72: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,119 INFO L290 TraceCheckUtils]: 73: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,120 INFO L290 TraceCheckUtils]: 74: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,120 INFO L290 TraceCheckUtils]: 75: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,120 INFO L290 TraceCheckUtils]: 76: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,120 INFO L290 TraceCheckUtils]: 77: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,121 INFO L290 TraceCheckUtils]: 78: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,121 INFO L290 TraceCheckUtils]: 79: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,121 INFO L290 TraceCheckUtils]: 80: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,121 INFO L290 TraceCheckUtils]: 81: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,122 INFO L290 TraceCheckUtils]: 82: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,122 INFO L290 TraceCheckUtils]: 83: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,122 INFO L290 TraceCheckUtils]: 84: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,123 INFO L290 TraceCheckUtils]: 85: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,123 INFO L290 TraceCheckUtils]: 86: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,123 INFO L290 TraceCheckUtils]: 87: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,123 INFO L290 TraceCheckUtils]: 88: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,124 INFO L290 TraceCheckUtils]: 89: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,124 INFO L290 TraceCheckUtils]: 90: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,124 INFO L290 TraceCheckUtils]: 91: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,124 INFO L290 TraceCheckUtils]: 92: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,125 INFO L290 TraceCheckUtils]: 93: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,125 INFO L290 TraceCheckUtils]: 94: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,125 INFO L290 TraceCheckUtils]: 95: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,125 INFO L290 TraceCheckUtils]: 96: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,126 INFO L290 TraceCheckUtils]: 97: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,126 INFO L290 TraceCheckUtils]: 98: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,126 INFO L290 TraceCheckUtils]: 99: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,127 INFO L290 TraceCheckUtils]: 100: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,127 INFO L290 TraceCheckUtils]: 101: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,127 INFO L290 TraceCheckUtils]: 102: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,127 INFO L290 TraceCheckUtils]: 103: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,128 INFO L290 TraceCheckUtils]: 104: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,128 INFO L290 TraceCheckUtils]: 105: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,128 INFO L290 TraceCheckUtils]: 106: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,128 INFO L290 TraceCheckUtils]: 107: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,129 INFO L290 TraceCheckUtils]: 108: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,129 INFO L290 TraceCheckUtils]: 109: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,129 INFO L290 TraceCheckUtils]: 110: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,129 INFO L290 TraceCheckUtils]: 111: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,130 INFO L290 TraceCheckUtils]: 112: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,130 INFO L290 TraceCheckUtils]: 113: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,130 INFO L290 TraceCheckUtils]: 114: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,130 INFO L290 TraceCheckUtils]: 115: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,131 INFO L290 TraceCheckUtils]: 116: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,131 INFO L290 TraceCheckUtils]: 117: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,131 INFO L290 TraceCheckUtils]: 118: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,131 INFO L290 TraceCheckUtils]: 119: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,132 INFO L290 TraceCheckUtils]: 120: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,132 INFO L290 TraceCheckUtils]: 121: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,132 INFO L290 TraceCheckUtils]: 122: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,133 INFO L290 TraceCheckUtils]: 123: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,133 INFO L290 TraceCheckUtils]: 124: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t14_pc~0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,133 INFO L290 TraceCheckUtils]: 125: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,133 INFO L290 TraceCheckUtils]: 126: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,134 INFO L290 TraceCheckUtils]: 127: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,134 INFO L290 TraceCheckUtils]: 128: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,134 INFO L290 TraceCheckUtils]: 129: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34854#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:50,134 INFO L290 TraceCheckUtils]: 130: Hoare triple {34854#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {34853#false} is VALID [2022-02-21 04:24:50,135 INFO L290 TraceCheckUtils]: 131: Hoare triple {34853#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,135 INFO L290 TraceCheckUtils]: 132: Hoare triple {34853#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,135 INFO L290 TraceCheckUtils]: 133: Hoare triple {34853#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,135 INFO L290 TraceCheckUtils]: 134: Hoare triple {34853#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,135 INFO L290 TraceCheckUtils]: 135: Hoare triple {34853#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,135 INFO L290 TraceCheckUtils]: 136: Hoare triple {34853#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,135 INFO L290 TraceCheckUtils]: 137: Hoare triple {34853#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,135 INFO L290 TraceCheckUtils]: 138: Hoare triple {34853#false} assume !(1 == ~T8_E~0); {34853#false} is VALID [2022-02-21 04:24:50,135 INFO L290 TraceCheckUtils]: 139: Hoare triple {34853#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,136 INFO L290 TraceCheckUtils]: 140: Hoare triple {34853#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,136 INFO L290 TraceCheckUtils]: 141: Hoare triple {34853#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,136 INFO L290 TraceCheckUtils]: 142: Hoare triple {34853#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,136 INFO L290 TraceCheckUtils]: 143: Hoare triple {34853#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,136 INFO L290 TraceCheckUtils]: 144: Hoare triple {34853#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,136 INFO L290 TraceCheckUtils]: 145: Hoare triple {34853#false} assume 1 == ~E_1~0;~E_1~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,136 INFO L290 TraceCheckUtils]: 146: Hoare triple {34853#false} assume !(1 == ~E_2~0); {34853#false} is VALID [2022-02-21 04:24:50,136 INFO L290 TraceCheckUtils]: 147: Hoare triple {34853#false} assume 1 == ~E_3~0;~E_3~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,136 INFO L290 TraceCheckUtils]: 148: Hoare triple {34853#false} assume 1 == ~E_4~0;~E_4~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,137 INFO L290 TraceCheckUtils]: 149: Hoare triple {34853#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,137 INFO L290 TraceCheckUtils]: 150: Hoare triple {34853#false} assume 1 == ~E_6~0;~E_6~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,137 INFO L290 TraceCheckUtils]: 151: Hoare triple {34853#false} assume 1 == ~E_7~0;~E_7~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,137 INFO L290 TraceCheckUtils]: 152: Hoare triple {34853#false} assume 1 == ~E_8~0;~E_8~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,137 INFO L290 TraceCheckUtils]: 153: Hoare triple {34853#false} assume 1 == ~E_9~0;~E_9~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,137 INFO L290 TraceCheckUtils]: 154: Hoare triple {34853#false} assume !(1 == ~E_10~0); {34853#false} is VALID [2022-02-21 04:24:50,137 INFO L290 TraceCheckUtils]: 155: Hoare triple {34853#false} assume 1 == ~E_11~0;~E_11~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,137 INFO L290 TraceCheckUtils]: 156: Hoare triple {34853#false} assume 1 == ~E_12~0;~E_12~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,137 INFO L290 TraceCheckUtils]: 157: Hoare triple {34853#false} assume 1 == ~E_13~0;~E_13~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,138 INFO L290 TraceCheckUtils]: 158: Hoare triple {34853#false} assume 1 == ~E_14~0;~E_14~0 := 2; {34853#false} is VALID [2022-02-21 04:24:50,138 INFO L290 TraceCheckUtils]: 159: Hoare triple {34853#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {34853#false} is VALID [2022-02-21 04:24:50,138 INFO L290 TraceCheckUtils]: 160: Hoare triple {34853#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {34853#false} is VALID [2022-02-21 04:24:50,138 INFO L290 TraceCheckUtils]: 161: Hoare triple {34853#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {34853#false} is VALID [2022-02-21 04:24:50,138 INFO L290 TraceCheckUtils]: 162: Hoare triple {34853#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {34853#false} is VALID [2022-02-21 04:24:50,138 INFO L290 TraceCheckUtils]: 163: Hoare triple {34853#false} assume !(0 == start_simulation_~tmp~3#1); {34853#false} is VALID [2022-02-21 04:24:50,138 INFO L290 TraceCheckUtils]: 164: Hoare triple {34853#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {34853#false} is VALID [2022-02-21 04:24:50,138 INFO L290 TraceCheckUtils]: 165: Hoare triple {34853#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {34853#false} is VALID [2022-02-21 04:24:50,139 INFO L290 TraceCheckUtils]: 166: Hoare triple {34853#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {34853#false} is VALID [2022-02-21 04:24:50,139 INFO L290 TraceCheckUtils]: 167: Hoare triple {34853#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {34853#false} is VALID [2022-02-21 04:24:50,139 INFO L290 TraceCheckUtils]: 168: Hoare triple {34853#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {34853#false} is VALID [2022-02-21 04:24:50,139 INFO L290 TraceCheckUtils]: 169: Hoare triple {34853#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {34853#false} is VALID [2022-02-21 04:24:50,139 INFO L290 TraceCheckUtils]: 170: Hoare triple {34853#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {34853#false} is VALID [2022-02-21 04:24:50,139 INFO L290 TraceCheckUtils]: 171: Hoare triple {34853#false} assume !(0 != start_simulation_~tmp___0~1#1); {34853#false} is VALID [2022-02-21 04:24:50,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:50,140 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:50,140 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188500322] [2022-02-21 04:24:50,140 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1188500322] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:50,140 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:50,140 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:50,140 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373287154] [2022-02-21 04:24:50,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:50,141 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:50,141 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:50,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:50,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:50,142 INFO L87 Difference]: Start difference. First operand 2047 states and 3031 transitions. cyclomatic complexity: 985 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:51,766 INFO L93 Difference]: Finished difference Result 2047 states and 3030 transitions. [2022-02-21 04:24:51,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:51,767 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,892 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:51,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3030 transitions. [2022-02-21 04:24:52,047 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:52,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3030 transitions. [2022-02-21 04:24:52,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:24:52,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:24:52,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3030 transitions. [2022-02-21 04:24:52,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:52,203 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2022-02-21 04:24:52,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3030 transitions. [2022-02-21 04:24:52,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:24:52,226 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:52,229 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3030 transitions. Second operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,231 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3030 transitions. Second operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,233 INFO L87 Difference]: Start difference. First operand 2047 states and 3030 transitions. Second operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:52,367 INFO L93 Difference]: Finished difference Result 2047 states and 3030 transitions. [2022-02-21 04:24:52,367 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3030 transitions. [2022-02-21 04:24:52,369 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:52,370 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:52,373 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3030 transitions. [2022-02-21 04:24:52,376 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3030 transitions. [2022-02-21 04:24:52,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:52,483 INFO L93 Difference]: Finished difference Result 2047 states and 3030 transitions. [2022-02-21 04:24:52,483 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3030 transitions. [2022-02-21 04:24:52,485 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:52,485 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:52,485 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:52,485 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:52,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3030 transitions. [2022-02-21 04:24:52,571 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2022-02-21 04:24:52,571 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2022-02-21 04:24:52,571 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:52,572 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3030 transitions. [2022-02-21 04:24:52,575 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:52,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:52,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:52,576 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:52,576 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:52,577 INFO L791 eck$LassoCheckResult]: Stem: 37828#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 37829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 38431#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37548#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37549#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 37794#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37795#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37522#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37523#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38746#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 38098#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 38099#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 38616#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 38008#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38009#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37429#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37430#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37761#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37959#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 37006#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37007#L1342 assume !(0 == ~M_E~0); 37172#L1342-2 assume !(0 == ~T1_E~0); 37728#L1347-1 assume !(0 == ~T2_E~0); 38729#L1352-1 assume !(0 == ~T3_E~0); 38525#L1357-1 assume !(0 == ~T4_E~0); 37753#L1362-1 assume !(0 == ~T5_E~0); 37754#L1367-1 assume !(0 == ~T6_E~0); 37351#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37352#L1377-1 assume !(0 == ~T8_E~0); 37682#L1382-1 assume !(0 == ~T9_E~0); 37683#L1387-1 assume !(0 == ~T10_E~0); 38410#L1392-1 assume !(0 == ~T11_E~0); 37714#L1397-1 assume !(0 == ~T12_E~0); 37715#L1402-1 assume !(0 == ~T13_E~0); 37367#L1407-1 assume !(0 == ~T14_E~0); 37368#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 38646#L1417-1 assume !(0 == ~E_2~0); 38647#L1422-1 assume !(0 == ~E_3~0); 38888#L1427-1 assume !(0 == ~E_4~0); 37555#L1432-1 assume !(0 == ~E_5~0); 37556#L1437-1 assume !(0 == ~E_6~0); 38564#L1442-1 assume !(0 == ~E_7~0); 38565#L1447-1 assume !(0 == ~E_8~0); 38407#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 37142#L1457-1 assume !(0 == ~E_10~0); 37143#L1462-1 assume !(0 == ~E_11~0); 38599#L1467-1 assume !(0 == ~E_12~0); 38611#L1472-1 assume !(0 == ~E_13~0); 38612#L1477-1 assume !(0 == ~E_14~0); 38354#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37341#L646 assume 1 == ~m_pc~0; 37342#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38018#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38033#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37431#L1666 assume !(0 != activate_threads_~tmp~1#1); 37432#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38909#L665 assume !(1 == ~t1_pc~0); 37907#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37908#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37440#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37441#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 38231#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38232#L684 assume 1 == ~t2_pc~0; 38349#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38273#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38338#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38733#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 38734#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38922#L703 assume !(1 == ~t3_pc~0); 37577#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37578#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38224#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36976#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 36977#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37462#L722 assume 1 == ~t4_pc~0; 38200#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37643#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37988#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38548#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 38055#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37173#L741 assume 1 == ~t5_pc~0; 37174#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37484#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37638#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37639#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 38318#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37729#L760 assume !(1 == ~t6_pc~0); 37576#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37575#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37433#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37434#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38155#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38156#L779 assume 1 == ~t7_pc~0; 37218#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37064#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37065#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37473#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 37496#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37497#L798 assume !(1 == ~t8_pc~0); 38778#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 38701#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37220#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37221#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 38911#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37041#L817 assume 1 == ~t9_pc~0; 37042#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37836#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37837#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38359#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 37447#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37448#L836 assume !(1 == ~t10_pc~0); 37464#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37395#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37396#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37644#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 37645#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38711#L855 assume 1 == ~t11_pc~0; 38029#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38030#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38594#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38403#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 38238#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37337#L874 assume !(1 == ~t12_pc~0); 37338#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37505#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37506#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37646#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 37014#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37015#L893 assume 1 == ~t13_pc~0; 38845#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37370#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37681#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38772#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 38780#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 38781#L912 assume 1 == ~t14_pc~0; 38571#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 38572#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 37340#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37272#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 37273#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38048#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 38464#L1495-2 assume !(1 == ~T1_E~0); 38465#L1500-1 assume !(1 == ~T2_E~0); 38151#L1505-1 assume !(1 == ~T3_E~0); 38152#L1510-1 assume !(1 == ~T4_E~0); 38209#L1515-1 assume !(1 == ~T5_E~0); 38210#L1520-1 assume !(1 == ~T6_E~0); 38779#L1525-1 assume !(1 == ~T7_E~0); 38489#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37442#L1535-1 assume !(1 == ~T9_E~0); 37443#L1540-1 assume !(1 == ~T10_E~0); 36935#L1545-1 assume !(1 == ~T11_E~0); 36936#L1550-1 assume !(1 == ~T12_E~0); 37184#L1555-1 assume !(1 == ~T13_E~0); 37185#L1560-1 assume !(1 == ~T14_E~0); 37485#L1565-1 assume !(1 == ~E_1~0); 38898#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 38376#L1575-1 assume !(1 == ~E_3~0); 37755#L1580-1 assume !(1 == ~E_4~0); 37756#L1585-1 assume !(1 == ~E_5~0); 38226#L1590-1 assume !(1 == ~E_6~0); 37790#L1595-1 assume !(1 == ~E_7~0); 37791#L1600-1 assume !(1 == ~E_8~0); 38163#L1605-1 assume !(1 == ~E_9~0); 38164#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 38681#L1615-1 assume !(1 == ~E_11~0); 37620#L1620-1 assume !(1 == ~E_12~0); 37621#L1625-1 assume !(1 == ~E_13~0); 38408#L1630-1 assume !(1 == ~E_14~0); 37789#L1635-1 assume { :end_inline_reset_delta_events } true; 37730#L2017-2 [2022-02-21 04:24:52,577 INFO L793 eck$LassoCheckResult]: Loop: 37730#L2017-2 assume !false; 37010#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37011#L1316 assume !false; 38339#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38401#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 36948#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37090#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37091#L1115 assume !(0 != eval_~tmp~0#1); 38424#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37845#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37846#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38028#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38529#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38198#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38199#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38761#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38936#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38931#L1372-3 assume !(0 == ~T7_E~0); 36992#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36993#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37662#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37663#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38574#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38884#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38142#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 37298#L1412-3 assume !(0 == ~E_1~0); 37299#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38063#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38064#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38758#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38445#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38157#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38158#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37058#L1452-3 assume !(0 == ~E_9~0); 37059#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38697#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38698#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38502#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38503#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 37296#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37297#L646-42 assume 1 == ~m_pc~0; 37882#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38730#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38731#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38869#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38870#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38662#L665-42 assume !(1 == ~t1_pc~0); 38624#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 38625#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38811#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37465#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37466#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38935#L684-42 assume 1 == ~t2_pc~0; 38314#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38315#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38925#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38094#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38095#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38217#L703-42 assume !(1 == ~t3_pc~0); 38417#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 38416#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37734#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37735#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38509#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38129#L722-42 assume 1 == ~t4_pc~0; 38130#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38540#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37783#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37610#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37611#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38905#L741-42 assume !(1 == ~t5_pc~0); 38522#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 37992#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37993#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38938#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37900#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37901#L760-42 assume !(1 == ~t6_pc~0); 38035#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 38170#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38171#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38559#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 37852#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37853#L779-42 assume !(1 == ~t7_pc~0); 38629#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38630#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37537#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37538#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37393#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37394#L798-42 assume 1 == ~t8_pc~0; 37844#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37005#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38748#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38194#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37224#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37225#L817-42 assume 1 == ~t9_pc~0; 37998#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37508#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37509#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37635#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38440#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38441#L836-42 assume 1 == ~t10_pc~0; 38533#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37546#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37547#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38848#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38849#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38890#L855-42 assume 1 == ~t11_pc~0; 38903#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37097#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37098#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37847#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38610#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37711#L874-42 assume 1 == ~t12_pc~0; 37712#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37951#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37012#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37013#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37266#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37267#L893-42 assume 1 == ~t13_pc~0; 38469#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38251#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38266#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38168#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 37640#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 37641#L912-42 assume !(1 == ~t14_pc~0); 38450#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 36958#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 36959#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38539#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 37386#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37387#L1495-3 assume !(1 == ~M_E~0); 38002#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38430#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38523#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37616#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37579#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37580#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38237#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38460#L1530-3 assume !(1 == ~T8_E~0); 37425#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37426#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37463#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38720#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38829#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 37869#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 37870#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38485#L1570-3 assume !(1 == ~E_2~0); 38436#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38437#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38792#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38836#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38882#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38259#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38260#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38735#L1610-3 assume !(1 == ~E_10~0); 37622#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37623#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38227#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38228#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 38132#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 37563#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37168#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37906#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 38462#L2036 assume !(0 == start_simulation_~tmp~3#1); 38463#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38615#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37775#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 38793#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38175#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 38176#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38896#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38897#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 37730#L2017-2 [2022-02-21 04:24:52,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:52,578 INFO L85 PathProgramCache]: Analyzing trace with hash -1293428376, now seen corresponding path program 1 times [2022-02-21 04:24:52,578 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:52,578 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [192770821] [2022-02-21 04:24:52,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:52,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:52,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:52,601 INFO L290 TraceCheckUtils]: 0: Hoare triple {43046#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {43046#true} is VALID [2022-02-21 04:24:52,601 INFO L290 TraceCheckUtils]: 1: Hoare triple {43046#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {43048#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:52,601 INFO L290 TraceCheckUtils]: 2: Hoare triple {43048#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {43048#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:52,602 INFO L290 TraceCheckUtils]: 3: Hoare triple {43048#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {43048#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:52,602 INFO L290 TraceCheckUtils]: 4: Hoare triple {43048#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {43048#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:52,602 INFO L290 TraceCheckUtils]: 5: Hoare triple {43048#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {43048#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:52,603 INFO L290 TraceCheckUtils]: 6: Hoare triple {43048#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {43048#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:52,603 INFO L290 TraceCheckUtils]: 7: Hoare triple {43048#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {43048#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:52,603 INFO L290 TraceCheckUtils]: 8: Hoare triple {43048#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {43048#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:52,603 INFO L290 TraceCheckUtils]: 9: Hoare triple {43048#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,603 INFO L290 TraceCheckUtils]: 10: Hoare triple {43047#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,604 INFO L290 TraceCheckUtils]: 11: Hoare triple {43047#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,604 INFO L290 TraceCheckUtils]: 12: Hoare triple {43047#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,604 INFO L290 TraceCheckUtils]: 13: Hoare triple {43047#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {43047#false} is VALID [2022-02-21 04:24:52,604 INFO L290 TraceCheckUtils]: 14: Hoare triple {43047#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,604 INFO L290 TraceCheckUtils]: 15: Hoare triple {43047#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,604 INFO L290 TraceCheckUtils]: 16: Hoare triple {43047#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,604 INFO L290 TraceCheckUtils]: 17: Hoare triple {43047#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,604 INFO L290 TraceCheckUtils]: 18: Hoare triple {43047#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,604 INFO L290 TraceCheckUtils]: 19: Hoare triple {43047#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {43047#false} is VALID [2022-02-21 04:24:52,605 INFO L290 TraceCheckUtils]: 20: Hoare triple {43047#false} assume !(0 == ~M_E~0); {43047#false} is VALID [2022-02-21 04:24:52,605 INFO L290 TraceCheckUtils]: 21: Hoare triple {43047#false} assume !(0 == ~T1_E~0); {43047#false} is VALID [2022-02-21 04:24:52,605 INFO L290 TraceCheckUtils]: 22: Hoare triple {43047#false} assume !(0 == ~T2_E~0); {43047#false} is VALID [2022-02-21 04:24:52,605 INFO L290 TraceCheckUtils]: 23: Hoare triple {43047#false} assume !(0 == ~T3_E~0); {43047#false} is VALID [2022-02-21 04:24:52,605 INFO L290 TraceCheckUtils]: 24: Hoare triple {43047#false} assume !(0 == ~T4_E~0); {43047#false} is VALID [2022-02-21 04:24:52,605 INFO L290 TraceCheckUtils]: 25: Hoare triple {43047#false} assume !(0 == ~T5_E~0); {43047#false} is VALID [2022-02-21 04:24:52,605 INFO L290 TraceCheckUtils]: 26: Hoare triple {43047#false} assume !(0 == ~T6_E~0); {43047#false} is VALID [2022-02-21 04:24:52,605 INFO L290 TraceCheckUtils]: 27: Hoare triple {43047#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {43047#false} is VALID [2022-02-21 04:24:52,606 INFO L290 TraceCheckUtils]: 28: Hoare triple {43047#false} assume !(0 == ~T8_E~0); {43047#false} is VALID [2022-02-21 04:24:52,606 INFO L290 TraceCheckUtils]: 29: Hoare triple {43047#false} assume !(0 == ~T9_E~0); {43047#false} is VALID [2022-02-21 04:24:52,606 INFO L290 TraceCheckUtils]: 30: Hoare triple {43047#false} assume !(0 == ~T10_E~0); {43047#false} is VALID [2022-02-21 04:24:52,606 INFO L290 TraceCheckUtils]: 31: Hoare triple {43047#false} assume !(0 == ~T11_E~0); {43047#false} is VALID [2022-02-21 04:24:52,606 INFO L290 TraceCheckUtils]: 32: Hoare triple {43047#false} assume !(0 == ~T12_E~0); {43047#false} is VALID [2022-02-21 04:24:52,606 INFO L290 TraceCheckUtils]: 33: Hoare triple {43047#false} assume !(0 == ~T13_E~0); {43047#false} is VALID [2022-02-21 04:24:52,606 INFO L290 TraceCheckUtils]: 34: Hoare triple {43047#false} assume !(0 == ~T14_E~0); {43047#false} is VALID [2022-02-21 04:24:52,606 INFO L290 TraceCheckUtils]: 35: Hoare triple {43047#false} assume 0 == ~E_1~0;~E_1~0 := 1; {43047#false} is VALID [2022-02-21 04:24:52,606 INFO L290 TraceCheckUtils]: 36: Hoare triple {43047#false} assume !(0 == ~E_2~0); {43047#false} is VALID [2022-02-21 04:24:52,607 INFO L290 TraceCheckUtils]: 37: Hoare triple {43047#false} assume !(0 == ~E_3~0); {43047#false} is VALID [2022-02-21 04:24:52,607 INFO L290 TraceCheckUtils]: 38: Hoare triple {43047#false} assume !(0 == ~E_4~0); {43047#false} is VALID [2022-02-21 04:24:52,607 INFO L290 TraceCheckUtils]: 39: Hoare triple {43047#false} assume !(0 == ~E_5~0); {43047#false} is VALID [2022-02-21 04:24:52,607 INFO L290 TraceCheckUtils]: 40: Hoare triple {43047#false} assume !(0 == ~E_6~0); {43047#false} is VALID [2022-02-21 04:24:52,607 INFO L290 TraceCheckUtils]: 41: Hoare triple {43047#false} assume !(0 == ~E_7~0); {43047#false} is VALID [2022-02-21 04:24:52,607 INFO L290 TraceCheckUtils]: 42: Hoare triple {43047#false} assume !(0 == ~E_8~0); {43047#false} is VALID [2022-02-21 04:24:52,607 INFO L290 TraceCheckUtils]: 43: Hoare triple {43047#false} assume 0 == ~E_9~0;~E_9~0 := 1; {43047#false} is VALID [2022-02-21 04:24:52,607 INFO L290 TraceCheckUtils]: 44: Hoare triple {43047#false} assume !(0 == ~E_10~0); {43047#false} is VALID [2022-02-21 04:24:52,607 INFO L290 TraceCheckUtils]: 45: Hoare triple {43047#false} assume !(0 == ~E_11~0); {43047#false} is VALID [2022-02-21 04:24:52,608 INFO L290 TraceCheckUtils]: 46: Hoare triple {43047#false} assume !(0 == ~E_12~0); {43047#false} is VALID [2022-02-21 04:24:52,608 INFO L290 TraceCheckUtils]: 47: Hoare triple {43047#false} assume !(0 == ~E_13~0); {43047#false} is VALID [2022-02-21 04:24:52,608 INFO L290 TraceCheckUtils]: 48: Hoare triple {43047#false} assume !(0 == ~E_14~0); {43047#false} is VALID [2022-02-21 04:24:52,608 INFO L290 TraceCheckUtils]: 49: Hoare triple {43047#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {43047#false} is VALID [2022-02-21 04:24:52,608 INFO L290 TraceCheckUtils]: 50: Hoare triple {43047#false} assume 1 == ~m_pc~0; {43047#false} is VALID [2022-02-21 04:24:52,608 INFO L290 TraceCheckUtils]: 51: Hoare triple {43047#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {43047#false} is VALID [2022-02-21 04:24:52,608 INFO L290 TraceCheckUtils]: 52: Hoare triple {43047#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {43047#false} is VALID [2022-02-21 04:24:52,608 INFO L290 TraceCheckUtils]: 53: Hoare triple {43047#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {43047#false} is VALID [2022-02-21 04:24:52,608 INFO L290 TraceCheckUtils]: 54: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp~1#1); {43047#false} is VALID [2022-02-21 04:24:52,609 INFO L290 TraceCheckUtils]: 55: Hoare triple {43047#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {43047#false} is VALID [2022-02-21 04:24:52,609 INFO L290 TraceCheckUtils]: 56: Hoare triple {43047#false} assume !(1 == ~t1_pc~0); {43047#false} is VALID [2022-02-21 04:24:52,609 INFO L290 TraceCheckUtils]: 57: Hoare triple {43047#false} is_transmit1_triggered_~__retres1~1#1 := 0; {43047#false} is VALID [2022-02-21 04:24:52,609 INFO L290 TraceCheckUtils]: 58: Hoare triple {43047#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {43047#false} is VALID [2022-02-21 04:24:52,609 INFO L290 TraceCheckUtils]: 59: Hoare triple {43047#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {43047#false} is VALID [2022-02-21 04:24:52,609 INFO L290 TraceCheckUtils]: 60: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___0~0#1); {43047#false} is VALID [2022-02-21 04:24:52,609 INFO L290 TraceCheckUtils]: 61: Hoare triple {43047#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {43047#false} is VALID [2022-02-21 04:24:52,609 INFO L290 TraceCheckUtils]: 62: Hoare triple {43047#false} assume 1 == ~t2_pc~0; {43047#false} is VALID [2022-02-21 04:24:52,609 INFO L290 TraceCheckUtils]: 63: Hoare triple {43047#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {43047#false} is VALID [2022-02-21 04:24:52,610 INFO L290 TraceCheckUtils]: 64: Hoare triple {43047#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {43047#false} is VALID [2022-02-21 04:24:52,610 INFO L290 TraceCheckUtils]: 65: Hoare triple {43047#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {43047#false} is VALID [2022-02-21 04:24:52,610 INFO L290 TraceCheckUtils]: 66: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___1~0#1); {43047#false} is VALID [2022-02-21 04:24:52,610 INFO L290 TraceCheckUtils]: 67: Hoare triple {43047#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {43047#false} is VALID [2022-02-21 04:24:52,610 INFO L290 TraceCheckUtils]: 68: Hoare triple {43047#false} assume !(1 == ~t3_pc~0); {43047#false} is VALID [2022-02-21 04:24:52,610 INFO L290 TraceCheckUtils]: 69: Hoare triple {43047#false} is_transmit3_triggered_~__retres1~3#1 := 0; {43047#false} is VALID [2022-02-21 04:24:52,610 INFO L290 TraceCheckUtils]: 70: Hoare triple {43047#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {43047#false} is VALID [2022-02-21 04:24:52,610 INFO L290 TraceCheckUtils]: 71: Hoare triple {43047#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {43047#false} is VALID [2022-02-21 04:24:52,610 INFO L290 TraceCheckUtils]: 72: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___2~0#1); {43047#false} is VALID [2022-02-21 04:24:52,611 INFO L290 TraceCheckUtils]: 73: Hoare triple {43047#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {43047#false} is VALID [2022-02-21 04:24:52,611 INFO L290 TraceCheckUtils]: 74: Hoare triple {43047#false} assume 1 == ~t4_pc~0; {43047#false} is VALID [2022-02-21 04:24:52,611 INFO L290 TraceCheckUtils]: 75: Hoare triple {43047#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {43047#false} is VALID [2022-02-21 04:24:52,611 INFO L290 TraceCheckUtils]: 76: Hoare triple {43047#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {43047#false} is VALID [2022-02-21 04:24:52,611 INFO L290 TraceCheckUtils]: 77: Hoare triple {43047#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {43047#false} is VALID [2022-02-21 04:24:52,611 INFO L290 TraceCheckUtils]: 78: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___3~0#1); {43047#false} is VALID [2022-02-21 04:24:52,611 INFO L290 TraceCheckUtils]: 79: Hoare triple {43047#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {43047#false} is VALID [2022-02-21 04:24:52,611 INFO L290 TraceCheckUtils]: 80: Hoare triple {43047#false} assume 1 == ~t5_pc~0; {43047#false} is VALID [2022-02-21 04:24:52,611 INFO L290 TraceCheckUtils]: 81: Hoare triple {43047#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {43047#false} is VALID [2022-02-21 04:24:52,612 INFO L290 TraceCheckUtils]: 82: Hoare triple {43047#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {43047#false} is VALID [2022-02-21 04:24:52,612 INFO L290 TraceCheckUtils]: 83: Hoare triple {43047#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {43047#false} is VALID [2022-02-21 04:24:52,612 INFO L290 TraceCheckUtils]: 84: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___4~0#1); {43047#false} is VALID [2022-02-21 04:24:52,612 INFO L290 TraceCheckUtils]: 85: Hoare triple {43047#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {43047#false} is VALID [2022-02-21 04:24:52,612 INFO L290 TraceCheckUtils]: 86: Hoare triple {43047#false} assume !(1 == ~t6_pc~0); {43047#false} is VALID [2022-02-21 04:24:52,612 INFO L290 TraceCheckUtils]: 87: Hoare triple {43047#false} is_transmit6_triggered_~__retres1~6#1 := 0; {43047#false} is VALID [2022-02-21 04:24:52,612 INFO L290 TraceCheckUtils]: 88: Hoare triple {43047#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {43047#false} is VALID [2022-02-21 04:24:52,612 INFO L290 TraceCheckUtils]: 89: Hoare triple {43047#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {43047#false} is VALID [2022-02-21 04:24:52,612 INFO L290 TraceCheckUtils]: 90: Hoare triple {43047#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {43047#false} is VALID [2022-02-21 04:24:52,613 INFO L290 TraceCheckUtils]: 91: Hoare triple {43047#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {43047#false} is VALID [2022-02-21 04:24:52,613 INFO L290 TraceCheckUtils]: 92: Hoare triple {43047#false} assume 1 == ~t7_pc~0; {43047#false} is VALID [2022-02-21 04:24:52,613 INFO L290 TraceCheckUtils]: 93: Hoare triple {43047#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {43047#false} is VALID [2022-02-21 04:24:52,613 INFO L290 TraceCheckUtils]: 94: Hoare triple {43047#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {43047#false} is VALID [2022-02-21 04:24:52,613 INFO L290 TraceCheckUtils]: 95: Hoare triple {43047#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {43047#false} is VALID [2022-02-21 04:24:52,613 INFO L290 TraceCheckUtils]: 96: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___6~0#1); {43047#false} is VALID [2022-02-21 04:24:52,613 INFO L290 TraceCheckUtils]: 97: Hoare triple {43047#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {43047#false} is VALID [2022-02-21 04:24:52,613 INFO L290 TraceCheckUtils]: 98: Hoare triple {43047#false} assume !(1 == ~t8_pc~0); {43047#false} is VALID [2022-02-21 04:24:52,613 INFO L290 TraceCheckUtils]: 99: Hoare triple {43047#false} is_transmit8_triggered_~__retres1~8#1 := 0; {43047#false} is VALID [2022-02-21 04:24:52,614 INFO L290 TraceCheckUtils]: 100: Hoare triple {43047#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {43047#false} is VALID [2022-02-21 04:24:52,614 INFO L290 TraceCheckUtils]: 101: Hoare triple {43047#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {43047#false} is VALID [2022-02-21 04:24:52,614 INFO L290 TraceCheckUtils]: 102: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___7~0#1); {43047#false} is VALID [2022-02-21 04:24:52,614 INFO L290 TraceCheckUtils]: 103: Hoare triple {43047#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {43047#false} is VALID [2022-02-21 04:24:52,614 INFO L290 TraceCheckUtils]: 104: Hoare triple {43047#false} assume 1 == ~t9_pc~0; {43047#false} is VALID [2022-02-21 04:24:52,614 INFO L290 TraceCheckUtils]: 105: Hoare triple {43047#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {43047#false} is VALID [2022-02-21 04:24:52,614 INFO L290 TraceCheckUtils]: 106: Hoare triple {43047#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {43047#false} is VALID [2022-02-21 04:24:52,614 INFO L290 TraceCheckUtils]: 107: Hoare triple {43047#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {43047#false} is VALID [2022-02-21 04:24:52,614 INFO L290 TraceCheckUtils]: 108: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___8~0#1); {43047#false} is VALID [2022-02-21 04:24:52,615 INFO L290 TraceCheckUtils]: 109: Hoare triple {43047#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {43047#false} is VALID [2022-02-21 04:24:52,615 INFO L290 TraceCheckUtils]: 110: Hoare triple {43047#false} assume !(1 == ~t10_pc~0); {43047#false} is VALID [2022-02-21 04:24:52,615 INFO L290 TraceCheckUtils]: 111: Hoare triple {43047#false} is_transmit10_triggered_~__retres1~10#1 := 0; {43047#false} is VALID [2022-02-21 04:24:52,615 INFO L290 TraceCheckUtils]: 112: Hoare triple {43047#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {43047#false} is VALID [2022-02-21 04:24:52,615 INFO L290 TraceCheckUtils]: 113: Hoare triple {43047#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {43047#false} is VALID [2022-02-21 04:24:52,615 INFO L290 TraceCheckUtils]: 114: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___9~0#1); {43047#false} is VALID [2022-02-21 04:24:52,615 INFO L290 TraceCheckUtils]: 115: Hoare triple {43047#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {43047#false} is VALID [2022-02-21 04:24:52,615 INFO L290 TraceCheckUtils]: 116: Hoare triple {43047#false} assume 1 == ~t11_pc~0; {43047#false} is VALID [2022-02-21 04:24:52,615 INFO L290 TraceCheckUtils]: 117: Hoare triple {43047#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {43047#false} is VALID [2022-02-21 04:24:52,616 INFO L290 TraceCheckUtils]: 118: Hoare triple {43047#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {43047#false} is VALID [2022-02-21 04:24:52,616 INFO L290 TraceCheckUtils]: 119: Hoare triple {43047#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {43047#false} is VALID [2022-02-21 04:24:52,616 INFO L290 TraceCheckUtils]: 120: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___10~0#1); {43047#false} is VALID [2022-02-21 04:24:52,616 INFO L290 TraceCheckUtils]: 121: Hoare triple {43047#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {43047#false} is VALID [2022-02-21 04:24:52,616 INFO L290 TraceCheckUtils]: 122: Hoare triple {43047#false} assume !(1 == ~t12_pc~0); {43047#false} is VALID [2022-02-21 04:24:52,616 INFO L290 TraceCheckUtils]: 123: Hoare triple {43047#false} is_transmit12_triggered_~__retres1~12#1 := 0; {43047#false} is VALID [2022-02-21 04:24:52,616 INFO L290 TraceCheckUtils]: 124: Hoare triple {43047#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {43047#false} is VALID [2022-02-21 04:24:52,616 INFO L290 TraceCheckUtils]: 125: Hoare triple {43047#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {43047#false} is VALID [2022-02-21 04:24:52,616 INFO L290 TraceCheckUtils]: 126: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___11~0#1); {43047#false} is VALID [2022-02-21 04:24:52,617 INFO L290 TraceCheckUtils]: 127: Hoare triple {43047#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {43047#false} is VALID [2022-02-21 04:24:52,617 INFO L290 TraceCheckUtils]: 128: Hoare triple {43047#false} assume 1 == ~t13_pc~0; {43047#false} is VALID [2022-02-21 04:24:52,617 INFO L290 TraceCheckUtils]: 129: Hoare triple {43047#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {43047#false} is VALID [2022-02-21 04:24:52,617 INFO L290 TraceCheckUtils]: 130: Hoare triple {43047#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {43047#false} is VALID [2022-02-21 04:24:52,617 INFO L290 TraceCheckUtils]: 131: Hoare triple {43047#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {43047#false} is VALID [2022-02-21 04:24:52,617 INFO L290 TraceCheckUtils]: 132: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___12~0#1); {43047#false} is VALID [2022-02-21 04:24:52,617 INFO L290 TraceCheckUtils]: 133: Hoare triple {43047#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {43047#false} is VALID [2022-02-21 04:24:52,617 INFO L290 TraceCheckUtils]: 134: Hoare triple {43047#false} assume 1 == ~t14_pc~0; {43047#false} is VALID [2022-02-21 04:24:52,618 INFO L290 TraceCheckUtils]: 135: Hoare triple {43047#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {43047#false} is VALID [2022-02-21 04:24:52,618 INFO L290 TraceCheckUtils]: 136: Hoare triple {43047#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {43047#false} is VALID [2022-02-21 04:24:52,618 INFO L290 TraceCheckUtils]: 137: Hoare triple {43047#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {43047#false} is VALID [2022-02-21 04:24:52,618 INFO L290 TraceCheckUtils]: 138: Hoare triple {43047#false} assume !(0 != activate_threads_~tmp___13~0#1); {43047#false} is VALID [2022-02-21 04:24:52,618 INFO L290 TraceCheckUtils]: 139: Hoare triple {43047#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {43047#false} is VALID [2022-02-21 04:24:52,618 INFO L290 TraceCheckUtils]: 140: Hoare triple {43047#false} assume 1 == ~M_E~0;~M_E~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,618 INFO L290 TraceCheckUtils]: 141: Hoare triple {43047#false} assume !(1 == ~T1_E~0); {43047#false} is VALID [2022-02-21 04:24:52,618 INFO L290 TraceCheckUtils]: 142: Hoare triple {43047#false} assume !(1 == ~T2_E~0); {43047#false} is VALID [2022-02-21 04:24:52,618 INFO L290 TraceCheckUtils]: 143: Hoare triple {43047#false} assume !(1 == ~T3_E~0); {43047#false} is VALID [2022-02-21 04:24:52,619 INFO L290 TraceCheckUtils]: 144: Hoare triple {43047#false} assume !(1 == ~T4_E~0); {43047#false} is VALID [2022-02-21 04:24:52,619 INFO L290 TraceCheckUtils]: 145: Hoare triple {43047#false} assume !(1 == ~T5_E~0); {43047#false} is VALID [2022-02-21 04:24:52,619 INFO L290 TraceCheckUtils]: 146: Hoare triple {43047#false} assume !(1 == ~T6_E~0); {43047#false} is VALID [2022-02-21 04:24:52,619 INFO L290 TraceCheckUtils]: 147: Hoare triple {43047#false} assume !(1 == ~T7_E~0); {43047#false} is VALID [2022-02-21 04:24:52,619 INFO L290 TraceCheckUtils]: 148: Hoare triple {43047#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,619 INFO L290 TraceCheckUtils]: 149: Hoare triple {43047#false} assume !(1 == ~T9_E~0); {43047#false} is VALID [2022-02-21 04:24:52,619 INFO L290 TraceCheckUtils]: 150: Hoare triple {43047#false} assume !(1 == ~T10_E~0); {43047#false} is VALID [2022-02-21 04:24:52,619 INFO L290 TraceCheckUtils]: 151: Hoare triple {43047#false} assume !(1 == ~T11_E~0); {43047#false} is VALID [2022-02-21 04:24:52,619 INFO L290 TraceCheckUtils]: 152: Hoare triple {43047#false} assume !(1 == ~T12_E~0); {43047#false} is VALID [2022-02-21 04:24:52,620 INFO L290 TraceCheckUtils]: 153: Hoare triple {43047#false} assume !(1 == ~T13_E~0); {43047#false} is VALID [2022-02-21 04:24:52,620 INFO L290 TraceCheckUtils]: 154: Hoare triple {43047#false} assume !(1 == ~T14_E~0); {43047#false} is VALID [2022-02-21 04:24:52,620 INFO L290 TraceCheckUtils]: 155: Hoare triple {43047#false} assume !(1 == ~E_1~0); {43047#false} is VALID [2022-02-21 04:24:52,620 INFO L290 TraceCheckUtils]: 156: Hoare triple {43047#false} assume 1 == ~E_2~0;~E_2~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,620 INFO L290 TraceCheckUtils]: 157: Hoare triple {43047#false} assume !(1 == ~E_3~0); {43047#false} is VALID [2022-02-21 04:24:52,620 INFO L290 TraceCheckUtils]: 158: Hoare triple {43047#false} assume !(1 == ~E_4~0); {43047#false} is VALID [2022-02-21 04:24:52,620 INFO L290 TraceCheckUtils]: 159: Hoare triple {43047#false} assume !(1 == ~E_5~0); {43047#false} is VALID [2022-02-21 04:24:52,620 INFO L290 TraceCheckUtils]: 160: Hoare triple {43047#false} assume !(1 == ~E_6~0); {43047#false} is VALID [2022-02-21 04:24:52,620 INFO L290 TraceCheckUtils]: 161: Hoare triple {43047#false} assume !(1 == ~E_7~0); {43047#false} is VALID [2022-02-21 04:24:52,621 INFO L290 TraceCheckUtils]: 162: Hoare triple {43047#false} assume !(1 == ~E_8~0); {43047#false} is VALID [2022-02-21 04:24:52,621 INFO L290 TraceCheckUtils]: 163: Hoare triple {43047#false} assume !(1 == ~E_9~0); {43047#false} is VALID [2022-02-21 04:24:52,621 INFO L290 TraceCheckUtils]: 164: Hoare triple {43047#false} assume 1 == ~E_10~0;~E_10~0 := 2; {43047#false} is VALID [2022-02-21 04:24:52,621 INFO L290 TraceCheckUtils]: 165: Hoare triple {43047#false} assume !(1 == ~E_11~0); {43047#false} is VALID [2022-02-21 04:24:52,621 INFO L290 TraceCheckUtils]: 166: Hoare triple {43047#false} assume !(1 == ~E_12~0); {43047#false} is VALID [2022-02-21 04:24:52,621 INFO L290 TraceCheckUtils]: 167: Hoare triple {43047#false} assume !(1 == ~E_13~0); {43047#false} is VALID [2022-02-21 04:24:52,621 INFO L290 TraceCheckUtils]: 168: Hoare triple {43047#false} assume !(1 == ~E_14~0); {43047#false} is VALID [2022-02-21 04:24:52,621 INFO L290 TraceCheckUtils]: 169: Hoare triple {43047#false} assume { :end_inline_reset_delta_events } true; {43047#false} is VALID [2022-02-21 04:24:52,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:52,622 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:52,622 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [192770821] [2022-02-21 04:24:52,622 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [192770821] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:52,622 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:52,622 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:52,622 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [42811815] [2022-02-21 04:24:52,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:52,623 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:52,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:52,623 INFO L85 PathProgramCache]: Analyzing trace with hash 721372171, now seen corresponding path program 1 times [2022-02-21 04:24:52,623 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:52,624 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477781683] [2022-02-21 04:24:52,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:52,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:52,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:52,649 INFO L290 TraceCheckUtils]: 0: Hoare triple {43049#true} assume !false; {43049#true} is VALID [2022-02-21 04:24:52,649 INFO L290 TraceCheckUtils]: 1: Hoare triple {43049#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {43049#true} is VALID [2022-02-21 04:24:52,649 INFO L290 TraceCheckUtils]: 2: Hoare triple {43049#true} assume !false; {43049#true} is VALID [2022-02-21 04:24:52,649 INFO L290 TraceCheckUtils]: 3: Hoare triple {43049#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {43049#true} is VALID [2022-02-21 04:24:52,649 INFO L290 TraceCheckUtils]: 4: Hoare triple {43049#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {43049#true} is VALID [2022-02-21 04:24:52,649 INFO L290 TraceCheckUtils]: 5: Hoare triple {43049#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {43049#true} is VALID [2022-02-21 04:24:52,650 INFO L290 TraceCheckUtils]: 6: Hoare triple {43049#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {43049#true} is VALID [2022-02-21 04:24:52,650 INFO L290 TraceCheckUtils]: 7: Hoare triple {43049#true} assume !(0 != eval_~tmp~0#1); {43049#true} is VALID [2022-02-21 04:24:52,650 INFO L290 TraceCheckUtils]: 8: Hoare triple {43049#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {43049#true} is VALID [2022-02-21 04:24:52,650 INFO L290 TraceCheckUtils]: 9: Hoare triple {43049#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {43049#true} is VALID [2022-02-21 04:24:52,650 INFO L290 TraceCheckUtils]: 10: Hoare triple {43049#true} assume 0 == ~M_E~0;~M_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,650 INFO L290 TraceCheckUtils]: 11: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,651 INFO L290 TraceCheckUtils]: 12: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,651 INFO L290 TraceCheckUtils]: 13: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,651 INFO L290 TraceCheckUtils]: 14: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,652 INFO L290 TraceCheckUtils]: 15: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,652 INFO L290 TraceCheckUtils]: 16: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,652 INFO L290 TraceCheckUtils]: 17: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,652 INFO L290 TraceCheckUtils]: 18: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,653 INFO L290 TraceCheckUtils]: 19: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,653 INFO L290 TraceCheckUtils]: 20: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,653 INFO L290 TraceCheckUtils]: 21: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,653 INFO L290 TraceCheckUtils]: 22: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,654 INFO L290 TraceCheckUtils]: 23: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,654 INFO L290 TraceCheckUtils]: 24: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,654 INFO L290 TraceCheckUtils]: 25: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,655 INFO L290 TraceCheckUtils]: 26: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,655 INFO L290 TraceCheckUtils]: 27: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,655 INFO L290 TraceCheckUtils]: 28: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,655 INFO L290 TraceCheckUtils]: 29: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,656 INFO L290 TraceCheckUtils]: 30: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,656 INFO L290 TraceCheckUtils]: 31: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,656 INFO L290 TraceCheckUtils]: 32: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,656 INFO L290 TraceCheckUtils]: 33: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,657 INFO L290 TraceCheckUtils]: 34: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,657 INFO L290 TraceCheckUtils]: 35: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,657 INFO L290 TraceCheckUtils]: 36: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,657 INFO L290 TraceCheckUtils]: 37: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,658 INFO L290 TraceCheckUtils]: 38: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,658 INFO L290 TraceCheckUtils]: 39: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,658 INFO L290 TraceCheckUtils]: 40: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,659 INFO L290 TraceCheckUtils]: 41: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,659 INFO L290 TraceCheckUtils]: 42: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,659 INFO L290 TraceCheckUtils]: 43: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,659 INFO L290 TraceCheckUtils]: 44: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,660 INFO L290 TraceCheckUtils]: 45: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,660 INFO L290 TraceCheckUtils]: 46: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,660 INFO L290 TraceCheckUtils]: 47: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,660 INFO L290 TraceCheckUtils]: 48: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,661 INFO L290 TraceCheckUtils]: 49: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,661 INFO L290 TraceCheckUtils]: 50: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,661 INFO L290 TraceCheckUtils]: 51: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,661 INFO L290 TraceCheckUtils]: 52: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,662 INFO L290 TraceCheckUtils]: 53: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,662 INFO L290 TraceCheckUtils]: 54: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,662 INFO L290 TraceCheckUtils]: 55: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,663 INFO L290 TraceCheckUtils]: 56: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,663 INFO L290 TraceCheckUtils]: 57: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,663 INFO L290 TraceCheckUtils]: 58: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,663 INFO L290 TraceCheckUtils]: 59: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,664 INFO L290 TraceCheckUtils]: 60: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,664 INFO L290 TraceCheckUtils]: 61: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,664 INFO L290 TraceCheckUtils]: 62: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,664 INFO L290 TraceCheckUtils]: 63: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,665 INFO L290 TraceCheckUtils]: 64: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,665 INFO L290 TraceCheckUtils]: 65: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,665 INFO L290 TraceCheckUtils]: 66: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,665 INFO L290 TraceCheckUtils]: 67: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,666 INFO L290 TraceCheckUtils]: 68: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,666 INFO L290 TraceCheckUtils]: 69: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,666 INFO L290 TraceCheckUtils]: 70: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,667 INFO L290 TraceCheckUtils]: 71: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,667 INFO L290 TraceCheckUtils]: 72: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,667 INFO L290 TraceCheckUtils]: 73: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,667 INFO L290 TraceCheckUtils]: 74: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,668 INFO L290 TraceCheckUtils]: 75: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,668 INFO L290 TraceCheckUtils]: 76: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,668 INFO L290 TraceCheckUtils]: 77: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,668 INFO L290 TraceCheckUtils]: 78: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,669 INFO L290 TraceCheckUtils]: 79: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,669 INFO L290 TraceCheckUtils]: 80: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,669 INFO L290 TraceCheckUtils]: 81: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,670 INFO L290 TraceCheckUtils]: 82: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,670 INFO L290 TraceCheckUtils]: 83: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,670 INFO L290 TraceCheckUtils]: 84: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,670 INFO L290 TraceCheckUtils]: 85: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,671 INFO L290 TraceCheckUtils]: 86: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,671 INFO L290 TraceCheckUtils]: 87: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,671 INFO L290 TraceCheckUtils]: 88: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,671 INFO L290 TraceCheckUtils]: 89: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,672 INFO L290 TraceCheckUtils]: 90: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,672 INFO L290 TraceCheckUtils]: 91: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,672 INFO L290 TraceCheckUtils]: 92: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,672 INFO L290 TraceCheckUtils]: 93: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,673 INFO L290 TraceCheckUtils]: 94: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,673 INFO L290 TraceCheckUtils]: 95: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,673 INFO L290 TraceCheckUtils]: 96: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,673 INFO L290 TraceCheckUtils]: 97: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,674 INFO L290 TraceCheckUtils]: 98: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,674 INFO L290 TraceCheckUtils]: 99: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,674 INFO L290 TraceCheckUtils]: 100: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,675 INFO L290 TraceCheckUtils]: 101: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,675 INFO L290 TraceCheckUtils]: 102: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,675 INFO L290 TraceCheckUtils]: 103: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,675 INFO L290 TraceCheckUtils]: 104: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,676 INFO L290 TraceCheckUtils]: 105: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,676 INFO L290 TraceCheckUtils]: 106: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,676 INFO L290 TraceCheckUtils]: 107: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,676 INFO L290 TraceCheckUtils]: 108: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,677 INFO L290 TraceCheckUtils]: 109: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,677 INFO L290 TraceCheckUtils]: 110: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,677 INFO L290 TraceCheckUtils]: 111: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,677 INFO L290 TraceCheckUtils]: 112: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,678 INFO L290 TraceCheckUtils]: 113: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,678 INFO L290 TraceCheckUtils]: 114: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,678 INFO L290 TraceCheckUtils]: 115: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,679 INFO L290 TraceCheckUtils]: 116: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,679 INFO L290 TraceCheckUtils]: 117: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,679 INFO L290 TraceCheckUtils]: 118: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,679 INFO L290 TraceCheckUtils]: 119: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,680 INFO L290 TraceCheckUtils]: 120: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,680 INFO L290 TraceCheckUtils]: 121: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,680 INFO L290 TraceCheckUtils]: 122: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,680 INFO L290 TraceCheckUtils]: 123: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,681 INFO L290 TraceCheckUtils]: 124: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,681 INFO L290 TraceCheckUtils]: 125: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,681 INFO L290 TraceCheckUtils]: 126: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,681 INFO L290 TraceCheckUtils]: 127: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,682 INFO L290 TraceCheckUtils]: 128: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,682 INFO L290 TraceCheckUtils]: 129: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {43051#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:52,682 INFO L290 TraceCheckUtils]: 130: Hoare triple {43051#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {43050#false} is VALID [2022-02-21 04:24:52,682 INFO L290 TraceCheckUtils]: 131: Hoare triple {43050#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,682 INFO L290 TraceCheckUtils]: 132: Hoare triple {43050#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,683 INFO L290 TraceCheckUtils]: 133: Hoare triple {43050#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,683 INFO L290 TraceCheckUtils]: 134: Hoare triple {43050#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,683 INFO L290 TraceCheckUtils]: 135: Hoare triple {43050#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,683 INFO L290 TraceCheckUtils]: 136: Hoare triple {43050#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,683 INFO L290 TraceCheckUtils]: 137: Hoare triple {43050#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,683 INFO L290 TraceCheckUtils]: 138: Hoare triple {43050#false} assume !(1 == ~T8_E~0); {43050#false} is VALID [2022-02-21 04:24:52,683 INFO L290 TraceCheckUtils]: 139: Hoare triple {43050#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,683 INFO L290 TraceCheckUtils]: 140: Hoare triple {43050#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,684 INFO L290 TraceCheckUtils]: 141: Hoare triple {43050#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,684 INFO L290 TraceCheckUtils]: 142: Hoare triple {43050#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,684 INFO L290 TraceCheckUtils]: 143: Hoare triple {43050#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,684 INFO L290 TraceCheckUtils]: 144: Hoare triple {43050#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,684 INFO L290 TraceCheckUtils]: 145: Hoare triple {43050#false} assume 1 == ~E_1~0;~E_1~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,684 INFO L290 TraceCheckUtils]: 146: Hoare triple {43050#false} assume !(1 == ~E_2~0); {43050#false} is VALID [2022-02-21 04:24:52,684 INFO L290 TraceCheckUtils]: 147: Hoare triple {43050#false} assume 1 == ~E_3~0;~E_3~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,684 INFO L290 TraceCheckUtils]: 148: Hoare triple {43050#false} assume 1 == ~E_4~0;~E_4~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,684 INFO L290 TraceCheckUtils]: 149: Hoare triple {43050#false} assume 1 == ~E_5~0;~E_5~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,685 INFO L290 TraceCheckUtils]: 150: Hoare triple {43050#false} assume 1 == ~E_6~0;~E_6~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,685 INFO L290 TraceCheckUtils]: 151: Hoare triple {43050#false} assume 1 == ~E_7~0;~E_7~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,685 INFO L290 TraceCheckUtils]: 152: Hoare triple {43050#false} assume 1 == ~E_8~0;~E_8~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,685 INFO L290 TraceCheckUtils]: 153: Hoare triple {43050#false} assume 1 == ~E_9~0;~E_9~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,685 INFO L290 TraceCheckUtils]: 154: Hoare triple {43050#false} assume !(1 == ~E_10~0); {43050#false} is VALID [2022-02-21 04:24:52,685 INFO L290 TraceCheckUtils]: 155: Hoare triple {43050#false} assume 1 == ~E_11~0;~E_11~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,685 INFO L290 TraceCheckUtils]: 156: Hoare triple {43050#false} assume 1 == ~E_12~0;~E_12~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,685 INFO L290 TraceCheckUtils]: 157: Hoare triple {43050#false} assume 1 == ~E_13~0;~E_13~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,685 INFO L290 TraceCheckUtils]: 158: Hoare triple {43050#false} assume 1 == ~E_14~0;~E_14~0 := 2; {43050#false} is VALID [2022-02-21 04:24:52,686 INFO L290 TraceCheckUtils]: 159: Hoare triple {43050#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {43050#false} is VALID [2022-02-21 04:24:52,686 INFO L290 TraceCheckUtils]: 160: Hoare triple {43050#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {43050#false} is VALID [2022-02-21 04:24:52,686 INFO L290 TraceCheckUtils]: 161: Hoare triple {43050#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {43050#false} is VALID [2022-02-21 04:24:52,686 INFO L290 TraceCheckUtils]: 162: Hoare triple {43050#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {43050#false} is VALID [2022-02-21 04:24:52,686 INFO L290 TraceCheckUtils]: 163: Hoare triple {43050#false} assume !(0 == start_simulation_~tmp~3#1); {43050#false} is VALID [2022-02-21 04:24:52,686 INFO L290 TraceCheckUtils]: 164: Hoare triple {43050#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {43050#false} is VALID [2022-02-21 04:24:52,686 INFO L290 TraceCheckUtils]: 165: Hoare triple {43050#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {43050#false} is VALID [2022-02-21 04:24:52,686 INFO L290 TraceCheckUtils]: 166: Hoare triple {43050#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {43050#false} is VALID [2022-02-21 04:24:52,686 INFO L290 TraceCheckUtils]: 167: Hoare triple {43050#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {43050#false} is VALID [2022-02-21 04:24:52,687 INFO L290 TraceCheckUtils]: 168: Hoare triple {43050#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {43050#false} is VALID [2022-02-21 04:24:52,687 INFO L290 TraceCheckUtils]: 169: Hoare triple {43050#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {43050#false} is VALID [2022-02-21 04:24:52,687 INFO L290 TraceCheckUtils]: 170: Hoare triple {43050#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {43050#false} is VALID [2022-02-21 04:24:52,687 INFO L290 TraceCheckUtils]: 171: Hoare triple {43050#false} assume !(0 != start_simulation_~tmp___0~1#1); {43050#false} is VALID [2022-02-21 04:24:52,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:52,688 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:52,688 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477781683] [2022-02-21 04:24:52,688 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477781683] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:52,688 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:52,688 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:52,688 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113140833] [2022-02-21 04:24:52,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:52,689 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:52,689 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:52,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:52,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:52,689 INFO L87 Difference]: Start difference. First operand 2047 states and 3030 transitions. cyclomatic complexity: 984 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:54,104 INFO L93 Difference]: Finished difference Result 2047 states and 3029 transitions. [2022-02-21 04:24:54,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:54,104 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,203 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:54,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3029 transitions. [2022-02-21 04:24:54,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:54,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3029 transitions. [2022-02-21 04:24:54,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:24:54,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:24:54,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3029 transitions. [2022-02-21 04:24:54,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:54,391 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2022-02-21 04:24:54,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3029 transitions. [2022-02-21 04:24:54,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:24:54,407 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:54,409 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3029 transitions. Second operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,410 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3029 transitions. Second operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,412 INFO L87 Difference]: Start difference. First operand 2047 states and 3029 transitions. Second operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:54,496 INFO L93 Difference]: Finished difference Result 2047 states and 3029 transitions. [2022-02-21 04:24:54,496 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3029 transitions. [2022-02-21 04:24:54,498 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:54,498 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:54,500 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3029 transitions. [2022-02-21 04:24:54,502 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3029 transitions. [2022-02-21 04:24:54,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:54,586 INFO L93 Difference]: Finished difference Result 2047 states and 3029 transitions. [2022-02-21 04:24:54,586 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3029 transitions. [2022-02-21 04:24:54,588 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:54,588 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:54,588 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:54,588 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:54,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3029 transitions. [2022-02-21 04:24:54,674 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2022-02-21 04:24:54,674 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2022-02-21 04:24:54,674 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:54,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3029 transitions. [2022-02-21 04:24:54,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:54,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:54,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:54,679 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:54,679 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:54,681 INFO L791 eck$LassoCheckResult]: Stem: 46025#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 46026#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 46628#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45745#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45746#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 45991#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45992#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45719#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45720#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46943#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46295#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 46296#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 46813#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 46205#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46206#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 45626#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 45627#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45958#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46156#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 45203#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45204#L1342 assume !(0 == ~M_E~0); 45369#L1342-2 assume !(0 == ~T1_E~0); 45925#L1347-1 assume !(0 == ~T2_E~0); 46926#L1352-1 assume !(0 == ~T3_E~0); 46722#L1357-1 assume !(0 == ~T4_E~0); 45950#L1362-1 assume !(0 == ~T5_E~0); 45951#L1367-1 assume !(0 == ~T6_E~0); 45548#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45549#L1377-1 assume !(0 == ~T8_E~0); 45879#L1382-1 assume !(0 == ~T9_E~0); 45880#L1387-1 assume !(0 == ~T10_E~0); 46607#L1392-1 assume !(0 == ~T11_E~0); 45911#L1397-1 assume !(0 == ~T12_E~0); 45912#L1402-1 assume !(0 == ~T13_E~0); 45564#L1407-1 assume !(0 == ~T14_E~0); 45565#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 46843#L1417-1 assume !(0 == ~E_2~0); 46844#L1422-1 assume !(0 == ~E_3~0); 47085#L1427-1 assume !(0 == ~E_4~0); 45752#L1432-1 assume !(0 == ~E_5~0); 45753#L1437-1 assume !(0 == ~E_6~0); 46761#L1442-1 assume !(0 == ~E_7~0); 46762#L1447-1 assume !(0 == ~E_8~0); 46604#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 45339#L1457-1 assume !(0 == ~E_10~0); 45340#L1462-1 assume !(0 == ~E_11~0); 46796#L1467-1 assume !(0 == ~E_12~0); 46808#L1472-1 assume !(0 == ~E_13~0); 46809#L1477-1 assume !(0 == ~E_14~0); 46551#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45538#L646 assume 1 == ~m_pc~0; 45539#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46215#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46230#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45628#L1666 assume !(0 != activate_threads_~tmp~1#1); 45629#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47106#L665 assume !(1 == ~t1_pc~0); 46104#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46105#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45637#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45638#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 46428#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46429#L684 assume 1 == ~t2_pc~0; 46546#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46470#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46535#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46930#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 46931#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47119#L703 assume !(1 == ~t3_pc~0); 45774#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45775#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46421#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45173#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 45174#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45659#L722 assume 1 == ~t4_pc~0; 46397#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45840#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46185#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46745#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 46252#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45370#L741 assume 1 == ~t5_pc~0; 45371#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45681#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45835#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45836#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 46515#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45926#L760 assume !(1 == ~t6_pc~0); 45773#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45772#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45630#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45631#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46352#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46353#L779 assume 1 == ~t7_pc~0; 45415#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45261#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45262#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45670#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 45693#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45694#L798 assume !(1 == ~t8_pc~0); 46975#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46898#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45417#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45418#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 47108#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45238#L817 assume 1 == ~t9_pc~0; 45239#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46033#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46034#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46556#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 45644#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45645#L836 assume !(1 == ~t10_pc~0); 45661#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45592#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45593#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45841#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 45842#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46908#L855 assume 1 == ~t11_pc~0; 46226#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46227#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46791#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46600#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 46435#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45534#L874 assume !(1 == ~t12_pc~0); 45535#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45702#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45703#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45843#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 45211#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45212#L893 assume 1 == ~t13_pc~0; 47042#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45567#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45878#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46969#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 46977#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 46978#L912 assume 1 == ~t14_pc~0; 46768#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 46769#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45537#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45469#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 45470#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46245#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 46661#L1495-2 assume !(1 == ~T1_E~0); 46662#L1500-1 assume !(1 == ~T2_E~0); 46348#L1505-1 assume !(1 == ~T3_E~0); 46349#L1510-1 assume !(1 == ~T4_E~0); 46406#L1515-1 assume !(1 == ~T5_E~0); 46407#L1520-1 assume !(1 == ~T6_E~0); 46976#L1525-1 assume !(1 == ~T7_E~0); 46686#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45639#L1535-1 assume !(1 == ~T9_E~0); 45640#L1540-1 assume !(1 == ~T10_E~0); 45132#L1545-1 assume !(1 == ~T11_E~0); 45133#L1550-1 assume !(1 == ~T12_E~0); 45381#L1555-1 assume !(1 == ~T13_E~0); 45382#L1560-1 assume !(1 == ~T14_E~0); 45682#L1565-1 assume !(1 == ~E_1~0); 47095#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 46573#L1575-1 assume !(1 == ~E_3~0); 45952#L1580-1 assume !(1 == ~E_4~0); 45953#L1585-1 assume !(1 == ~E_5~0); 46423#L1590-1 assume !(1 == ~E_6~0); 45987#L1595-1 assume !(1 == ~E_7~0); 45988#L1600-1 assume !(1 == ~E_8~0); 46360#L1605-1 assume !(1 == ~E_9~0); 46361#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 46878#L1615-1 assume !(1 == ~E_11~0); 45817#L1620-1 assume !(1 == ~E_12~0); 45818#L1625-1 assume !(1 == ~E_13~0); 46605#L1630-1 assume !(1 == ~E_14~0); 45986#L1635-1 assume { :end_inline_reset_delta_events } true; 45927#L2017-2 [2022-02-21 04:24:54,682 INFO L793 eck$LassoCheckResult]: Loop: 45927#L2017-2 assume !false; 45207#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45208#L1316 assume !false; 46536#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46598#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45145#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45287#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45288#L1115 assume !(0 != eval_~tmp~0#1); 46621#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46042#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46043#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46225#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46726#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46395#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46396#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46958#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47133#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47128#L1372-3 assume !(0 == ~T7_E~0); 45189#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45190#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45859#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45860#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46771#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47081#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46339#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 45495#L1412-3 assume !(0 == ~E_1~0); 45496#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46260#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46261#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46955#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46642#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46354#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46355#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45255#L1452-3 assume !(0 == ~E_9~0); 45256#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46894#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46895#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 46699#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46700#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 45493#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45494#L646-42 assume !(1 == ~m_pc~0); 46080#L646-44 is_master_triggered_~__retres1~0#1 := 0; 46927#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46928#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47066#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47067#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46859#L665-42 assume 1 == ~t1_pc~0; 46820#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46822#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47008#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45662#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45663#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47132#L684-42 assume !(1 == ~t2_pc~0); 46513#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 46512#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47122#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46291#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46292#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46414#L703-42 assume 1 == ~t3_pc~0; 46612#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46613#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45931#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45932#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46706#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46326#L722-42 assume 1 == ~t4_pc~0; 46327#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46737#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45980#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45807#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45808#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47102#L741-42 assume 1 == ~t5_pc~0; 47044#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46189#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46190#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47135#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46097#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46098#L760-42 assume !(1 == ~t6_pc~0); 46232#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 46367#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46368#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46756#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 46049#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46050#L779-42 assume !(1 == ~t7_pc~0); 46826#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 46827#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45736#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45737#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45590#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45591#L798-42 assume !(1 == ~t8_pc~0); 45201#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 45202#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46945#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46391#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45421#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45422#L817-42 assume 1 == ~t9_pc~0; 46195#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45705#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45706#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45832#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46637#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46638#L836-42 assume 1 == ~t10_pc~0; 46730#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45743#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45744#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47045#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47046#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47087#L855-42 assume 1 == ~t11_pc~0; 47100#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45294#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45295#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46044#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46807#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45908#L874-42 assume 1 == ~t12_pc~0; 45909#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46148#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45209#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45210#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45463#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45464#L893-42 assume 1 == ~t13_pc~0; 46666#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46448#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46463#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46365#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 45837#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 45838#L912-42 assume !(1 == ~t14_pc~0); 46647#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 45155#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45156#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46736#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 45583#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45584#L1495-3 assume !(1 == ~M_E~0); 46199#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46627#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46720#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45813#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45776#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45777#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46434#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46657#L1530-3 assume !(1 == ~T8_E~0); 45622#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45623#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45660#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46917#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47026#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46066#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 46067#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46682#L1570-3 assume !(1 == ~E_2~0); 46633#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46634#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46989#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47033#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47079#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46456#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46457#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46932#L1610-3 assume !(1 == ~E_10~0); 45819#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45820#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46424#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46425#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 46329#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 45760#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45365#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 46103#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46659#L2036 assume !(0 == start_simulation_~tmp~3#1); 46660#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46812#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45972#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 46990#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46372#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 46373#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47093#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 47094#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 45927#L2017-2 [2022-02-21 04:24:54,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:54,683 INFO L85 PathProgramCache]: Analyzing trace with hash 1597669734, now seen corresponding path program 1 times [2022-02-21 04:24:54,683 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:54,683 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407086062] [2022-02-21 04:24:54,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:54,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:54,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:54,715 INFO L290 TraceCheckUtils]: 0: Hoare triple {51243#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {51243#true} is VALID [2022-02-21 04:24:54,716 INFO L290 TraceCheckUtils]: 1: Hoare triple {51243#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {51245#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:54,716 INFO L290 TraceCheckUtils]: 2: Hoare triple {51245#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {51245#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:54,716 INFO L290 TraceCheckUtils]: 3: Hoare triple {51245#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {51245#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:54,717 INFO L290 TraceCheckUtils]: 4: Hoare triple {51245#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {51245#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:54,717 INFO L290 TraceCheckUtils]: 5: Hoare triple {51245#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {51245#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:54,717 INFO L290 TraceCheckUtils]: 6: Hoare triple {51245#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {51245#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:54,717 INFO L290 TraceCheckUtils]: 7: Hoare triple {51245#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {51245#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:54,718 INFO L290 TraceCheckUtils]: 8: Hoare triple {51245#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {51245#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:54,718 INFO L290 TraceCheckUtils]: 9: Hoare triple {51245#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {51245#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:54,718 INFO L290 TraceCheckUtils]: 10: Hoare triple {51245#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,718 INFO L290 TraceCheckUtils]: 11: Hoare triple {51244#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,718 INFO L290 TraceCheckUtils]: 12: Hoare triple {51244#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,719 INFO L290 TraceCheckUtils]: 13: Hoare triple {51244#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {51244#false} is VALID [2022-02-21 04:24:54,719 INFO L290 TraceCheckUtils]: 14: Hoare triple {51244#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,719 INFO L290 TraceCheckUtils]: 15: Hoare triple {51244#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,719 INFO L290 TraceCheckUtils]: 16: Hoare triple {51244#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,719 INFO L290 TraceCheckUtils]: 17: Hoare triple {51244#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,719 INFO L290 TraceCheckUtils]: 18: Hoare triple {51244#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,719 INFO L290 TraceCheckUtils]: 19: Hoare triple {51244#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {51244#false} is VALID [2022-02-21 04:24:54,719 INFO L290 TraceCheckUtils]: 20: Hoare triple {51244#false} assume !(0 == ~M_E~0); {51244#false} is VALID [2022-02-21 04:24:54,719 INFO L290 TraceCheckUtils]: 21: Hoare triple {51244#false} assume !(0 == ~T1_E~0); {51244#false} is VALID [2022-02-21 04:24:54,720 INFO L290 TraceCheckUtils]: 22: Hoare triple {51244#false} assume !(0 == ~T2_E~0); {51244#false} is VALID [2022-02-21 04:24:54,720 INFO L290 TraceCheckUtils]: 23: Hoare triple {51244#false} assume !(0 == ~T3_E~0); {51244#false} is VALID [2022-02-21 04:24:54,720 INFO L290 TraceCheckUtils]: 24: Hoare triple {51244#false} assume !(0 == ~T4_E~0); {51244#false} is VALID [2022-02-21 04:24:54,720 INFO L290 TraceCheckUtils]: 25: Hoare triple {51244#false} assume !(0 == ~T5_E~0); {51244#false} is VALID [2022-02-21 04:24:54,720 INFO L290 TraceCheckUtils]: 26: Hoare triple {51244#false} assume !(0 == ~T6_E~0); {51244#false} is VALID [2022-02-21 04:24:54,720 INFO L290 TraceCheckUtils]: 27: Hoare triple {51244#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {51244#false} is VALID [2022-02-21 04:24:54,720 INFO L290 TraceCheckUtils]: 28: Hoare triple {51244#false} assume !(0 == ~T8_E~0); {51244#false} is VALID [2022-02-21 04:24:54,720 INFO L290 TraceCheckUtils]: 29: Hoare triple {51244#false} assume !(0 == ~T9_E~0); {51244#false} is VALID [2022-02-21 04:24:54,720 INFO L290 TraceCheckUtils]: 30: Hoare triple {51244#false} assume !(0 == ~T10_E~0); {51244#false} is VALID [2022-02-21 04:24:54,721 INFO L290 TraceCheckUtils]: 31: Hoare triple {51244#false} assume !(0 == ~T11_E~0); {51244#false} is VALID [2022-02-21 04:24:54,721 INFO L290 TraceCheckUtils]: 32: Hoare triple {51244#false} assume !(0 == ~T12_E~0); {51244#false} is VALID [2022-02-21 04:24:54,721 INFO L290 TraceCheckUtils]: 33: Hoare triple {51244#false} assume !(0 == ~T13_E~0); {51244#false} is VALID [2022-02-21 04:24:54,721 INFO L290 TraceCheckUtils]: 34: Hoare triple {51244#false} assume !(0 == ~T14_E~0); {51244#false} is VALID [2022-02-21 04:24:54,721 INFO L290 TraceCheckUtils]: 35: Hoare triple {51244#false} assume 0 == ~E_1~0;~E_1~0 := 1; {51244#false} is VALID [2022-02-21 04:24:54,721 INFO L290 TraceCheckUtils]: 36: Hoare triple {51244#false} assume !(0 == ~E_2~0); {51244#false} is VALID [2022-02-21 04:24:54,721 INFO L290 TraceCheckUtils]: 37: Hoare triple {51244#false} assume !(0 == ~E_3~0); {51244#false} is VALID [2022-02-21 04:24:54,721 INFO L290 TraceCheckUtils]: 38: Hoare triple {51244#false} assume !(0 == ~E_4~0); {51244#false} is VALID [2022-02-21 04:24:54,721 INFO L290 TraceCheckUtils]: 39: Hoare triple {51244#false} assume !(0 == ~E_5~0); {51244#false} is VALID [2022-02-21 04:24:54,722 INFO L290 TraceCheckUtils]: 40: Hoare triple {51244#false} assume !(0 == ~E_6~0); {51244#false} is VALID [2022-02-21 04:24:54,722 INFO L290 TraceCheckUtils]: 41: Hoare triple {51244#false} assume !(0 == ~E_7~0); {51244#false} is VALID [2022-02-21 04:24:54,722 INFO L290 TraceCheckUtils]: 42: Hoare triple {51244#false} assume !(0 == ~E_8~0); {51244#false} is VALID [2022-02-21 04:24:54,722 INFO L290 TraceCheckUtils]: 43: Hoare triple {51244#false} assume 0 == ~E_9~0;~E_9~0 := 1; {51244#false} is VALID [2022-02-21 04:24:54,722 INFO L290 TraceCheckUtils]: 44: Hoare triple {51244#false} assume !(0 == ~E_10~0); {51244#false} is VALID [2022-02-21 04:24:54,722 INFO L290 TraceCheckUtils]: 45: Hoare triple {51244#false} assume !(0 == ~E_11~0); {51244#false} is VALID [2022-02-21 04:24:54,722 INFO L290 TraceCheckUtils]: 46: Hoare triple {51244#false} assume !(0 == ~E_12~0); {51244#false} is VALID [2022-02-21 04:24:54,722 INFO L290 TraceCheckUtils]: 47: Hoare triple {51244#false} assume !(0 == ~E_13~0); {51244#false} is VALID [2022-02-21 04:24:54,722 INFO L290 TraceCheckUtils]: 48: Hoare triple {51244#false} assume !(0 == ~E_14~0); {51244#false} is VALID [2022-02-21 04:24:54,723 INFO L290 TraceCheckUtils]: 49: Hoare triple {51244#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {51244#false} is VALID [2022-02-21 04:24:54,723 INFO L290 TraceCheckUtils]: 50: Hoare triple {51244#false} assume 1 == ~m_pc~0; {51244#false} is VALID [2022-02-21 04:24:54,723 INFO L290 TraceCheckUtils]: 51: Hoare triple {51244#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {51244#false} is VALID [2022-02-21 04:24:54,723 INFO L290 TraceCheckUtils]: 52: Hoare triple {51244#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {51244#false} is VALID [2022-02-21 04:24:54,723 INFO L290 TraceCheckUtils]: 53: Hoare triple {51244#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {51244#false} is VALID [2022-02-21 04:24:54,723 INFO L290 TraceCheckUtils]: 54: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp~1#1); {51244#false} is VALID [2022-02-21 04:24:54,723 INFO L290 TraceCheckUtils]: 55: Hoare triple {51244#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {51244#false} is VALID [2022-02-21 04:24:54,723 INFO L290 TraceCheckUtils]: 56: Hoare triple {51244#false} assume !(1 == ~t1_pc~0); {51244#false} is VALID [2022-02-21 04:24:54,723 INFO L290 TraceCheckUtils]: 57: Hoare triple {51244#false} is_transmit1_triggered_~__retres1~1#1 := 0; {51244#false} is VALID [2022-02-21 04:24:54,724 INFO L290 TraceCheckUtils]: 58: Hoare triple {51244#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {51244#false} is VALID [2022-02-21 04:24:54,724 INFO L290 TraceCheckUtils]: 59: Hoare triple {51244#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {51244#false} is VALID [2022-02-21 04:24:54,724 INFO L290 TraceCheckUtils]: 60: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___0~0#1); {51244#false} is VALID [2022-02-21 04:24:54,724 INFO L290 TraceCheckUtils]: 61: Hoare triple {51244#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {51244#false} is VALID [2022-02-21 04:24:54,724 INFO L290 TraceCheckUtils]: 62: Hoare triple {51244#false} assume 1 == ~t2_pc~0; {51244#false} is VALID [2022-02-21 04:24:54,724 INFO L290 TraceCheckUtils]: 63: Hoare triple {51244#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {51244#false} is VALID [2022-02-21 04:24:54,724 INFO L290 TraceCheckUtils]: 64: Hoare triple {51244#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {51244#false} is VALID [2022-02-21 04:24:54,724 INFO L290 TraceCheckUtils]: 65: Hoare triple {51244#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {51244#false} is VALID [2022-02-21 04:24:54,724 INFO L290 TraceCheckUtils]: 66: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___1~0#1); {51244#false} is VALID [2022-02-21 04:24:54,725 INFO L290 TraceCheckUtils]: 67: Hoare triple {51244#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {51244#false} is VALID [2022-02-21 04:24:54,725 INFO L290 TraceCheckUtils]: 68: Hoare triple {51244#false} assume !(1 == ~t3_pc~0); {51244#false} is VALID [2022-02-21 04:24:54,725 INFO L290 TraceCheckUtils]: 69: Hoare triple {51244#false} is_transmit3_triggered_~__retres1~3#1 := 0; {51244#false} is VALID [2022-02-21 04:24:54,725 INFO L290 TraceCheckUtils]: 70: Hoare triple {51244#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {51244#false} is VALID [2022-02-21 04:24:54,725 INFO L290 TraceCheckUtils]: 71: Hoare triple {51244#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {51244#false} is VALID [2022-02-21 04:24:54,725 INFO L290 TraceCheckUtils]: 72: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___2~0#1); {51244#false} is VALID [2022-02-21 04:24:54,725 INFO L290 TraceCheckUtils]: 73: Hoare triple {51244#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {51244#false} is VALID [2022-02-21 04:24:54,725 INFO L290 TraceCheckUtils]: 74: Hoare triple {51244#false} assume 1 == ~t4_pc~0; {51244#false} is VALID [2022-02-21 04:24:54,725 INFO L290 TraceCheckUtils]: 75: Hoare triple {51244#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {51244#false} is VALID [2022-02-21 04:24:54,726 INFO L290 TraceCheckUtils]: 76: Hoare triple {51244#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {51244#false} is VALID [2022-02-21 04:24:54,726 INFO L290 TraceCheckUtils]: 77: Hoare triple {51244#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {51244#false} is VALID [2022-02-21 04:24:54,726 INFO L290 TraceCheckUtils]: 78: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___3~0#1); {51244#false} is VALID [2022-02-21 04:24:54,726 INFO L290 TraceCheckUtils]: 79: Hoare triple {51244#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {51244#false} is VALID [2022-02-21 04:24:54,726 INFO L290 TraceCheckUtils]: 80: Hoare triple {51244#false} assume 1 == ~t5_pc~0; {51244#false} is VALID [2022-02-21 04:24:54,726 INFO L290 TraceCheckUtils]: 81: Hoare triple {51244#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {51244#false} is VALID [2022-02-21 04:24:54,726 INFO L290 TraceCheckUtils]: 82: Hoare triple {51244#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {51244#false} is VALID [2022-02-21 04:24:54,726 INFO L290 TraceCheckUtils]: 83: Hoare triple {51244#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {51244#false} is VALID [2022-02-21 04:24:54,726 INFO L290 TraceCheckUtils]: 84: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___4~0#1); {51244#false} is VALID [2022-02-21 04:24:54,727 INFO L290 TraceCheckUtils]: 85: Hoare triple {51244#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {51244#false} is VALID [2022-02-21 04:24:54,727 INFO L290 TraceCheckUtils]: 86: Hoare triple {51244#false} assume !(1 == ~t6_pc~0); {51244#false} is VALID [2022-02-21 04:24:54,727 INFO L290 TraceCheckUtils]: 87: Hoare triple {51244#false} is_transmit6_triggered_~__retres1~6#1 := 0; {51244#false} is VALID [2022-02-21 04:24:54,727 INFO L290 TraceCheckUtils]: 88: Hoare triple {51244#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {51244#false} is VALID [2022-02-21 04:24:54,727 INFO L290 TraceCheckUtils]: 89: Hoare triple {51244#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {51244#false} is VALID [2022-02-21 04:24:54,727 INFO L290 TraceCheckUtils]: 90: Hoare triple {51244#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {51244#false} is VALID [2022-02-21 04:24:54,727 INFO L290 TraceCheckUtils]: 91: Hoare triple {51244#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {51244#false} is VALID [2022-02-21 04:24:54,727 INFO L290 TraceCheckUtils]: 92: Hoare triple {51244#false} assume 1 == ~t7_pc~0; {51244#false} is VALID [2022-02-21 04:24:54,727 INFO L290 TraceCheckUtils]: 93: Hoare triple {51244#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {51244#false} is VALID [2022-02-21 04:24:54,728 INFO L290 TraceCheckUtils]: 94: Hoare triple {51244#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {51244#false} is VALID [2022-02-21 04:24:54,728 INFO L290 TraceCheckUtils]: 95: Hoare triple {51244#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {51244#false} is VALID [2022-02-21 04:24:54,728 INFO L290 TraceCheckUtils]: 96: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___6~0#1); {51244#false} is VALID [2022-02-21 04:24:54,728 INFO L290 TraceCheckUtils]: 97: Hoare triple {51244#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {51244#false} is VALID [2022-02-21 04:24:54,728 INFO L290 TraceCheckUtils]: 98: Hoare triple {51244#false} assume !(1 == ~t8_pc~0); {51244#false} is VALID [2022-02-21 04:24:54,728 INFO L290 TraceCheckUtils]: 99: Hoare triple {51244#false} is_transmit8_triggered_~__retres1~8#1 := 0; {51244#false} is VALID [2022-02-21 04:24:54,728 INFO L290 TraceCheckUtils]: 100: Hoare triple {51244#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {51244#false} is VALID [2022-02-21 04:24:54,728 INFO L290 TraceCheckUtils]: 101: Hoare triple {51244#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {51244#false} is VALID [2022-02-21 04:24:54,729 INFO L290 TraceCheckUtils]: 102: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___7~0#1); {51244#false} is VALID [2022-02-21 04:24:54,729 INFO L290 TraceCheckUtils]: 103: Hoare triple {51244#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {51244#false} is VALID [2022-02-21 04:24:54,729 INFO L290 TraceCheckUtils]: 104: Hoare triple {51244#false} assume 1 == ~t9_pc~0; {51244#false} is VALID [2022-02-21 04:24:54,729 INFO L290 TraceCheckUtils]: 105: Hoare triple {51244#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {51244#false} is VALID [2022-02-21 04:24:54,729 INFO L290 TraceCheckUtils]: 106: Hoare triple {51244#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {51244#false} is VALID [2022-02-21 04:24:54,729 INFO L290 TraceCheckUtils]: 107: Hoare triple {51244#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {51244#false} is VALID [2022-02-21 04:24:54,729 INFO L290 TraceCheckUtils]: 108: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___8~0#1); {51244#false} is VALID [2022-02-21 04:24:54,729 INFO L290 TraceCheckUtils]: 109: Hoare triple {51244#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {51244#false} is VALID [2022-02-21 04:24:54,729 INFO L290 TraceCheckUtils]: 110: Hoare triple {51244#false} assume !(1 == ~t10_pc~0); {51244#false} is VALID [2022-02-21 04:24:54,730 INFO L290 TraceCheckUtils]: 111: Hoare triple {51244#false} is_transmit10_triggered_~__retres1~10#1 := 0; {51244#false} is VALID [2022-02-21 04:24:54,730 INFO L290 TraceCheckUtils]: 112: Hoare triple {51244#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {51244#false} is VALID [2022-02-21 04:24:54,730 INFO L290 TraceCheckUtils]: 113: Hoare triple {51244#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {51244#false} is VALID [2022-02-21 04:24:54,730 INFO L290 TraceCheckUtils]: 114: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___9~0#1); {51244#false} is VALID [2022-02-21 04:24:54,730 INFO L290 TraceCheckUtils]: 115: Hoare triple {51244#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {51244#false} is VALID [2022-02-21 04:24:54,730 INFO L290 TraceCheckUtils]: 116: Hoare triple {51244#false} assume 1 == ~t11_pc~0; {51244#false} is VALID [2022-02-21 04:24:54,730 INFO L290 TraceCheckUtils]: 117: Hoare triple {51244#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {51244#false} is VALID [2022-02-21 04:24:54,730 INFO L290 TraceCheckUtils]: 118: Hoare triple {51244#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {51244#false} is VALID [2022-02-21 04:24:54,730 INFO L290 TraceCheckUtils]: 119: Hoare triple {51244#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {51244#false} is VALID [2022-02-21 04:24:54,731 INFO L290 TraceCheckUtils]: 120: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___10~0#1); {51244#false} is VALID [2022-02-21 04:24:54,731 INFO L290 TraceCheckUtils]: 121: Hoare triple {51244#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {51244#false} is VALID [2022-02-21 04:24:54,731 INFO L290 TraceCheckUtils]: 122: Hoare triple {51244#false} assume !(1 == ~t12_pc~0); {51244#false} is VALID [2022-02-21 04:24:54,731 INFO L290 TraceCheckUtils]: 123: Hoare triple {51244#false} is_transmit12_triggered_~__retres1~12#1 := 0; {51244#false} is VALID [2022-02-21 04:24:54,731 INFO L290 TraceCheckUtils]: 124: Hoare triple {51244#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {51244#false} is VALID [2022-02-21 04:24:54,731 INFO L290 TraceCheckUtils]: 125: Hoare triple {51244#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {51244#false} is VALID [2022-02-21 04:24:54,731 INFO L290 TraceCheckUtils]: 126: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___11~0#1); {51244#false} is VALID [2022-02-21 04:24:54,731 INFO L290 TraceCheckUtils]: 127: Hoare triple {51244#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {51244#false} is VALID [2022-02-21 04:24:54,731 INFO L290 TraceCheckUtils]: 128: Hoare triple {51244#false} assume 1 == ~t13_pc~0; {51244#false} is VALID [2022-02-21 04:24:54,732 INFO L290 TraceCheckUtils]: 129: Hoare triple {51244#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {51244#false} is VALID [2022-02-21 04:24:54,732 INFO L290 TraceCheckUtils]: 130: Hoare triple {51244#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {51244#false} is VALID [2022-02-21 04:24:54,732 INFO L290 TraceCheckUtils]: 131: Hoare triple {51244#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {51244#false} is VALID [2022-02-21 04:24:54,732 INFO L290 TraceCheckUtils]: 132: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___12~0#1); {51244#false} is VALID [2022-02-21 04:24:54,732 INFO L290 TraceCheckUtils]: 133: Hoare triple {51244#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {51244#false} is VALID [2022-02-21 04:24:54,732 INFO L290 TraceCheckUtils]: 134: Hoare triple {51244#false} assume 1 == ~t14_pc~0; {51244#false} is VALID [2022-02-21 04:24:54,732 INFO L290 TraceCheckUtils]: 135: Hoare triple {51244#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {51244#false} is VALID [2022-02-21 04:24:54,732 INFO L290 TraceCheckUtils]: 136: Hoare triple {51244#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {51244#false} is VALID [2022-02-21 04:24:54,732 INFO L290 TraceCheckUtils]: 137: Hoare triple {51244#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {51244#false} is VALID [2022-02-21 04:24:54,733 INFO L290 TraceCheckUtils]: 138: Hoare triple {51244#false} assume !(0 != activate_threads_~tmp___13~0#1); {51244#false} is VALID [2022-02-21 04:24:54,733 INFO L290 TraceCheckUtils]: 139: Hoare triple {51244#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51244#false} is VALID [2022-02-21 04:24:54,733 INFO L290 TraceCheckUtils]: 140: Hoare triple {51244#false} assume 1 == ~M_E~0;~M_E~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,733 INFO L290 TraceCheckUtils]: 141: Hoare triple {51244#false} assume !(1 == ~T1_E~0); {51244#false} is VALID [2022-02-21 04:24:54,733 INFO L290 TraceCheckUtils]: 142: Hoare triple {51244#false} assume !(1 == ~T2_E~0); {51244#false} is VALID [2022-02-21 04:24:54,733 INFO L290 TraceCheckUtils]: 143: Hoare triple {51244#false} assume !(1 == ~T3_E~0); {51244#false} is VALID [2022-02-21 04:24:54,733 INFO L290 TraceCheckUtils]: 144: Hoare triple {51244#false} assume !(1 == ~T4_E~0); {51244#false} is VALID [2022-02-21 04:24:54,733 INFO L290 TraceCheckUtils]: 145: Hoare triple {51244#false} assume !(1 == ~T5_E~0); {51244#false} is VALID [2022-02-21 04:24:54,733 INFO L290 TraceCheckUtils]: 146: Hoare triple {51244#false} assume !(1 == ~T6_E~0); {51244#false} is VALID [2022-02-21 04:24:54,734 INFO L290 TraceCheckUtils]: 147: Hoare triple {51244#false} assume !(1 == ~T7_E~0); {51244#false} is VALID [2022-02-21 04:24:54,734 INFO L290 TraceCheckUtils]: 148: Hoare triple {51244#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,734 INFO L290 TraceCheckUtils]: 149: Hoare triple {51244#false} assume !(1 == ~T9_E~0); {51244#false} is VALID [2022-02-21 04:24:54,734 INFO L290 TraceCheckUtils]: 150: Hoare triple {51244#false} assume !(1 == ~T10_E~0); {51244#false} is VALID [2022-02-21 04:24:54,734 INFO L290 TraceCheckUtils]: 151: Hoare triple {51244#false} assume !(1 == ~T11_E~0); {51244#false} is VALID [2022-02-21 04:24:54,734 INFO L290 TraceCheckUtils]: 152: Hoare triple {51244#false} assume !(1 == ~T12_E~0); {51244#false} is VALID [2022-02-21 04:24:54,734 INFO L290 TraceCheckUtils]: 153: Hoare triple {51244#false} assume !(1 == ~T13_E~0); {51244#false} is VALID [2022-02-21 04:24:54,734 INFO L290 TraceCheckUtils]: 154: Hoare triple {51244#false} assume !(1 == ~T14_E~0); {51244#false} is VALID [2022-02-21 04:24:54,734 INFO L290 TraceCheckUtils]: 155: Hoare triple {51244#false} assume !(1 == ~E_1~0); {51244#false} is VALID [2022-02-21 04:24:54,735 INFO L290 TraceCheckUtils]: 156: Hoare triple {51244#false} assume 1 == ~E_2~0;~E_2~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,735 INFO L290 TraceCheckUtils]: 157: Hoare triple {51244#false} assume !(1 == ~E_3~0); {51244#false} is VALID [2022-02-21 04:24:54,735 INFO L290 TraceCheckUtils]: 158: Hoare triple {51244#false} assume !(1 == ~E_4~0); {51244#false} is VALID [2022-02-21 04:24:54,735 INFO L290 TraceCheckUtils]: 159: Hoare triple {51244#false} assume !(1 == ~E_5~0); {51244#false} is VALID [2022-02-21 04:24:54,735 INFO L290 TraceCheckUtils]: 160: Hoare triple {51244#false} assume !(1 == ~E_6~0); {51244#false} is VALID [2022-02-21 04:24:54,735 INFO L290 TraceCheckUtils]: 161: Hoare triple {51244#false} assume !(1 == ~E_7~0); {51244#false} is VALID [2022-02-21 04:24:54,735 INFO L290 TraceCheckUtils]: 162: Hoare triple {51244#false} assume !(1 == ~E_8~0); {51244#false} is VALID [2022-02-21 04:24:54,735 INFO L290 TraceCheckUtils]: 163: Hoare triple {51244#false} assume !(1 == ~E_9~0); {51244#false} is VALID [2022-02-21 04:24:54,735 INFO L290 TraceCheckUtils]: 164: Hoare triple {51244#false} assume 1 == ~E_10~0;~E_10~0 := 2; {51244#false} is VALID [2022-02-21 04:24:54,736 INFO L290 TraceCheckUtils]: 165: Hoare triple {51244#false} assume !(1 == ~E_11~0); {51244#false} is VALID [2022-02-21 04:24:54,736 INFO L290 TraceCheckUtils]: 166: Hoare triple {51244#false} assume !(1 == ~E_12~0); {51244#false} is VALID [2022-02-21 04:24:54,736 INFO L290 TraceCheckUtils]: 167: Hoare triple {51244#false} assume !(1 == ~E_13~0); {51244#false} is VALID [2022-02-21 04:24:54,736 INFO L290 TraceCheckUtils]: 168: Hoare triple {51244#false} assume !(1 == ~E_14~0); {51244#false} is VALID [2022-02-21 04:24:54,736 INFO L290 TraceCheckUtils]: 169: Hoare triple {51244#false} assume { :end_inline_reset_delta_events } true; {51244#false} is VALID [2022-02-21 04:24:54,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:54,737 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:54,737 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1407086062] [2022-02-21 04:24:54,737 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1407086062] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:54,737 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:54,737 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:54,737 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996457106] [2022-02-21 04:24:54,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:54,738 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:54,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:54,738 INFO L85 PathProgramCache]: Analyzing trace with hash -1842591925, now seen corresponding path program 1 times [2022-02-21 04:24:54,738 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:54,739 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458568949] [2022-02-21 04:24:54,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:54,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:54,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:54,773 INFO L290 TraceCheckUtils]: 0: Hoare triple {51246#true} assume !false; {51246#true} is VALID [2022-02-21 04:24:54,773 INFO L290 TraceCheckUtils]: 1: Hoare triple {51246#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {51246#true} is VALID [2022-02-21 04:24:54,774 INFO L290 TraceCheckUtils]: 2: Hoare triple {51246#true} assume !false; {51246#true} is VALID [2022-02-21 04:24:54,774 INFO L290 TraceCheckUtils]: 3: Hoare triple {51246#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {51246#true} is VALID [2022-02-21 04:24:54,774 INFO L290 TraceCheckUtils]: 4: Hoare triple {51246#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {51246#true} is VALID [2022-02-21 04:24:54,774 INFO L290 TraceCheckUtils]: 5: Hoare triple {51246#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {51246#true} is VALID [2022-02-21 04:24:54,774 INFO L290 TraceCheckUtils]: 6: Hoare triple {51246#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {51246#true} is VALID [2022-02-21 04:24:54,774 INFO L290 TraceCheckUtils]: 7: Hoare triple {51246#true} assume !(0 != eval_~tmp~0#1); {51246#true} is VALID [2022-02-21 04:24:54,774 INFO L290 TraceCheckUtils]: 8: Hoare triple {51246#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {51246#true} is VALID [2022-02-21 04:24:54,774 INFO L290 TraceCheckUtils]: 9: Hoare triple {51246#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {51246#true} is VALID [2022-02-21 04:24:54,775 INFO L290 TraceCheckUtils]: 10: Hoare triple {51246#true} assume 0 == ~M_E~0;~M_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,775 INFO L290 TraceCheckUtils]: 11: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,775 INFO L290 TraceCheckUtils]: 12: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,776 INFO L290 TraceCheckUtils]: 13: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,776 INFO L290 TraceCheckUtils]: 14: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,776 INFO L290 TraceCheckUtils]: 15: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,776 INFO L290 TraceCheckUtils]: 16: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,777 INFO L290 TraceCheckUtils]: 17: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,777 INFO L290 TraceCheckUtils]: 18: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,777 INFO L290 TraceCheckUtils]: 19: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,778 INFO L290 TraceCheckUtils]: 20: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,778 INFO L290 TraceCheckUtils]: 21: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,778 INFO L290 TraceCheckUtils]: 22: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,778 INFO L290 TraceCheckUtils]: 23: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,779 INFO L290 TraceCheckUtils]: 24: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,779 INFO L290 TraceCheckUtils]: 25: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,779 INFO L290 TraceCheckUtils]: 26: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,780 INFO L290 TraceCheckUtils]: 27: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,780 INFO L290 TraceCheckUtils]: 28: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,780 INFO L290 TraceCheckUtils]: 29: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,780 INFO L290 TraceCheckUtils]: 30: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,781 INFO L290 TraceCheckUtils]: 31: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,781 INFO L290 TraceCheckUtils]: 32: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,781 INFO L290 TraceCheckUtils]: 33: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,782 INFO L290 TraceCheckUtils]: 34: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,782 INFO L290 TraceCheckUtils]: 35: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,782 INFO L290 TraceCheckUtils]: 36: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,782 INFO L290 TraceCheckUtils]: 37: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,783 INFO L290 TraceCheckUtils]: 38: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,783 INFO L290 TraceCheckUtils]: 39: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,783 INFO L290 TraceCheckUtils]: 40: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,784 INFO L290 TraceCheckUtils]: 41: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,784 INFO L290 TraceCheckUtils]: 42: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,784 INFO L290 TraceCheckUtils]: 43: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,784 INFO L290 TraceCheckUtils]: 44: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,785 INFO L290 TraceCheckUtils]: 45: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,785 INFO L290 TraceCheckUtils]: 46: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,785 INFO L290 TraceCheckUtils]: 47: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,786 INFO L290 TraceCheckUtils]: 48: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,786 INFO L290 TraceCheckUtils]: 49: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,786 INFO L290 TraceCheckUtils]: 50: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,786 INFO L290 TraceCheckUtils]: 51: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,787 INFO L290 TraceCheckUtils]: 52: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,787 INFO L290 TraceCheckUtils]: 53: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,787 INFO L290 TraceCheckUtils]: 54: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,788 INFO L290 TraceCheckUtils]: 55: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,788 INFO L290 TraceCheckUtils]: 56: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,788 INFO L290 TraceCheckUtils]: 57: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,788 INFO L290 TraceCheckUtils]: 58: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,789 INFO L290 TraceCheckUtils]: 59: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,789 INFO L290 TraceCheckUtils]: 60: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,789 INFO L290 TraceCheckUtils]: 61: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,790 INFO L290 TraceCheckUtils]: 62: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,790 INFO L290 TraceCheckUtils]: 63: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,790 INFO L290 TraceCheckUtils]: 64: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,790 INFO L290 TraceCheckUtils]: 65: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,791 INFO L290 TraceCheckUtils]: 66: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,791 INFO L290 TraceCheckUtils]: 67: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,791 INFO L290 TraceCheckUtils]: 68: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,792 INFO L290 TraceCheckUtils]: 69: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,792 INFO L290 TraceCheckUtils]: 70: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,792 INFO L290 TraceCheckUtils]: 71: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,792 INFO L290 TraceCheckUtils]: 72: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,793 INFO L290 TraceCheckUtils]: 73: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,793 INFO L290 TraceCheckUtils]: 74: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,793 INFO L290 TraceCheckUtils]: 75: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,794 INFO L290 TraceCheckUtils]: 76: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,794 INFO L290 TraceCheckUtils]: 77: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,794 INFO L290 TraceCheckUtils]: 78: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,794 INFO L290 TraceCheckUtils]: 79: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,795 INFO L290 TraceCheckUtils]: 80: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,795 INFO L290 TraceCheckUtils]: 81: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,795 INFO L290 TraceCheckUtils]: 82: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,796 INFO L290 TraceCheckUtils]: 83: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,796 INFO L290 TraceCheckUtils]: 84: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,796 INFO L290 TraceCheckUtils]: 85: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,796 INFO L290 TraceCheckUtils]: 86: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,797 INFO L290 TraceCheckUtils]: 87: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,797 INFO L290 TraceCheckUtils]: 88: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,797 INFO L290 TraceCheckUtils]: 89: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,798 INFO L290 TraceCheckUtils]: 90: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,798 INFO L290 TraceCheckUtils]: 91: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,798 INFO L290 TraceCheckUtils]: 92: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,798 INFO L290 TraceCheckUtils]: 93: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,799 INFO L290 TraceCheckUtils]: 94: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,799 INFO L290 TraceCheckUtils]: 95: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,799 INFO L290 TraceCheckUtils]: 96: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,800 INFO L290 TraceCheckUtils]: 97: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,800 INFO L290 TraceCheckUtils]: 98: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,800 INFO L290 TraceCheckUtils]: 99: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,800 INFO L290 TraceCheckUtils]: 100: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,801 INFO L290 TraceCheckUtils]: 101: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,801 INFO L290 TraceCheckUtils]: 102: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,801 INFO L290 TraceCheckUtils]: 103: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,801 INFO L290 TraceCheckUtils]: 104: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,802 INFO L290 TraceCheckUtils]: 105: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,802 INFO L290 TraceCheckUtils]: 106: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,802 INFO L290 TraceCheckUtils]: 107: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,803 INFO L290 TraceCheckUtils]: 108: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,803 INFO L290 TraceCheckUtils]: 109: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,803 INFO L290 TraceCheckUtils]: 110: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,803 INFO L290 TraceCheckUtils]: 111: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,804 INFO L290 TraceCheckUtils]: 112: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,804 INFO L290 TraceCheckUtils]: 113: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,804 INFO L290 TraceCheckUtils]: 114: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,805 INFO L290 TraceCheckUtils]: 115: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,805 INFO L290 TraceCheckUtils]: 116: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,805 INFO L290 TraceCheckUtils]: 117: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,805 INFO L290 TraceCheckUtils]: 118: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,806 INFO L290 TraceCheckUtils]: 119: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,806 INFO L290 TraceCheckUtils]: 120: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,806 INFO L290 TraceCheckUtils]: 121: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,807 INFO L290 TraceCheckUtils]: 122: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,807 INFO L290 TraceCheckUtils]: 123: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,807 INFO L290 TraceCheckUtils]: 124: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,807 INFO L290 TraceCheckUtils]: 125: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,808 INFO L290 TraceCheckUtils]: 126: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,808 INFO L290 TraceCheckUtils]: 127: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,808 INFO L290 TraceCheckUtils]: 128: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,809 INFO L290 TraceCheckUtils]: 129: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51248#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,809 INFO L290 TraceCheckUtils]: 130: Hoare triple {51248#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {51247#false} is VALID [2022-02-21 04:24:54,809 INFO L290 TraceCheckUtils]: 131: Hoare triple {51247#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,809 INFO L290 TraceCheckUtils]: 132: Hoare triple {51247#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,809 INFO L290 TraceCheckUtils]: 133: Hoare triple {51247#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,809 INFO L290 TraceCheckUtils]: 134: Hoare triple {51247#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,810 INFO L290 TraceCheckUtils]: 135: Hoare triple {51247#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,810 INFO L290 TraceCheckUtils]: 136: Hoare triple {51247#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,810 INFO L290 TraceCheckUtils]: 137: Hoare triple {51247#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,810 INFO L290 TraceCheckUtils]: 138: Hoare triple {51247#false} assume !(1 == ~T8_E~0); {51247#false} is VALID [2022-02-21 04:24:54,810 INFO L290 TraceCheckUtils]: 139: Hoare triple {51247#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,810 INFO L290 TraceCheckUtils]: 140: Hoare triple {51247#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,810 INFO L290 TraceCheckUtils]: 141: Hoare triple {51247#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,810 INFO L290 TraceCheckUtils]: 142: Hoare triple {51247#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,810 INFO L290 TraceCheckUtils]: 143: Hoare triple {51247#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,811 INFO L290 TraceCheckUtils]: 144: Hoare triple {51247#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,811 INFO L290 TraceCheckUtils]: 145: Hoare triple {51247#false} assume 1 == ~E_1~0;~E_1~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,811 INFO L290 TraceCheckUtils]: 146: Hoare triple {51247#false} assume !(1 == ~E_2~0); {51247#false} is VALID [2022-02-21 04:24:54,811 INFO L290 TraceCheckUtils]: 147: Hoare triple {51247#false} assume 1 == ~E_3~0;~E_3~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,811 INFO L290 TraceCheckUtils]: 148: Hoare triple {51247#false} assume 1 == ~E_4~0;~E_4~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,811 INFO L290 TraceCheckUtils]: 149: Hoare triple {51247#false} assume 1 == ~E_5~0;~E_5~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,811 INFO L290 TraceCheckUtils]: 150: Hoare triple {51247#false} assume 1 == ~E_6~0;~E_6~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,811 INFO L290 TraceCheckUtils]: 151: Hoare triple {51247#false} assume 1 == ~E_7~0;~E_7~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,811 INFO L290 TraceCheckUtils]: 152: Hoare triple {51247#false} assume 1 == ~E_8~0;~E_8~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,812 INFO L290 TraceCheckUtils]: 153: Hoare triple {51247#false} assume 1 == ~E_9~0;~E_9~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,812 INFO L290 TraceCheckUtils]: 154: Hoare triple {51247#false} assume !(1 == ~E_10~0); {51247#false} is VALID [2022-02-21 04:24:54,812 INFO L290 TraceCheckUtils]: 155: Hoare triple {51247#false} assume 1 == ~E_11~0;~E_11~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,812 INFO L290 TraceCheckUtils]: 156: Hoare triple {51247#false} assume 1 == ~E_12~0;~E_12~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,812 INFO L290 TraceCheckUtils]: 157: Hoare triple {51247#false} assume 1 == ~E_13~0;~E_13~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,812 INFO L290 TraceCheckUtils]: 158: Hoare triple {51247#false} assume 1 == ~E_14~0;~E_14~0 := 2; {51247#false} is VALID [2022-02-21 04:24:54,812 INFO L290 TraceCheckUtils]: 159: Hoare triple {51247#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {51247#false} is VALID [2022-02-21 04:24:54,812 INFO L290 TraceCheckUtils]: 160: Hoare triple {51247#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {51247#false} is VALID [2022-02-21 04:24:54,812 INFO L290 TraceCheckUtils]: 161: Hoare triple {51247#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {51247#false} is VALID [2022-02-21 04:24:54,813 INFO L290 TraceCheckUtils]: 162: Hoare triple {51247#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {51247#false} is VALID [2022-02-21 04:24:54,813 INFO L290 TraceCheckUtils]: 163: Hoare triple {51247#false} assume !(0 == start_simulation_~tmp~3#1); {51247#false} is VALID [2022-02-21 04:24:54,813 INFO L290 TraceCheckUtils]: 164: Hoare triple {51247#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {51247#false} is VALID [2022-02-21 04:24:54,813 INFO L290 TraceCheckUtils]: 165: Hoare triple {51247#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {51247#false} is VALID [2022-02-21 04:24:54,813 INFO L290 TraceCheckUtils]: 166: Hoare triple {51247#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {51247#false} is VALID [2022-02-21 04:24:54,813 INFO L290 TraceCheckUtils]: 167: Hoare triple {51247#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {51247#false} is VALID [2022-02-21 04:24:54,813 INFO L290 TraceCheckUtils]: 168: Hoare triple {51247#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {51247#false} is VALID [2022-02-21 04:24:54,813 INFO L290 TraceCheckUtils]: 169: Hoare triple {51247#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {51247#false} is VALID [2022-02-21 04:24:54,813 INFO L290 TraceCheckUtils]: 170: Hoare triple {51247#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {51247#false} is VALID [2022-02-21 04:24:54,814 INFO L290 TraceCheckUtils]: 171: Hoare triple {51247#false} assume !(0 != start_simulation_~tmp___0~1#1); {51247#false} is VALID [2022-02-21 04:24:54,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:54,814 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:54,814 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458568949] [2022-02-21 04:24:54,814 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458568949] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:54,815 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:54,815 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:54,815 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299169536] [2022-02-21 04:24:54,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:54,815 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:54,815 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:54,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:54,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:54,817 INFO L87 Difference]: Start difference. First operand 2047 states and 3029 transitions. cyclomatic complexity: 983 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:56,263 INFO L93 Difference]: Finished difference Result 2047 states and 3028 transitions. [2022-02-21 04:24:56,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:56,263 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,355 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:56,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3028 transitions. [2022-02-21 04:24:56,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:56,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3028 transitions. [2022-02-21 04:24:56,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:24:56,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:24:56,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3028 transitions. [2022-02-21 04:24:56,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:56,565 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2022-02-21 04:24:56,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3028 transitions. [2022-02-21 04:24:56,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:24:56,582 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:56,584 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3028 transitions. Second operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,585 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3028 transitions. Second operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,586 INFO L87 Difference]: Start difference. First operand 2047 states and 3028 transitions. Second operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:56,670 INFO L93 Difference]: Finished difference Result 2047 states and 3028 transitions. [2022-02-21 04:24:56,670 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3028 transitions. [2022-02-21 04:24:56,672 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:56,672 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:56,674 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3028 transitions. [2022-02-21 04:24:56,675 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3028 transitions. [2022-02-21 04:24:56,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:56,763 INFO L93 Difference]: Finished difference Result 2047 states and 3028 transitions. [2022-02-21 04:24:56,763 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3028 transitions. [2022-02-21 04:24:56,765 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:56,765 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:56,765 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:56,765 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:56,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3028 transitions. [2022-02-21 04:24:56,852 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2022-02-21 04:24:56,853 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2022-02-21 04:24:56,853 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:56,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3028 transitions. [2022-02-21 04:24:56,857 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:56,857 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:56,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:56,858 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:56,858 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:56,859 INFO L791 eck$LassoCheckResult]: Stem: 54222#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 54223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 54825#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53942#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53943#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 54188#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54189#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53916#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53917#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55140#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54492#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54493#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 55010#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 54402#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54403#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 53823#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 53824#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 54155#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 54353#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 53400#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53401#L1342 assume !(0 == ~M_E~0); 53566#L1342-2 assume !(0 == ~T1_E~0); 54122#L1347-1 assume !(0 == ~T2_E~0); 55123#L1352-1 assume !(0 == ~T3_E~0); 54919#L1357-1 assume !(0 == ~T4_E~0); 54147#L1362-1 assume !(0 == ~T5_E~0); 54148#L1367-1 assume !(0 == ~T6_E~0); 53745#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53746#L1377-1 assume !(0 == ~T8_E~0); 54076#L1382-1 assume !(0 == ~T9_E~0); 54077#L1387-1 assume !(0 == ~T10_E~0); 54804#L1392-1 assume !(0 == ~T11_E~0); 54108#L1397-1 assume !(0 == ~T12_E~0); 54109#L1402-1 assume !(0 == ~T13_E~0); 53761#L1407-1 assume !(0 == ~T14_E~0); 53762#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 55040#L1417-1 assume !(0 == ~E_2~0); 55041#L1422-1 assume !(0 == ~E_3~0); 55282#L1427-1 assume !(0 == ~E_4~0); 53949#L1432-1 assume !(0 == ~E_5~0); 53950#L1437-1 assume !(0 == ~E_6~0); 54958#L1442-1 assume !(0 == ~E_7~0); 54959#L1447-1 assume !(0 == ~E_8~0); 54801#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 53536#L1457-1 assume !(0 == ~E_10~0); 53537#L1462-1 assume !(0 == ~E_11~0); 54993#L1467-1 assume !(0 == ~E_12~0); 55005#L1472-1 assume !(0 == ~E_13~0); 55006#L1477-1 assume !(0 == ~E_14~0); 54748#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53735#L646 assume 1 == ~m_pc~0; 53736#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54412#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54427#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53825#L1666 assume !(0 != activate_threads_~tmp~1#1); 53826#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55303#L665 assume !(1 == ~t1_pc~0); 54301#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54302#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53834#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53835#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 54625#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54626#L684 assume 1 == ~t2_pc~0; 54743#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54667#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54732#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55127#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 55128#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55316#L703 assume !(1 == ~t3_pc~0); 53971#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53972#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54618#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53370#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 53371#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53856#L722 assume 1 == ~t4_pc~0; 54594#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54037#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54382#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54942#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 54449#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53567#L741 assume 1 == ~t5_pc~0; 53568#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53878#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54032#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54033#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 54712#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54123#L760 assume !(1 == ~t6_pc~0); 53970#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53969#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53827#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53828#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54549#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54550#L779 assume 1 == ~t7_pc~0; 53612#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53458#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53459#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53867#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 53890#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53891#L798 assume !(1 == ~t8_pc~0); 55172#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 55095#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53614#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53615#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 55305#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53435#L817 assume 1 == ~t9_pc~0; 53436#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54230#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54231#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54753#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 53841#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53842#L836 assume !(1 == ~t10_pc~0); 53858#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53789#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53790#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54038#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 54039#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55105#L855 assume 1 == ~t11_pc~0; 54423#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54424#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54988#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54797#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 54632#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53731#L874 assume !(1 == ~t12_pc~0); 53732#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53899#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53900#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54040#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 53408#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53409#L893 assume 1 == ~t13_pc~0; 55239#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53764#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54075#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 55166#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 55174#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 55175#L912 assume 1 == ~t14_pc~0; 54965#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 54966#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53734#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 53666#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 53667#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54442#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 54858#L1495-2 assume !(1 == ~T1_E~0); 54859#L1500-1 assume !(1 == ~T2_E~0); 54545#L1505-1 assume !(1 == ~T3_E~0); 54546#L1510-1 assume !(1 == ~T4_E~0); 54603#L1515-1 assume !(1 == ~T5_E~0); 54604#L1520-1 assume !(1 == ~T6_E~0); 55173#L1525-1 assume !(1 == ~T7_E~0); 54883#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53836#L1535-1 assume !(1 == ~T9_E~0); 53837#L1540-1 assume !(1 == ~T10_E~0); 53329#L1545-1 assume !(1 == ~T11_E~0); 53330#L1550-1 assume !(1 == ~T12_E~0); 53578#L1555-1 assume !(1 == ~T13_E~0); 53579#L1560-1 assume !(1 == ~T14_E~0); 53879#L1565-1 assume !(1 == ~E_1~0); 55292#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 54770#L1575-1 assume !(1 == ~E_3~0); 54149#L1580-1 assume !(1 == ~E_4~0); 54150#L1585-1 assume !(1 == ~E_5~0); 54620#L1590-1 assume !(1 == ~E_6~0); 54184#L1595-1 assume !(1 == ~E_7~0); 54185#L1600-1 assume !(1 == ~E_8~0); 54557#L1605-1 assume !(1 == ~E_9~0); 54558#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 55075#L1615-1 assume !(1 == ~E_11~0); 54014#L1620-1 assume !(1 == ~E_12~0); 54015#L1625-1 assume !(1 == ~E_13~0); 54802#L1630-1 assume !(1 == ~E_14~0); 54183#L1635-1 assume { :end_inline_reset_delta_events } true; 54124#L2017-2 [2022-02-21 04:24:56,859 INFO L793 eck$LassoCheckResult]: Loop: 54124#L2017-2 assume !false; 53404#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53405#L1316 assume !false; 54733#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 54795#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53342#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 53484#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53485#L1115 assume !(0 != eval_~tmp~0#1); 54818#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54239#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54240#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54422#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54923#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54592#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54593#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55155#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55330#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55325#L1372-3 assume !(0 == ~T7_E~0); 53386#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53387#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54056#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54057#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54968#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 55278#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54536#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 53692#L1412-3 assume !(0 == ~E_1~0); 53693#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54457#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54458#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55152#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54839#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54551#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54552#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53452#L1452-3 assume !(0 == ~E_9~0); 53453#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55091#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55092#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54896#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54897#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 53690#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53691#L646-42 assume 1 == ~m_pc~0; 54276#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 55124#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55125#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55263#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55264#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55056#L665-42 assume 1 == ~t1_pc~0; 55017#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55019#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55205#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53859#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53860#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55329#L684-42 assume 1 == ~t2_pc~0; 54708#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54709#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55319#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54488#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54489#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54611#L703-42 assume 1 == ~t3_pc~0; 54809#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54810#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54128#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54129#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54903#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54523#L722-42 assume 1 == ~t4_pc~0; 54524#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54934#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54177#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54004#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54005#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55299#L741-42 assume !(1 == ~t5_pc~0); 54916#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 54386#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54387#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55332#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54294#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54295#L760-42 assume !(1 == ~t6_pc~0); 54429#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 54564#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54565#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54953#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 54246#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54247#L779-42 assume 1 == ~t7_pc~0; 55076#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55024#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53933#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53934#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53787#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53788#L798-42 assume !(1 == ~t8_pc~0); 53398#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 53399#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55142#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54588#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53618#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53619#L817-42 assume 1 == ~t9_pc~0; 54392#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53902#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53903#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54029#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54834#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54835#L836-42 assume !(1 == ~t10_pc~0); 54928#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 53940#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53941#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55242#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55243#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55284#L855-42 assume 1 == ~t11_pc~0; 55297#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53491#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53492#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54241#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 55004#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54105#L874-42 assume 1 == ~t12_pc~0; 54106#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54345#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53406#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53407#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53660#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53661#L893-42 assume 1 == ~t13_pc~0; 54864#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54645#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54660#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54562#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 54034#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 54035#L912-42 assume !(1 == ~t14_pc~0); 54844#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 53352#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53353#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54933#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 53780#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53781#L1495-3 assume !(1 == ~M_E~0); 54396#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54824#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54917#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54010#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53973#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53974#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54631#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54854#L1530-3 assume !(1 == ~T8_E~0); 53819#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53820#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53857#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 55114#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55223#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54263#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 54264#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54879#L1570-3 assume !(1 == ~E_2~0); 54830#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54831#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55186#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55230#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55276#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54653#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54654#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 55129#L1610-3 assume !(1 == ~E_10~0); 54016#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54017#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54621#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54622#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 54526#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 53957#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53562#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 54300#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54856#L2036 assume !(0 == start_simulation_~tmp~3#1); 54857#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55009#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 54169#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 55187#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54569#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 54570#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55290#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 55291#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 54124#L2017-2 [2022-02-21 04:24:56,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:56,860 INFO L85 PathProgramCache]: Analyzing trace with hash -1911299672, now seen corresponding path program 1 times [2022-02-21 04:24:56,860 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:56,860 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529937849] [2022-02-21 04:24:56,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:56,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:56,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:56,889 INFO L290 TraceCheckUtils]: 0: Hoare triple {59440#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {59440#true} is VALID [2022-02-21 04:24:56,889 INFO L290 TraceCheckUtils]: 1: Hoare triple {59440#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,890 INFO L290 TraceCheckUtils]: 2: Hoare triple {59442#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,890 INFO L290 TraceCheckUtils]: 3: Hoare triple {59442#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,890 INFO L290 TraceCheckUtils]: 4: Hoare triple {59442#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,890 INFO L290 TraceCheckUtils]: 5: Hoare triple {59442#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,891 INFO L290 TraceCheckUtils]: 6: Hoare triple {59442#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,891 INFO L290 TraceCheckUtils]: 7: Hoare triple {59442#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,891 INFO L290 TraceCheckUtils]: 8: Hoare triple {59442#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,892 INFO L290 TraceCheckUtils]: 9: Hoare triple {59442#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,892 INFO L290 TraceCheckUtils]: 10: Hoare triple {59442#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {59442#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:56,892 INFO L290 TraceCheckUtils]: 11: Hoare triple {59442#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,892 INFO L290 TraceCheckUtils]: 12: Hoare triple {59441#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,893 INFO L290 TraceCheckUtils]: 13: Hoare triple {59441#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {59441#false} is VALID [2022-02-21 04:24:56,893 INFO L290 TraceCheckUtils]: 14: Hoare triple {59441#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,893 INFO L290 TraceCheckUtils]: 15: Hoare triple {59441#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,893 INFO L290 TraceCheckUtils]: 16: Hoare triple {59441#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,893 INFO L290 TraceCheckUtils]: 17: Hoare triple {59441#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,893 INFO L290 TraceCheckUtils]: 18: Hoare triple {59441#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,893 INFO L290 TraceCheckUtils]: 19: Hoare triple {59441#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {59441#false} is VALID [2022-02-21 04:24:56,894 INFO L290 TraceCheckUtils]: 20: Hoare triple {59441#false} assume !(0 == ~M_E~0); {59441#false} is VALID [2022-02-21 04:24:56,894 INFO L290 TraceCheckUtils]: 21: Hoare triple {59441#false} assume !(0 == ~T1_E~0); {59441#false} is VALID [2022-02-21 04:24:56,894 INFO L290 TraceCheckUtils]: 22: Hoare triple {59441#false} assume !(0 == ~T2_E~0); {59441#false} is VALID [2022-02-21 04:24:56,894 INFO L290 TraceCheckUtils]: 23: Hoare triple {59441#false} assume !(0 == ~T3_E~0); {59441#false} is VALID [2022-02-21 04:24:56,894 INFO L290 TraceCheckUtils]: 24: Hoare triple {59441#false} assume !(0 == ~T4_E~0); {59441#false} is VALID [2022-02-21 04:24:56,894 INFO L290 TraceCheckUtils]: 25: Hoare triple {59441#false} assume !(0 == ~T5_E~0); {59441#false} is VALID [2022-02-21 04:24:56,894 INFO L290 TraceCheckUtils]: 26: Hoare triple {59441#false} assume !(0 == ~T6_E~0); {59441#false} is VALID [2022-02-21 04:24:56,895 INFO L290 TraceCheckUtils]: 27: Hoare triple {59441#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {59441#false} is VALID [2022-02-21 04:24:56,895 INFO L290 TraceCheckUtils]: 28: Hoare triple {59441#false} assume !(0 == ~T8_E~0); {59441#false} is VALID [2022-02-21 04:24:56,895 INFO L290 TraceCheckUtils]: 29: Hoare triple {59441#false} assume !(0 == ~T9_E~0); {59441#false} is VALID [2022-02-21 04:24:56,895 INFO L290 TraceCheckUtils]: 30: Hoare triple {59441#false} assume !(0 == ~T10_E~0); {59441#false} is VALID [2022-02-21 04:24:56,895 INFO L290 TraceCheckUtils]: 31: Hoare triple {59441#false} assume !(0 == ~T11_E~0); {59441#false} is VALID [2022-02-21 04:24:56,895 INFO L290 TraceCheckUtils]: 32: Hoare triple {59441#false} assume !(0 == ~T12_E~0); {59441#false} is VALID [2022-02-21 04:24:56,895 INFO L290 TraceCheckUtils]: 33: Hoare triple {59441#false} assume !(0 == ~T13_E~0); {59441#false} is VALID [2022-02-21 04:24:56,896 INFO L290 TraceCheckUtils]: 34: Hoare triple {59441#false} assume !(0 == ~T14_E~0); {59441#false} is VALID [2022-02-21 04:24:56,896 INFO L290 TraceCheckUtils]: 35: Hoare triple {59441#false} assume 0 == ~E_1~0;~E_1~0 := 1; {59441#false} is VALID [2022-02-21 04:24:56,896 INFO L290 TraceCheckUtils]: 36: Hoare triple {59441#false} assume !(0 == ~E_2~0); {59441#false} is VALID [2022-02-21 04:24:56,896 INFO L290 TraceCheckUtils]: 37: Hoare triple {59441#false} assume !(0 == ~E_3~0); {59441#false} is VALID [2022-02-21 04:24:56,896 INFO L290 TraceCheckUtils]: 38: Hoare triple {59441#false} assume !(0 == ~E_4~0); {59441#false} is VALID [2022-02-21 04:24:56,896 INFO L290 TraceCheckUtils]: 39: Hoare triple {59441#false} assume !(0 == ~E_5~0); {59441#false} is VALID [2022-02-21 04:24:56,896 INFO L290 TraceCheckUtils]: 40: Hoare triple {59441#false} assume !(0 == ~E_6~0); {59441#false} is VALID [2022-02-21 04:24:56,896 INFO L290 TraceCheckUtils]: 41: Hoare triple {59441#false} assume !(0 == ~E_7~0); {59441#false} is VALID [2022-02-21 04:24:56,897 INFO L290 TraceCheckUtils]: 42: Hoare triple {59441#false} assume !(0 == ~E_8~0); {59441#false} is VALID [2022-02-21 04:24:56,897 INFO L290 TraceCheckUtils]: 43: Hoare triple {59441#false} assume 0 == ~E_9~0;~E_9~0 := 1; {59441#false} is VALID [2022-02-21 04:24:56,897 INFO L290 TraceCheckUtils]: 44: Hoare triple {59441#false} assume !(0 == ~E_10~0); {59441#false} is VALID [2022-02-21 04:24:56,897 INFO L290 TraceCheckUtils]: 45: Hoare triple {59441#false} assume !(0 == ~E_11~0); {59441#false} is VALID [2022-02-21 04:24:56,897 INFO L290 TraceCheckUtils]: 46: Hoare triple {59441#false} assume !(0 == ~E_12~0); {59441#false} is VALID [2022-02-21 04:24:56,897 INFO L290 TraceCheckUtils]: 47: Hoare triple {59441#false} assume !(0 == ~E_13~0); {59441#false} is VALID [2022-02-21 04:24:56,897 INFO L290 TraceCheckUtils]: 48: Hoare triple {59441#false} assume !(0 == ~E_14~0); {59441#false} is VALID [2022-02-21 04:24:56,898 INFO L290 TraceCheckUtils]: 49: Hoare triple {59441#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {59441#false} is VALID [2022-02-21 04:24:56,898 INFO L290 TraceCheckUtils]: 50: Hoare triple {59441#false} assume 1 == ~m_pc~0; {59441#false} is VALID [2022-02-21 04:24:56,898 INFO L290 TraceCheckUtils]: 51: Hoare triple {59441#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {59441#false} is VALID [2022-02-21 04:24:56,898 INFO L290 TraceCheckUtils]: 52: Hoare triple {59441#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {59441#false} is VALID [2022-02-21 04:24:56,898 INFO L290 TraceCheckUtils]: 53: Hoare triple {59441#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {59441#false} is VALID [2022-02-21 04:24:56,898 INFO L290 TraceCheckUtils]: 54: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp~1#1); {59441#false} is VALID [2022-02-21 04:24:56,898 INFO L290 TraceCheckUtils]: 55: Hoare triple {59441#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {59441#false} is VALID [2022-02-21 04:24:56,899 INFO L290 TraceCheckUtils]: 56: Hoare triple {59441#false} assume !(1 == ~t1_pc~0); {59441#false} is VALID [2022-02-21 04:24:56,899 INFO L290 TraceCheckUtils]: 57: Hoare triple {59441#false} is_transmit1_triggered_~__retres1~1#1 := 0; {59441#false} is VALID [2022-02-21 04:24:56,899 INFO L290 TraceCheckUtils]: 58: Hoare triple {59441#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {59441#false} is VALID [2022-02-21 04:24:56,899 INFO L290 TraceCheckUtils]: 59: Hoare triple {59441#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {59441#false} is VALID [2022-02-21 04:24:56,899 INFO L290 TraceCheckUtils]: 60: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___0~0#1); {59441#false} is VALID [2022-02-21 04:24:56,899 INFO L290 TraceCheckUtils]: 61: Hoare triple {59441#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {59441#false} is VALID [2022-02-21 04:24:56,899 INFO L290 TraceCheckUtils]: 62: Hoare triple {59441#false} assume 1 == ~t2_pc~0; {59441#false} is VALID [2022-02-21 04:24:56,900 INFO L290 TraceCheckUtils]: 63: Hoare triple {59441#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {59441#false} is VALID [2022-02-21 04:24:56,900 INFO L290 TraceCheckUtils]: 64: Hoare triple {59441#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {59441#false} is VALID [2022-02-21 04:24:56,900 INFO L290 TraceCheckUtils]: 65: Hoare triple {59441#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {59441#false} is VALID [2022-02-21 04:24:56,900 INFO L290 TraceCheckUtils]: 66: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___1~0#1); {59441#false} is VALID [2022-02-21 04:24:56,900 INFO L290 TraceCheckUtils]: 67: Hoare triple {59441#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {59441#false} is VALID [2022-02-21 04:24:56,900 INFO L290 TraceCheckUtils]: 68: Hoare triple {59441#false} assume !(1 == ~t3_pc~0); {59441#false} is VALID [2022-02-21 04:24:56,900 INFO L290 TraceCheckUtils]: 69: Hoare triple {59441#false} is_transmit3_triggered_~__retres1~3#1 := 0; {59441#false} is VALID [2022-02-21 04:24:56,901 INFO L290 TraceCheckUtils]: 70: Hoare triple {59441#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {59441#false} is VALID [2022-02-21 04:24:56,901 INFO L290 TraceCheckUtils]: 71: Hoare triple {59441#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {59441#false} is VALID [2022-02-21 04:24:56,901 INFO L290 TraceCheckUtils]: 72: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___2~0#1); {59441#false} is VALID [2022-02-21 04:24:56,901 INFO L290 TraceCheckUtils]: 73: Hoare triple {59441#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {59441#false} is VALID [2022-02-21 04:24:56,901 INFO L290 TraceCheckUtils]: 74: Hoare triple {59441#false} assume 1 == ~t4_pc~0; {59441#false} is VALID [2022-02-21 04:24:56,901 INFO L290 TraceCheckUtils]: 75: Hoare triple {59441#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {59441#false} is VALID [2022-02-21 04:24:56,901 INFO L290 TraceCheckUtils]: 76: Hoare triple {59441#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {59441#false} is VALID [2022-02-21 04:24:56,902 INFO L290 TraceCheckUtils]: 77: Hoare triple {59441#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {59441#false} is VALID [2022-02-21 04:24:56,902 INFO L290 TraceCheckUtils]: 78: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___3~0#1); {59441#false} is VALID [2022-02-21 04:24:56,902 INFO L290 TraceCheckUtils]: 79: Hoare triple {59441#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {59441#false} is VALID [2022-02-21 04:24:56,902 INFO L290 TraceCheckUtils]: 80: Hoare triple {59441#false} assume 1 == ~t5_pc~0; {59441#false} is VALID [2022-02-21 04:24:56,902 INFO L290 TraceCheckUtils]: 81: Hoare triple {59441#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {59441#false} is VALID [2022-02-21 04:24:56,902 INFO L290 TraceCheckUtils]: 82: Hoare triple {59441#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {59441#false} is VALID [2022-02-21 04:24:56,902 INFO L290 TraceCheckUtils]: 83: Hoare triple {59441#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {59441#false} is VALID [2022-02-21 04:24:56,903 INFO L290 TraceCheckUtils]: 84: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___4~0#1); {59441#false} is VALID [2022-02-21 04:24:56,903 INFO L290 TraceCheckUtils]: 85: Hoare triple {59441#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {59441#false} is VALID [2022-02-21 04:24:56,903 INFO L290 TraceCheckUtils]: 86: Hoare triple {59441#false} assume !(1 == ~t6_pc~0); {59441#false} is VALID [2022-02-21 04:24:56,903 INFO L290 TraceCheckUtils]: 87: Hoare triple {59441#false} is_transmit6_triggered_~__retres1~6#1 := 0; {59441#false} is VALID [2022-02-21 04:24:56,903 INFO L290 TraceCheckUtils]: 88: Hoare triple {59441#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {59441#false} is VALID [2022-02-21 04:24:56,903 INFO L290 TraceCheckUtils]: 89: Hoare triple {59441#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {59441#false} is VALID [2022-02-21 04:24:56,903 INFO L290 TraceCheckUtils]: 90: Hoare triple {59441#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {59441#false} is VALID [2022-02-21 04:24:56,904 INFO L290 TraceCheckUtils]: 91: Hoare triple {59441#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {59441#false} is VALID [2022-02-21 04:24:56,904 INFO L290 TraceCheckUtils]: 92: Hoare triple {59441#false} assume 1 == ~t7_pc~0; {59441#false} is VALID [2022-02-21 04:24:56,904 INFO L290 TraceCheckUtils]: 93: Hoare triple {59441#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {59441#false} is VALID [2022-02-21 04:24:56,904 INFO L290 TraceCheckUtils]: 94: Hoare triple {59441#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {59441#false} is VALID [2022-02-21 04:24:56,904 INFO L290 TraceCheckUtils]: 95: Hoare triple {59441#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {59441#false} is VALID [2022-02-21 04:24:56,904 INFO L290 TraceCheckUtils]: 96: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___6~0#1); {59441#false} is VALID [2022-02-21 04:24:56,904 INFO L290 TraceCheckUtils]: 97: Hoare triple {59441#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {59441#false} is VALID [2022-02-21 04:24:56,905 INFO L290 TraceCheckUtils]: 98: Hoare triple {59441#false} assume !(1 == ~t8_pc~0); {59441#false} is VALID [2022-02-21 04:24:56,905 INFO L290 TraceCheckUtils]: 99: Hoare triple {59441#false} is_transmit8_triggered_~__retres1~8#1 := 0; {59441#false} is VALID [2022-02-21 04:24:56,905 INFO L290 TraceCheckUtils]: 100: Hoare triple {59441#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {59441#false} is VALID [2022-02-21 04:24:56,905 INFO L290 TraceCheckUtils]: 101: Hoare triple {59441#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {59441#false} is VALID [2022-02-21 04:24:56,905 INFO L290 TraceCheckUtils]: 102: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___7~0#1); {59441#false} is VALID [2022-02-21 04:24:56,905 INFO L290 TraceCheckUtils]: 103: Hoare triple {59441#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {59441#false} is VALID [2022-02-21 04:24:56,905 INFO L290 TraceCheckUtils]: 104: Hoare triple {59441#false} assume 1 == ~t9_pc~0; {59441#false} is VALID [2022-02-21 04:24:56,906 INFO L290 TraceCheckUtils]: 105: Hoare triple {59441#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {59441#false} is VALID [2022-02-21 04:24:56,906 INFO L290 TraceCheckUtils]: 106: Hoare triple {59441#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {59441#false} is VALID [2022-02-21 04:24:56,906 INFO L290 TraceCheckUtils]: 107: Hoare triple {59441#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {59441#false} is VALID [2022-02-21 04:24:56,906 INFO L290 TraceCheckUtils]: 108: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___8~0#1); {59441#false} is VALID [2022-02-21 04:24:56,906 INFO L290 TraceCheckUtils]: 109: Hoare triple {59441#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {59441#false} is VALID [2022-02-21 04:24:56,906 INFO L290 TraceCheckUtils]: 110: Hoare triple {59441#false} assume !(1 == ~t10_pc~0); {59441#false} is VALID [2022-02-21 04:24:56,906 INFO L290 TraceCheckUtils]: 111: Hoare triple {59441#false} is_transmit10_triggered_~__retres1~10#1 := 0; {59441#false} is VALID [2022-02-21 04:24:56,907 INFO L290 TraceCheckUtils]: 112: Hoare triple {59441#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {59441#false} is VALID [2022-02-21 04:24:56,907 INFO L290 TraceCheckUtils]: 113: Hoare triple {59441#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {59441#false} is VALID [2022-02-21 04:24:56,907 INFO L290 TraceCheckUtils]: 114: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___9~0#1); {59441#false} is VALID [2022-02-21 04:24:56,907 INFO L290 TraceCheckUtils]: 115: Hoare triple {59441#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {59441#false} is VALID [2022-02-21 04:24:56,907 INFO L290 TraceCheckUtils]: 116: Hoare triple {59441#false} assume 1 == ~t11_pc~0; {59441#false} is VALID [2022-02-21 04:24:56,907 INFO L290 TraceCheckUtils]: 117: Hoare triple {59441#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {59441#false} is VALID [2022-02-21 04:24:56,907 INFO L290 TraceCheckUtils]: 118: Hoare triple {59441#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {59441#false} is VALID [2022-02-21 04:24:56,908 INFO L290 TraceCheckUtils]: 119: Hoare triple {59441#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {59441#false} is VALID [2022-02-21 04:24:56,908 INFO L290 TraceCheckUtils]: 120: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___10~0#1); {59441#false} is VALID [2022-02-21 04:24:56,908 INFO L290 TraceCheckUtils]: 121: Hoare triple {59441#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {59441#false} is VALID [2022-02-21 04:24:56,908 INFO L290 TraceCheckUtils]: 122: Hoare triple {59441#false} assume !(1 == ~t12_pc~0); {59441#false} is VALID [2022-02-21 04:24:56,908 INFO L290 TraceCheckUtils]: 123: Hoare triple {59441#false} is_transmit12_triggered_~__retres1~12#1 := 0; {59441#false} is VALID [2022-02-21 04:24:56,908 INFO L290 TraceCheckUtils]: 124: Hoare triple {59441#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {59441#false} is VALID [2022-02-21 04:24:56,908 INFO L290 TraceCheckUtils]: 125: Hoare triple {59441#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {59441#false} is VALID [2022-02-21 04:24:56,909 INFO L290 TraceCheckUtils]: 126: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___11~0#1); {59441#false} is VALID [2022-02-21 04:24:56,909 INFO L290 TraceCheckUtils]: 127: Hoare triple {59441#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {59441#false} is VALID [2022-02-21 04:24:56,909 INFO L290 TraceCheckUtils]: 128: Hoare triple {59441#false} assume 1 == ~t13_pc~0; {59441#false} is VALID [2022-02-21 04:24:56,909 INFO L290 TraceCheckUtils]: 129: Hoare triple {59441#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {59441#false} is VALID [2022-02-21 04:24:56,909 INFO L290 TraceCheckUtils]: 130: Hoare triple {59441#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {59441#false} is VALID [2022-02-21 04:24:56,909 INFO L290 TraceCheckUtils]: 131: Hoare triple {59441#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {59441#false} is VALID [2022-02-21 04:24:56,909 INFO L290 TraceCheckUtils]: 132: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___12~0#1); {59441#false} is VALID [2022-02-21 04:24:56,910 INFO L290 TraceCheckUtils]: 133: Hoare triple {59441#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {59441#false} is VALID [2022-02-21 04:24:56,910 INFO L290 TraceCheckUtils]: 134: Hoare triple {59441#false} assume 1 == ~t14_pc~0; {59441#false} is VALID [2022-02-21 04:24:56,910 INFO L290 TraceCheckUtils]: 135: Hoare triple {59441#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {59441#false} is VALID [2022-02-21 04:24:56,910 INFO L290 TraceCheckUtils]: 136: Hoare triple {59441#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {59441#false} is VALID [2022-02-21 04:24:56,910 INFO L290 TraceCheckUtils]: 137: Hoare triple {59441#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {59441#false} is VALID [2022-02-21 04:24:56,910 INFO L290 TraceCheckUtils]: 138: Hoare triple {59441#false} assume !(0 != activate_threads_~tmp___13~0#1); {59441#false} is VALID [2022-02-21 04:24:56,910 INFO L290 TraceCheckUtils]: 139: Hoare triple {59441#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {59441#false} is VALID [2022-02-21 04:24:56,911 INFO L290 TraceCheckUtils]: 140: Hoare triple {59441#false} assume 1 == ~M_E~0;~M_E~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,911 INFO L290 TraceCheckUtils]: 141: Hoare triple {59441#false} assume !(1 == ~T1_E~0); {59441#false} is VALID [2022-02-21 04:24:56,911 INFO L290 TraceCheckUtils]: 142: Hoare triple {59441#false} assume !(1 == ~T2_E~0); {59441#false} is VALID [2022-02-21 04:24:56,911 INFO L290 TraceCheckUtils]: 143: Hoare triple {59441#false} assume !(1 == ~T3_E~0); {59441#false} is VALID [2022-02-21 04:24:56,911 INFO L290 TraceCheckUtils]: 144: Hoare triple {59441#false} assume !(1 == ~T4_E~0); {59441#false} is VALID [2022-02-21 04:24:56,911 INFO L290 TraceCheckUtils]: 145: Hoare triple {59441#false} assume !(1 == ~T5_E~0); {59441#false} is VALID [2022-02-21 04:24:56,911 INFO L290 TraceCheckUtils]: 146: Hoare triple {59441#false} assume !(1 == ~T6_E~0); {59441#false} is VALID [2022-02-21 04:24:56,912 INFO L290 TraceCheckUtils]: 147: Hoare triple {59441#false} assume !(1 == ~T7_E~0); {59441#false} is VALID [2022-02-21 04:24:56,912 INFO L290 TraceCheckUtils]: 148: Hoare triple {59441#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,912 INFO L290 TraceCheckUtils]: 149: Hoare triple {59441#false} assume !(1 == ~T9_E~0); {59441#false} is VALID [2022-02-21 04:24:56,912 INFO L290 TraceCheckUtils]: 150: Hoare triple {59441#false} assume !(1 == ~T10_E~0); {59441#false} is VALID [2022-02-21 04:24:56,912 INFO L290 TraceCheckUtils]: 151: Hoare triple {59441#false} assume !(1 == ~T11_E~0); {59441#false} is VALID [2022-02-21 04:24:56,912 INFO L290 TraceCheckUtils]: 152: Hoare triple {59441#false} assume !(1 == ~T12_E~0); {59441#false} is VALID [2022-02-21 04:24:56,912 INFO L290 TraceCheckUtils]: 153: Hoare triple {59441#false} assume !(1 == ~T13_E~0); {59441#false} is VALID [2022-02-21 04:24:56,913 INFO L290 TraceCheckUtils]: 154: Hoare triple {59441#false} assume !(1 == ~T14_E~0); {59441#false} is VALID [2022-02-21 04:24:56,913 INFO L290 TraceCheckUtils]: 155: Hoare triple {59441#false} assume !(1 == ~E_1~0); {59441#false} is VALID [2022-02-21 04:24:56,913 INFO L290 TraceCheckUtils]: 156: Hoare triple {59441#false} assume 1 == ~E_2~0;~E_2~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,913 INFO L290 TraceCheckUtils]: 157: Hoare triple {59441#false} assume !(1 == ~E_3~0); {59441#false} is VALID [2022-02-21 04:24:56,913 INFO L290 TraceCheckUtils]: 158: Hoare triple {59441#false} assume !(1 == ~E_4~0); {59441#false} is VALID [2022-02-21 04:24:56,913 INFO L290 TraceCheckUtils]: 159: Hoare triple {59441#false} assume !(1 == ~E_5~0); {59441#false} is VALID [2022-02-21 04:24:56,913 INFO L290 TraceCheckUtils]: 160: Hoare triple {59441#false} assume !(1 == ~E_6~0); {59441#false} is VALID [2022-02-21 04:24:56,914 INFO L290 TraceCheckUtils]: 161: Hoare triple {59441#false} assume !(1 == ~E_7~0); {59441#false} is VALID [2022-02-21 04:24:56,914 INFO L290 TraceCheckUtils]: 162: Hoare triple {59441#false} assume !(1 == ~E_8~0); {59441#false} is VALID [2022-02-21 04:24:56,914 INFO L290 TraceCheckUtils]: 163: Hoare triple {59441#false} assume !(1 == ~E_9~0); {59441#false} is VALID [2022-02-21 04:24:56,914 INFO L290 TraceCheckUtils]: 164: Hoare triple {59441#false} assume 1 == ~E_10~0;~E_10~0 := 2; {59441#false} is VALID [2022-02-21 04:24:56,914 INFO L290 TraceCheckUtils]: 165: Hoare triple {59441#false} assume !(1 == ~E_11~0); {59441#false} is VALID [2022-02-21 04:24:56,914 INFO L290 TraceCheckUtils]: 166: Hoare triple {59441#false} assume !(1 == ~E_12~0); {59441#false} is VALID [2022-02-21 04:24:56,914 INFO L290 TraceCheckUtils]: 167: Hoare triple {59441#false} assume !(1 == ~E_13~0); {59441#false} is VALID [2022-02-21 04:24:56,915 INFO L290 TraceCheckUtils]: 168: Hoare triple {59441#false} assume !(1 == ~E_14~0); {59441#false} is VALID [2022-02-21 04:24:56,915 INFO L290 TraceCheckUtils]: 169: Hoare triple {59441#false} assume { :end_inline_reset_delta_events } true; {59441#false} is VALID [2022-02-21 04:24:56,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:56,915 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:56,916 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529937849] [2022-02-21 04:24:56,916 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529937849] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:56,916 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:56,916 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:56,916 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069585854] [2022-02-21 04:24:56,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:56,917 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:56,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:56,917 INFO L85 PathProgramCache]: Analyzing trace with hash 1991472556, now seen corresponding path program 1 times [2022-02-21 04:24:56,918 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:56,918 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66869067] [2022-02-21 04:24:56,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:56,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:56,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:56,952 INFO L290 TraceCheckUtils]: 0: Hoare triple {59443#true} assume !false; {59443#true} is VALID [2022-02-21 04:24:56,952 INFO L290 TraceCheckUtils]: 1: Hoare triple {59443#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {59443#true} is VALID [2022-02-21 04:24:56,953 INFO L290 TraceCheckUtils]: 2: Hoare triple {59443#true} assume !false; {59443#true} is VALID [2022-02-21 04:24:56,953 INFO L290 TraceCheckUtils]: 3: Hoare triple {59443#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {59443#true} is VALID [2022-02-21 04:24:56,953 INFO L290 TraceCheckUtils]: 4: Hoare triple {59443#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {59443#true} is VALID [2022-02-21 04:24:56,953 INFO L290 TraceCheckUtils]: 5: Hoare triple {59443#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {59443#true} is VALID [2022-02-21 04:24:56,953 INFO L290 TraceCheckUtils]: 6: Hoare triple {59443#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {59443#true} is VALID [2022-02-21 04:24:56,953 INFO L290 TraceCheckUtils]: 7: Hoare triple {59443#true} assume !(0 != eval_~tmp~0#1); {59443#true} is VALID [2022-02-21 04:24:56,953 INFO L290 TraceCheckUtils]: 8: Hoare triple {59443#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {59443#true} is VALID [2022-02-21 04:24:56,954 INFO L290 TraceCheckUtils]: 9: Hoare triple {59443#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {59443#true} is VALID [2022-02-21 04:24:56,954 INFO L290 TraceCheckUtils]: 10: Hoare triple {59443#true} assume 0 == ~M_E~0;~M_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,954 INFO L290 TraceCheckUtils]: 11: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,955 INFO L290 TraceCheckUtils]: 12: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,955 INFO L290 TraceCheckUtils]: 13: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,955 INFO L290 TraceCheckUtils]: 14: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,956 INFO L290 TraceCheckUtils]: 15: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,956 INFO L290 TraceCheckUtils]: 16: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,956 INFO L290 TraceCheckUtils]: 17: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,956 INFO L290 TraceCheckUtils]: 18: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,957 INFO L290 TraceCheckUtils]: 19: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,957 INFO L290 TraceCheckUtils]: 20: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,957 INFO L290 TraceCheckUtils]: 21: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,958 INFO L290 TraceCheckUtils]: 22: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,958 INFO L290 TraceCheckUtils]: 23: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,958 INFO L290 TraceCheckUtils]: 24: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,959 INFO L290 TraceCheckUtils]: 25: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,959 INFO L290 TraceCheckUtils]: 26: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,959 INFO L290 TraceCheckUtils]: 27: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,960 INFO L290 TraceCheckUtils]: 28: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,960 INFO L290 TraceCheckUtils]: 29: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,960 INFO L290 TraceCheckUtils]: 30: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,961 INFO L290 TraceCheckUtils]: 31: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,961 INFO L290 TraceCheckUtils]: 32: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,961 INFO L290 TraceCheckUtils]: 33: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,961 INFO L290 TraceCheckUtils]: 34: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,962 INFO L290 TraceCheckUtils]: 35: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,962 INFO L290 TraceCheckUtils]: 36: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,962 INFO L290 TraceCheckUtils]: 37: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,963 INFO L290 TraceCheckUtils]: 38: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,963 INFO L290 TraceCheckUtils]: 39: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,963 INFO L290 TraceCheckUtils]: 40: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,964 INFO L290 TraceCheckUtils]: 41: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,964 INFO L290 TraceCheckUtils]: 42: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,964 INFO L290 TraceCheckUtils]: 43: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,965 INFO L290 TraceCheckUtils]: 44: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,965 INFO L290 TraceCheckUtils]: 45: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,965 INFO L290 TraceCheckUtils]: 46: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,965 INFO L290 TraceCheckUtils]: 47: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,966 INFO L290 TraceCheckUtils]: 48: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,966 INFO L290 TraceCheckUtils]: 49: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,966 INFO L290 TraceCheckUtils]: 50: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,967 INFO L290 TraceCheckUtils]: 51: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,967 INFO L290 TraceCheckUtils]: 52: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,967 INFO L290 TraceCheckUtils]: 53: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,968 INFO L290 TraceCheckUtils]: 54: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,968 INFO L290 TraceCheckUtils]: 55: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,968 INFO L290 TraceCheckUtils]: 56: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,969 INFO L290 TraceCheckUtils]: 57: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,969 INFO L290 TraceCheckUtils]: 58: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,969 INFO L290 TraceCheckUtils]: 59: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,970 INFO L290 TraceCheckUtils]: 60: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,970 INFO L290 TraceCheckUtils]: 61: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,970 INFO L290 TraceCheckUtils]: 62: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,970 INFO L290 TraceCheckUtils]: 63: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,971 INFO L290 TraceCheckUtils]: 64: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,971 INFO L290 TraceCheckUtils]: 65: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,971 INFO L290 TraceCheckUtils]: 66: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,972 INFO L290 TraceCheckUtils]: 67: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,972 INFO L290 TraceCheckUtils]: 68: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,972 INFO L290 TraceCheckUtils]: 69: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,973 INFO L290 TraceCheckUtils]: 70: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,973 INFO L290 TraceCheckUtils]: 71: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,973 INFO L290 TraceCheckUtils]: 72: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,974 INFO L290 TraceCheckUtils]: 73: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,974 INFO L290 TraceCheckUtils]: 74: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,974 INFO L290 TraceCheckUtils]: 75: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,975 INFO L290 TraceCheckUtils]: 76: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,975 INFO L290 TraceCheckUtils]: 77: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,975 INFO L290 TraceCheckUtils]: 78: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,976 INFO L290 TraceCheckUtils]: 79: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,976 INFO L290 TraceCheckUtils]: 80: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,976 INFO L290 TraceCheckUtils]: 81: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,976 INFO L290 TraceCheckUtils]: 82: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,977 INFO L290 TraceCheckUtils]: 83: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,977 INFO L290 TraceCheckUtils]: 84: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,977 INFO L290 TraceCheckUtils]: 85: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,978 INFO L290 TraceCheckUtils]: 86: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,978 INFO L290 TraceCheckUtils]: 87: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,978 INFO L290 TraceCheckUtils]: 88: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,979 INFO L290 TraceCheckUtils]: 89: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,979 INFO L290 TraceCheckUtils]: 90: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,979 INFO L290 TraceCheckUtils]: 91: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,980 INFO L290 TraceCheckUtils]: 92: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,980 INFO L290 TraceCheckUtils]: 93: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,980 INFO L290 TraceCheckUtils]: 94: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,981 INFO L290 TraceCheckUtils]: 95: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,981 INFO L290 TraceCheckUtils]: 96: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,981 INFO L290 TraceCheckUtils]: 97: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,981 INFO L290 TraceCheckUtils]: 98: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,982 INFO L290 TraceCheckUtils]: 99: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,982 INFO L290 TraceCheckUtils]: 100: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,993 INFO L290 TraceCheckUtils]: 101: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,993 INFO L290 TraceCheckUtils]: 102: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,993 INFO L290 TraceCheckUtils]: 103: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,994 INFO L290 TraceCheckUtils]: 104: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,994 INFO L290 TraceCheckUtils]: 105: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,994 INFO L290 TraceCheckUtils]: 106: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,995 INFO L290 TraceCheckUtils]: 107: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,995 INFO L290 TraceCheckUtils]: 108: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,995 INFO L290 TraceCheckUtils]: 109: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,996 INFO L290 TraceCheckUtils]: 110: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,996 INFO L290 TraceCheckUtils]: 111: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,996 INFO L290 TraceCheckUtils]: 112: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,997 INFO L290 TraceCheckUtils]: 113: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,997 INFO L290 TraceCheckUtils]: 114: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,997 INFO L290 TraceCheckUtils]: 115: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,998 INFO L290 TraceCheckUtils]: 116: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,998 INFO L290 TraceCheckUtils]: 117: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,998 INFO L290 TraceCheckUtils]: 118: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,999 INFO L290 TraceCheckUtils]: 119: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,999 INFO L290 TraceCheckUtils]: 120: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,999 INFO L290 TraceCheckUtils]: 121: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:56,999 INFO L290 TraceCheckUtils]: 122: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:57,000 INFO L290 TraceCheckUtils]: 123: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:57,000 INFO L290 TraceCheckUtils]: 124: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:57,000 INFO L290 TraceCheckUtils]: 125: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:57,001 INFO L290 TraceCheckUtils]: 126: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:57,001 INFO L290 TraceCheckUtils]: 127: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:57,001 INFO L290 TraceCheckUtils]: 128: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:57,002 INFO L290 TraceCheckUtils]: 129: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {59445#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:57,002 INFO L290 TraceCheckUtils]: 130: Hoare triple {59445#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {59444#false} is VALID [2022-02-21 04:24:57,002 INFO L290 TraceCheckUtils]: 131: Hoare triple {59444#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,002 INFO L290 TraceCheckUtils]: 132: Hoare triple {59444#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,002 INFO L290 TraceCheckUtils]: 133: Hoare triple {59444#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,003 INFO L290 TraceCheckUtils]: 134: Hoare triple {59444#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,003 INFO L290 TraceCheckUtils]: 135: Hoare triple {59444#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,003 INFO L290 TraceCheckUtils]: 136: Hoare triple {59444#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,003 INFO L290 TraceCheckUtils]: 137: Hoare triple {59444#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,003 INFO L290 TraceCheckUtils]: 138: Hoare triple {59444#false} assume !(1 == ~T8_E~0); {59444#false} is VALID [2022-02-21 04:24:57,003 INFO L290 TraceCheckUtils]: 139: Hoare triple {59444#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,003 INFO L290 TraceCheckUtils]: 140: Hoare triple {59444#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,004 INFO L290 TraceCheckUtils]: 141: Hoare triple {59444#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,004 INFO L290 TraceCheckUtils]: 142: Hoare triple {59444#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,004 INFO L290 TraceCheckUtils]: 143: Hoare triple {59444#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,004 INFO L290 TraceCheckUtils]: 144: Hoare triple {59444#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,004 INFO L290 TraceCheckUtils]: 145: Hoare triple {59444#false} assume 1 == ~E_1~0;~E_1~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,004 INFO L290 TraceCheckUtils]: 146: Hoare triple {59444#false} assume !(1 == ~E_2~0); {59444#false} is VALID [2022-02-21 04:24:57,004 INFO L290 TraceCheckUtils]: 147: Hoare triple {59444#false} assume 1 == ~E_3~0;~E_3~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,005 INFO L290 TraceCheckUtils]: 148: Hoare triple {59444#false} assume 1 == ~E_4~0;~E_4~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,005 INFO L290 TraceCheckUtils]: 149: Hoare triple {59444#false} assume 1 == ~E_5~0;~E_5~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,005 INFO L290 TraceCheckUtils]: 150: Hoare triple {59444#false} assume 1 == ~E_6~0;~E_6~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,005 INFO L290 TraceCheckUtils]: 151: Hoare triple {59444#false} assume 1 == ~E_7~0;~E_7~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,005 INFO L290 TraceCheckUtils]: 152: Hoare triple {59444#false} assume 1 == ~E_8~0;~E_8~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,005 INFO L290 TraceCheckUtils]: 153: Hoare triple {59444#false} assume 1 == ~E_9~0;~E_9~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,005 INFO L290 TraceCheckUtils]: 154: Hoare triple {59444#false} assume !(1 == ~E_10~0); {59444#false} is VALID [2022-02-21 04:24:57,006 INFO L290 TraceCheckUtils]: 155: Hoare triple {59444#false} assume 1 == ~E_11~0;~E_11~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,006 INFO L290 TraceCheckUtils]: 156: Hoare triple {59444#false} assume 1 == ~E_12~0;~E_12~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,006 INFO L290 TraceCheckUtils]: 157: Hoare triple {59444#false} assume 1 == ~E_13~0;~E_13~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,006 INFO L290 TraceCheckUtils]: 158: Hoare triple {59444#false} assume 1 == ~E_14~0;~E_14~0 := 2; {59444#false} is VALID [2022-02-21 04:24:57,006 INFO L290 TraceCheckUtils]: 159: Hoare triple {59444#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {59444#false} is VALID [2022-02-21 04:24:57,006 INFO L290 TraceCheckUtils]: 160: Hoare triple {59444#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {59444#false} is VALID [2022-02-21 04:24:57,006 INFO L290 TraceCheckUtils]: 161: Hoare triple {59444#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {59444#false} is VALID [2022-02-21 04:24:57,007 INFO L290 TraceCheckUtils]: 162: Hoare triple {59444#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {59444#false} is VALID [2022-02-21 04:24:57,007 INFO L290 TraceCheckUtils]: 163: Hoare triple {59444#false} assume !(0 == start_simulation_~tmp~3#1); {59444#false} is VALID [2022-02-21 04:24:57,007 INFO L290 TraceCheckUtils]: 164: Hoare triple {59444#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {59444#false} is VALID [2022-02-21 04:24:57,007 INFO L290 TraceCheckUtils]: 165: Hoare triple {59444#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {59444#false} is VALID [2022-02-21 04:24:57,007 INFO L290 TraceCheckUtils]: 166: Hoare triple {59444#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {59444#false} is VALID [2022-02-21 04:24:57,007 INFO L290 TraceCheckUtils]: 167: Hoare triple {59444#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {59444#false} is VALID [2022-02-21 04:24:57,007 INFO L290 TraceCheckUtils]: 168: Hoare triple {59444#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {59444#false} is VALID [2022-02-21 04:24:57,008 INFO L290 TraceCheckUtils]: 169: Hoare triple {59444#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {59444#false} is VALID [2022-02-21 04:24:57,008 INFO L290 TraceCheckUtils]: 170: Hoare triple {59444#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {59444#false} is VALID [2022-02-21 04:24:57,008 INFO L290 TraceCheckUtils]: 171: Hoare triple {59444#false} assume !(0 != start_simulation_~tmp___0~1#1); {59444#false} is VALID [2022-02-21 04:24:57,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:57,009 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:57,009 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66869067] [2022-02-21 04:24:57,009 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [66869067] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:57,009 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:57,009 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:57,010 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383078905] [2022-02-21 04:24:57,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:57,010 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:57,010 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:57,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:57,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:57,011 INFO L87 Difference]: Start difference. First operand 2047 states and 3028 transitions. cyclomatic complexity: 982 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:58,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:58,169 INFO L93 Difference]: Finished difference Result 2047 states and 3027 transitions. [2022-02-21 04:24:58,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:58,170 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:58,227 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:58,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3027 transitions. [2022-02-21 04:24:58,333 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:58,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3027 transitions. [2022-02-21 04:24:58,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:24:58,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:24:58,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3027 transitions. [2022-02-21 04:24:58,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:58,442 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2022-02-21 04:24:58,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3027 transitions. [2022-02-21 04:24:58,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:24:58,461 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:58,463 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3027 transitions. Second operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:58,465 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3027 transitions. Second operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:58,467 INFO L87 Difference]: Start difference. First operand 2047 states and 3027 transitions. Second operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:58,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:58,559 INFO L93 Difference]: Finished difference Result 2047 states and 3027 transitions. [2022-02-21 04:24:58,559 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3027 transitions. [2022-02-21 04:24:58,560 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:58,561 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:58,563 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3027 transitions. [2022-02-21 04:24:58,564 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3027 transitions. [2022-02-21 04:24:58,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:58,650 INFO L93 Difference]: Finished difference Result 2047 states and 3027 transitions. [2022-02-21 04:24:58,650 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3027 transitions. [2022-02-21 04:24:58,652 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:58,652 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:58,652 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:58,652 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:58,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:58,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3027 transitions. [2022-02-21 04:24:58,740 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2022-02-21 04:24:58,740 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2022-02-21 04:24:58,740 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:58,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3027 transitions. [2022-02-21 04:24:58,743 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:24:58,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:58,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:58,745 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:58,745 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:58,745 INFO L791 eck$LassoCheckResult]: Stem: 62419#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 62420#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 63022#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62139#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62140#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 62385#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62386#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62113#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62114#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63337#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62689#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62690#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63207#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 62599#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62600#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 62020#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 62021#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 62352#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 62550#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 61597#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61598#L1342 assume !(0 == ~M_E~0); 61763#L1342-2 assume !(0 == ~T1_E~0); 62319#L1347-1 assume !(0 == ~T2_E~0); 63320#L1352-1 assume !(0 == ~T3_E~0); 63116#L1357-1 assume !(0 == ~T4_E~0); 62344#L1362-1 assume !(0 == ~T5_E~0); 62345#L1367-1 assume !(0 == ~T6_E~0); 61942#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61943#L1377-1 assume !(0 == ~T8_E~0); 62273#L1382-1 assume !(0 == ~T9_E~0); 62274#L1387-1 assume !(0 == ~T10_E~0); 63001#L1392-1 assume !(0 == ~T11_E~0); 62305#L1397-1 assume !(0 == ~T12_E~0); 62306#L1402-1 assume !(0 == ~T13_E~0); 61958#L1407-1 assume !(0 == ~T14_E~0); 61959#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 63237#L1417-1 assume !(0 == ~E_2~0); 63238#L1422-1 assume !(0 == ~E_3~0); 63479#L1427-1 assume !(0 == ~E_4~0); 62146#L1432-1 assume !(0 == ~E_5~0); 62147#L1437-1 assume !(0 == ~E_6~0); 63155#L1442-1 assume !(0 == ~E_7~0); 63156#L1447-1 assume !(0 == ~E_8~0); 62998#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 61733#L1457-1 assume !(0 == ~E_10~0); 61734#L1462-1 assume !(0 == ~E_11~0); 63190#L1467-1 assume !(0 == ~E_12~0); 63202#L1472-1 assume !(0 == ~E_13~0); 63203#L1477-1 assume !(0 == ~E_14~0); 62945#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61932#L646 assume 1 == ~m_pc~0; 61933#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 62609#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62624#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62022#L1666 assume !(0 != activate_threads_~tmp~1#1); 62023#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63500#L665 assume !(1 == ~t1_pc~0); 62498#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62499#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62031#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62032#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 62822#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62823#L684 assume 1 == ~t2_pc~0; 62940#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62864#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62929#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63324#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 63325#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63513#L703 assume !(1 == ~t3_pc~0); 62168#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62169#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62815#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61567#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 61568#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62053#L722 assume 1 == ~t4_pc~0; 62791#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62234#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62579#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63139#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 62646#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61764#L741 assume 1 == ~t5_pc~0; 61765#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62075#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62229#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62230#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 62909#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62320#L760 assume !(1 == ~t6_pc~0); 62167#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 62166#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62024#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62025#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62746#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62747#L779 assume 1 == ~t7_pc~0; 61809#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61655#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61656#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62064#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 62087#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62088#L798 assume !(1 == ~t8_pc~0); 63369#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 63292#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61811#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61812#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 63502#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61632#L817 assume 1 == ~t9_pc~0; 61633#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62427#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62428#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62950#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 62038#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62039#L836 assume !(1 == ~t10_pc~0); 62055#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 61986#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61987#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62235#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 62236#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63302#L855 assume 1 == ~t11_pc~0; 62620#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62621#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63185#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62994#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 62829#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61928#L874 assume !(1 == ~t12_pc~0); 61929#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62096#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62097#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 62237#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 61605#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61606#L893 assume 1 == ~t13_pc~0; 63436#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 61961#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 62272#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 63363#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 63371#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 63372#L912 assume 1 == ~t14_pc~0; 63162#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 63163#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 61931#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 61863#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 61864#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62639#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 63055#L1495-2 assume !(1 == ~T1_E~0); 63056#L1500-1 assume !(1 == ~T2_E~0); 62742#L1505-1 assume !(1 == ~T3_E~0); 62743#L1510-1 assume !(1 == ~T4_E~0); 62800#L1515-1 assume !(1 == ~T5_E~0); 62801#L1520-1 assume !(1 == ~T6_E~0); 63370#L1525-1 assume !(1 == ~T7_E~0); 63080#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62033#L1535-1 assume !(1 == ~T9_E~0); 62034#L1540-1 assume !(1 == ~T10_E~0); 61526#L1545-1 assume !(1 == ~T11_E~0); 61527#L1550-1 assume !(1 == ~T12_E~0); 61775#L1555-1 assume !(1 == ~T13_E~0); 61776#L1560-1 assume !(1 == ~T14_E~0); 62076#L1565-1 assume !(1 == ~E_1~0); 63489#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 62967#L1575-1 assume !(1 == ~E_3~0); 62346#L1580-1 assume !(1 == ~E_4~0); 62347#L1585-1 assume !(1 == ~E_5~0); 62817#L1590-1 assume !(1 == ~E_6~0); 62381#L1595-1 assume !(1 == ~E_7~0); 62382#L1600-1 assume !(1 == ~E_8~0); 62754#L1605-1 assume !(1 == ~E_9~0); 62755#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 63272#L1615-1 assume !(1 == ~E_11~0); 62211#L1620-1 assume !(1 == ~E_12~0); 62212#L1625-1 assume !(1 == ~E_13~0); 62999#L1630-1 assume !(1 == ~E_14~0); 62380#L1635-1 assume { :end_inline_reset_delta_events } true; 62321#L2017-2 [2022-02-21 04:24:58,746 INFO L793 eck$LassoCheckResult]: Loop: 62321#L2017-2 assume !false; 61601#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61602#L1316 assume !false; 62930#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 62992#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 61539#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 61681#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 61682#L1115 assume !(0 != eval_~tmp~0#1); 63015#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 62436#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 62437#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62619#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 63120#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62789#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62790#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63352#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63527#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 63522#L1372-3 assume !(0 == ~T7_E~0); 61583#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 61584#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62253#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62254#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 63165#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 63475#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62733#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 61889#L1412-3 assume !(0 == ~E_1~0); 61890#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62654#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62655#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 63349#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 63036#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62748#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62749#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61649#L1452-3 assume !(0 == ~E_9~0); 61650#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 63288#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 63289#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 63093#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 63094#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 61887#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61888#L646-42 assume 1 == ~m_pc~0; 62473#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 63321#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63322#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63460#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 63461#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63253#L665-42 assume 1 == ~t1_pc~0; 63214#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 63216#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63402#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62056#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62057#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63526#L684-42 assume 1 == ~t2_pc~0; 62905#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62906#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63516#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62685#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62686#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62808#L703-42 assume !(1 == ~t3_pc~0); 63008#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 63007#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62325#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62326#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 63100#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62720#L722-42 assume 1 == ~t4_pc~0; 62721#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63131#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62374#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62201#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62202#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63496#L741-42 assume !(1 == ~t5_pc~0); 63113#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 62583#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62584#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63529#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62491#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62492#L760-42 assume !(1 == ~t6_pc~0); 62626#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 62761#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62762#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63150#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 62443#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62444#L779-42 assume !(1 == ~t7_pc~0); 63220#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 63221#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62130#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62131#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 61984#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61985#L798-42 assume 1 == ~t8_pc~0; 62435#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61596#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63339#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62785#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61815#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61816#L817-42 assume 1 == ~t9_pc~0; 62589#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62099#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62100#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62226#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 63031#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 63032#L836-42 assume 1 == ~t10_pc~0; 63124#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 62137#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62138#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63439#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63440#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63481#L855-42 assume 1 == ~t11_pc~0; 63494#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61688#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61689#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62438#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 63201#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62302#L874-42 assume !(1 == ~t12_pc~0); 62304#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 62545#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61603#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61604#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61857#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61858#L893-42 assume 1 == ~t13_pc~0; 63061#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 62842#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 62857#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 62759#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 62231#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 62232#L912-42 assume !(1 == ~t14_pc~0); 63041#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 61549#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 61550#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 63130#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 61977#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61978#L1495-3 assume !(1 == ~M_E~0); 62593#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63021#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63114#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62207#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62170#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62171#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62828#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63051#L1530-3 assume !(1 == ~T8_E~0); 62016#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62017#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62054#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 63311#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 63420#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 62460#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 62461#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63076#L1570-3 assume !(1 == ~E_2~0); 63027#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 63028#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63383#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63427#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63473#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 62850#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62851#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 63326#L1610-3 assume !(1 == ~E_10~0); 62213#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 62214#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 62818#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 62819#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 62723#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 62154#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 61759#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 62497#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 63053#L2036 assume !(0 == start_simulation_~tmp~3#1); 63054#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 63206#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 62366#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 63384#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 62766#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 62767#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63487#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 63488#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 62321#L2017-2 [2022-02-21 04:24:58,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:58,746 INFO L85 PathProgramCache]: Analyzing trace with hash 1716285734, now seen corresponding path program 1 times [2022-02-21 04:24:58,746 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:58,747 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450037902] [2022-02-21 04:24:58,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:58,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:58,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:58,765 INFO L290 TraceCheckUtils]: 0: Hoare triple {67637#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {67637#true} is VALID [2022-02-21 04:24:58,766 INFO L290 TraceCheckUtils]: 1: Hoare triple {67637#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,766 INFO L290 TraceCheckUtils]: 2: Hoare triple {67639#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,766 INFO L290 TraceCheckUtils]: 3: Hoare triple {67639#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,767 INFO L290 TraceCheckUtils]: 4: Hoare triple {67639#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,767 INFO L290 TraceCheckUtils]: 5: Hoare triple {67639#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,767 INFO L290 TraceCheckUtils]: 6: Hoare triple {67639#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,767 INFO L290 TraceCheckUtils]: 7: Hoare triple {67639#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,768 INFO L290 TraceCheckUtils]: 8: Hoare triple {67639#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,768 INFO L290 TraceCheckUtils]: 9: Hoare triple {67639#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,768 INFO L290 TraceCheckUtils]: 10: Hoare triple {67639#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,769 INFO L290 TraceCheckUtils]: 11: Hoare triple {67639#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {67639#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:58,769 INFO L290 TraceCheckUtils]: 12: Hoare triple {67639#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,769 INFO L290 TraceCheckUtils]: 13: Hoare triple {67638#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {67638#false} is VALID [2022-02-21 04:24:58,769 INFO L290 TraceCheckUtils]: 14: Hoare triple {67638#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,769 INFO L290 TraceCheckUtils]: 15: Hoare triple {67638#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,769 INFO L290 TraceCheckUtils]: 16: Hoare triple {67638#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,769 INFO L290 TraceCheckUtils]: 17: Hoare triple {67638#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,769 INFO L290 TraceCheckUtils]: 18: Hoare triple {67638#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,770 INFO L290 TraceCheckUtils]: 19: Hoare triple {67638#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {67638#false} is VALID [2022-02-21 04:24:58,770 INFO L290 TraceCheckUtils]: 20: Hoare triple {67638#false} assume !(0 == ~M_E~0); {67638#false} is VALID [2022-02-21 04:24:58,770 INFO L290 TraceCheckUtils]: 21: Hoare triple {67638#false} assume !(0 == ~T1_E~0); {67638#false} is VALID [2022-02-21 04:24:58,770 INFO L290 TraceCheckUtils]: 22: Hoare triple {67638#false} assume !(0 == ~T2_E~0); {67638#false} is VALID [2022-02-21 04:24:58,770 INFO L290 TraceCheckUtils]: 23: Hoare triple {67638#false} assume !(0 == ~T3_E~0); {67638#false} is VALID [2022-02-21 04:24:58,770 INFO L290 TraceCheckUtils]: 24: Hoare triple {67638#false} assume !(0 == ~T4_E~0); {67638#false} is VALID [2022-02-21 04:24:58,770 INFO L290 TraceCheckUtils]: 25: Hoare triple {67638#false} assume !(0 == ~T5_E~0); {67638#false} is VALID [2022-02-21 04:24:58,770 INFO L290 TraceCheckUtils]: 26: Hoare triple {67638#false} assume !(0 == ~T6_E~0); {67638#false} is VALID [2022-02-21 04:24:58,770 INFO L290 TraceCheckUtils]: 27: Hoare triple {67638#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {67638#false} is VALID [2022-02-21 04:24:58,771 INFO L290 TraceCheckUtils]: 28: Hoare triple {67638#false} assume !(0 == ~T8_E~0); {67638#false} is VALID [2022-02-21 04:24:58,771 INFO L290 TraceCheckUtils]: 29: Hoare triple {67638#false} assume !(0 == ~T9_E~0); {67638#false} is VALID [2022-02-21 04:24:58,771 INFO L290 TraceCheckUtils]: 30: Hoare triple {67638#false} assume !(0 == ~T10_E~0); {67638#false} is VALID [2022-02-21 04:24:58,771 INFO L290 TraceCheckUtils]: 31: Hoare triple {67638#false} assume !(0 == ~T11_E~0); {67638#false} is VALID [2022-02-21 04:24:58,771 INFO L290 TraceCheckUtils]: 32: Hoare triple {67638#false} assume !(0 == ~T12_E~0); {67638#false} is VALID [2022-02-21 04:24:58,771 INFO L290 TraceCheckUtils]: 33: Hoare triple {67638#false} assume !(0 == ~T13_E~0); {67638#false} is VALID [2022-02-21 04:24:58,771 INFO L290 TraceCheckUtils]: 34: Hoare triple {67638#false} assume !(0 == ~T14_E~0); {67638#false} is VALID [2022-02-21 04:24:58,771 INFO L290 TraceCheckUtils]: 35: Hoare triple {67638#false} assume 0 == ~E_1~0;~E_1~0 := 1; {67638#false} is VALID [2022-02-21 04:24:58,772 INFO L290 TraceCheckUtils]: 36: Hoare triple {67638#false} assume !(0 == ~E_2~0); {67638#false} is VALID [2022-02-21 04:24:58,772 INFO L290 TraceCheckUtils]: 37: Hoare triple {67638#false} assume !(0 == ~E_3~0); {67638#false} is VALID [2022-02-21 04:24:58,772 INFO L290 TraceCheckUtils]: 38: Hoare triple {67638#false} assume !(0 == ~E_4~0); {67638#false} is VALID [2022-02-21 04:24:58,772 INFO L290 TraceCheckUtils]: 39: Hoare triple {67638#false} assume !(0 == ~E_5~0); {67638#false} is VALID [2022-02-21 04:24:58,772 INFO L290 TraceCheckUtils]: 40: Hoare triple {67638#false} assume !(0 == ~E_6~0); {67638#false} is VALID [2022-02-21 04:24:58,772 INFO L290 TraceCheckUtils]: 41: Hoare triple {67638#false} assume !(0 == ~E_7~0); {67638#false} is VALID [2022-02-21 04:24:58,772 INFO L290 TraceCheckUtils]: 42: Hoare triple {67638#false} assume !(0 == ~E_8~0); {67638#false} is VALID [2022-02-21 04:24:58,772 INFO L290 TraceCheckUtils]: 43: Hoare triple {67638#false} assume 0 == ~E_9~0;~E_9~0 := 1; {67638#false} is VALID [2022-02-21 04:24:58,772 INFO L290 TraceCheckUtils]: 44: Hoare triple {67638#false} assume !(0 == ~E_10~0); {67638#false} is VALID [2022-02-21 04:24:58,773 INFO L290 TraceCheckUtils]: 45: Hoare triple {67638#false} assume !(0 == ~E_11~0); {67638#false} is VALID [2022-02-21 04:24:58,773 INFO L290 TraceCheckUtils]: 46: Hoare triple {67638#false} assume !(0 == ~E_12~0); {67638#false} is VALID [2022-02-21 04:24:58,773 INFO L290 TraceCheckUtils]: 47: Hoare triple {67638#false} assume !(0 == ~E_13~0); {67638#false} is VALID [2022-02-21 04:24:58,773 INFO L290 TraceCheckUtils]: 48: Hoare triple {67638#false} assume !(0 == ~E_14~0); {67638#false} is VALID [2022-02-21 04:24:58,773 INFO L290 TraceCheckUtils]: 49: Hoare triple {67638#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {67638#false} is VALID [2022-02-21 04:24:58,773 INFO L290 TraceCheckUtils]: 50: Hoare triple {67638#false} assume 1 == ~m_pc~0; {67638#false} is VALID [2022-02-21 04:24:58,773 INFO L290 TraceCheckUtils]: 51: Hoare triple {67638#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {67638#false} is VALID [2022-02-21 04:24:58,773 INFO L290 TraceCheckUtils]: 52: Hoare triple {67638#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {67638#false} is VALID [2022-02-21 04:24:58,773 INFO L290 TraceCheckUtils]: 53: Hoare triple {67638#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {67638#false} is VALID [2022-02-21 04:24:58,774 INFO L290 TraceCheckUtils]: 54: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp~1#1); {67638#false} is VALID [2022-02-21 04:24:58,774 INFO L290 TraceCheckUtils]: 55: Hoare triple {67638#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {67638#false} is VALID [2022-02-21 04:24:58,774 INFO L290 TraceCheckUtils]: 56: Hoare triple {67638#false} assume !(1 == ~t1_pc~0); {67638#false} is VALID [2022-02-21 04:24:58,774 INFO L290 TraceCheckUtils]: 57: Hoare triple {67638#false} is_transmit1_triggered_~__retres1~1#1 := 0; {67638#false} is VALID [2022-02-21 04:24:58,774 INFO L290 TraceCheckUtils]: 58: Hoare triple {67638#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {67638#false} is VALID [2022-02-21 04:24:58,774 INFO L290 TraceCheckUtils]: 59: Hoare triple {67638#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {67638#false} is VALID [2022-02-21 04:24:58,774 INFO L290 TraceCheckUtils]: 60: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___0~0#1); {67638#false} is VALID [2022-02-21 04:24:58,774 INFO L290 TraceCheckUtils]: 61: Hoare triple {67638#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {67638#false} is VALID [2022-02-21 04:24:58,774 INFO L290 TraceCheckUtils]: 62: Hoare triple {67638#false} assume 1 == ~t2_pc~0; {67638#false} is VALID [2022-02-21 04:24:58,775 INFO L290 TraceCheckUtils]: 63: Hoare triple {67638#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {67638#false} is VALID [2022-02-21 04:24:58,775 INFO L290 TraceCheckUtils]: 64: Hoare triple {67638#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {67638#false} is VALID [2022-02-21 04:24:58,775 INFO L290 TraceCheckUtils]: 65: Hoare triple {67638#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {67638#false} is VALID [2022-02-21 04:24:58,775 INFO L290 TraceCheckUtils]: 66: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___1~0#1); {67638#false} is VALID [2022-02-21 04:24:58,775 INFO L290 TraceCheckUtils]: 67: Hoare triple {67638#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {67638#false} is VALID [2022-02-21 04:24:58,775 INFO L290 TraceCheckUtils]: 68: Hoare triple {67638#false} assume !(1 == ~t3_pc~0); {67638#false} is VALID [2022-02-21 04:24:58,775 INFO L290 TraceCheckUtils]: 69: Hoare triple {67638#false} is_transmit3_triggered_~__retres1~3#1 := 0; {67638#false} is VALID [2022-02-21 04:24:58,775 INFO L290 TraceCheckUtils]: 70: Hoare triple {67638#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {67638#false} is VALID [2022-02-21 04:24:58,776 INFO L290 TraceCheckUtils]: 71: Hoare triple {67638#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {67638#false} is VALID [2022-02-21 04:24:58,776 INFO L290 TraceCheckUtils]: 72: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___2~0#1); {67638#false} is VALID [2022-02-21 04:24:58,776 INFO L290 TraceCheckUtils]: 73: Hoare triple {67638#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {67638#false} is VALID [2022-02-21 04:24:58,776 INFO L290 TraceCheckUtils]: 74: Hoare triple {67638#false} assume 1 == ~t4_pc~0; {67638#false} is VALID [2022-02-21 04:24:58,776 INFO L290 TraceCheckUtils]: 75: Hoare triple {67638#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {67638#false} is VALID [2022-02-21 04:24:58,776 INFO L290 TraceCheckUtils]: 76: Hoare triple {67638#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {67638#false} is VALID [2022-02-21 04:24:58,776 INFO L290 TraceCheckUtils]: 77: Hoare triple {67638#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {67638#false} is VALID [2022-02-21 04:24:58,776 INFO L290 TraceCheckUtils]: 78: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___3~0#1); {67638#false} is VALID [2022-02-21 04:24:58,776 INFO L290 TraceCheckUtils]: 79: Hoare triple {67638#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {67638#false} is VALID [2022-02-21 04:24:58,777 INFO L290 TraceCheckUtils]: 80: Hoare triple {67638#false} assume 1 == ~t5_pc~0; {67638#false} is VALID [2022-02-21 04:24:58,777 INFO L290 TraceCheckUtils]: 81: Hoare triple {67638#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {67638#false} is VALID [2022-02-21 04:24:58,777 INFO L290 TraceCheckUtils]: 82: Hoare triple {67638#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {67638#false} is VALID [2022-02-21 04:24:58,777 INFO L290 TraceCheckUtils]: 83: Hoare triple {67638#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {67638#false} is VALID [2022-02-21 04:24:58,777 INFO L290 TraceCheckUtils]: 84: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___4~0#1); {67638#false} is VALID [2022-02-21 04:24:58,777 INFO L290 TraceCheckUtils]: 85: Hoare triple {67638#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {67638#false} is VALID [2022-02-21 04:24:58,777 INFO L290 TraceCheckUtils]: 86: Hoare triple {67638#false} assume !(1 == ~t6_pc~0); {67638#false} is VALID [2022-02-21 04:24:58,785 INFO L290 TraceCheckUtils]: 87: Hoare triple {67638#false} is_transmit6_triggered_~__retres1~6#1 := 0; {67638#false} is VALID [2022-02-21 04:24:58,786 INFO L290 TraceCheckUtils]: 88: Hoare triple {67638#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {67638#false} is VALID [2022-02-21 04:24:58,786 INFO L290 TraceCheckUtils]: 89: Hoare triple {67638#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {67638#false} is VALID [2022-02-21 04:24:58,786 INFO L290 TraceCheckUtils]: 90: Hoare triple {67638#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {67638#false} is VALID [2022-02-21 04:24:58,786 INFO L290 TraceCheckUtils]: 91: Hoare triple {67638#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {67638#false} is VALID [2022-02-21 04:24:58,786 INFO L290 TraceCheckUtils]: 92: Hoare triple {67638#false} assume 1 == ~t7_pc~0; {67638#false} is VALID [2022-02-21 04:24:58,786 INFO L290 TraceCheckUtils]: 93: Hoare triple {67638#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {67638#false} is VALID [2022-02-21 04:24:58,786 INFO L290 TraceCheckUtils]: 94: Hoare triple {67638#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {67638#false} is VALID [2022-02-21 04:24:58,786 INFO L290 TraceCheckUtils]: 95: Hoare triple {67638#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {67638#false} is VALID [2022-02-21 04:24:58,786 INFO L290 TraceCheckUtils]: 96: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___6~0#1); {67638#false} is VALID [2022-02-21 04:24:58,787 INFO L290 TraceCheckUtils]: 97: Hoare triple {67638#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {67638#false} is VALID [2022-02-21 04:24:58,787 INFO L290 TraceCheckUtils]: 98: Hoare triple {67638#false} assume !(1 == ~t8_pc~0); {67638#false} is VALID [2022-02-21 04:24:58,787 INFO L290 TraceCheckUtils]: 99: Hoare triple {67638#false} is_transmit8_triggered_~__retres1~8#1 := 0; {67638#false} is VALID [2022-02-21 04:24:58,787 INFO L290 TraceCheckUtils]: 100: Hoare triple {67638#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {67638#false} is VALID [2022-02-21 04:24:58,787 INFO L290 TraceCheckUtils]: 101: Hoare triple {67638#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {67638#false} is VALID [2022-02-21 04:24:58,787 INFO L290 TraceCheckUtils]: 102: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___7~0#1); {67638#false} is VALID [2022-02-21 04:24:58,787 INFO L290 TraceCheckUtils]: 103: Hoare triple {67638#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {67638#false} is VALID [2022-02-21 04:24:58,787 INFO L290 TraceCheckUtils]: 104: Hoare triple {67638#false} assume 1 == ~t9_pc~0; {67638#false} is VALID [2022-02-21 04:24:58,788 INFO L290 TraceCheckUtils]: 105: Hoare triple {67638#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {67638#false} is VALID [2022-02-21 04:24:58,788 INFO L290 TraceCheckUtils]: 106: Hoare triple {67638#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {67638#false} is VALID [2022-02-21 04:24:58,788 INFO L290 TraceCheckUtils]: 107: Hoare triple {67638#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {67638#false} is VALID [2022-02-21 04:24:58,788 INFO L290 TraceCheckUtils]: 108: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___8~0#1); {67638#false} is VALID [2022-02-21 04:24:58,788 INFO L290 TraceCheckUtils]: 109: Hoare triple {67638#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {67638#false} is VALID [2022-02-21 04:24:58,788 INFO L290 TraceCheckUtils]: 110: Hoare triple {67638#false} assume !(1 == ~t10_pc~0); {67638#false} is VALID [2022-02-21 04:24:58,788 INFO L290 TraceCheckUtils]: 111: Hoare triple {67638#false} is_transmit10_triggered_~__retres1~10#1 := 0; {67638#false} is VALID [2022-02-21 04:24:58,788 INFO L290 TraceCheckUtils]: 112: Hoare triple {67638#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {67638#false} is VALID [2022-02-21 04:24:58,788 INFO L290 TraceCheckUtils]: 113: Hoare triple {67638#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {67638#false} is VALID [2022-02-21 04:24:58,789 INFO L290 TraceCheckUtils]: 114: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___9~0#1); {67638#false} is VALID [2022-02-21 04:24:58,789 INFO L290 TraceCheckUtils]: 115: Hoare triple {67638#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {67638#false} is VALID [2022-02-21 04:24:58,789 INFO L290 TraceCheckUtils]: 116: Hoare triple {67638#false} assume 1 == ~t11_pc~0; {67638#false} is VALID [2022-02-21 04:24:58,789 INFO L290 TraceCheckUtils]: 117: Hoare triple {67638#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {67638#false} is VALID [2022-02-21 04:24:58,789 INFO L290 TraceCheckUtils]: 118: Hoare triple {67638#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {67638#false} is VALID [2022-02-21 04:24:58,789 INFO L290 TraceCheckUtils]: 119: Hoare triple {67638#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {67638#false} is VALID [2022-02-21 04:24:58,789 INFO L290 TraceCheckUtils]: 120: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___10~0#1); {67638#false} is VALID [2022-02-21 04:24:58,789 INFO L290 TraceCheckUtils]: 121: Hoare triple {67638#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {67638#false} is VALID [2022-02-21 04:24:58,789 INFO L290 TraceCheckUtils]: 122: Hoare triple {67638#false} assume !(1 == ~t12_pc~0); {67638#false} is VALID [2022-02-21 04:24:58,790 INFO L290 TraceCheckUtils]: 123: Hoare triple {67638#false} is_transmit12_triggered_~__retres1~12#1 := 0; {67638#false} is VALID [2022-02-21 04:24:58,790 INFO L290 TraceCheckUtils]: 124: Hoare triple {67638#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {67638#false} is VALID [2022-02-21 04:24:58,790 INFO L290 TraceCheckUtils]: 125: Hoare triple {67638#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {67638#false} is VALID [2022-02-21 04:24:58,790 INFO L290 TraceCheckUtils]: 126: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___11~0#1); {67638#false} is VALID [2022-02-21 04:24:58,790 INFO L290 TraceCheckUtils]: 127: Hoare triple {67638#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {67638#false} is VALID [2022-02-21 04:24:58,790 INFO L290 TraceCheckUtils]: 128: Hoare triple {67638#false} assume 1 == ~t13_pc~0; {67638#false} is VALID [2022-02-21 04:24:58,790 INFO L290 TraceCheckUtils]: 129: Hoare triple {67638#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {67638#false} is VALID [2022-02-21 04:24:58,790 INFO L290 TraceCheckUtils]: 130: Hoare triple {67638#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {67638#false} is VALID [2022-02-21 04:24:58,790 INFO L290 TraceCheckUtils]: 131: Hoare triple {67638#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {67638#false} is VALID [2022-02-21 04:24:58,791 INFO L290 TraceCheckUtils]: 132: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___12~0#1); {67638#false} is VALID [2022-02-21 04:24:58,791 INFO L290 TraceCheckUtils]: 133: Hoare triple {67638#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {67638#false} is VALID [2022-02-21 04:24:58,791 INFO L290 TraceCheckUtils]: 134: Hoare triple {67638#false} assume 1 == ~t14_pc~0; {67638#false} is VALID [2022-02-21 04:24:58,791 INFO L290 TraceCheckUtils]: 135: Hoare triple {67638#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {67638#false} is VALID [2022-02-21 04:24:58,791 INFO L290 TraceCheckUtils]: 136: Hoare triple {67638#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {67638#false} is VALID [2022-02-21 04:24:58,791 INFO L290 TraceCheckUtils]: 137: Hoare triple {67638#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {67638#false} is VALID [2022-02-21 04:24:58,791 INFO L290 TraceCheckUtils]: 138: Hoare triple {67638#false} assume !(0 != activate_threads_~tmp___13~0#1); {67638#false} is VALID [2022-02-21 04:24:58,791 INFO L290 TraceCheckUtils]: 139: Hoare triple {67638#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {67638#false} is VALID [2022-02-21 04:24:58,791 INFO L290 TraceCheckUtils]: 140: Hoare triple {67638#false} assume 1 == ~M_E~0;~M_E~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,792 INFO L290 TraceCheckUtils]: 141: Hoare triple {67638#false} assume !(1 == ~T1_E~0); {67638#false} is VALID [2022-02-21 04:24:58,792 INFO L290 TraceCheckUtils]: 142: Hoare triple {67638#false} assume !(1 == ~T2_E~0); {67638#false} is VALID [2022-02-21 04:24:58,792 INFO L290 TraceCheckUtils]: 143: Hoare triple {67638#false} assume !(1 == ~T3_E~0); {67638#false} is VALID [2022-02-21 04:24:58,792 INFO L290 TraceCheckUtils]: 144: Hoare triple {67638#false} assume !(1 == ~T4_E~0); {67638#false} is VALID [2022-02-21 04:24:58,792 INFO L290 TraceCheckUtils]: 145: Hoare triple {67638#false} assume !(1 == ~T5_E~0); {67638#false} is VALID [2022-02-21 04:24:58,792 INFO L290 TraceCheckUtils]: 146: Hoare triple {67638#false} assume !(1 == ~T6_E~0); {67638#false} is VALID [2022-02-21 04:24:58,792 INFO L290 TraceCheckUtils]: 147: Hoare triple {67638#false} assume !(1 == ~T7_E~0); {67638#false} is VALID [2022-02-21 04:24:58,792 INFO L290 TraceCheckUtils]: 148: Hoare triple {67638#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,792 INFO L290 TraceCheckUtils]: 149: Hoare triple {67638#false} assume !(1 == ~T9_E~0); {67638#false} is VALID [2022-02-21 04:24:58,793 INFO L290 TraceCheckUtils]: 150: Hoare triple {67638#false} assume !(1 == ~T10_E~0); {67638#false} is VALID [2022-02-21 04:24:58,793 INFO L290 TraceCheckUtils]: 151: Hoare triple {67638#false} assume !(1 == ~T11_E~0); {67638#false} is VALID [2022-02-21 04:24:58,793 INFO L290 TraceCheckUtils]: 152: Hoare triple {67638#false} assume !(1 == ~T12_E~0); {67638#false} is VALID [2022-02-21 04:24:58,793 INFO L290 TraceCheckUtils]: 153: Hoare triple {67638#false} assume !(1 == ~T13_E~0); {67638#false} is VALID [2022-02-21 04:24:58,793 INFO L290 TraceCheckUtils]: 154: Hoare triple {67638#false} assume !(1 == ~T14_E~0); {67638#false} is VALID [2022-02-21 04:24:58,793 INFO L290 TraceCheckUtils]: 155: Hoare triple {67638#false} assume !(1 == ~E_1~0); {67638#false} is VALID [2022-02-21 04:24:58,793 INFO L290 TraceCheckUtils]: 156: Hoare triple {67638#false} assume 1 == ~E_2~0;~E_2~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,793 INFO L290 TraceCheckUtils]: 157: Hoare triple {67638#false} assume !(1 == ~E_3~0); {67638#false} is VALID [2022-02-21 04:24:58,793 INFO L290 TraceCheckUtils]: 158: Hoare triple {67638#false} assume !(1 == ~E_4~0); {67638#false} is VALID [2022-02-21 04:24:58,794 INFO L290 TraceCheckUtils]: 159: Hoare triple {67638#false} assume !(1 == ~E_5~0); {67638#false} is VALID [2022-02-21 04:24:58,794 INFO L290 TraceCheckUtils]: 160: Hoare triple {67638#false} assume !(1 == ~E_6~0); {67638#false} is VALID [2022-02-21 04:24:58,794 INFO L290 TraceCheckUtils]: 161: Hoare triple {67638#false} assume !(1 == ~E_7~0); {67638#false} is VALID [2022-02-21 04:24:58,794 INFO L290 TraceCheckUtils]: 162: Hoare triple {67638#false} assume !(1 == ~E_8~0); {67638#false} is VALID [2022-02-21 04:24:58,794 INFO L290 TraceCheckUtils]: 163: Hoare triple {67638#false} assume !(1 == ~E_9~0); {67638#false} is VALID [2022-02-21 04:24:58,794 INFO L290 TraceCheckUtils]: 164: Hoare triple {67638#false} assume 1 == ~E_10~0;~E_10~0 := 2; {67638#false} is VALID [2022-02-21 04:24:58,794 INFO L290 TraceCheckUtils]: 165: Hoare triple {67638#false} assume !(1 == ~E_11~0); {67638#false} is VALID [2022-02-21 04:24:58,794 INFO L290 TraceCheckUtils]: 166: Hoare triple {67638#false} assume !(1 == ~E_12~0); {67638#false} is VALID [2022-02-21 04:24:58,794 INFO L290 TraceCheckUtils]: 167: Hoare triple {67638#false} assume !(1 == ~E_13~0); {67638#false} is VALID [2022-02-21 04:24:58,795 INFO L290 TraceCheckUtils]: 168: Hoare triple {67638#false} assume !(1 == ~E_14~0); {67638#false} is VALID [2022-02-21 04:24:58,795 INFO L290 TraceCheckUtils]: 169: Hoare triple {67638#false} assume { :end_inline_reset_delta_events } true; {67638#false} is VALID [2022-02-21 04:24:58,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:58,795 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:58,795 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450037902] [2022-02-21 04:24:58,796 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450037902] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:58,796 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:58,796 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:58,796 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197181089] [2022-02-21 04:24:58,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:58,796 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:58,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:58,797 INFO L85 PathProgramCache]: Analyzing trace with hash -1856485429, now seen corresponding path program 1 times [2022-02-21 04:24:58,797 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:58,797 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958735279] [2022-02-21 04:24:58,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:58,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:58,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:58,821 INFO L290 TraceCheckUtils]: 0: Hoare triple {67640#true} assume !false; {67640#true} is VALID [2022-02-21 04:24:58,821 INFO L290 TraceCheckUtils]: 1: Hoare triple {67640#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {67640#true} is VALID [2022-02-21 04:24:58,821 INFO L290 TraceCheckUtils]: 2: Hoare triple {67640#true} assume !false; {67640#true} is VALID [2022-02-21 04:24:58,822 INFO L290 TraceCheckUtils]: 3: Hoare triple {67640#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {67640#true} is VALID [2022-02-21 04:24:58,822 INFO L290 TraceCheckUtils]: 4: Hoare triple {67640#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {67640#true} is VALID [2022-02-21 04:24:58,822 INFO L290 TraceCheckUtils]: 5: Hoare triple {67640#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {67640#true} is VALID [2022-02-21 04:24:58,822 INFO L290 TraceCheckUtils]: 6: Hoare triple {67640#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {67640#true} is VALID [2022-02-21 04:24:58,822 INFO L290 TraceCheckUtils]: 7: Hoare triple {67640#true} assume !(0 != eval_~tmp~0#1); {67640#true} is VALID [2022-02-21 04:24:58,822 INFO L290 TraceCheckUtils]: 8: Hoare triple {67640#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {67640#true} is VALID [2022-02-21 04:24:58,822 INFO L290 TraceCheckUtils]: 9: Hoare triple {67640#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {67640#true} is VALID [2022-02-21 04:24:58,823 INFO L290 TraceCheckUtils]: 10: Hoare triple {67640#true} assume 0 == ~M_E~0;~M_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,823 INFO L290 TraceCheckUtils]: 11: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,823 INFO L290 TraceCheckUtils]: 12: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,823 INFO L290 TraceCheckUtils]: 13: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,824 INFO L290 TraceCheckUtils]: 14: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,824 INFO L290 TraceCheckUtils]: 15: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,824 INFO L290 TraceCheckUtils]: 16: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,824 INFO L290 TraceCheckUtils]: 17: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,825 INFO L290 TraceCheckUtils]: 18: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,825 INFO L290 TraceCheckUtils]: 19: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,825 INFO L290 TraceCheckUtils]: 20: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,825 INFO L290 TraceCheckUtils]: 21: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,826 INFO L290 TraceCheckUtils]: 22: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,826 INFO L290 TraceCheckUtils]: 23: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,826 INFO L290 TraceCheckUtils]: 24: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,826 INFO L290 TraceCheckUtils]: 25: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,827 INFO L290 TraceCheckUtils]: 26: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,827 INFO L290 TraceCheckUtils]: 27: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,827 INFO L290 TraceCheckUtils]: 28: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,828 INFO L290 TraceCheckUtils]: 29: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,828 INFO L290 TraceCheckUtils]: 30: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,828 INFO L290 TraceCheckUtils]: 31: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,828 INFO L290 TraceCheckUtils]: 32: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,829 INFO L290 TraceCheckUtils]: 33: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,829 INFO L290 TraceCheckUtils]: 34: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,829 INFO L290 TraceCheckUtils]: 35: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,829 INFO L290 TraceCheckUtils]: 36: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,830 INFO L290 TraceCheckUtils]: 37: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,830 INFO L290 TraceCheckUtils]: 38: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,830 INFO L290 TraceCheckUtils]: 39: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,830 INFO L290 TraceCheckUtils]: 40: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,831 INFO L290 TraceCheckUtils]: 41: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,831 INFO L290 TraceCheckUtils]: 42: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,831 INFO L290 TraceCheckUtils]: 43: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,831 INFO L290 TraceCheckUtils]: 44: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,832 INFO L290 TraceCheckUtils]: 45: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,832 INFO L290 TraceCheckUtils]: 46: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,832 INFO L290 TraceCheckUtils]: 47: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,832 INFO L290 TraceCheckUtils]: 48: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,833 INFO L290 TraceCheckUtils]: 49: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,833 INFO L290 TraceCheckUtils]: 50: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,833 INFO L290 TraceCheckUtils]: 51: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,834 INFO L290 TraceCheckUtils]: 52: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,834 INFO L290 TraceCheckUtils]: 53: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,834 INFO L290 TraceCheckUtils]: 54: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,834 INFO L290 TraceCheckUtils]: 55: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,835 INFO L290 TraceCheckUtils]: 56: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,835 INFO L290 TraceCheckUtils]: 57: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,835 INFO L290 TraceCheckUtils]: 58: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,835 INFO L290 TraceCheckUtils]: 59: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,836 INFO L290 TraceCheckUtils]: 60: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,836 INFO L290 TraceCheckUtils]: 61: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,836 INFO L290 TraceCheckUtils]: 62: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,836 INFO L290 TraceCheckUtils]: 63: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,837 INFO L290 TraceCheckUtils]: 64: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,837 INFO L290 TraceCheckUtils]: 65: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,837 INFO L290 TraceCheckUtils]: 66: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,837 INFO L290 TraceCheckUtils]: 67: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,838 INFO L290 TraceCheckUtils]: 68: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,838 INFO L290 TraceCheckUtils]: 69: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,838 INFO L290 TraceCheckUtils]: 70: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,838 INFO L290 TraceCheckUtils]: 71: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,839 INFO L290 TraceCheckUtils]: 72: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,839 INFO L290 TraceCheckUtils]: 73: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,839 INFO L290 TraceCheckUtils]: 74: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,839 INFO L290 TraceCheckUtils]: 75: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,840 INFO L290 TraceCheckUtils]: 76: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,840 INFO L290 TraceCheckUtils]: 77: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,840 INFO L290 TraceCheckUtils]: 78: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,841 INFO L290 TraceCheckUtils]: 79: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,841 INFO L290 TraceCheckUtils]: 80: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,841 INFO L290 TraceCheckUtils]: 81: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,841 INFO L290 TraceCheckUtils]: 82: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,842 INFO L290 TraceCheckUtils]: 83: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,842 INFO L290 TraceCheckUtils]: 84: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,842 INFO L290 TraceCheckUtils]: 85: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,842 INFO L290 TraceCheckUtils]: 86: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,843 INFO L290 TraceCheckUtils]: 87: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,843 INFO L290 TraceCheckUtils]: 88: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,843 INFO L290 TraceCheckUtils]: 89: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,843 INFO L290 TraceCheckUtils]: 90: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,844 INFO L290 TraceCheckUtils]: 91: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,844 INFO L290 TraceCheckUtils]: 92: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,844 INFO L290 TraceCheckUtils]: 93: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,844 INFO L290 TraceCheckUtils]: 94: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,845 INFO L290 TraceCheckUtils]: 95: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,845 INFO L290 TraceCheckUtils]: 96: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,845 INFO L290 TraceCheckUtils]: 97: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,845 INFO L290 TraceCheckUtils]: 98: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,846 INFO L290 TraceCheckUtils]: 99: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,846 INFO L290 TraceCheckUtils]: 100: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,846 INFO L290 TraceCheckUtils]: 101: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,846 INFO L290 TraceCheckUtils]: 102: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,847 INFO L290 TraceCheckUtils]: 103: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,847 INFO L290 TraceCheckUtils]: 104: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,847 INFO L290 TraceCheckUtils]: 105: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,848 INFO L290 TraceCheckUtils]: 106: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,848 INFO L290 TraceCheckUtils]: 107: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,848 INFO L290 TraceCheckUtils]: 108: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,848 INFO L290 TraceCheckUtils]: 109: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,849 INFO L290 TraceCheckUtils]: 110: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,849 INFO L290 TraceCheckUtils]: 111: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,849 INFO L290 TraceCheckUtils]: 112: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,849 INFO L290 TraceCheckUtils]: 113: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,850 INFO L290 TraceCheckUtils]: 114: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,850 INFO L290 TraceCheckUtils]: 115: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,850 INFO L290 TraceCheckUtils]: 116: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,850 INFO L290 TraceCheckUtils]: 117: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,851 INFO L290 TraceCheckUtils]: 118: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,851 INFO L290 TraceCheckUtils]: 119: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,851 INFO L290 TraceCheckUtils]: 120: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,851 INFO L290 TraceCheckUtils]: 121: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,852 INFO L290 TraceCheckUtils]: 122: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,852 INFO L290 TraceCheckUtils]: 123: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,852 INFO L290 TraceCheckUtils]: 124: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,852 INFO L290 TraceCheckUtils]: 125: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,853 INFO L290 TraceCheckUtils]: 126: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,853 INFO L290 TraceCheckUtils]: 127: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,853 INFO L290 TraceCheckUtils]: 128: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,853 INFO L290 TraceCheckUtils]: 129: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {67642#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:58,854 INFO L290 TraceCheckUtils]: 130: Hoare triple {67642#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {67641#false} is VALID [2022-02-21 04:24:58,854 INFO L290 TraceCheckUtils]: 131: Hoare triple {67641#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,854 INFO L290 TraceCheckUtils]: 132: Hoare triple {67641#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,854 INFO L290 TraceCheckUtils]: 133: Hoare triple {67641#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,854 INFO L290 TraceCheckUtils]: 134: Hoare triple {67641#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,854 INFO L290 TraceCheckUtils]: 135: Hoare triple {67641#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,854 INFO L290 TraceCheckUtils]: 136: Hoare triple {67641#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,855 INFO L290 TraceCheckUtils]: 137: Hoare triple {67641#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,855 INFO L290 TraceCheckUtils]: 138: Hoare triple {67641#false} assume !(1 == ~T8_E~0); {67641#false} is VALID [2022-02-21 04:24:58,855 INFO L290 TraceCheckUtils]: 139: Hoare triple {67641#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,855 INFO L290 TraceCheckUtils]: 140: Hoare triple {67641#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,855 INFO L290 TraceCheckUtils]: 141: Hoare triple {67641#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,855 INFO L290 TraceCheckUtils]: 142: Hoare triple {67641#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,855 INFO L290 TraceCheckUtils]: 143: Hoare triple {67641#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,855 INFO L290 TraceCheckUtils]: 144: Hoare triple {67641#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,855 INFO L290 TraceCheckUtils]: 145: Hoare triple {67641#false} assume 1 == ~E_1~0;~E_1~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,856 INFO L290 TraceCheckUtils]: 146: Hoare triple {67641#false} assume !(1 == ~E_2~0); {67641#false} is VALID [2022-02-21 04:24:58,856 INFO L290 TraceCheckUtils]: 147: Hoare triple {67641#false} assume 1 == ~E_3~0;~E_3~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,856 INFO L290 TraceCheckUtils]: 148: Hoare triple {67641#false} assume 1 == ~E_4~0;~E_4~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,856 INFO L290 TraceCheckUtils]: 149: Hoare triple {67641#false} assume 1 == ~E_5~0;~E_5~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,856 INFO L290 TraceCheckUtils]: 150: Hoare triple {67641#false} assume 1 == ~E_6~0;~E_6~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,856 INFO L290 TraceCheckUtils]: 151: Hoare triple {67641#false} assume 1 == ~E_7~0;~E_7~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,856 INFO L290 TraceCheckUtils]: 152: Hoare triple {67641#false} assume 1 == ~E_8~0;~E_8~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,856 INFO L290 TraceCheckUtils]: 153: Hoare triple {67641#false} assume 1 == ~E_9~0;~E_9~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,856 INFO L290 TraceCheckUtils]: 154: Hoare triple {67641#false} assume !(1 == ~E_10~0); {67641#false} is VALID [2022-02-21 04:24:58,857 INFO L290 TraceCheckUtils]: 155: Hoare triple {67641#false} assume 1 == ~E_11~0;~E_11~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,857 INFO L290 TraceCheckUtils]: 156: Hoare triple {67641#false} assume 1 == ~E_12~0;~E_12~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,857 INFO L290 TraceCheckUtils]: 157: Hoare triple {67641#false} assume 1 == ~E_13~0;~E_13~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,857 INFO L290 TraceCheckUtils]: 158: Hoare triple {67641#false} assume 1 == ~E_14~0;~E_14~0 := 2; {67641#false} is VALID [2022-02-21 04:24:58,857 INFO L290 TraceCheckUtils]: 159: Hoare triple {67641#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {67641#false} is VALID [2022-02-21 04:24:58,857 INFO L290 TraceCheckUtils]: 160: Hoare triple {67641#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {67641#false} is VALID [2022-02-21 04:24:58,857 INFO L290 TraceCheckUtils]: 161: Hoare triple {67641#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {67641#false} is VALID [2022-02-21 04:24:58,857 INFO L290 TraceCheckUtils]: 162: Hoare triple {67641#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {67641#false} is VALID [2022-02-21 04:24:58,857 INFO L290 TraceCheckUtils]: 163: Hoare triple {67641#false} assume !(0 == start_simulation_~tmp~3#1); {67641#false} is VALID [2022-02-21 04:24:58,858 INFO L290 TraceCheckUtils]: 164: Hoare triple {67641#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {67641#false} is VALID [2022-02-21 04:24:58,858 INFO L290 TraceCheckUtils]: 165: Hoare triple {67641#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {67641#false} is VALID [2022-02-21 04:24:58,858 INFO L290 TraceCheckUtils]: 166: Hoare triple {67641#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {67641#false} is VALID [2022-02-21 04:24:58,858 INFO L290 TraceCheckUtils]: 167: Hoare triple {67641#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {67641#false} is VALID [2022-02-21 04:24:58,858 INFO L290 TraceCheckUtils]: 168: Hoare triple {67641#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {67641#false} is VALID [2022-02-21 04:24:58,858 INFO L290 TraceCheckUtils]: 169: Hoare triple {67641#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {67641#false} is VALID [2022-02-21 04:24:58,858 INFO L290 TraceCheckUtils]: 170: Hoare triple {67641#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {67641#false} is VALID [2022-02-21 04:24:58,858 INFO L290 TraceCheckUtils]: 171: Hoare triple {67641#false} assume !(0 != start_simulation_~tmp___0~1#1); {67641#false} is VALID [2022-02-21 04:24:58,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:58,859 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:58,859 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1958735279] [2022-02-21 04:24:58,859 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1958735279] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:58,859 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:58,859 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:58,860 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797514863] [2022-02-21 04:24:58,860 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:58,860 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:58,860 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:58,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:58,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:58,861 INFO L87 Difference]: Start difference. First operand 2047 states and 3027 transitions. cyclomatic complexity: 981 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:59,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:59,784 INFO L93 Difference]: Finished difference Result 2047 states and 3026 transitions. [2022-02-21 04:24:59,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:59,784 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:59,840 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:59,841 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3026 transitions. [2022-02-21 04:24:59,943 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:00,103 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3026 transitions. [2022-02-21 04:25:00,103 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:25:00,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:25:00,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3026 transitions. [2022-02-21 04:25:00,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:00,107 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2022-02-21 04:25:00,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3026 transitions. [2022-02-21 04:25:00,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:25:00,131 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:00,134 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3026 transitions. Second operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:00,136 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3026 transitions. Second operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:00,139 INFO L87 Difference]: Start difference. First operand 2047 states and 3026 transitions. Second operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:00,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:00,263 INFO L93 Difference]: Finished difference Result 2047 states and 3026 transitions. [2022-02-21 04:25:00,263 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3026 transitions. [2022-02-21 04:25:00,266 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:00,266 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:00,270 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3026 transitions. [2022-02-21 04:25:00,273 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3026 transitions. [2022-02-21 04:25:00,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:00,415 INFO L93 Difference]: Finished difference Result 2047 states and 3026 transitions. [2022-02-21 04:25:00,415 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3026 transitions. [2022-02-21 04:25:00,435 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:00,435 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:00,435 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:00,435 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:00,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:00,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3026 transitions. [2022-02-21 04:25:00,541 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2022-02-21 04:25:00,541 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2022-02-21 04:25:00,542 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:25:00,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3026 transitions. [2022-02-21 04:25:00,545 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:00,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:00,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:00,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:00,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:00,547 INFO L791 eck$LassoCheckResult]: Stem: 70616#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 70617#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 71219#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70336#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70337#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 70582#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70583#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70310#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70311#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71534#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 70886#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 70887#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 71404#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70796#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70797#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 70217#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 70218#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 70549#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 70747#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 69794#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69795#L1342 assume !(0 == ~M_E~0); 69960#L1342-2 assume !(0 == ~T1_E~0); 70516#L1347-1 assume !(0 == ~T2_E~0); 71517#L1352-1 assume !(0 == ~T3_E~0); 71313#L1357-1 assume !(0 == ~T4_E~0); 70541#L1362-1 assume !(0 == ~T5_E~0); 70542#L1367-1 assume !(0 == ~T6_E~0); 70139#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 70140#L1377-1 assume !(0 == ~T8_E~0); 70470#L1382-1 assume !(0 == ~T9_E~0); 70471#L1387-1 assume !(0 == ~T10_E~0); 71198#L1392-1 assume !(0 == ~T11_E~0); 70502#L1397-1 assume !(0 == ~T12_E~0); 70503#L1402-1 assume !(0 == ~T13_E~0); 70155#L1407-1 assume !(0 == ~T14_E~0); 70156#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 71434#L1417-1 assume !(0 == ~E_2~0); 71435#L1422-1 assume !(0 == ~E_3~0); 71676#L1427-1 assume !(0 == ~E_4~0); 70343#L1432-1 assume !(0 == ~E_5~0); 70344#L1437-1 assume !(0 == ~E_6~0); 71352#L1442-1 assume !(0 == ~E_7~0); 71353#L1447-1 assume !(0 == ~E_8~0); 71195#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 69930#L1457-1 assume !(0 == ~E_10~0); 69931#L1462-1 assume !(0 == ~E_11~0); 71387#L1467-1 assume !(0 == ~E_12~0); 71399#L1472-1 assume !(0 == ~E_13~0); 71400#L1477-1 assume !(0 == ~E_14~0); 71142#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70129#L646 assume 1 == ~m_pc~0; 70130#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 70806#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70821#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70219#L1666 assume !(0 != activate_threads_~tmp~1#1); 70220#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71697#L665 assume !(1 == ~t1_pc~0); 70695#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 70696#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70228#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70229#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 71019#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71020#L684 assume 1 == ~t2_pc~0; 71137#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 71061#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71126#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71521#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 71522#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71710#L703 assume !(1 == ~t3_pc~0); 70365#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70366#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71012#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69764#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 69765#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70250#L722 assume 1 == ~t4_pc~0; 70988#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70431#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70776#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 71336#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 70843#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69961#L741 assume 1 == ~t5_pc~0; 69962#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 70272#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70426#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70427#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 71106#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70517#L760 assume !(1 == ~t6_pc~0); 70364#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 70363#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70221#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70222#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70943#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70944#L779 assume 1 == ~t7_pc~0; 70006#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69852#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69853#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70261#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 70284#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70285#L798 assume !(1 == ~t8_pc~0); 71566#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 71489#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70008#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70009#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 71699#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69829#L817 assume 1 == ~t9_pc~0; 69830#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70624#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70625#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 71147#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 70235#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70236#L836 assume !(1 == ~t10_pc~0); 70252#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 70183#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70184#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70432#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 70433#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 71499#L855 assume 1 == ~t11_pc~0; 70817#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 70818#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 71382#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 71191#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 71026#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 70125#L874 assume !(1 == ~t12_pc~0); 70126#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 70293#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70294#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 70434#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 69802#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69803#L893 assume 1 == ~t13_pc~0; 71633#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 70158#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 70469#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 71560#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 71568#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 71569#L912 assume 1 == ~t14_pc~0; 71359#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 71360#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 70128#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 70060#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 70061#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70836#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 71252#L1495-2 assume !(1 == ~T1_E~0); 71253#L1500-1 assume !(1 == ~T2_E~0); 70939#L1505-1 assume !(1 == ~T3_E~0); 70940#L1510-1 assume !(1 == ~T4_E~0); 70997#L1515-1 assume !(1 == ~T5_E~0); 70998#L1520-1 assume !(1 == ~T6_E~0); 71567#L1525-1 assume !(1 == ~T7_E~0); 71277#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70230#L1535-1 assume !(1 == ~T9_E~0); 70231#L1540-1 assume !(1 == ~T10_E~0); 69723#L1545-1 assume !(1 == ~T11_E~0); 69724#L1550-1 assume !(1 == ~T12_E~0); 69972#L1555-1 assume !(1 == ~T13_E~0); 69973#L1560-1 assume !(1 == ~T14_E~0); 70273#L1565-1 assume !(1 == ~E_1~0); 71686#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 71164#L1575-1 assume !(1 == ~E_3~0); 70543#L1580-1 assume !(1 == ~E_4~0); 70544#L1585-1 assume !(1 == ~E_5~0); 71014#L1590-1 assume !(1 == ~E_6~0); 70578#L1595-1 assume !(1 == ~E_7~0); 70579#L1600-1 assume !(1 == ~E_8~0); 70951#L1605-1 assume !(1 == ~E_9~0); 70952#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 71469#L1615-1 assume !(1 == ~E_11~0); 70408#L1620-1 assume !(1 == ~E_12~0); 70409#L1625-1 assume !(1 == ~E_13~0); 71196#L1630-1 assume !(1 == ~E_14~0); 70577#L1635-1 assume { :end_inline_reset_delta_events } true; 70518#L2017-2 [2022-02-21 04:25:00,548 INFO L793 eck$LassoCheckResult]: Loop: 70518#L2017-2 assume !false; 69798#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69799#L1316 assume !false; 71127#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 71189#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 69736#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 69878#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69879#L1115 assume !(0 != eval_~tmp~0#1); 71212#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 70633#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 70634#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 70816#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 71317#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70986#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70987#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71549#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 71724#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 71719#L1372-3 assume !(0 == ~T7_E~0); 69780#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69781#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70450#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 70451#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 71362#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 71672#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 70930#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 70086#L1412-3 assume !(0 == ~E_1~0); 70087#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70851#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70852#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71546#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71233#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70945#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70946#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69846#L1452-3 assume !(0 == ~E_9~0); 69847#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 71485#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 71486#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 71290#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 71291#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 70084#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70085#L646-42 assume !(1 == ~m_pc~0); 70671#L646-44 is_master_triggered_~__retres1~0#1 := 0; 71518#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71519#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71657#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 71658#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71450#L665-42 assume 1 == ~t1_pc~0; 71411#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 71413#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71599#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70253#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70254#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71723#L684-42 assume !(1 == ~t2_pc~0); 71104#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 71103#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71713#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70882#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70883#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71005#L703-42 assume 1 == ~t3_pc~0; 71203#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 71204#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70522#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70523#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 71297#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70917#L722-42 assume !(1 == ~t4_pc~0); 70919#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 71328#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70571#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70398#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70399#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71693#L741-42 assume 1 == ~t5_pc~0; 71635#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 70780#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70781#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 71726#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70688#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70689#L760-42 assume !(1 == ~t6_pc~0); 70823#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 70958#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70959#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 71347#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 70640#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70641#L779-42 assume !(1 == ~t7_pc~0); 71417#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 71418#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70327#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70328#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70181#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70182#L798-42 assume !(1 == ~t8_pc~0); 69792#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 69793#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 71536#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70982#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70012#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70013#L817-42 assume !(1 == ~t9_pc~0); 70787#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 70296#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70297#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70423#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 71228#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 71229#L836-42 assume 1 == ~t10_pc~0; 71321#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 70334#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70335#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 71636#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 71637#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 71678#L855-42 assume 1 == ~t11_pc~0; 71691#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69885#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69886#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70635#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 71398#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 70499#L874-42 assume !(1 == ~t12_pc~0); 70501#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 70742#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69800#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69801#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 70054#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70055#L893-42 assume 1 == ~t13_pc~0; 71258#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 71039#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 71054#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 70956#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 70428#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 70429#L912-42 assume !(1 == ~t14_pc~0); 71238#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 69746#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 69747#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 71327#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 70174#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70175#L1495-3 assume !(1 == ~M_E~0); 70790#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71218#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71311#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70404#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70367#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70368#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 71025#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 71248#L1530-3 assume !(1 == ~T8_E~0); 70213#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70214#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 70251#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 71508#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 71617#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 70657#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 70658#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 71273#L1570-3 assume !(1 == ~E_2~0); 71224#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 71225#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 71580#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 71624#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 71670#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 71047#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 71048#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 71523#L1610-3 assume !(1 == ~E_10~0); 70410#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 70411#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 71015#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 71016#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 70920#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 70351#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 69956#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 70694#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 71250#L2036 assume !(0 == start_simulation_~tmp~3#1); 71251#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 71403#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 70563#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 71581#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 70963#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 70964#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 71684#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 71685#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 70518#L2017-2 [2022-02-21 04:25:00,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:00,548 INFO L85 PathProgramCache]: Analyzing trace with hash -383452696, now seen corresponding path program 1 times [2022-02-21 04:25:00,548 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:00,548 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [650423087] [2022-02-21 04:25:00,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:00,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:00,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:00,567 INFO L290 TraceCheckUtils]: 0: Hoare triple {75834#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {75834#true} is VALID [2022-02-21 04:25:00,567 INFO L290 TraceCheckUtils]: 1: Hoare triple {75834#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,567 INFO L290 TraceCheckUtils]: 2: Hoare triple {75836#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,568 INFO L290 TraceCheckUtils]: 3: Hoare triple {75836#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,568 INFO L290 TraceCheckUtils]: 4: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,568 INFO L290 TraceCheckUtils]: 5: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,568 INFO L290 TraceCheckUtils]: 6: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,569 INFO L290 TraceCheckUtils]: 7: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,569 INFO L290 TraceCheckUtils]: 8: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,569 INFO L290 TraceCheckUtils]: 9: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,569 INFO L290 TraceCheckUtils]: 10: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,570 INFO L290 TraceCheckUtils]: 11: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,570 INFO L290 TraceCheckUtils]: 12: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,570 INFO L290 TraceCheckUtils]: 13: Hoare triple {75836#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {75836#(= ~t10_i~0 1)} is VALID [2022-02-21 04:25:00,570 INFO L290 TraceCheckUtils]: 14: Hoare triple {75836#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {75835#false} is VALID [2022-02-21 04:25:00,571 INFO L290 TraceCheckUtils]: 15: Hoare triple {75835#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {75835#false} is VALID [2022-02-21 04:25:00,571 INFO L290 TraceCheckUtils]: 16: Hoare triple {75835#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {75835#false} is VALID [2022-02-21 04:25:00,571 INFO L290 TraceCheckUtils]: 17: Hoare triple {75835#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {75835#false} is VALID [2022-02-21 04:25:00,571 INFO L290 TraceCheckUtils]: 18: Hoare triple {75835#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {75835#false} is VALID [2022-02-21 04:25:00,571 INFO L290 TraceCheckUtils]: 19: Hoare triple {75835#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {75835#false} is VALID [2022-02-21 04:25:00,571 INFO L290 TraceCheckUtils]: 20: Hoare triple {75835#false} assume !(0 == ~M_E~0); {75835#false} is VALID [2022-02-21 04:25:00,571 INFO L290 TraceCheckUtils]: 21: Hoare triple {75835#false} assume !(0 == ~T1_E~0); {75835#false} is VALID [2022-02-21 04:25:00,571 INFO L290 TraceCheckUtils]: 22: Hoare triple {75835#false} assume !(0 == ~T2_E~0); {75835#false} is VALID [2022-02-21 04:25:00,571 INFO L290 TraceCheckUtils]: 23: Hoare triple {75835#false} assume !(0 == ~T3_E~0); {75835#false} is VALID [2022-02-21 04:25:00,572 INFO L290 TraceCheckUtils]: 24: Hoare triple {75835#false} assume !(0 == ~T4_E~0); {75835#false} is VALID [2022-02-21 04:25:00,572 INFO L290 TraceCheckUtils]: 25: Hoare triple {75835#false} assume !(0 == ~T5_E~0); {75835#false} is VALID [2022-02-21 04:25:00,572 INFO L290 TraceCheckUtils]: 26: Hoare triple {75835#false} assume !(0 == ~T6_E~0); {75835#false} is VALID [2022-02-21 04:25:00,572 INFO L290 TraceCheckUtils]: 27: Hoare triple {75835#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {75835#false} is VALID [2022-02-21 04:25:00,572 INFO L290 TraceCheckUtils]: 28: Hoare triple {75835#false} assume !(0 == ~T8_E~0); {75835#false} is VALID [2022-02-21 04:25:00,572 INFO L290 TraceCheckUtils]: 29: Hoare triple {75835#false} assume !(0 == ~T9_E~0); {75835#false} is VALID [2022-02-21 04:25:00,572 INFO L290 TraceCheckUtils]: 30: Hoare triple {75835#false} assume !(0 == ~T10_E~0); {75835#false} is VALID [2022-02-21 04:25:00,572 INFO L290 TraceCheckUtils]: 31: Hoare triple {75835#false} assume !(0 == ~T11_E~0); {75835#false} is VALID [2022-02-21 04:25:00,572 INFO L290 TraceCheckUtils]: 32: Hoare triple {75835#false} assume !(0 == ~T12_E~0); {75835#false} is VALID [2022-02-21 04:25:00,573 INFO L290 TraceCheckUtils]: 33: Hoare triple {75835#false} assume !(0 == ~T13_E~0); {75835#false} is VALID [2022-02-21 04:25:00,573 INFO L290 TraceCheckUtils]: 34: Hoare triple {75835#false} assume !(0 == ~T14_E~0); {75835#false} is VALID [2022-02-21 04:25:00,573 INFO L290 TraceCheckUtils]: 35: Hoare triple {75835#false} assume 0 == ~E_1~0;~E_1~0 := 1; {75835#false} is VALID [2022-02-21 04:25:00,573 INFO L290 TraceCheckUtils]: 36: Hoare triple {75835#false} assume !(0 == ~E_2~0); {75835#false} is VALID [2022-02-21 04:25:00,573 INFO L290 TraceCheckUtils]: 37: Hoare triple {75835#false} assume !(0 == ~E_3~0); {75835#false} is VALID [2022-02-21 04:25:00,573 INFO L290 TraceCheckUtils]: 38: Hoare triple {75835#false} assume !(0 == ~E_4~0); {75835#false} is VALID [2022-02-21 04:25:00,573 INFO L290 TraceCheckUtils]: 39: Hoare triple {75835#false} assume !(0 == ~E_5~0); {75835#false} is VALID [2022-02-21 04:25:00,573 INFO L290 TraceCheckUtils]: 40: Hoare triple {75835#false} assume !(0 == ~E_6~0); {75835#false} is VALID [2022-02-21 04:25:00,573 INFO L290 TraceCheckUtils]: 41: Hoare triple {75835#false} assume !(0 == ~E_7~0); {75835#false} is VALID [2022-02-21 04:25:00,574 INFO L290 TraceCheckUtils]: 42: Hoare triple {75835#false} assume !(0 == ~E_8~0); {75835#false} is VALID [2022-02-21 04:25:00,574 INFO L290 TraceCheckUtils]: 43: Hoare triple {75835#false} assume 0 == ~E_9~0;~E_9~0 := 1; {75835#false} is VALID [2022-02-21 04:25:00,574 INFO L290 TraceCheckUtils]: 44: Hoare triple {75835#false} assume !(0 == ~E_10~0); {75835#false} is VALID [2022-02-21 04:25:00,574 INFO L290 TraceCheckUtils]: 45: Hoare triple {75835#false} assume !(0 == ~E_11~0); {75835#false} is VALID [2022-02-21 04:25:00,574 INFO L290 TraceCheckUtils]: 46: Hoare triple {75835#false} assume !(0 == ~E_12~0); {75835#false} is VALID [2022-02-21 04:25:00,574 INFO L290 TraceCheckUtils]: 47: Hoare triple {75835#false} assume !(0 == ~E_13~0); {75835#false} is VALID [2022-02-21 04:25:00,574 INFO L290 TraceCheckUtils]: 48: Hoare triple {75835#false} assume !(0 == ~E_14~0); {75835#false} is VALID [2022-02-21 04:25:00,574 INFO L290 TraceCheckUtils]: 49: Hoare triple {75835#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {75835#false} is VALID [2022-02-21 04:25:00,574 INFO L290 TraceCheckUtils]: 50: Hoare triple {75835#false} assume 1 == ~m_pc~0; {75835#false} is VALID [2022-02-21 04:25:00,575 INFO L290 TraceCheckUtils]: 51: Hoare triple {75835#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {75835#false} is VALID [2022-02-21 04:25:00,575 INFO L290 TraceCheckUtils]: 52: Hoare triple {75835#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {75835#false} is VALID [2022-02-21 04:25:00,575 INFO L290 TraceCheckUtils]: 53: Hoare triple {75835#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {75835#false} is VALID [2022-02-21 04:25:00,575 INFO L290 TraceCheckUtils]: 54: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp~1#1); {75835#false} is VALID [2022-02-21 04:25:00,575 INFO L290 TraceCheckUtils]: 55: Hoare triple {75835#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {75835#false} is VALID [2022-02-21 04:25:00,575 INFO L290 TraceCheckUtils]: 56: Hoare triple {75835#false} assume !(1 == ~t1_pc~0); {75835#false} is VALID [2022-02-21 04:25:00,575 INFO L290 TraceCheckUtils]: 57: Hoare triple {75835#false} is_transmit1_triggered_~__retres1~1#1 := 0; {75835#false} is VALID [2022-02-21 04:25:00,575 INFO L290 TraceCheckUtils]: 58: Hoare triple {75835#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {75835#false} is VALID [2022-02-21 04:25:00,575 INFO L290 TraceCheckUtils]: 59: Hoare triple {75835#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {75835#false} is VALID [2022-02-21 04:25:00,576 INFO L290 TraceCheckUtils]: 60: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___0~0#1); {75835#false} is VALID [2022-02-21 04:25:00,576 INFO L290 TraceCheckUtils]: 61: Hoare triple {75835#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {75835#false} is VALID [2022-02-21 04:25:00,576 INFO L290 TraceCheckUtils]: 62: Hoare triple {75835#false} assume 1 == ~t2_pc~0; {75835#false} is VALID [2022-02-21 04:25:00,576 INFO L290 TraceCheckUtils]: 63: Hoare triple {75835#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {75835#false} is VALID [2022-02-21 04:25:00,576 INFO L290 TraceCheckUtils]: 64: Hoare triple {75835#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {75835#false} is VALID [2022-02-21 04:25:00,576 INFO L290 TraceCheckUtils]: 65: Hoare triple {75835#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {75835#false} is VALID [2022-02-21 04:25:00,576 INFO L290 TraceCheckUtils]: 66: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___1~0#1); {75835#false} is VALID [2022-02-21 04:25:00,576 INFO L290 TraceCheckUtils]: 67: Hoare triple {75835#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {75835#false} is VALID [2022-02-21 04:25:00,576 INFO L290 TraceCheckUtils]: 68: Hoare triple {75835#false} assume !(1 == ~t3_pc~0); {75835#false} is VALID [2022-02-21 04:25:00,577 INFO L290 TraceCheckUtils]: 69: Hoare triple {75835#false} is_transmit3_triggered_~__retres1~3#1 := 0; {75835#false} is VALID [2022-02-21 04:25:00,577 INFO L290 TraceCheckUtils]: 70: Hoare triple {75835#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {75835#false} is VALID [2022-02-21 04:25:00,577 INFO L290 TraceCheckUtils]: 71: Hoare triple {75835#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {75835#false} is VALID [2022-02-21 04:25:00,577 INFO L290 TraceCheckUtils]: 72: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___2~0#1); {75835#false} is VALID [2022-02-21 04:25:00,577 INFO L290 TraceCheckUtils]: 73: Hoare triple {75835#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {75835#false} is VALID [2022-02-21 04:25:00,577 INFO L290 TraceCheckUtils]: 74: Hoare triple {75835#false} assume 1 == ~t4_pc~0; {75835#false} is VALID [2022-02-21 04:25:00,577 INFO L290 TraceCheckUtils]: 75: Hoare triple {75835#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {75835#false} is VALID [2022-02-21 04:25:00,577 INFO L290 TraceCheckUtils]: 76: Hoare triple {75835#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {75835#false} is VALID [2022-02-21 04:25:00,577 INFO L290 TraceCheckUtils]: 77: Hoare triple {75835#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {75835#false} is VALID [2022-02-21 04:25:00,578 INFO L290 TraceCheckUtils]: 78: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___3~0#1); {75835#false} is VALID [2022-02-21 04:25:00,578 INFO L290 TraceCheckUtils]: 79: Hoare triple {75835#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {75835#false} is VALID [2022-02-21 04:25:00,578 INFO L290 TraceCheckUtils]: 80: Hoare triple {75835#false} assume 1 == ~t5_pc~0; {75835#false} is VALID [2022-02-21 04:25:00,578 INFO L290 TraceCheckUtils]: 81: Hoare triple {75835#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {75835#false} is VALID [2022-02-21 04:25:00,578 INFO L290 TraceCheckUtils]: 82: Hoare triple {75835#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {75835#false} is VALID [2022-02-21 04:25:00,578 INFO L290 TraceCheckUtils]: 83: Hoare triple {75835#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {75835#false} is VALID [2022-02-21 04:25:00,578 INFO L290 TraceCheckUtils]: 84: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___4~0#1); {75835#false} is VALID [2022-02-21 04:25:00,578 INFO L290 TraceCheckUtils]: 85: Hoare triple {75835#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {75835#false} is VALID [2022-02-21 04:25:00,579 INFO L290 TraceCheckUtils]: 86: Hoare triple {75835#false} assume !(1 == ~t6_pc~0); {75835#false} is VALID [2022-02-21 04:25:00,579 INFO L290 TraceCheckUtils]: 87: Hoare triple {75835#false} is_transmit6_triggered_~__retres1~6#1 := 0; {75835#false} is VALID [2022-02-21 04:25:00,579 INFO L290 TraceCheckUtils]: 88: Hoare triple {75835#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {75835#false} is VALID [2022-02-21 04:25:00,579 INFO L290 TraceCheckUtils]: 89: Hoare triple {75835#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {75835#false} is VALID [2022-02-21 04:25:00,579 INFO L290 TraceCheckUtils]: 90: Hoare triple {75835#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {75835#false} is VALID [2022-02-21 04:25:00,579 INFO L290 TraceCheckUtils]: 91: Hoare triple {75835#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {75835#false} is VALID [2022-02-21 04:25:00,579 INFO L290 TraceCheckUtils]: 92: Hoare triple {75835#false} assume 1 == ~t7_pc~0; {75835#false} is VALID [2022-02-21 04:25:00,579 INFO L290 TraceCheckUtils]: 93: Hoare triple {75835#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {75835#false} is VALID [2022-02-21 04:25:00,579 INFO L290 TraceCheckUtils]: 94: Hoare triple {75835#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {75835#false} is VALID [2022-02-21 04:25:00,580 INFO L290 TraceCheckUtils]: 95: Hoare triple {75835#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {75835#false} is VALID [2022-02-21 04:25:00,580 INFO L290 TraceCheckUtils]: 96: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___6~0#1); {75835#false} is VALID [2022-02-21 04:25:00,580 INFO L290 TraceCheckUtils]: 97: Hoare triple {75835#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {75835#false} is VALID [2022-02-21 04:25:00,580 INFO L290 TraceCheckUtils]: 98: Hoare triple {75835#false} assume !(1 == ~t8_pc~0); {75835#false} is VALID [2022-02-21 04:25:00,580 INFO L290 TraceCheckUtils]: 99: Hoare triple {75835#false} is_transmit8_triggered_~__retres1~8#1 := 0; {75835#false} is VALID [2022-02-21 04:25:00,580 INFO L290 TraceCheckUtils]: 100: Hoare triple {75835#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {75835#false} is VALID [2022-02-21 04:25:00,580 INFO L290 TraceCheckUtils]: 101: Hoare triple {75835#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {75835#false} is VALID [2022-02-21 04:25:00,580 INFO L290 TraceCheckUtils]: 102: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___7~0#1); {75835#false} is VALID [2022-02-21 04:25:00,580 INFO L290 TraceCheckUtils]: 103: Hoare triple {75835#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {75835#false} is VALID [2022-02-21 04:25:00,581 INFO L290 TraceCheckUtils]: 104: Hoare triple {75835#false} assume 1 == ~t9_pc~0; {75835#false} is VALID [2022-02-21 04:25:00,581 INFO L290 TraceCheckUtils]: 105: Hoare triple {75835#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {75835#false} is VALID [2022-02-21 04:25:00,581 INFO L290 TraceCheckUtils]: 106: Hoare triple {75835#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {75835#false} is VALID [2022-02-21 04:25:00,581 INFO L290 TraceCheckUtils]: 107: Hoare triple {75835#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {75835#false} is VALID [2022-02-21 04:25:00,581 INFO L290 TraceCheckUtils]: 108: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___8~0#1); {75835#false} is VALID [2022-02-21 04:25:00,581 INFO L290 TraceCheckUtils]: 109: Hoare triple {75835#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {75835#false} is VALID [2022-02-21 04:25:00,581 INFO L290 TraceCheckUtils]: 110: Hoare triple {75835#false} assume !(1 == ~t10_pc~0); {75835#false} is VALID [2022-02-21 04:25:00,581 INFO L290 TraceCheckUtils]: 111: Hoare triple {75835#false} is_transmit10_triggered_~__retres1~10#1 := 0; {75835#false} is VALID [2022-02-21 04:25:00,581 INFO L290 TraceCheckUtils]: 112: Hoare triple {75835#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {75835#false} is VALID [2022-02-21 04:25:00,582 INFO L290 TraceCheckUtils]: 113: Hoare triple {75835#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {75835#false} is VALID [2022-02-21 04:25:00,582 INFO L290 TraceCheckUtils]: 114: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___9~0#1); {75835#false} is VALID [2022-02-21 04:25:00,582 INFO L290 TraceCheckUtils]: 115: Hoare triple {75835#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {75835#false} is VALID [2022-02-21 04:25:00,582 INFO L290 TraceCheckUtils]: 116: Hoare triple {75835#false} assume 1 == ~t11_pc~0; {75835#false} is VALID [2022-02-21 04:25:00,582 INFO L290 TraceCheckUtils]: 117: Hoare triple {75835#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {75835#false} is VALID [2022-02-21 04:25:00,582 INFO L290 TraceCheckUtils]: 118: Hoare triple {75835#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {75835#false} is VALID [2022-02-21 04:25:00,582 INFO L290 TraceCheckUtils]: 119: Hoare triple {75835#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {75835#false} is VALID [2022-02-21 04:25:00,582 INFO L290 TraceCheckUtils]: 120: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___10~0#1); {75835#false} is VALID [2022-02-21 04:25:00,582 INFO L290 TraceCheckUtils]: 121: Hoare triple {75835#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {75835#false} is VALID [2022-02-21 04:25:00,583 INFO L290 TraceCheckUtils]: 122: Hoare triple {75835#false} assume !(1 == ~t12_pc~0); {75835#false} is VALID [2022-02-21 04:25:00,583 INFO L290 TraceCheckUtils]: 123: Hoare triple {75835#false} is_transmit12_triggered_~__retres1~12#1 := 0; {75835#false} is VALID [2022-02-21 04:25:00,583 INFO L290 TraceCheckUtils]: 124: Hoare triple {75835#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {75835#false} is VALID [2022-02-21 04:25:00,583 INFO L290 TraceCheckUtils]: 125: Hoare triple {75835#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {75835#false} is VALID [2022-02-21 04:25:00,583 INFO L290 TraceCheckUtils]: 126: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___11~0#1); {75835#false} is VALID [2022-02-21 04:25:00,583 INFO L290 TraceCheckUtils]: 127: Hoare triple {75835#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {75835#false} is VALID [2022-02-21 04:25:00,583 INFO L290 TraceCheckUtils]: 128: Hoare triple {75835#false} assume 1 == ~t13_pc~0; {75835#false} is VALID [2022-02-21 04:25:00,583 INFO L290 TraceCheckUtils]: 129: Hoare triple {75835#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {75835#false} is VALID [2022-02-21 04:25:00,583 INFO L290 TraceCheckUtils]: 130: Hoare triple {75835#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {75835#false} is VALID [2022-02-21 04:25:00,584 INFO L290 TraceCheckUtils]: 131: Hoare triple {75835#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {75835#false} is VALID [2022-02-21 04:25:00,584 INFO L290 TraceCheckUtils]: 132: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___12~0#1); {75835#false} is VALID [2022-02-21 04:25:00,584 INFO L290 TraceCheckUtils]: 133: Hoare triple {75835#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {75835#false} is VALID [2022-02-21 04:25:00,584 INFO L290 TraceCheckUtils]: 134: Hoare triple {75835#false} assume 1 == ~t14_pc~0; {75835#false} is VALID [2022-02-21 04:25:00,584 INFO L290 TraceCheckUtils]: 135: Hoare triple {75835#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {75835#false} is VALID [2022-02-21 04:25:00,584 INFO L290 TraceCheckUtils]: 136: Hoare triple {75835#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {75835#false} is VALID [2022-02-21 04:25:00,584 INFO L290 TraceCheckUtils]: 137: Hoare triple {75835#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {75835#false} is VALID [2022-02-21 04:25:00,584 INFO L290 TraceCheckUtils]: 138: Hoare triple {75835#false} assume !(0 != activate_threads_~tmp___13~0#1); {75835#false} is VALID [2022-02-21 04:25:00,584 INFO L290 TraceCheckUtils]: 139: Hoare triple {75835#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {75835#false} is VALID [2022-02-21 04:25:00,585 INFO L290 TraceCheckUtils]: 140: Hoare triple {75835#false} assume 1 == ~M_E~0;~M_E~0 := 2; {75835#false} is VALID [2022-02-21 04:25:00,585 INFO L290 TraceCheckUtils]: 141: Hoare triple {75835#false} assume !(1 == ~T1_E~0); {75835#false} is VALID [2022-02-21 04:25:00,585 INFO L290 TraceCheckUtils]: 142: Hoare triple {75835#false} assume !(1 == ~T2_E~0); {75835#false} is VALID [2022-02-21 04:25:00,585 INFO L290 TraceCheckUtils]: 143: Hoare triple {75835#false} assume !(1 == ~T3_E~0); {75835#false} is VALID [2022-02-21 04:25:00,585 INFO L290 TraceCheckUtils]: 144: Hoare triple {75835#false} assume !(1 == ~T4_E~0); {75835#false} is VALID [2022-02-21 04:25:00,585 INFO L290 TraceCheckUtils]: 145: Hoare triple {75835#false} assume !(1 == ~T5_E~0); {75835#false} is VALID [2022-02-21 04:25:00,585 INFO L290 TraceCheckUtils]: 146: Hoare triple {75835#false} assume !(1 == ~T6_E~0); {75835#false} is VALID [2022-02-21 04:25:00,585 INFO L290 TraceCheckUtils]: 147: Hoare triple {75835#false} assume !(1 == ~T7_E~0); {75835#false} is VALID [2022-02-21 04:25:00,585 INFO L290 TraceCheckUtils]: 148: Hoare triple {75835#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {75835#false} is VALID [2022-02-21 04:25:00,586 INFO L290 TraceCheckUtils]: 149: Hoare triple {75835#false} assume !(1 == ~T9_E~0); {75835#false} is VALID [2022-02-21 04:25:00,586 INFO L290 TraceCheckUtils]: 150: Hoare triple {75835#false} assume !(1 == ~T10_E~0); {75835#false} is VALID [2022-02-21 04:25:00,586 INFO L290 TraceCheckUtils]: 151: Hoare triple {75835#false} assume !(1 == ~T11_E~0); {75835#false} is VALID [2022-02-21 04:25:00,586 INFO L290 TraceCheckUtils]: 152: Hoare triple {75835#false} assume !(1 == ~T12_E~0); {75835#false} is VALID [2022-02-21 04:25:00,586 INFO L290 TraceCheckUtils]: 153: Hoare triple {75835#false} assume !(1 == ~T13_E~0); {75835#false} is VALID [2022-02-21 04:25:00,586 INFO L290 TraceCheckUtils]: 154: Hoare triple {75835#false} assume !(1 == ~T14_E~0); {75835#false} is VALID [2022-02-21 04:25:00,586 INFO L290 TraceCheckUtils]: 155: Hoare triple {75835#false} assume !(1 == ~E_1~0); {75835#false} is VALID [2022-02-21 04:25:00,586 INFO L290 TraceCheckUtils]: 156: Hoare triple {75835#false} assume 1 == ~E_2~0;~E_2~0 := 2; {75835#false} is VALID [2022-02-21 04:25:00,586 INFO L290 TraceCheckUtils]: 157: Hoare triple {75835#false} assume !(1 == ~E_3~0); {75835#false} is VALID [2022-02-21 04:25:00,587 INFO L290 TraceCheckUtils]: 158: Hoare triple {75835#false} assume !(1 == ~E_4~0); {75835#false} is VALID [2022-02-21 04:25:00,587 INFO L290 TraceCheckUtils]: 159: Hoare triple {75835#false} assume !(1 == ~E_5~0); {75835#false} is VALID [2022-02-21 04:25:00,587 INFO L290 TraceCheckUtils]: 160: Hoare triple {75835#false} assume !(1 == ~E_6~0); {75835#false} is VALID [2022-02-21 04:25:00,587 INFO L290 TraceCheckUtils]: 161: Hoare triple {75835#false} assume !(1 == ~E_7~0); {75835#false} is VALID [2022-02-21 04:25:00,587 INFO L290 TraceCheckUtils]: 162: Hoare triple {75835#false} assume !(1 == ~E_8~0); {75835#false} is VALID [2022-02-21 04:25:00,587 INFO L290 TraceCheckUtils]: 163: Hoare triple {75835#false} assume !(1 == ~E_9~0); {75835#false} is VALID [2022-02-21 04:25:00,587 INFO L290 TraceCheckUtils]: 164: Hoare triple {75835#false} assume 1 == ~E_10~0;~E_10~0 := 2; {75835#false} is VALID [2022-02-21 04:25:00,587 INFO L290 TraceCheckUtils]: 165: Hoare triple {75835#false} assume !(1 == ~E_11~0); {75835#false} is VALID [2022-02-21 04:25:00,587 INFO L290 TraceCheckUtils]: 166: Hoare triple {75835#false} assume !(1 == ~E_12~0); {75835#false} is VALID [2022-02-21 04:25:00,588 INFO L290 TraceCheckUtils]: 167: Hoare triple {75835#false} assume !(1 == ~E_13~0); {75835#false} is VALID [2022-02-21 04:25:00,588 INFO L290 TraceCheckUtils]: 168: Hoare triple {75835#false} assume !(1 == ~E_14~0); {75835#false} is VALID [2022-02-21 04:25:00,588 INFO L290 TraceCheckUtils]: 169: Hoare triple {75835#false} assume { :end_inline_reset_delta_events } true; {75835#false} is VALID [2022-02-21 04:25:00,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:00,588 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:00,588 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [650423087] [2022-02-21 04:25:00,589 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [650423087] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:00,589 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:00,589 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:00,589 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452361593] [2022-02-21 04:25:00,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:00,589 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:00,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:00,590 INFO L85 PathProgramCache]: Analyzing trace with hash -1178019864, now seen corresponding path program 1 times [2022-02-21 04:25:00,590 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:00,590 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990820200] [2022-02-21 04:25:00,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:00,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:00,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:00,613 INFO L290 TraceCheckUtils]: 0: Hoare triple {75837#true} assume !false; {75837#true} is VALID [2022-02-21 04:25:00,613 INFO L290 TraceCheckUtils]: 1: Hoare triple {75837#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {75837#true} is VALID [2022-02-21 04:25:00,613 INFO L290 TraceCheckUtils]: 2: Hoare triple {75837#true} assume !false; {75837#true} is VALID [2022-02-21 04:25:00,614 INFO L290 TraceCheckUtils]: 3: Hoare triple {75837#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {75837#true} is VALID [2022-02-21 04:25:00,614 INFO L290 TraceCheckUtils]: 4: Hoare triple {75837#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {75837#true} is VALID [2022-02-21 04:25:00,614 INFO L290 TraceCheckUtils]: 5: Hoare triple {75837#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {75837#true} is VALID [2022-02-21 04:25:00,614 INFO L290 TraceCheckUtils]: 6: Hoare triple {75837#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {75837#true} is VALID [2022-02-21 04:25:00,614 INFO L290 TraceCheckUtils]: 7: Hoare triple {75837#true} assume !(0 != eval_~tmp~0#1); {75837#true} is VALID [2022-02-21 04:25:00,614 INFO L290 TraceCheckUtils]: 8: Hoare triple {75837#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {75837#true} is VALID [2022-02-21 04:25:00,614 INFO L290 TraceCheckUtils]: 9: Hoare triple {75837#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {75837#true} is VALID [2022-02-21 04:25:00,615 INFO L290 TraceCheckUtils]: 10: Hoare triple {75837#true} assume 0 == ~M_E~0;~M_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,615 INFO L290 TraceCheckUtils]: 11: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,615 INFO L290 TraceCheckUtils]: 12: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,615 INFO L290 TraceCheckUtils]: 13: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,616 INFO L290 TraceCheckUtils]: 14: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,616 INFO L290 TraceCheckUtils]: 15: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,616 INFO L290 TraceCheckUtils]: 16: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,616 INFO L290 TraceCheckUtils]: 17: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,617 INFO L290 TraceCheckUtils]: 18: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,617 INFO L290 TraceCheckUtils]: 19: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,617 INFO L290 TraceCheckUtils]: 20: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,617 INFO L290 TraceCheckUtils]: 21: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,618 INFO L290 TraceCheckUtils]: 22: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,618 INFO L290 TraceCheckUtils]: 23: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,618 INFO L290 TraceCheckUtils]: 24: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,618 INFO L290 TraceCheckUtils]: 25: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,619 INFO L290 TraceCheckUtils]: 26: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,619 INFO L290 TraceCheckUtils]: 27: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,619 INFO L290 TraceCheckUtils]: 28: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,619 INFO L290 TraceCheckUtils]: 29: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,620 INFO L290 TraceCheckUtils]: 30: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,620 INFO L290 TraceCheckUtils]: 31: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,620 INFO L290 TraceCheckUtils]: 32: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,620 INFO L290 TraceCheckUtils]: 33: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,621 INFO L290 TraceCheckUtils]: 34: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,621 INFO L290 TraceCheckUtils]: 35: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,621 INFO L290 TraceCheckUtils]: 36: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,621 INFO L290 TraceCheckUtils]: 37: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,622 INFO L290 TraceCheckUtils]: 38: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,622 INFO L290 TraceCheckUtils]: 39: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,622 INFO L290 TraceCheckUtils]: 40: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,622 INFO L290 TraceCheckUtils]: 41: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,623 INFO L290 TraceCheckUtils]: 42: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,623 INFO L290 TraceCheckUtils]: 43: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,623 INFO L290 TraceCheckUtils]: 44: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,623 INFO L290 TraceCheckUtils]: 45: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,624 INFO L290 TraceCheckUtils]: 46: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,624 INFO L290 TraceCheckUtils]: 47: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,624 INFO L290 TraceCheckUtils]: 48: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,624 INFO L290 TraceCheckUtils]: 49: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,631 INFO L290 TraceCheckUtils]: 50: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,632 INFO L290 TraceCheckUtils]: 51: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,632 INFO L290 TraceCheckUtils]: 52: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,632 INFO L290 TraceCheckUtils]: 53: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,632 INFO L290 TraceCheckUtils]: 54: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,633 INFO L290 TraceCheckUtils]: 55: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,633 INFO L290 TraceCheckUtils]: 56: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,633 INFO L290 TraceCheckUtils]: 57: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,633 INFO L290 TraceCheckUtils]: 58: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,634 INFO L290 TraceCheckUtils]: 59: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,634 INFO L290 TraceCheckUtils]: 60: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,634 INFO L290 TraceCheckUtils]: 61: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,634 INFO L290 TraceCheckUtils]: 62: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,635 INFO L290 TraceCheckUtils]: 63: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,635 INFO L290 TraceCheckUtils]: 64: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,635 INFO L290 TraceCheckUtils]: 65: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,635 INFO L290 TraceCheckUtils]: 66: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,636 INFO L290 TraceCheckUtils]: 67: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,636 INFO L290 TraceCheckUtils]: 68: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,636 INFO L290 TraceCheckUtils]: 69: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,637 INFO L290 TraceCheckUtils]: 70: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,637 INFO L290 TraceCheckUtils]: 71: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,637 INFO L290 TraceCheckUtils]: 72: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,637 INFO L290 TraceCheckUtils]: 73: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,638 INFO L290 TraceCheckUtils]: 74: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,638 INFO L290 TraceCheckUtils]: 75: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,638 INFO L290 TraceCheckUtils]: 76: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,638 INFO L290 TraceCheckUtils]: 77: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,639 INFO L290 TraceCheckUtils]: 78: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,639 INFO L290 TraceCheckUtils]: 79: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,639 INFO L290 TraceCheckUtils]: 80: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,639 INFO L290 TraceCheckUtils]: 81: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,640 INFO L290 TraceCheckUtils]: 82: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,640 INFO L290 TraceCheckUtils]: 83: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,640 INFO L290 TraceCheckUtils]: 84: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,640 INFO L290 TraceCheckUtils]: 85: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,641 INFO L290 TraceCheckUtils]: 86: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,641 INFO L290 TraceCheckUtils]: 87: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,641 INFO L290 TraceCheckUtils]: 88: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,641 INFO L290 TraceCheckUtils]: 89: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,642 INFO L290 TraceCheckUtils]: 90: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,642 INFO L290 TraceCheckUtils]: 91: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,642 INFO L290 TraceCheckUtils]: 92: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,642 INFO L290 TraceCheckUtils]: 93: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,643 INFO L290 TraceCheckUtils]: 94: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,643 INFO L290 TraceCheckUtils]: 95: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,643 INFO L290 TraceCheckUtils]: 96: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,643 INFO L290 TraceCheckUtils]: 97: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,644 INFO L290 TraceCheckUtils]: 98: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,644 INFO L290 TraceCheckUtils]: 99: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,644 INFO L290 TraceCheckUtils]: 100: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,644 INFO L290 TraceCheckUtils]: 101: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,645 INFO L290 TraceCheckUtils]: 102: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,645 INFO L290 TraceCheckUtils]: 103: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,645 INFO L290 TraceCheckUtils]: 104: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,645 INFO L290 TraceCheckUtils]: 105: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,646 INFO L290 TraceCheckUtils]: 106: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,646 INFO L290 TraceCheckUtils]: 107: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,646 INFO L290 TraceCheckUtils]: 108: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,646 INFO L290 TraceCheckUtils]: 109: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,647 INFO L290 TraceCheckUtils]: 110: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,647 INFO L290 TraceCheckUtils]: 111: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,647 INFO L290 TraceCheckUtils]: 112: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,647 INFO L290 TraceCheckUtils]: 113: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,648 INFO L290 TraceCheckUtils]: 114: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,648 INFO L290 TraceCheckUtils]: 115: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,648 INFO L290 TraceCheckUtils]: 116: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,648 INFO L290 TraceCheckUtils]: 117: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,649 INFO L290 TraceCheckUtils]: 118: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,649 INFO L290 TraceCheckUtils]: 119: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,649 INFO L290 TraceCheckUtils]: 120: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,649 INFO L290 TraceCheckUtils]: 121: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,650 INFO L290 TraceCheckUtils]: 122: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,650 INFO L290 TraceCheckUtils]: 123: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,650 INFO L290 TraceCheckUtils]: 124: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,650 INFO L290 TraceCheckUtils]: 125: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,651 INFO L290 TraceCheckUtils]: 126: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,651 INFO L290 TraceCheckUtils]: 127: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,651 INFO L290 TraceCheckUtils]: 128: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,651 INFO L290 TraceCheckUtils]: 129: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {75839#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:00,652 INFO L290 TraceCheckUtils]: 130: Hoare triple {75839#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {75838#false} is VALID [2022-02-21 04:25:00,652 INFO L290 TraceCheckUtils]: 131: Hoare triple {75838#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,652 INFO L290 TraceCheckUtils]: 132: Hoare triple {75838#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,652 INFO L290 TraceCheckUtils]: 133: Hoare triple {75838#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,652 INFO L290 TraceCheckUtils]: 134: Hoare triple {75838#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,652 INFO L290 TraceCheckUtils]: 135: Hoare triple {75838#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,652 INFO L290 TraceCheckUtils]: 136: Hoare triple {75838#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,652 INFO L290 TraceCheckUtils]: 137: Hoare triple {75838#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,652 INFO L290 TraceCheckUtils]: 138: Hoare triple {75838#false} assume !(1 == ~T8_E~0); {75838#false} is VALID [2022-02-21 04:25:00,653 INFO L290 TraceCheckUtils]: 139: Hoare triple {75838#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,653 INFO L290 TraceCheckUtils]: 140: Hoare triple {75838#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,653 INFO L290 TraceCheckUtils]: 141: Hoare triple {75838#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,653 INFO L290 TraceCheckUtils]: 142: Hoare triple {75838#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,653 INFO L290 TraceCheckUtils]: 143: Hoare triple {75838#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,653 INFO L290 TraceCheckUtils]: 144: Hoare triple {75838#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,653 INFO L290 TraceCheckUtils]: 145: Hoare triple {75838#false} assume 1 == ~E_1~0;~E_1~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,653 INFO L290 TraceCheckUtils]: 146: Hoare triple {75838#false} assume !(1 == ~E_2~0); {75838#false} is VALID [2022-02-21 04:25:00,653 INFO L290 TraceCheckUtils]: 147: Hoare triple {75838#false} assume 1 == ~E_3~0;~E_3~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 148: Hoare triple {75838#false} assume 1 == ~E_4~0;~E_4~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 149: Hoare triple {75838#false} assume 1 == ~E_5~0;~E_5~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 150: Hoare triple {75838#false} assume 1 == ~E_6~0;~E_6~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 151: Hoare triple {75838#false} assume 1 == ~E_7~0;~E_7~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 152: Hoare triple {75838#false} assume 1 == ~E_8~0;~E_8~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 153: Hoare triple {75838#false} assume 1 == ~E_9~0;~E_9~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 154: Hoare triple {75838#false} assume !(1 == ~E_10~0); {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 155: Hoare triple {75838#false} assume 1 == ~E_11~0;~E_11~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 156: Hoare triple {75838#false} assume 1 == ~E_12~0;~E_12~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,654 INFO L290 TraceCheckUtils]: 157: Hoare triple {75838#false} assume 1 == ~E_13~0;~E_13~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,655 INFO L290 TraceCheckUtils]: 158: Hoare triple {75838#false} assume 1 == ~E_14~0;~E_14~0 := 2; {75838#false} is VALID [2022-02-21 04:25:00,655 INFO L290 TraceCheckUtils]: 159: Hoare triple {75838#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {75838#false} is VALID [2022-02-21 04:25:00,655 INFO L290 TraceCheckUtils]: 160: Hoare triple {75838#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {75838#false} is VALID [2022-02-21 04:25:00,655 INFO L290 TraceCheckUtils]: 161: Hoare triple {75838#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {75838#false} is VALID [2022-02-21 04:25:00,655 INFO L290 TraceCheckUtils]: 162: Hoare triple {75838#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {75838#false} is VALID [2022-02-21 04:25:00,655 INFO L290 TraceCheckUtils]: 163: Hoare triple {75838#false} assume !(0 == start_simulation_~tmp~3#1); {75838#false} is VALID [2022-02-21 04:25:00,655 INFO L290 TraceCheckUtils]: 164: Hoare triple {75838#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {75838#false} is VALID [2022-02-21 04:25:00,655 INFO L290 TraceCheckUtils]: 165: Hoare triple {75838#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {75838#false} is VALID [2022-02-21 04:25:00,655 INFO L290 TraceCheckUtils]: 166: Hoare triple {75838#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {75838#false} is VALID [2022-02-21 04:25:00,656 INFO L290 TraceCheckUtils]: 167: Hoare triple {75838#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {75838#false} is VALID [2022-02-21 04:25:00,656 INFO L290 TraceCheckUtils]: 168: Hoare triple {75838#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {75838#false} is VALID [2022-02-21 04:25:00,656 INFO L290 TraceCheckUtils]: 169: Hoare triple {75838#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {75838#false} is VALID [2022-02-21 04:25:00,656 INFO L290 TraceCheckUtils]: 170: Hoare triple {75838#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {75838#false} is VALID [2022-02-21 04:25:00,656 INFO L290 TraceCheckUtils]: 171: Hoare triple {75838#false} assume !(0 != start_simulation_~tmp___0~1#1); {75838#false} is VALID [2022-02-21 04:25:00,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:00,657 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:00,657 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990820200] [2022-02-21 04:25:00,657 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [990820200] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:00,657 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:00,657 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:00,657 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143329986] [2022-02-21 04:25:00,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:00,658 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:00,658 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:00,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:25:00,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:25:00,658 INFO L87 Difference]: Start difference. First operand 2047 states and 3026 transitions. cyclomatic complexity: 980 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:01,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:01,548 INFO L93 Difference]: Finished difference Result 2047 states and 3025 transitions. [2022-02-21 04:25:01,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:25:01,548 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:01,636 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:01,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3025 transitions. [2022-02-21 04:25:01,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:01,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3025 transitions. [2022-02-21 04:25:01,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:25:01,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:25:01,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3025 transitions. [2022-02-21 04:25:01,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:01,837 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2022-02-21 04:25:01,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3025 transitions. [2022-02-21 04:25:01,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:25:01,853 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:01,855 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3025 transitions. Second operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:01,857 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3025 transitions. Second operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:01,858 INFO L87 Difference]: Start difference. First operand 2047 states and 3025 transitions. Second operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:01,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:01,944 INFO L93 Difference]: Finished difference Result 2047 states and 3025 transitions. [2022-02-21 04:25:01,944 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3025 transitions. [2022-02-21 04:25:01,946 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:01,946 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:01,948 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3025 transitions. [2022-02-21 04:25:01,949 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3025 transitions. [2022-02-21 04:25:02,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:02,033 INFO L93 Difference]: Finished difference Result 2047 states and 3025 transitions. [2022-02-21 04:25:02,033 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3025 transitions. [2022-02-21 04:25:02,035 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:02,035 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:02,035 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:02,035 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:02,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:02,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3025 transitions. [2022-02-21 04:25:02,122 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2022-02-21 04:25:02,122 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2022-02-21 04:25:02,122 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:25:02,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3025 transitions. [2022-02-21 04:25:02,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:02,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:02,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:02,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:02,126 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:02,126 INFO L791 eck$LassoCheckResult]: Stem: 78813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 78814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 79416#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78533#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78534#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 78779#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78780#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78507#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78508#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 79731#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 79083#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 79084#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 79601#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 78993#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 78994#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 78414#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 78415#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 78746#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 78944#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 77991#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77992#L1342 assume !(0 == ~M_E~0); 78157#L1342-2 assume !(0 == ~T1_E~0); 78713#L1347-1 assume !(0 == ~T2_E~0); 79714#L1352-1 assume !(0 == ~T3_E~0); 79510#L1357-1 assume !(0 == ~T4_E~0); 78738#L1362-1 assume !(0 == ~T5_E~0); 78739#L1367-1 assume !(0 == ~T6_E~0); 78336#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 78337#L1377-1 assume !(0 == ~T8_E~0); 78667#L1382-1 assume !(0 == ~T9_E~0); 78668#L1387-1 assume !(0 == ~T10_E~0); 79395#L1392-1 assume !(0 == ~T11_E~0); 78699#L1397-1 assume !(0 == ~T12_E~0); 78700#L1402-1 assume !(0 == ~T13_E~0); 78352#L1407-1 assume !(0 == ~T14_E~0); 78353#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 79631#L1417-1 assume !(0 == ~E_2~0); 79632#L1422-1 assume !(0 == ~E_3~0); 79873#L1427-1 assume !(0 == ~E_4~0); 78540#L1432-1 assume !(0 == ~E_5~0); 78541#L1437-1 assume !(0 == ~E_6~0); 79549#L1442-1 assume !(0 == ~E_7~0); 79550#L1447-1 assume !(0 == ~E_8~0); 79392#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 78127#L1457-1 assume !(0 == ~E_10~0); 78128#L1462-1 assume !(0 == ~E_11~0); 79584#L1467-1 assume !(0 == ~E_12~0); 79596#L1472-1 assume !(0 == ~E_13~0); 79597#L1477-1 assume !(0 == ~E_14~0); 79339#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78326#L646 assume 1 == ~m_pc~0; 78327#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 79003#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79018#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78416#L1666 assume !(0 != activate_threads_~tmp~1#1); 78417#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79894#L665 assume !(1 == ~t1_pc~0); 78892#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 78893#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78425#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78426#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 79216#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79217#L684 assume 1 == ~t2_pc~0; 79334#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79258#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79323#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79718#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 79719#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79907#L703 assume !(1 == ~t3_pc~0); 78562#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 78563#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79209#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77961#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 77962#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78447#L722 assume 1 == ~t4_pc~0; 79185#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78628#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78973#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 79533#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 79040#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78158#L741 assume 1 == ~t5_pc~0; 78159#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78469#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78623#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78624#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 79303#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78714#L760 assume !(1 == ~t6_pc~0); 78561#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 78560#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78418#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78419#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 79140#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79141#L779 assume 1 == ~t7_pc~0; 78203#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 78049#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78050#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78458#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 78481#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78482#L798 assume !(1 == ~t8_pc~0); 79763#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 79686#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78205#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78206#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 79896#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78026#L817 assume 1 == ~t9_pc~0; 78027#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78821#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78822#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 79344#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 78432#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78433#L836 assume !(1 == ~t10_pc~0); 78449#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 78380#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78381#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78629#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 78630#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79696#L855 assume 1 == ~t11_pc~0; 79014#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 79015#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 79579#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 79388#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 79223#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78322#L874 assume !(1 == ~t12_pc~0); 78323#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 78490#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 78491#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 78631#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 77999#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78000#L893 assume 1 == ~t13_pc~0; 79830#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78355#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78666#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 79757#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 79765#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 79766#L912 assume 1 == ~t14_pc~0; 79556#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 79557#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 78325#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 78257#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 78258#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79033#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 79449#L1495-2 assume !(1 == ~T1_E~0); 79450#L1500-1 assume !(1 == ~T2_E~0); 79136#L1505-1 assume !(1 == ~T3_E~0); 79137#L1510-1 assume !(1 == ~T4_E~0); 79194#L1515-1 assume !(1 == ~T5_E~0); 79195#L1520-1 assume !(1 == ~T6_E~0); 79764#L1525-1 assume !(1 == ~T7_E~0); 79474#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78427#L1535-1 assume !(1 == ~T9_E~0); 78428#L1540-1 assume !(1 == ~T10_E~0); 77920#L1545-1 assume !(1 == ~T11_E~0); 77921#L1550-1 assume !(1 == ~T12_E~0); 78169#L1555-1 assume !(1 == ~T13_E~0); 78170#L1560-1 assume !(1 == ~T14_E~0); 78470#L1565-1 assume !(1 == ~E_1~0); 79883#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 79361#L1575-1 assume !(1 == ~E_3~0); 78740#L1580-1 assume !(1 == ~E_4~0); 78741#L1585-1 assume !(1 == ~E_5~0); 79211#L1590-1 assume !(1 == ~E_6~0); 78775#L1595-1 assume !(1 == ~E_7~0); 78776#L1600-1 assume !(1 == ~E_8~0); 79148#L1605-1 assume !(1 == ~E_9~0); 79149#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 79666#L1615-1 assume !(1 == ~E_11~0); 78605#L1620-1 assume !(1 == ~E_12~0); 78606#L1625-1 assume !(1 == ~E_13~0); 79393#L1630-1 assume !(1 == ~E_14~0); 78774#L1635-1 assume { :end_inline_reset_delta_events } true; 78715#L2017-2 [2022-02-21 04:25:02,127 INFO L793 eck$LassoCheckResult]: Loop: 78715#L2017-2 assume !false; 77995#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77996#L1316 assume !false; 79324#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 79386#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77933#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 78075#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 78076#L1115 assume !(0 != eval_~tmp~0#1); 79409#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 78830#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78831#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 79013#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 79514#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79183#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79184#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79746#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 79921#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 79916#L1372-3 assume !(0 == ~T7_E~0); 77977#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 77978#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78647#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 78648#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 79559#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 79869#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 79127#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 78283#L1412-3 assume !(0 == ~E_1~0); 78284#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 79048#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79049#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 79743#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79430#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 79142#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 79143#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 78043#L1452-3 assume !(0 == ~E_9~0); 78044#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 79682#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 79683#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 79487#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 79488#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 78281#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78282#L646-42 assume 1 == ~m_pc~0; 78867#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 79715#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79716#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 79854#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 79855#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79647#L665-42 assume !(1 == ~t1_pc~0); 79609#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 79610#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79796#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78450#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78451#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79920#L684-42 assume 1 == ~t2_pc~0; 79299#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79300#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79910#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79079#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79080#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79202#L703-42 assume 1 == ~t3_pc~0; 79400#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 79401#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78719#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78720#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 79494#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79114#L722-42 assume 1 == ~t4_pc~0; 79115#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79525#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78768#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78595#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78596#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79890#L741-42 assume !(1 == ~t5_pc~0); 79507#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 78977#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78978#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 79923#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78885#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78886#L760-42 assume 1 == ~t6_pc~0; 79021#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 79155#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79156#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 79544#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 78837#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78838#L779-42 assume 1 == ~t7_pc~0; 79667#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 79615#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78524#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78525#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78378#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78379#L798-42 assume !(1 == ~t8_pc~0); 77989#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 77990#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 79733#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 79179#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78209#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78210#L817-42 assume 1 == ~t9_pc~0; 78983#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78493#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78494#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78620#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 79425#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 79426#L836-42 assume !(1 == ~t10_pc~0); 79519#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 78531#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78532#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 79833#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 79834#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79875#L855-42 assume !(1 == ~t11_pc~0); 79889#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 78082#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78083#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78832#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 79595#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78696#L874-42 assume 1 == ~t12_pc~0; 78697#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 78939#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77997#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77998#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78251#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78252#L893-42 assume !(1 == ~t13_pc~0); 79235#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 79236#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 79251#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 79153#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 78625#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 78626#L912-42 assume !(1 == ~t14_pc~0); 79435#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 77943#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 77944#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 79524#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 78371#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78372#L1495-3 assume !(1 == ~M_E~0); 78987#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 79415#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 79508#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78601#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78564#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78565#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 79222#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 79445#L1530-3 assume !(1 == ~T8_E~0); 78410#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78411#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78448#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 79705#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 79814#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 78854#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 78855#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 79470#L1570-3 assume !(1 == ~E_2~0); 79421#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 79422#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 79777#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 79822#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 79867#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 79244#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 79245#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 79720#L1610-3 assume !(1 == ~E_10~0); 78607#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78608#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 79212#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 79213#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 79117#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 78548#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 78153#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 78891#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 79447#L2036 assume !(0 == start_simulation_~tmp~3#1); 79448#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 79600#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 78760#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 79778#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 79160#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 79161#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 79881#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 79882#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 78715#L2017-2 [2022-02-21 04:25:02,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:02,127 INFO L85 PathProgramCache]: Analyzing trace with hash -1364407510, now seen corresponding path program 1 times [2022-02-21 04:25:02,127 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:02,127 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135970741] [2022-02-21 04:25:02,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:02,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:02,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:02,163 INFO L290 TraceCheckUtils]: 0: Hoare triple {84031#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {84031#true} is VALID [2022-02-21 04:25:02,163 INFO L290 TraceCheckUtils]: 1: Hoare triple {84031#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,164 INFO L290 TraceCheckUtils]: 2: Hoare triple {84033#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,164 INFO L290 TraceCheckUtils]: 3: Hoare triple {84033#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,164 INFO L290 TraceCheckUtils]: 4: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,164 INFO L290 TraceCheckUtils]: 5: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,165 INFO L290 TraceCheckUtils]: 6: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,165 INFO L290 TraceCheckUtils]: 7: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,165 INFO L290 TraceCheckUtils]: 8: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,165 INFO L290 TraceCheckUtils]: 9: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,165 INFO L290 TraceCheckUtils]: 10: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,166 INFO L290 TraceCheckUtils]: 11: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,166 INFO L290 TraceCheckUtils]: 12: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,166 INFO L290 TraceCheckUtils]: 13: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,166 INFO L290 TraceCheckUtils]: 14: Hoare triple {84033#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {84033#(= ~t11_i~0 1)} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 15: Hoare triple {84033#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 16: Hoare triple {84032#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 17: Hoare triple {84032#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 18: Hoare triple {84032#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 19: Hoare triple {84032#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 20: Hoare triple {84032#false} assume !(0 == ~M_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 21: Hoare triple {84032#false} assume !(0 == ~T1_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 22: Hoare triple {84032#false} assume !(0 == ~T2_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 23: Hoare triple {84032#false} assume !(0 == ~T3_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 24: Hoare triple {84032#false} assume !(0 == ~T4_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 25: Hoare triple {84032#false} assume !(0 == ~T5_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 26: Hoare triple {84032#false} assume !(0 == ~T6_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 27: Hoare triple {84032#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 28: Hoare triple {84032#false} assume !(0 == ~T8_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 29: Hoare triple {84032#false} assume !(0 == ~T9_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 30: Hoare triple {84032#false} assume !(0 == ~T10_E~0); {84032#false} is VALID [2022-02-21 04:25:02,167 INFO L290 TraceCheckUtils]: 31: Hoare triple {84032#false} assume !(0 == ~T11_E~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 32: Hoare triple {84032#false} assume !(0 == ~T12_E~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 33: Hoare triple {84032#false} assume !(0 == ~T13_E~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 34: Hoare triple {84032#false} assume !(0 == ~T14_E~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 35: Hoare triple {84032#false} assume 0 == ~E_1~0;~E_1~0 := 1; {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 36: Hoare triple {84032#false} assume !(0 == ~E_2~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 37: Hoare triple {84032#false} assume !(0 == ~E_3~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 38: Hoare triple {84032#false} assume !(0 == ~E_4~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 39: Hoare triple {84032#false} assume !(0 == ~E_5~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 40: Hoare triple {84032#false} assume !(0 == ~E_6~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 41: Hoare triple {84032#false} assume !(0 == ~E_7~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 42: Hoare triple {84032#false} assume !(0 == ~E_8~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 43: Hoare triple {84032#false} assume 0 == ~E_9~0;~E_9~0 := 1; {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 44: Hoare triple {84032#false} assume !(0 == ~E_10~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 45: Hoare triple {84032#false} assume !(0 == ~E_11~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 46: Hoare triple {84032#false} assume !(0 == ~E_12~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 47: Hoare triple {84032#false} assume !(0 == ~E_13~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 48: Hoare triple {84032#false} assume !(0 == ~E_14~0); {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 49: Hoare triple {84032#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {84032#false} is VALID [2022-02-21 04:25:02,168 INFO L290 TraceCheckUtils]: 50: Hoare triple {84032#false} assume 1 == ~m_pc~0; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 51: Hoare triple {84032#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 52: Hoare triple {84032#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 53: Hoare triple {84032#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 54: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp~1#1); {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 55: Hoare triple {84032#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 56: Hoare triple {84032#false} assume !(1 == ~t1_pc~0); {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 57: Hoare triple {84032#false} is_transmit1_triggered_~__retres1~1#1 := 0; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 58: Hoare triple {84032#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 59: Hoare triple {84032#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 60: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___0~0#1); {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 61: Hoare triple {84032#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 62: Hoare triple {84032#false} assume 1 == ~t2_pc~0; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 63: Hoare triple {84032#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 64: Hoare triple {84032#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 65: Hoare triple {84032#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 66: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___1~0#1); {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 67: Hoare triple {84032#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {84032#false} is VALID [2022-02-21 04:25:02,169 INFO L290 TraceCheckUtils]: 68: Hoare triple {84032#false} assume !(1 == ~t3_pc~0); {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 69: Hoare triple {84032#false} is_transmit3_triggered_~__retres1~3#1 := 0; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 70: Hoare triple {84032#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 71: Hoare triple {84032#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 72: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___2~0#1); {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 73: Hoare triple {84032#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 74: Hoare triple {84032#false} assume 1 == ~t4_pc~0; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 75: Hoare triple {84032#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 76: Hoare triple {84032#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 77: Hoare triple {84032#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 78: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___3~0#1); {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 79: Hoare triple {84032#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 80: Hoare triple {84032#false} assume 1 == ~t5_pc~0; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 81: Hoare triple {84032#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 82: Hoare triple {84032#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 83: Hoare triple {84032#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 84: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___4~0#1); {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 85: Hoare triple {84032#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 86: Hoare triple {84032#false} assume !(1 == ~t6_pc~0); {84032#false} is VALID [2022-02-21 04:25:02,170 INFO L290 TraceCheckUtils]: 87: Hoare triple {84032#false} is_transmit6_triggered_~__retres1~6#1 := 0; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 88: Hoare triple {84032#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 89: Hoare triple {84032#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 90: Hoare triple {84032#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 91: Hoare triple {84032#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 92: Hoare triple {84032#false} assume 1 == ~t7_pc~0; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 93: Hoare triple {84032#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 94: Hoare triple {84032#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 95: Hoare triple {84032#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 96: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___6~0#1); {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 97: Hoare triple {84032#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 98: Hoare triple {84032#false} assume !(1 == ~t8_pc~0); {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 99: Hoare triple {84032#false} is_transmit8_triggered_~__retres1~8#1 := 0; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 100: Hoare triple {84032#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 101: Hoare triple {84032#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 102: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___7~0#1); {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 103: Hoare triple {84032#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 104: Hoare triple {84032#false} assume 1 == ~t9_pc~0; {84032#false} is VALID [2022-02-21 04:25:02,171 INFO L290 TraceCheckUtils]: 105: Hoare triple {84032#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 106: Hoare triple {84032#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 107: Hoare triple {84032#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 108: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___8~0#1); {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 109: Hoare triple {84032#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 110: Hoare triple {84032#false} assume !(1 == ~t10_pc~0); {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 111: Hoare triple {84032#false} is_transmit10_triggered_~__retres1~10#1 := 0; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 112: Hoare triple {84032#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 113: Hoare triple {84032#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 114: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___9~0#1); {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 115: Hoare triple {84032#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 116: Hoare triple {84032#false} assume 1 == ~t11_pc~0; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 117: Hoare triple {84032#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 118: Hoare triple {84032#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 119: Hoare triple {84032#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 120: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___10~0#1); {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 121: Hoare triple {84032#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 122: Hoare triple {84032#false} assume !(1 == ~t12_pc~0); {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 123: Hoare triple {84032#false} is_transmit12_triggered_~__retres1~12#1 := 0; {84032#false} is VALID [2022-02-21 04:25:02,172 INFO L290 TraceCheckUtils]: 124: Hoare triple {84032#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 125: Hoare triple {84032#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 126: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___11~0#1); {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 127: Hoare triple {84032#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 128: Hoare triple {84032#false} assume 1 == ~t13_pc~0; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 129: Hoare triple {84032#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 130: Hoare triple {84032#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 131: Hoare triple {84032#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 132: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___12~0#1); {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 133: Hoare triple {84032#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 134: Hoare triple {84032#false} assume 1 == ~t14_pc~0; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 135: Hoare triple {84032#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 136: Hoare triple {84032#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 137: Hoare triple {84032#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 138: Hoare triple {84032#false} assume !(0 != activate_threads_~tmp___13~0#1); {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 139: Hoare triple {84032#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 140: Hoare triple {84032#false} assume 1 == ~M_E~0;~M_E~0 := 2; {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 141: Hoare triple {84032#false} assume !(1 == ~T1_E~0); {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 142: Hoare triple {84032#false} assume !(1 == ~T2_E~0); {84032#false} is VALID [2022-02-21 04:25:02,173 INFO L290 TraceCheckUtils]: 143: Hoare triple {84032#false} assume !(1 == ~T3_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 144: Hoare triple {84032#false} assume !(1 == ~T4_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 145: Hoare triple {84032#false} assume !(1 == ~T5_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 146: Hoare triple {84032#false} assume !(1 == ~T6_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 147: Hoare triple {84032#false} assume !(1 == ~T7_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 148: Hoare triple {84032#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 149: Hoare triple {84032#false} assume !(1 == ~T9_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 150: Hoare triple {84032#false} assume !(1 == ~T10_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 151: Hoare triple {84032#false} assume !(1 == ~T11_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 152: Hoare triple {84032#false} assume !(1 == ~T12_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 153: Hoare triple {84032#false} assume !(1 == ~T13_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 154: Hoare triple {84032#false} assume !(1 == ~T14_E~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 155: Hoare triple {84032#false} assume !(1 == ~E_1~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 156: Hoare triple {84032#false} assume 1 == ~E_2~0;~E_2~0 := 2; {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 157: Hoare triple {84032#false} assume !(1 == ~E_3~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 158: Hoare triple {84032#false} assume !(1 == ~E_4~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 159: Hoare triple {84032#false} assume !(1 == ~E_5~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 160: Hoare triple {84032#false} assume !(1 == ~E_6~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 161: Hoare triple {84032#false} assume !(1 == ~E_7~0); {84032#false} is VALID [2022-02-21 04:25:02,174 INFO L290 TraceCheckUtils]: 162: Hoare triple {84032#false} assume !(1 == ~E_8~0); {84032#false} is VALID [2022-02-21 04:25:02,175 INFO L290 TraceCheckUtils]: 163: Hoare triple {84032#false} assume !(1 == ~E_9~0); {84032#false} is VALID [2022-02-21 04:25:02,175 INFO L290 TraceCheckUtils]: 164: Hoare triple {84032#false} assume 1 == ~E_10~0;~E_10~0 := 2; {84032#false} is VALID [2022-02-21 04:25:02,175 INFO L290 TraceCheckUtils]: 165: Hoare triple {84032#false} assume !(1 == ~E_11~0); {84032#false} is VALID [2022-02-21 04:25:02,175 INFO L290 TraceCheckUtils]: 166: Hoare triple {84032#false} assume !(1 == ~E_12~0); {84032#false} is VALID [2022-02-21 04:25:02,175 INFO L290 TraceCheckUtils]: 167: Hoare triple {84032#false} assume !(1 == ~E_13~0); {84032#false} is VALID [2022-02-21 04:25:02,175 INFO L290 TraceCheckUtils]: 168: Hoare triple {84032#false} assume !(1 == ~E_14~0); {84032#false} is VALID [2022-02-21 04:25:02,175 INFO L290 TraceCheckUtils]: 169: Hoare triple {84032#false} assume { :end_inline_reset_delta_events } true; {84032#false} is VALID [2022-02-21 04:25:02,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:02,175 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:02,175 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135970741] [2022-02-21 04:25:02,175 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135970741] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:02,175 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:02,176 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:02,176 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474868755] [2022-02-21 04:25:02,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:02,176 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:02,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:02,176 INFO L85 PathProgramCache]: Analyzing trace with hash 1232076202, now seen corresponding path program 1 times [2022-02-21 04:25:02,176 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:02,176 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242069281] [2022-02-21 04:25:02,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:02,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:02,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:02,204 INFO L290 TraceCheckUtils]: 0: Hoare triple {84034#true} assume !false; {84034#true} is VALID [2022-02-21 04:25:02,204 INFO L290 TraceCheckUtils]: 1: Hoare triple {84034#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {84034#true} is VALID [2022-02-21 04:25:02,204 INFO L290 TraceCheckUtils]: 2: Hoare triple {84034#true} assume !false; {84034#true} is VALID [2022-02-21 04:25:02,204 INFO L290 TraceCheckUtils]: 3: Hoare triple {84034#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {84034#true} is VALID [2022-02-21 04:25:02,205 INFO L290 TraceCheckUtils]: 4: Hoare triple {84034#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {84034#true} is VALID [2022-02-21 04:25:02,205 INFO L290 TraceCheckUtils]: 5: Hoare triple {84034#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {84034#true} is VALID [2022-02-21 04:25:02,205 INFO L290 TraceCheckUtils]: 6: Hoare triple {84034#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {84034#true} is VALID [2022-02-21 04:25:02,205 INFO L290 TraceCheckUtils]: 7: Hoare triple {84034#true} assume !(0 != eval_~tmp~0#1); {84034#true} is VALID [2022-02-21 04:25:02,205 INFO L290 TraceCheckUtils]: 8: Hoare triple {84034#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {84034#true} is VALID [2022-02-21 04:25:02,205 INFO L290 TraceCheckUtils]: 9: Hoare triple {84034#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {84034#true} is VALID [2022-02-21 04:25:02,205 INFO L290 TraceCheckUtils]: 10: Hoare triple {84034#true} assume 0 == ~M_E~0;~M_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,205 INFO L290 TraceCheckUtils]: 11: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,205 INFO L290 TraceCheckUtils]: 12: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,206 INFO L290 TraceCheckUtils]: 13: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,206 INFO L290 TraceCheckUtils]: 14: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,206 INFO L290 TraceCheckUtils]: 15: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,206 INFO L290 TraceCheckUtils]: 16: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,207 INFO L290 TraceCheckUtils]: 17: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,207 INFO L290 TraceCheckUtils]: 18: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,207 INFO L290 TraceCheckUtils]: 19: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,207 INFO L290 TraceCheckUtils]: 20: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,207 INFO L290 TraceCheckUtils]: 21: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,208 INFO L290 TraceCheckUtils]: 22: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,208 INFO L290 TraceCheckUtils]: 23: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,208 INFO L290 TraceCheckUtils]: 24: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,208 INFO L290 TraceCheckUtils]: 25: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,209 INFO L290 TraceCheckUtils]: 26: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,209 INFO L290 TraceCheckUtils]: 27: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,209 INFO L290 TraceCheckUtils]: 28: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,209 INFO L290 TraceCheckUtils]: 29: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,209 INFO L290 TraceCheckUtils]: 30: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,210 INFO L290 TraceCheckUtils]: 31: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,210 INFO L290 TraceCheckUtils]: 32: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,210 INFO L290 TraceCheckUtils]: 33: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,210 INFO L290 TraceCheckUtils]: 34: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,211 INFO L290 TraceCheckUtils]: 35: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,211 INFO L290 TraceCheckUtils]: 36: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,211 INFO L290 TraceCheckUtils]: 37: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,211 INFO L290 TraceCheckUtils]: 38: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,212 INFO L290 TraceCheckUtils]: 39: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,212 INFO L290 TraceCheckUtils]: 40: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,212 INFO L290 TraceCheckUtils]: 41: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,212 INFO L290 TraceCheckUtils]: 42: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,212 INFO L290 TraceCheckUtils]: 43: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,213 INFO L290 TraceCheckUtils]: 44: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,213 INFO L290 TraceCheckUtils]: 45: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,213 INFO L290 TraceCheckUtils]: 46: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,213 INFO L290 TraceCheckUtils]: 47: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,214 INFO L290 TraceCheckUtils]: 48: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,214 INFO L290 TraceCheckUtils]: 49: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,214 INFO L290 TraceCheckUtils]: 50: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,214 INFO L290 TraceCheckUtils]: 51: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,215 INFO L290 TraceCheckUtils]: 52: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,215 INFO L290 TraceCheckUtils]: 53: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,215 INFO L290 TraceCheckUtils]: 54: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,215 INFO L290 TraceCheckUtils]: 55: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,215 INFO L290 TraceCheckUtils]: 56: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,216 INFO L290 TraceCheckUtils]: 57: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,216 INFO L290 TraceCheckUtils]: 58: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,216 INFO L290 TraceCheckUtils]: 59: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,216 INFO L290 TraceCheckUtils]: 60: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,217 INFO L290 TraceCheckUtils]: 61: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,217 INFO L290 TraceCheckUtils]: 62: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,217 INFO L290 TraceCheckUtils]: 63: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,217 INFO L290 TraceCheckUtils]: 64: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,218 INFO L290 TraceCheckUtils]: 65: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,218 INFO L290 TraceCheckUtils]: 66: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,218 INFO L290 TraceCheckUtils]: 67: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,218 INFO L290 TraceCheckUtils]: 68: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,218 INFO L290 TraceCheckUtils]: 69: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,219 INFO L290 TraceCheckUtils]: 70: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,219 INFO L290 TraceCheckUtils]: 71: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,219 INFO L290 TraceCheckUtils]: 72: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,219 INFO L290 TraceCheckUtils]: 73: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,220 INFO L290 TraceCheckUtils]: 74: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,220 INFO L290 TraceCheckUtils]: 75: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,220 INFO L290 TraceCheckUtils]: 76: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,220 INFO L290 TraceCheckUtils]: 77: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,220 INFO L290 TraceCheckUtils]: 78: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,221 INFO L290 TraceCheckUtils]: 79: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,221 INFO L290 TraceCheckUtils]: 80: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,221 INFO L290 TraceCheckUtils]: 81: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,221 INFO L290 TraceCheckUtils]: 82: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,222 INFO L290 TraceCheckUtils]: 83: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,222 INFO L290 TraceCheckUtils]: 84: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,222 INFO L290 TraceCheckUtils]: 85: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,222 INFO L290 TraceCheckUtils]: 86: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,222 INFO L290 TraceCheckUtils]: 87: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,223 INFO L290 TraceCheckUtils]: 88: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,223 INFO L290 TraceCheckUtils]: 89: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,223 INFO L290 TraceCheckUtils]: 90: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,223 INFO L290 TraceCheckUtils]: 91: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,224 INFO L290 TraceCheckUtils]: 92: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,224 INFO L290 TraceCheckUtils]: 93: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,224 INFO L290 TraceCheckUtils]: 94: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,224 INFO L290 TraceCheckUtils]: 95: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,225 INFO L290 TraceCheckUtils]: 96: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,225 INFO L290 TraceCheckUtils]: 97: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,225 INFO L290 TraceCheckUtils]: 98: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,225 INFO L290 TraceCheckUtils]: 99: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,225 INFO L290 TraceCheckUtils]: 100: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,226 INFO L290 TraceCheckUtils]: 101: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,226 INFO L290 TraceCheckUtils]: 102: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,226 INFO L290 TraceCheckUtils]: 103: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,226 INFO L290 TraceCheckUtils]: 104: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,227 INFO L290 TraceCheckUtils]: 105: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,227 INFO L290 TraceCheckUtils]: 106: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,227 INFO L290 TraceCheckUtils]: 107: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,227 INFO L290 TraceCheckUtils]: 108: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,228 INFO L290 TraceCheckUtils]: 109: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,228 INFO L290 TraceCheckUtils]: 110: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,228 INFO L290 TraceCheckUtils]: 111: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,228 INFO L290 TraceCheckUtils]: 112: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,228 INFO L290 TraceCheckUtils]: 113: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,229 INFO L290 TraceCheckUtils]: 114: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,229 INFO L290 TraceCheckUtils]: 115: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,229 INFO L290 TraceCheckUtils]: 116: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,229 INFO L290 TraceCheckUtils]: 117: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,230 INFO L290 TraceCheckUtils]: 118: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t13_pc~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,230 INFO L290 TraceCheckUtils]: 119: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,230 INFO L290 TraceCheckUtils]: 120: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,230 INFO L290 TraceCheckUtils]: 121: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,230 INFO L290 TraceCheckUtils]: 122: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,231 INFO L290 TraceCheckUtils]: 123: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,231 INFO L290 TraceCheckUtils]: 124: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,231 INFO L290 TraceCheckUtils]: 125: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,231 INFO L290 TraceCheckUtils]: 126: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,232 INFO L290 TraceCheckUtils]: 127: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,232 INFO L290 TraceCheckUtils]: 128: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,232 INFO L290 TraceCheckUtils]: 129: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {84036#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:02,232 INFO L290 TraceCheckUtils]: 130: Hoare triple {84036#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {84035#false} is VALID [2022-02-21 04:25:02,232 INFO L290 TraceCheckUtils]: 131: Hoare triple {84035#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,232 INFO L290 TraceCheckUtils]: 132: Hoare triple {84035#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 133: Hoare triple {84035#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 134: Hoare triple {84035#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 135: Hoare triple {84035#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 136: Hoare triple {84035#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 137: Hoare triple {84035#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 138: Hoare triple {84035#false} assume !(1 == ~T8_E~0); {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 139: Hoare triple {84035#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 140: Hoare triple {84035#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 141: Hoare triple {84035#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 142: Hoare triple {84035#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 143: Hoare triple {84035#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 144: Hoare triple {84035#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 145: Hoare triple {84035#false} assume 1 == ~E_1~0;~E_1~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 146: Hoare triple {84035#false} assume !(1 == ~E_2~0); {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 147: Hoare triple {84035#false} assume 1 == ~E_3~0;~E_3~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 148: Hoare triple {84035#false} assume 1 == ~E_4~0;~E_4~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 149: Hoare triple {84035#false} assume 1 == ~E_5~0;~E_5~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 150: Hoare triple {84035#false} assume 1 == ~E_6~0;~E_6~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,233 INFO L290 TraceCheckUtils]: 151: Hoare triple {84035#false} assume 1 == ~E_7~0;~E_7~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 152: Hoare triple {84035#false} assume 1 == ~E_8~0;~E_8~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 153: Hoare triple {84035#false} assume 1 == ~E_9~0;~E_9~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 154: Hoare triple {84035#false} assume !(1 == ~E_10~0); {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 155: Hoare triple {84035#false} assume 1 == ~E_11~0;~E_11~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 156: Hoare triple {84035#false} assume 1 == ~E_12~0;~E_12~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 157: Hoare triple {84035#false} assume 1 == ~E_13~0;~E_13~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 158: Hoare triple {84035#false} assume 1 == ~E_14~0;~E_14~0 := 2; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 159: Hoare triple {84035#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 160: Hoare triple {84035#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 161: Hoare triple {84035#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 162: Hoare triple {84035#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 163: Hoare triple {84035#false} assume !(0 == start_simulation_~tmp~3#1); {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 164: Hoare triple {84035#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 165: Hoare triple {84035#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 166: Hoare triple {84035#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 167: Hoare triple {84035#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 168: Hoare triple {84035#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {84035#false} is VALID [2022-02-21 04:25:02,234 INFO L290 TraceCheckUtils]: 169: Hoare triple {84035#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {84035#false} is VALID [2022-02-21 04:25:02,235 INFO L290 TraceCheckUtils]: 170: Hoare triple {84035#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {84035#false} is VALID [2022-02-21 04:25:02,235 INFO L290 TraceCheckUtils]: 171: Hoare triple {84035#false} assume !(0 != start_simulation_~tmp___0~1#1); {84035#false} is VALID [2022-02-21 04:25:02,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:02,235 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:02,235 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242069281] [2022-02-21 04:25:02,235 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [242069281] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:02,235 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:02,235 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:02,235 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181830054] [2022-02-21 04:25:02,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:02,236 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:02,236 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:02,236 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:25:02,236 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:25:02,236 INFO L87 Difference]: Start difference. First operand 2047 states and 3025 transitions. cyclomatic complexity: 979 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:03,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:03,669 INFO L93 Difference]: Finished difference Result 2047 states and 3024 transitions. [2022-02-21 04:25:03,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:25:03,669 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:03,768 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:03,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3024 transitions. [2022-02-21 04:25:03,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:03,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3024 transitions. [2022-02-21 04:25:03,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:25:03,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:25:03,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3024 transitions. [2022-02-21 04:25:03,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:03,945 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2022-02-21 04:25:03,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3024 transitions. [2022-02-21 04:25:03,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:25:03,962 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:03,964 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3024 transitions. Second operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:03,966 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3024 transitions. Second operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:03,967 INFO L87 Difference]: Start difference. First operand 2047 states and 3024 transitions. Second operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:04,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:04,052 INFO L93 Difference]: Finished difference Result 2047 states and 3024 transitions. [2022-02-21 04:25:04,052 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3024 transitions. [2022-02-21 04:25:04,054 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:04,054 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:04,056 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3024 transitions. [2022-02-21 04:25:04,058 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3024 transitions. [2022-02-21 04:25:04,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:04,143 INFO L93 Difference]: Finished difference Result 2047 states and 3024 transitions. [2022-02-21 04:25:04,143 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3024 transitions. [2022-02-21 04:25:04,145 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:04,145 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:04,145 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:04,145 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:04,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:04,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3024 transitions. [2022-02-21 04:25:04,231 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2022-02-21 04:25:04,231 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2022-02-21 04:25:04,231 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:25:04,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3024 transitions. [2022-02-21 04:25:04,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:04,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:04,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:04,235 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:04,235 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:04,235 INFO L791 eck$LassoCheckResult]: Stem: 87010#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 87011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 87613#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86730#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86731#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 86976#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86977#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86704#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86705#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87928#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87280#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87281#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 87798#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 87190#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87191#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86611#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86612#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 86943#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 87141#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 86188#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86189#L1342 assume !(0 == ~M_E~0); 86354#L1342-2 assume !(0 == ~T1_E~0); 86910#L1347-1 assume !(0 == ~T2_E~0); 87911#L1352-1 assume !(0 == ~T3_E~0); 87707#L1357-1 assume !(0 == ~T4_E~0); 86935#L1362-1 assume !(0 == ~T5_E~0); 86936#L1367-1 assume !(0 == ~T6_E~0); 86533#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 86534#L1377-1 assume !(0 == ~T8_E~0); 86864#L1382-1 assume !(0 == ~T9_E~0); 86865#L1387-1 assume !(0 == ~T10_E~0); 87592#L1392-1 assume !(0 == ~T11_E~0); 86896#L1397-1 assume !(0 == ~T12_E~0); 86897#L1402-1 assume !(0 == ~T13_E~0); 86549#L1407-1 assume !(0 == ~T14_E~0); 86550#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 87828#L1417-1 assume !(0 == ~E_2~0); 87829#L1422-1 assume !(0 == ~E_3~0); 88070#L1427-1 assume !(0 == ~E_4~0); 86737#L1432-1 assume !(0 == ~E_5~0); 86738#L1437-1 assume !(0 == ~E_6~0); 87746#L1442-1 assume !(0 == ~E_7~0); 87747#L1447-1 assume !(0 == ~E_8~0); 87589#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 86324#L1457-1 assume !(0 == ~E_10~0); 86325#L1462-1 assume !(0 == ~E_11~0); 87781#L1467-1 assume !(0 == ~E_12~0); 87793#L1472-1 assume !(0 == ~E_13~0); 87794#L1477-1 assume !(0 == ~E_14~0); 87536#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86523#L646 assume 1 == ~m_pc~0; 86524#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 87200#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87215#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86613#L1666 assume !(0 != activate_threads_~tmp~1#1); 86614#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88091#L665 assume !(1 == ~t1_pc~0); 87089#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87090#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86622#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86623#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 87413#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87414#L684 assume 1 == ~t2_pc~0; 87531#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 87455#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87520#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87915#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 87916#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88104#L703 assume !(1 == ~t3_pc~0); 86759#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86760#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87406#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86158#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 86159#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86644#L722 assume 1 == ~t4_pc~0; 87382#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86825#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87170#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87730#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 87237#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86355#L741 assume 1 == ~t5_pc~0; 86356#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 86666#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86820#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86821#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 87500#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86911#L760 assume !(1 == ~t6_pc~0); 86758#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86757#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86615#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86616#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87337#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87338#L779 assume 1 == ~t7_pc~0; 86400#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86246#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86247#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86655#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 86678#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86679#L798 assume !(1 == ~t8_pc~0); 87960#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 87883#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86402#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86403#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 88093#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86223#L817 assume 1 == ~t9_pc~0; 86224#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87018#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87019#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87541#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 86629#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86630#L836 assume !(1 == ~t10_pc~0); 86646#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86577#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86578#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86826#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 86827#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87893#L855 assume 1 == ~t11_pc~0; 87211#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 87212#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87776#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 87585#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 87420#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86519#L874 assume !(1 == ~t12_pc~0); 86520#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86687#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86688#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86828#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 86196#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86197#L893 assume 1 == ~t13_pc~0; 88027#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86552#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86863#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 87954#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 87962#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 87963#L912 assume 1 == ~t14_pc~0; 87753#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 87754#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 86522#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86454#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 86455#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87230#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 87646#L1495-2 assume !(1 == ~T1_E~0); 87647#L1500-1 assume !(1 == ~T2_E~0); 87333#L1505-1 assume !(1 == ~T3_E~0); 87334#L1510-1 assume !(1 == ~T4_E~0); 87391#L1515-1 assume !(1 == ~T5_E~0); 87392#L1520-1 assume !(1 == ~T6_E~0); 87961#L1525-1 assume !(1 == ~T7_E~0); 87671#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86624#L1535-1 assume !(1 == ~T9_E~0); 86625#L1540-1 assume !(1 == ~T10_E~0); 86117#L1545-1 assume !(1 == ~T11_E~0); 86118#L1550-1 assume !(1 == ~T12_E~0); 86366#L1555-1 assume !(1 == ~T13_E~0); 86367#L1560-1 assume !(1 == ~T14_E~0); 86667#L1565-1 assume !(1 == ~E_1~0); 88080#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 87558#L1575-1 assume !(1 == ~E_3~0); 86937#L1580-1 assume !(1 == ~E_4~0); 86938#L1585-1 assume !(1 == ~E_5~0); 87408#L1590-1 assume !(1 == ~E_6~0); 86972#L1595-1 assume !(1 == ~E_7~0); 86973#L1600-1 assume !(1 == ~E_8~0); 87345#L1605-1 assume !(1 == ~E_9~0); 87346#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 87863#L1615-1 assume !(1 == ~E_11~0); 86802#L1620-1 assume !(1 == ~E_12~0); 86803#L1625-1 assume !(1 == ~E_13~0); 87590#L1630-1 assume !(1 == ~E_14~0); 86971#L1635-1 assume { :end_inline_reset_delta_events } true; 86912#L2017-2 [2022-02-21 04:25:04,236 INFO L793 eck$LassoCheckResult]: Loop: 86912#L2017-2 assume !false; 86192#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86193#L1316 assume !false; 87521#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 87583#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 86130#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 86272#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 86273#L1115 assume !(0 != eval_~tmp~0#1); 87606#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87027#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87028#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 87210#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87711#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87380#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87381#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87943#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88118#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88113#L1372-3 assume !(0 == ~T7_E~0); 86174#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 86175#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86844#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 86845#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 87756#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 88066#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 87324#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 86480#L1412-3 assume !(0 == ~E_1~0); 86481#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87245#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87246#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 87940#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 87627#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 87339#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 87340#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86240#L1452-3 assume !(0 == ~E_9~0); 86241#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 87879#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 87880#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 87684#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 87685#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 86478#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86479#L646-42 assume !(1 == ~m_pc~0); 87065#L646-44 is_master_triggered_~__retres1~0#1 := 0; 87912#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87913#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88051#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88052#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87844#L665-42 assume 1 == ~t1_pc~0; 87805#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 87807#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87993#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86647#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86648#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88117#L684-42 assume 1 == ~t2_pc~0; 87496#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 87497#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88107#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87276#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87277#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87399#L703-42 assume 1 == ~t3_pc~0; 87597#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 87598#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86916#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86917#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87691#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87311#L722-42 assume !(1 == ~t4_pc~0); 87313#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 87722#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86965#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86792#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86793#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88087#L741-42 assume !(1 == ~t5_pc~0); 87704#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 87174#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87175#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88120#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87082#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87083#L760-42 assume !(1 == ~t6_pc~0); 87217#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 87352#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87353#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87741#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 87034#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87035#L779-42 assume !(1 == ~t7_pc~0); 87811#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 87812#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86721#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86722#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86575#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86576#L798-42 assume 1 == ~t8_pc~0; 87026#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86187#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87930#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87376#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 86406#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86407#L817-42 assume !(1 == ~t9_pc~0); 87181#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 86690#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86691#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86817#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 87622#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87623#L836-42 assume 1 == ~t10_pc~0; 87715#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 86728#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86729#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 88030#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 88031#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88072#L855-42 assume 1 == ~t11_pc~0; 88085#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86279#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86280#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 87029#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 87792#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86893#L874-42 assume !(1 == ~t12_pc~0); 86895#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 87136#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86194#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86195#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 86448#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86449#L893-42 assume 1 == ~t13_pc~0; 87652#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 87433#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 87448#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 87350#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 86822#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 86823#L912-42 assume !(1 == ~t14_pc~0); 87632#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 86140#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 86141#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 87721#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 86568#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86569#L1495-3 assume !(1 == ~M_E~0); 87184#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87612#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87705#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86798#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86761#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86762#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 87419#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 87642#L1530-3 assume !(1 == ~T8_E~0); 86607#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86608#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86645#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87902#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 88011#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 87051#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 87052#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 87667#L1570-3 assume !(1 == ~E_2~0); 87618#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87619#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87974#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88019#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 88064#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87441#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 87442#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 87917#L1610-3 assume !(1 == ~E_10~0); 86804#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 86805#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 87409#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 87410#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 87314#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 86745#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 86350#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 87088#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 87644#L2036 assume !(0 == start_simulation_~tmp~3#1); 87645#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 87797#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 86957#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 87975#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 87357#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 87358#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88078#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 88079#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 86912#L2017-2 [2022-02-21 04:25:04,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:04,236 INFO L85 PathProgramCache]: Analyzing trace with hash 405064104, now seen corresponding path program 1 times [2022-02-21 04:25:04,237 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:04,237 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70111954] [2022-02-21 04:25:04,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:04,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:04,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:04,256 INFO L290 TraceCheckUtils]: 0: Hoare triple {92228#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {92228#true} is VALID [2022-02-21 04:25:04,256 INFO L290 TraceCheckUtils]: 1: Hoare triple {92228#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,257 INFO L290 TraceCheckUtils]: 2: Hoare triple {92230#(= ~t12_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,257 INFO L290 TraceCheckUtils]: 3: Hoare triple {92230#(= ~t12_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,257 INFO L290 TraceCheckUtils]: 4: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,257 INFO L290 TraceCheckUtils]: 5: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,258 INFO L290 TraceCheckUtils]: 6: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,258 INFO L290 TraceCheckUtils]: 7: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,258 INFO L290 TraceCheckUtils]: 8: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,258 INFO L290 TraceCheckUtils]: 9: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,259 INFO L290 TraceCheckUtils]: 10: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,259 INFO L290 TraceCheckUtils]: 11: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,259 INFO L290 TraceCheckUtils]: 12: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,260 INFO L290 TraceCheckUtils]: 13: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,260 INFO L290 TraceCheckUtils]: 14: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,260 INFO L290 TraceCheckUtils]: 15: Hoare triple {92230#(= ~t12_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {92230#(= ~t12_i~0 1)} is VALID [2022-02-21 04:25:04,260 INFO L290 TraceCheckUtils]: 16: Hoare triple {92230#(= ~t12_i~0 1)} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {92229#false} is VALID [2022-02-21 04:25:04,260 INFO L290 TraceCheckUtils]: 17: Hoare triple {92229#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {92229#false} is VALID [2022-02-21 04:25:04,261 INFO L290 TraceCheckUtils]: 18: Hoare triple {92229#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {92229#false} is VALID [2022-02-21 04:25:04,261 INFO L290 TraceCheckUtils]: 19: Hoare triple {92229#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {92229#false} is VALID [2022-02-21 04:25:04,261 INFO L290 TraceCheckUtils]: 20: Hoare triple {92229#false} assume !(0 == ~M_E~0); {92229#false} is VALID [2022-02-21 04:25:04,261 INFO L290 TraceCheckUtils]: 21: Hoare triple {92229#false} assume !(0 == ~T1_E~0); {92229#false} is VALID [2022-02-21 04:25:04,261 INFO L290 TraceCheckUtils]: 22: Hoare triple {92229#false} assume !(0 == ~T2_E~0); {92229#false} is VALID [2022-02-21 04:25:04,261 INFO L290 TraceCheckUtils]: 23: Hoare triple {92229#false} assume !(0 == ~T3_E~0); {92229#false} is VALID [2022-02-21 04:25:04,261 INFO L290 TraceCheckUtils]: 24: Hoare triple {92229#false} assume !(0 == ~T4_E~0); {92229#false} is VALID [2022-02-21 04:25:04,261 INFO L290 TraceCheckUtils]: 25: Hoare triple {92229#false} assume !(0 == ~T5_E~0); {92229#false} is VALID [2022-02-21 04:25:04,261 INFO L290 TraceCheckUtils]: 26: Hoare triple {92229#false} assume !(0 == ~T6_E~0); {92229#false} is VALID [2022-02-21 04:25:04,262 INFO L290 TraceCheckUtils]: 27: Hoare triple {92229#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {92229#false} is VALID [2022-02-21 04:25:04,262 INFO L290 TraceCheckUtils]: 28: Hoare triple {92229#false} assume !(0 == ~T8_E~0); {92229#false} is VALID [2022-02-21 04:25:04,262 INFO L290 TraceCheckUtils]: 29: Hoare triple {92229#false} assume !(0 == ~T9_E~0); {92229#false} is VALID [2022-02-21 04:25:04,262 INFO L290 TraceCheckUtils]: 30: Hoare triple {92229#false} assume !(0 == ~T10_E~0); {92229#false} is VALID [2022-02-21 04:25:04,262 INFO L290 TraceCheckUtils]: 31: Hoare triple {92229#false} assume !(0 == ~T11_E~0); {92229#false} is VALID [2022-02-21 04:25:04,262 INFO L290 TraceCheckUtils]: 32: Hoare triple {92229#false} assume !(0 == ~T12_E~0); {92229#false} is VALID [2022-02-21 04:25:04,262 INFO L290 TraceCheckUtils]: 33: Hoare triple {92229#false} assume !(0 == ~T13_E~0); {92229#false} is VALID [2022-02-21 04:25:04,262 INFO L290 TraceCheckUtils]: 34: Hoare triple {92229#false} assume !(0 == ~T14_E~0); {92229#false} is VALID [2022-02-21 04:25:04,262 INFO L290 TraceCheckUtils]: 35: Hoare triple {92229#false} assume 0 == ~E_1~0;~E_1~0 := 1; {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 36: Hoare triple {92229#false} assume !(0 == ~E_2~0); {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 37: Hoare triple {92229#false} assume !(0 == ~E_3~0); {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 38: Hoare triple {92229#false} assume !(0 == ~E_4~0); {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 39: Hoare triple {92229#false} assume !(0 == ~E_5~0); {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 40: Hoare triple {92229#false} assume !(0 == ~E_6~0); {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 41: Hoare triple {92229#false} assume !(0 == ~E_7~0); {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 42: Hoare triple {92229#false} assume !(0 == ~E_8~0); {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 43: Hoare triple {92229#false} assume 0 == ~E_9~0;~E_9~0 := 1; {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 44: Hoare triple {92229#false} assume !(0 == ~E_10~0); {92229#false} is VALID [2022-02-21 04:25:04,263 INFO L290 TraceCheckUtils]: 45: Hoare triple {92229#false} assume !(0 == ~E_11~0); {92229#false} is VALID [2022-02-21 04:25:04,264 INFO L290 TraceCheckUtils]: 46: Hoare triple {92229#false} assume !(0 == ~E_12~0); {92229#false} is VALID [2022-02-21 04:25:04,264 INFO L290 TraceCheckUtils]: 47: Hoare triple {92229#false} assume !(0 == ~E_13~0); {92229#false} is VALID [2022-02-21 04:25:04,264 INFO L290 TraceCheckUtils]: 48: Hoare triple {92229#false} assume !(0 == ~E_14~0); {92229#false} is VALID [2022-02-21 04:25:04,264 INFO L290 TraceCheckUtils]: 49: Hoare triple {92229#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {92229#false} is VALID [2022-02-21 04:25:04,264 INFO L290 TraceCheckUtils]: 50: Hoare triple {92229#false} assume 1 == ~m_pc~0; {92229#false} is VALID [2022-02-21 04:25:04,264 INFO L290 TraceCheckUtils]: 51: Hoare triple {92229#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {92229#false} is VALID [2022-02-21 04:25:04,264 INFO L290 TraceCheckUtils]: 52: Hoare triple {92229#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {92229#false} is VALID [2022-02-21 04:25:04,264 INFO L290 TraceCheckUtils]: 53: Hoare triple {92229#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {92229#false} is VALID [2022-02-21 04:25:04,264 INFO L290 TraceCheckUtils]: 54: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp~1#1); {92229#false} is VALID [2022-02-21 04:25:04,265 INFO L290 TraceCheckUtils]: 55: Hoare triple {92229#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {92229#false} is VALID [2022-02-21 04:25:04,265 INFO L290 TraceCheckUtils]: 56: Hoare triple {92229#false} assume !(1 == ~t1_pc~0); {92229#false} is VALID [2022-02-21 04:25:04,265 INFO L290 TraceCheckUtils]: 57: Hoare triple {92229#false} is_transmit1_triggered_~__retres1~1#1 := 0; {92229#false} is VALID [2022-02-21 04:25:04,265 INFO L290 TraceCheckUtils]: 58: Hoare triple {92229#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {92229#false} is VALID [2022-02-21 04:25:04,265 INFO L290 TraceCheckUtils]: 59: Hoare triple {92229#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {92229#false} is VALID [2022-02-21 04:25:04,265 INFO L290 TraceCheckUtils]: 60: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___0~0#1); {92229#false} is VALID [2022-02-21 04:25:04,265 INFO L290 TraceCheckUtils]: 61: Hoare triple {92229#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {92229#false} is VALID [2022-02-21 04:25:04,265 INFO L290 TraceCheckUtils]: 62: Hoare triple {92229#false} assume 1 == ~t2_pc~0; {92229#false} is VALID [2022-02-21 04:25:04,265 INFO L290 TraceCheckUtils]: 63: Hoare triple {92229#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {92229#false} is VALID [2022-02-21 04:25:04,266 INFO L290 TraceCheckUtils]: 64: Hoare triple {92229#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {92229#false} is VALID [2022-02-21 04:25:04,266 INFO L290 TraceCheckUtils]: 65: Hoare triple {92229#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {92229#false} is VALID [2022-02-21 04:25:04,266 INFO L290 TraceCheckUtils]: 66: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___1~0#1); {92229#false} is VALID [2022-02-21 04:25:04,266 INFO L290 TraceCheckUtils]: 67: Hoare triple {92229#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {92229#false} is VALID [2022-02-21 04:25:04,266 INFO L290 TraceCheckUtils]: 68: Hoare triple {92229#false} assume !(1 == ~t3_pc~0); {92229#false} is VALID [2022-02-21 04:25:04,266 INFO L290 TraceCheckUtils]: 69: Hoare triple {92229#false} is_transmit3_triggered_~__retres1~3#1 := 0; {92229#false} is VALID [2022-02-21 04:25:04,266 INFO L290 TraceCheckUtils]: 70: Hoare triple {92229#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {92229#false} is VALID [2022-02-21 04:25:04,266 INFO L290 TraceCheckUtils]: 71: Hoare triple {92229#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {92229#false} is VALID [2022-02-21 04:25:04,266 INFO L290 TraceCheckUtils]: 72: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___2~0#1); {92229#false} is VALID [2022-02-21 04:25:04,267 INFO L290 TraceCheckUtils]: 73: Hoare triple {92229#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {92229#false} is VALID [2022-02-21 04:25:04,267 INFO L290 TraceCheckUtils]: 74: Hoare triple {92229#false} assume 1 == ~t4_pc~0; {92229#false} is VALID [2022-02-21 04:25:04,267 INFO L290 TraceCheckUtils]: 75: Hoare triple {92229#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {92229#false} is VALID [2022-02-21 04:25:04,267 INFO L290 TraceCheckUtils]: 76: Hoare triple {92229#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {92229#false} is VALID [2022-02-21 04:25:04,267 INFO L290 TraceCheckUtils]: 77: Hoare triple {92229#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {92229#false} is VALID [2022-02-21 04:25:04,267 INFO L290 TraceCheckUtils]: 78: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___3~0#1); {92229#false} is VALID [2022-02-21 04:25:04,267 INFO L290 TraceCheckUtils]: 79: Hoare triple {92229#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {92229#false} is VALID [2022-02-21 04:25:04,267 INFO L290 TraceCheckUtils]: 80: Hoare triple {92229#false} assume 1 == ~t5_pc~0; {92229#false} is VALID [2022-02-21 04:25:04,267 INFO L290 TraceCheckUtils]: 81: Hoare triple {92229#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 82: Hoare triple {92229#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 83: Hoare triple {92229#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 84: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___4~0#1); {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 85: Hoare triple {92229#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 86: Hoare triple {92229#false} assume !(1 == ~t6_pc~0); {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 87: Hoare triple {92229#false} is_transmit6_triggered_~__retres1~6#1 := 0; {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 88: Hoare triple {92229#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 89: Hoare triple {92229#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 90: Hoare triple {92229#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {92229#false} is VALID [2022-02-21 04:25:04,268 INFO L290 TraceCheckUtils]: 91: Hoare triple {92229#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {92229#false} is VALID [2022-02-21 04:25:04,269 INFO L290 TraceCheckUtils]: 92: Hoare triple {92229#false} assume 1 == ~t7_pc~0; {92229#false} is VALID [2022-02-21 04:25:04,269 INFO L290 TraceCheckUtils]: 93: Hoare triple {92229#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {92229#false} is VALID [2022-02-21 04:25:04,269 INFO L290 TraceCheckUtils]: 94: Hoare triple {92229#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {92229#false} is VALID [2022-02-21 04:25:04,269 INFO L290 TraceCheckUtils]: 95: Hoare triple {92229#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {92229#false} is VALID [2022-02-21 04:25:04,269 INFO L290 TraceCheckUtils]: 96: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___6~0#1); {92229#false} is VALID [2022-02-21 04:25:04,269 INFO L290 TraceCheckUtils]: 97: Hoare triple {92229#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {92229#false} is VALID [2022-02-21 04:25:04,269 INFO L290 TraceCheckUtils]: 98: Hoare triple {92229#false} assume !(1 == ~t8_pc~0); {92229#false} is VALID [2022-02-21 04:25:04,269 INFO L290 TraceCheckUtils]: 99: Hoare triple {92229#false} is_transmit8_triggered_~__retres1~8#1 := 0; {92229#false} is VALID [2022-02-21 04:25:04,269 INFO L290 TraceCheckUtils]: 100: Hoare triple {92229#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {92229#false} is VALID [2022-02-21 04:25:04,270 INFO L290 TraceCheckUtils]: 101: Hoare triple {92229#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {92229#false} is VALID [2022-02-21 04:25:04,270 INFO L290 TraceCheckUtils]: 102: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___7~0#1); {92229#false} is VALID [2022-02-21 04:25:04,270 INFO L290 TraceCheckUtils]: 103: Hoare triple {92229#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {92229#false} is VALID [2022-02-21 04:25:04,270 INFO L290 TraceCheckUtils]: 104: Hoare triple {92229#false} assume 1 == ~t9_pc~0; {92229#false} is VALID [2022-02-21 04:25:04,270 INFO L290 TraceCheckUtils]: 105: Hoare triple {92229#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {92229#false} is VALID [2022-02-21 04:25:04,270 INFO L290 TraceCheckUtils]: 106: Hoare triple {92229#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {92229#false} is VALID [2022-02-21 04:25:04,270 INFO L290 TraceCheckUtils]: 107: Hoare triple {92229#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {92229#false} is VALID [2022-02-21 04:25:04,270 INFO L290 TraceCheckUtils]: 108: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___8~0#1); {92229#false} is VALID [2022-02-21 04:25:04,270 INFO L290 TraceCheckUtils]: 109: Hoare triple {92229#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {92229#false} is VALID [2022-02-21 04:25:04,271 INFO L290 TraceCheckUtils]: 110: Hoare triple {92229#false} assume !(1 == ~t10_pc~0); {92229#false} is VALID [2022-02-21 04:25:04,271 INFO L290 TraceCheckUtils]: 111: Hoare triple {92229#false} is_transmit10_triggered_~__retres1~10#1 := 0; {92229#false} is VALID [2022-02-21 04:25:04,271 INFO L290 TraceCheckUtils]: 112: Hoare triple {92229#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {92229#false} is VALID [2022-02-21 04:25:04,271 INFO L290 TraceCheckUtils]: 113: Hoare triple {92229#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {92229#false} is VALID [2022-02-21 04:25:04,271 INFO L290 TraceCheckUtils]: 114: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___9~0#1); {92229#false} is VALID [2022-02-21 04:25:04,271 INFO L290 TraceCheckUtils]: 115: Hoare triple {92229#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {92229#false} is VALID [2022-02-21 04:25:04,271 INFO L290 TraceCheckUtils]: 116: Hoare triple {92229#false} assume 1 == ~t11_pc~0; {92229#false} is VALID [2022-02-21 04:25:04,271 INFO L290 TraceCheckUtils]: 117: Hoare triple {92229#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {92229#false} is VALID [2022-02-21 04:25:04,271 INFO L290 TraceCheckUtils]: 118: Hoare triple {92229#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {92229#false} is VALID [2022-02-21 04:25:04,272 INFO L290 TraceCheckUtils]: 119: Hoare triple {92229#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {92229#false} is VALID [2022-02-21 04:25:04,272 INFO L290 TraceCheckUtils]: 120: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___10~0#1); {92229#false} is VALID [2022-02-21 04:25:04,272 INFO L290 TraceCheckUtils]: 121: Hoare triple {92229#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {92229#false} is VALID [2022-02-21 04:25:04,272 INFO L290 TraceCheckUtils]: 122: Hoare triple {92229#false} assume !(1 == ~t12_pc~0); {92229#false} is VALID [2022-02-21 04:25:04,272 INFO L290 TraceCheckUtils]: 123: Hoare triple {92229#false} is_transmit12_triggered_~__retres1~12#1 := 0; {92229#false} is VALID [2022-02-21 04:25:04,272 INFO L290 TraceCheckUtils]: 124: Hoare triple {92229#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {92229#false} is VALID [2022-02-21 04:25:04,272 INFO L290 TraceCheckUtils]: 125: Hoare triple {92229#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {92229#false} is VALID [2022-02-21 04:25:04,272 INFO L290 TraceCheckUtils]: 126: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___11~0#1); {92229#false} is VALID [2022-02-21 04:25:04,272 INFO L290 TraceCheckUtils]: 127: Hoare triple {92229#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {92229#false} is VALID [2022-02-21 04:25:04,273 INFO L290 TraceCheckUtils]: 128: Hoare triple {92229#false} assume 1 == ~t13_pc~0; {92229#false} is VALID [2022-02-21 04:25:04,273 INFO L290 TraceCheckUtils]: 129: Hoare triple {92229#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {92229#false} is VALID [2022-02-21 04:25:04,273 INFO L290 TraceCheckUtils]: 130: Hoare triple {92229#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {92229#false} is VALID [2022-02-21 04:25:04,273 INFO L290 TraceCheckUtils]: 131: Hoare triple {92229#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {92229#false} is VALID [2022-02-21 04:25:04,273 INFO L290 TraceCheckUtils]: 132: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___12~0#1); {92229#false} is VALID [2022-02-21 04:25:04,273 INFO L290 TraceCheckUtils]: 133: Hoare triple {92229#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {92229#false} is VALID [2022-02-21 04:25:04,273 INFO L290 TraceCheckUtils]: 134: Hoare triple {92229#false} assume 1 == ~t14_pc~0; {92229#false} is VALID [2022-02-21 04:25:04,273 INFO L290 TraceCheckUtils]: 135: Hoare triple {92229#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {92229#false} is VALID [2022-02-21 04:25:04,273 INFO L290 TraceCheckUtils]: 136: Hoare triple {92229#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 137: Hoare triple {92229#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 138: Hoare triple {92229#false} assume !(0 != activate_threads_~tmp___13~0#1); {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 139: Hoare triple {92229#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 140: Hoare triple {92229#false} assume 1 == ~M_E~0;~M_E~0 := 2; {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 141: Hoare triple {92229#false} assume !(1 == ~T1_E~0); {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 142: Hoare triple {92229#false} assume !(1 == ~T2_E~0); {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 143: Hoare triple {92229#false} assume !(1 == ~T3_E~0); {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 144: Hoare triple {92229#false} assume !(1 == ~T4_E~0); {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 145: Hoare triple {92229#false} assume !(1 == ~T5_E~0); {92229#false} is VALID [2022-02-21 04:25:04,274 INFO L290 TraceCheckUtils]: 146: Hoare triple {92229#false} assume !(1 == ~T6_E~0); {92229#false} is VALID [2022-02-21 04:25:04,275 INFO L290 TraceCheckUtils]: 147: Hoare triple {92229#false} assume !(1 == ~T7_E~0); {92229#false} is VALID [2022-02-21 04:25:04,275 INFO L290 TraceCheckUtils]: 148: Hoare triple {92229#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {92229#false} is VALID [2022-02-21 04:25:04,275 INFO L290 TraceCheckUtils]: 149: Hoare triple {92229#false} assume !(1 == ~T9_E~0); {92229#false} is VALID [2022-02-21 04:25:04,275 INFO L290 TraceCheckUtils]: 150: Hoare triple {92229#false} assume !(1 == ~T10_E~0); {92229#false} is VALID [2022-02-21 04:25:04,275 INFO L290 TraceCheckUtils]: 151: Hoare triple {92229#false} assume !(1 == ~T11_E~0); {92229#false} is VALID [2022-02-21 04:25:04,275 INFO L290 TraceCheckUtils]: 152: Hoare triple {92229#false} assume !(1 == ~T12_E~0); {92229#false} is VALID [2022-02-21 04:25:04,275 INFO L290 TraceCheckUtils]: 153: Hoare triple {92229#false} assume !(1 == ~T13_E~0); {92229#false} is VALID [2022-02-21 04:25:04,275 INFO L290 TraceCheckUtils]: 154: Hoare triple {92229#false} assume !(1 == ~T14_E~0); {92229#false} is VALID [2022-02-21 04:25:04,275 INFO L290 TraceCheckUtils]: 155: Hoare triple {92229#false} assume !(1 == ~E_1~0); {92229#false} is VALID [2022-02-21 04:25:04,276 INFO L290 TraceCheckUtils]: 156: Hoare triple {92229#false} assume 1 == ~E_2~0;~E_2~0 := 2; {92229#false} is VALID [2022-02-21 04:25:04,276 INFO L290 TraceCheckUtils]: 157: Hoare triple {92229#false} assume !(1 == ~E_3~0); {92229#false} is VALID [2022-02-21 04:25:04,276 INFO L290 TraceCheckUtils]: 158: Hoare triple {92229#false} assume !(1 == ~E_4~0); {92229#false} is VALID [2022-02-21 04:25:04,276 INFO L290 TraceCheckUtils]: 159: Hoare triple {92229#false} assume !(1 == ~E_5~0); {92229#false} is VALID [2022-02-21 04:25:04,276 INFO L290 TraceCheckUtils]: 160: Hoare triple {92229#false} assume !(1 == ~E_6~0); {92229#false} is VALID [2022-02-21 04:25:04,276 INFO L290 TraceCheckUtils]: 161: Hoare triple {92229#false} assume !(1 == ~E_7~0); {92229#false} is VALID [2022-02-21 04:25:04,276 INFO L290 TraceCheckUtils]: 162: Hoare triple {92229#false} assume !(1 == ~E_8~0); {92229#false} is VALID [2022-02-21 04:25:04,276 INFO L290 TraceCheckUtils]: 163: Hoare triple {92229#false} assume !(1 == ~E_9~0); {92229#false} is VALID [2022-02-21 04:25:04,276 INFO L290 TraceCheckUtils]: 164: Hoare triple {92229#false} assume 1 == ~E_10~0;~E_10~0 := 2; {92229#false} is VALID [2022-02-21 04:25:04,277 INFO L290 TraceCheckUtils]: 165: Hoare triple {92229#false} assume !(1 == ~E_11~0); {92229#false} is VALID [2022-02-21 04:25:04,277 INFO L290 TraceCheckUtils]: 166: Hoare triple {92229#false} assume !(1 == ~E_12~0); {92229#false} is VALID [2022-02-21 04:25:04,277 INFO L290 TraceCheckUtils]: 167: Hoare triple {92229#false} assume !(1 == ~E_13~0); {92229#false} is VALID [2022-02-21 04:25:04,277 INFO L290 TraceCheckUtils]: 168: Hoare triple {92229#false} assume !(1 == ~E_14~0); {92229#false} is VALID [2022-02-21 04:25:04,277 INFO L290 TraceCheckUtils]: 169: Hoare triple {92229#false} assume { :end_inline_reset_delta_events } true; {92229#false} is VALID [2022-02-21 04:25:04,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:04,278 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:04,278 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [70111954] [2022-02-21 04:25:04,278 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [70111954] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:04,278 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:04,278 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:04,278 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792820788] [2022-02-21 04:25:04,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:04,279 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:04,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:04,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1359797623, now seen corresponding path program 1 times [2022-02-21 04:25:04,279 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:04,279 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1175415444] [2022-02-21 04:25:04,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:04,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:04,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:04,336 INFO L290 TraceCheckUtils]: 0: Hoare triple {92231#true} assume !false; {92231#true} is VALID [2022-02-21 04:25:04,337 INFO L290 TraceCheckUtils]: 1: Hoare triple {92231#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {92231#true} is VALID [2022-02-21 04:25:04,337 INFO L290 TraceCheckUtils]: 2: Hoare triple {92231#true} assume !false; {92231#true} is VALID [2022-02-21 04:25:04,337 INFO L290 TraceCheckUtils]: 3: Hoare triple {92231#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {92231#true} is VALID [2022-02-21 04:25:04,337 INFO L290 TraceCheckUtils]: 4: Hoare triple {92231#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {92231#true} is VALID [2022-02-21 04:25:04,337 INFO L290 TraceCheckUtils]: 5: Hoare triple {92231#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {92231#true} is VALID [2022-02-21 04:25:04,337 INFO L290 TraceCheckUtils]: 6: Hoare triple {92231#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {92231#true} is VALID [2022-02-21 04:25:04,338 INFO L290 TraceCheckUtils]: 7: Hoare triple {92231#true} assume !(0 != eval_~tmp~0#1); {92231#true} is VALID [2022-02-21 04:25:04,338 INFO L290 TraceCheckUtils]: 8: Hoare triple {92231#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {92231#true} is VALID [2022-02-21 04:25:04,338 INFO L290 TraceCheckUtils]: 9: Hoare triple {92231#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {92231#true} is VALID [2022-02-21 04:25:04,338 INFO L290 TraceCheckUtils]: 10: Hoare triple {92231#true} assume 0 == ~M_E~0;~M_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,339 INFO L290 TraceCheckUtils]: 11: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,339 INFO L290 TraceCheckUtils]: 12: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,339 INFO L290 TraceCheckUtils]: 13: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,339 INFO L290 TraceCheckUtils]: 14: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,340 INFO L290 TraceCheckUtils]: 15: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,340 INFO L290 TraceCheckUtils]: 16: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,340 INFO L290 TraceCheckUtils]: 17: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,341 INFO L290 TraceCheckUtils]: 18: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,341 INFO L290 TraceCheckUtils]: 19: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,341 INFO L290 TraceCheckUtils]: 20: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,342 INFO L290 TraceCheckUtils]: 21: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,342 INFO L290 TraceCheckUtils]: 22: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,342 INFO L290 TraceCheckUtils]: 23: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,343 INFO L290 TraceCheckUtils]: 24: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,343 INFO L290 TraceCheckUtils]: 25: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,343 INFO L290 TraceCheckUtils]: 26: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,344 INFO L290 TraceCheckUtils]: 27: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,344 INFO L290 TraceCheckUtils]: 28: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,344 INFO L290 TraceCheckUtils]: 29: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,345 INFO L290 TraceCheckUtils]: 30: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,345 INFO L290 TraceCheckUtils]: 31: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,345 INFO L290 TraceCheckUtils]: 32: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,345 INFO L290 TraceCheckUtils]: 33: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,346 INFO L290 TraceCheckUtils]: 34: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,346 INFO L290 TraceCheckUtils]: 35: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,346 INFO L290 TraceCheckUtils]: 36: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,347 INFO L290 TraceCheckUtils]: 37: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,347 INFO L290 TraceCheckUtils]: 38: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,347 INFO L290 TraceCheckUtils]: 39: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,348 INFO L290 TraceCheckUtils]: 40: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,348 INFO L290 TraceCheckUtils]: 41: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,348 INFO L290 TraceCheckUtils]: 42: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,349 INFO L290 TraceCheckUtils]: 43: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,349 INFO L290 TraceCheckUtils]: 44: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,349 INFO L290 TraceCheckUtils]: 45: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,350 INFO L290 TraceCheckUtils]: 46: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,350 INFO L290 TraceCheckUtils]: 47: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,350 INFO L290 TraceCheckUtils]: 48: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,351 INFO L290 TraceCheckUtils]: 49: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,358 INFO L290 TraceCheckUtils]: 50: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,358 INFO L290 TraceCheckUtils]: 51: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,359 INFO L290 TraceCheckUtils]: 52: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,359 INFO L290 TraceCheckUtils]: 53: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,359 INFO L290 TraceCheckUtils]: 54: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,360 INFO L290 TraceCheckUtils]: 55: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,360 INFO L290 TraceCheckUtils]: 56: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,360 INFO L290 TraceCheckUtils]: 57: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,361 INFO L290 TraceCheckUtils]: 58: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,361 INFO L290 TraceCheckUtils]: 59: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,361 INFO L290 TraceCheckUtils]: 60: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,362 INFO L290 TraceCheckUtils]: 61: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,362 INFO L290 TraceCheckUtils]: 62: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,362 INFO L290 TraceCheckUtils]: 63: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,363 INFO L290 TraceCheckUtils]: 64: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,363 INFO L290 TraceCheckUtils]: 65: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,363 INFO L290 TraceCheckUtils]: 66: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,364 INFO L290 TraceCheckUtils]: 67: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,364 INFO L290 TraceCheckUtils]: 68: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,364 INFO L290 TraceCheckUtils]: 69: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,365 INFO L290 TraceCheckUtils]: 70: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,365 INFO L290 TraceCheckUtils]: 71: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,365 INFO L290 TraceCheckUtils]: 72: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,366 INFO L290 TraceCheckUtils]: 73: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,366 INFO L290 TraceCheckUtils]: 74: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,366 INFO L290 TraceCheckUtils]: 75: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,366 INFO L290 TraceCheckUtils]: 76: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,367 INFO L290 TraceCheckUtils]: 77: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,367 INFO L290 TraceCheckUtils]: 78: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,367 INFO L290 TraceCheckUtils]: 79: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,368 INFO L290 TraceCheckUtils]: 80: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,368 INFO L290 TraceCheckUtils]: 81: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,368 INFO L290 TraceCheckUtils]: 82: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,369 INFO L290 TraceCheckUtils]: 83: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,369 INFO L290 TraceCheckUtils]: 84: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,369 INFO L290 TraceCheckUtils]: 85: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,370 INFO L290 TraceCheckUtils]: 86: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,370 INFO L290 TraceCheckUtils]: 87: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,370 INFO L290 TraceCheckUtils]: 88: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,371 INFO L290 TraceCheckUtils]: 89: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,371 INFO L290 TraceCheckUtils]: 90: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,371 INFO L290 TraceCheckUtils]: 91: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,372 INFO L290 TraceCheckUtils]: 92: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,372 INFO L290 TraceCheckUtils]: 93: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,384 INFO L290 TraceCheckUtils]: 94: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,385 INFO L290 TraceCheckUtils]: 95: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,385 INFO L290 TraceCheckUtils]: 96: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,386 INFO L290 TraceCheckUtils]: 97: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,386 INFO L290 TraceCheckUtils]: 98: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,386 INFO L290 TraceCheckUtils]: 99: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,386 INFO L290 TraceCheckUtils]: 100: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,387 INFO L290 TraceCheckUtils]: 101: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,387 INFO L290 TraceCheckUtils]: 102: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,387 INFO L290 TraceCheckUtils]: 103: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,388 INFO L290 TraceCheckUtils]: 104: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,388 INFO L290 TraceCheckUtils]: 105: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,388 INFO L290 TraceCheckUtils]: 106: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,388 INFO L290 TraceCheckUtils]: 107: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,389 INFO L290 TraceCheckUtils]: 108: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,389 INFO L290 TraceCheckUtils]: 109: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,389 INFO L290 TraceCheckUtils]: 110: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,390 INFO L290 TraceCheckUtils]: 111: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,390 INFO L290 TraceCheckUtils]: 112: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,390 INFO L290 TraceCheckUtils]: 113: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,390 INFO L290 TraceCheckUtils]: 114: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,391 INFO L290 TraceCheckUtils]: 115: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,391 INFO L290 TraceCheckUtils]: 116: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,391 INFO L290 TraceCheckUtils]: 117: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,391 INFO L290 TraceCheckUtils]: 118: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,392 INFO L290 TraceCheckUtils]: 119: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,392 INFO L290 TraceCheckUtils]: 120: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,392 INFO L290 TraceCheckUtils]: 121: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,393 INFO L290 TraceCheckUtils]: 122: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,393 INFO L290 TraceCheckUtils]: 123: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,393 INFO L290 TraceCheckUtils]: 124: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,393 INFO L290 TraceCheckUtils]: 125: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,394 INFO L290 TraceCheckUtils]: 126: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,394 INFO L290 TraceCheckUtils]: 127: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,394 INFO L290 TraceCheckUtils]: 128: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,395 INFO L290 TraceCheckUtils]: 129: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {92233#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:04,395 INFO L290 TraceCheckUtils]: 130: Hoare triple {92233#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {92232#false} is VALID [2022-02-21 04:25:04,395 INFO L290 TraceCheckUtils]: 131: Hoare triple {92232#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,395 INFO L290 TraceCheckUtils]: 132: Hoare triple {92232#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,395 INFO L290 TraceCheckUtils]: 133: Hoare triple {92232#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,395 INFO L290 TraceCheckUtils]: 134: Hoare triple {92232#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,395 INFO L290 TraceCheckUtils]: 135: Hoare triple {92232#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,395 INFO L290 TraceCheckUtils]: 136: Hoare triple {92232#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,396 INFO L290 TraceCheckUtils]: 137: Hoare triple {92232#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,396 INFO L290 TraceCheckUtils]: 138: Hoare triple {92232#false} assume !(1 == ~T8_E~0); {92232#false} is VALID [2022-02-21 04:25:04,396 INFO L290 TraceCheckUtils]: 139: Hoare triple {92232#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,396 INFO L290 TraceCheckUtils]: 140: Hoare triple {92232#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,396 INFO L290 TraceCheckUtils]: 141: Hoare triple {92232#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,396 INFO L290 TraceCheckUtils]: 142: Hoare triple {92232#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,396 INFO L290 TraceCheckUtils]: 143: Hoare triple {92232#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,396 INFO L290 TraceCheckUtils]: 144: Hoare triple {92232#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,396 INFO L290 TraceCheckUtils]: 145: Hoare triple {92232#false} assume 1 == ~E_1~0;~E_1~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,397 INFO L290 TraceCheckUtils]: 146: Hoare triple {92232#false} assume !(1 == ~E_2~0); {92232#false} is VALID [2022-02-21 04:25:04,397 INFO L290 TraceCheckUtils]: 147: Hoare triple {92232#false} assume 1 == ~E_3~0;~E_3~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,397 INFO L290 TraceCheckUtils]: 148: Hoare triple {92232#false} assume 1 == ~E_4~0;~E_4~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,397 INFO L290 TraceCheckUtils]: 149: Hoare triple {92232#false} assume 1 == ~E_5~0;~E_5~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,397 INFO L290 TraceCheckUtils]: 150: Hoare triple {92232#false} assume 1 == ~E_6~0;~E_6~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,397 INFO L290 TraceCheckUtils]: 151: Hoare triple {92232#false} assume 1 == ~E_7~0;~E_7~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,397 INFO L290 TraceCheckUtils]: 152: Hoare triple {92232#false} assume 1 == ~E_8~0;~E_8~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,397 INFO L290 TraceCheckUtils]: 153: Hoare triple {92232#false} assume 1 == ~E_9~0;~E_9~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,397 INFO L290 TraceCheckUtils]: 154: Hoare triple {92232#false} assume !(1 == ~E_10~0); {92232#false} is VALID [2022-02-21 04:25:04,398 INFO L290 TraceCheckUtils]: 155: Hoare triple {92232#false} assume 1 == ~E_11~0;~E_11~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,398 INFO L290 TraceCheckUtils]: 156: Hoare triple {92232#false} assume 1 == ~E_12~0;~E_12~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,398 INFO L290 TraceCheckUtils]: 157: Hoare triple {92232#false} assume 1 == ~E_13~0;~E_13~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,398 INFO L290 TraceCheckUtils]: 158: Hoare triple {92232#false} assume 1 == ~E_14~0;~E_14~0 := 2; {92232#false} is VALID [2022-02-21 04:25:04,398 INFO L290 TraceCheckUtils]: 159: Hoare triple {92232#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {92232#false} is VALID [2022-02-21 04:25:04,398 INFO L290 TraceCheckUtils]: 160: Hoare triple {92232#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {92232#false} is VALID [2022-02-21 04:25:04,398 INFO L290 TraceCheckUtils]: 161: Hoare triple {92232#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {92232#false} is VALID [2022-02-21 04:25:04,398 INFO L290 TraceCheckUtils]: 162: Hoare triple {92232#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {92232#false} is VALID [2022-02-21 04:25:04,398 INFO L290 TraceCheckUtils]: 163: Hoare triple {92232#false} assume !(0 == start_simulation_~tmp~3#1); {92232#false} is VALID [2022-02-21 04:25:04,399 INFO L290 TraceCheckUtils]: 164: Hoare triple {92232#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {92232#false} is VALID [2022-02-21 04:25:04,399 INFO L290 TraceCheckUtils]: 165: Hoare triple {92232#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {92232#false} is VALID [2022-02-21 04:25:04,399 INFO L290 TraceCheckUtils]: 166: Hoare triple {92232#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {92232#false} is VALID [2022-02-21 04:25:04,399 INFO L290 TraceCheckUtils]: 167: Hoare triple {92232#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {92232#false} is VALID [2022-02-21 04:25:04,399 INFO L290 TraceCheckUtils]: 168: Hoare triple {92232#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {92232#false} is VALID [2022-02-21 04:25:04,399 INFO L290 TraceCheckUtils]: 169: Hoare triple {92232#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {92232#false} is VALID [2022-02-21 04:25:04,399 INFO L290 TraceCheckUtils]: 170: Hoare triple {92232#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {92232#false} is VALID [2022-02-21 04:25:04,399 INFO L290 TraceCheckUtils]: 171: Hoare triple {92232#false} assume !(0 != start_simulation_~tmp___0~1#1); {92232#false} is VALID [2022-02-21 04:25:04,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:04,400 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:04,400 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1175415444] [2022-02-21 04:25:04,400 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1175415444] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:04,400 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:04,400 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:04,401 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661728708] [2022-02-21 04:25:04,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:04,402 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:04,402 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:04,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:25:04,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:25:04,402 INFO L87 Difference]: Start difference. First operand 2047 states and 3024 transitions. cyclomatic complexity: 978 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:05,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:05,876 INFO L93 Difference]: Finished difference Result 2047 states and 3023 transitions. [2022-02-21 04:25:05,876 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:25:05,876 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:05,974 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:05,974 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3023 transitions. [2022-02-21 04:25:06,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:06,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3023 transitions. [2022-02-21 04:25:06,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:25:06,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:25:06,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3023 transitions. [2022-02-21 04:25:06,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:06,156 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2022-02-21 04:25:06,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3023 transitions. [2022-02-21 04:25:06,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:25:06,184 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:06,186 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3023 transitions. Second operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:06,188 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3023 transitions. Second operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:06,189 INFO L87 Difference]: Start difference. First operand 2047 states and 3023 transitions. Second operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:06,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:06,274 INFO L93 Difference]: Finished difference Result 2047 states and 3023 transitions. [2022-02-21 04:25:06,274 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3023 transitions. [2022-02-21 04:25:06,276 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:06,276 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:06,279 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3023 transitions. [2022-02-21 04:25:06,280 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3023 transitions. [2022-02-21 04:25:06,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:06,368 INFO L93 Difference]: Finished difference Result 2047 states and 3023 transitions. [2022-02-21 04:25:06,368 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3023 transitions. [2022-02-21 04:25:06,370 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:06,370 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:06,370 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:06,370 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:06,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:06,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3023 transitions. [2022-02-21 04:25:06,457 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2022-02-21 04:25:06,457 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2022-02-21 04:25:06,457 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:25:06,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3023 transitions. [2022-02-21 04:25:06,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:06,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:06,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:06,462 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:06,463 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:06,463 INFO L791 eck$LassoCheckResult]: Stem: 95207#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 95208#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 95810#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94927#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94928#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 95173#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95174#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94901#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94902#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96125#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95477#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95478#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95995#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95387#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 95388#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 94808#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 94809#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 95140#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 95338#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 94385#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94386#L1342 assume !(0 == ~M_E~0); 94551#L1342-2 assume !(0 == ~T1_E~0); 95107#L1347-1 assume !(0 == ~T2_E~0); 96108#L1352-1 assume !(0 == ~T3_E~0); 95904#L1357-1 assume !(0 == ~T4_E~0); 95132#L1362-1 assume !(0 == ~T5_E~0); 95133#L1367-1 assume !(0 == ~T6_E~0); 94730#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 94731#L1377-1 assume !(0 == ~T8_E~0); 95061#L1382-1 assume !(0 == ~T9_E~0); 95062#L1387-1 assume !(0 == ~T10_E~0); 95789#L1392-1 assume !(0 == ~T11_E~0); 95093#L1397-1 assume !(0 == ~T12_E~0); 95094#L1402-1 assume !(0 == ~T13_E~0); 94746#L1407-1 assume !(0 == ~T14_E~0); 94747#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 96025#L1417-1 assume !(0 == ~E_2~0); 96026#L1422-1 assume !(0 == ~E_3~0); 96267#L1427-1 assume !(0 == ~E_4~0); 94934#L1432-1 assume !(0 == ~E_5~0); 94935#L1437-1 assume !(0 == ~E_6~0); 95943#L1442-1 assume !(0 == ~E_7~0); 95944#L1447-1 assume !(0 == ~E_8~0); 95786#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 94521#L1457-1 assume !(0 == ~E_10~0); 94522#L1462-1 assume !(0 == ~E_11~0); 95978#L1467-1 assume !(0 == ~E_12~0); 95990#L1472-1 assume !(0 == ~E_13~0); 95991#L1477-1 assume !(0 == ~E_14~0); 95733#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94720#L646 assume 1 == ~m_pc~0; 94721#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 95397#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95412#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 94810#L1666 assume !(0 != activate_threads_~tmp~1#1); 94811#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96288#L665 assume !(1 == ~t1_pc~0); 95286#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95287#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94819#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94820#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 95610#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95611#L684 assume 1 == ~t2_pc~0; 95728#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95652#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95717#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96112#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 96113#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96301#L703 assume !(1 == ~t3_pc~0); 94956#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94957#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95603#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94355#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 94356#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94841#L722 assume 1 == ~t4_pc~0; 95579#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95022#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95367#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95927#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 95434#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94552#L741 assume 1 == ~t5_pc~0; 94553#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94863#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95017#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 95018#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 95697#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95108#L760 assume !(1 == ~t6_pc~0); 94955#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 94954#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94812#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94813#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95534#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95535#L779 assume 1 == ~t7_pc~0; 94597#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 94443#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94444#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94852#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 94875#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94876#L798 assume !(1 == ~t8_pc~0); 96157#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 96080#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 94599#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94600#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 96290#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94420#L817 assume 1 == ~t9_pc~0; 94421#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95215#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95216#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95738#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 94826#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 94827#L836 assume !(1 == ~t10_pc~0); 94843#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 94774#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94775#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 95023#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 95024#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 96090#L855 assume 1 == ~t11_pc~0; 95408#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95409#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95973#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 95782#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 95617#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 94716#L874 assume !(1 == ~t12_pc~0); 94717#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 94884#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 94885#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 95025#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 94393#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 94394#L893 assume 1 == ~t13_pc~0; 96224#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 94749#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 95060#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 96151#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 96159#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 96160#L912 assume 1 == ~t14_pc~0; 95950#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 95951#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 94719#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 94651#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 94652#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95427#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 95843#L1495-2 assume !(1 == ~T1_E~0); 95844#L1500-1 assume !(1 == ~T2_E~0); 95530#L1505-1 assume !(1 == ~T3_E~0); 95531#L1510-1 assume !(1 == ~T4_E~0); 95588#L1515-1 assume !(1 == ~T5_E~0); 95589#L1520-1 assume !(1 == ~T6_E~0); 96158#L1525-1 assume !(1 == ~T7_E~0); 95868#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 94821#L1535-1 assume !(1 == ~T9_E~0); 94822#L1540-1 assume !(1 == ~T10_E~0); 94314#L1545-1 assume !(1 == ~T11_E~0); 94315#L1550-1 assume !(1 == ~T12_E~0); 94563#L1555-1 assume !(1 == ~T13_E~0); 94564#L1560-1 assume !(1 == ~T14_E~0); 94864#L1565-1 assume !(1 == ~E_1~0); 96277#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 95755#L1575-1 assume !(1 == ~E_3~0); 95134#L1580-1 assume !(1 == ~E_4~0); 95135#L1585-1 assume !(1 == ~E_5~0); 95605#L1590-1 assume !(1 == ~E_6~0); 95169#L1595-1 assume !(1 == ~E_7~0); 95170#L1600-1 assume !(1 == ~E_8~0); 95542#L1605-1 assume !(1 == ~E_9~0); 95543#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 96060#L1615-1 assume !(1 == ~E_11~0); 94999#L1620-1 assume !(1 == ~E_12~0); 95000#L1625-1 assume !(1 == ~E_13~0); 95787#L1630-1 assume !(1 == ~E_14~0); 95168#L1635-1 assume { :end_inline_reset_delta_events } true; 95109#L2017-2 [2022-02-21 04:25:06,463 INFO L793 eck$LassoCheckResult]: Loop: 95109#L2017-2 assume !false; 94389#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 94390#L1316 assume !false; 95718#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 95780#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 94327#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 94469#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 94470#L1115 assume !(0 != eval_~tmp~0#1); 95803#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 95224#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 95225#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 95407#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 95908#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 95577#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95578#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96140#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96315#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 96310#L1372-3 assume !(0 == ~T7_E~0); 94371#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 94372#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 95041#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 95042#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 95953#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 96263#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 95521#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 94677#L1412-3 assume !(0 == ~E_1~0); 94678#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 95442#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 95443#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 96137#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 95824#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 95536#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 95537#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 94437#L1452-3 assume !(0 == ~E_9~0); 94438#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 96076#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 96077#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 95881#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 95882#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 94675#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94676#L646-42 assume 1 == ~m_pc~0; 95261#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 96109#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96110#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96248#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96249#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96041#L665-42 assume !(1 == ~t1_pc~0); 96003#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 96004#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96190#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94844#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 94845#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96314#L684-42 assume 1 == ~t2_pc~0; 95693#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95694#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96304#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95473#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95474#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95596#L703-42 assume 1 == ~t3_pc~0; 95794#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95795#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95113#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95114#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 95888#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95508#L722-42 assume 1 == ~t4_pc~0; 95509#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95919#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95162#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94989#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94990#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96284#L741-42 assume 1 == ~t5_pc~0; 96226#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95371#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95372#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96317#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 95279#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95280#L760-42 assume 1 == ~t6_pc~0; 95415#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 95549#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95550#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 95938#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 95231#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95232#L779-42 assume !(1 == ~t7_pc~0); 96008#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 96009#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94918#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94919#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 94772#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94773#L798-42 assume 1 == ~t8_pc~0; 95223#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94384#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96127#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95573#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 94603#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94604#L817-42 assume 1 == ~t9_pc~0; 95379#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 94887#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94888#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95014#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 95819#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95820#L836-42 assume !(1 == ~t10_pc~0); 95913#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 94925#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94926#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96227#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 96228#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 96269#L855-42 assume !(1 == ~t11_pc~0); 96283#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 94476#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 94477#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 95226#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 95989#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 95090#L874-42 assume 1 == ~t12_pc~0; 95091#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 95333#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 94391#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 94392#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 94645#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 94646#L893-42 assume 1 == ~t13_pc~0; 95849#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 95630#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 95645#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 95547#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 95019#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 95020#L912-42 assume !(1 == ~t14_pc~0); 95829#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 94337#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 94338#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 95918#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 94765#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94766#L1495-3 assume !(1 == ~M_E~0); 95381#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 95809#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 95902#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94995#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94958#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94959#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 95616#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 95839#L1530-3 assume !(1 == ~T8_E~0); 94804#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 94805#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 94842#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 96099#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 96208#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 95248#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 95249#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 95864#L1570-3 assume !(1 == ~E_2~0); 95815#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 95816#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96171#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 96216#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 96261#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 95638#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 95639#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 96114#L1610-3 assume !(1 == ~E_10~0); 95001#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 95002#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 95606#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 95607#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 95511#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 94942#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 94547#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 95285#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 95841#L2036 assume !(0 == start_simulation_~tmp~3#1); 95842#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 95994#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 95154#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 96172#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 95554#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 95555#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 96275#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 96276#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 95109#L2017-2 [2022-02-21 04:25:06,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:06,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1016333162, now seen corresponding path program 1 times [2022-02-21 04:25:06,464 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:06,464 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521198907] [2022-02-21 04:25:06,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:06,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:06,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:06,483 INFO L290 TraceCheckUtils]: 0: Hoare triple {100425#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {100425#true} is VALID [2022-02-21 04:25:06,484 INFO L290 TraceCheckUtils]: 1: Hoare triple {100425#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,484 INFO L290 TraceCheckUtils]: 2: Hoare triple {100427#(= ~t13_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,484 INFO L290 TraceCheckUtils]: 3: Hoare triple {100427#(= ~t13_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,484 INFO L290 TraceCheckUtils]: 4: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,485 INFO L290 TraceCheckUtils]: 5: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,485 INFO L290 TraceCheckUtils]: 6: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,485 INFO L290 TraceCheckUtils]: 7: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,485 INFO L290 TraceCheckUtils]: 8: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,486 INFO L290 TraceCheckUtils]: 9: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,486 INFO L290 TraceCheckUtils]: 10: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,486 INFO L290 TraceCheckUtils]: 11: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,487 INFO L290 TraceCheckUtils]: 12: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,487 INFO L290 TraceCheckUtils]: 13: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,487 INFO L290 TraceCheckUtils]: 14: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,487 INFO L290 TraceCheckUtils]: 15: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,488 INFO L290 TraceCheckUtils]: 16: Hoare triple {100427#(= ~t13_i~0 1)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {100427#(= ~t13_i~0 1)} is VALID [2022-02-21 04:25:06,488 INFO L290 TraceCheckUtils]: 17: Hoare triple {100427#(= ~t13_i~0 1)} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {100426#false} is VALID [2022-02-21 04:25:06,488 INFO L290 TraceCheckUtils]: 18: Hoare triple {100426#false} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {100426#false} is VALID [2022-02-21 04:25:06,488 INFO L290 TraceCheckUtils]: 19: Hoare triple {100426#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {100426#false} is VALID [2022-02-21 04:25:06,488 INFO L290 TraceCheckUtils]: 20: Hoare triple {100426#false} assume !(0 == ~M_E~0); {100426#false} is VALID [2022-02-21 04:25:06,488 INFO L290 TraceCheckUtils]: 21: Hoare triple {100426#false} assume !(0 == ~T1_E~0); {100426#false} is VALID [2022-02-21 04:25:06,488 INFO L290 TraceCheckUtils]: 22: Hoare triple {100426#false} assume !(0 == ~T2_E~0); {100426#false} is VALID [2022-02-21 04:25:06,489 INFO L290 TraceCheckUtils]: 23: Hoare triple {100426#false} assume !(0 == ~T3_E~0); {100426#false} is VALID [2022-02-21 04:25:06,489 INFO L290 TraceCheckUtils]: 24: Hoare triple {100426#false} assume !(0 == ~T4_E~0); {100426#false} is VALID [2022-02-21 04:25:06,489 INFO L290 TraceCheckUtils]: 25: Hoare triple {100426#false} assume !(0 == ~T5_E~0); {100426#false} is VALID [2022-02-21 04:25:06,489 INFO L290 TraceCheckUtils]: 26: Hoare triple {100426#false} assume !(0 == ~T6_E~0); {100426#false} is VALID [2022-02-21 04:25:06,489 INFO L290 TraceCheckUtils]: 27: Hoare triple {100426#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {100426#false} is VALID [2022-02-21 04:25:06,489 INFO L290 TraceCheckUtils]: 28: Hoare triple {100426#false} assume !(0 == ~T8_E~0); {100426#false} is VALID [2022-02-21 04:25:06,489 INFO L290 TraceCheckUtils]: 29: Hoare triple {100426#false} assume !(0 == ~T9_E~0); {100426#false} is VALID [2022-02-21 04:25:06,489 INFO L290 TraceCheckUtils]: 30: Hoare triple {100426#false} assume !(0 == ~T10_E~0); {100426#false} is VALID [2022-02-21 04:25:06,489 INFO L290 TraceCheckUtils]: 31: Hoare triple {100426#false} assume !(0 == ~T11_E~0); {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 32: Hoare triple {100426#false} assume !(0 == ~T12_E~0); {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 33: Hoare triple {100426#false} assume !(0 == ~T13_E~0); {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 34: Hoare triple {100426#false} assume !(0 == ~T14_E~0); {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 35: Hoare triple {100426#false} assume 0 == ~E_1~0;~E_1~0 := 1; {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 36: Hoare triple {100426#false} assume !(0 == ~E_2~0); {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 37: Hoare triple {100426#false} assume !(0 == ~E_3~0); {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 38: Hoare triple {100426#false} assume !(0 == ~E_4~0); {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 39: Hoare triple {100426#false} assume !(0 == ~E_5~0); {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 40: Hoare triple {100426#false} assume !(0 == ~E_6~0); {100426#false} is VALID [2022-02-21 04:25:06,490 INFO L290 TraceCheckUtils]: 41: Hoare triple {100426#false} assume !(0 == ~E_7~0); {100426#false} is VALID [2022-02-21 04:25:06,491 INFO L290 TraceCheckUtils]: 42: Hoare triple {100426#false} assume !(0 == ~E_8~0); {100426#false} is VALID [2022-02-21 04:25:06,491 INFO L290 TraceCheckUtils]: 43: Hoare triple {100426#false} assume 0 == ~E_9~0;~E_9~0 := 1; {100426#false} is VALID [2022-02-21 04:25:06,491 INFO L290 TraceCheckUtils]: 44: Hoare triple {100426#false} assume !(0 == ~E_10~0); {100426#false} is VALID [2022-02-21 04:25:06,491 INFO L290 TraceCheckUtils]: 45: Hoare triple {100426#false} assume !(0 == ~E_11~0); {100426#false} is VALID [2022-02-21 04:25:06,491 INFO L290 TraceCheckUtils]: 46: Hoare triple {100426#false} assume !(0 == ~E_12~0); {100426#false} is VALID [2022-02-21 04:25:06,491 INFO L290 TraceCheckUtils]: 47: Hoare triple {100426#false} assume !(0 == ~E_13~0); {100426#false} is VALID [2022-02-21 04:25:06,491 INFO L290 TraceCheckUtils]: 48: Hoare triple {100426#false} assume !(0 == ~E_14~0); {100426#false} is VALID [2022-02-21 04:25:06,491 INFO L290 TraceCheckUtils]: 49: Hoare triple {100426#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {100426#false} is VALID [2022-02-21 04:25:06,491 INFO L290 TraceCheckUtils]: 50: Hoare triple {100426#false} assume 1 == ~m_pc~0; {100426#false} is VALID [2022-02-21 04:25:06,492 INFO L290 TraceCheckUtils]: 51: Hoare triple {100426#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {100426#false} is VALID [2022-02-21 04:25:06,492 INFO L290 TraceCheckUtils]: 52: Hoare triple {100426#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {100426#false} is VALID [2022-02-21 04:25:06,492 INFO L290 TraceCheckUtils]: 53: Hoare triple {100426#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {100426#false} is VALID [2022-02-21 04:25:06,492 INFO L290 TraceCheckUtils]: 54: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp~1#1); {100426#false} is VALID [2022-02-21 04:25:06,492 INFO L290 TraceCheckUtils]: 55: Hoare triple {100426#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {100426#false} is VALID [2022-02-21 04:25:06,492 INFO L290 TraceCheckUtils]: 56: Hoare triple {100426#false} assume !(1 == ~t1_pc~0); {100426#false} is VALID [2022-02-21 04:25:06,492 INFO L290 TraceCheckUtils]: 57: Hoare triple {100426#false} is_transmit1_triggered_~__retres1~1#1 := 0; {100426#false} is VALID [2022-02-21 04:25:06,492 INFO L290 TraceCheckUtils]: 58: Hoare triple {100426#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {100426#false} is VALID [2022-02-21 04:25:06,492 INFO L290 TraceCheckUtils]: 59: Hoare triple {100426#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {100426#false} is VALID [2022-02-21 04:25:06,493 INFO L290 TraceCheckUtils]: 60: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___0~0#1); {100426#false} is VALID [2022-02-21 04:25:06,493 INFO L290 TraceCheckUtils]: 61: Hoare triple {100426#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {100426#false} is VALID [2022-02-21 04:25:06,493 INFO L290 TraceCheckUtils]: 62: Hoare triple {100426#false} assume 1 == ~t2_pc~0; {100426#false} is VALID [2022-02-21 04:25:06,493 INFO L290 TraceCheckUtils]: 63: Hoare triple {100426#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {100426#false} is VALID [2022-02-21 04:25:06,493 INFO L290 TraceCheckUtils]: 64: Hoare triple {100426#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {100426#false} is VALID [2022-02-21 04:25:06,493 INFO L290 TraceCheckUtils]: 65: Hoare triple {100426#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {100426#false} is VALID [2022-02-21 04:25:06,493 INFO L290 TraceCheckUtils]: 66: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___1~0#1); {100426#false} is VALID [2022-02-21 04:25:06,493 INFO L290 TraceCheckUtils]: 67: Hoare triple {100426#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {100426#false} is VALID [2022-02-21 04:25:06,493 INFO L290 TraceCheckUtils]: 68: Hoare triple {100426#false} assume !(1 == ~t3_pc~0); {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 69: Hoare triple {100426#false} is_transmit3_triggered_~__retres1~3#1 := 0; {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 70: Hoare triple {100426#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 71: Hoare triple {100426#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 72: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___2~0#1); {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 73: Hoare triple {100426#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 74: Hoare triple {100426#false} assume 1 == ~t4_pc~0; {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 75: Hoare triple {100426#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 76: Hoare triple {100426#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 77: Hoare triple {100426#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {100426#false} is VALID [2022-02-21 04:25:06,494 INFO L290 TraceCheckUtils]: 78: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___3~0#1); {100426#false} is VALID [2022-02-21 04:25:06,495 INFO L290 TraceCheckUtils]: 79: Hoare triple {100426#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {100426#false} is VALID [2022-02-21 04:25:06,495 INFO L290 TraceCheckUtils]: 80: Hoare triple {100426#false} assume 1 == ~t5_pc~0; {100426#false} is VALID [2022-02-21 04:25:06,495 INFO L290 TraceCheckUtils]: 81: Hoare triple {100426#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {100426#false} is VALID [2022-02-21 04:25:06,495 INFO L290 TraceCheckUtils]: 82: Hoare triple {100426#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {100426#false} is VALID [2022-02-21 04:25:06,495 INFO L290 TraceCheckUtils]: 83: Hoare triple {100426#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {100426#false} is VALID [2022-02-21 04:25:06,495 INFO L290 TraceCheckUtils]: 84: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___4~0#1); {100426#false} is VALID [2022-02-21 04:25:06,495 INFO L290 TraceCheckUtils]: 85: Hoare triple {100426#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {100426#false} is VALID [2022-02-21 04:25:06,495 INFO L290 TraceCheckUtils]: 86: Hoare triple {100426#false} assume !(1 == ~t6_pc~0); {100426#false} is VALID [2022-02-21 04:25:06,495 INFO L290 TraceCheckUtils]: 87: Hoare triple {100426#false} is_transmit6_triggered_~__retres1~6#1 := 0; {100426#false} is VALID [2022-02-21 04:25:06,496 INFO L290 TraceCheckUtils]: 88: Hoare triple {100426#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {100426#false} is VALID [2022-02-21 04:25:06,496 INFO L290 TraceCheckUtils]: 89: Hoare triple {100426#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {100426#false} is VALID [2022-02-21 04:25:06,496 INFO L290 TraceCheckUtils]: 90: Hoare triple {100426#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {100426#false} is VALID [2022-02-21 04:25:06,496 INFO L290 TraceCheckUtils]: 91: Hoare triple {100426#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {100426#false} is VALID [2022-02-21 04:25:06,496 INFO L290 TraceCheckUtils]: 92: Hoare triple {100426#false} assume 1 == ~t7_pc~0; {100426#false} is VALID [2022-02-21 04:25:06,496 INFO L290 TraceCheckUtils]: 93: Hoare triple {100426#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {100426#false} is VALID [2022-02-21 04:25:06,496 INFO L290 TraceCheckUtils]: 94: Hoare triple {100426#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {100426#false} is VALID [2022-02-21 04:25:06,496 INFO L290 TraceCheckUtils]: 95: Hoare triple {100426#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {100426#false} is VALID [2022-02-21 04:25:06,496 INFO L290 TraceCheckUtils]: 96: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___6~0#1); {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 97: Hoare triple {100426#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 98: Hoare triple {100426#false} assume !(1 == ~t8_pc~0); {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 99: Hoare triple {100426#false} is_transmit8_triggered_~__retres1~8#1 := 0; {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 100: Hoare triple {100426#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 101: Hoare triple {100426#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 102: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___7~0#1); {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 103: Hoare triple {100426#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 104: Hoare triple {100426#false} assume 1 == ~t9_pc~0; {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 105: Hoare triple {100426#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {100426#false} is VALID [2022-02-21 04:25:06,497 INFO L290 TraceCheckUtils]: 106: Hoare triple {100426#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {100426#false} is VALID [2022-02-21 04:25:06,498 INFO L290 TraceCheckUtils]: 107: Hoare triple {100426#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {100426#false} is VALID [2022-02-21 04:25:06,498 INFO L290 TraceCheckUtils]: 108: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___8~0#1); {100426#false} is VALID [2022-02-21 04:25:06,498 INFO L290 TraceCheckUtils]: 109: Hoare triple {100426#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {100426#false} is VALID [2022-02-21 04:25:06,498 INFO L290 TraceCheckUtils]: 110: Hoare triple {100426#false} assume !(1 == ~t10_pc~0); {100426#false} is VALID [2022-02-21 04:25:06,498 INFO L290 TraceCheckUtils]: 111: Hoare triple {100426#false} is_transmit10_triggered_~__retres1~10#1 := 0; {100426#false} is VALID [2022-02-21 04:25:06,498 INFO L290 TraceCheckUtils]: 112: Hoare triple {100426#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {100426#false} is VALID [2022-02-21 04:25:06,498 INFO L290 TraceCheckUtils]: 113: Hoare triple {100426#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {100426#false} is VALID [2022-02-21 04:25:06,498 INFO L290 TraceCheckUtils]: 114: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___9~0#1); {100426#false} is VALID [2022-02-21 04:25:06,498 INFO L290 TraceCheckUtils]: 115: Hoare triple {100426#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {100426#false} is VALID [2022-02-21 04:25:06,499 INFO L290 TraceCheckUtils]: 116: Hoare triple {100426#false} assume 1 == ~t11_pc~0; {100426#false} is VALID [2022-02-21 04:25:06,499 INFO L290 TraceCheckUtils]: 117: Hoare triple {100426#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {100426#false} is VALID [2022-02-21 04:25:06,499 INFO L290 TraceCheckUtils]: 118: Hoare triple {100426#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {100426#false} is VALID [2022-02-21 04:25:06,499 INFO L290 TraceCheckUtils]: 119: Hoare triple {100426#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {100426#false} is VALID [2022-02-21 04:25:06,499 INFO L290 TraceCheckUtils]: 120: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___10~0#1); {100426#false} is VALID [2022-02-21 04:25:06,499 INFO L290 TraceCheckUtils]: 121: Hoare triple {100426#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {100426#false} is VALID [2022-02-21 04:25:06,499 INFO L290 TraceCheckUtils]: 122: Hoare triple {100426#false} assume !(1 == ~t12_pc~0); {100426#false} is VALID [2022-02-21 04:25:06,499 INFO L290 TraceCheckUtils]: 123: Hoare triple {100426#false} is_transmit12_triggered_~__retres1~12#1 := 0; {100426#false} is VALID [2022-02-21 04:25:06,499 INFO L290 TraceCheckUtils]: 124: Hoare triple {100426#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {100426#false} is VALID [2022-02-21 04:25:06,500 INFO L290 TraceCheckUtils]: 125: Hoare triple {100426#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {100426#false} is VALID [2022-02-21 04:25:06,500 INFO L290 TraceCheckUtils]: 126: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___11~0#1); {100426#false} is VALID [2022-02-21 04:25:06,500 INFO L290 TraceCheckUtils]: 127: Hoare triple {100426#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {100426#false} is VALID [2022-02-21 04:25:06,500 INFO L290 TraceCheckUtils]: 128: Hoare triple {100426#false} assume 1 == ~t13_pc~0; {100426#false} is VALID [2022-02-21 04:25:06,500 INFO L290 TraceCheckUtils]: 129: Hoare triple {100426#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {100426#false} is VALID [2022-02-21 04:25:06,500 INFO L290 TraceCheckUtils]: 130: Hoare triple {100426#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {100426#false} is VALID [2022-02-21 04:25:06,500 INFO L290 TraceCheckUtils]: 131: Hoare triple {100426#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {100426#false} is VALID [2022-02-21 04:25:06,500 INFO L290 TraceCheckUtils]: 132: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___12~0#1); {100426#false} is VALID [2022-02-21 04:25:06,500 INFO L290 TraceCheckUtils]: 133: Hoare triple {100426#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {100426#false} is VALID [2022-02-21 04:25:06,501 INFO L290 TraceCheckUtils]: 134: Hoare triple {100426#false} assume 1 == ~t14_pc~0; {100426#false} is VALID [2022-02-21 04:25:06,501 INFO L290 TraceCheckUtils]: 135: Hoare triple {100426#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {100426#false} is VALID [2022-02-21 04:25:06,501 INFO L290 TraceCheckUtils]: 136: Hoare triple {100426#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {100426#false} is VALID [2022-02-21 04:25:06,501 INFO L290 TraceCheckUtils]: 137: Hoare triple {100426#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {100426#false} is VALID [2022-02-21 04:25:06,501 INFO L290 TraceCheckUtils]: 138: Hoare triple {100426#false} assume !(0 != activate_threads_~tmp___13~0#1); {100426#false} is VALID [2022-02-21 04:25:06,501 INFO L290 TraceCheckUtils]: 139: Hoare triple {100426#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {100426#false} is VALID [2022-02-21 04:25:06,501 INFO L290 TraceCheckUtils]: 140: Hoare triple {100426#false} assume 1 == ~M_E~0;~M_E~0 := 2; {100426#false} is VALID [2022-02-21 04:25:06,501 INFO L290 TraceCheckUtils]: 141: Hoare triple {100426#false} assume !(1 == ~T1_E~0); {100426#false} is VALID [2022-02-21 04:25:06,501 INFO L290 TraceCheckUtils]: 142: Hoare triple {100426#false} assume !(1 == ~T2_E~0); {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 143: Hoare triple {100426#false} assume !(1 == ~T3_E~0); {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 144: Hoare triple {100426#false} assume !(1 == ~T4_E~0); {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 145: Hoare triple {100426#false} assume !(1 == ~T5_E~0); {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 146: Hoare triple {100426#false} assume !(1 == ~T6_E~0); {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 147: Hoare triple {100426#false} assume !(1 == ~T7_E~0); {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 148: Hoare triple {100426#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 149: Hoare triple {100426#false} assume !(1 == ~T9_E~0); {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 150: Hoare triple {100426#false} assume !(1 == ~T10_E~0); {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 151: Hoare triple {100426#false} assume !(1 == ~T11_E~0); {100426#false} is VALID [2022-02-21 04:25:06,502 INFO L290 TraceCheckUtils]: 152: Hoare triple {100426#false} assume !(1 == ~T12_E~0); {100426#false} is VALID [2022-02-21 04:25:06,503 INFO L290 TraceCheckUtils]: 153: Hoare triple {100426#false} assume !(1 == ~T13_E~0); {100426#false} is VALID [2022-02-21 04:25:06,503 INFO L290 TraceCheckUtils]: 154: Hoare triple {100426#false} assume !(1 == ~T14_E~0); {100426#false} is VALID [2022-02-21 04:25:06,503 INFO L290 TraceCheckUtils]: 155: Hoare triple {100426#false} assume !(1 == ~E_1~0); {100426#false} is VALID [2022-02-21 04:25:06,503 INFO L290 TraceCheckUtils]: 156: Hoare triple {100426#false} assume 1 == ~E_2~0;~E_2~0 := 2; {100426#false} is VALID [2022-02-21 04:25:06,503 INFO L290 TraceCheckUtils]: 157: Hoare triple {100426#false} assume !(1 == ~E_3~0); {100426#false} is VALID [2022-02-21 04:25:06,503 INFO L290 TraceCheckUtils]: 158: Hoare triple {100426#false} assume !(1 == ~E_4~0); {100426#false} is VALID [2022-02-21 04:25:06,503 INFO L290 TraceCheckUtils]: 159: Hoare triple {100426#false} assume !(1 == ~E_5~0); {100426#false} is VALID [2022-02-21 04:25:06,503 INFO L290 TraceCheckUtils]: 160: Hoare triple {100426#false} assume !(1 == ~E_6~0); {100426#false} is VALID [2022-02-21 04:25:06,503 INFO L290 TraceCheckUtils]: 161: Hoare triple {100426#false} assume !(1 == ~E_7~0); {100426#false} is VALID [2022-02-21 04:25:06,504 INFO L290 TraceCheckUtils]: 162: Hoare triple {100426#false} assume !(1 == ~E_8~0); {100426#false} is VALID [2022-02-21 04:25:06,504 INFO L290 TraceCheckUtils]: 163: Hoare triple {100426#false} assume !(1 == ~E_9~0); {100426#false} is VALID [2022-02-21 04:25:06,504 INFO L290 TraceCheckUtils]: 164: Hoare triple {100426#false} assume 1 == ~E_10~0;~E_10~0 := 2; {100426#false} is VALID [2022-02-21 04:25:06,504 INFO L290 TraceCheckUtils]: 165: Hoare triple {100426#false} assume !(1 == ~E_11~0); {100426#false} is VALID [2022-02-21 04:25:06,504 INFO L290 TraceCheckUtils]: 166: Hoare triple {100426#false} assume !(1 == ~E_12~0); {100426#false} is VALID [2022-02-21 04:25:06,504 INFO L290 TraceCheckUtils]: 167: Hoare triple {100426#false} assume !(1 == ~E_13~0); {100426#false} is VALID [2022-02-21 04:25:06,504 INFO L290 TraceCheckUtils]: 168: Hoare triple {100426#false} assume !(1 == ~E_14~0); {100426#false} is VALID [2022-02-21 04:25:06,504 INFO L290 TraceCheckUtils]: 169: Hoare triple {100426#false} assume { :end_inline_reset_delta_events } true; {100426#false} is VALID [2022-02-21 04:25:06,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:06,505 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:06,505 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521198907] [2022-02-21 04:25:06,505 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1521198907] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:06,505 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:06,505 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:06,505 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887569969] [2022-02-21 04:25:06,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:06,506 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:06,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:06,506 INFO L85 PathProgramCache]: Analyzing trace with hash -883259988, now seen corresponding path program 1 times [2022-02-21 04:25:06,506 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:06,506 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561754696] [2022-02-21 04:25:06,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:06,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:06,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:06,531 INFO L290 TraceCheckUtils]: 0: Hoare triple {100428#true} assume !false; {100428#true} is VALID [2022-02-21 04:25:06,531 INFO L290 TraceCheckUtils]: 1: Hoare triple {100428#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {100428#true} is VALID [2022-02-21 04:25:06,531 INFO L290 TraceCheckUtils]: 2: Hoare triple {100428#true} assume !false; {100428#true} is VALID [2022-02-21 04:25:06,531 INFO L290 TraceCheckUtils]: 3: Hoare triple {100428#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {100428#true} is VALID [2022-02-21 04:25:06,531 INFO L290 TraceCheckUtils]: 4: Hoare triple {100428#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {100428#true} is VALID [2022-02-21 04:25:06,531 INFO L290 TraceCheckUtils]: 5: Hoare triple {100428#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {100428#true} is VALID [2022-02-21 04:25:06,531 INFO L290 TraceCheckUtils]: 6: Hoare triple {100428#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {100428#true} is VALID [2022-02-21 04:25:06,532 INFO L290 TraceCheckUtils]: 7: Hoare triple {100428#true} assume !(0 != eval_~tmp~0#1); {100428#true} is VALID [2022-02-21 04:25:06,532 INFO L290 TraceCheckUtils]: 8: Hoare triple {100428#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {100428#true} is VALID [2022-02-21 04:25:06,532 INFO L290 TraceCheckUtils]: 9: Hoare triple {100428#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {100428#true} is VALID [2022-02-21 04:25:06,532 INFO L290 TraceCheckUtils]: 10: Hoare triple {100428#true} assume 0 == ~M_E~0;~M_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,532 INFO L290 TraceCheckUtils]: 11: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,533 INFO L290 TraceCheckUtils]: 12: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,533 INFO L290 TraceCheckUtils]: 13: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,533 INFO L290 TraceCheckUtils]: 14: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,533 INFO L290 TraceCheckUtils]: 15: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,534 INFO L290 TraceCheckUtils]: 16: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,534 INFO L290 TraceCheckUtils]: 17: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,534 INFO L290 TraceCheckUtils]: 18: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,535 INFO L290 TraceCheckUtils]: 19: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,535 INFO L290 TraceCheckUtils]: 20: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,535 INFO L290 TraceCheckUtils]: 21: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,535 INFO L290 TraceCheckUtils]: 22: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,536 INFO L290 TraceCheckUtils]: 23: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,536 INFO L290 TraceCheckUtils]: 24: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,536 INFO L290 TraceCheckUtils]: 25: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,536 INFO L290 TraceCheckUtils]: 26: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,537 INFO L290 TraceCheckUtils]: 27: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,537 INFO L290 TraceCheckUtils]: 28: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,537 INFO L290 TraceCheckUtils]: 29: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,538 INFO L290 TraceCheckUtils]: 30: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,538 INFO L290 TraceCheckUtils]: 31: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,538 INFO L290 TraceCheckUtils]: 32: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,538 INFO L290 TraceCheckUtils]: 33: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,539 INFO L290 TraceCheckUtils]: 34: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,539 INFO L290 TraceCheckUtils]: 35: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,539 INFO L290 TraceCheckUtils]: 36: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,539 INFO L290 TraceCheckUtils]: 37: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,540 INFO L290 TraceCheckUtils]: 38: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,540 INFO L290 TraceCheckUtils]: 39: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,540 INFO L290 TraceCheckUtils]: 40: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,541 INFO L290 TraceCheckUtils]: 41: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,541 INFO L290 TraceCheckUtils]: 42: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,541 INFO L290 TraceCheckUtils]: 43: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,541 INFO L290 TraceCheckUtils]: 44: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,542 INFO L290 TraceCheckUtils]: 45: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,542 INFO L290 TraceCheckUtils]: 46: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,542 INFO L290 TraceCheckUtils]: 47: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,542 INFO L290 TraceCheckUtils]: 48: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,543 INFO L290 TraceCheckUtils]: 49: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,543 INFO L290 TraceCheckUtils]: 50: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,543 INFO L290 TraceCheckUtils]: 51: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,544 INFO L290 TraceCheckUtils]: 52: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,544 INFO L290 TraceCheckUtils]: 53: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,544 INFO L290 TraceCheckUtils]: 54: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,544 INFO L290 TraceCheckUtils]: 55: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,545 INFO L290 TraceCheckUtils]: 56: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,545 INFO L290 TraceCheckUtils]: 57: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,545 INFO L290 TraceCheckUtils]: 58: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,545 INFO L290 TraceCheckUtils]: 59: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,546 INFO L290 TraceCheckUtils]: 60: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,546 INFO L290 TraceCheckUtils]: 61: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,546 INFO L290 TraceCheckUtils]: 62: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,546 INFO L290 TraceCheckUtils]: 63: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,547 INFO L290 TraceCheckUtils]: 64: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,547 INFO L290 TraceCheckUtils]: 65: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,547 INFO L290 TraceCheckUtils]: 66: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,548 INFO L290 TraceCheckUtils]: 67: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,548 INFO L290 TraceCheckUtils]: 68: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,548 INFO L290 TraceCheckUtils]: 69: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,548 INFO L290 TraceCheckUtils]: 70: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,549 INFO L290 TraceCheckUtils]: 71: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,549 INFO L290 TraceCheckUtils]: 72: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,549 INFO L290 TraceCheckUtils]: 73: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,549 INFO L290 TraceCheckUtils]: 74: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,550 INFO L290 TraceCheckUtils]: 75: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,550 INFO L290 TraceCheckUtils]: 76: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,550 INFO L290 TraceCheckUtils]: 77: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,550 INFO L290 TraceCheckUtils]: 78: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,551 INFO L290 TraceCheckUtils]: 79: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,551 INFO L290 TraceCheckUtils]: 80: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,551 INFO L290 TraceCheckUtils]: 81: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,551 INFO L290 TraceCheckUtils]: 82: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,552 INFO L290 TraceCheckUtils]: 83: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,552 INFO L290 TraceCheckUtils]: 84: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,552 INFO L290 TraceCheckUtils]: 85: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,552 INFO L290 TraceCheckUtils]: 86: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,553 INFO L290 TraceCheckUtils]: 87: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,553 INFO L290 TraceCheckUtils]: 88: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,553 INFO L290 TraceCheckUtils]: 89: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,553 INFO L290 TraceCheckUtils]: 90: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,554 INFO L290 TraceCheckUtils]: 91: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,554 INFO L290 TraceCheckUtils]: 92: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,554 INFO L290 TraceCheckUtils]: 93: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,554 INFO L290 TraceCheckUtils]: 94: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,555 INFO L290 TraceCheckUtils]: 95: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,555 INFO L290 TraceCheckUtils]: 96: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,555 INFO L290 TraceCheckUtils]: 97: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,556 INFO L290 TraceCheckUtils]: 98: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,556 INFO L290 TraceCheckUtils]: 99: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,556 INFO L290 TraceCheckUtils]: 100: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,556 INFO L290 TraceCheckUtils]: 101: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,557 INFO L290 TraceCheckUtils]: 102: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,557 INFO L290 TraceCheckUtils]: 103: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,557 INFO L290 TraceCheckUtils]: 104: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,557 INFO L290 TraceCheckUtils]: 105: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,558 INFO L290 TraceCheckUtils]: 106: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,558 INFO L290 TraceCheckUtils]: 107: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,558 INFO L290 TraceCheckUtils]: 108: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,558 INFO L290 TraceCheckUtils]: 109: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,559 INFO L290 TraceCheckUtils]: 110: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,559 INFO L290 TraceCheckUtils]: 111: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,559 INFO L290 TraceCheckUtils]: 112: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,559 INFO L290 TraceCheckUtils]: 113: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,560 INFO L290 TraceCheckUtils]: 114: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,560 INFO L290 TraceCheckUtils]: 115: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,560 INFO L290 TraceCheckUtils]: 116: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,560 INFO L290 TraceCheckUtils]: 117: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,561 INFO L290 TraceCheckUtils]: 118: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,561 INFO L290 TraceCheckUtils]: 119: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,561 INFO L290 TraceCheckUtils]: 120: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,562 INFO L290 TraceCheckUtils]: 121: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,562 INFO L290 TraceCheckUtils]: 122: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,562 INFO L290 TraceCheckUtils]: 123: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,562 INFO L290 TraceCheckUtils]: 124: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,563 INFO L290 TraceCheckUtils]: 125: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,563 INFO L290 TraceCheckUtils]: 126: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,563 INFO L290 TraceCheckUtils]: 127: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,563 INFO L290 TraceCheckUtils]: 128: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,564 INFO L290 TraceCheckUtils]: 129: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {100430#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:06,564 INFO L290 TraceCheckUtils]: 130: Hoare triple {100430#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {100429#false} is VALID [2022-02-21 04:25:06,564 INFO L290 TraceCheckUtils]: 131: Hoare triple {100429#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,564 INFO L290 TraceCheckUtils]: 132: Hoare triple {100429#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,564 INFO L290 TraceCheckUtils]: 133: Hoare triple {100429#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,564 INFO L290 TraceCheckUtils]: 134: Hoare triple {100429#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,564 INFO L290 TraceCheckUtils]: 135: Hoare triple {100429#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 136: Hoare triple {100429#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 137: Hoare triple {100429#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 138: Hoare triple {100429#false} assume !(1 == ~T8_E~0); {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 139: Hoare triple {100429#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 140: Hoare triple {100429#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 141: Hoare triple {100429#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 142: Hoare triple {100429#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 143: Hoare triple {100429#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 144: Hoare triple {100429#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,565 INFO L290 TraceCheckUtils]: 145: Hoare triple {100429#false} assume 1 == ~E_1~0;~E_1~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,566 INFO L290 TraceCheckUtils]: 146: Hoare triple {100429#false} assume !(1 == ~E_2~0); {100429#false} is VALID [2022-02-21 04:25:06,566 INFO L290 TraceCheckUtils]: 147: Hoare triple {100429#false} assume 1 == ~E_3~0;~E_3~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,566 INFO L290 TraceCheckUtils]: 148: Hoare triple {100429#false} assume 1 == ~E_4~0;~E_4~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,566 INFO L290 TraceCheckUtils]: 149: Hoare triple {100429#false} assume 1 == ~E_5~0;~E_5~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,566 INFO L290 TraceCheckUtils]: 150: Hoare triple {100429#false} assume 1 == ~E_6~0;~E_6~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,566 INFO L290 TraceCheckUtils]: 151: Hoare triple {100429#false} assume 1 == ~E_7~0;~E_7~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,566 INFO L290 TraceCheckUtils]: 152: Hoare triple {100429#false} assume 1 == ~E_8~0;~E_8~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,566 INFO L290 TraceCheckUtils]: 153: Hoare triple {100429#false} assume 1 == ~E_9~0;~E_9~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,566 INFO L290 TraceCheckUtils]: 154: Hoare triple {100429#false} assume !(1 == ~E_10~0); {100429#false} is VALID [2022-02-21 04:25:06,567 INFO L290 TraceCheckUtils]: 155: Hoare triple {100429#false} assume 1 == ~E_11~0;~E_11~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,567 INFO L290 TraceCheckUtils]: 156: Hoare triple {100429#false} assume 1 == ~E_12~0;~E_12~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,567 INFO L290 TraceCheckUtils]: 157: Hoare triple {100429#false} assume 1 == ~E_13~0;~E_13~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,567 INFO L290 TraceCheckUtils]: 158: Hoare triple {100429#false} assume 1 == ~E_14~0;~E_14~0 := 2; {100429#false} is VALID [2022-02-21 04:25:06,567 INFO L290 TraceCheckUtils]: 159: Hoare triple {100429#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {100429#false} is VALID [2022-02-21 04:25:06,567 INFO L290 TraceCheckUtils]: 160: Hoare triple {100429#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {100429#false} is VALID [2022-02-21 04:25:06,567 INFO L290 TraceCheckUtils]: 161: Hoare triple {100429#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {100429#false} is VALID [2022-02-21 04:25:06,567 INFO L290 TraceCheckUtils]: 162: Hoare triple {100429#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {100429#false} is VALID [2022-02-21 04:25:06,567 INFO L290 TraceCheckUtils]: 163: Hoare triple {100429#false} assume !(0 == start_simulation_~tmp~3#1); {100429#false} is VALID [2022-02-21 04:25:06,568 INFO L290 TraceCheckUtils]: 164: Hoare triple {100429#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {100429#false} is VALID [2022-02-21 04:25:06,568 INFO L290 TraceCheckUtils]: 165: Hoare triple {100429#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {100429#false} is VALID [2022-02-21 04:25:06,568 INFO L290 TraceCheckUtils]: 166: Hoare triple {100429#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {100429#false} is VALID [2022-02-21 04:25:06,568 INFO L290 TraceCheckUtils]: 167: Hoare triple {100429#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {100429#false} is VALID [2022-02-21 04:25:06,568 INFO L290 TraceCheckUtils]: 168: Hoare triple {100429#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {100429#false} is VALID [2022-02-21 04:25:06,568 INFO L290 TraceCheckUtils]: 169: Hoare triple {100429#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {100429#false} is VALID [2022-02-21 04:25:06,568 INFO L290 TraceCheckUtils]: 170: Hoare triple {100429#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {100429#false} is VALID [2022-02-21 04:25:06,568 INFO L290 TraceCheckUtils]: 171: Hoare triple {100429#false} assume !(0 != start_simulation_~tmp___0~1#1); {100429#false} is VALID [2022-02-21 04:25:06,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:06,569 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:06,569 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561754696] [2022-02-21 04:25:06,569 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561754696] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:06,569 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:06,569 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:06,569 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [208138912] [2022-02-21 04:25:06,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:06,570 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:06,570 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:06,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:25:06,570 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:25:06,571 INFO L87 Difference]: Start difference. First operand 2047 states and 3023 transitions. cyclomatic complexity: 977 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:07,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:07,805 INFO L93 Difference]: Finished difference Result 2047 states and 3022 transitions. [2022-02-21 04:25:07,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:25:07,805 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:07,872 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:07,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3022 transitions. [2022-02-21 04:25:07,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:08,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3022 transitions. [2022-02-21 04:25:08,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:25:08,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:25:08,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3022 transitions. [2022-02-21 04:25:08,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:08,053 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2022-02-21 04:25:08,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3022 transitions. [2022-02-21 04:25:08,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:25:08,070 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:08,072 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3022 transitions. Second operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:08,073 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3022 transitions. Second operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:08,075 INFO L87 Difference]: Start difference. First operand 2047 states and 3022 transitions. Second operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:08,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:08,159 INFO L93 Difference]: Finished difference Result 2047 states and 3022 transitions. [2022-02-21 04:25:08,160 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3022 transitions. [2022-02-21 04:25:08,161 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:08,162 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:08,164 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3022 transitions. [2022-02-21 04:25:08,165 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3022 transitions. [2022-02-21 04:25:08,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:08,250 INFO L93 Difference]: Finished difference Result 2047 states and 3022 transitions. [2022-02-21 04:25:08,250 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3022 transitions. [2022-02-21 04:25:08,252 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:08,252 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:08,252 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:08,253 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:08,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:08,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3022 transitions. [2022-02-21 04:25:08,339 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2022-02-21 04:25:08,339 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2022-02-21 04:25:08,339 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:25:08,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3022 transitions. [2022-02-21 04:25:08,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:08,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:08,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:08,344 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:08,344 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:08,344 INFO L791 eck$LassoCheckResult]: Stem: 103404#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 103405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 104007#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 103124#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103125#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 103370#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 103371#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 103098#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 103099#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104322#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 103674#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 103675#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 104192#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 103584#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 103585#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 103005#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 103006#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 103337#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 103535#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 102582#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102583#L1342 assume !(0 == ~M_E~0); 102748#L1342-2 assume !(0 == ~T1_E~0); 103304#L1347-1 assume !(0 == ~T2_E~0); 104305#L1352-1 assume !(0 == ~T3_E~0); 104101#L1357-1 assume !(0 == ~T4_E~0); 103329#L1362-1 assume !(0 == ~T5_E~0); 103330#L1367-1 assume !(0 == ~T6_E~0); 102927#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 102928#L1377-1 assume !(0 == ~T8_E~0); 103258#L1382-1 assume !(0 == ~T9_E~0); 103259#L1387-1 assume !(0 == ~T10_E~0); 103986#L1392-1 assume !(0 == ~T11_E~0); 103290#L1397-1 assume !(0 == ~T12_E~0); 103291#L1402-1 assume !(0 == ~T13_E~0); 102943#L1407-1 assume !(0 == ~T14_E~0); 102944#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 104222#L1417-1 assume !(0 == ~E_2~0); 104223#L1422-1 assume !(0 == ~E_3~0); 104464#L1427-1 assume !(0 == ~E_4~0); 103131#L1432-1 assume !(0 == ~E_5~0); 103132#L1437-1 assume !(0 == ~E_6~0); 104140#L1442-1 assume !(0 == ~E_7~0); 104141#L1447-1 assume !(0 == ~E_8~0); 103983#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 102718#L1457-1 assume !(0 == ~E_10~0); 102719#L1462-1 assume !(0 == ~E_11~0); 104175#L1467-1 assume !(0 == ~E_12~0); 104187#L1472-1 assume !(0 == ~E_13~0); 104188#L1477-1 assume !(0 == ~E_14~0); 103930#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102917#L646 assume 1 == ~m_pc~0; 102918#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 103594#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103609#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 103007#L1666 assume !(0 != activate_threads_~tmp~1#1); 103008#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104485#L665 assume !(1 == ~t1_pc~0); 103483#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 103484#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103016#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103017#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 103807#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103808#L684 assume 1 == ~t2_pc~0; 103925#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 103849#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103914#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 104309#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 104310#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104498#L703 assume !(1 == ~t3_pc~0); 103153#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 103154#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103800#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102552#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 102553#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103038#L722 assume 1 == ~t4_pc~0; 103776#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 103219#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103564#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 104124#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 103631#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102749#L741 assume 1 == ~t5_pc~0; 102750#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 103060#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103214#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 103215#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 103894#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103305#L760 assume !(1 == ~t6_pc~0); 103152#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 103151#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103009#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 103010#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 103731#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103732#L779 assume 1 == ~t7_pc~0; 102794#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 102640#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102641#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 103049#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 103072#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 103073#L798 assume !(1 == ~t8_pc~0); 104354#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 104277#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102796#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 102797#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 104487#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102617#L817 assume 1 == ~t9_pc~0; 102618#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103412#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103413#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 103935#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 103023#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103024#L836 assume !(1 == ~t10_pc~0); 103040#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 102971#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 102972#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 103220#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 103221#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 104287#L855 assume 1 == ~t11_pc~0; 103605#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 103606#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 104170#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 103979#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 103814#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 102913#L874 assume !(1 == ~t12_pc~0); 102914#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 103081#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 103082#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 103222#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 102590#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 102591#L893 assume 1 == ~t13_pc~0; 104421#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 102946#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 103257#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 104348#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 104356#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 104357#L912 assume 1 == ~t14_pc~0; 104147#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 104148#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 102916#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 102848#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 102849#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103624#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 104040#L1495-2 assume !(1 == ~T1_E~0); 104041#L1500-1 assume !(1 == ~T2_E~0); 103727#L1505-1 assume !(1 == ~T3_E~0); 103728#L1510-1 assume !(1 == ~T4_E~0); 103785#L1515-1 assume !(1 == ~T5_E~0); 103786#L1520-1 assume !(1 == ~T6_E~0); 104355#L1525-1 assume !(1 == ~T7_E~0); 104065#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103018#L1535-1 assume !(1 == ~T9_E~0); 103019#L1540-1 assume !(1 == ~T10_E~0); 102511#L1545-1 assume !(1 == ~T11_E~0); 102512#L1550-1 assume !(1 == ~T12_E~0); 102760#L1555-1 assume !(1 == ~T13_E~0); 102761#L1560-1 assume !(1 == ~T14_E~0); 103061#L1565-1 assume !(1 == ~E_1~0); 104474#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 103952#L1575-1 assume !(1 == ~E_3~0); 103331#L1580-1 assume !(1 == ~E_4~0); 103332#L1585-1 assume !(1 == ~E_5~0); 103802#L1590-1 assume !(1 == ~E_6~0); 103366#L1595-1 assume !(1 == ~E_7~0); 103367#L1600-1 assume !(1 == ~E_8~0); 103739#L1605-1 assume !(1 == ~E_9~0); 103740#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 104257#L1615-1 assume !(1 == ~E_11~0); 103196#L1620-1 assume !(1 == ~E_12~0); 103197#L1625-1 assume !(1 == ~E_13~0); 103984#L1630-1 assume !(1 == ~E_14~0); 103365#L1635-1 assume { :end_inline_reset_delta_events } true; 103306#L2017-2 [2022-02-21 04:25:08,345 INFO L793 eck$LassoCheckResult]: Loop: 103306#L2017-2 assume !false; 102586#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102587#L1316 assume !false; 103915#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 103977#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 102524#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 102666#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 102667#L1115 assume !(0 != eval_~tmp~0#1); 104000#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103421#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103422#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103604#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 104105#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 103774#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103775#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104337#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 104512#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 104507#L1372-3 assume !(0 == ~T7_E~0); 102568#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 102569#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 103238#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 103239#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 104150#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 104460#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 103718#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 102874#L1412-3 assume !(0 == ~E_1~0); 102875#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103639#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103640#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 104334#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 104021#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 103733#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103734#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 102634#L1452-3 assume !(0 == ~E_9~0); 102635#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 104273#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 104274#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 104078#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 104079#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 102872#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102873#L646-42 assume !(1 == ~m_pc~0); 103459#L646-44 is_master_triggered_~__retres1~0#1 := 0; 104306#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104307#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 104445#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 104446#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104238#L665-42 assume 1 == ~t1_pc~0; 104199#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 104201#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104387#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103041#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103042#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104511#L684-42 assume 1 == ~t2_pc~0; 103890#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 103891#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104501#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103670#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103671#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103793#L703-42 assume 1 == ~t3_pc~0; 103991#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 103992#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103310#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103311#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 104085#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103705#L722-42 assume !(1 == ~t4_pc~0); 103707#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 104116#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103359#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103186#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103187#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104481#L741-42 assume !(1 == ~t5_pc~0); 104098#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 103568#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103569#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 104514#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 103476#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103477#L760-42 assume !(1 == ~t6_pc~0); 103611#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 103746#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103747#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 104135#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 103428#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103429#L779-42 assume 1 == ~t7_pc~0; 104258#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 104206#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103115#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 103116#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 102969#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102970#L798-42 assume !(1 == ~t8_pc~0); 102580#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 102581#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 104324#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 103770#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 102800#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102801#L817-42 assume !(1 == ~t9_pc~0); 103577#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 103084#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103085#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 103211#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 104016#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 104017#L836-42 assume 1 == ~t10_pc~0; 104109#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 103122#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 103123#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 104424#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 104425#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 104466#L855-42 assume !(1 == ~t11_pc~0); 104480#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 102673#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 102674#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 103423#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 104186#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 103287#L874-42 assume !(1 == ~t12_pc~0); 103289#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 103530#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 102588#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 102589#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 102842#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 102843#L893-42 assume !(1 == ~t13_pc~0); 103826#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 103827#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 103842#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 103744#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 103216#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 103217#L912-42 assume !(1 == ~t14_pc~0); 104026#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 102534#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 102535#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 104115#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 102962#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102963#L1495-3 assume !(1 == ~M_E~0); 103578#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 104006#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 104099#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 103192#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103155#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 103156#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103813#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 104036#L1530-3 assume !(1 == ~T8_E~0); 103001#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 103002#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 103039#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 104296#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 104405#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 103445#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 103446#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 104061#L1570-3 assume !(1 == ~E_2~0); 104012#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 104013#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 104368#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 104413#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 104458#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 103835#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 103836#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 104311#L1610-3 assume !(1 == ~E_10~0); 103198#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 103199#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 103803#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 103804#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 103708#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 103139#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 102744#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 103482#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 104038#L2036 assume !(0 == start_simulation_~tmp~3#1); 104039#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 104191#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 103351#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 104369#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 103751#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 103752#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104472#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 104473#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 103306#L2017-2 [2022-02-21 04:25:08,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:08,345 INFO L85 PathProgramCache]: Analyzing trace with hash -1873442456, now seen corresponding path program 1 times [2022-02-21 04:25:08,345 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:08,345 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601855446] [2022-02-21 04:25:08,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:08,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:08,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:08,364 INFO L290 TraceCheckUtils]: 0: Hoare triple {108622#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {108622#true} is VALID [2022-02-21 04:25:08,367 INFO L290 TraceCheckUtils]: 1: Hoare triple {108622#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,368 INFO L290 TraceCheckUtils]: 2: Hoare triple {108624#(= ~t14_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,368 INFO L290 TraceCheckUtils]: 3: Hoare triple {108624#(= ~t14_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,368 INFO L290 TraceCheckUtils]: 4: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,368 INFO L290 TraceCheckUtils]: 5: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,369 INFO L290 TraceCheckUtils]: 6: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,369 INFO L290 TraceCheckUtils]: 7: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,369 INFO L290 TraceCheckUtils]: 8: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,369 INFO L290 TraceCheckUtils]: 9: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,369 INFO L290 TraceCheckUtils]: 10: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,370 INFO L290 TraceCheckUtils]: 11: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,370 INFO L290 TraceCheckUtils]: 12: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,370 INFO L290 TraceCheckUtils]: 13: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,370 INFO L290 TraceCheckUtils]: 14: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,371 INFO L290 TraceCheckUtils]: 15: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,371 INFO L290 TraceCheckUtils]: 16: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,371 INFO L290 TraceCheckUtils]: 17: Hoare triple {108624#(= ~t14_i~0 1)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {108624#(= ~t14_i~0 1)} is VALID [2022-02-21 04:25:08,371 INFO L290 TraceCheckUtils]: 18: Hoare triple {108624#(= ~t14_i~0 1)} assume !(1 == ~t14_i~0);~t14_st~0 := 2; {108623#false} is VALID [2022-02-21 04:25:08,372 INFO L290 TraceCheckUtils]: 19: Hoare triple {108623#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {108623#false} is VALID [2022-02-21 04:25:08,372 INFO L290 TraceCheckUtils]: 20: Hoare triple {108623#false} assume !(0 == ~M_E~0); {108623#false} is VALID [2022-02-21 04:25:08,372 INFO L290 TraceCheckUtils]: 21: Hoare triple {108623#false} assume !(0 == ~T1_E~0); {108623#false} is VALID [2022-02-21 04:25:08,372 INFO L290 TraceCheckUtils]: 22: Hoare triple {108623#false} assume !(0 == ~T2_E~0); {108623#false} is VALID [2022-02-21 04:25:08,372 INFO L290 TraceCheckUtils]: 23: Hoare triple {108623#false} assume !(0 == ~T3_E~0); {108623#false} is VALID [2022-02-21 04:25:08,372 INFO L290 TraceCheckUtils]: 24: Hoare triple {108623#false} assume !(0 == ~T4_E~0); {108623#false} is VALID [2022-02-21 04:25:08,372 INFO L290 TraceCheckUtils]: 25: Hoare triple {108623#false} assume !(0 == ~T5_E~0); {108623#false} is VALID [2022-02-21 04:25:08,372 INFO L290 TraceCheckUtils]: 26: Hoare triple {108623#false} assume !(0 == ~T6_E~0); {108623#false} is VALID [2022-02-21 04:25:08,372 INFO L290 TraceCheckUtils]: 27: Hoare triple {108623#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 28: Hoare triple {108623#false} assume !(0 == ~T8_E~0); {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 29: Hoare triple {108623#false} assume !(0 == ~T9_E~0); {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 30: Hoare triple {108623#false} assume !(0 == ~T10_E~0); {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 31: Hoare triple {108623#false} assume !(0 == ~T11_E~0); {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 32: Hoare triple {108623#false} assume !(0 == ~T12_E~0); {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 33: Hoare triple {108623#false} assume !(0 == ~T13_E~0); {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 34: Hoare triple {108623#false} assume !(0 == ~T14_E~0); {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 35: Hoare triple {108623#false} assume 0 == ~E_1~0;~E_1~0 := 1; {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 36: Hoare triple {108623#false} assume !(0 == ~E_2~0); {108623#false} is VALID [2022-02-21 04:25:08,373 INFO L290 TraceCheckUtils]: 37: Hoare triple {108623#false} assume !(0 == ~E_3~0); {108623#false} is VALID [2022-02-21 04:25:08,374 INFO L290 TraceCheckUtils]: 38: Hoare triple {108623#false} assume !(0 == ~E_4~0); {108623#false} is VALID [2022-02-21 04:25:08,374 INFO L290 TraceCheckUtils]: 39: Hoare triple {108623#false} assume !(0 == ~E_5~0); {108623#false} is VALID [2022-02-21 04:25:08,374 INFO L290 TraceCheckUtils]: 40: Hoare triple {108623#false} assume !(0 == ~E_6~0); {108623#false} is VALID [2022-02-21 04:25:08,374 INFO L290 TraceCheckUtils]: 41: Hoare triple {108623#false} assume !(0 == ~E_7~0); {108623#false} is VALID [2022-02-21 04:25:08,374 INFO L290 TraceCheckUtils]: 42: Hoare triple {108623#false} assume !(0 == ~E_8~0); {108623#false} is VALID [2022-02-21 04:25:08,374 INFO L290 TraceCheckUtils]: 43: Hoare triple {108623#false} assume 0 == ~E_9~0;~E_9~0 := 1; {108623#false} is VALID [2022-02-21 04:25:08,374 INFO L290 TraceCheckUtils]: 44: Hoare triple {108623#false} assume !(0 == ~E_10~0); {108623#false} is VALID [2022-02-21 04:25:08,374 INFO L290 TraceCheckUtils]: 45: Hoare triple {108623#false} assume !(0 == ~E_11~0); {108623#false} is VALID [2022-02-21 04:25:08,374 INFO L290 TraceCheckUtils]: 46: Hoare triple {108623#false} assume !(0 == ~E_12~0); {108623#false} is VALID [2022-02-21 04:25:08,375 INFO L290 TraceCheckUtils]: 47: Hoare triple {108623#false} assume !(0 == ~E_13~0); {108623#false} is VALID [2022-02-21 04:25:08,375 INFO L290 TraceCheckUtils]: 48: Hoare triple {108623#false} assume !(0 == ~E_14~0); {108623#false} is VALID [2022-02-21 04:25:08,375 INFO L290 TraceCheckUtils]: 49: Hoare triple {108623#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {108623#false} is VALID [2022-02-21 04:25:08,375 INFO L290 TraceCheckUtils]: 50: Hoare triple {108623#false} assume 1 == ~m_pc~0; {108623#false} is VALID [2022-02-21 04:25:08,375 INFO L290 TraceCheckUtils]: 51: Hoare triple {108623#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {108623#false} is VALID [2022-02-21 04:25:08,375 INFO L290 TraceCheckUtils]: 52: Hoare triple {108623#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {108623#false} is VALID [2022-02-21 04:25:08,375 INFO L290 TraceCheckUtils]: 53: Hoare triple {108623#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {108623#false} is VALID [2022-02-21 04:25:08,375 INFO L290 TraceCheckUtils]: 54: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp~1#1); {108623#false} is VALID [2022-02-21 04:25:08,375 INFO L290 TraceCheckUtils]: 55: Hoare triple {108623#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 56: Hoare triple {108623#false} assume !(1 == ~t1_pc~0); {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 57: Hoare triple {108623#false} is_transmit1_triggered_~__retres1~1#1 := 0; {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 58: Hoare triple {108623#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 59: Hoare triple {108623#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 60: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___0~0#1); {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 61: Hoare triple {108623#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 62: Hoare triple {108623#false} assume 1 == ~t2_pc~0; {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 63: Hoare triple {108623#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 64: Hoare triple {108623#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {108623#false} is VALID [2022-02-21 04:25:08,376 INFO L290 TraceCheckUtils]: 65: Hoare triple {108623#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 66: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___1~0#1); {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 67: Hoare triple {108623#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 68: Hoare triple {108623#false} assume !(1 == ~t3_pc~0); {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 69: Hoare triple {108623#false} is_transmit3_triggered_~__retres1~3#1 := 0; {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 70: Hoare triple {108623#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 71: Hoare triple {108623#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 72: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___2~0#1); {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 73: Hoare triple {108623#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 74: Hoare triple {108623#false} assume 1 == ~t4_pc~0; {108623#false} is VALID [2022-02-21 04:25:08,377 INFO L290 TraceCheckUtils]: 75: Hoare triple {108623#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {108623#false} is VALID [2022-02-21 04:25:08,378 INFO L290 TraceCheckUtils]: 76: Hoare triple {108623#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {108623#false} is VALID [2022-02-21 04:25:08,378 INFO L290 TraceCheckUtils]: 77: Hoare triple {108623#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {108623#false} is VALID [2022-02-21 04:25:08,378 INFO L290 TraceCheckUtils]: 78: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___3~0#1); {108623#false} is VALID [2022-02-21 04:25:08,378 INFO L290 TraceCheckUtils]: 79: Hoare triple {108623#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {108623#false} is VALID [2022-02-21 04:25:08,378 INFO L290 TraceCheckUtils]: 80: Hoare triple {108623#false} assume 1 == ~t5_pc~0; {108623#false} is VALID [2022-02-21 04:25:08,378 INFO L290 TraceCheckUtils]: 81: Hoare triple {108623#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {108623#false} is VALID [2022-02-21 04:25:08,378 INFO L290 TraceCheckUtils]: 82: Hoare triple {108623#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {108623#false} is VALID [2022-02-21 04:25:08,378 INFO L290 TraceCheckUtils]: 83: Hoare triple {108623#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {108623#false} is VALID [2022-02-21 04:25:08,378 INFO L290 TraceCheckUtils]: 84: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___4~0#1); {108623#false} is VALID [2022-02-21 04:25:08,379 INFO L290 TraceCheckUtils]: 85: Hoare triple {108623#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {108623#false} is VALID [2022-02-21 04:25:08,379 INFO L290 TraceCheckUtils]: 86: Hoare triple {108623#false} assume !(1 == ~t6_pc~0); {108623#false} is VALID [2022-02-21 04:25:08,379 INFO L290 TraceCheckUtils]: 87: Hoare triple {108623#false} is_transmit6_triggered_~__retres1~6#1 := 0; {108623#false} is VALID [2022-02-21 04:25:08,379 INFO L290 TraceCheckUtils]: 88: Hoare triple {108623#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {108623#false} is VALID [2022-02-21 04:25:08,379 INFO L290 TraceCheckUtils]: 89: Hoare triple {108623#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {108623#false} is VALID [2022-02-21 04:25:08,379 INFO L290 TraceCheckUtils]: 90: Hoare triple {108623#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {108623#false} is VALID [2022-02-21 04:25:08,379 INFO L290 TraceCheckUtils]: 91: Hoare triple {108623#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {108623#false} is VALID [2022-02-21 04:25:08,379 INFO L290 TraceCheckUtils]: 92: Hoare triple {108623#false} assume 1 == ~t7_pc~0; {108623#false} is VALID [2022-02-21 04:25:08,379 INFO L290 TraceCheckUtils]: 93: Hoare triple {108623#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 94: Hoare triple {108623#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 95: Hoare triple {108623#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 96: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___6~0#1); {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 97: Hoare triple {108623#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 98: Hoare triple {108623#false} assume !(1 == ~t8_pc~0); {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 99: Hoare triple {108623#false} is_transmit8_triggered_~__retres1~8#1 := 0; {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 100: Hoare triple {108623#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 101: Hoare triple {108623#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 102: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___7~0#1); {108623#false} is VALID [2022-02-21 04:25:08,380 INFO L290 TraceCheckUtils]: 103: Hoare triple {108623#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {108623#false} is VALID [2022-02-21 04:25:08,381 INFO L290 TraceCheckUtils]: 104: Hoare triple {108623#false} assume 1 == ~t9_pc~0; {108623#false} is VALID [2022-02-21 04:25:08,381 INFO L290 TraceCheckUtils]: 105: Hoare triple {108623#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {108623#false} is VALID [2022-02-21 04:25:08,381 INFO L290 TraceCheckUtils]: 106: Hoare triple {108623#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {108623#false} is VALID [2022-02-21 04:25:08,381 INFO L290 TraceCheckUtils]: 107: Hoare triple {108623#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {108623#false} is VALID [2022-02-21 04:25:08,381 INFO L290 TraceCheckUtils]: 108: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___8~0#1); {108623#false} is VALID [2022-02-21 04:25:08,381 INFO L290 TraceCheckUtils]: 109: Hoare triple {108623#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {108623#false} is VALID [2022-02-21 04:25:08,381 INFO L290 TraceCheckUtils]: 110: Hoare triple {108623#false} assume !(1 == ~t10_pc~0); {108623#false} is VALID [2022-02-21 04:25:08,381 INFO L290 TraceCheckUtils]: 111: Hoare triple {108623#false} is_transmit10_triggered_~__retres1~10#1 := 0; {108623#false} is VALID [2022-02-21 04:25:08,381 INFO L290 TraceCheckUtils]: 112: Hoare triple {108623#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 113: Hoare triple {108623#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 114: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___9~0#1); {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 115: Hoare triple {108623#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 116: Hoare triple {108623#false} assume 1 == ~t11_pc~0; {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 117: Hoare triple {108623#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 118: Hoare triple {108623#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 119: Hoare triple {108623#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 120: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___10~0#1); {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 121: Hoare triple {108623#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {108623#false} is VALID [2022-02-21 04:25:08,382 INFO L290 TraceCheckUtils]: 122: Hoare triple {108623#false} assume !(1 == ~t12_pc~0); {108623#false} is VALID [2022-02-21 04:25:08,383 INFO L290 TraceCheckUtils]: 123: Hoare triple {108623#false} is_transmit12_triggered_~__retres1~12#1 := 0; {108623#false} is VALID [2022-02-21 04:25:08,383 INFO L290 TraceCheckUtils]: 124: Hoare triple {108623#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {108623#false} is VALID [2022-02-21 04:25:08,383 INFO L290 TraceCheckUtils]: 125: Hoare triple {108623#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {108623#false} is VALID [2022-02-21 04:25:08,383 INFO L290 TraceCheckUtils]: 126: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___11~0#1); {108623#false} is VALID [2022-02-21 04:25:08,383 INFO L290 TraceCheckUtils]: 127: Hoare triple {108623#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {108623#false} is VALID [2022-02-21 04:25:08,383 INFO L290 TraceCheckUtils]: 128: Hoare triple {108623#false} assume 1 == ~t13_pc~0; {108623#false} is VALID [2022-02-21 04:25:08,383 INFO L290 TraceCheckUtils]: 129: Hoare triple {108623#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {108623#false} is VALID [2022-02-21 04:25:08,383 INFO L290 TraceCheckUtils]: 130: Hoare triple {108623#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {108623#false} is VALID [2022-02-21 04:25:08,383 INFO L290 TraceCheckUtils]: 131: Hoare triple {108623#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 132: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___12~0#1); {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 133: Hoare triple {108623#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 134: Hoare triple {108623#false} assume 1 == ~t14_pc~0; {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 135: Hoare triple {108623#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 136: Hoare triple {108623#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 137: Hoare triple {108623#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 138: Hoare triple {108623#false} assume !(0 != activate_threads_~tmp___13~0#1); {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 139: Hoare triple {108623#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 140: Hoare triple {108623#false} assume 1 == ~M_E~0;~M_E~0 := 2; {108623#false} is VALID [2022-02-21 04:25:08,384 INFO L290 TraceCheckUtils]: 141: Hoare triple {108623#false} assume !(1 == ~T1_E~0); {108623#false} is VALID [2022-02-21 04:25:08,385 INFO L290 TraceCheckUtils]: 142: Hoare triple {108623#false} assume !(1 == ~T2_E~0); {108623#false} is VALID [2022-02-21 04:25:08,385 INFO L290 TraceCheckUtils]: 143: Hoare triple {108623#false} assume !(1 == ~T3_E~0); {108623#false} is VALID [2022-02-21 04:25:08,385 INFO L290 TraceCheckUtils]: 144: Hoare triple {108623#false} assume !(1 == ~T4_E~0); {108623#false} is VALID [2022-02-21 04:25:08,385 INFO L290 TraceCheckUtils]: 145: Hoare triple {108623#false} assume !(1 == ~T5_E~0); {108623#false} is VALID [2022-02-21 04:25:08,385 INFO L290 TraceCheckUtils]: 146: Hoare triple {108623#false} assume !(1 == ~T6_E~0); {108623#false} is VALID [2022-02-21 04:25:08,385 INFO L290 TraceCheckUtils]: 147: Hoare triple {108623#false} assume !(1 == ~T7_E~0); {108623#false} is VALID [2022-02-21 04:25:08,385 INFO L290 TraceCheckUtils]: 148: Hoare triple {108623#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {108623#false} is VALID [2022-02-21 04:25:08,385 INFO L290 TraceCheckUtils]: 149: Hoare triple {108623#false} assume !(1 == ~T9_E~0); {108623#false} is VALID [2022-02-21 04:25:08,385 INFO L290 TraceCheckUtils]: 150: Hoare triple {108623#false} assume !(1 == ~T10_E~0); {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 151: Hoare triple {108623#false} assume !(1 == ~T11_E~0); {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 152: Hoare triple {108623#false} assume !(1 == ~T12_E~0); {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 153: Hoare triple {108623#false} assume !(1 == ~T13_E~0); {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 154: Hoare triple {108623#false} assume !(1 == ~T14_E~0); {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 155: Hoare triple {108623#false} assume !(1 == ~E_1~0); {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 156: Hoare triple {108623#false} assume 1 == ~E_2~0;~E_2~0 := 2; {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 157: Hoare triple {108623#false} assume !(1 == ~E_3~0); {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 158: Hoare triple {108623#false} assume !(1 == ~E_4~0); {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 159: Hoare triple {108623#false} assume !(1 == ~E_5~0); {108623#false} is VALID [2022-02-21 04:25:08,386 INFO L290 TraceCheckUtils]: 160: Hoare triple {108623#false} assume !(1 == ~E_6~0); {108623#false} is VALID [2022-02-21 04:25:08,387 INFO L290 TraceCheckUtils]: 161: Hoare triple {108623#false} assume !(1 == ~E_7~0); {108623#false} is VALID [2022-02-21 04:25:08,387 INFO L290 TraceCheckUtils]: 162: Hoare triple {108623#false} assume !(1 == ~E_8~0); {108623#false} is VALID [2022-02-21 04:25:08,387 INFO L290 TraceCheckUtils]: 163: Hoare triple {108623#false} assume !(1 == ~E_9~0); {108623#false} is VALID [2022-02-21 04:25:08,387 INFO L290 TraceCheckUtils]: 164: Hoare triple {108623#false} assume 1 == ~E_10~0;~E_10~0 := 2; {108623#false} is VALID [2022-02-21 04:25:08,387 INFO L290 TraceCheckUtils]: 165: Hoare triple {108623#false} assume !(1 == ~E_11~0); {108623#false} is VALID [2022-02-21 04:25:08,387 INFO L290 TraceCheckUtils]: 166: Hoare triple {108623#false} assume !(1 == ~E_12~0); {108623#false} is VALID [2022-02-21 04:25:08,387 INFO L290 TraceCheckUtils]: 167: Hoare triple {108623#false} assume !(1 == ~E_13~0); {108623#false} is VALID [2022-02-21 04:25:08,387 INFO L290 TraceCheckUtils]: 168: Hoare triple {108623#false} assume !(1 == ~E_14~0); {108623#false} is VALID [2022-02-21 04:25:08,387 INFO L290 TraceCheckUtils]: 169: Hoare triple {108623#false} assume { :end_inline_reset_delta_events } true; {108623#false} is VALID [2022-02-21 04:25:08,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:08,388 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:08,388 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601855446] [2022-02-21 04:25:08,388 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601855446] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:08,388 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:08,388 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:08,389 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882849235] [2022-02-21 04:25:08,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:08,389 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:08,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:08,389 INFO L85 PathProgramCache]: Analyzing trace with hash 1442536967, now seen corresponding path program 1 times [2022-02-21 04:25:08,389 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:08,390 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473681783] [2022-02-21 04:25:08,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:08,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:08,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:08,415 INFO L290 TraceCheckUtils]: 0: Hoare triple {108625#true} assume !false; {108625#true} is VALID [2022-02-21 04:25:08,415 INFO L290 TraceCheckUtils]: 1: Hoare triple {108625#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {108625#true} is VALID [2022-02-21 04:25:08,415 INFO L290 TraceCheckUtils]: 2: Hoare triple {108625#true} assume !false; {108625#true} is VALID [2022-02-21 04:25:08,415 INFO L290 TraceCheckUtils]: 3: Hoare triple {108625#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {108625#true} is VALID [2022-02-21 04:25:08,415 INFO L290 TraceCheckUtils]: 4: Hoare triple {108625#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {108625#true} is VALID [2022-02-21 04:25:08,415 INFO L290 TraceCheckUtils]: 5: Hoare triple {108625#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {108625#true} is VALID [2022-02-21 04:25:08,415 INFO L290 TraceCheckUtils]: 6: Hoare triple {108625#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {108625#true} is VALID [2022-02-21 04:25:08,415 INFO L290 TraceCheckUtils]: 7: Hoare triple {108625#true} assume !(0 != eval_~tmp~0#1); {108625#true} is VALID [2022-02-21 04:25:08,416 INFO L290 TraceCheckUtils]: 8: Hoare triple {108625#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {108625#true} is VALID [2022-02-21 04:25:08,416 INFO L290 TraceCheckUtils]: 9: Hoare triple {108625#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {108625#true} is VALID [2022-02-21 04:25:08,416 INFO L290 TraceCheckUtils]: 10: Hoare triple {108625#true} assume 0 == ~M_E~0;~M_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,416 INFO L290 TraceCheckUtils]: 11: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,416 INFO L290 TraceCheckUtils]: 12: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,417 INFO L290 TraceCheckUtils]: 13: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,417 INFO L290 TraceCheckUtils]: 14: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,417 INFO L290 TraceCheckUtils]: 15: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,417 INFO L290 TraceCheckUtils]: 16: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,418 INFO L290 TraceCheckUtils]: 17: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,418 INFO L290 TraceCheckUtils]: 18: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,418 INFO L290 TraceCheckUtils]: 19: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,418 INFO L290 TraceCheckUtils]: 20: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,419 INFO L290 TraceCheckUtils]: 21: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,419 INFO L290 TraceCheckUtils]: 22: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,419 INFO L290 TraceCheckUtils]: 23: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,419 INFO L290 TraceCheckUtils]: 24: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,420 INFO L290 TraceCheckUtils]: 25: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,420 INFO L290 TraceCheckUtils]: 26: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,420 INFO L290 TraceCheckUtils]: 27: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,420 INFO L290 TraceCheckUtils]: 28: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,421 INFO L290 TraceCheckUtils]: 29: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,421 INFO L290 TraceCheckUtils]: 30: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,421 INFO L290 TraceCheckUtils]: 31: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,421 INFO L290 TraceCheckUtils]: 32: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,422 INFO L290 TraceCheckUtils]: 33: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,422 INFO L290 TraceCheckUtils]: 34: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,422 INFO L290 TraceCheckUtils]: 35: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,422 INFO L290 TraceCheckUtils]: 36: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,423 INFO L290 TraceCheckUtils]: 37: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,423 INFO L290 TraceCheckUtils]: 38: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,423 INFO L290 TraceCheckUtils]: 39: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,423 INFO L290 TraceCheckUtils]: 40: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,424 INFO L290 TraceCheckUtils]: 41: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,424 INFO L290 TraceCheckUtils]: 42: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,424 INFO L290 TraceCheckUtils]: 43: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,424 INFO L290 TraceCheckUtils]: 44: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,425 INFO L290 TraceCheckUtils]: 45: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,425 INFO L290 TraceCheckUtils]: 46: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,425 INFO L290 TraceCheckUtils]: 47: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,425 INFO L290 TraceCheckUtils]: 48: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,426 INFO L290 TraceCheckUtils]: 49: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,426 INFO L290 TraceCheckUtils]: 50: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,426 INFO L290 TraceCheckUtils]: 51: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,426 INFO L290 TraceCheckUtils]: 52: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,427 INFO L290 TraceCheckUtils]: 53: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,427 INFO L290 TraceCheckUtils]: 54: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,427 INFO L290 TraceCheckUtils]: 55: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,427 INFO L290 TraceCheckUtils]: 56: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,428 INFO L290 TraceCheckUtils]: 57: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,428 INFO L290 TraceCheckUtils]: 58: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,428 INFO L290 TraceCheckUtils]: 59: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,428 INFO L290 TraceCheckUtils]: 60: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,429 INFO L290 TraceCheckUtils]: 61: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,429 INFO L290 TraceCheckUtils]: 62: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,429 INFO L290 TraceCheckUtils]: 63: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,429 INFO L290 TraceCheckUtils]: 64: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,430 INFO L290 TraceCheckUtils]: 65: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,430 INFO L290 TraceCheckUtils]: 66: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,430 INFO L290 TraceCheckUtils]: 67: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,430 INFO L290 TraceCheckUtils]: 68: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,431 INFO L290 TraceCheckUtils]: 69: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,431 INFO L290 TraceCheckUtils]: 70: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,431 INFO L290 TraceCheckUtils]: 71: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,431 INFO L290 TraceCheckUtils]: 72: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,432 INFO L290 TraceCheckUtils]: 73: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,432 INFO L290 TraceCheckUtils]: 74: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,432 INFO L290 TraceCheckUtils]: 75: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,432 INFO L290 TraceCheckUtils]: 76: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,433 INFO L290 TraceCheckUtils]: 77: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,433 INFO L290 TraceCheckUtils]: 78: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,433 INFO L290 TraceCheckUtils]: 79: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,433 INFO L290 TraceCheckUtils]: 80: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,434 INFO L290 TraceCheckUtils]: 81: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,434 INFO L290 TraceCheckUtils]: 82: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,434 INFO L290 TraceCheckUtils]: 83: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,434 INFO L290 TraceCheckUtils]: 84: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,435 INFO L290 TraceCheckUtils]: 85: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,435 INFO L290 TraceCheckUtils]: 86: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,435 INFO L290 TraceCheckUtils]: 87: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,435 INFO L290 TraceCheckUtils]: 88: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,436 INFO L290 TraceCheckUtils]: 89: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,436 INFO L290 TraceCheckUtils]: 90: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,436 INFO L290 TraceCheckUtils]: 91: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,436 INFO L290 TraceCheckUtils]: 92: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,437 INFO L290 TraceCheckUtils]: 93: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,437 INFO L290 TraceCheckUtils]: 94: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,437 INFO L290 TraceCheckUtils]: 95: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,437 INFO L290 TraceCheckUtils]: 96: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,438 INFO L290 TraceCheckUtils]: 97: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,438 INFO L290 TraceCheckUtils]: 98: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,438 INFO L290 TraceCheckUtils]: 99: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,438 INFO L290 TraceCheckUtils]: 100: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,438 INFO L290 TraceCheckUtils]: 101: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,439 INFO L290 TraceCheckUtils]: 102: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,439 INFO L290 TraceCheckUtils]: 103: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,439 INFO L290 TraceCheckUtils]: 104: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,439 INFO L290 TraceCheckUtils]: 105: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,440 INFO L290 TraceCheckUtils]: 106: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,440 INFO L290 TraceCheckUtils]: 107: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,440 INFO L290 TraceCheckUtils]: 108: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,440 INFO L290 TraceCheckUtils]: 109: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,441 INFO L290 TraceCheckUtils]: 110: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,441 INFO L290 TraceCheckUtils]: 111: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,441 INFO L290 TraceCheckUtils]: 112: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t12_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,441 INFO L290 TraceCheckUtils]: 113: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,442 INFO L290 TraceCheckUtils]: 114: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,442 INFO L290 TraceCheckUtils]: 115: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,442 INFO L290 TraceCheckUtils]: 116: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,442 INFO L290 TraceCheckUtils]: 117: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,443 INFO L290 TraceCheckUtils]: 118: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t13_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,443 INFO L290 TraceCheckUtils]: 119: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,443 INFO L290 TraceCheckUtils]: 120: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,443 INFO L290 TraceCheckUtils]: 121: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,444 INFO L290 TraceCheckUtils]: 122: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,444 INFO L290 TraceCheckUtils]: 123: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,444 INFO L290 TraceCheckUtils]: 124: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,444 INFO L290 TraceCheckUtils]: 125: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,445 INFO L290 TraceCheckUtils]: 126: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,445 INFO L290 TraceCheckUtils]: 127: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,445 INFO L290 TraceCheckUtils]: 128: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,445 INFO L290 TraceCheckUtils]: 129: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {108627#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 130: Hoare triple {108627#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {108626#false} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 131: Hoare triple {108626#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 132: Hoare triple {108626#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 133: Hoare triple {108626#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 134: Hoare triple {108626#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 135: Hoare triple {108626#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 136: Hoare triple {108626#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 137: Hoare triple {108626#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 138: Hoare triple {108626#false} assume !(1 == ~T8_E~0); {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 139: Hoare triple {108626#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 140: Hoare triple {108626#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 141: Hoare triple {108626#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 142: Hoare triple {108626#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 143: Hoare triple {108626#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 144: Hoare triple {108626#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 145: Hoare triple {108626#false} assume 1 == ~E_1~0;~E_1~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 146: Hoare triple {108626#false} assume !(1 == ~E_2~0); {108626#false} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 147: Hoare triple {108626#false} assume 1 == ~E_3~0;~E_3~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 148: Hoare triple {108626#false} assume 1 == ~E_4~0;~E_4~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 149: Hoare triple {108626#false} assume 1 == ~E_5~0;~E_5~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 150: Hoare triple {108626#false} assume 1 == ~E_6~0;~E_6~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 151: Hoare triple {108626#false} assume 1 == ~E_7~0;~E_7~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 152: Hoare triple {108626#false} assume 1 == ~E_8~0;~E_8~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 153: Hoare triple {108626#false} assume 1 == ~E_9~0;~E_9~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 154: Hoare triple {108626#false} assume !(1 == ~E_10~0); {108626#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 155: Hoare triple {108626#false} assume 1 == ~E_11~0;~E_11~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 156: Hoare triple {108626#false} assume 1 == ~E_12~0;~E_12~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 157: Hoare triple {108626#false} assume 1 == ~E_13~0;~E_13~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 158: Hoare triple {108626#false} assume 1 == ~E_14~0;~E_14~0 := 2; {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 159: Hoare triple {108626#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 160: Hoare triple {108626#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 161: Hoare triple {108626#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 162: Hoare triple {108626#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 163: Hoare triple {108626#false} assume !(0 == start_simulation_~tmp~3#1); {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 164: Hoare triple {108626#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 165: Hoare triple {108626#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {108626#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 166: Hoare triple {108626#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {108626#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 167: Hoare triple {108626#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {108626#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 168: Hoare triple {108626#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {108626#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 169: Hoare triple {108626#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {108626#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 170: Hoare triple {108626#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {108626#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 171: Hoare triple {108626#false} assume !(0 != start_simulation_~tmp___0~1#1); {108626#false} is VALID [2022-02-21 04:25:08,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:08,451 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:08,451 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [473681783] [2022-02-21 04:25:08,451 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [473681783] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:08,451 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:08,451 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:08,451 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849775834] [2022-02-21 04:25:08,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:08,452 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:08,452 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:08,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:25:08,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:25:08,453 INFO L87 Difference]: Start difference. First operand 2047 states and 3022 transitions. cyclomatic complexity: 976 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:09,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:09,326 INFO L93 Difference]: Finished difference Result 2047 states and 3021 transitions. [2022-02-21 04:25:09,326 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:25:09,326 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:09,393 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:09,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3021 transitions. [2022-02-21 04:25:09,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:09,587 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3021 transitions. [2022-02-21 04:25:09,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-02-21 04:25:09,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-02-21 04:25:09,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3021 transitions. [2022-02-21 04:25:09,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:09,590 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2022-02-21 04:25:09,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3021 transitions. [2022-02-21 04:25:09,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-02-21 04:25:09,606 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:09,608 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2047 states and 3021 transitions. Second operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:09,609 INFO L74 IsIncluded]: Start isIncluded. First operand 2047 states and 3021 transitions. Second operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:09,610 INFO L87 Difference]: Start difference. First operand 2047 states and 3021 transitions. Second operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:09,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:09,695 INFO L93 Difference]: Finished difference Result 2047 states and 3021 transitions. [2022-02-21 04:25:09,695 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3021 transitions. [2022-02-21 04:25:09,697 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:09,697 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:09,699 INFO L74 IsIncluded]: Start isIncluded. First operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3021 transitions. [2022-02-21 04:25:09,701 INFO L87 Difference]: Start difference. First operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2047 states and 3021 transitions. [2022-02-21 04:25:09,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:09,789 INFO L93 Difference]: Finished difference Result 2047 states and 3021 transitions. [2022-02-21 04:25:09,789 INFO L276 IsEmpty]: Start isEmpty. Operand 2047 states and 3021 transitions. [2022-02-21 04:25:09,791 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:09,791 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:09,791 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:09,791 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:09,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:09,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3021 transitions. [2022-02-21 04:25:09,885 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2022-02-21 04:25:09,885 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2022-02-21 04:25:09,885 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:25:09,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3021 transitions. [2022-02-21 04:25:09,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-02-21 04:25:09,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:09,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:09,890 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:09,891 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:09,891 INFO L791 eck$LassoCheckResult]: Stem: 111601#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 111602#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 112204#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111321#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111322#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 111567#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111568#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111295#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111296#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112519#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111871#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111872#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 112389#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 111781#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 111782#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 111202#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 111203#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 111534#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 111732#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 110779#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 110780#L1342 assume !(0 == ~M_E~0); 110945#L1342-2 assume !(0 == ~T1_E~0); 111501#L1347-1 assume !(0 == ~T2_E~0); 112502#L1352-1 assume !(0 == ~T3_E~0); 112298#L1357-1 assume !(0 == ~T4_E~0); 111526#L1362-1 assume !(0 == ~T5_E~0); 111527#L1367-1 assume !(0 == ~T6_E~0); 111124#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 111125#L1377-1 assume !(0 == ~T8_E~0); 111455#L1382-1 assume !(0 == ~T9_E~0); 111456#L1387-1 assume !(0 == ~T10_E~0); 112183#L1392-1 assume !(0 == ~T11_E~0); 111487#L1397-1 assume !(0 == ~T12_E~0); 111488#L1402-1 assume !(0 == ~T13_E~0); 111140#L1407-1 assume !(0 == ~T14_E~0); 111141#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 112419#L1417-1 assume !(0 == ~E_2~0); 112420#L1422-1 assume !(0 == ~E_3~0); 112661#L1427-1 assume !(0 == ~E_4~0); 111328#L1432-1 assume !(0 == ~E_5~0); 111329#L1437-1 assume !(0 == ~E_6~0); 112337#L1442-1 assume !(0 == ~E_7~0); 112338#L1447-1 assume !(0 == ~E_8~0); 112180#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 110915#L1457-1 assume !(0 == ~E_10~0); 110916#L1462-1 assume !(0 == ~E_11~0); 112372#L1467-1 assume !(0 == ~E_12~0); 112384#L1472-1 assume !(0 == ~E_13~0); 112385#L1477-1 assume !(0 == ~E_14~0); 112127#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111116#L646 assume 1 == ~m_pc~0; 111117#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 111791#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111806#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 111204#L1666 assume !(0 != activate_threads_~tmp~1#1); 111205#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112682#L665 assume !(1 == ~t1_pc~0); 111680#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111681#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111213#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 111214#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 112004#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112005#L684 assume 1 == ~t2_pc~0; 112122#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 112046#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112111#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112506#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 112507#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112695#L703 assume !(1 == ~t3_pc~0); 111350#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 111351#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111997#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 110749#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 110750#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111235#L722 assume 1 == ~t4_pc~0; 111973#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 111416#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111761#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 112321#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 111828#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110946#L741 assume 1 == ~t5_pc~0; 110947#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 111257#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111411#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 111412#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 112091#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 111502#L760 assume !(1 == ~t6_pc~0); 111349#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 111348#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111206#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111207#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 111928#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 111929#L779 assume 1 == ~t7_pc~0; 110991#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 110837#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 110838#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111246#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 111269#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 111270#L798 assume !(1 == ~t8_pc~0); 112551#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 112474#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 110993#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 110994#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 112684#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 110814#L817 assume 1 == ~t9_pc~0; 110815#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 111609#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111610#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112132#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 111220#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111221#L836 assume !(1 == ~t10_pc~0); 111237#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 111168#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111169#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111417#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 111418#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112484#L855 assume 1 == ~t11_pc~0; 111802#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 111803#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112367#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 112176#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 112011#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 111110#L874 assume !(1 == ~t12_pc~0); 111111#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 111278#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 111279#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 111419#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 110787#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 110788#L893 assume 1 == ~t13_pc~0; 112618#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111143#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 111454#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 112545#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 112553#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 112554#L912 assume 1 == ~t14_pc~0; 112344#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 112345#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 111113#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 111045#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 111046#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111821#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 112237#L1495-2 assume !(1 == ~T1_E~0); 112238#L1500-1 assume !(1 == ~T2_E~0); 111924#L1505-1 assume !(1 == ~T3_E~0); 111925#L1510-1 assume !(1 == ~T4_E~0); 111982#L1515-1 assume !(1 == ~T5_E~0); 111983#L1520-1 assume !(1 == ~T6_E~0); 112552#L1525-1 assume !(1 == ~T7_E~0); 112262#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 111215#L1535-1 assume !(1 == ~T9_E~0); 111216#L1540-1 assume !(1 == ~T10_E~0); 110708#L1545-1 assume !(1 == ~T11_E~0); 110709#L1550-1 assume !(1 == ~T12_E~0); 110957#L1555-1 assume !(1 == ~T13_E~0); 110958#L1560-1 assume !(1 == ~T14_E~0); 111258#L1565-1 assume !(1 == ~E_1~0); 112671#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 112149#L1575-1 assume !(1 == ~E_3~0); 111528#L1580-1 assume !(1 == ~E_4~0); 111529#L1585-1 assume !(1 == ~E_5~0); 111999#L1590-1 assume !(1 == ~E_6~0); 111563#L1595-1 assume !(1 == ~E_7~0); 111564#L1600-1 assume !(1 == ~E_8~0); 111936#L1605-1 assume !(1 == ~E_9~0); 111937#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 112454#L1615-1 assume !(1 == ~E_11~0); 111393#L1620-1 assume !(1 == ~E_12~0); 111394#L1625-1 assume !(1 == ~E_13~0); 112181#L1630-1 assume !(1 == ~E_14~0); 111562#L1635-1 assume { :end_inline_reset_delta_events } true; 111503#L2017-2 [2022-02-21 04:25:09,891 INFO L793 eck$LassoCheckResult]: Loop: 111503#L2017-2 assume !false; 110783#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 110784#L1316 assume !false; 112112#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 112174#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 110721#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 110863#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 110864#L1115 assume !(0 != eval_~tmp~0#1); 112197#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 111618#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 111619#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 111801#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 112302#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 111971#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 111972#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 112534#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 112709#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 112704#L1372-3 assume !(0 == ~T7_E~0); 110765#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 110766#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 111435#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 111436#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 112347#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 112657#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 111915#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 111071#L1412-3 assume !(0 == ~E_1~0); 111072#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 111836#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 111837#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 112531#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 112218#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 111930#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 111931#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 110831#L1452-3 assume !(0 == ~E_9~0); 110832#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 112470#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 112471#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 112275#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 112276#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 111069#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111070#L646-42 assume 1 == ~m_pc~0; 111655#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 112503#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112504#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 112642#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 112643#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112435#L665-42 assume !(1 == ~t1_pc~0); 112397#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 112398#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112584#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 111238#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 111239#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112708#L684-42 assume 1 == ~t2_pc~0; 112087#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 112088#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112698#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 111867#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 111868#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111990#L703-42 assume 1 == ~t3_pc~0; 112188#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 112189#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111507#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 111508#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112282#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111902#L722-42 assume !(1 == ~t4_pc~0); 111904#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 112313#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111556#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 111383#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 111384#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112678#L741-42 assume !(1 == ~t5_pc~0); 112295#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 111765#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111766#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 112711#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 111673#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 111674#L760-42 assume 1 == ~t6_pc~0; 111809#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111943#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111944#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112332#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 111625#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 111626#L779-42 assume !(1 == ~t7_pc~0); 112402#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 112403#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 111312#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111313#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 111166#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 111167#L798-42 assume 1 == ~t8_pc~0; 111617#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 110778#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112521#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 111967#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 110997#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 110998#L817-42 assume 1 == ~t9_pc~0; 111773#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 111281#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111282#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 111408#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 112213#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 112214#L836-42 assume !(1 == ~t10_pc~0); 112307#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 111319#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111320#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 112621#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 112622#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112663#L855-42 assume !(1 == ~t11_pc~0); 112677#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 110870#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 110871#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111620#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 112383#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 111484#L874-42 assume 1 == ~t12_pc~0; 111485#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 111727#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110785#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 110786#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 111039#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 111040#L893-42 assume 1 == ~t13_pc~0; 112243#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 112024#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 112039#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 111941#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 111413#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 111414#L912-42 assume 1 == ~t14_pc~0; 112658#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 110731#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 110732#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 112312#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 111159#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111160#L1495-3 assume !(1 == ~M_E~0); 111775#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 112203#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112296#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111389#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111352#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 111353#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 112010#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 112233#L1530-3 assume !(1 == ~T8_E~0); 111198#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 111199#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 111236#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 112493#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 112602#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 111642#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 111643#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 112258#L1570-3 assume !(1 == ~E_2~0); 112209#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112210#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 112565#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 112610#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 112655#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 112032#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 112033#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 112508#L1610-3 assume !(1 == ~E_10~0); 111395#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 111396#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 112000#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 112001#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 111905#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 111336#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 110941#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 111679#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 112235#L2036 assume !(0 == start_simulation_~tmp~3#1); 112236#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 112388#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 111548#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 112566#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 111948#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 111949#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112669#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 112670#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 111503#L2017-2 [2022-02-21 04:25:09,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:09,892 INFO L85 PathProgramCache]: Analyzing trace with hash 527190954, now seen corresponding path program 1 times [2022-02-21 04:25:09,892 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:09,892 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82261061] [2022-02-21 04:25:09,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:09,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:09,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:09,920 INFO L290 TraceCheckUtils]: 0: Hoare triple {116819#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,921 INFO L290 TraceCheckUtils]: 1: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,921 INFO L290 TraceCheckUtils]: 2: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,921 INFO L290 TraceCheckUtils]: 3: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,921 INFO L290 TraceCheckUtils]: 4: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,922 INFO L290 TraceCheckUtils]: 5: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,922 INFO L290 TraceCheckUtils]: 6: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,922 INFO L290 TraceCheckUtils]: 7: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,922 INFO L290 TraceCheckUtils]: 8: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,923 INFO L290 TraceCheckUtils]: 9: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,923 INFO L290 TraceCheckUtils]: 10: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,923 INFO L290 TraceCheckUtils]: 11: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,923 INFO L290 TraceCheckUtils]: 12: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,924 INFO L290 TraceCheckUtils]: 13: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,924 INFO L290 TraceCheckUtils]: 14: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,924 INFO L290 TraceCheckUtils]: 15: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,924 INFO L290 TraceCheckUtils]: 16: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,925 INFO L290 TraceCheckUtils]: 17: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,925 INFO L290 TraceCheckUtils]: 18: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume 1 == ~t14_i~0;~t14_st~0 := 0; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,925 INFO L290 TraceCheckUtils]: 19: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,925 INFO L290 TraceCheckUtils]: 20: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume !(0 == ~M_E~0); {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,926 INFO L290 TraceCheckUtils]: 21: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume !(0 == ~T1_E~0); {116821#(= ~T2_E~0 ~T7_E~0)} is VALID [2022-02-21 04:25:09,926 INFO L290 TraceCheckUtils]: 22: Hoare triple {116821#(= ~T2_E~0 ~T7_E~0)} assume !(0 == ~T2_E~0); {116822#(not (= ~T7_E~0 0))} is VALID [2022-02-21 04:25:09,926 INFO L290 TraceCheckUtils]: 23: Hoare triple {116822#(not (= ~T7_E~0 0))} assume !(0 == ~T3_E~0); {116822#(not (= ~T7_E~0 0))} is VALID [2022-02-21 04:25:09,927 INFO L290 TraceCheckUtils]: 24: Hoare triple {116822#(not (= ~T7_E~0 0))} assume !(0 == ~T4_E~0); {116822#(not (= ~T7_E~0 0))} is VALID [2022-02-21 04:25:09,927 INFO L290 TraceCheckUtils]: 25: Hoare triple {116822#(not (= ~T7_E~0 0))} assume !(0 == ~T5_E~0); {116822#(not (= ~T7_E~0 0))} is VALID [2022-02-21 04:25:09,927 INFO L290 TraceCheckUtils]: 26: Hoare triple {116822#(not (= ~T7_E~0 0))} assume !(0 == ~T6_E~0); {116822#(not (= ~T7_E~0 0))} is VALID [2022-02-21 04:25:09,927 INFO L290 TraceCheckUtils]: 27: Hoare triple {116822#(not (= ~T7_E~0 0))} assume 0 == ~T7_E~0;~T7_E~0 := 1; {116820#false} is VALID [2022-02-21 04:25:09,927 INFO L290 TraceCheckUtils]: 28: Hoare triple {116820#false} assume !(0 == ~T8_E~0); {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 29: Hoare triple {116820#false} assume !(0 == ~T9_E~0); {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 30: Hoare triple {116820#false} assume !(0 == ~T10_E~0); {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 31: Hoare triple {116820#false} assume !(0 == ~T11_E~0); {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 32: Hoare triple {116820#false} assume !(0 == ~T12_E~0); {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 33: Hoare triple {116820#false} assume !(0 == ~T13_E~0); {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 34: Hoare triple {116820#false} assume !(0 == ~T14_E~0); {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 35: Hoare triple {116820#false} assume 0 == ~E_1~0;~E_1~0 := 1; {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 36: Hoare triple {116820#false} assume !(0 == ~E_2~0); {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 37: Hoare triple {116820#false} assume !(0 == ~E_3~0); {116820#false} is VALID [2022-02-21 04:25:09,928 INFO L290 TraceCheckUtils]: 38: Hoare triple {116820#false} assume !(0 == ~E_4~0); {116820#false} is VALID [2022-02-21 04:25:09,929 INFO L290 TraceCheckUtils]: 39: Hoare triple {116820#false} assume !(0 == ~E_5~0); {116820#false} is VALID [2022-02-21 04:25:09,929 INFO L290 TraceCheckUtils]: 40: Hoare triple {116820#false} assume !(0 == ~E_6~0); {116820#false} is VALID [2022-02-21 04:25:09,929 INFO L290 TraceCheckUtils]: 41: Hoare triple {116820#false} assume !(0 == ~E_7~0); {116820#false} is VALID [2022-02-21 04:25:09,929 INFO L290 TraceCheckUtils]: 42: Hoare triple {116820#false} assume !(0 == ~E_8~0); {116820#false} is VALID [2022-02-21 04:25:09,929 INFO L290 TraceCheckUtils]: 43: Hoare triple {116820#false} assume 0 == ~E_9~0;~E_9~0 := 1; {116820#false} is VALID [2022-02-21 04:25:09,929 INFO L290 TraceCheckUtils]: 44: Hoare triple {116820#false} assume !(0 == ~E_10~0); {116820#false} is VALID [2022-02-21 04:25:09,929 INFO L290 TraceCheckUtils]: 45: Hoare triple {116820#false} assume !(0 == ~E_11~0); {116820#false} is VALID [2022-02-21 04:25:09,929 INFO L290 TraceCheckUtils]: 46: Hoare triple {116820#false} assume !(0 == ~E_12~0); {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 47: Hoare triple {116820#false} assume !(0 == ~E_13~0); {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 48: Hoare triple {116820#false} assume !(0 == ~E_14~0); {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 49: Hoare triple {116820#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 50: Hoare triple {116820#false} assume 1 == ~m_pc~0; {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 51: Hoare triple {116820#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 52: Hoare triple {116820#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 53: Hoare triple {116820#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 54: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp~1#1); {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 55: Hoare triple {116820#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {116820#false} is VALID [2022-02-21 04:25:09,930 INFO L290 TraceCheckUtils]: 56: Hoare triple {116820#false} assume !(1 == ~t1_pc~0); {116820#false} is VALID [2022-02-21 04:25:09,931 INFO L290 TraceCheckUtils]: 57: Hoare triple {116820#false} is_transmit1_triggered_~__retres1~1#1 := 0; {116820#false} is VALID [2022-02-21 04:25:09,931 INFO L290 TraceCheckUtils]: 58: Hoare triple {116820#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {116820#false} is VALID [2022-02-21 04:25:09,931 INFO L290 TraceCheckUtils]: 59: Hoare triple {116820#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {116820#false} is VALID [2022-02-21 04:25:09,931 INFO L290 TraceCheckUtils]: 60: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___0~0#1); {116820#false} is VALID [2022-02-21 04:25:09,931 INFO L290 TraceCheckUtils]: 61: Hoare triple {116820#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {116820#false} is VALID [2022-02-21 04:25:09,931 INFO L290 TraceCheckUtils]: 62: Hoare triple {116820#false} assume 1 == ~t2_pc~0; {116820#false} is VALID [2022-02-21 04:25:09,931 INFO L290 TraceCheckUtils]: 63: Hoare triple {116820#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {116820#false} is VALID [2022-02-21 04:25:09,931 INFO L290 TraceCheckUtils]: 64: Hoare triple {116820#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {116820#false} is VALID [2022-02-21 04:25:09,931 INFO L290 TraceCheckUtils]: 65: Hoare triple {116820#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {116820#false} is VALID [2022-02-21 04:25:09,932 INFO L290 TraceCheckUtils]: 66: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___1~0#1); {116820#false} is VALID [2022-02-21 04:25:09,932 INFO L290 TraceCheckUtils]: 67: Hoare triple {116820#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {116820#false} is VALID [2022-02-21 04:25:09,932 INFO L290 TraceCheckUtils]: 68: Hoare triple {116820#false} assume !(1 == ~t3_pc~0); {116820#false} is VALID [2022-02-21 04:25:09,932 INFO L290 TraceCheckUtils]: 69: Hoare triple {116820#false} is_transmit3_triggered_~__retres1~3#1 := 0; {116820#false} is VALID [2022-02-21 04:25:09,932 INFO L290 TraceCheckUtils]: 70: Hoare triple {116820#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {116820#false} is VALID [2022-02-21 04:25:09,932 INFO L290 TraceCheckUtils]: 71: Hoare triple {116820#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {116820#false} is VALID [2022-02-21 04:25:09,932 INFO L290 TraceCheckUtils]: 72: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___2~0#1); {116820#false} is VALID [2022-02-21 04:25:09,932 INFO L290 TraceCheckUtils]: 73: Hoare triple {116820#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {116820#false} is VALID [2022-02-21 04:25:09,932 INFO L290 TraceCheckUtils]: 74: Hoare triple {116820#false} assume 1 == ~t4_pc~0; {116820#false} is VALID [2022-02-21 04:25:09,933 INFO L290 TraceCheckUtils]: 75: Hoare triple {116820#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {116820#false} is VALID [2022-02-21 04:25:09,933 INFO L290 TraceCheckUtils]: 76: Hoare triple {116820#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {116820#false} is VALID [2022-02-21 04:25:09,933 INFO L290 TraceCheckUtils]: 77: Hoare triple {116820#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {116820#false} is VALID [2022-02-21 04:25:09,933 INFO L290 TraceCheckUtils]: 78: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___3~0#1); {116820#false} is VALID [2022-02-21 04:25:09,933 INFO L290 TraceCheckUtils]: 79: Hoare triple {116820#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {116820#false} is VALID [2022-02-21 04:25:09,933 INFO L290 TraceCheckUtils]: 80: Hoare triple {116820#false} assume 1 == ~t5_pc~0; {116820#false} is VALID [2022-02-21 04:25:09,933 INFO L290 TraceCheckUtils]: 81: Hoare triple {116820#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {116820#false} is VALID [2022-02-21 04:25:09,933 INFO L290 TraceCheckUtils]: 82: Hoare triple {116820#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {116820#false} is VALID [2022-02-21 04:25:09,933 INFO L290 TraceCheckUtils]: 83: Hoare triple {116820#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 84: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___4~0#1); {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 85: Hoare triple {116820#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 86: Hoare triple {116820#false} assume !(1 == ~t6_pc~0); {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 87: Hoare triple {116820#false} is_transmit6_triggered_~__retres1~6#1 := 0; {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 88: Hoare triple {116820#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 89: Hoare triple {116820#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 90: Hoare triple {116820#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 91: Hoare triple {116820#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 92: Hoare triple {116820#false} assume 1 == ~t7_pc~0; {116820#false} is VALID [2022-02-21 04:25:09,934 INFO L290 TraceCheckUtils]: 93: Hoare triple {116820#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {116820#false} is VALID [2022-02-21 04:25:09,935 INFO L290 TraceCheckUtils]: 94: Hoare triple {116820#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {116820#false} is VALID [2022-02-21 04:25:09,935 INFO L290 TraceCheckUtils]: 95: Hoare triple {116820#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {116820#false} is VALID [2022-02-21 04:25:09,935 INFO L290 TraceCheckUtils]: 96: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___6~0#1); {116820#false} is VALID [2022-02-21 04:25:09,935 INFO L290 TraceCheckUtils]: 97: Hoare triple {116820#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {116820#false} is VALID [2022-02-21 04:25:09,935 INFO L290 TraceCheckUtils]: 98: Hoare triple {116820#false} assume !(1 == ~t8_pc~0); {116820#false} is VALID [2022-02-21 04:25:09,935 INFO L290 TraceCheckUtils]: 99: Hoare triple {116820#false} is_transmit8_triggered_~__retres1~8#1 := 0; {116820#false} is VALID [2022-02-21 04:25:09,935 INFO L290 TraceCheckUtils]: 100: Hoare triple {116820#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {116820#false} is VALID [2022-02-21 04:25:09,935 INFO L290 TraceCheckUtils]: 101: Hoare triple {116820#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {116820#false} is VALID [2022-02-21 04:25:09,935 INFO L290 TraceCheckUtils]: 102: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___7~0#1); {116820#false} is VALID [2022-02-21 04:25:09,936 INFO L290 TraceCheckUtils]: 103: Hoare triple {116820#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {116820#false} is VALID [2022-02-21 04:25:09,936 INFO L290 TraceCheckUtils]: 104: Hoare triple {116820#false} assume 1 == ~t9_pc~0; {116820#false} is VALID [2022-02-21 04:25:09,936 INFO L290 TraceCheckUtils]: 105: Hoare triple {116820#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {116820#false} is VALID [2022-02-21 04:25:09,936 INFO L290 TraceCheckUtils]: 106: Hoare triple {116820#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {116820#false} is VALID [2022-02-21 04:25:09,936 INFO L290 TraceCheckUtils]: 107: Hoare triple {116820#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {116820#false} is VALID [2022-02-21 04:25:09,936 INFO L290 TraceCheckUtils]: 108: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___8~0#1); {116820#false} is VALID [2022-02-21 04:25:09,936 INFO L290 TraceCheckUtils]: 109: Hoare triple {116820#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {116820#false} is VALID [2022-02-21 04:25:09,936 INFO L290 TraceCheckUtils]: 110: Hoare triple {116820#false} assume !(1 == ~t10_pc~0); {116820#false} is VALID [2022-02-21 04:25:09,936 INFO L290 TraceCheckUtils]: 111: Hoare triple {116820#false} is_transmit10_triggered_~__retres1~10#1 := 0; {116820#false} is VALID [2022-02-21 04:25:09,937 INFO L290 TraceCheckUtils]: 112: Hoare triple {116820#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {116820#false} is VALID [2022-02-21 04:25:09,937 INFO L290 TraceCheckUtils]: 113: Hoare triple {116820#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {116820#false} is VALID [2022-02-21 04:25:09,937 INFO L290 TraceCheckUtils]: 114: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___9~0#1); {116820#false} is VALID [2022-02-21 04:25:09,937 INFO L290 TraceCheckUtils]: 115: Hoare triple {116820#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {116820#false} is VALID [2022-02-21 04:25:09,937 INFO L290 TraceCheckUtils]: 116: Hoare triple {116820#false} assume 1 == ~t11_pc~0; {116820#false} is VALID [2022-02-21 04:25:09,937 INFO L290 TraceCheckUtils]: 117: Hoare triple {116820#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {116820#false} is VALID [2022-02-21 04:25:09,937 INFO L290 TraceCheckUtils]: 118: Hoare triple {116820#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {116820#false} is VALID [2022-02-21 04:25:09,937 INFO L290 TraceCheckUtils]: 119: Hoare triple {116820#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {116820#false} is VALID [2022-02-21 04:25:09,937 INFO L290 TraceCheckUtils]: 120: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___10~0#1); {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 121: Hoare triple {116820#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 122: Hoare triple {116820#false} assume !(1 == ~t12_pc~0); {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 123: Hoare triple {116820#false} is_transmit12_triggered_~__retres1~12#1 := 0; {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 124: Hoare triple {116820#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 125: Hoare triple {116820#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 126: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___11~0#1); {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 127: Hoare triple {116820#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 128: Hoare triple {116820#false} assume 1 == ~t13_pc~0; {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 129: Hoare triple {116820#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {116820#false} is VALID [2022-02-21 04:25:09,938 INFO L290 TraceCheckUtils]: 130: Hoare triple {116820#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {116820#false} is VALID [2022-02-21 04:25:09,939 INFO L290 TraceCheckUtils]: 131: Hoare triple {116820#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {116820#false} is VALID [2022-02-21 04:25:09,939 INFO L290 TraceCheckUtils]: 132: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___12~0#1); {116820#false} is VALID [2022-02-21 04:25:09,939 INFO L290 TraceCheckUtils]: 133: Hoare triple {116820#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {116820#false} is VALID [2022-02-21 04:25:09,939 INFO L290 TraceCheckUtils]: 134: Hoare triple {116820#false} assume 1 == ~t14_pc~0; {116820#false} is VALID [2022-02-21 04:25:09,939 INFO L290 TraceCheckUtils]: 135: Hoare triple {116820#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {116820#false} is VALID [2022-02-21 04:25:09,939 INFO L290 TraceCheckUtils]: 136: Hoare triple {116820#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {116820#false} is VALID [2022-02-21 04:25:09,939 INFO L290 TraceCheckUtils]: 137: Hoare triple {116820#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {116820#false} is VALID [2022-02-21 04:25:09,939 INFO L290 TraceCheckUtils]: 138: Hoare triple {116820#false} assume !(0 != activate_threads_~tmp___13~0#1); {116820#false} is VALID [2022-02-21 04:25:09,939 INFO L290 TraceCheckUtils]: 139: Hoare triple {116820#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {116820#false} is VALID [2022-02-21 04:25:09,940 INFO L290 TraceCheckUtils]: 140: Hoare triple {116820#false} assume 1 == ~M_E~0;~M_E~0 := 2; {116820#false} is VALID [2022-02-21 04:25:09,940 INFO L290 TraceCheckUtils]: 141: Hoare triple {116820#false} assume !(1 == ~T1_E~0); {116820#false} is VALID [2022-02-21 04:25:09,940 INFO L290 TraceCheckUtils]: 142: Hoare triple {116820#false} assume !(1 == ~T2_E~0); {116820#false} is VALID [2022-02-21 04:25:09,940 INFO L290 TraceCheckUtils]: 143: Hoare triple {116820#false} assume !(1 == ~T3_E~0); {116820#false} is VALID [2022-02-21 04:25:09,940 INFO L290 TraceCheckUtils]: 144: Hoare triple {116820#false} assume !(1 == ~T4_E~0); {116820#false} is VALID [2022-02-21 04:25:09,940 INFO L290 TraceCheckUtils]: 145: Hoare triple {116820#false} assume !(1 == ~T5_E~0); {116820#false} is VALID [2022-02-21 04:25:09,940 INFO L290 TraceCheckUtils]: 146: Hoare triple {116820#false} assume !(1 == ~T6_E~0); {116820#false} is VALID [2022-02-21 04:25:09,940 INFO L290 TraceCheckUtils]: 147: Hoare triple {116820#false} assume !(1 == ~T7_E~0); {116820#false} is VALID [2022-02-21 04:25:09,940 INFO L290 TraceCheckUtils]: 148: Hoare triple {116820#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 149: Hoare triple {116820#false} assume !(1 == ~T9_E~0); {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 150: Hoare triple {116820#false} assume !(1 == ~T10_E~0); {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 151: Hoare triple {116820#false} assume !(1 == ~T11_E~0); {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 152: Hoare triple {116820#false} assume !(1 == ~T12_E~0); {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 153: Hoare triple {116820#false} assume !(1 == ~T13_E~0); {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 154: Hoare triple {116820#false} assume !(1 == ~T14_E~0); {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 155: Hoare triple {116820#false} assume !(1 == ~E_1~0); {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 156: Hoare triple {116820#false} assume 1 == ~E_2~0;~E_2~0 := 2; {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 157: Hoare triple {116820#false} assume !(1 == ~E_3~0); {116820#false} is VALID [2022-02-21 04:25:09,941 INFO L290 TraceCheckUtils]: 158: Hoare triple {116820#false} assume !(1 == ~E_4~0); {116820#false} is VALID [2022-02-21 04:25:09,942 INFO L290 TraceCheckUtils]: 159: Hoare triple {116820#false} assume !(1 == ~E_5~0); {116820#false} is VALID [2022-02-21 04:25:09,942 INFO L290 TraceCheckUtils]: 160: Hoare triple {116820#false} assume !(1 == ~E_6~0); {116820#false} is VALID [2022-02-21 04:25:09,942 INFO L290 TraceCheckUtils]: 161: Hoare triple {116820#false} assume !(1 == ~E_7~0); {116820#false} is VALID [2022-02-21 04:25:09,942 INFO L290 TraceCheckUtils]: 162: Hoare triple {116820#false} assume !(1 == ~E_8~0); {116820#false} is VALID [2022-02-21 04:25:09,942 INFO L290 TraceCheckUtils]: 163: Hoare triple {116820#false} assume !(1 == ~E_9~0); {116820#false} is VALID [2022-02-21 04:25:09,942 INFO L290 TraceCheckUtils]: 164: Hoare triple {116820#false} assume 1 == ~E_10~0;~E_10~0 := 2; {116820#false} is VALID [2022-02-21 04:25:09,942 INFO L290 TraceCheckUtils]: 165: Hoare triple {116820#false} assume !(1 == ~E_11~0); {116820#false} is VALID [2022-02-21 04:25:09,942 INFO L290 TraceCheckUtils]: 166: Hoare triple {116820#false} assume !(1 == ~E_12~0); {116820#false} is VALID [2022-02-21 04:25:09,942 INFO L290 TraceCheckUtils]: 167: Hoare triple {116820#false} assume !(1 == ~E_13~0); {116820#false} is VALID [2022-02-21 04:25:09,943 INFO L290 TraceCheckUtils]: 168: Hoare triple {116820#false} assume !(1 == ~E_14~0); {116820#false} is VALID [2022-02-21 04:25:09,943 INFO L290 TraceCheckUtils]: 169: Hoare triple {116820#false} assume { :end_inline_reset_delta_events } true; {116820#false} is VALID [2022-02-21 04:25:09,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:09,943 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:09,943 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82261061] [2022-02-21 04:25:09,943 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82261061] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:09,944 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:09,944 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:09,944 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145093767] [2022-02-21 04:25:09,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:09,944 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:09,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:09,945 INFO L85 PathProgramCache]: Analyzing trace with hash -332858741, now seen corresponding path program 1 times [2022-02-21 04:25:09,945 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:09,945 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840729965] [2022-02-21 04:25:09,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:09,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:09,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:09,968 INFO L290 TraceCheckUtils]: 0: Hoare triple {116823#true} assume !false; {116823#true} is VALID [2022-02-21 04:25:09,979 INFO L290 TraceCheckUtils]: 1: Hoare triple {116823#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {116823#true} is VALID [2022-02-21 04:25:09,979 INFO L290 TraceCheckUtils]: 2: Hoare triple {116823#true} assume !false; {116823#true} is VALID [2022-02-21 04:25:09,979 INFO L290 TraceCheckUtils]: 3: Hoare triple {116823#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {116823#true} is VALID [2022-02-21 04:25:09,979 INFO L290 TraceCheckUtils]: 4: Hoare triple {116823#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {116823#true} is VALID [2022-02-21 04:25:09,979 INFO L290 TraceCheckUtils]: 5: Hoare triple {116823#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {116823#true} is VALID [2022-02-21 04:25:09,980 INFO L290 TraceCheckUtils]: 6: Hoare triple {116823#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {116823#true} is VALID [2022-02-21 04:25:09,980 INFO L290 TraceCheckUtils]: 7: Hoare triple {116823#true} assume !(0 != eval_~tmp~0#1); {116823#true} is VALID [2022-02-21 04:25:09,980 INFO L290 TraceCheckUtils]: 8: Hoare triple {116823#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {116823#true} is VALID [2022-02-21 04:25:09,980 INFO L290 TraceCheckUtils]: 9: Hoare triple {116823#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {116823#true} is VALID [2022-02-21 04:25:09,981 INFO L290 TraceCheckUtils]: 10: Hoare triple {116823#true} assume 0 == ~M_E~0;~M_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,981 INFO L290 TraceCheckUtils]: 11: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,981 INFO L290 TraceCheckUtils]: 12: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,981 INFO L290 TraceCheckUtils]: 13: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,982 INFO L290 TraceCheckUtils]: 14: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,982 INFO L290 TraceCheckUtils]: 15: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,982 INFO L290 TraceCheckUtils]: 16: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,983 INFO L290 TraceCheckUtils]: 17: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,983 INFO L290 TraceCheckUtils]: 18: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,983 INFO L290 TraceCheckUtils]: 19: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,984 INFO L290 TraceCheckUtils]: 20: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,984 INFO L290 TraceCheckUtils]: 21: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,984 INFO L290 TraceCheckUtils]: 22: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,984 INFO L290 TraceCheckUtils]: 23: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,985 INFO L290 TraceCheckUtils]: 24: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,985 INFO L290 TraceCheckUtils]: 25: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,985 INFO L290 TraceCheckUtils]: 26: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,986 INFO L290 TraceCheckUtils]: 27: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,986 INFO L290 TraceCheckUtils]: 28: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,986 INFO L290 TraceCheckUtils]: 29: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,987 INFO L290 TraceCheckUtils]: 30: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,987 INFO L290 TraceCheckUtils]: 31: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,987 INFO L290 TraceCheckUtils]: 32: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,987 INFO L290 TraceCheckUtils]: 33: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,988 INFO L290 TraceCheckUtils]: 34: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,988 INFO L290 TraceCheckUtils]: 35: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,988 INFO L290 TraceCheckUtils]: 36: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,989 INFO L290 TraceCheckUtils]: 37: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,989 INFO L290 TraceCheckUtils]: 38: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,989 INFO L290 TraceCheckUtils]: 39: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,989 INFO L290 TraceCheckUtils]: 40: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,990 INFO L290 TraceCheckUtils]: 41: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,990 INFO L290 TraceCheckUtils]: 42: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,990 INFO L290 TraceCheckUtils]: 43: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,991 INFO L290 TraceCheckUtils]: 44: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,991 INFO L290 TraceCheckUtils]: 45: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,991 INFO L290 TraceCheckUtils]: 46: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,992 INFO L290 TraceCheckUtils]: 47: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,992 INFO L290 TraceCheckUtils]: 48: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,992 INFO L290 TraceCheckUtils]: 49: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,992 INFO L290 TraceCheckUtils]: 50: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,993 INFO L290 TraceCheckUtils]: 51: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,993 INFO L290 TraceCheckUtils]: 52: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,993 INFO L290 TraceCheckUtils]: 53: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,994 INFO L290 TraceCheckUtils]: 54: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,994 INFO L290 TraceCheckUtils]: 55: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,994 INFO L290 TraceCheckUtils]: 56: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,995 INFO L290 TraceCheckUtils]: 57: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,995 INFO L290 TraceCheckUtils]: 58: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,995 INFO L290 TraceCheckUtils]: 59: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,995 INFO L290 TraceCheckUtils]: 60: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,996 INFO L290 TraceCheckUtils]: 61: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,996 INFO L290 TraceCheckUtils]: 62: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,996 INFO L290 TraceCheckUtils]: 63: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,997 INFO L290 TraceCheckUtils]: 64: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,997 INFO L290 TraceCheckUtils]: 65: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,997 INFO L290 TraceCheckUtils]: 66: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,997 INFO L290 TraceCheckUtils]: 67: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,998 INFO L290 TraceCheckUtils]: 68: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,998 INFO L290 TraceCheckUtils]: 69: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,998 INFO L290 TraceCheckUtils]: 70: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,999 INFO L290 TraceCheckUtils]: 71: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,999 INFO L290 TraceCheckUtils]: 72: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:09,999 INFO L290 TraceCheckUtils]: 73: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,000 INFO L290 TraceCheckUtils]: 74: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,000 INFO L290 TraceCheckUtils]: 75: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,000 INFO L290 TraceCheckUtils]: 76: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,001 INFO L290 TraceCheckUtils]: 77: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,001 INFO L290 TraceCheckUtils]: 78: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,001 INFO L290 TraceCheckUtils]: 79: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,001 INFO L290 TraceCheckUtils]: 80: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,002 INFO L290 TraceCheckUtils]: 81: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,002 INFO L290 TraceCheckUtils]: 82: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,002 INFO L290 TraceCheckUtils]: 83: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,003 INFO L290 TraceCheckUtils]: 84: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,003 INFO L290 TraceCheckUtils]: 85: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,003 INFO L290 TraceCheckUtils]: 86: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,004 INFO L290 TraceCheckUtils]: 87: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,004 INFO L290 TraceCheckUtils]: 88: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,004 INFO L290 TraceCheckUtils]: 89: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,004 INFO L290 TraceCheckUtils]: 90: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,005 INFO L290 TraceCheckUtils]: 91: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,005 INFO L290 TraceCheckUtils]: 92: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,005 INFO L290 TraceCheckUtils]: 93: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,006 INFO L290 TraceCheckUtils]: 94: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,006 INFO L290 TraceCheckUtils]: 95: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,006 INFO L290 TraceCheckUtils]: 96: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,006 INFO L290 TraceCheckUtils]: 97: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,007 INFO L290 TraceCheckUtils]: 98: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,007 INFO L290 TraceCheckUtils]: 99: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,007 INFO L290 TraceCheckUtils]: 100: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,008 INFO L290 TraceCheckUtils]: 101: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,008 INFO L290 TraceCheckUtils]: 102: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,008 INFO L290 TraceCheckUtils]: 103: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,008 INFO L290 TraceCheckUtils]: 104: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,009 INFO L290 TraceCheckUtils]: 105: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,009 INFO L290 TraceCheckUtils]: 106: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t11_pc~0); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,009 INFO L290 TraceCheckUtils]: 107: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,010 INFO L290 TraceCheckUtils]: 108: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,010 INFO L290 TraceCheckUtils]: 109: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,010 INFO L290 TraceCheckUtils]: 110: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,011 INFO L290 TraceCheckUtils]: 111: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,011 INFO L290 TraceCheckUtils]: 112: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,011 INFO L290 TraceCheckUtils]: 113: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,011 INFO L290 TraceCheckUtils]: 114: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,012 INFO L290 TraceCheckUtils]: 115: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,012 INFO L290 TraceCheckUtils]: 116: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,012 INFO L290 TraceCheckUtils]: 117: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,012 INFO L290 TraceCheckUtils]: 118: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,013 INFO L290 TraceCheckUtils]: 119: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,013 INFO L290 TraceCheckUtils]: 120: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,013 INFO L290 TraceCheckUtils]: 121: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,014 INFO L290 TraceCheckUtils]: 122: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,014 INFO L290 TraceCheckUtils]: 123: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,014 INFO L290 TraceCheckUtils]: 124: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t14_pc~0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,015 INFO L290 TraceCheckUtils]: 125: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,015 INFO L290 TraceCheckUtils]: 126: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,015 INFO L290 TraceCheckUtils]: 127: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,015 INFO L290 TraceCheckUtils]: 128: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,016 INFO L290 TraceCheckUtils]: 129: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {116825#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:10,016 INFO L290 TraceCheckUtils]: 130: Hoare triple {116825#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {116824#false} is VALID [2022-02-21 04:25:10,016 INFO L290 TraceCheckUtils]: 131: Hoare triple {116824#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,016 INFO L290 TraceCheckUtils]: 132: Hoare triple {116824#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,016 INFO L290 TraceCheckUtils]: 133: Hoare triple {116824#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,017 INFO L290 TraceCheckUtils]: 134: Hoare triple {116824#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,017 INFO L290 TraceCheckUtils]: 135: Hoare triple {116824#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,017 INFO L290 TraceCheckUtils]: 136: Hoare triple {116824#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,017 INFO L290 TraceCheckUtils]: 137: Hoare triple {116824#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,017 INFO L290 TraceCheckUtils]: 138: Hoare triple {116824#false} assume !(1 == ~T8_E~0); {116824#false} is VALID [2022-02-21 04:25:10,017 INFO L290 TraceCheckUtils]: 139: Hoare triple {116824#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,017 INFO L290 TraceCheckUtils]: 140: Hoare triple {116824#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,017 INFO L290 TraceCheckUtils]: 141: Hoare triple {116824#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,018 INFO L290 TraceCheckUtils]: 142: Hoare triple {116824#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,018 INFO L290 TraceCheckUtils]: 143: Hoare triple {116824#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,018 INFO L290 TraceCheckUtils]: 144: Hoare triple {116824#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,018 INFO L290 TraceCheckUtils]: 145: Hoare triple {116824#false} assume 1 == ~E_1~0;~E_1~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,018 INFO L290 TraceCheckUtils]: 146: Hoare triple {116824#false} assume !(1 == ~E_2~0); {116824#false} is VALID [2022-02-21 04:25:10,018 INFO L290 TraceCheckUtils]: 147: Hoare triple {116824#false} assume 1 == ~E_3~0;~E_3~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,018 INFO L290 TraceCheckUtils]: 148: Hoare triple {116824#false} assume 1 == ~E_4~0;~E_4~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,018 INFO L290 TraceCheckUtils]: 149: Hoare triple {116824#false} assume 1 == ~E_5~0;~E_5~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,019 INFO L290 TraceCheckUtils]: 150: Hoare triple {116824#false} assume 1 == ~E_6~0;~E_6~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,019 INFO L290 TraceCheckUtils]: 151: Hoare triple {116824#false} assume 1 == ~E_7~0;~E_7~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,019 INFO L290 TraceCheckUtils]: 152: Hoare triple {116824#false} assume 1 == ~E_8~0;~E_8~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,019 INFO L290 TraceCheckUtils]: 153: Hoare triple {116824#false} assume 1 == ~E_9~0;~E_9~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,019 INFO L290 TraceCheckUtils]: 154: Hoare triple {116824#false} assume !(1 == ~E_10~0); {116824#false} is VALID [2022-02-21 04:25:10,019 INFO L290 TraceCheckUtils]: 155: Hoare triple {116824#false} assume 1 == ~E_11~0;~E_11~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,019 INFO L290 TraceCheckUtils]: 156: Hoare triple {116824#false} assume 1 == ~E_12~0;~E_12~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,020 INFO L290 TraceCheckUtils]: 157: Hoare triple {116824#false} assume 1 == ~E_13~0;~E_13~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,020 INFO L290 TraceCheckUtils]: 158: Hoare triple {116824#false} assume 1 == ~E_14~0;~E_14~0 := 2; {116824#false} is VALID [2022-02-21 04:25:10,020 INFO L290 TraceCheckUtils]: 159: Hoare triple {116824#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {116824#false} is VALID [2022-02-21 04:25:10,020 INFO L290 TraceCheckUtils]: 160: Hoare triple {116824#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {116824#false} is VALID [2022-02-21 04:25:10,020 INFO L290 TraceCheckUtils]: 161: Hoare triple {116824#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {116824#false} is VALID [2022-02-21 04:25:10,020 INFO L290 TraceCheckUtils]: 162: Hoare triple {116824#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {116824#false} is VALID [2022-02-21 04:25:10,020 INFO L290 TraceCheckUtils]: 163: Hoare triple {116824#false} assume !(0 == start_simulation_~tmp~3#1); {116824#false} is VALID [2022-02-21 04:25:10,020 INFO L290 TraceCheckUtils]: 164: Hoare triple {116824#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {116824#false} is VALID [2022-02-21 04:25:10,021 INFO L290 TraceCheckUtils]: 165: Hoare triple {116824#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {116824#false} is VALID [2022-02-21 04:25:10,021 INFO L290 TraceCheckUtils]: 166: Hoare triple {116824#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {116824#false} is VALID [2022-02-21 04:25:10,021 INFO L290 TraceCheckUtils]: 167: Hoare triple {116824#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {116824#false} is VALID [2022-02-21 04:25:10,021 INFO L290 TraceCheckUtils]: 168: Hoare triple {116824#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {116824#false} is VALID [2022-02-21 04:25:10,021 INFO L290 TraceCheckUtils]: 169: Hoare triple {116824#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {116824#false} is VALID [2022-02-21 04:25:10,021 INFO L290 TraceCheckUtils]: 170: Hoare triple {116824#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {116824#false} is VALID [2022-02-21 04:25:10,021 INFO L290 TraceCheckUtils]: 171: Hoare triple {116824#false} assume !(0 != start_simulation_~tmp___0~1#1); {116824#false} is VALID [2022-02-21 04:25:10,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:10,022 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:10,022 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840729965] [2022-02-21 04:25:10,022 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1840729965] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:10,023 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:10,024 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:10,024 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317101245] [2022-02-21 04:25:10,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:10,024 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:10,024 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:10,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:25:10,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:25:10,025 INFO L87 Difference]: Start difference. First operand 2047 states and 3021 transitions. cyclomatic complexity: 975 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:13,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:13,975 INFO L93 Difference]: Finished difference Result 3936 states and 5800 transitions. [2022-02-21 04:25:13,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:25:13,975 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:14,058 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:14,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3936 states and 5800 transitions. [2022-02-21 04:25:14,413 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3724 [2022-02-21 04:25:14,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3936 states to 3936 states and 5800 transitions. [2022-02-21 04:25:14,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3936 [2022-02-21 04:25:14,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3936 [2022-02-21 04:25:14,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3936 states and 5800 transitions. [2022-02-21 04:25:14,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:14,778 INFO L681 BuchiCegarLoop]: Abstraction has 3936 states and 5800 transitions. [2022-02-21 04:25:14,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3936 states and 5800 transitions. [2022-02-21 04:25:14,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3936 to 3936. [2022-02-21 04:25:14,818 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:14,823 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3936 states and 5800 transitions. Second operand has 3936 states, 3936 states have (on average 1.4735772357723578) internal successors, (5800), 3935 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:14,827 INFO L74 IsIncluded]: Start isIncluded. First operand 3936 states and 5800 transitions. Second operand has 3936 states, 3936 states have (on average 1.4735772357723578) internal successors, (5800), 3935 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:14,874 INFO L87 Difference]: Start difference. First operand 3936 states and 5800 transitions. Second operand has 3936 states, 3936 states have (on average 1.4735772357723578) internal successors, (5800), 3935 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:15,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:15,189 INFO L93 Difference]: Finished difference Result 3936 states and 5800 transitions. [2022-02-21 04:25:15,190 INFO L276 IsEmpty]: Start isEmpty. Operand 3936 states and 5800 transitions. [2022-02-21 04:25:15,193 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:15,194 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:15,197 INFO L74 IsIncluded]: Start isIncluded. First operand has 3936 states, 3936 states have (on average 1.4735772357723578) internal successors, (5800), 3935 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3936 states and 5800 transitions. [2022-02-21 04:25:15,200 INFO L87 Difference]: Start difference. First operand has 3936 states, 3936 states have (on average 1.4735772357723578) internal successors, (5800), 3935 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3936 states and 5800 transitions. [2022-02-21 04:25:15,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:15,559 INFO L93 Difference]: Finished difference Result 3936 states and 5800 transitions. [2022-02-21 04:25:15,559 INFO L276 IsEmpty]: Start isEmpty. Operand 3936 states and 5800 transitions. [2022-02-21 04:25:15,562 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:15,562 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:15,562 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:15,562 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:15,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3936 states, 3936 states have (on average 1.4735772357723578) internal successors, (5800), 3935 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:15,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3936 states to 3936 states and 5800 transitions. [2022-02-21 04:25:15,950 INFO L704 BuchiCegarLoop]: Abstraction has 3936 states and 5800 transitions. [2022-02-21 04:25:15,950 INFO L587 BuchiCegarLoop]: Abstraction has 3936 states and 5800 transitions. [2022-02-21 04:25:15,950 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:25:15,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3936 states and 5800 transitions. [2022-02-21 04:25:15,956 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3724 [2022-02-21 04:25:15,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:15,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:15,958 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:15,958 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:15,958 INFO L791 eck$LassoCheckResult]: Stem: 121691#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 121692#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 122312#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 121411#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 121412#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 121657#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 121658#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121385#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121386#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 122665#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 121967#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 121968#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122522#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 121874#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 121875#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 121292#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 121293#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 121624#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 121824#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 120868#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 120869#L1342 assume !(0 == ~M_E~0); 121034#L1342-2 assume !(0 == ~T1_E~0); 121591#L1347-1 assume !(0 == ~T2_E~0); 122647#L1352-1 assume !(0 == ~T3_E~0); 122416#L1357-1 assume !(0 == ~T4_E~0); 121616#L1362-1 assume !(0 == ~T5_E~0); 121617#L1367-1 assume !(0 == ~T6_E~0); 121213#L1372-1 assume !(0 == ~T7_E~0); 121214#L1377-1 assume !(0 == ~T8_E~0); 121545#L1382-1 assume !(0 == ~T9_E~0); 121546#L1387-1 assume !(0 == ~T10_E~0); 122290#L1392-1 assume !(0 == ~T11_E~0); 121577#L1397-1 assume !(0 == ~T12_E~0); 121578#L1402-1 assume !(0 == ~T13_E~0); 121229#L1407-1 assume !(0 == ~T14_E~0); 121230#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 122555#L1417-1 assume !(0 == ~E_2~0); 122556#L1422-1 assume !(0 == ~E_3~0); 122834#L1427-1 assume !(0 == ~E_4~0); 121418#L1432-1 assume !(0 == ~E_5~0); 121419#L1437-1 assume !(0 == ~E_6~0); 122462#L1442-1 assume !(0 == ~E_7~0); 122463#L1447-1 assume !(0 == ~E_8~0); 122286#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 121004#L1457-1 assume !(0 == ~E_10~0); 121005#L1462-1 assume !(0 == ~E_11~0); 122501#L1467-1 assume !(0 == ~E_12~0); 122517#L1472-1 assume !(0 == ~E_13~0); 122518#L1477-1 assume !(0 == ~E_14~0); 122231#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121203#L646 assume 1 == ~m_pc~0; 121204#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 121885#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121900#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 121294#L1666 assume !(0 != activate_threads_~tmp~1#1); 121295#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122864#L665 assume !(1 == ~t1_pc~0); 121772#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 121773#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121303#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 121304#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 122101#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122102#L684 assume 1 == ~t2_pc~0; 122226#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 122144#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122213#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 122651#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 122652#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122882#L703 assume !(1 == ~t3_pc~0); 121440#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 121441#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122093#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 120838#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 120839#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 121325#L722 assume 1 == ~t4_pc~0; 122069#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 121506#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121854#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122445#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 121924#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121035#L741 assume 1 == ~t5_pc~0; 121036#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 121347#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 121501#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121502#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 122191#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 121592#L760 assume !(1 == ~t6_pc~0); 121439#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 121438#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121296#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 121297#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 122024#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122025#L779 assume 1 == ~t7_pc~0; 121080#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 120926#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120927#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 121336#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 121359#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121360#L798 assume !(1 == ~t8_pc~0); 122704#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 122614#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 121082#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 121083#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 122866#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 120903#L817 assume 1 == ~t9_pc~0; 120904#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 121700#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 121701#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 122236#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 121310#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 121311#L836 assume !(1 == ~t10_pc~0); 121327#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 121257#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 121258#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 121507#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 121508#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 122628#L855 assume 1 == ~t11_pc~0; 121896#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 121897#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 122496#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 122282#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 122108#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 121199#L874 assume !(1 == ~t12_pc~0); 121200#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 121368#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 121369#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 121509#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 120876#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 120877#L893 assume 1 == ~t13_pc~0; 122781#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 121232#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 121544#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 122698#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 122707#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 122708#L912 assume 1 == ~t14_pc~0; 122469#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 122470#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 121202#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 121134#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 121135#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121917#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 122348#L1495-2 assume !(1 == ~T1_E~0); 122349#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 122830#L1505-1 assume !(1 == ~T3_E~0); 123735#L1510-1 assume !(1 == ~T4_E~0); 123734#L1515-1 assume !(1 == ~T5_E~0); 123733#L1520-1 assume !(1 == ~T6_E~0); 123732#L1525-1 assume !(1 == ~T7_E~0); 122706#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 123731#L1535-1 assume !(1 == ~T9_E~0); 123729#L1540-1 assume !(1 == ~T10_E~0); 123726#L1545-1 assume !(1 == ~T11_E~0); 123012#L1550-1 assume !(1 == ~T12_E~0); 123011#L1555-1 assume !(1 == ~T13_E~0); 123010#L1560-1 assume !(1 == ~T14_E~0); 123009#L1565-1 assume !(1 == ~E_1~0); 123008#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 123007#L1575-1 assume !(1 == ~E_3~0); 123006#L1580-1 assume !(1 == ~E_4~0); 123005#L1585-1 assume !(1 == ~E_5~0); 123004#L1590-1 assume !(1 == ~E_6~0); 123003#L1595-1 assume !(1 == ~E_7~0); 123002#L1600-1 assume !(1 == ~E_8~0); 123001#L1605-1 assume !(1 == ~E_9~0); 122824#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 122594#L1615-1 assume !(1 == ~E_11~0); 121483#L1620-1 assume !(1 == ~E_12~0); 121484#L1625-1 assume !(1 == ~E_13~0); 122287#L1630-1 assume !(1 == ~E_14~0); 122288#L1635-1 assume { :end_inline_reset_delta_events } true; 122952#L2017-2 [2022-02-21 04:25:15,959 INFO L793 eck$LassoCheckResult]: Loop: 122952#L2017-2 assume !false; 122950#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 122214#L1316 assume !false; 122215#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 122943#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 122932#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 122931#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 122930#L1115 assume !(0 != eval_~tmp~0#1); 122621#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 122622#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 122929#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 122421#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 122422#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 122067#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 122068#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 122684#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 122901#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 122895#L1372-3 assume !(0 == ~T7_E~0); 120854#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 120855#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 121525#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 121526#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 122472#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 122828#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 122011#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 121160#L1412-3 assume !(0 == ~E_1~0); 121161#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 121932#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 121933#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 122679#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 122326#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 122026#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 122027#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 120920#L1452-3 assume !(0 == ~E_9~0); 120921#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 122610#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 122611#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 122392#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 122393#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 121158#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121159#L646-42 assume !(1 == ~m_pc~0); 121747#L646-44 is_master_triggered_~__retres1~0#1 := 0; 124286#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124285#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124284#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 124283#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124282#L665-42 assume 1 == ~t1_pc~0; 124281#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 124279#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124278#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 124277#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 124276#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124275#L684-42 assume 1 == ~t2_pc~0; 124273#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 124272#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124271#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124270#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 124269#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124268#L703-42 assume 1 == ~t3_pc~0; 124267#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 124265#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124264#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124263#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 124262#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124261#L722-42 assume 1 == ~t4_pc~0; 124259#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 124258#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124257#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124256#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124255#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124254#L741-42 assume 1 == ~t5_pc~0; 124253#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 124251#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124250#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124249#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 124248#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124247#L760-42 assume !(1 == ~t6_pc~0); 122193#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 122039#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 122040#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 122457#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 121716#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 121717#L779-42 assume 1 == ~t7_pc~0; 122595#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 122538#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 121400#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 121401#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 121255#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121256#L798-42 assume !(1 == ~t8_pc~0); 120866#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 120867#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 122667#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 122063#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 121086#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 121087#L817-42 assume !(1 == ~t9_pc~0); 121865#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 121371#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 121372#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 121498#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 122321#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 122322#L836-42 assume !(1 == ~t10_pc~0); 122427#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 121409#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 121410#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 122784#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 122785#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 122837#L855-42 assume 1 == ~t11_pc~0; 122853#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 120959#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 120960#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 121711#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 122516#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 121574#L874-42 assume 1 == ~t12_pc~0; 121575#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 121816#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 120874#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 120875#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 121128#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 121129#L893-42 assume 1 == ~t13_pc~0; 122355#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 122121#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 122136#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 122037#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 121503#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 121504#L912-42 assume !(1 == ~t14_pc~0); 122331#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 120820#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 120821#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 122432#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 124145#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124143#L1495-3 assume !(1 == ~M_E~0); 124140#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124138#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 122797#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 124135#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 124134#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 124133#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 124132#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 122343#L1530-3 assume !(1 == ~T8_E~0); 124131#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 124129#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 124126#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 124124#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 124122#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 124120#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 124118#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 124116#L1570-3 assume !(1 == ~E_2~0); 124113#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 124111#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 124109#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 124107#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 124105#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 124103#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 124100#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 124098#L1610-3 assume !(1 == ~E_10~0); 124096#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 124094#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 124092#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 124090#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 124087#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 124064#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 124048#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 122920#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 122921#L2036 assume !(0 == start_simulation_~tmp~3#1); 123131#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 122817#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 121638#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 122723#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 122044#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 122045#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122843#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 122844#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 122952#L2017-2 [2022-02-21 04:25:15,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:15,959 INFO L85 PathProgramCache]: Analyzing trace with hash 1463218542, now seen corresponding path program 1 times [2022-02-21 04:25:15,959 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:15,959 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461258222] [2022-02-21 04:25:15,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:15,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:15,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:16,012 INFO L290 TraceCheckUtils]: 0: Hoare triple {132575#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,013 INFO L290 TraceCheckUtils]: 1: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,013 INFO L290 TraceCheckUtils]: 2: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,013 INFO L290 TraceCheckUtils]: 3: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,014 INFO L290 TraceCheckUtils]: 4: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,014 INFO L290 TraceCheckUtils]: 5: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,014 INFO L290 TraceCheckUtils]: 6: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,015 INFO L290 TraceCheckUtils]: 7: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,015 INFO L290 TraceCheckUtils]: 8: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,015 INFO L290 TraceCheckUtils]: 9: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,015 INFO L290 TraceCheckUtils]: 10: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,016 INFO L290 TraceCheckUtils]: 11: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,016 INFO L290 TraceCheckUtils]: 12: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,016 INFO L290 TraceCheckUtils]: 13: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,017 INFO L290 TraceCheckUtils]: 14: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,017 INFO L290 TraceCheckUtils]: 15: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,017 INFO L290 TraceCheckUtils]: 16: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,018 INFO L290 TraceCheckUtils]: 17: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,018 INFO L290 TraceCheckUtils]: 18: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t14_i~0;~t14_st~0 := 0; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,018 INFO L290 TraceCheckUtils]: 19: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,018 INFO L290 TraceCheckUtils]: 20: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~M_E~0); {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,019 INFO L290 TraceCheckUtils]: 21: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T1_E~0); {132577#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:25:16,019 INFO L290 TraceCheckUtils]: 22: Hoare triple {132577#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T2_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,019 INFO L290 TraceCheckUtils]: 23: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T3_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,020 INFO L290 TraceCheckUtils]: 24: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T4_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,020 INFO L290 TraceCheckUtils]: 25: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T5_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,020 INFO L290 TraceCheckUtils]: 26: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T6_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,020 INFO L290 TraceCheckUtils]: 27: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T7_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,021 INFO L290 TraceCheckUtils]: 28: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T8_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,021 INFO L290 TraceCheckUtils]: 29: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T9_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,021 INFO L290 TraceCheckUtils]: 30: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T10_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,021 INFO L290 TraceCheckUtils]: 31: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T11_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,022 INFO L290 TraceCheckUtils]: 32: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T12_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,022 INFO L290 TraceCheckUtils]: 33: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T13_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,022 INFO L290 TraceCheckUtils]: 34: Hoare triple {132578#(not (= ~E_1~0 0))} assume !(0 == ~T14_E~0); {132578#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:25:16,022 INFO L290 TraceCheckUtils]: 35: Hoare triple {132578#(not (= ~E_1~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {132576#false} is VALID [2022-02-21 04:25:16,023 INFO L290 TraceCheckUtils]: 36: Hoare triple {132576#false} assume !(0 == ~E_2~0); {132576#false} is VALID [2022-02-21 04:25:16,023 INFO L290 TraceCheckUtils]: 37: Hoare triple {132576#false} assume !(0 == ~E_3~0); {132576#false} is VALID [2022-02-21 04:25:16,023 INFO L290 TraceCheckUtils]: 38: Hoare triple {132576#false} assume !(0 == ~E_4~0); {132576#false} is VALID [2022-02-21 04:25:16,023 INFO L290 TraceCheckUtils]: 39: Hoare triple {132576#false} assume !(0 == ~E_5~0); {132576#false} is VALID [2022-02-21 04:25:16,023 INFO L290 TraceCheckUtils]: 40: Hoare triple {132576#false} assume !(0 == ~E_6~0); {132576#false} is VALID [2022-02-21 04:25:16,023 INFO L290 TraceCheckUtils]: 41: Hoare triple {132576#false} assume !(0 == ~E_7~0); {132576#false} is VALID [2022-02-21 04:25:16,023 INFO L290 TraceCheckUtils]: 42: Hoare triple {132576#false} assume !(0 == ~E_8~0); {132576#false} is VALID [2022-02-21 04:25:16,023 INFO L290 TraceCheckUtils]: 43: Hoare triple {132576#false} assume 0 == ~E_9~0;~E_9~0 := 1; {132576#false} is VALID [2022-02-21 04:25:16,024 INFO L290 TraceCheckUtils]: 44: Hoare triple {132576#false} assume !(0 == ~E_10~0); {132576#false} is VALID [2022-02-21 04:25:16,024 INFO L290 TraceCheckUtils]: 45: Hoare triple {132576#false} assume !(0 == ~E_11~0); {132576#false} is VALID [2022-02-21 04:25:16,024 INFO L290 TraceCheckUtils]: 46: Hoare triple {132576#false} assume !(0 == ~E_12~0); {132576#false} is VALID [2022-02-21 04:25:16,024 INFO L290 TraceCheckUtils]: 47: Hoare triple {132576#false} assume !(0 == ~E_13~0); {132576#false} is VALID [2022-02-21 04:25:16,024 INFO L290 TraceCheckUtils]: 48: Hoare triple {132576#false} assume !(0 == ~E_14~0); {132576#false} is VALID [2022-02-21 04:25:16,024 INFO L290 TraceCheckUtils]: 49: Hoare triple {132576#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {132576#false} is VALID [2022-02-21 04:25:16,024 INFO L290 TraceCheckUtils]: 50: Hoare triple {132576#false} assume 1 == ~m_pc~0; {132576#false} is VALID [2022-02-21 04:25:16,025 INFO L290 TraceCheckUtils]: 51: Hoare triple {132576#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {132576#false} is VALID [2022-02-21 04:25:16,025 INFO L290 TraceCheckUtils]: 52: Hoare triple {132576#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {132576#false} is VALID [2022-02-21 04:25:16,025 INFO L290 TraceCheckUtils]: 53: Hoare triple {132576#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {132576#false} is VALID [2022-02-21 04:25:16,025 INFO L290 TraceCheckUtils]: 54: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp~1#1); {132576#false} is VALID [2022-02-21 04:25:16,025 INFO L290 TraceCheckUtils]: 55: Hoare triple {132576#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {132576#false} is VALID [2022-02-21 04:25:16,025 INFO L290 TraceCheckUtils]: 56: Hoare triple {132576#false} assume !(1 == ~t1_pc~0); {132576#false} is VALID [2022-02-21 04:25:16,025 INFO L290 TraceCheckUtils]: 57: Hoare triple {132576#false} is_transmit1_triggered_~__retres1~1#1 := 0; {132576#false} is VALID [2022-02-21 04:25:16,025 INFO L290 TraceCheckUtils]: 58: Hoare triple {132576#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {132576#false} is VALID [2022-02-21 04:25:16,026 INFO L290 TraceCheckUtils]: 59: Hoare triple {132576#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {132576#false} is VALID [2022-02-21 04:25:16,026 INFO L290 TraceCheckUtils]: 60: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___0~0#1); {132576#false} is VALID [2022-02-21 04:25:16,026 INFO L290 TraceCheckUtils]: 61: Hoare triple {132576#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {132576#false} is VALID [2022-02-21 04:25:16,026 INFO L290 TraceCheckUtils]: 62: Hoare triple {132576#false} assume 1 == ~t2_pc~0; {132576#false} is VALID [2022-02-21 04:25:16,026 INFO L290 TraceCheckUtils]: 63: Hoare triple {132576#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {132576#false} is VALID [2022-02-21 04:25:16,026 INFO L290 TraceCheckUtils]: 64: Hoare triple {132576#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {132576#false} is VALID [2022-02-21 04:25:16,026 INFO L290 TraceCheckUtils]: 65: Hoare triple {132576#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {132576#false} is VALID [2022-02-21 04:25:16,027 INFO L290 TraceCheckUtils]: 66: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___1~0#1); {132576#false} is VALID [2022-02-21 04:25:16,027 INFO L290 TraceCheckUtils]: 67: Hoare triple {132576#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {132576#false} is VALID [2022-02-21 04:25:16,027 INFO L290 TraceCheckUtils]: 68: Hoare triple {132576#false} assume !(1 == ~t3_pc~0); {132576#false} is VALID [2022-02-21 04:25:16,027 INFO L290 TraceCheckUtils]: 69: Hoare triple {132576#false} is_transmit3_triggered_~__retres1~3#1 := 0; {132576#false} is VALID [2022-02-21 04:25:16,027 INFO L290 TraceCheckUtils]: 70: Hoare triple {132576#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {132576#false} is VALID [2022-02-21 04:25:16,027 INFO L290 TraceCheckUtils]: 71: Hoare triple {132576#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {132576#false} is VALID [2022-02-21 04:25:16,027 INFO L290 TraceCheckUtils]: 72: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___2~0#1); {132576#false} is VALID [2022-02-21 04:25:16,027 INFO L290 TraceCheckUtils]: 73: Hoare triple {132576#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 74: Hoare triple {132576#false} assume 1 == ~t4_pc~0; {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 75: Hoare triple {132576#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 76: Hoare triple {132576#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 77: Hoare triple {132576#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 78: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___3~0#1); {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 79: Hoare triple {132576#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 80: Hoare triple {132576#false} assume 1 == ~t5_pc~0; {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 81: Hoare triple {132576#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 82: Hoare triple {132576#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {132576#false} is VALID [2022-02-21 04:25:16,028 INFO L290 TraceCheckUtils]: 83: Hoare triple {132576#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {132576#false} is VALID [2022-02-21 04:25:16,029 INFO L290 TraceCheckUtils]: 84: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___4~0#1); {132576#false} is VALID [2022-02-21 04:25:16,029 INFO L290 TraceCheckUtils]: 85: Hoare triple {132576#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {132576#false} is VALID [2022-02-21 04:25:16,029 INFO L290 TraceCheckUtils]: 86: Hoare triple {132576#false} assume !(1 == ~t6_pc~0); {132576#false} is VALID [2022-02-21 04:25:16,029 INFO L290 TraceCheckUtils]: 87: Hoare triple {132576#false} is_transmit6_triggered_~__retres1~6#1 := 0; {132576#false} is VALID [2022-02-21 04:25:16,029 INFO L290 TraceCheckUtils]: 88: Hoare triple {132576#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {132576#false} is VALID [2022-02-21 04:25:16,029 INFO L290 TraceCheckUtils]: 89: Hoare triple {132576#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {132576#false} is VALID [2022-02-21 04:25:16,029 INFO L290 TraceCheckUtils]: 90: Hoare triple {132576#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {132576#false} is VALID [2022-02-21 04:25:16,029 INFO L290 TraceCheckUtils]: 91: Hoare triple {132576#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {132576#false} is VALID [2022-02-21 04:25:16,029 INFO L290 TraceCheckUtils]: 92: Hoare triple {132576#false} assume 1 == ~t7_pc~0; {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 93: Hoare triple {132576#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 94: Hoare triple {132576#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 95: Hoare triple {132576#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 96: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___6~0#1); {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 97: Hoare triple {132576#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 98: Hoare triple {132576#false} assume !(1 == ~t8_pc~0); {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 99: Hoare triple {132576#false} is_transmit8_triggered_~__retres1~8#1 := 0; {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 100: Hoare triple {132576#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 101: Hoare triple {132576#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {132576#false} is VALID [2022-02-21 04:25:16,030 INFO L290 TraceCheckUtils]: 102: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___7~0#1); {132576#false} is VALID [2022-02-21 04:25:16,031 INFO L290 TraceCheckUtils]: 103: Hoare triple {132576#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {132576#false} is VALID [2022-02-21 04:25:16,031 INFO L290 TraceCheckUtils]: 104: Hoare triple {132576#false} assume 1 == ~t9_pc~0; {132576#false} is VALID [2022-02-21 04:25:16,031 INFO L290 TraceCheckUtils]: 105: Hoare triple {132576#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {132576#false} is VALID [2022-02-21 04:25:16,031 INFO L290 TraceCheckUtils]: 106: Hoare triple {132576#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {132576#false} is VALID [2022-02-21 04:25:16,031 INFO L290 TraceCheckUtils]: 107: Hoare triple {132576#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {132576#false} is VALID [2022-02-21 04:25:16,031 INFO L290 TraceCheckUtils]: 108: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___8~0#1); {132576#false} is VALID [2022-02-21 04:25:16,031 INFO L290 TraceCheckUtils]: 109: Hoare triple {132576#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {132576#false} is VALID [2022-02-21 04:25:16,031 INFO L290 TraceCheckUtils]: 110: Hoare triple {132576#false} assume !(1 == ~t10_pc~0); {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 111: Hoare triple {132576#false} is_transmit10_triggered_~__retres1~10#1 := 0; {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 112: Hoare triple {132576#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 113: Hoare triple {132576#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 114: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___9~0#1); {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 115: Hoare triple {132576#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 116: Hoare triple {132576#false} assume 1 == ~t11_pc~0; {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 117: Hoare triple {132576#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 118: Hoare triple {132576#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 119: Hoare triple {132576#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {132576#false} is VALID [2022-02-21 04:25:16,032 INFO L290 TraceCheckUtils]: 120: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___10~0#1); {132576#false} is VALID [2022-02-21 04:25:16,033 INFO L290 TraceCheckUtils]: 121: Hoare triple {132576#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {132576#false} is VALID [2022-02-21 04:25:16,033 INFO L290 TraceCheckUtils]: 122: Hoare triple {132576#false} assume !(1 == ~t12_pc~0); {132576#false} is VALID [2022-02-21 04:25:16,033 INFO L290 TraceCheckUtils]: 123: Hoare triple {132576#false} is_transmit12_triggered_~__retres1~12#1 := 0; {132576#false} is VALID [2022-02-21 04:25:16,033 INFO L290 TraceCheckUtils]: 124: Hoare triple {132576#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {132576#false} is VALID [2022-02-21 04:25:16,033 INFO L290 TraceCheckUtils]: 125: Hoare triple {132576#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {132576#false} is VALID [2022-02-21 04:25:16,033 INFO L290 TraceCheckUtils]: 126: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___11~0#1); {132576#false} is VALID [2022-02-21 04:25:16,033 INFO L290 TraceCheckUtils]: 127: Hoare triple {132576#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {132576#false} is VALID [2022-02-21 04:25:16,033 INFO L290 TraceCheckUtils]: 128: Hoare triple {132576#false} assume 1 == ~t13_pc~0; {132576#false} is VALID [2022-02-21 04:25:16,033 INFO L290 TraceCheckUtils]: 129: Hoare triple {132576#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {132576#false} is VALID [2022-02-21 04:25:16,034 INFO L290 TraceCheckUtils]: 130: Hoare triple {132576#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {132576#false} is VALID [2022-02-21 04:25:16,034 INFO L290 TraceCheckUtils]: 131: Hoare triple {132576#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {132576#false} is VALID [2022-02-21 04:25:16,034 INFO L290 TraceCheckUtils]: 132: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___12~0#1); {132576#false} is VALID [2022-02-21 04:25:16,034 INFO L290 TraceCheckUtils]: 133: Hoare triple {132576#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {132576#false} is VALID [2022-02-21 04:25:16,034 INFO L290 TraceCheckUtils]: 134: Hoare triple {132576#false} assume 1 == ~t14_pc~0; {132576#false} is VALID [2022-02-21 04:25:16,034 INFO L290 TraceCheckUtils]: 135: Hoare triple {132576#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {132576#false} is VALID [2022-02-21 04:25:16,034 INFO L290 TraceCheckUtils]: 136: Hoare triple {132576#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {132576#false} is VALID [2022-02-21 04:25:16,034 INFO L290 TraceCheckUtils]: 137: Hoare triple {132576#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {132576#false} is VALID [2022-02-21 04:25:16,034 INFO L290 TraceCheckUtils]: 138: Hoare triple {132576#false} assume !(0 != activate_threads_~tmp___13~0#1); {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 139: Hoare triple {132576#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 140: Hoare triple {132576#false} assume 1 == ~M_E~0;~M_E~0 := 2; {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 141: Hoare triple {132576#false} assume !(1 == ~T1_E~0); {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 142: Hoare triple {132576#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 143: Hoare triple {132576#false} assume !(1 == ~T3_E~0); {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 144: Hoare triple {132576#false} assume !(1 == ~T4_E~0); {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 145: Hoare triple {132576#false} assume !(1 == ~T5_E~0); {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 146: Hoare triple {132576#false} assume !(1 == ~T6_E~0); {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 147: Hoare triple {132576#false} assume !(1 == ~T7_E~0); {132576#false} is VALID [2022-02-21 04:25:16,035 INFO L290 TraceCheckUtils]: 148: Hoare triple {132576#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {132576#false} is VALID [2022-02-21 04:25:16,036 INFO L290 TraceCheckUtils]: 149: Hoare triple {132576#false} assume !(1 == ~T9_E~0); {132576#false} is VALID [2022-02-21 04:25:16,036 INFO L290 TraceCheckUtils]: 150: Hoare triple {132576#false} assume !(1 == ~T10_E~0); {132576#false} is VALID [2022-02-21 04:25:16,036 INFO L290 TraceCheckUtils]: 151: Hoare triple {132576#false} assume !(1 == ~T11_E~0); {132576#false} is VALID [2022-02-21 04:25:16,036 INFO L290 TraceCheckUtils]: 152: Hoare triple {132576#false} assume !(1 == ~T12_E~0); {132576#false} is VALID [2022-02-21 04:25:16,036 INFO L290 TraceCheckUtils]: 153: Hoare triple {132576#false} assume !(1 == ~T13_E~0); {132576#false} is VALID [2022-02-21 04:25:16,036 INFO L290 TraceCheckUtils]: 154: Hoare triple {132576#false} assume !(1 == ~T14_E~0); {132576#false} is VALID [2022-02-21 04:25:16,036 INFO L290 TraceCheckUtils]: 155: Hoare triple {132576#false} assume !(1 == ~E_1~0); {132576#false} is VALID [2022-02-21 04:25:16,036 INFO L290 TraceCheckUtils]: 156: Hoare triple {132576#false} assume 1 == ~E_2~0;~E_2~0 := 2; {132576#false} is VALID [2022-02-21 04:25:16,036 INFO L290 TraceCheckUtils]: 157: Hoare triple {132576#false} assume !(1 == ~E_3~0); {132576#false} is VALID [2022-02-21 04:25:16,037 INFO L290 TraceCheckUtils]: 158: Hoare triple {132576#false} assume !(1 == ~E_4~0); {132576#false} is VALID [2022-02-21 04:25:16,037 INFO L290 TraceCheckUtils]: 159: Hoare triple {132576#false} assume !(1 == ~E_5~0); {132576#false} is VALID [2022-02-21 04:25:16,037 INFO L290 TraceCheckUtils]: 160: Hoare triple {132576#false} assume !(1 == ~E_6~0); {132576#false} is VALID [2022-02-21 04:25:16,037 INFO L290 TraceCheckUtils]: 161: Hoare triple {132576#false} assume !(1 == ~E_7~0); {132576#false} is VALID [2022-02-21 04:25:16,037 INFO L290 TraceCheckUtils]: 162: Hoare triple {132576#false} assume !(1 == ~E_8~0); {132576#false} is VALID [2022-02-21 04:25:16,037 INFO L290 TraceCheckUtils]: 163: Hoare triple {132576#false} assume !(1 == ~E_9~0); {132576#false} is VALID [2022-02-21 04:25:16,037 INFO L290 TraceCheckUtils]: 164: Hoare triple {132576#false} assume 1 == ~E_10~0;~E_10~0 := 2; {132576#false} is VALID [2022-02-21 04:25:16,037 INFO L290 TraceCheckUtils]: 165: Hoare triple {132576#false} assume !(1 == ~E_11~0); {132576#false} is VALID [2022-02-21 04:25:16,037 INFO L290 TraceCheckUtils]: 166: Hoare triple {132576#false} assume !(1 == ~E_12~0); {132576#false} is VALID [2022-02-21 04:25:16,038 INFO L290 TraceCheckUtils]: 167: Hoare triple {132576#false} assume !(1 == ~E_13~0); {132576#false} is VALID [2022-02-21 04:25:16,038 INFO L290 TraceCheckUtils]: 168: Hoare triple {132576#false} assume !(1 == ~E_14~0); {132576#false} is VALID [2022-02-21 04:25:16,038 INFO L290 TraceCheckUtils]: 169: Hoare triple {132576#false} assume { :end_inline_reset_delta_events } true; {132576#false} is VALID [2022-02-21 04:25:16,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:16,039 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:16,039 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461258222] [2022-02-21 04:25:16,039 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [461258222] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:16,039 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:16,039 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:16,039 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141433451] [2022-02-21 04:25:16,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:16,040 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:16,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:16,040 INFO L85 PathProgramCache]: Analyzing trace with hash 1955542987, now seen corresponding path program 1 times [2022-02-21 04:25:16,040 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:16,040 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841191023] [2022-02-21 04:25:16,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:16,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:16,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:16,091 INFO L290 TraceCheckUtils]: 0: Hoare triple {132579#true} assume !false; {132579#true} is VALID [2022-02-21 04:25:16,091 INFO L290 TraceCheckUtils]: 1: Hoare triple {132579#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {132579#true} is VALID [2022-02-21 04:25:16,091 INFO L290 TraceCheckUtils]: 2: Hoare triple {132579#true} assume !false; {132579#true} is VALID [2022-02-21 04:25:16,091 INFO L290 TraceCheckUtils]: 3: Hoare triple {132579#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {132579#true} is VALID [2022-02-21 04:25:16,091 INFO L290 TraceCheckUtils]: 4: Hoare triple {132579#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {132579#true} is VALID [2022-02-21 04:25:16,091 INFO L290 TraceCheckUtils]: 5: Hoare triple {132579#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {132579#true} is VALID [2022-02-21 04:25:16,091 INFO L290 TraceCheckUtils]: 6: Hoare triple {132579#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {132579#true} is VALID [2022-02-21 04:25:16,092 INFO L290 TraceCheckUtils]: 7: Hoare triple {132579#true} assume !(0 != eval_~tmp~0#1); {132579#true} is VALID [2022-02-21 04:25:16,092 INFO L290 TraceCheckUtils]: 8: Hoare triple {132579#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {132579#true} is VALID [2022-02-21 04:25:16,092 INFO L290 TraceCheckUtils]: 9: Hoare triple {132579#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {132579#true} is VALID [2022-02-21 04:25:16,092 INFO L290 TraceCheckUtils]: 10: Hoare triple {132579#true} assume 0 == ~M_E~0;~M_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,092 INFO L290 TraceCheckUtils]: 11: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,093 INFO L290 TraceCheckUtils]: 12: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,093 INFO L290 TraceCheckUtils]: 13: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,093 INFO L290 TraceCheckUtils]: 14: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,094 INFO L290 TraceCheckUtils]: 15: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,094 INFO L290 TraceCheckUtils]: 16: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,094 INFO L290 TraceCheckUtils]: 17: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,094 INFO L290 TraceCheckUtils]: 18: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,095 INFO L290 TraceCheckUtils]: 19: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,095 INFO L290 TraceCheckUtils]: 20: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,095 INFO L290 TraceCheckUtils]: 21: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,095 INFO L290 TraceCheckUtils]: 22: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,096 INFO L290 TraceCheckUtils]: 23: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,096 INFO L290 TraceCheckUtils]: 24: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,096 INFO L290 TraceCheckUtils]: 25: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,096 INFO L290 TraceCheckUtils]: 26: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,097 INFO L290 TraceCheckUtils]: 27: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,097 INFO L290 TraceCheckUtils]: 28: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,097 INFO L290 TraceCheckUtils]: 29: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,097 INFO L290 TraceCheckUtils]: 30: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,098 INFO L290 TraceCheckUtils]: 31: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,098 INFO L290 TraceCheckUtils]: 32: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,098 INFO L290 TraceCheckUtils]: 33: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,098 INFO L290 TraceCheckUtils]: 34: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,099 INFO L290 TraceCheckUtils]: 35: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,099 INFO L290 TraceCheckUtils]: 36: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,099 INFO L290 TraceCheckUtils]: 37: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,100 INFO L290 TraceCheckUtils]: 38: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,100 INFO L290 TraceCheckUtils]: 39: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,100 INFO L290 TraceCheckUtils]: 40: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,100 INFO L290 TraceCheckUtils]: 41: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,101 INFO L290 TraceCheckUtils]: 42: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,101 INFO L290 TraceCheckUtils]: 43: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,101 INFO L290 TraceCheckUtils]: 44: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,101 INFO L290 TraceCheckUtils]: 45: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,102 INFO L290 TraceCheckUtils]: 46: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,102 INFO L290 TraceCheckUtils]: 47: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,102 INFO L290 TraceCheckUtils]: 48: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,103 INFO L290 TraceCheckUtils]: 49: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,103 INFO L290 TraceCheckUtils]: 50: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,103 INFO L290 TraceCheckUtils]: 51: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,103 INFO L290 TraceCheckUtils]: 52: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,104 INFO L290 TraceCheckUtils]: 53: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,104 INFO L290 TraceCheckUtils]: 54: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,104 INFO L290 TraceCheckUtils]: 55: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,104 INFO L290 TraceCheckUtils]: 56: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,105 INFO L290 TraceCheckUtils]: 57: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,105 INFO L290 TraceCheckUtils]: 58: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,105 INFO L290 TraceCheckUtils]: 59: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,105 INFO L290 TraceCheckUtils]: 60: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,106 INFO L290 TraceCheckUtils]: 61: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,106 INFO L290 TraceCheckUtils]: 62: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,106 INFO L290 TraceCheckUtils]: 63: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,107 INFO L290 TraceCheckUtils]: 64: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,107 INFO L290 TraceCheckUtils]: 65: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,107 INFO L290 TraceCheckUtils]: 66: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,107 INFO L290 TraceCheckUtils]: 67: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,108 INFO L290 TraceCheckUtils]: 68: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,108 INFO L290 TraceCheckUtils]: 69: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,108 INFO L290 TraceCheckUtils]: 70: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,108 INFO L290 TraceCheckUtils]: 71: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,109 INFO L290 TraceCheckUtils]: 72: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,109 INFO L290 TraceCheckUtils]: 73: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,109 INFO L290 TraceCheckUtils]: 74: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,109 INFO L290 TraceCheckUtils]: 75: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,110 INFO L290 TraceCheckUtils]: 76: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,110 INFO L290 TraceCheckUtils]: 77: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,110 INFO L290 TraceCheckUtils]: 78: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,111 INFO L290 TraceCheckUtils]: 79: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,111 INFO L290 TraceCheckUtils]: 80: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,111 INFO L290 TraceCheckUtils]: 81: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,111 INFO L290 TraceCheckUtils]: 82: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,112 INFO L290 TraceCheckUtils]: 83: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,112 INFO L290 TraceCheckUtils]: 84: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,112 INFO L290 TraceCheckUtils]: 85: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,112 INFO L290 TraceCheckUtils]: 86: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,113 INFO L290 TraceCheckUtils]: 87: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,113 INFO L290 TraceCheckUtils]: 88: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t8_pc~0); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,113 INFO L290 TraceCheckUtils]: 89: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,113 INFO L290 TraceCheckUtils]: 90: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,114 INFO L290 TraceCheckUtils]: 91: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,114 INFO L290 TraceCheckUtils]: 92: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,114 INFO L290 TraceCheckUtils]: 93: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,114 INFO L290 TraceCheckUtils]: 94: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t9_pc~0); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,115 INFO L290 TraceCheckUtils]: 95: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,115 INFO L290 TraceCheckUtils]: 96: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,115 INFO L290 TraceCheckUtils]: 97: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,116 INFO L290 TraceCheckUtils]: 98: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,116 INFO L290 TraceCheckUtils]: 99: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,116 INFO L290 TraceCheckUtils]: 100: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t10_pc~0); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,116 INFO L290 TraceCheckUtils]: 101: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,117 INFO L290 TraceCheckUtils]: 102: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,117 INFO L290 TraceCheckUtils]: 103: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,117 INFO L290 TraceCheckUtils]: 104: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,118 INFO L290 TraceCheckUtils]: 105: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,118 INFO L290 TraceCheckUtils]: 106: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,118 INFO L290 TraceCheckUtils]: 107: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,119 INFO L290 TraceCheckUtils]: 108: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,119 INFO L290 TraceCheckUtils]: 109: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,119 INFO L290 TraceCheckUtils]: 110: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,120 INFO L290 TraceCheckUtils]: 111: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,120 INFO L290 TraceCheckUtils]: 112: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,120 INFO L290 TraceCheckUtils]: 113: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,121 INFO L290 TraceCheckUtils]: 114: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,121 INFO L290 TraceCheckUtils]: 115: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,121 INFO L290 TraceCheckUtils]: 116: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,122 INFO L290 TraceCheckUtils]: 117: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,122 INFO L290 TraceCheckUtils]: 118: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,122 INFO L290 TraceCheckUtils]: 119: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,122 INFO L290 TraceCheckUtils]: 120: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,123 INFO L290 TraceCheckUtils]: 121: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,123 INFO L290 TraceCheckUtils]: 122: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,123 INFO L290 TraceCheckUtils]: 123: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,123 INFO L290 TraceCheckUtils]: 124: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,124 INFO L290 TraceCheckUtils]: 125: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,124 INFO L290 TraceCheckUtils]: 126: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,124 INFO L290 TraceCheckUtils]: 127: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,124 INFO L290 TraceCheckUtils]: 128: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,125 INFO L290 TraceCheckUtils]: 129: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {132581#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:16,125 INFO L290 TraceCheckUtils]: 130: Hoare triple {132581#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {132580#false} is VALID [2022-02-21 04:25:16,125 INFO L290 TraceCheckUtils]: 131: Hoare triple {132580#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,125 INFO L290 TraceCheckUtils]: 132: Hoare triple {132580#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,125 INFO L290 TraceCheckUtils]: 133: Hoare triple {132580#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,125 INFO L290 TraceCheckUtils]: 134: Hoare triple {132580#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 135: Hoare triple {132580#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 136: Hoare triple {132580#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 137: Hoare triple {132580#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 138: Hoare triple {132580#false} assume !(1 == ~T8_E~0); {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 139: Hoare triple {132580#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 140: Hoare triple {132580#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 141: Hoare triple {132580#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 142: Hoare triple {132580#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 143: Hoare triple {132580#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,126 INFO L290 TraceCheckUtils]: 144: Hoare triple {132580#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,127 INFO L290 TraceCheckUtils]: 145: Hoare triple {132580#false} assume 1 == ~E_1~0;~E_1~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,127 INFO L290 TraceCheckUtils]: 146: Hoare triple {132580#false} assume !(1 == ~E_2~0); {132580#false} is VALID [2022-02-21 04:25:16,127 INFO L290 TraceCheckUtils]: 147: Hoare triple {132580#false} assume 1 == ~E_3~0;~E_3~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,127 INFO L290 TraceCheckUtils]: 148: Hoare triple {132580#false} assume 1 == ~E_4~0;~E_4~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,127 INFO L290 TraceCheckUtils]: 149: Hoare triple {132580#false} assume 1 == ~E_5~0;~E_5~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,127 INFO L290 TraceCheckUtils]: 150: Hoare triple {132580#false} assume 1 == ~E_6~0;~E_6~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,127 INFO L290 TraceCheckUtils]: 151: Hoare triple {132580#false} assume 1 == ~E_7~0;~E_7~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,127 INFO L290 TraceCheckUtils]: 152: Hoare triple {132580#false} assume 1 == ~E_8~0;~E_8~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,127 INFO L290 TraceCheckUtils]: 153: Hoare triple {132580#false} assume 1 == ~E_9~0;~E_9~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,128 INFO L290 TraceCheckUtils]: 154: Hoare triple {132580#false} assume !(1 == ~E_10~0); {132580#false} is VALID [2022-02-21 04:25:16,128 INFO L290 TraceCheckUtils]: 155: Hoare triple {132580#false} assume 1 == ~E_11~0;~E_11~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,128 INFO L290 TraceCheckUtils]: 156: Hoare triple {132580#false} assume 1 == ~E_12~0;~E_12~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,128 INFO L290 TraceCheckUtils]: 157: Hoare triple {132580#false} assume 1 == ~E_13~0;~E_13~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,128 INFO L290 TraceCheckUtils]: 158: Hoare triple {132580#false} assume 1 == ~E_14~0;~E_14~0 := 2; {132580#false} is VALID [2022-02-21 04:25:16,128 INFO L290 TraceCheckUtils]: 159: Hoare triple {132580#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {132580#false} is VALID [2022-02-21 04:25:16,128 INFO L290 TraceCheckUtils]: 160: Hoare triple {132580#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {132580#false} is VALID [2022-02-21 04:25:16,128 INFO L290 TraceCheckUtils]: 161: Hoare triple {132580#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {132580#false} is VALID [2022-02-21 04:25:16,128 INFO L290 TraceCheckUtils]: 162: Hoare triple {132580#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {132580#false} is VALID [2022-02-21 04:25:16,129 INFO L290 TraceCheckUtils]: 163: Hoare triple {132580#false} assume !(0 == start_simulation_~tmp~3#1); {132580#false} is VALID [2022-02-21 04:25:16,129 INFO L290 TraceCheckUtils]: 164: Hoare triple {132580#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {132580#false} is VALID [2022-02-21 04:25:16,129 INFO L290 TraceCheckUtils]: 165: Hoare triple {132580#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {132580#false} is VALID [2022-02-21 04:25:16,129 INFO L290 TraceCheckUtils]: 166: Hoare triple {132580#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {132580#false} is VALID [2022-02-21 04:25:16,129 INFO L290 TraceCheckUtils]: 167: Hoare triple {132580#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {132580#false} is VALID [2022-02-21 04:25:16,129 INFO L290 TraceCheckUtils]: 168: Hoare triple {132580#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {132580#false} is VALID [2022-02-21 04:25:16,129 INFO L290 TraceCheckUtils]: 169: Hoare triple {132580#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {132580#false} is VALID [2022-02-21 04:25:16,129 INFO L290 TraceCheckUtils]: 170: Hoare triple {132580#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {132580#false} is VALID [2022-02-21 04:25:16,129 INFO L290 TraceCheckUtils]: 171: Hoare triple {132580#false} assume !(0 != start_simulation_~tmp___0~1#1); {132580#false} is VALID [2022-02-21 04:25:16,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:16,130 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:16,131 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841191023] [2022-02-21 04:25:16,131 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841191023] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:16,131 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:16,131 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:16,131 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018403069] [2022-02-21 04:25:16,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:16,131 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:16,132 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:16,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:25:16,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:25:16,132 INFO L87 Difference]: Start difference. First operand 3936 states and 5800 transitions. cyclomatic complexity: 1866 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:20,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:20,893 INFO L93 Difference]: Finished difference Result 7484 states and 11021 transitions. [2022-02-21 04:25:20,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:25:20,893 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:20,999 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:21,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7484 states and 11021 transitions. [2022-02-21 04:25:22,116 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7232 [2022-02-21 04:25:23,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7484 states to 7484 states and 11021 transitions. [2022-02-21 04:25:23,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7484 [2022-02-21 04:25:23,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7484 [2022-02-21 04:25:23,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7484 states and 11021 transitions. [2022-02-21 04:25:23,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:23,245 INFO L681 BuchiCegarLoop]: Abstraction has 7484 states and 11021 transitions. [2022-02-21 04:25:23,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7484 states and 11021 transitions. [2022-02-21 04:25:23,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7484 to 7480. [2022-02-21 04:25:23,316 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:23,325 INFO L82 GeneralOperation]: Start isEquivalent. First operand 7484 states and 11021 transitions. Second operand has 7480 states, 7480 states have (on average 1.472860962566845) internal successors, (11017), 7479 states have internal predecessors, (11017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:23,334 INFO L74 IsIncluded]: Start isIncluded. First operand 7484 states and 11021 transitions. Second operand has 7480 states, 7480 states have (on average 1.472860962566845) internal successors, (11017), 7479 states have internal predecessors, (11017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:23,343 INFO L87 Difference]: Start difference. First operand 7484 states and 11021 transitions. Second operand has 7480 states, 7480 states have (on average 1.472860962566845) internal successors, (11017), 7479 states have internal predecessors, (11017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:24,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:24,492 INFO L93 Difference]: Finished difference Result 7484 states and 11021 transitions. [2022-02-21 04:25:24,492 INFO L276 IsEmpty]: Start isEmpty. Operand 7484 states and 11021 transitions. [2022-02-21 04:25:24,498 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:24,498 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:24,506 INFO L74 IsIncluded]: Start isIncluded. First operand has 7480 states, 7480 states have (on average 1.472860962566845) internal successors, (11017), 7479 states have internal predecessors, (11017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7484 states and 11021 transitions. [2022-02-21 04:25:24,512 INFO L87 Difference]: Start difference. First operand has 7480 states, 7480 states have (on average 1.472860962566845) internal successors, (11017), 7479 states have internal predecessors, (11017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7484 states and 11021 transitions. [2022-02-21 04:25:25,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:25,730 INFO L93 Difference]: Finished difference Result 7484 states and 11021 transitions. [2022-02-21 04:25:25,730 INFO L276 IsEmpty]: Start isEmpty. Operand 7484 states and 11021 transitions. [2022-02-21 04:25:25,736 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:25,737 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:25,737 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:25,737 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:25,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7480 states, 7480 states have (on average 1.472860962566845) internal successors, (11017), 7479 states have internal predecessors, (11017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:26,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7480 states to 7480 states and 11017 transitions. [2022-02-21 04:25:26,951 INFO L704 BuchiCegarLoop]: Abstraction has 7480 states and 11017 transitions. [2022-02-21 04:25:26,951 INFO L587 BuchiCegarLoop]: Abstraction has 7480 states and 11017 transitions. [2022-02-21 04:25:26,951 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2022-02-21 04:25:26,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7480 states and 11017 transitions. [2022-02-21 04:25:26,967 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7232 [2022-02-21 04:25:26,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:26,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:26,968 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:26,968 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:26,969 INFO L791 eck$LassoCheckResult]: Stem: 141011#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 141012#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 141635#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 140727#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 140728#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 140977#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 140978#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 140701#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 140702#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 141985#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 141291#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 141292#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 141841#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 141201#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 141202#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 140603#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 140604#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 140941#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 141150#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 140172#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 140173#L1342 assume !(0 == ~M_E~0); 140338#L1342-2 assume !(0 == ~T1_E~0); 140908#L1347-1 assume !(0 == ~T2_E~0); 141968#L1352-1 assume !(0 == ~T3_E~0); 141739#L1357-1 assume !(0 == ~T4_E~0); 140933#L1362-1 assume !(0 == ~T5_E~0); 140934#L1367-1 assume !(0 == ~T6_E~0); 140521#L1372-1 assume !(0 == ~T7_E~0); 140522#L1377-1 assume !(0 == ~T8_E~0); 140861#L1382-1 assume !(0 == ~T9_E~0); 140862#L1387-1 assume !(0 == ~T10_E~0); 141613#L1392-1 assume !(0 == ~T11_E~0); 140894#L1397-1 assume !(0 == ~T12_E~0); 140895#L1402-1 assume !(0 == ~T13_E~0); 140538#L1407-1 assume !(0 == ~T14_E~0); 140539#L1412-1 assume !(0 == ~E_1~0); 141871#L1417-1 assume !(0 == ~E_2~0); 141872#L1422-1 assume !(0 == ~E_3~0); 142168#L1427-1 assume !(0 == ~E_4~0); 140734#L1432-1 assume !(0 == ~E_5~0); 140735#L1437-1 assume !(0 == ~E_6~0); 141779#L1442-1 assume !(0 == ~E_7~0); 141780#L1447-1 assume !(0 == ~E_8~0); 141610#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 140308#L1457-1 assume !(0 == ~E_10~0); 140309#L1462-1 assume !(0 == ~E_11~0); 141818#L1467-1 assume !(0 == ~E_12~0); 141836#L1472-1 assume !(0 == ~E_13~0); 141837#L1477-1 assume !(0 == ~E_14~0); 141554#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 140511#L646 assume 1 == ~m_pc~0; 140512#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 141211#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141226#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140605#L1666 assume !(0 != activate_threads_~tmp~1#1); 140606#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 142197#L665 assume !(1 == ~t1_pc~0); 141094#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 141095#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 140614#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 140615#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 141429#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 141430#L684 assume 1 == ~t2_pc~0; 141549#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 141471#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 141538#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 141972#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 141973#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 142212#L703 assume !(1 == ~t3_pc~0); 140756#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 140757#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 141422#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 140142#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 140143#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 140637#L722 assume 1 == ~t4_pc~0; 141396#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 140822#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 141181#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 141762#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 141248#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140339#L741 assume 1 == ~t5_pc~0; 140340#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 140659#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 140817#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 140818#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 141516#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 140909#L760 assume !(1 == ~t6_pc~0); 140755#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 140754#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 140607#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 140608#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 141348#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 141349#L779 assume 1 == ~t7_pc~0; 140384#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 140230#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 140231#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 140648#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 140673#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 140674#L798 assume !(1 == ~t8_pc~0); 142027#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 141936#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 140386#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 140387#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 142199#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 140207#L817 assume 1 == ~t9_pc~0; 140208#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 141019#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 141020#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 141559#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 140621#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 140622#L836 assume !(1 == ~t10_pc~0); 140639#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 140567#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 140568#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 140823#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 140824#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 141948#L855 assume 1 == ~t11_pc~0; 141222#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 141223#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 141811#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 141606#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 141436#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 140507#L874 assume !(1 == ~t12_pc~0); 140508#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 140682#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 140683#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 140825#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 140180#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 140181#L893 assume 1 == ~t13_pc~0; 142110#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 140541#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 140860#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 142020#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 142030#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 142031#L912 assume 1 == ~t14_pc~0; 141786#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 141787#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 140510#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 140439#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 140440#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 141241#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 141673#L1495-2 assume !(1 == ~T1_E~0); 141674#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 142162#L1505-1 assume !(1 == ~T3_E~0); 142678#L1510-1 assume !(1 == ~T4_E~0); 141406#L1515-1 assume !(1 == ~T5_E~0); 141407#L1520-1 assume !(1 == ~T6_E~0); 142028#L1525-1 assume !(1 == ~T7_E~0); 142029#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 142633#L1535-1 assume !(1 == ~T9_E~0); 142632#L1540-1 assume !(1 == ~T10_E~0); 142597#L1545-1 assume !(1 == ~T11_E~0); 142595#L1550-1 assume !(1 == ~T12_E~0); 142593#L1555-1 assume !(1 == ~T13_E~0); 140660#L1560-1 assume !(1 == ~T14_E~0); 140661#L1565-1 assume !(1 == ~E_1~0); 142523#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 142521#L1575-1 assume !(1 == ~E_3~0); 142481#L1580-1 assume !(1 == ~E_4~0); 142457#L1585-1 assume !(1 == ~E_5~0); 142437#L1590-1 assume !(1 == ~E_6~0); 142421#L1595-1 assume !(1 == ~E_7~0); 142414#L1600-1 assume !(1 == ~E_8~0); 142409#L1605-1 assume !(1 == ~E_9~0); 142393#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 142359#L1615-1 assume !(1 == ~E_11~0); 142341#L1620-1 assume !(1 == ~E_12~0); 142332#L1625-1 assume !(1 == ~E_13~0); 142324#L1630-1 assume !(1 == ~E_14~0); 142316#L1635-1 assume { :end_inline_reset_delta_events } true; 142309#L2017-2 [2022-02-21 04:25:26,969 INFO L793 eck$LassoCheckResult]: Loop: 142309#L2017-2 assume !false; 142306#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 142302#L1316 assume !false; 142301#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 142296#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 142285#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 142284#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 142282#L1115 assume !(0 != eval_~tmp~0#1); 142281#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 142280#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 142279#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 142278#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 142277#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 141394#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 141395#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 142005#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 142236#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 142228#L1372-3 assume !(0 == ~T7_E~0); 140158#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 140159#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 140841#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 140842#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 141789#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 142160#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 141335#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 140466#L1412-3 assume !(0 == ~E_1~0); 140467#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 141256#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 141257#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 141998#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 141649#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 141350#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 141351#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 140224#L1452-3 assume !(0 == ~E_9~0); 140225#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 141932#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 141933#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 141716#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 141717#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 140464#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 140465#L646-42 assume !(1 == ~m_pc~0); 141070#L646-44 is_master_triggered_~__retres1~0#1 := 0; 141969#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 141970#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 142141#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 142142#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 141891#L665-42 assume 1 == ~t1_pc~0; 141848#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 141850#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 142066#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 140640#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 140641#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 142235#L684-42 assume !(1 == ~t2_pc~0); 141514#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 141513#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 142215#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 141287#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 141288#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 141415#L703-42 assume 1 == ~t3_pc~0; 141619#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 141620#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 140914#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 140915#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 141723#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141322#L722-42 assume 1 == ~t4_pc~0; 141323#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 141754#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 140966#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 140789#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 140790#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 142192#L741-42 assume 1 == ~t5_pc~0; 142113#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 141185#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 141186#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 142243#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 141087#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 141088#L760-42 assume !(1 == ~t6_pc~0); 141228#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 141363#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 141364#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 141773#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 141038#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 141039#L779-42 assume 1 == ~t7_pc~0; 141915#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 141855#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 140716#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 140717#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 140565#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 140566#L798-42 assume 1 == ~t8_pc~0; 141028#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 140171#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 141987#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 141389#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 140390#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 140391#L817-42 assume 1 == ~t9_pc~0; 141191#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 140687#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 140688#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 140814#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 141644#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 141645#L836-42 assume 1 == ~t10_pc~0; 141747#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 140725#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 140726#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 142114#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 142115#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 142171#L855-42 assume 1 == ~t11_pc~0; 142190#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 140263#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 140264#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 141033#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 141835#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 140890#L874-42 assume 1 == ~t12_pc~0; 140891#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 141142#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 140178#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 140179#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 140433#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 140434#L893-42 assume 1 == ~t13_pc~0; 142266#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 143308#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 143305#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 143303#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 143301#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 143299#L912-42 assume !(1 == ~t14_pc~0); 143296#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 143292#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 143290#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 143227#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 143225#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143223#L1495-3 assume !(1 == ~M_E~0); 143221#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 143219#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 142126#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143216#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 143214#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 143212#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 143211#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 143207#L1530-3 assume !(1 == ~T8_E~0); 143205#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 143203#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 143201#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 143199#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 143138#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 143135#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 143132#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 141696#L1570-3 assume !(1 == ~E_2~0); 142723#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 142721#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 142719#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 142679#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 142677#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 142631#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 142596#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 142594#L1610-3 assume !(1 == ~E_10~0); 142592#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 142591#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 142589#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 142587#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 142552#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 142513#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 142475#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 142473#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 142446#L2036 assume !(0 == start_simulation_~tmp~3#1); 142406#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 142377#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 142375#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 142358#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 142340#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 142331#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 142323#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 142315#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 142309#L2017-2 [2022-02-21 04:25:26,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:26,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1432795152, now seen corresponding path program 1 times [2022-02-21 04:25:26,970 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:26,970 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967172160] [2022-02-21 04:25:26,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:26,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:26,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:26,996 INFO L290 TraceCheckUtils]: 0: Hoare triple {162519#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,996 INFO L290 TraceCheckUtils]: 1: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,997 INFO L290 TraceCheckUtils]: 2: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,997 INFO L290 TraceCheckUtils]: 3: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,997 INFO L290 TraceCheckUtils]: 4: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,997 INFO L290 TraceCheckUtils]: 5: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,998 INFO L290 TraceCheckUtils]: 6: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,998 INFO L290 TraceCheckUtils]: 7: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,998 INFO L290 TraceCheckUtils]: 8: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,998 INFO L290 TraceCheckUtils]: 9: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,999 INFO L290 TraceCheckUtils]: 10: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,999 INFO L290 TraceCheckUtils]: 11: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,999 INFO L290 TraceCheckUtils]: 12: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:26,999 INFO L290 TraceCheckUtils]: 13: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:27,000 INFO L290 TraceCheckUtils]: 14: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:27,000 INFO L290 TraceCheckUtils]: 15: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:27,000 INFO L290 TraceCheckUtils]: 16: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:27,000 INFO L290 TraceCheckUtils]: 17: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:27,001 INFO L290 TraceCheckUtils]: 18: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t14_i~0;~t14_st~0 := 0; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:27,001 INFO L290 TraceCheckUtils]: 19: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:27,001 INFO L290 TraceCheckUtils]: 20: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume !(0 == ~M_E~0); {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:27,001 INFO L290 TraceCheckUtils]: 21: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume !(0 == ~T1_E~0); {162521#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:25:27,002 INFO L290 TraceCheckUtils]: 22: Hoare triple {162521#(= ~T2_E~0 ~E_9~0)} assume !(0 == ~T2_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,002 INFO L290 TraceCheckUtils]: 23: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T3_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,002 INFO L290 TraceCheckUtils]: 24: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T4_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,003 INFO L290 TraceCheckUtils]: 25: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T5_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,003 INFO L290 TraceCheckUtils]: 26: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T6_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,003 INFO L290 TraceCheckUtils]: 27: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T7_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,003 INFO L290 TraceCheckUtils]: 28: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T8_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,004 INFO L290 TraceCheckUtils]: 29: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T9_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,004 INFO L290 TraceCheckUtils]: 30: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T10_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,004 INFO L290 TraceCheckUtils]: 31: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T11_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,004 INFO L290 TraceCheckUtils]: 32: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T12_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,005 INFO L290 TraceCheckUtils]: 33: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T13_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,005 INFO L290 TraceCheckUtils]: 34: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~T14_E~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,005 INFO L290 TraceCheckUtils]: 35: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~E_1~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,005 INFO L290 TraceCheckUtils]: 36: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~E_2~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,006 INFO L290 TraceCheckUtils]: 37: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~E_3~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,006 INFO L290 TraceCheckUtils]: 38: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~E_4~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,006 INFO L290 TraceCheckUtils]: 39: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~E_5~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,006 INFO L290 TraceCheckUtils]: 40: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~E_6~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,007 INFO L290 TraceCheckUtils]: 41: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~E_7~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,007 INFO L290 TraceCheckUtils]: 42: Hoare triple {162522#(not (= ~E_9~0 0))} assume !(0 == ~E_8~0); {162522#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:25:27,007 INFO L290 TraceCheckUtils]: 43: Hoare triple {162522#(not (= ~E_9~0 0))} assume 0 == ~E_9~0;~E_9~0 := 1; {162520#false} is VALID [2022-02-21 04:25:27,007 INFO L290 TraceCheckUtils]: 44: Hoare triple {162520#false} assume !(0 == ~E_10~0); {162520#false} is VALID [2022-02-21 04:25:27,007 INFO L290 TraceCheckUtils]: 45: Hoare triple {162520#false} assume !(0 == ~E_11~0); {162520#false} is VALID [2022-02-21 04:25:27,008 INFO L290 TraceCheckUtils]: 46: Hoare triple {162520#false} assume !(0 == ~E_12~0); {162520#false} is VALID [2022-02-21 04:25:27,008 INFO L290 TraceCheckUtils]: 47: Hoare triple {162520#false} assume !(0 == ~E_13~0); {162520#false} is VALID [2022-02-21 04:25:27,008 INFO L290 TraceCheckUtils]: 48: Hoare triple {162520#false} assume !(0 == ~E_14~0); {162520#false} is VALID [2022-02-21 04:25:27,008 INFO L290 TraceCheckUtils]: 49: Hoare triple {162520#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {162520#false} is VALID [2022-02-21 04:25:27,008 INFO L290 TraceCheckUtils]: 50: Hoare triple {162520#false} assume 1 == ~m_pc~0; {162520#false} is VALID [2022-02-21 04:25:27,008 INFO L290 TraceCheckUtils]: 51: Hoare triple {162520#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {162520#false} is VALID [2022-02-21 04:25:27,008 INFO L290 TraceCheckUtils]: 52: Hoare triple {162520#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {162520#false} is VALID [2022-02-21 04:25:27,008 INFO L290 TraceCheckUtils]: 53: Hoare triple {162520#false} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {162520#false} is VALID [2022-02-21 04:25:27,008 INFO L290 TraceCheckUtils]: 54: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp~1#1); {162520#false} is VALID [2022-02-21 04:25:27,009 INFO L290 TraceCheckUtils]: 55: Hoare triple {162520#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {162520#false} is VALID [2022-02-21 04:25:27,009 INFO L290 TraceCheckUtils]: 56: Hoare triple {162520#false} assume !(1 == ~t1_pc~0); {162520#false} is VALID [2022-02-21 04:25:27,009 INFO L290 TraceCheckUtils]: 57: Hoare triple {162520#false} is_transmit1_triggered_~__retres1~1#1 := 0; {162520#false} is VALID [2022-02-21 04:25:27,009 INFO L290 TraceCheckUtils]: 58: Hoare triple {162520#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {162520#false} is VALID [2022-02-21 04:25:27,009 INFO L290 TraceCheckUtils]: 59: Hoare triple {162520#false} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {162520#false} is VALID [2022-02-21 04:25:27,009 INFO L290 TraceCheckUtils]: 60: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___0~0#1); {162520#false} is VALID [2022-02-21 04:25:27,009 INFO L290 TraceCheckUtils]: 61: Hoare triple {162520#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {162520#false} is VALID [2022-02-21 04:25:27,009 INFO L290 TraceCheckUtils]: 62: Hoare triple {162520#false} assume 1 == ~t2_pc~0; {162520#false} is VALID [2022-02-21 04:25:27,009 INFO L290 TraceCheckUtils]: 63: Hoare triple {162520#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 64: Hoare triple {162520#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 65: Hoare triple {162520#false} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 66: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___1~0#1); {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 67: Hoare triple {162520#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 68: Hoare triple {162520#false} assume !(1 == ~t3_pc~0); {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 69: Hoare triple {162520#false} is_transmit3_triggered_~__retres1~3#1 := 0; {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 70: Hoare triple {162520#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 71: Hoare triple {162520#false} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 72: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___2~0#1); {162520#false} is VALID [2022-02-21 04:25:27,010 INFO L290 TraceCheckUtils]: 73: Hoare triple {162520#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {162520#false} is VALID [2022-02-21 04:25:27,011 INFO L290 TraceCheckUtils]: 74: Hoare triple {162520#false} assume 1 == ~t4_pc~0; {162520#false} is VALID [2022-02-21 04:25:27,011 INFO L290 TraceCheckUtils]: 75: Hoare triple {162520#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {162520#false} is VALID [2022-02-21 04:25:27,011 INFO L290 TraceCheckUtils]: 76: Hoare triple {162520#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {162520#false} is VALID [2022-02-21 04:25:27,011 INFO L290 TraceCheckUtils]: 77: Hoare triple {162520#false} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {162520#false} is VALID [2022-02-21 04:25:27,011 INFO L290 TraceCheckUtils]: 78: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___3~0#1); {162520#false} is VALID [2022-02-21 04:25:27,011 INFO L290 TraceCheckUtils]: 79: Hoare triple {162520#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {162520#false} is VALID [2022-02-21 04:25:27,011 INFO L290 TraceCheckUtils]: 80: Hoare triple {162520#false} assume 1 == ~t5_pc~0; {162520#false} is VALID [2022-02-21 04:25:27,011 INFO L290 TraceCheckUtils]: 81: Hoare triple {162520#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {162520#false} is VALID [2022-02-21 04:25:27,011 INFO L290 TraceCheckUtils]: 82: Hoare triple {162520#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {162520#false} is VALID [2022-02-21 04:25:27,012 INFO L290 TraceCheckUtils]: 83: Hoare triple {162520#false} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {162520#false} is VALID [2022-02-21 04:25:27,012 INFO L290 TraceCheckUtils]: 84: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___4~0#1); {162520#false} is VALID [2022-02-21 04:25:27,012 INFO L290 TraceCheckUtils]: 85: Hoare triple {162520#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {162520#false} is VALID [2022-02-21 04:25:27,012 INFO L290 TraceCheckUtils]: 86: Hoare triple {162520#false} assume !(1 == ~t6_pc~0); {162520#false} is VALID [2022-02-21 04:25:27,012 INFO L290 TraceCheckUtils]: 87: Hoare triple {162520#false} is_transmit6_triggered_~__retres1~6#1 := 0; {162520#false} is VALID [2022-02-21 04:25:27,012 INFO L290 TraceCheckUtils]: 88: Hoare triple {162520#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {162520#false} is VALID [2022-02-21 04:25:27,012 INFO L290 TraceCheckUtils]: 89: Hoare triple {162520#false} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {162520#false} is VALID [2022-02-21 04:25:27,012 INFO L290 TraceCheckUtils]: 90: Hoare triple {162520#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {162520#false} is VALID [2022-02-21 04:25:27,012 INFO L290 TraceCheckUtils]: 91: Hoare triple {162520#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 92: Hoare triple {162520#false} assume 1 == ~t7_pc~0; {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 93: Hoare triple {162520#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 94: Hoare triple {162520#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 95: Hoare triple {162520#false} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 96: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___6~0#1); {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 97: Hoare triple {162520#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 98: Hoare triple {162520#false} assume !(1 == ~t8_pc~0); {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 99: Hoare triple {162520#false} is_transmit8_triggered_~__retres1~8#1 := 0; {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 100: Hoare triple {162520#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {162520#false} is VALID [2022-02-21 04:25:27,013 INFO L290 TraceCheckUtils]: 101: Hoare triple {162520#false} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {162520#false} is VALID [2022-02-21 04:25:27,014 INFO L290 TraceCheckUtils]: 102: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___7~0#1); {162520#false} is VALID [2022-02-21 04:25:27,014 INFO L290 TraceCheckUtils]: 103: Hoare triple {162520#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {162520#false} is VALID [2022-02-21 04:25:27,014 INFO L290 TraceCheckUtils]: 104: Hoare triple {162520#false} assume 1 == ~t9_pc~0; {162520#false} is VALID [2022-02-21 04:25:27,014 INFO L290 TraceCheckUtils]: 105: Hoare triple {162520#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {162520#false} is VALID [2022-02-21 04:25:27,014 INFO L290 TraceCheckUtils]: 106: Hoare triple {162520#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {162520#false} is VALID [2022-02-21 04:25:27,014 INFO L290 TraceCheckUtils]: 107: Hoare triple {162520#false} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {162520#false} is VALID [2022-02-21 04:25:27,014 INFO L290 TraceCheckUtils]: 108: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___8~0#1); {162520#false} is VALID [2022-02-21 04:25:27,014 INFO L290 TraceCheckUtils]: 109: Hoare triple {162520#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {162520#false} is VALID [2022-02-21 04:25:27,014 INFO L290 TraceCheckUtils]: 110: Hoare triple {162520#false} assume !(1 == ~t10_pc~0); {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 111: Hoare triple {162520#false} is_transmit10_triggered_~__retres1~10#1 := 0; {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 112: Hoare triple {162520#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 113: Hoare triple {162520#false} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 114: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___9~0#1); {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 115: Hoare triple {162520#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 116: Hoare triple {162520#false} assume 1 == ~t11_pc~0; {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 117: Hoare triple {162520#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 118: Hoare triple {162520#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 119: Hoare triple {162520#false} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {162520#false} is VALID [2022-02-21 04:25:27,015 INFO L290 TraceCheckUtils]: 120: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___10~0#1); {162520#false} is VALID [2022-02-21 04:25:27,016 INFO L290 TraceCheckUtils]: 121: Hoare triple {162520#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {162520#false} is VALID [2022-02-21 04:25:27,016 INFO L290 TraceCheckUtils]: 122: Hoare triple {162520#false} assume !(1 == ~t12_pc~0); {162520#false} is VALID [2022-02-21 04:25:27,016 INFO L290 TraceCheckUtils]: 123: Hoare triple {162520#false} is_transmit12_triggered_~__retres1~12#1 := 0; {162520#false} is VALID [2022-02-21 04:25:27,016 INFO L290 TraceCheckUtils]: 124: Hoare triple {162520#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {162520#false} is VALID [2022-02-21 04:25:27,016 INFO L290 TraceCheckUtils]: 125: Hoare triple {162520#false} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {162520#false} is VALID [2022-02-21 04:25:27,016 INFO L290 TraceCheckUtils]: 126: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___11~0#1); {162520#false} is VALID [2022-02-21 04:25:27,016 INFO L290 TraceCheckUtils]: 127: Hoare triple {162520#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {162520#false} is VALID [2022-02-21 04:25:27,016 INFO L290 TraceCheckUtils]: 128: Hoare triple {162520#false} assume 1 == ~t13_pc~0; {162520#false} is VALID [2022-02-21 04:25:27,016 INFO L290 TraceCheckUtils]: 129: Hoare triple {162520#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 130: Hoare triple {162520#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 131: Hoare triple {162520#false} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 132: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___12~0#1); {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 133: Hoare triple {162520#false} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 134: Hoare triple {162520#false} assume 1 == ~t14_pc~0; {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 135: Hoare triple {162520#false} assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 136: Hoare triple {162520#false} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 137: Hoare triple {162520#false} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 138: Hoare triple {162520#false} assume !(0 != activate_threads_~tmp___13~0#1); {162520#false} is VALID [2022-02-21 04:25:27,017 INFO L290 TraceCheckUtils]: 139: Hoare triple {162520#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {162520#false} is VALID [2022-02-21 04:25:27,018 INFO L290 TraceCheckUtils]: 140: Hoare triple {162520#false} assume 1 == ~M_E~0;~M_E~0 := 2; {162520#false} is VALID [2022-02-21 04:25:27,018 INFO L290 TraceCheckUtils]: 141: Hoare triple {162520#false} assume !(1 == ~T1_E~0); {162520#false} is VALID [2022-02-21 04:25:27,018 INFO L290 TraceCheckUtils]: 142: Hoare triple {162520#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {162520#false} is VALID [2022-02-21 04:25:27,018 INFO L290 TraceCheckUtils]: 143: Hoare triple {162520#false} assume !(1 == ~T3_E~0); {162520#false} is VALID [2022-02-21 04:25:27,018 INFO L290 TraceCheckUtils]: 144: Hoare triple {162520#false} assume !(1 == ~T4_E~0); {162520#false} is VALID [2022-02-21 04:25:27,018 INFO L290 TraceCheckUtils]: 145: Hoare triple {162520#false} assume !(1 == ~T5_E~0); {162520#false} is VALID [2022-02-21 04:25:27,018 INFO L290 TraceCheckUtils]: 146: Hoare triple {162520#false} assume !(1 == ~T6_E~0); {162520#false} is VALID [2022-02-21 04:25:27,018 INFO L290 TraceCheckUtils]: 147: Hoare triple {162520#false} assume !(1 == ~T7_E~0); {162520#false} is VALID [2022-02-21 04:25:27,018 INFO L290 TraceCheckUtils]: 148: Hoare triple {162520#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 149: Hoare triple {162520#false} assume !(1 == ~T9_E~0); {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 150: Hoare triple {162520#false} assume !(1 == ~T10_E~0); {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 151: Hoare triple {162520#false} assume !(1 == ~T11_E~0); {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 152: Hoare triple {162520#false} assume !(1 == ~T12_E~0); {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 153: Hoare triple {162520#false} assume !(1 == ~T13_E~0); {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 154: Hoare triple {162520#false} assume !(1 == ~T14_E~0); {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 155: Hoare triple {162520#false} assume !(1 == ~E_1~0); {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 156: Hoare triple {162520#false} assume 1 == ~E_2~0;~E_2~0 := 2; {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 157: Hoare triple {162520#false} assume !(1 == ~E_3~0); {162520#false} is VALID [2022-02-21 04:25:27,019 INFO L290 TraceCheckUtils]: 158: Hoare triple {162520#false} assume !(1 == ~E_4~0); {162520#false} is VALID [2022-02-21 04:25:27,020 INFO L290 TraceCheckUtils]: 159: Hoare triple {162520#false} assume !(1 == ~E_5~0); {162520#false} is VALID [2022-02-21 04:25:27,020 INFO L290 TraceCheckUtils]: 160: Hoare triple {162520#false} assume !(1 == ~E_6~0); {162520#false} is VALID [2022-02-21 04:25:27,020 INFO L290 TraceCheckUtils]: 161: Hoare triple {162520#false} assume !(1 == ~E_7~0); {162520#false} is VALID [2022-02-21 04:25:27,020 INFO L290 TraceCheckUtils]: 162: Hoare triple {162520#false} assume !(1 == ~E_8~0); {162520#false} is VALID [2022-02-21 04:25:27,020 INFO L290 TraceCheckUtils]: 163: Hoare triple {162520#false} assume !(1 == ~E_9~0); {162520#false} is VALID [2022-02-21 04:25:27,020 INFO L290 TraceCheckUtils]: 164: Hoare triple {162520#false} assume 1 == ~E_10~0;~E_10~0 := 2; {162520#false} is VALID [2022-02-21 04:25:27,020 INFO L290 TraceCheckUtils]: 165: Hoare triple {162520#false} assume !(1 == ~E_11~0); {162520#false} is VALID [2022-02-21 04:25:27,020 INFO L290 TraceCheckUtils]: 166: Hoare triple {162520#false} assume !(1 == ~E_12~0); {162520#false} is VALID [2022-02-21 04:25:27,020 INFO L290 TraceCheckUtils]: 167: Hoare triple {162520#false} assume !(1 == ~E_13~0); {162520#false} is VALID [2022-02-21 04:25:27,021 INFO L290 TraceCheckUtils]: 168: Hoare triple {162520#false} assume !(1 == ~E_14~0); {162520#false} is VALID [2022-02-21 04:25:27,021 INFO L290 TraceCheckUtils]: 169: Hoare triple {162520#false} assume { :end_inline_reset_delta_events } true; {162520#false} is VALID [2022-02-21 04:25:27,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:27,021 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:27,021 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967172160] [2022-02-21 04:25:27,021 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967172160] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:27,022 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:27,022 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:27,022 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143589638] [2022-02-21 04:25:27,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:27,022 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:27,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:27,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1350239155, now seen corresponding path program 1 times [2022-02-21 04:25:27,023 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:27,023 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619284702] [2022-02-21 04:25:27,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:27,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:27,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:27,050 INFO L290 TraceCheckUtils]: 0: Hoare triple {162523#true} assume !false; {162523#true} is VALID [2022-02-21 04:25:27,051 INFO L290 TraceCheckUtils]: 1: Hoare triple {162523#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {162523#true} is VALID [2022-02-21 04:25:27,051 INFO L290 TraceCheckUtils]: 2: Hoare triple {162523#true} assume !false; {162523#true} is VALID [2022-02-21 04:25:27,051 INFO L290 TraceCheckUtils]: 3: Hoare triple {162523#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {162523#true} is VALID [2022-02-21 04:25:27,051 INFO L290 TraceCheckUtils]: 4: Hoare triple {162523#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {162523#true} is VALID [2022-02-21 04:25:27,051 INFO L290 TraceCheckUtils]: 5: Hoare triple {162523#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {162523#true} is VALID [2022-02-21 04:25:27,051 INFO L290 TraceCheckUtils]: 6: Hoare triple {162523#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {162523#true} is VALID [2022-02-21 04:25:27,051 INFO L290 TraceCheckUtils]: 7: Hoare triple {162523#true} assume !(0 != eval_~tmp~0#1); {162523#true} is VALID [2022-02-21 04:25:27,052 INFO L290 TraceCheckUtils]: 8: Hoare triple {162523#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {162523#true} is VALID [2022-02-21 04:25:27,052 INFO L290 TraceCheckUtils]: 9: Hoare triple {162523#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {162523#true} is VALID [2022-02-21 04:25:27,052 INFO L290 TraceCheckUtils]: 10: Hoare triple {162523#true} assume 0 == ~M_E~0;~M_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,052 INFO L290 TraceCheckUtils]: 11: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,053 INFO L290 TraceCheckUtils]: 12: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,053 INFO L290 TraceCheckUtils]: 13: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,053 INFO L290 TraceCheckUtils]: 14: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,053 INFO L290 TraceCheckUtils]: 15: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,054 INFO L290 TraceCheckUtils]: 16: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,054 INFO L290 TraceCheckUtils]: 17: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T7_E~0); {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,054 INFO L290 TraceCheckUtils]: 18: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,054 INFO L290 TraceCheckUtils]: 19: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,055 INFO L290 TraceCheckUtils]: 20: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,055 INFO L290 TraceCheckUtils]: 21: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,055 INFO L290 TraceCheckUtils]: 22: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,055 INFO L290 TraceCheckUtils]: 23: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,056 INFO L290 TraceCheckUtils]: 24: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T14_E~0;~T14_E~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,056 INFO L290 TraceCheckUtils]: 25: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_1~0); {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,056 INFO L290 TraceCheckUtils]: 26: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,056 INFO L290 TraceCheckUtils]: 27: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,057 INFO L290 TraceCheckUtils]: 28: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,057 INFO L290 TraceCheckUtils]: 29: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,057 INFO L290 TraceCheckUtils]: 30: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,057 INFO L290 TraceCheckUtils]: 31: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,058 INFO L290 TraceCheckUtils]: 32: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,058 INFO L290 TraceCheckUtils]: 33: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_9~0); {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,058 INFO L290 TraceCheckUtils]: 34: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,058 INFO L290 TraceCheckUtils]: 35: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,059 INFO L290 TraceCheckUtils]: 36: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_12~0;~E_12~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,059 INFO L290 TraceCheckUtils]: 37: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,059 INFO L290 TraceCheckUtils]: 38: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_14~0;~E_14~0 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,060 INFO L290 TraceCheckUtils]: 39: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,060 INFO L290 TraceCheckUtils]: 40: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,060 INFO L290 TraceCheckUtils]: 41: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,060 INFO L290 TraceCheckUtils]: 42: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,061 INFO L290 TraceCheckUtils]: 43: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,061 INFO L290 TraceCheckUtils]: 44: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,061 INFO L290 TraceCheckUtils]: 45: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,061 INFO L290 TraceCheckUtils]: 46: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,062 INFO L290 TraceCheckUtils]: 47: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,062 INFO L290 TraceCheckUtils]: 48: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,062 INFO L290 TraceCheckUtils]: 49: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,063 INFO L290 TraceCheckUtils]: 50: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,063 INFO L290 TraceCheckUtils]: 51: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,063 INFO L290 TraceCheckUtils]: 52: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,063 INFO L290 TraceCheckUtils]: 53: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,064 INFO L290 TraceCheckUtils]: 54: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,064 INFO L290 TraceCheckUtils]: 55: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,064 INFO L290 TraceCheckUtils]: 56: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,064 INFO L290 TraceCheckUtils]: 57: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,065 INFO L290 TraceCheckUtils]: 58: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,065 INFO L290 TraceCheckUtils]: 59: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,065 INFO L290 TraceCheckUtils]: 60: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,065 INFO L290 TraceCheckUtils]: 61: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,066 INFO L290 TraceCheckUtils]: 62: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,066 INFO L290 TraceCheckUtils]: 63: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,066 INFO L290 TraceCheckUtils]: 64: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,067 INFO L290 TraceCheckUtils]: 65: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,067 INFO L290 TraceCheckUtils]: 66: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,067 INFO L290 TraceCheckUtils]: 67: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,067 INFO L290 TraceCheckUtils]: 68: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,068 INFO L290 TraceCheckUtils]: 69: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,068 INFO L290 TraceCheckUtils]: 70: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,068 INFO L290 TraceCheckUtils]: 71: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,068 INFO L290 TraceCheckUtils]: 72: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,069 INFO L290 TraceCheckUtils]: 73: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,069 INFO L290 TraceCheckUtils]: 74: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,069 INFO L290 TraceCheckUtils]: 75: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,070 INFO L290 TraceCheckUtils]: 76: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,070 INFO L290 TraceCheckUtils]: 77: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,070 INFO L290 TraceCheckUtils]: 78: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,070 INFO L290 TraceCheckUtils]: 79: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,071 INFO L290 TraceCheckUtils]: 80: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,071 INFO L290 TraceCheckUtils]: 81: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,071 INFO L290 TraceCheckUtils]: 82: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,071 INFO L290 TraceCheckUtils]: 83: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,072 INFO L290 TraceCheckUtils]: 84: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,072 INFO L290 TraceCheckUtils]: 85: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,072 INFO L290 TraceCheckUtils]: 86: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,073 INFO L290 TraceCheckUtils]: 87: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,073 INFO L290 TraceCheckUtils]: 88: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t8_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,073 INFO L290 TraceCheckUtils]: 89: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,073 INFO L290 TraceCheckUtils]: 90: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,074 INFO L290 TraceCheckUtils]: 91: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,074 INFO L290 TraceCheckUtils]: 92: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,074 INFO L290 TraceCheckUtils]: 93: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,074 INFO L290 TraceCheckUtils]: 94: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t9_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,075 INFO L290 TraceCheckUtils]: 95: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,075 INFO L290 TraceCheckUtils]: 96: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,075 INFO L290 TraceCheckUtils]: 97: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,075 INFO L290 TraceCheckUtils]: 98: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,076 INFO L290 TraceCheckUtils]: 99: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,076 INFO L290 TraceCheckUtils]: 100: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t10_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,076 INFO L290 TraceCheckUtils]: 101: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,077 INFO L290 TraceCheckUtils]: 102: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,077 INFO L290 TraceCheckUtils]: 103: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,077 INFO L290 TraceCheckUtils]: 104: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,078 INFO L290 TraceCheckUtils]: 105: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,078 INFO L290 TraceCheckUtils]: 106: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t11_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,078 INFO L290 TraceCheckUtils]: 107: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,078 INFO L290 TraceCheckUtils]: 108: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,079 INFO L290 TraceCheckUtils]: 109: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,079 INFO L290 TraceCheckUtils]: 110: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,079 INFO L290 TraceCheckUtils]: 111: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,079 INFO L290 TraceCheckUtils]: 112: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t12_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,080 INFO L290 TraceCheckUtils]: 113: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,080 INFO L290 TraceCheckUtils]: 114: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,080 INFO L290 TraceCheckUtils]: 115: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,081 INFO L290 TraceCheckUtils]: 116: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,081 INFO L290 TraceCheckUtils]: 117: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,081 INFO L290 TraceCheckUtils]: 118: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t13_pc~0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,081 INFO L290 TraceCheckUtils]: 119: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,082 INFO L290 TraceCheckUtils]: 120: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,082 INFO L290 TraceCheckUtils]: 121: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,082 INFO L290 TraceCheckUtils]: 122: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___12~0#1); {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,082 INFO L290 TraceCheckUtils]: 123: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,083 INFO L290 TraceCheckUtils]: 124: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t14_pc~0); {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,083 INFO L290 TraceCheckUtils]: 125: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_~__retres1~14#1 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,083 INFO L290 TraceCheckUtils]: 126: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,084 INFO L290 TraceCheckUtils]: 127: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,084 INFO L290 TraceCheckUtils]: 128: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,084 INFO L290 TraceCheckUtils]: 129: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {162525#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:25:27,084 INFO L290 TraceCheckUtils]: 130: Hoare triple {162525#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {162524#false} is VALID [2022-02-21 04:25:27,084 INFO L290 TraceCheckUtils]: 131: Hoare triple {162524#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,085 INFO L290 TraceCheckUtils]: 132: Hoare triple {162524#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,085 INFO L290 TraceCheckUtils]: 133: Hoare triple {162524#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,085 INFO L290 TraceCheckUtils]: 134: Hoare triple {162524#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,085 INFO L290 TraceCheckUtils]: 135: Hoare triple {162524#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,085 INFO L290 TraceCheckUtils]: 136: Hoare triple {162524#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,085 INFO L290 TraceCheckUtils]: 137: Hoare triple {162524#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,085 INFO L290 TraceCheckUtils]: 138: Hoare triple {162524#false} assume !(1 == ~T8_E~0); {162524#false} is VALID [2022-02-21 04:25:27,085 INFO L290 TraceCheckUtils]: 139: Hoare triple {162524#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,085 INFO L290 TraceCheckUtils]: 140: Hoare triple {162524#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 141: Hoare triple {162524#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 142: Hoare triple {162524#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 143: Hoare triple {162524#false} assume 1 == ~T13_E~0;~T13_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 144: Hoare triple {162524#false} assume 1 == ~T14_E~0;~T14_E~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 145: Hoare triple {162524#false} assume 1 == ~E_1~0;~E_1~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 146: Hoare triple {162524#false} assume !(1 == ~E_2~0); {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 147: Hoare triple {162524#false} assume 1 == ~E_3~0;~E_3~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 148: Hoare triple {162524#false} assume 1 == ~E_4~0;~E_4~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 149: Hoare triple {162524#false} assume 1 == ~E_5~0;~E_5~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,086 INFO L290 TraceCheckUtils]: 150: Hoare triple {162524#false} assume 1 == ~E_6~0;~E_6~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,087 INFO L290 TraceCheckUtils]: 151: Hoare triple {162524#false} assume 1 == ~E_7~0;~E_7~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,087 INFO L290 TraceCheckUtils]: 152: Hoare triple {162524#false} assume 1 == ~E_8~0;~E_8~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,087 INFO L290 TraceCheckUtils]: 153: Hoare triple {162524#false} assume 1 == ~E_9~0;~E_9~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,087 INFO L290 TraceCheckUtils]: 154: Hoare triple {162524#false} assume !(1 == ~E_10~0); {162524#false} is VALID [2022-02-21 04:25:27,087 INFO L290 TraceCheckUtils]: 155: Hoare triple {162524#false} assume 1 == ~E_11~0;~E_11~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,087 INFO L290 TraceCheckUtils]: 156: Hoare triple {162524#false} assume 1 == ~E_12~0;~E_12~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,087 INFO L290 TraceCheckUtils]: 157: Hoare triple {162524#false} assume 1 == ~E_13~0;~E_13~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,087 INFO L290 TraceCheckUtils]: 158: Hoare triple {162524#false} assume 1 == ~E_14~0;~E_14~0 := 2; {162524#false} is VALID [2022-02-21 04:25:27,087 INFO L290 TraceCheckUtils]: 159: Hoare triple {162524#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {162524#false} is VALID [2022-02-21 04:25:27,088 INFO L290 TraceCheckUtils]: 160: Hoare triple {162524#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {162524#false} is VALID [2022-02-21 04:25:27,088 INFO L290 TraceCheckUtils]: 161: Hoare triple {162524#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {162524#false} is VALID [2022-02-21 04:25:27,088 INFO L290 TraceCheckUtils]: 162: Hoare triple {162524#false} start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; {162524#false} is VALID [2022-02-21 04:25:27,088 INFO L290 TraceCheckUtils]: 163: Hoare triple {162524#false} assume !(0 == start_simulation_~tmp~3#1); {162524#false} is VALID [2022-02-21 04:25:27,088 INFO L290 TraceCheckUtils]: 164: Hoare triple {162524#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; {162524#false} is VALID [2022-02-21 04:25:27,088 INFO L290 TraceCheckUtils]: 165: Hoare triple {162524#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; {162524#false} is VALID [2022-02-21 04:25:27,088 INFO L290 TraceCheckUtils]: 166: Hoare triple {162524#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; {162524#false} is VALID [2022-02-21 04:25:27,088 INFO L290 TraceCheckUtils]: 167: Hoare triple {162524#false} stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; {162524#false} is VALID [2022-02-21 04:25:27,088 INFO L290 TraceCheckUtils]: 168: Hoare triple {162524#false} assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; {162524#false} is VALID [2022-02-21 04:25:27,089 INFO L290 TraceCheckUtils]: 169: Hoare triple {162524#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {162524#false} is VALID [2022-02-21 04:25:27,089 INFO L290 TraceCheckUtils]: 170: Hoare triple {162524#false} start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; {162524#false} is VALID [2022-02-21 04:25:27,089 INFO L290 TraceCheckUtils]: 171: Hoare triple {162524#false} assume !(0 != start_simulation_~tmp___0~1#1); {162524#false} is VALID [2022-02-21 04:25:27,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:27,089 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:27,089 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619284702] [2022-02-21 04:25:27,090 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619284702] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:27,090 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:27,090 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:27,090 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286462420] [2022-02-21 04:25:27,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:27,090 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:27,091 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:27,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:25:27,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:25:27,091 INFO L87 Difference]: Start difference. First operand 7480 states and 11017 transitions. cyclomatic complexity: 3541 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:34,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:34,664 INFO L93 Difference]: Finished difference Result 14320 states and 21070 transitions. [2022-02-21 04:25:34,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:25:34,665 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:34,768 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 170 edges. 170 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:34,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14320 states and 21070 transitions. [2022-02-21 04:25:39,243 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14036 [2022-02-21 04:25:43,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14320 states to 14320 states and 21070 transitions. [2022-02-21 04:25:43,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14320 [2022-02-21 04:25:43,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14320 [2022-02-21 04:25:43,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14320 states and 21070 transitions. [2022-02-21 04:25:43,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:43,659 INFO L681 BuchiCegarLoop]: Abstraction has 14320 states and 21070 transitions. [2022-02-21 04:25:43,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14320 states and 21070 transitions. [2022-02-21 04:25:43,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14320 to 14316. [2022-02-21 04:25:43,782 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:43,799 INFO L82 GeneralOperation]: Start isEquivalent. First operand 14320 states and 21070 transitions. Second operand has 14316 states, 14316 states have (on average 1.4715004191114835) internal successors, (21066), 14315 states have internal predecessors, (21066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:43,815 INFO L74 IsIncluded]: Start isIncluded. First operand 14320 states and 21070 transitions. Second operand has 14316 states, 14316 states have (on average 1.4715004191114835) internal successors, (21066), 14315 states have internal predecessors, (21066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:43,832 INFO L87 Difference]: Start difference. First operand 14320 states and 21070 transitions. Second operand has 14316 states, 14316 states have (on average 1.4715004191114835) internal successors, (21066), 14315 states have internal predecessors, (21066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)