./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-linux-3.16-rc1/43_2a_consumption_linux-3.16-rc1.tar.xz-43_2a-drivers--tty--isicom.ko-entry_point.cil.out.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-linux-3.16-rc1/43_2a_consumption_linux-3.16-rc1.tar.xz-43_2a-drivers--tty--isicom.ko-entry_point.cil.out.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash f2c7848ca043d8b9ca4f9ab4b1ce08f583c2bd8d8967a557df683af547558d91 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 22:01:55,598 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 22:01:55,600 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 22:01:55,641 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 22:01:55,641 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 22:01:55,646 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 22:01:55,648 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 22:01:55,655 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 22:01:55,657 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 22:01:55,663 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 22:01:55,664 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 22:01:55,665 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 22:01:55,666 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 22:01:55,668 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 22:01:55,669 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 22:01:55,671 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 22:01:55,672 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 22:01:55,673 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 22:01:55,679 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 22:01:55,685 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 22:01:55,687 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 22:01:55,687 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 22:01:55,689 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 22:01:55,689 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 22:01:55,692 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 22:01:55,692 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 22:01:55,693 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 22:01:55,694 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 22:01:55,694 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 22:01:55,695 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 22:01:55,695 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 22:01:55,696 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 22:01:55,697 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 22:01:55,698 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 22:01:55,699 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 22:01:55,699 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 22:01:55,700 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 22:01:55,700 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 22:01:55,700 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 22:01:55,700 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 22:01:55,701 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 22:01:55,702 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 22:01:55,733 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 22:01:55,734 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 22:01:55,734 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 22:01:55,734 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 22:01:55,736 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 22:01:55,736 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 22:01:55,737 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 22:01:55,737 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 22:01:55,737 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 22:01:55,737 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 22:01:55,738 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 22:01:55,738 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 22:01:55,738 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 22:01:55,738 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 22:01:55,738 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 22:01:55,739 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 22:01:55,739 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 22:01:55,739 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 22:01:55,739 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 22:01:55,739 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 22:01:55,739 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 22:01:55,740 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:01:55,740 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 22:01:55,740 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 22:01:55,740 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 22:01:55,740 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 22:01:55,740 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 22:01:55,741 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 22:01:55,741 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 22:01:55,741 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 22:01:55,741 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f2c7848ca043d8b9ca4f9ab4b1ce08f583c2bd8d8967a557df683af547558d91 [2022-02-20 22:01:55,920 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 22:01:55,942 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 22:01:55,944 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 22:01:55,945 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 22:01:55,946 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 22:01:55,947 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-linux-3.16-rc1/43_2a_consumption_linux-3.16-rc1.tar.xz-43_2a-drivers--tty--isicom.ko-entry_point.cil.out.i [2022-02-20 22:01:56,010 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/aa275a3f5/2ed6137ebe9c4ca59b1884c8a31dda3b/FLAG1146b333f [2022-02-20 22:01:56,567 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 22:01:56,567 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.16-rc1/43_2a_consumption_linux-3.16-rc1.tar.xz-43_2a-drivers--tty--isicom.ko-entry_point.cil.out.i [2022-02-20 22:01:56,602 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/aa275a3f5/2ed6137ebe9c4ca59b1884c8a31dda3b/FLAG1146b333f [2022-02-20 22:01:56,755 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/aa275a3f5/2ed6137ebe9c4ca59b1884c8a31dda3b [2022-02-20 22:01:56,757 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 22:01:56,758 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 22:01:56,759 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 22:01:56,759 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 22:01:56,767 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 22:01:56,768 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:01:56" (1/1) ... [2022-02-20 22:01:56,772 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5d699216 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:56, skipping insertion in model container [2022-02-20 22:01:56,772 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:01:56" (1/1) ... [2022-02-20 22:01:56,777 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 22:01:56,849 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 22:01:57,206 WARN L1246 CHandler]: Detected problem Invalid redeclaration of the name show at C: (*show)(struct kobject___0 * , struct attribute___0 * , char * ) [3602] [2022-02-20 22:01:57,207 WARN L1246 CHandler]: Detected problem Invalid redeclaration of the name store at C: (*store)(struct kobject___0 * , struct attribute___0 * , char const * , size_t ) [3603-3604] [2022-02-20 22:01:57,324 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.16-rc1/43_2a_consumption_linux-3.16-rc1.tar.xz-43_2a-drivers--tty--isicom.ko-entry_point.cil.out.i[110145,110158] [2022-02-20 22:01:58,002 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:01:58,182 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 22:01:58,269 WARN L1246 CHandler]: Detected problem Invalid redeclaration of the name show at C: (*show)(struct kobject___0 * , struct attribute___0 * , char * ) [3602] [2022-02-20 22:01:58,269 WARN L1246 CHandler]: Detected problem Invalid redeclaration of the name store at C: (*store)(struct kobject___0 * , struct attribute___0 * , char const * , size_t ) [3603-3604] [2022-02-20 22:01:58,276 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.16-rc1/43_2a_consumption_linux-3.16-rc1.tar.xz-43_2a-drivers--tty--isicom.ko-entry_point.cil.out.i[110145,110158] [2022-02-20 22:01:58,441 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:01:58,510 INFO L208 MainTranslator]: Completed translation [2022-02-20 22:01:58,511 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58 WrapperNode [2022-02-20 22:01:58,511 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 22:01:58,523 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 22:01:58,523 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 22:01:58,523 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 22:01:58,528 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,593 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,715 INFO L137 Inliner]: procedures = 199, calls = 1517, calls flagged for inlining = 95, calls inlined = 93, statements flattened = 3890 [2022-02-20 22:01:58,716 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 22:01:58,717 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 22:01:58,717 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 22:01:58,717 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 22:01:58,723 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,723 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,746 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,747 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,843 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,869 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,889 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,905 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 22:01:58,907 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 22:01:58,907 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 22:01:58,907 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 22:01:58,908 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (1/1) ... [2022-02-20 22:01:58,913 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:01:58,922 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:01:58,973 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 22:01:58,991 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 22:01:59,003 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_start [2022-02-20 22:01:59,003 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_start [2022-02-20 22:01:59,003 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_set_termios [2022-02-20 22:01:59,004 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_set_termios [2022-02-20 22:01:59,004 INFO L130 BoogieDeclarations]: Found specification of procedure msleep [2022-02-20 22:01:59,004 INFO L138 BoogieDeclarations]: Found implementation of procedure msleep [2022-02-20 22:01:59,004 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2022-02-20 22:01:59,004 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2022-02-20 22:01:59,004 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 22:01:59,004 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 22:01:59,004 INFO L130 BoogieDeclarations]: Found specification of procedure tty_kref_put [2022-02-20 22:01:59,005 INFO L138 BoogieDeclarations]: Found implementation of procedure tty_kref_put [2022-02-20 22:01:59,005 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock [2022-02-20 22:01:59,005 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock [2022-02-20 22:01:59,005 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_tiocmset [2022-02-20 22:01:59,005 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_tiocmset [2022-02-20 22:01:59,005 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_disconnect_3 [2022-02-20 22:01:59,005 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_disconnect_3 [2022-02-20 22:01:59,005 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 22:01:59,005 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 22:01:59,006 INFO L130 BoogieDeclarations]: Found specification of procedure pci_release_region [2022-02-20 22:01:59,006 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_release_region [2022-02-20 22:01:59,006 INFO L130 BoogieDeclarations]: Found specification of procedure char_buf_ptr [2022-02-20 22:01:59,006 INFO L138 BoogieDeclarations]: Found implementation of procedure char_buf_ptr [2022-02-20 22:01:59,006 INFO L130 BoogieDeclarations]: Found specification of procedure raise_dtr [2022-02-20 22:01:59,006 INFO L138 BoogieDeclarations]: Found implementation of procedure raise_dtr [2022-02-20 22:01:59,006 INFO L130 BoogieDeclarations]: Found specification of procedure tty_flip_buffer_push [2022-02-20 22:01:59,006 INFO L138 BoogieDeclarations]: Found implementation of procedure tty_flip_buffer_push [2022-02-20 22:01:59,007 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_chars_in_buffer [2022-02-20 22:01:59,007 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_chars_in_buffer [2022-02-20 22:01:59,007 INFO L130 BoogieDeclarations]: Found specification of procedure tty_insert_flip_char [2022-02-20 22:01:59,007 INFO L138 BoogieDeclarations]: Found implementation of procedure tty_insert_flip_char [2022-02-20 22:01:59,007 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2022-02-20 22:01:59,007 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2022-02-20 22:01:59,007 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_flush_buffer [2022-02-20 22:01:59,008 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_flush_buffer [2022-02-20 22:01:59,008 INFO L130 BoogieDeclarations]: Found specification of procedure mutex_unlock [2022-02-20 22:01:59,008 INFO L138 BoogieDeclarations]: Found implementation of procedure mutex_unlock [2022-02-20 22:01:59,008 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2022-02-20 22:01:59,008 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2022-02-20 22:01:59,008 INFO L130 BoogieDeclarations]: Found specification of procedure outsw [2022-02-20 22:01:59,008 INFO L138 BoogieDeclarations]: Found implementation of procedure outsw [2022-02-20 22:01:59,008 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2022-02-20 22:01:59,009 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2022-02-20 22:01:59,009 INFO L130 BoogieDeclarations]: Found specification of procedure insw [2022-02-20 22:01:59,009 INFO L138 BoogieDeclarations]: Found implementation of procedure insw [2022-02-20 22:01:59,009 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_put_char [2022-02-20 22:01:59,009 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_put_char [2022-02-20 22:01:59,009 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 22:01:59,009 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 22:01:59,010 INFO L130 BoogieDeclarations]: Found specification of procedure pci_get_drvdata [2022-02-20 22:01:59,010 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_get_drvdata [2022-02-20 22:01:59,010 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_write_room [2022-02-20 22:01:59,010 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_write_room [2022-02-20 22:01:59,011 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_ioctl [2022-02-20 22:01:59,011 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_ioctl [2022-02-20 22:01:59,011 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock [2022-02-20 22:01:59,012 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock [2022-02-20 22:01:59,012 INFO L130 BoogieDeclarations]: Found specification of procedure drop_dtr [2022-02-20 22:01:59,012 INFO L138 BoogieDeclarations]: Found implementation of procedure drop_dtr [2022-02-20 22:01:59,012 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2022-02-20 22:01:59,012 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2022-02-20 22:01:59,012 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 22:01:59,012 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 22:01:59,012 INFO L130 BoogieDeclarations]: Found specification of procedure might_fault [2022-02-20 22:01:59,013 INFO L138 BoogieDeclarations]: Found implementation of procedure might_fault [2022-02-20 22:01:59,013 INFO L130 BoogieDeclarations]: Found specification of procedure put_tty_driver [2022-02-20 22:01:59,013 INFO L138 BoogieDeclarations]: Found implementation of procedure put_tty_driver [2022-02-20 22:01:59,013 INFO L130 BoogieDeclarations]: Found specification of procedure outw [2022-02-20 22:01:59,014 INFO L138 BoogieDeclarations]: Found implementation of procedure outw [2022-02-20 22:01:59,014 INFO L130 BoogieDeclarations]: Found specification of procedure mutex_lock_nested [2022-02-20 22:01:59,014 INFO L138 BoogieDeclarations]: Found implementation of procedure mutex_lock_nested [2022-02-20 22:01:59,014 INFO L130 BoogieDeclarations]: Found specification of procedure tty_port_tty_get [2022-02-20 22:01:59,014 INFO L138 BoogieDeclarations]: Found implementation of procedure tty_port_tty_get [2022-02-20 22:01:59,014 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock [2022-02-20 22:01:59,014 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock [2022-02-20 22:01:59,014 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2022-02-20 22:01:59,014 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_dtr_rts [2022-02-20 22:01:59,015 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_dtr_rts [2022-02-20 22:01:59,015 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2022-02-20 22:01:59,015 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2022-02-20 22:01:59,015 INFO L130 BoogieDeclarations]: Found specification of procedure _copy_from_user [2022-02-20 22:01:59,015 INFO L138 BoogieDeclarations]: Found implementation of procedure _copy_from_user [2022-02-20 22:01:59,015 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_config_port [2022-02-20 22:01:59,015 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_config_port [2022-02-20 22:01:59,015 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2022-02-20 22:01:59,016 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 22:01:59,016 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_tiocmget [2022-02-20 22:01:59,016 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_tiocmget [2022-02-20 22:01:59,016 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_unthrottle [2022-02-20 22:01:59,016 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_unthrottle [2022-02-20 22:01:59,016 INFO L130 BoogieDeclarations]: Found specification of procedure lock_card [2022-02-20 22:01:59,017 INFO L138 BoogieDeclarations]: Found implementation of procedure lock_card [2022-02-20 22:01:59,017 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_flush_chars [2022-02-20 22:01:59,017 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_flush_chars [2022-02-20 22:01:59,017 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2022-02-20 22:01:59,017 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2022-02-20 22:01:59,017 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 22:01:59,018 INFO L130 BoogieDeclarations]: Found specification of procedure pci_disable_device [2022-02-20 22:01:59,018 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_disable_device [2022-02-20 22:01:59,018 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2022-02-20 22:01:59,018 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2022-02-20 22:01:59,018 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2022-02-20 22:01:59,018 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2022-02-20 22:01:59,018 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_carrier_raised [2022-02-20 22:01:59,018 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_carrier_raised [2022-02-20 22:01:59,019 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 22:01:59,019 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_hangup [2022-02-20 22:01:59,019 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_hangup [2022-02-20 22:01:59,019 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_throttle [2022-02-20 22:01:59,019 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_throttle [2022-02-20 22:01:59,019 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 22:01:59,020 INFO L130 BoogieDeclarations]: Found specification of procedure tty_wakeup [2022-02-20 22:01:59,020 INFO L138 BoogieDeclarations]: Found implementation of procedure tty_wakeup [2022-02-20 22:01:59,020 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2022-02-20 22:01:59,021 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2022-02-20 22:01:59,022 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-02-20 22:01:59,022 INFO L130 BoogieDeclarations]: Found specification of procedure __bad_percpu_size [2022-02-20 22:01:59,022 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2022-02-20 22:01:59,022 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2022-02-20 22:01:59,023 INFO L130 BoogieDeclarations]: Found specification of procedure _copy_to_user [2022-02-20 22:01:59,024 INFO L138 BoogieDeclarations]: Found implementation of procedure _copy_to_user [2022-02-20 22:01:59,024 INFO L130 BoogieDeclarations]: Found specification of procedure mod_timer [2022-02-20 22:01:59,024 INFO L138 BoogieDeclarations]: Found implementation of procedure mod_timer [2022-02-20 22:01:59,025 INFO L130 BoogieDeclarations]: Found specification of procedure unlock_card [2022-02-20 22:01:59,029 INFO L138 BoogieDeclarations]: Found implementation of procedure unlock_card [2022-02-20 22:01:59,029 INFO L130 BoogieDeclarations]: Found specification of procedure isicom_send_break [2022-02-20 22:01:59,029 INFO L138 BoogieDeclarations]: Found implementation of procedure isicom_send_break [2022-02-20 22:01:59,029 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 22:01:59,029 INFO L130 BoogieDeclarations]: Found specification of procedure inw [2022-02-20 22:01:59,029 INFO L138 BoogieDeclarations]: Found implementation of procedure inw [2022-02-20 22:01:59,029 INFO L130 BoogieDeclarations]: Found specification of procedure WaitTillCardIsFree [2022-02-20 22:01:59,030 INFO L138 BoogieDeclarations]: Found implementation of procedure WaitTillCardIsFree [2022-02-20 22:01:59,030 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 22:01:59,030 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 22:01:59,030 INFO L130 BoogieDeclarations]: Found specification of procedure tty_unregister_driver [2022-02-20 22:01:59,030 INFO L138 BoogieDeclarations]: Found implementation of procedure tty_unregister_driver [2022-02-20 22:01:59,030 INFO L130 BoogieDeclarations]: Found specification of procedure IS_ERR [2022-02-20 22:01:59,030 INFO L138 BoogieDeclarations]: Found implementation of procedure IS_ERR [2022-02-20 22:01:59,504 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 22:01:59,506 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 22:02:00,049 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 22:02:12,638 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 22:02:12,653 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 22:02:12,654 INFO L299 CfgBuilder]: Removed 1 assume(true) statements. [2022-02-20 22:02:12,658 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:02:12 BoogieIcfgContainer [2022-02-20 22:02:12,658 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 22:02:12,659 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 22:02:12,659 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 22:02:12,662 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 22:02:12,662 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 10:01:56" (1/3) ... [2022-02-20 22:02:12,663 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@28c6e9d7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:02:12, skipping insertion in model container [2022-02-20 22:02:12,663 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:01:58" (2/3) ... [2022-02-20 22:02:12,663 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@28c6e9d7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:02:12, skipping insertion in model container [2022-02-20 22:02:12,663 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:02:12" (3/3) ... [2022-02-20 22:02:12,664 INFO L111 eAbstractionObserver]: Analyzing ICFG 43_2a_consumption_linux-3.16-rc1.tar.xz-43_2a-drivers--tty--isicom.ko-entry_point.cil.out.i [2022-02-20 22:02:12,669 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 22:02:12,669 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-02-20 22:02:12,716 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 22:02:12,722 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 22:02:12,723 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-02-20 22:02:12,776 INFO L276 IsEmpty]: Start isEmpty. Operand has 1364 states, 973 states have (on average 1.433710174717369) internal successors, (1395), 1004 states have internal predecessors, (1395), 330 states have call successors, (330), 61 states have call predecessors, (330), 60 states have return successors, (322), 320 states have call predecessors, (322), 322 states have call successors, (322) [2022-02-20 22:02:12,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 190 [2022-02-20 22:02:12,809 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:02:12,810 INFO L514 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:02:12,811 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:02:12,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:02:12,814 INFO L85 PathProgramCache]: Analyzing trace with hash -1655239035, now seen corresponding path program 1 times [2022-02-20 22:02:12,821 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:02:12,821 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421624162] [2022-02-20 22:02:12,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:02:12,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:02:13,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,291 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:02:13,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,304 INFO L290 TraceCheckUtils]: 0: Hoare triple {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {1367#true} is VALID [2022-02-20 22:02:13,305 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {1367#true} is VALID [2022-02-20 22:02:13,305 INFO L290 TraceCheckUtils]: 2: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,305 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1367#true} {1367#true} #3596#return; {1367#true} is VALID [2022-02-20 22:02:13,306 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 8 [2022-02-20 22:02:13,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,314 INFO L290 TraceCheckUtils]: 0: Hoare triple {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {1367#true} is VALID [2022-02-20 22:02:13,314 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {1367#true} is VALID [2022-02-20 22:02:13,315 INFO L290 TraceCheckUtils]: 2: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,315 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1367#true} {1367#true} #3598#return; {1367#true} is VALID [2022-02-20 22:02:13,315 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 14 [2022-02-20 22:02:13,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,322 INFO L290 TraceCheckUtils]: 0: Hoare triple {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {1367#true} is VALID [2022-02-20 22:02:13,323 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {1367#true} is VALID [2022-02-20 22:02:13,323 INFO L290 TraceCheckUtils]: 2: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,323 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1367#true} {1367#true} #3600#return; {1367#true} is VALID [2022-02-20 22:02:13,324 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 20 [2022-02-20 22:02:13,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,331 INFO L290 TraceCheckUtils]: 0: Hoare triple {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {1367#true} is VALID [2022-02-20 22:02:13,331 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {1367#true} is VALID [2022-02-20 22:02:13,331 INFO L290 TraceCheckUtils]: 2: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,332 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1367#true} {1367#true} #3602#return; {1367#true} is VALID [2022-02-20 22:02:13,332 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 54 [2022-02-20 22:02:13,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,339 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~pdev#1.base, ~pdev#1.offset := #in~pdev#1.base, #in~pdev#1.offset;havoc ~tmp~11#1.base, ~tmp~11#1.offset;assume { :begin_inline_dev_get_drvdata } true;dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset := ~pdev#1.base, 147 + ~pdev#1.offset;havoc dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset, dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset;dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset := dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset;call dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset := read~$Pointer$(dev_get_drvdata_~dev#1.base, 489 + dev_get_drvdata_~dev#1.offset, 8);dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset := dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset; {1367#true} is VALID [2022-02-20 22:02:13,339 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} #t~ret153#1.base, #t~ret153#1.offset := dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;assume { :end_inline_dev_get_drvdata } true;~tmp~11#1.base, ~tmp~11#1.offset := #t~ret153#1.base, #t~ret153#1.offset;havoc #t~ret153#1.base, #t~ret153#1.offset;#res#1.base, #res#1.offset := ~tmp~11#1.base, ~tmp~11#1.offset; {1367#true} is VALID [2022-02-20 22:02:13,340 INFO L290 TraceCheckUtils]: 2: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,340 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1367#true} {1368#false} #3860#return; {1368#false} is VALID [2022-02-20 22:02:13,340 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 60 [2022-02-20 22:02:13,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,346 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {1367#true} is VALID [2022-02-20 22:02:13,347 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,347 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3862#return; {1368#false} is VALID [2022-02-20 22:02:13,347 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 66 [2022-02-20 22:02:13,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,354 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,354 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,354 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3864#return; {1368#false} is VALID [2022-02-20 22:02:13,354 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 71 [2022-02-20 22:02:13,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,360 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~arg0 := #in~arg0; {1367#true} is VALID [2022-02-20 22:02:13,360 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,361 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3866#return; {1368#false} is VALID [2022-02-20 22:02:13,361 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 75 [2022-02-20 22:02:13,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,367 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,367 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,368 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3868#return; {1368#false} is VALID [2022-02-20 22:02:13,368 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 79 [2022-02-20 22:02:13,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,373 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~arg0 := #in~arg0; {1367#true} is VALID [2022-02-20 22:02:13,373 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,374 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3870#return; {1368#false} is VALID [2022-02-20 22:02:13,374 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 83 [2022-02-20 22:02:13,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,380 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,380 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,380 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3872#return; {1368#false} is VALID [2022-02-20 22:02:13,380 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 90 [2022-02-20 22:02:13,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,386 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {1367#true} is VALID [2022-02-20 22:02:13,386 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,386 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3874#return; {1368#false} is VALID [2022-02-20 22:02:13,387 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 100 [2022-02-20 22:02:13,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,393 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~pdev#1.base, ~pdev#1.offset := #in~pdev#1.base, #in~pdev#1.offset;havoc ~tmp~11#1.base, ~tmp~11#1.offset;assume { :begin_inline_dev_get_drvdata } true;dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset := ~pdev#1.base, 147 + ~pdev#1.offset;havoc dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset, dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset;dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset := dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset;call dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset := read~$Pointer$(dev_get_drvdata_~dev#1.base, 489 + dev_get_drvdata_~dev#1.offset, 8);dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset := dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset; {1367#true} is VALID [2022-02-20 22:02:13,394 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} #t~ret153#1.base, #t~ret153#1.offset := dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;assume { :end_inline_dev_get_drvdata } true;~tmp~11#1.base, ~tmp~11#1.offset := #t~ret153#1.base, #t~ret153#1.offset;havoc #t~ret153#1.base, #t~ret153#1.offset;#res#1.base, #res#1.offset := ~tmp~11#1.base, ~tmp~11#1.offset; {1367#true} is VALID [2022-02-20 22:02:13,394 INFO L290 TraceCheckUtils]: 2: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,394 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1367#true} {1368#false} #3882#return; {1368#false} is VALID [2022-02-20 22:02:13,394 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 114 [2022-02-20 22:02:13,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,407 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 22:02:13,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,412 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,413 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,413 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1367#true} #3568#return; {1367#true} is VALID [2022-02-20 22:02:13,413 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 10 [2022-02-20 22:02:13,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,418 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,419 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,419 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1367#true} #3570#return; {1367#true} is VALID [2022-02-20 22:02:13,419 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~base#1 := #in~base#1;havoc ~count~0#1;havoc ~a~0#1;havoc ~tmp~12#1;havoc ~__ms~0#1;havoc ~tmp___0~6#1;havoc ~tmp___1~3#1;havoc ~tmp___2~2#1;havoc ~tmp___3~0#1;~count~0#1 := 0;assume { :begin_inline_preempt_count } true;havoc preempt_count_#res#1;havoc preempt_count_#t~switch11#1, preempt_count_~pfo_ret__~0#1;havoc preempt_count_~pfo_ret__~0#1;preempt_count_#t~switch11#1 := false; {1367#true} is VALID [2022-02-20 22:02:13,419 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume preempt_count_#t~switch11#1; {1367#true} is VALID [2022-02-20 22:02:13,420 INFO L290 TraceCheckUtils]: 2: Hoare triple {1367#true} preempt_count_#res#1 := (if 0 == preempt_count_~pfo_ret__~0#1 then 0 else (if 1 == preempt_count_~pfo_ret__~0#1 then 1 else ~bitwiseAnd(preempt_count_~pfo_ret__~0#1, 2147483647))); {1367#true} is VALID [2022-02-20 22:02:13,420 INFO L290 TraceCheckUtils]: 3: Hoare triple {1367#true} #t~ret154#1 := preempt_count_#res#1;assume { :end_inline_preempt_count } true;assume -2147483648 <= #t~ret154#1 && #t~ret154#1 <= 2147483647;~tmp~12#1 := #t~ret154#1;havoc #t~ret154#1;~a~0#1 := (if 0 != (if 0 == ~tmp~12#1 then 0 else (if 1 == ~tmp~12#1 then 1 else ~bitwiseAnd(~tmp~12#1, 18446744073707454463))) % 18446744073709551616 then 1 else 0); {1367#true} is VALID [2022-02-20 22:02:13,420 INFO L272 TraceCheckUtils]: 4: Hoare triple {1367#true} call #t~ret155#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,420 INFO L290 TraceCheckUtils]: 5: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,420 INFO L290 TraceCheckUtils]: 6: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,421 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1367#true} {1367#true} #3568#return; {1367#true} is VALID [2022-02-20 22:02:13,421 INFO L290 TraceCheckUtils]: 8: Hoare triple {1367#true} ~tmp___1~3#1 := #t~ret155#1;havoc #t~ret155#1; {1367#true} is VALID [2022-02-20 22:02:13,421 INFO L290 TraceCheckUtils]: 9: Hoare triple {1367#true} assume !(0 == ~tmp___1~3#1 % 65536); {1367#true} is VALID [2022-02-20 22:02:13,421 INFO L272 TraceCheckUtils]: 10: Hoare triple {1367#true} call #t~ret156#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,421 INFO L290 TraceCheckUtils]: 11: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,422 INFO L290 TraceCheckUtils]: 12: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,422 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1367#true} {1367#true} #3570#return; {1367#true} is VALID [2022-02-20 22:02:13,422 INFO L290 TraceCheckUtils]: 14: Hoare triple {1367#true} ~tmp___3~0#1 := #t~ret156#1;havoc #t~ret156#1;#res#1 := (if 0 == ~tmp___3~0#1 % 65536 then 1 else 0); {1367#true} is VALID [2022-02-20 22:02:13,422 INFO L290 TraceCheckUtils]: 15: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,422 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1367#true} {1368#false} #3912#return; {1368#false} is VALID [2022-02-20 22:02:13,423 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 134 [2022-02-20 22:02:13,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,429 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,429 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,429 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3914#return; {1368#false} is VALID [2022-02-20 22:02:13,429 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 138 [2022-02-20 22:02:13,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,435 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,435 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,435 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3916#return; {1368#false} is VALID [2022-02-20 22:02:13,436 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 143 [2022-02-20 22:02:13,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,441 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,442 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,442 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3918#return; {1368#false} is VALID [2022-02-20 22:02:13,442 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 148 [2022-02-20 22:02:13,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,448 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,449 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,449 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3920#return; {1368#false} is VALID [2022-02-20 22:02:13,449 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 152 [2022-02-20 22:02:13,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,455 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,455 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,455 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3922#return; {1368#false} is VALID [2022-02-20 22:02:13,455 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 156 [2022-02-20 22:02:13,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,460 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~arg0 := #in~arg0; {1367#true} is VALID [2022-02-20 22:02:13,461 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,461 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3924#return; {1368#false} is VALID [2022-02-20 22:02:13,461 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 160 [2022-02-20 22:02:13,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,534 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 22:02:13,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,539 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,539 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,540 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1367#true} #3568#return; {1367#true} is VALID [2022-02-20 22:02:13,540 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 10 [2022-02-20 22:02:13,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,544 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,545 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,545 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1367#true} #3570#return; {1367#true} is VALID [2022-02-20 22:02:13,545 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~base#1 := #in~base#1;havoc ~count~0#1;havoc ~a~0#1;havoc ~tmp~12#1;havoc ~__ms~0#1;havoc ~tmp___0~6#1;havoc ~tmp___1~3#1;havoc ~tmp___2~2#1;havoc ~tmp___3~0#1;~count~0#1 := 0;assume { :begin_inline_preempt_count } true;havoc preempt_count_#res#1;havoc preempt_count_#t~switch11#1, preempt_count_~pfo_ret__~0#1;havoc preempt_count_~pfo_ret__~0#1;preempt_count_#t~switch11#1 := false; {1367#true} is VALID [2022-02-20 22:02:13,545 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume preempt_count_#t~switch11#1; {1367#true} is VALID [2022-02-20 22:02:13,545 INFO L290 TraceCheckUtils]: 2: Hoare triple {1367#true} preempt_count_#res#1 := (if 0 == preempt_count_~pfo_ret__~0#1 then 0 else (if 1 == preempt_count_~pfo_ret__~0#1 then 1 else ~bitwiseAnd(preempt_count_~pfo_ret__~0#1, 2147483647))); {1367#true} is VALID [2022-02-20 22:02:13,546 INFO L290 TraceCheckUtils]: 3: Hoare triple {1367#true} #t~ret154#1 := preempt_count_#res#1;assume { :end_inline_preempt_count } true;assume -2147483648 <= #t~ret154#1 && #t~ret154#1 <= 2147483647;~tmp~12#1 := #t~ret154#1;havoc #t~ret154#1;~a~0#1 := (if 0 != (if 0 == ~tmp~12#1 then 0 else (if 1 == ~tmp~12#1 then 1 else ~bitwiseAnd(~tmp~12#1, 18446744073707454463))) % 18446744073709551616 then 1 else 0); {1367#true} is VALID [2022-02-20 22:02:13,546 INFO L272 TraceCheckUtils]: 4: Hoare triple {1367#true} call #t~ret155#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,546 INFO L290 TraceCheckUtils]: 5: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,546 INFO L290 TraceCheckUtils]: 6: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,546 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1367#true} {1367#true} #3568#return; {1367#true} is VALID [2022-02-20 22:02:13,547 INFO L290 TraceCheckUtils]: 8: Hoare triple {1367#true} ~tmp___1~3#1 := #t~ret155#1;havoc #t~ret155#1; {1367#true} is VALID [2022-02-20 22:02:13,547 INFO L290 TraceCheckUtils]: 9: Hoare triple {1367#true} assume !(0 == ~tmp___1~3#1 % 65536); {1367#true} is VALID [2022-02-20 22:02:13,547 INFO L272 TraceCheckUtils]: 10: Hoare triple {1367#true} call #t~ret156#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,547 INFO L290 TraceCheckUtils]: 11: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,547 INFO L290 TraceCheckUtils]: 12: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,547 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1367#true} {1367#true} #3570#return; {1367#true} is VALID [2022-02-20 22:02:13,548 INFO L290 TraceCheckUtils]: 14: Hoare triple {1367#true} ~tmp___3~0#1 := #t~ret156#1;havoc #t~ret156#1;#res#1 := (if 0 == ~tmp___3~0#1 % 65536 then 1 else 0); {1367#true} is VALID [2022-02-20 22:02:13,548 INFO L290 TraceCheckUtils]: 15: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,548 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1367#true} {1368#false} #3926#return; {1368#false} is VALID [2022-02-20 22:02:13,548 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 180 [2022-02-20 22:02:13,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:13,554 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,554 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,554 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1367#true} {1368#false} #3928#return; {1368#false} is VALID [2022-02-20 22:02:13,557 INFO L290 TraceCheckUtils]: 0: Hoare triple {1367#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(92, 2);call #Ultimate.allocInit(7, 3);call write~init~int(105, 3, 0, 1);call write~init~int(115, 3, 1, 1);call write~init~int(105, 3, 2, 1);call write~init~int(99, 3, 3, 1);call write~init~int(111, 3, 4, 1);call write~init~int(109, 3, 5, 1);call write~init~int(0, 3, 6, 1);call #Ultimate.allocInit(214, 4);call #Ultimate.allocInit(214, 5);call #Ultimate.allocInit(38, 6);call #Ultimate.allocInit(7, 7);call write~init~int(105, 7, 0, 1);call write~init~int(115, 7, 1, 1);call write~init~int(105, 7, 2, 1);call write~init~int(99, 7, 3, 1);call write~init~int(111, 7, 4, 1);call write~init~int(109, 7, 5, 1);call write~init~int(0, 7, 6, 1);call #Ultimate.allocInit(10, 8);call #Ultimate.allocInit(210, 9);call #Ultimate.allocInit(25, 10);call #Ultimate.allocInit(33, 11);call #Ultimate.allocInit(47, 12);call #Ultimate.allocInit(17, 13);call #Ultimate.allocInit(7, 14);call write~init~int(105, 14, 0, 1);call write~init~int(115, 14, 1, 1);call write~init~int(105, 14, 2, 1);call write~init~int(99, 14, 3, 1);call write~init~int(111, 14, 4, 1);call write~init~int(109, 14, 5, 1);call write~init~int(0, 14, 6, 1);call #Ultimate.allocInit(17, 15);call #Ultimate.allocInit(210, 16);call #Ultimate.allocInit(15, 17);call #Ultimate.allocInit(23, 18);call #Ultimate.allocInit(17, 19);call #Ultimate.allocInit(7, 20);call write~init~int(105, 20, 0, 1);call write~init~int(115, 20, 1, 1);call write~init~int(105, 20, 2, 1);call write~init~int(99, 20, 3, 1);call write~init~int(111, 20, 4, 1);call write~init~int(109, 20, 5, 1);call write~init~int(0, 20, 6, 1);call #Ultimate.allocInit(17, 21);call #Ultimate.allocInit(210, 22);call #Ultimate.allocInit(16, 23);call #Ultimate.allocInit(24, 24);call #Ultimate.allocInit(17, 25);call #Ultimate.allocInit(7, 26);call write~init~int(105, 26, 0, 1);call write~init~int(115, 26, 1, 1);call write~init~int(105, 26, 2, 1);call write~init~int(99, 26, 3, 1);call write~init~int(111, 26, 4, 1);call write~init~int(109, 26, 5, 1);call write~init~int(0, 26, 6, 1);call #Ultimate.allocInit(17, 27);call #Ultimate.allocInit(210, 28);call #Ultimate.allocInit(14, 29);call #Ultimate.allocInit(22, 30);call #Ultimate.allocInit(17, 31);call #Ultimate.allocInit(7, 32);call write~init~int(105, 32, 0, 1);call write~init~int(115, 32, 1, 1);call write~init~int(105, 32, 2, 1);call write~init~int(99, 32, 3, 1);call write~init~int(111, 32, 4, 1);call write~init~int(109, 32, 5, 1);call write~init~int(0, 32, 6, 1);call #Ultimate.allocInit(17, 33);call #Ultimate.allocInit(210, 34);call #Ultimate.allocInit(36, 35);call #Ultimate.allocInit(44, 36);call #Ultimate.allocInit(17, 37);call #Ultimate.allocInit(7, 38);call write~init~int(105, 38, 0, 1);call write~init~int(115, 38, 1, 1);call write~init~int(105, 38, 2, 1);call write~init~int(99, 38, 3, 1);call write~init~int(111, 38, 4, 1);call write~init~int(109, 38, 5, 1);call write~init~int(0, 38, 6, 1);call #Ultimate.allocInit(17, 39);call #Ultimate.allocInit(210, 40);call #Ultimate.allocInit(28, 41);call #Ultimate.allocInit(36, 42);call #Ultimate.allocInit(17, 43);call #Ultimate.allocInit(7, 44);call write~init~int(105, 44, 0, 1);call write~init~int(115, 44, 1, 1);call write~init~int(105, 44, 2, 1);call write~init~int(99, 44, 3, 1);call write~init~int(111, 44, 4, 1);call write~init~int(109, 44, 5, 1);call write~init~int(0, 44, 6, 1);call #Ultimate.allocInit(17, 45);call #Ultimate.allocInit(210, 46);call #Ultimate.allocInit(55, 47);call #Ultimate.allocInit(63, 48);call #Ultimate.allocInit(17, 49);call #Ultimate.allocInit(7, 50);call write~init~int(105, 50, 0, 1);call write~init~int(115, 50, 1, 1);call write~init~int(105, 50, 2, 1);call write~init~int(99, 50, 3, 1);call write~init~int(111, 50, 4, 1);call write~init~int(109, 50, 5, 1);call write~init~int(0, 50, 6, 1);call #Ultimate.allocInit(21, 51);call #Ultimate.allocInit(210, 52);call #Ultimate.allocInit(32, 53);call #Ultimate.allocInit(40, 54);call #Ultimate.allocInit(21, 55);call #Ultimate.allocInit(7, 56);call write~init~int(105, 56, 0, 1);call write~init~int(115, 56, 1, 1);call write~init~int(105, 56, 2, 1);call write~init~int(99, 56, 3, 1);call write~init~int(111, 56, 4, 1);call write~init~int(109, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(11, 57);call #Ultimate.allocInit(210, 58);call #Ultimate.allocInit(35, 59);call #Ultimate.allocInit(35, 60);call #Ultimate.allocInit(69, 61);call #Ultimate.allocInit(7, 62);call write~init~int(105, 62, 0, 1);call write~init~int(115, 62, 1, 1);call write~init~int(105, 62, 2, 1);call write~init~int(99, 62, 3, 1);call write~init~int(111, 62, 4, 1);call write~init~int(109, 62, 5, 1);call write~init~int(0, 62, 6, 1);call #Ultimate.allocInit(11, 63);call #Ultimate.allocInit(210, 64);call #Ultimate.allocInit(10, 65);call #Ultimate.allocInit(10, 66);call #Ultimate.allocInit(35, 67);call #Ultimate.allocInit(7, 68);call write~init~int(45, 68, 0, 1);call write~init~int(68, 68, 1, 1);call write~init~int(111, 68, 2, 1);call write~init~int(110, 68, 3, 1);call write~init~int(101, 68, 4, 1);call write~init~int(10, 68, 5, 1);call write~init~int(0, 68, 6, 1);call #Ultimate.allocInit(11, 69);call #Ultimate.allocInit(13, 70);call #Ultimate.allocInit(13, 71);call #Ultimate.allocInit(12, 72);call #Ultimate.allocInit(12, 73);call #Ultimate.allocInit(20, 74);call #Ultimate.allocInit(66, 75);call #Ultimate.allocInit(41, 76);call #Ultimate.allocInit(69, 77);call #Ultimate.allocInit(51, 78);call #Ultimate.allocInit(32, 79);call #Ultimate.allocInit(49, 80);call #Ultimate.allocInit(18, 81);call #Ultimate.allocInit(30, 82);call #Ultimate.allocInit(7, 83);call write~init~int(73, 83, 0, 1);call write~init~int(83, 83, 1, 1);call write~init~int(73, 83, 2, 1);call write~init~int(67, 83, 3, 1);call write~init~int(111, 83, 4, 1);call write~init~int(109, 83, 5, 1);call write~init~int(0, 83, 6, 1);call #Ultimate.allocInit(58, 84);call #Ultimate.allocInit(7, 85);call write~init~int(73, 85, 0, 1);call write~init~int(83, 85, 1, 1);call write~init~int(73, 85, 2, 1);call write~init~int(67, 85, 3, 1);call write~init~int(111, 85, 4, 1);call write~init~int(109, 85, 5, 1);call write~init~int(0, 85, 6, 1);call #Ultimate.allocInit(63, 86);call #Ultimate.allocInit(35, 87);call #Ultimate.allocInit(5, 88);call write~init~int(116, 88, 0, 1);call write~init~int(116, 88, 1, 1);call write~init~int(121, 88, 2, 1);call write~init~int(77, 88, 3, 1);call write~init~int(0, 88, 4, 1);call #Ultimate.allocInit(7, 89);call write~init~int(105, 89, 0, 1);call write~init~int(115, 89, 1, 1);call write~init~int(105, 89, 2, 1);call write~init~int(99, 89, 3, 1);call write~init~int(111, 89, 4, 1);call write~init~int(109, 89, 5, 1);call write~init~int(0, 89, 6, 1);call #Ultimate.allocInit(12, 90);call #Ultimate.allocInit(210, 91);call #Ultimate.allocInit(37, 92);call #Ultimate.allocInit(45, 93);call #Ultimate.allocInit(7, 94);call write~init~int(105, 94, 0, 1);call write~init~int(115, 94, 1, 1);call write~init~int(105, 94, 2, 1);call write~init~int(99, 94, 3, 1);call write~init~int(111, 94, 4, 1);call write~init~int(109, 94, 5, 1);call write~init~int(0, 94, 6, 1);call #Ultimate.allocInit(41, 95);~ldv_irq_1_3~0 := 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_0~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~ldv_state_variable_5~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~isicom_ops_group1~0.base, ~isicom_ops_group1~0.offset := 0, 0;~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~isicom_ops_group0~0.base, ~isicom_ops_group0~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_line_1_3~0 := 0;~isicom_port_ops_group1~0.base, ~isicom_port_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~ldv_state_variable_4~0 := 0;~isicom_driver_group0~0.base, ~isicom_driver_group0~0.offset := 0, 0;~#isicom_pci_tbl~0.base, ~#isicom_pci_tbl~0.offset := 96, 0;call #Ultimate.allocInit(320, 96);call write~init~int(4277, ~#isicom_pci_tbl~0.base, ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8232, ~#isicom_pci_tbl~0.base, 4 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 8 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 12 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 16 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 20 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 24 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 32 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8273, ~#isicom_pci_tbl~0.base, 36 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 40 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 44 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 48 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 52 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 56 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 64 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8274, ~#isicom_pci_tbl~0.base, 68 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 72 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 76 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 80 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 84 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 88 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 96 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8275, ~#isicom_pci_tbl~0.base, 100 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 104 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 108 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 112 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 116 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 120 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 128 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8276, ~#isicom_pci_tbl~0.base, 132 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 136 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 140 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 144 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 148 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 152 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 160 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8277, ~#isicom_pci_tbl~0.base, 164 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 168 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 172 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 176 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 180 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 184 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 192 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8278, ~#isicom_pci_tbl~0.base, 196 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 200 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 204 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 208 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 212 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 216 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 224 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8279, ~#isicom_pci_tbl~0.base, 228 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 232 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 236 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 240 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 244 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 248 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 256 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8280, ~#isicom_pci_tbl~0.base, 260 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 264 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 268 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 272 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 276 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 280 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(0, ~#isicom_pci_tbl~0.base, 288 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 292 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 296 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 300 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 304 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 308 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 312 + ~#isicom_pci_tbl~0.offset, 8);~__mod_pci__isicom_pci_tbl_device_table~0.vendor := 0;~__mod_pci__isicom_pci_tbl_device_table~0.device := 0;~__mod_pci__isicom_pci_tbl_device_table~0.subvendor := 0;~__mod_pci__isicom_pci_tbl_device_table~0.subdevice := 0;~__mod_pci__isicom_pci_tbl_device_table~0.class := 0;~__mod_pci__isicom_pci_tbl_device_table~0.class_mask := 0;~__mod_pci__isicom_pci_tbl_device_table~0.driver_data := 0;~#isicom_driver~0.base, ~#isicom_driver~0.offset := 97, 0;call #Ultimate.allocInit(301, 97);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 8 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(3, 0, ~#isicom_driver~0.base, 16 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(~#isicom_pci_tbl~0.base, ~#isicom_pci_tbl~0.offset, ~#isicom_driver~0.base, 24 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_probe.base, #funAddr~isicom_probe.offset, ~#isicom_driver~0.base, 32 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_remove.base, #funAddr~isicom_remove.offset, ~#isicom_driver~0.base, 40 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 48 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 56 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 64 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 72 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 80 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 88 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 96 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 104 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 112 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 120 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 128 + ~#isicom_driver~0.offset, 8);call write~init~int(0, ~#isicom_driver~0.base, 136 + ~#isicom_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 137 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 145 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 153 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 161 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 169 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 177 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 185 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 193 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 201 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 209 + ~#isicom_driver~0.offset, 8);call write~init~int(0, ~#isicom_driver~0.base, 217 + ~#isicom_driver~0.offset, 4);call write~init~int(0, ~#isicom_driver~0.base, 221 + ~#isicom_driver~0.offset, 4);call write~init~int(0, ~#isicom_driver~0.base, 225 + ~#isicom_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 229 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 237 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 245 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 253 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 261 + ~#isicom_driver~0.offset, 8);call write~init~int(0, ~#isicom_driver~0.base, 269 + ~#isicom_driver~0.offset, 4);call write~init~int(0, ~#isicom_driver~0.base, 273 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 285 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 293 + ~#isicom_driver~0.offset, 8);~prev_card~0 := 3;~isicom_normal~0.base, ~isicom_normal~0.offset := 0, 0;~#tx~0.base, ~#tx~0.offset := 98, 0;call #Ultimate.allocInit(124, 98);call write~init~$Pointer$(0, 0, ~#tx~0.base, ~#tx~0.offset, 8);call write~init~$Pointer$(0, 1953723489, ~#tx~0.base, 8 + ~#tx~0.offset, 8);call write~init~int(0, ~#tx~0.base, 16 + ~#tx~0.offset, 8);call write~init~$Pointer$(~#boot_tvec_bases~0.base, ~#boot_tvec_bases~0.offset, ~#tx~0.base, 24 + ~#tx~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_tx.base, #funAddr~isicom_tx.offset, ~#tx~0.base, 32 + ~#tx~0.offset, 8);call write~init~int(0, ~#tx~0.base, 40 + ~#tx~0.offset, 8);call write~init~int(-1, ~#tx~0.base, 48 + ~#tx~0.offset, 4);call write~init~int(0, ~#tx~0.base, 52 + ~#tx~0.offset, 4);call write~init~$Pointer$(0, 0, ~#tx~0.base, 56 + ~#tx~0.offset, 8);call write~init~int(0, ~#tx~0.base, 64 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 65 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 66 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 67 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 68 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 69 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 70 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 71 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 72 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 73 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 74 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 75 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 76 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 77 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 78 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 79 + ~#tx~0.offset, 1);call write~init~$Pointer$(4, 0, ~#tx~0.base, 80 + ~#tx~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tx~0.base, 88 + ~#tx~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tx~0.base, 96 + ~#tx~0.offset, 8);call write~init~$Pointer$(5, 0, ~#tx~0.base, 104 + ~#tx~0.offset, 8);call write~init~int(0, ~#tx~0.base, 112 + ~#tx~0.offset, 4);call write~init~int(0, ~#tx~0.base, 116 + ~#tx~0.offset, 8);~#linuxb_to_isib~0.base, ~#linuxb_to_isib~0.offset := 99, 0;call #Ultimate.allocInit(20, 99);call write~init~int(-1, ~#linuxb_to_isib~0.base, ~#linuxb_to_isib~0.offset, 1);call write~init~int(0, ~#linuxb_to_isib~0.base, 1 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(1, ~#linuxb_to_isib~0.base, 2 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(2, ~#linuxb_to_isib~0.base, 3 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(3, ~#linuxb_to_isib~0.base, 4 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(4, ~#linuxb_to_isib~0.base, 5 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(5, ~#linuxb_to_isib~0.base, 6 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(6, ~#linuxb_to_isib~0.base, 7 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(7, ~#linuxb_to_isib~0.base, 8 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(8, ~#linuxb_to_isib~0.base, 9 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(9, ~#linuxb_to_isib~0.base, 10 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(11, ~#linuxb_to_isib~0.base, 11 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(13, ~#linuxb_to_isib~0.base, 12 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(15, ~#linuxb_to_isib~0.base, 13 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(16, ~#linuxb_to_isib~0.base, 14 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(17, ~#linuxb_to_isib~0.base, 15 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(18, ~#linuxb_to_isib~0.base, 16 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(19, ~#linuxb_to_isib~0.base, 17 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(20, ~#linuxb_to_isib~0.base, 18 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(21, ~#linuxb_to_isib~0.base, 19 + ~#linuxb_to_isib~0.offset, 1);~#isi_card~0.base, ~#isi_card~0.offset := 100, 0;call #Ultimate.allocInit(432, 100);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#isi_card~0.base);#memory_$Pointer$.base, #memory_$Pointer$.offset := ~initToZeroAtPointerBaseAddress~$Pointer$.base(#memory_$Pointer$.base, #memory_$Pointer$.offset, ~#isi_card~0.base), ~initToZeroAtPointerBaseAddress~$Pointer$.offset(#memory_$Pointer$.base, #memory_$Pointer$.offset, ~#isi_card~0.base);~#isi_ports~0.base, ~#isi_ports~0.offset := 101, 0;call #Ultimate.allocInit(65792, 101);#memory_$Pointer$.base, #memory_$Pointer$.offset := ~initToZeroAtPointerBaseAddress~$Pointer$.base(#memory_$Pointer$.base, #memory_$Pointer$.offset, ~#isi_ports~0.base), ~initToZeroAtPointerBaseAddress~$Pointer$.offset(#memory_$Pointer$.base, #memory_$Pointer$.offset, ~#isi_ports~0.base);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#isi_ports~0.base);~#isicom_ops~0.base, ~#isicom_ops~0.offset := 102, 0;call #Ultimate.allocInit(272, 102);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 8 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 16 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_open.base, #funAddr~isicom_open.offset, ~#isicom_ops~0.base, 24 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_close.base, #funAddr~isicom_close.offset, ~#isicom_ops~0.base, 32 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 40 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 48 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_write.base, #funAddr~isicom_write.offset, ~#isicom_ops~0.base, 56 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_put_char.base, #funAddr~isicom_put_char.offset, ~#isicom_ops~0.base, 64 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_flush_chars.base, #funAddr~isicom_flush_chars.offset, ~#isicom_ops~0.base, 72 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_write_room.base, #funAddr~isicom_write_room.offset, ~#isicom_ops~0.base, 80 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_chars_in_buffer.base, #funAddr~isicom_chars_in_buffer.offset, ~#isicom_ops~0.base, 88 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_ioctl.base, #funAddr~isicom_ioctl.offset, ~#isicom_ops~0.base, 96 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 104 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_set_termios.base, #funAddr~isicom_set_termios.offset, ~#isicom_ops~0.base, 112 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_throttle.base, #funAddr~isicom_throttle.offset, ~#isicom_ops~0.base, 120 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_unthrottle.base, #funAddr~isicom_unthrottle.offset, ~#isicom_ops~0.base, 128 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_stop.base, #funAddr~isicom_stop.offset, ~#isicom_ops~0.base, 136 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_start.base, #funAddr~isicom_start.offset, ~#isicom_ops~0.base, 144 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_hangup.base, #funAddr~isicom_hangup.offset, ~#isicom_ops~0.base, 152 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_send_break.base, #funAddr~isicom_send_break.offset, ~#isicom_ops~0.base, 160 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_flush_buffer.base, #funAddr~isicom_flush_buffer.offset, ~#isicom_ops~0.base, 168 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 176 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 184 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 192 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_tiocmget.base, #funAddr~isicom_tiocmget.offset, ~#isicom_ops~0.base, 200 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_tiocmset.base, #funAddr~isicom_tiocmset.offset, ~#isicom_ops~0.base, 208 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 216 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 224 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 232 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 240 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 248 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 256 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 264 + ~#isicom_ops~0.offset, 8);~#isicom_port_ops~0.base, ~#isicom_port_ops~0.offset := 103, 0;call #Ultimate.allocInit(40, 103);call write~init~$Pointer$(#funAddr~isicom_carrier_raised.base, #funAddr~isicom_carrier_raised.offset, ~#isicom_port_ops~0.base, ~#isicom_port_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_dtr_rts.base, #funAddr~isicom_dtr_rts.offset, ~#isicom_port_ops~0.base, 8 + ~#isicom_port_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_shutdown.base, #funAddr~isicom_shutdown.offset, ~#isicom_port_ops~0.base, 16 + ~#isicom_port_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_activate.base, #funAddr~isicom_activate.offset, ~#isicom_port_ops~0.base, 24 + ~#isicom_port_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_port_ops~0.base, 32 + ~#isicom_port_ops~0.offset, 8);~card_count~0 := 0;~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_retval_3~0 := 0;~ldv_spin~0 := 0; {1367#true} is VALID [2022-02-20 22:02:13,557 INFO L290 TraceCheckUtils]: 1: Hoare triple {1367#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet658#1, main_#t~nondet659#1, main_#t~ret660#1.base, main_#t~ret660#1.offset, main_#t~nondet661#1, main_#t~nondet662#1, main_#t~nondet663#1, main_#t~ret664#1.base, main_#t~ret664#1.offset, main_#t~nondet665#1, main_#t~nondet666#1, main_#t~nondet667#1, main_#t~nondet668#1, main_#t~ret669#1.base, main_#t~ret669#1.offset, main_#t~ret670#1.base, main_#t~ret670#1.offset, main_#t~nondet671#1, main_#t~switch672#1, main_#t~nondet673#1, main_#t~switch674#1, main_#t~nondet675#1, main_#t~switch676#1, main_#t~ret677#1, main_#t~nondet678#1, main_#t~switch679#1, main_#t~ret680#1, main_#t~ret681#1, main_#t~ret682#1, main_#t~ret683#1, main_#t~ret684#1, main_#t~ret685#1, main_#t~ret686#1, main_#t~ret687#1, main_#t~ret688#1, main_#t~ret689#1, main_#t~ret690#1, main_#t~ret691#1, main_#t~ret692#1, main_#t~ret693#1, main_#t~ret694#1, main_#t~ret695#1, main_#t~ret696#1, main_#t~ret697#1, main_#t~ret698#1, main_#t~ret699#1, main_#t~ret700#1, main_#t~ret701#1, main_#t~ret702#1, main_#t~ret703#1, main_#t~ret704#1, main_#t~ret705#1, main_#t~ret706#1, main_#t~ret707#1, main_#t~ret708#1, main_#t~ret709#1, main_#t~ret710#1, main_#t~ret711#1, main_#t~ret712#1, main_#t~ret713#1, main_#t~ret714#1, main_#t~ret715#1, main_#t~ret716#1, main_#t~ret717#1, main_#t~ret718#1, main_#t~ret719#1, main_#t~ret720#1, main_#t~ret721#1, main_#t~nondet722#1, main_#t~switch723#1, main_#t~ret724#1, main_#t~ret725#1, main_#t~ret726#1, main_#t~ret727#1, main_#t~ret728#1, main_#t~nondet729#1, main_#t~switch730#1, main_#t~ret731#1, main_~ldvarg0~0#1, main_~tmp~41#1, main_~ldvarg7~0#1, main_~tmp___0~17#1, main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset, main_~tmp___1~10#1.base, main_~tmp___1~10#1.offset, main_~ldvarg5~0#1, main_~tmp___2~8#1, main_~ldvarg6~0#1, main_~tmp___3~5#1, main_~ldvarg1~0#1, main_~tmp___4~3#1, main_~ldvarg8~0#1.base, main_~ldvarg8~0#1.offset, main_~tmp___5~2#1.base, main_~tmp___5~2#1.offset, main_~ldvarg4~0#1, main_~tmp___6~2#1, main_~ldvarg9~0#1, main_~tmp___7~2#1, main_~ldvarg2~0#1, main_~tmp___8~1#1, main_~ldvarg11~0#1, main_~tmp___9~0#1, main_~ldvarg10~0#1.base, main_~ldvarg10~0#1.offset, main_~tmp___10~0#1.base, main_~tmp___10~0#1.offset, main_~ldvarg12~0#1.base, main_~ldvarg12~0#1.offset, main_~tmp___11~0#1.base, main_~tmp___11~0#1.offset, main_~tmp___12~0#1, main_~tmp___13~0#1, main_~tmp___14~0#1, main_~tmp___15~0#1, main_~tmp___16~0#1, main_~tmp___17~0#1;havoc main_~ldvarg0~0#1;havoc main_~tmp~41#1;havoc main_~ldvarg7~0#1;havoc main_~tmp___0~17#1;havoc main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset;havoc main_~tmp___1~10#1.base, main_~tmp___1~10#1.offset;havoc main_~ldvarg5~0#1;havoc main_~tmp___2~8#1;havoc main_~ldvarg6~0#1;havoc main_~tmp___3~5#1;havoc main_~ldvarg1~0#1;havoc main_~tmp___4~3#1;havoc main_~ldvarg8~0#1.base, main_~ldvarg8~0#1.offset;havoc main_~tmp___5~2#1.base, main_~tmp___5~2#1.offset;havoc main_~ldvarg4~0#1;havoc main_~tmp___6~2#1;havoc main_~ldvarg9~0#1;havoc main_~tmp___7~2#1;havoc main_~ldvarg2~0#1;havoc main_~tmp___8~1#1;havoc main_~ldvarg11~0#1;havoc main_~tmp___9~0#1;havoc main_~ldvarg10~0#1.base, main_~ldvarg10~0#1.offset;havoc main_~tmp___10~0#1.base, main_~tmp___10~0#1.offset;havoc main_~ldvarg12~0#1.base, main_~ldvarg12~0#1.offset;havoc main_~tmp___11~0#1.base, main_~tmp___11~0#1.offset;havoc main_~tmp___12~0#1;havoc main_~tmp___13~0#1;havoc main_~tmp___14~0#1;havoc main_~tmp___15~0#1;havoc main_~tmp___16~0#1;havoc main_~tmp___17~0#1;main_~tmp~41#1 := main_#t~nondet658#1;havoc main_#t~nondet658#1;main_~ldvarg0~0#1 := main_~tmp~41#1;main_~tmp___0~17#1 := main_#t~nondet659#1;havoc main_#t~nondet659#1;main_~ldvarg7~0#1 := main_~tmp___0~17#1; {1367#true} is VALID [2022-02-20 22:02:13,558 INFO L272 TraceCheckUtils]: 2: Hoare triple {1367#true} call main_#t~ret660#1.base, main_#t~ret660#1.offset := ldv_zalloc(1); {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:13,558 INFO L290 TraceCheckUtils]: 3: Hoare triple {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {1367#true} is VALID [2022-02-20 22:02:13,559 INFO L290 TraceCheckUtils]: 4: Hoare triple {1367#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {1367#true} is VALID [2022-02-20 22:02:13,559 INFO L290 TraceCheckUtils]: 5: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,559 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {1367#true} {1367#true} #3596#return; {1367#true} is VALID [2022-02-20 22:02:13,559 INFO L290 TraceCheckUtils]: 7: Hoare triple {1367#true} main_~tmp___1~10#1.base, main_~tmp___1~10#1.offset := main_#t~ret660#1.base, main_#t~ret660#1.offset;havoc main_#t~ret660#1.base, main_#t~ret660#1.offset;main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset := main_~tmp___1~10#1.base, main_~tmp___1~10#1.offset;main_~tmp___2~8#1 := main_#t~nondet661#1;havoc main_#t~nondet661#1;main_~ldvarg5~0#1 := main_~tmp___2~8#1;main_~tmp___3~5#1 := main_#t~nondet662#1;havoc main_#t~nondet662#1;main_~ldvarg6~0#1 := main_~tmp___3~5#1;assume -2147483648 <= main_#t~nondet663#1 && main_#t~nondet663#1 <= 2147483647;main_~tmp___4~3#1 := main_#t~nondet663#1;havoc main_#t~nondet663#1;main_~ldvarg1~0#1 := main_~tmp___4~3#1; {1367#true} is VALID [2022-02-20 22:02:13,560 INFO L272 TraceCheckUtils]: 8: Hoare triple {1367#true} call main_#t~ret664#1.base, main_#t~ret664#1.offset := ldv_zalloc(44); {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:13,560 INFO L290 TraceCheckUtils]: 9: Hoare triple {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {1367#true} is VALID [2022-02-20 22:02:13,560 INFO L290 TraceCheckUtils]: 10: Hoare triple {1367#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {1367#true} is VALID [2022-02-20 22:02:13,560 INFO L290 TraceCheckUtils]: 11: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,560 INFO L284 TraceCheckUtils]: 12: Hoare quadruple {1367#true} {1367#true} #3598#return; {1367#true} is VALID [2022-02-20 22:02:13,561 INFO L290 TraceCheckUtils]: 13: Hoare triple {1367#true} main_~tmp___5~2#1.base, main_~tmp___5~2#1.offset := main_#t~ret664#1.base, main_#t~ret664#1.offset;havoc main_#t~ret664#1.base, main_#t~ret664#1.offset;main_~ldvarg8~0#1.base, main_~ldvarg8~0#1.offset := main_~tmp___5~2#1.base, main_~tmp___5~2#1.offset;main_~tmp___6~2#1 := main_#t~nondet665#1;havoc main_#t~nondet665#1;main_~ldvarg4~0#1 := main_~tmp___6~2#1;main_~tmp___7~2#1 := main_#t~nondet666#1;havoc main_#t~nondet666#1;main_~ldvarg9~0#1 := main_~tmp___7~2#1;assume -2147483648 <= main_#t~nondet667#1 && main_#t~nondet667#1 <= 2147483647;main_~tmp___8~1#1 := main_#t~nondet667#1;havoc main_#t~nondet667#1;main_~ldvarg2~0#1 := main_~tmp___8~1#1;assume -2147483648 <= main_#t~nondet668#1 && main_#t~nondet668#1 <= 2147483647;main_~tmp___9~0#1 := main_#t~nondet668#1;havoc main_#t~nondet668#1;main_~ldvarg11~0#1 := main_~tmp___9~0#1; {1367#true} is VALID [2022-02-20 22:02:13,561 INFO L272 TraceCheckUtils]: 14: Hoare triple {1367#true} call main_#t~ret669#1.base, main_#t~ret669#1.offset := ldv_zalloc(1752); {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:13,562 INFO L290 TraceCheckUtils]: 15: Hoare triple {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {1367#true} is VALID [2022-02-20 22:02:13,562 INFO L290 TraceCheckUtils]: 16: Hoare triple {1367#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {1367#true} is VALID [2022-02-20 22:02:13,562 INFO L290 TraceCheckUtils]: 17: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,562 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {1367#true} {1367#true} #3600#return; {1367#true} is VALID [2022-02-20 22:02:13,562 INFO L290 TraceCheckUtils]: 19: Hoare triple {1367#true} main_~tmp___10~0#1.base, main_~tmp___10~0#1.offset := main_#t~ret669#1.base, main_#t~ret669#1.offset;havoc main_#t~ret669#1.base, main_#t~ret669#1.offset;main_~ldvarg10~0#1.base, main_~ldvarg10~0#1.offset := main_~tmp___10~0#1.base, main_~tmp___10~0#1.offset; {1367#true} is VALID [2022-02-20 22:02:13,563 INFO L272 TraceCheckUtils]: 20: Hoare triple {1367#true} call main_#t~ret670#1.base, main_#t~ret670#1.offset := ldv_zalloc(32); {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:13,563 INFO L290 TraceCheckUtils]: 21: Hoare triple {1470#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {1367#true} is VALID [2022-02-20 22:02:13,563 INFO L290 TraceCheckUtils]: 22: Hoare triple {1367#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {1367#true} is VALID [2022-02-20 22:02:13,564 INFO L290 TraceCheckUtils]: 23: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,564 INFO L284 TraceCheckUtils]: 24: Hoare quadruple {1367#true} {1367#true} #3602#return; {1367#true} is VALID [2022-02-20 22:02:13,564 INFO L290 TraceCheckUtils]: 25: Hoare triple {1367#true} main_~tmp___11~0#1.base, main_~tmp___11~0#1.offset := main_#t~ret670#1.base, main_#t~ret670#1.offset;havoc main_#t~ret670#1.base, main_#t~ret670#1.offset;main_~ldvarg12~0#1.base, main_~ldvarg12~0#1.offset := main_~tmp___11~0#1.base, main_~tmp___11~0#1.offset;assume { :begin_inline_ldv_initialize } true; {1367#true} is VALID [2022-02-20 22:02:13,573 INFO L290 TraceCheckUtils]: 26: Hoare triple {1367#true} assume { :end_inline_ldv_initialize } true;~ldv_state_variable_4~0 := 0;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_state_variable_5~0 := 0; {1385#(= ~ldv_state_variable_5~0 0)} is VALID [2022-02-20 22:02:13,574 INFO L290 TraceCheckUtils]: 27: Hoare triple {1385#(= ~ldv_state_variable_5~0 0)} assume -2147483648 <= main_#t~nondet671#1 && main_#t~nondet671#1 <= 2147483647;main_~tmp___12~0#1 := main_#t~nondet671#1;havoc main_#t~nondet671#1;main_#t~switch672#1 := 0 == main_~tmp___12~0#1; {1385#(= ~ldv_state_variable_5~0 0)} is VALID [2022-02-20 22:02:13,574 INFO L290 TraceCheckUtils]: 28: Hoare triple {1385#(= ~ldv_state_variable_5~0 0)} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 1 == main_~tmp___12~0#1; {1385#(= ~ldv_state_variable_5~0 0)} is VALID [2022-02-20 22:02:13,574 INFO L290 TraceCheckUtils]: 29: Hoare triple {1385#(= ~ldv_state_variable_5~0 0)} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 2 == main_~tmp___12~0#1; {1385#(= ~ldv_state_variable_5~0 0)} is VALID [2022-02-20 22:02:13,575 INFO L290 TraceCheckUtils]: 30: Hoare triple {1385#(= ~ldv_state_variable_5~0 0)} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 3 == main_~tmp___12~0#1; {1385#(= ~ldv_state_variable_5~0 0)} is VALID [2022-02-20 22:02:13,575 INFO L290 TraceCheckUtils]: 31: Hoare triple {1385#(= ~ldv_state_variable_5~0 0)} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 4 == main_~tmp___12~0#1; {1385#(= ~ldv_state_variable_5~0 0)} is VALID [2022-02-20 22:02:13,576 INFO L290 TraceCheckUtils]: 32: Hoare triple {1385#(= ~ldv_state_variable_5~0 0)} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 5 == main_~tmp___12~0#1; {1385#(= ~ldv_state_variable_5~0 0)} is VALID [2022-02-20 22:02:13,576 INFO L290 TraceCheckUtils]: 33: Hoare triple {1385#(= ~ldv_state_variable_5~0 0)} assume main_#t~switch672#1; {1385#(= ~ldv_state_variable_5~0 0)} is VALID [2022-02-20 22:02:13,576 INFO L290 TraceCheckUtils]: 34: Hoare triple {1385#(= ~ldv_state_variable_5~0 0)} assume 0 != ~ldv_state_variable_5~0;assume -2147483648 <= main_#t~nondet729#1 && main_#t~nondet729#1 <= 2147483647;main_~tmp___17~0#1 := main_#t~nondet729#1;havoc main_#t~nondet729#1;main_#t~switch730#1 := 0 == main_~tmp___17~0#1; {1368#false} is VALID [2022-02-20 22:02:13,576 INFO L290 TraceCheckUtils]: 35: Hoare triple {1368#false} assume main_#t~switch730#1; {1368#false} is VALID [2022-02-20 22:02:13,577 INFO L290 TraceCheckUtils]: 36: Hoare triple {1368#false} assume 1 == ~ldv_state_variable_5~0;assume { :begin_inline_isicom_probe } true;isicom_probe_#in~pdev#1.base, isicom_probe_#in~pdev#1.offset, isicom_probe_#in~ent#1.base, isicom_probe_#in~ent#1.offset := ~isicom_driver_group0~0.base, ~isicom_driver_group0~0.offset, main_~ldvarg12~0#1.base, main_~ldvarg12~0#1.offset;havoc isicom_probe_#res#1;havoc isicom_probe_#t~mem577#1, isicom_probe_#t~ret578#1, isicom_probe_#t~nondet579#1, isicom_probe_#t~nondet580#1, isicom_probe_#t~mem581#1, isicom_probe_#t~mem582#1, isicom_probe_#t~mem583#1, isicom_probe_#t~mem584#1, isicom_probe_#t~ret585#1, isicom_probe_#t~nondet586#1, isicom_probe_#t~mem587#1, isicom_probe_#t~mem588#1, isicom_probe_#t~mem589#1, isicom_probe_#t~ret590#1, isicom_probe_#t~nondet591#1, isicom_probe_#t~mem592#1, isicom_probe_#t~ret593#1, isicom_probe_#t~mem594#1, isicom_probe_#t~ret595#1, isicom_probe_#t~mem596#1.base, isicom_probe_#t~mem596#1.offset, isicom_probe_#t~mem597#1, isicom_probe_#t~ret598#1.base, isicom_probe_#t~ret598#1.offset, isicom_probe_#t~mem599#1, isicom_probe_#t~mem600#1, isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, isicom_probe_~ent#1.base, isicom_probe_~ent#1.offset, isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset, isicom_probe_~index~0#1, isicom_probe_~retval~2#1, isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset, isicom_probe_~tport~1#1.base, isicom_probe_~tport~1#1.offset;isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset := isicom_probe_#in~pdev#1.base, isicom_probe_#in~pdev#1.offset;isicom_probe_~ent#1.base, isicom_probe_~ent#1.offset := isicom_probe_#in~ent#1.base, isicom_probe_#in~ent#1.offset;call isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset := #Ultimate.allocOnStack(4);havoc isicom_probe_~index~0#1;havoc isicom_probe_~retval~2#1;havoc isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset;havoc isicom_probe_~tport~1#1.base, isicom_probe_~tport~1#1.offset;call isicom_probe_#t~mem577#1 := read~int(isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset, 4);call write~int(isicom_probe_#t~mem577#1, isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset, 4);havoc isicom_probe_#t~mem577#1;isicom_probe_~retval~2#1 := -1;isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset := 0, 0; {1368#false} is VALID [2022-02-20 22:02:13,578 INFO L290 TraceCheckUtils]: 37: Hoare triple {1368#false} assume !(~card_count~0 % 4294967296 > 3);assume { :begin_inline_pci_enable_device } true;pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset;havoc pci_enable_device_#res#1;havoc pci_enable_device_#t~nondet756#1, pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset;pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset := pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset;assume -2147483648 <= pci_enable_device_#t~nondet756#1 && pci_enable_device_#t~nondet756#1 <= 2147483647;pci_enable_device_#res#1 := pci_enable_device_#t~nondet756#1;havoc pci_enable_device_#t~nondet756#1; {1368#false} is VALID [2022-02-20 22:02:13,578 INFO L290 TraceCheckUtils]: 38: Hoare triple {1368#false} isicom_probe_#t~ret578#1 := pci_enable_device_#res#1;assume { :end_inline_pci_enable_device } true;assume -2147483648 <= isicom_probe_#t~ret578#1 && isicom_probe_#t~ret578#1 <= 2147483647;isicom_probe_~retval~2#1 := isicom_probe_#t~ret578#1;havoc isicom_probe_#t~ret578#1; {1368#false} is VALID [2022-02-20 22:02:13,578 INFO L290 TraceCheckUtils]: 39: Hoare triple {1368#false} assume !(0 != isicom_probe_~retval~2#1);havoc isicom_probe_#t~nondet580#1;call isicom_probe_#t~mem581#1 := read~int(isicom_probe_~ent#1.base, 4 + isicom_probe_~ent#1.offset, 4);havoc isicom_probe_#t~mem581#1;isicom_probe_~index~0#1 := 0; {1368#false} is VALID [2022-02-20 22:02:13,578 INFO L290 TraceCheckUtils]: 40: Hoare triple {1368#false} assume !(isicom_probe_~index~0#1 % 4294967296 <= 3); {1368#false} is VALID [2022-02-20 22:02:13,579 INFO L290 TraceCheckUtils]: 41: Hoare triple {1368#false} assume !(4 == isicom_probe_~index~0#1 % 4294967296);call write~int(isicom_probe_~index~0#1, isicom_probe_~board~3#1.base, 104 + isicom_probe_~board~3#1.offset, 4);call isicom_probe_#t~mem583#1 := read~int(isicom_probe_~pdev#1.base, 1668 + isicom_probe_~pdev#1.offset, 8);call write~int(isicom_probe_#t~mem583#1, isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset, 8);havoc isicom_probe_#t~mem583#1;call isicom_probe_#t~mem584#1 := read~int(isicom_probe_~pdev#1.base, 1496 + isicom_probe_~pdev#1.offset, 4);call write~int((if isicom_probe_#t~mem584#1 % 4294967296 % 4294967296 <= 2147483647 then isicom_probe_#t~mem584#1 % 4294967296 % 4294967296 else isicom_probe_#t~mem584#1 % 4294967296 % 4294967296 - 4294967296), isicom_probe_~board~3#1.base, 8 + isicom_probe_~board~3#1.offset, 4);havoc isicom_probe_#t~mem584#1;~card_count~0 := 1 + ~card_count~0;assume { :begin_inline_pci_set_drvdata } true;pci_set_drvdata_#in~pdev#1.base, pci_set_drvdata_#in~pdev#1.offset, pci_set_drvdata_#in~data#1.base, pci_set_drvdata_#in~data#1.offset := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset;havoc pci_set_drvdata_~pdev#1.base, pci_set_drvdata_~pdev#1.offset, pci_set_drvdata_~data#1.base, pci_set_drvdata_~data#1.offset;pci_set_drvdata_~pdev#1.base, pci_set_drvdata_~pdev#1.offset := pci_set_drvdata_#in~pdev#1.base, pci_set_drvdata_#in~pdev#1.offset;pci_set_drvdata_~data#1.base, pci_set_drvdata_~data#1.offset := pci_set_drvdata_#in~data#1.base, pci_set_drvdata_#in~data#1.offset;assume { :begin_inline_dev_set_drvdata } true;dev_set_drvdata_#in~dev#1.base, dev_set_drvdata_#in~dev#1.offset, dev_set_drvdata_#in~data#1.base, dev_set_drvdata_#in~data#1.offset := pci_set_drvdata_~pdev#1.base, 147 + pci_set_drvdata_~pdev#1.offset, pci_set_drvdata_~data#1.base, pci_set_drvdata_~data#1.offset;havoc dev_set_drvdata_~dev#1.base, dev_set_drvdata_~dev#1.offset, dev_set_drvdata_~data#1.base, dev_set_drvdata_~data#1.offset;dev_set_drvdata_~dev#1.base, dev_set_drvdata_~dev#1.offset := dev_set_drvdata_#in~dev#1.base, dev_set_drvdata_#in~dev#1.offset;dev_set_drvdata_~data#1.base, dev_set_drvdata_~data#1.offset := dev_set_drvdata_#in~data#1.base, dev_set_drvdata_#in~data#1.offset;call write~$Pointer$(dev_set_drvdata_~data#1.base, dev_set_drvdata_~data#1.offset, dev_set_drvdata_~dev#1.base, 489 + dev_set_drvdata_~dev#1.offset, 8); {1368#false} is VALID [2022-02-20 22:02:13,579 INFO L290 TraceCheckUtils]: 42: Hoare triple {1368#false} assume { :end_inline_dev_set_drvdata } true; {1368#false} is VALID [2022-02-20 22:02:13,579 INFO L290 TraceCheckUtils]: 43: Hoare triple {1368#false} assume { :end_inline_pci_set_drvdata } true;assume { :begin_inline_pci_request_region } true;pci_request_region_#in~arg0#1.base, pci_request_region_#in~arg0#1.offset, pci_request_region_#in~arg1#1, pci_request_region_#in~arg2#1.base, pci_request_region_#in~arg2#1.offset := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, 3, 83, 0;havoc pci_request_region_#res#1;havoc pci_request_region_#t~nondet757#1, pci_request_region_~arg0#1.base, pci_request_region_~arg0#1.offset, pci_request_region_~arg1#1, pci_request_region_~arg2#1.base, pci_request_region_~arg2#1.offset;pci_request_region_~arg0#1.base, pci_request_region_~arg0#1.offset := pci_request_region_#in~arg0#1.base, pci_request_region_#in~arg0#1.offset;pci_request_region_~arg1#1 := pci_request_region_#in~arg1#1;pci_request_region_~arg2#1.base, pci_request_region_~arg2#1.offset := pci_request_region_#in~arg2#1.base, pci_request_region_#in~arg2#1.offset;assume -2147483648 <= pci_request_region_#t~nondet757#1 && pci_request_region_#t~nondet757#1 <= 2147483647;pci_request_region_#res#1 := pci_request_region_#t~nondet757#1;havoc pci_request_region_#t~nondet757#1; {1368#false} is VALID [2022-02-20 22:02:13,579 INFO L290 TraceCheckUtils]: 44: Hoare triple {1368#false} isicom_probe_#t~ret585#1 := pci_request_region_#res#1;assume { :end_inline_pci_request_region } true;assume -2147483648 <= isicom_probe_#t~ret585#1 && isicom_probe_#t~ret585#1 <= 2147483647;isicom_probe_~retval~2#1 := isicom_probe_#t~ret585#1;havoc isicom_probe_#t~ret585#1; {1368#false} is VALID [2022-02-20 22:02:13,579 INFO L290 TraceCheckUtils]: 45: Hoare triple {1368#false} assume !(0 != isicom_probe_~retval~2#1);call isicom_probe_#t~mem589#1 := read~int(isicom_probe_~board~3#1.base, 8 + isicom_probe_~board~3#1.offset, 4);assume { :begin_inline_ldv_request_irq_20 } true;ldv_request_irq_20_#in~irq#1, ldv_request_irq_20_#in~handler#1.base, ldv_request_irq_20_#in~handler#1.offset, ldv_request_irq_20_#in~flags#1, ldv_request_irq_20_#in~name#1.base, ldv_request_irq_20_#in~name#1.offset, ldv_request_irq_20_#in~dev#1.base, ldv_request_irq_20_#in~dev#1.offset := isicom_probe_#t~mem589#1, #funAddr~isicom_interrupt.base, #funAddr~isicom_interrupt.offset, 128, 85, 0, isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset;havoc ldv_request_irq_20_#res#1;havoc ldv_request_irq_20_#t~ret733#1, ldv_request_irq_20_#t~ret734#1, ldv_request_irq_20_~irq#1, ldv_request_irq_20_~handler#1.base, ldv_request_irq_20_~handler#1.offset, ldv_request_irq_20_~flags#1, ldv_request_irq_20_~name#1.base, ldv_request_irq_20_~name#1.offset, ldv_request_irq_20_~dev#1.base, ldv_request_irq_20_~dev#1.offset, ldv_request_irq_20_~ldv_func_res~0#1, ldv_request_irq_20_~tmp~42#1, ldv_request_irq_20_~tmp___0~18#1;ldv_request_irq_20_~irq#1 := ldv_request_irq_20_#in~irq#1;ldv_request_irq_20_~handler#1.base, ldv_request_irq_20_~handler#1.offset := ldv_request_irq_20_#in~handler#1.base, ldv_request_irq_20_#in~handler#1.offset;ldv_request_irq_20_~flags#1 := ldv_request_irq_20_#in~flags#1;ldv_request_irq_20_~name#1.base, ldv_request_irq_20_~name#1.offset := ldv_request_irq_20_#in~name#1.base, ldv_request_irq_20_#in~name#1.offset;ldv_request_irq_20_~dev#1.base, ldv_request_irq_20_~dev#1.offset := ldv_request_irq_20_#in~dev#1.base, ldv_request_irq_20_#in~dev#1.offset;havoc ldv_request_irq_20_~ldv_func_res~0#1;havoc ldv_request_irq_20_~tmp~42#1;havoc ldv_request_irq_20_~tmp___0~18#1;assume { :begin_inline_request_irq } true;request_irq_#in~irq#1, request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset, request_irq_#in~flags#1, request_irq_#in~name#1.base, request_irq_#in~name#1.offset, request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset := ldv_request_irq_20_~irq#1, ldv_request_irq_20_~handler#1.base, ldv_request_irq_20_~handler#1.offset, ldv_request_irq_20_~flags#1, ldv_request_irq_20_~name#1.base, ldv_request_irq_20_~name#1.offset, ldv_request_irq_20_~dev#1.base, ldv_request_irq_20_~dev#1.offset;havoc request_irq_#res#1;havoc request_irq_#t~ret130#1, request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset, request_irq_~tmp~10#1;request_irq_~irq#1 := request_irq_#in~irq#1;request_irq_~handler#1.base, request_irq_~handler#1.offset := request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset;request_irq_~flags#1 := request_irq_#in~flags#1;request_irq_~name#1.base, request_irq_~name#1.offset := request_irq_#in~name#1.base, request_irq_#in~name#1.offset;request_irq_~dev#1.base, request_irq_~dev#1.offset := request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset;havoc request_irq_~tmp~10#1;assume { :begin_inline_request_threaded_irq } true;request_threaded_irq_#in~arg0#1, request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset, request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset, request_threaded_irq_#in~arg3#1, request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset, request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset := request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, 0, 0, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset;havoc request_threaded_irq_#res#1;havoc request_threaded_irq_#t~nondet760#1, request_threaded_irq_~arg0#1, request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset, request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset, request_threaded_irq_~arg3#1, request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset, request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset;request_threaded_irq_~arg0#1 := request_threaded_irq_#in~arg0#1;request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset := request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset;request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset := request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset;request_threaded_irq_~arg3#1 := request_threaded_irq_#in~arg3#1;request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset := request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset;request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset := request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset;assume -2147483648 <= request_threaded_irq_#t~nondet760#1 && request_threaded_irq_#t~nondet760#1 <= 2147483647;request_threaded_irq_#res#1 := request_threaded_irq_#t~nondet760#1;havoc request_threaded_irq_#t~nondet760#1; {1368#false} is VALID [2022-02-20 22:02:13,580 INFO L290 TraceCheckUtils]: 46: Hoare triple {1368#false} request_irq_#t~ret130#1 := request_threaded_irq_#res#1;assume { :end_inline_request_threaded_irq } true;assume -2147483648 <= request_irq_#t~ret130#1 && request_irq_#t~ret130#1 <= 2147483647;request_irq_~tmp~10#1 := request_irq_#t~ret130#1;havoc request_irq_#t~ret130#1;request_irq_#res#1 := request_irq_~tmp~10#1; {1368#false} is VALID [2022-02-20 22:02:13,580 INFO L290 TraceCheckUtils]: 47: Hoare triple {1368#false} ldv_request_irq_20_#t~ret733#1 := request_irq_#res#1;assume { :end_inline_request_irq } true;assume -2147483648 <= ldv_request_irq_20_#t~ret733#1 && ldv_request_irq_20_#t~ret733#1 <= 2147483647;ldv_request_irq_20_~tmp~42#1 := ldv_request_irq_20_#t~ret733#1;havoc ldv_request_irq_20_#t~ret733#1;ldv_request_irq_20_~ldv_func_res~0#1 := ldv_request_irq_20_~tmp~42#1;assume { :begin_inline_reg_check_1 } true;reg_check_1_#in~handler#1.base, reg_check_1_#in~handler#1.offset := ldv_request_irq_20_~handler#1.base, ldv_request_irq_20_~handler#1.offset;havoc reg_check_1_#res#1;havoc reg_check_1_~handler#1.base, reg_check_1_~handler#1.offset;reg_check_1_~handler#1.base, reg_check_1_~handler#1.offset := reg_check_1_#in~handler#1.base, reg_check_1_#in~handler#1.offset; {1368#false} is VALID [2022-02-20 22:02:13,580 INFO L290 TraceCheckUtils]: 48: Hoare triple {1368#false} assume (reg_check_1_~handler#1.base + reg_check_1_~handler#1.offset) % 18446744073709551616 == (#funAddr~isicom_interrupt.base + #funAddr~isicom_interrupt.offset) % 18446744073709551616;reg_check_1_#res#1 := 1; {1368#false} is VALID [2022-02-20 22:02:13,580 INFO L290 TraceCheckUtils]: 49: Hoare triple {1368#false} ldv_request_irq_20_#t~ret734#1 := reg_check_1_#res#1;assume { :end_inline_reg_check_1 } true;assume -2147483648 <= ldv_request_irq_20_#t~ret734#1 && ldv_request_irq_20_#t~ret734#1 <= 2147483647;ldv_request_irq_20_~tmp___0~18#1 := ldv_request_irq_20_#t~ret734#1;havoc ldv_request_irq_20_#t~ret734#1; {1368#false} is VALID [2022-02-20 22:02:13,580 INFO L290 TraceCheckUtils]: 50: Hoare triple {1368#false} assume !(0 != ldv_request_irq_20_~tmp___0~18#1 && 0 == ldv_request_irq_20_~ldv_func_res~0#1); {1368#false} is VALID [2022-02-20 22:02:13,581 INFO L290 TraceCheckUtils]: 51: Hoare triple {1368#false} ldv_request_irq_20_#res#1 := ldv_request_irq_20_~ldv_func_res~0#1; {1368#false} is VALID [2022-02-20 22:02:13,581 INFO L290 TraceCheckUtils]: 52: Hoare triple {1368#false} isicom_probe_#t~ret590#1 := ldv_request_irq_20_#res#1;assume { :end_inline_ldv_request_irq_20 } true;assume -2147483648 <= isicom_probe_#t~ret590#1 && isicom_probe_#t~ret590#1 <= 2147483647;isicom_probe_~retval~2#1 := isicom_probe_#t~ret590#1;havoc isicom_probe_#t~mem589#1;havoc isicom_probe_#t~ret590#1; {1368#false} is VALID [2022-02-20 22:02:13,581 INFO L290 TraceCheckUtils]: 53: Hoare triple {1368#false} assume !(isicom_probe_~retval~2#1 < 0);assume { :begin_inline_reset_card } true;reset_card_#in~pdev#1.base, reset_card_#in~pdev#1.offset, reset_card_#in~card#1, reset_card_#in~signature#1.base, reset_card_#in~signature#1.offset := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, isicom_probe_~index~0#1, isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset;havoc reset_card_#res#1;havoc reset_card_#t~ret506#1.base, reset_card_#t~ret506#1.offset, reset_card_#t~mem507#1, reset_card_#t~mem508#1, reset_card_#t~ret509#1, reset_card_#t~nondet510#1, reset_card_#t~ret511#1, reset_card_#t~ret512#1, reset_card_#t~nondet514#1, reset_card_#t~mem515#1, reset_card_#t~ret516#1, reset_card_#t~nondet517#1, reset_card_#t~ret518#1, reset_card_#t~ret519#1, reset_card_#t~nondet520#1, reset_card_#t~switch521#1, reset_card_#t~ite522#1, reset_card_#t~nondet523#1, reset_card_#t~nondet513#1, reset_card_~pdev#1.base, reset_card_~pdev#1.offset, reset_card_~card#1, reset_card_~signature#1.base, reset_card_~signature#1.offset, reset_card_~board~1#1.base, reset_card_~board~1#1.offset, reset_card_~tmp~32#1.base, reset_card_~tmp~32#1.offset, reset_card_~base~11#1, reset_card_~sig~0#1, reset_card_~portcount~0#1, reset_card_~retval~0#1, reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset, reset_card_~tmp___0~14#1, reset_card_~tmp___1~8#1, reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset, reset_card_~tmp___2~6#1, reset_card_~tmp___3~3#1, reset_card_~tmp___4~1#1;reset_card_~pdev#1.base, reset_card_~pdev#1.offset := reset_card_#in~pdev#1.base, reset_card_#in~pdev#1.offset;reset_card_~card#1 := reset_card_#in~card#1;reset_card_~signature#1.base, reset_card_~signature#1.offset := reset_card_#in~signature#1.base, reset_card_#in~signature#1.offset;havoc reset_card_~board~1#1.base, reset_card_~board~1#1.offset;havoc reset_card_~tmp~32#1.base, reset_card_~tmp~32#1.offset;havoc reset_card_~base~11#1;havoc reset_card_~sig~0#1;havoc reset_card_~portcount~0#1;havoc reset_card_~retval~0#1;call reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset := #Ultimate.allocOnStack(37);havoc reset_card_~tmp___0~14#1;havoc reset_card_~tmp___1~8#1;call reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset := #Ultimate.allocOnStack(37);havoc reset_card_~tmp___2~6#1;havoc reset_card_~tmp___3~3#1;havoc reset_card_~tmp___4~1#1; {1368#false} is VALID [2022-02-20 22:02:13,581 INFO L272 TraceCheckUtils]: 54: Hoare triple {1368#false} call reset_card_#t~ret506#1.base, reset_card_#t~ret506#1.offset := pci_get_drvdata(reset_card_~pdev#1.base, reset_card_~pdev#1.offset); {1367#true} is VALID [2022-02-20 22:02:13,581 INFO L290 TraceCheckUtils]: 55: Hoare triple {1367#true} ~pdev#1.base, ~pdev#1.offset := #in~pdev#1.base, #in~pdev#1.offset;havoc ~tmp~11#1.base, ~tmp~11#1.offset;assume { :begin_inline_dev_get_drvdata } true;dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset := ~pdev#1.base, 147 + ~pdev#1.offset;havoc dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset, dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset;dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset := dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset;call dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset := read~$Pointer$(dev_get_drvdata_~dev#1.base, 489 + dev_get_drvdata_~dev#1.offset, 8);dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset := dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset; {1367#true} is VALID [2022-02-20 22:02:13,582 INFO L290 TraceCheckUtils]: 56: Hoare triple {1367#true} #t~ret153#1.base, #t~ret153#1.offset := dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;assume { :end_inline_dev_get_drvdata } true;~tmp~11#1.base, ~tmp~11#1.offset := #t~ret153#1.base, #t~ret153#1.offset;havoc #t~ret153#1.base, #t~ret153#1.offset;#res#1.base, #res#1.offset := ~tmp~11#1.base, ~tmp~11#1.offset; {1367#true} is VALID [2022-02-20 22:02:13,582 INFO L290 TraceCheckUtils]: 57: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,582 INFO L284 TraceCheckUtils]: 58: Hoare quadruple {1367#true} {1368#false} #3860#return; {1368#false} is VALID [2022-02-20 22:02:13,582 INFO L290 TraceCheckUtils]: 59: Hoare triple {1368#false} reset_card_~tmp~32#1.base, reset_card_~tmp~32#1.offset := reset_card_#t~ret506#1.base, reset_card_#t~ret506#1.offset;havoc reset_card_#t~ret506#1.base, reset_card_#t~ret506#1.offset;reset_card_~board~1#1.base, reset_card_~board~1#1.offset := reset_card_~tmp~32#1.base, reset_card_~tmp~32#1.offset;call reset_card_#t~mem507#1 := read~int(reset_card_~board~1#1.base, reset_card_~board~1#1.offset, 8);reset_card_~base~11#1 := reset_card_#t~mem507#1;havoc reset_card_#t~mem507#1;reset_card_~portcount~0#1 := 0;reset_card_~retval~0#1 := 0;call write~$Pointer$(56, 0, reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset, 8);call write~$Pointer$(57, 0, reset_card_~#descriptor~3#1.base, 8 + reset_card_~#descriptor~3#1.offset, 8);call write~$Pointer$(58, 0, reset_card_~#descriptor~3#1.base, 16 + reset_card_~#descriptor~3#1.offset, 8);call write~$Pointer$(59, 0, reset_card_~#descriptor~3#1.base, 24 + reset_card_~#descriptor~3#1.offset, 8);call write~int(1372, reset_card_~#descriptor~3#1.base, 32 + reset_card_~#descriptor~3#1.offset, 4);call write~int(0, reset_card_~#descriptor~3#1.base, 36 + reset_card_~#descriptor~3#1.offset, 1);call reset_card_#t~mem508#1 := read~int(reset_card_~#descriptor~3#1.base, 36 + reset_card_~#descriptor~3#1.offset, 1); {1368#false} is VALID [2022-02-20 22:02:13,582 INFO L272 TraceCheckUtils]: 60: Hoare triple {1368#false} call reset_card_#t~ret509#1 := ldv__builtin_expect(reset_card_#t~mem508#1 % 256, 0); {1367#true} is VALID [2022-02-20 22:02:13,582 INFO L290 TraceCheckUtils]: 61: Hoare triple {1367#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {1367#true} is VALID [2022-02-20 22:02:13,583 INFO L290 TraceCheckUtils]: 62: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,583 INFO L284 TraceCheckUtils]: 63: Hoare quadruple {1367#true} {1368#false} #3862#return; {1368#false} is VALID [2022-02-20 22:02:13,583 INFO L290 TraceCheckUtils]: 64: Hoare triple {1368#false} assume -9223372036854775808 <= reset_card_#t~ret509#1 && reset_card_#t~ret509#1 <= 9223372036854775807;reset_card_~tmp___0~14#1 := reset_card_#t~ret509#1;havoc reset_card_#t~mem508#1;havoc reset_card_#t~ret509#1; {1368#false} is VALID [2022-02-20 22:02:13,583 INFO L290 TraceCheckUtils]: 65: Hoare triple {1368#false} assume 0 != reset_card_~tmp___0~14#1;havoc reset_card_#t~nondet510#1; {1368#false} is VALID [2022-02-20 22:02:13,583 INFO L272 TraceCheckUtils]: 66: Hoare triple {1368#false} call reset_card_#t~ret511#1 := inw((if (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 <= 2147483647 then (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 else (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,583 INFO L290 TraceCheckUtils]: 67: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,584 INFO L290 TraceCheckUtils]: 68: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,584 INFO L284 TraceCheckUtils]: 69: Hoare quadruple {1367#true} {1368#false} #3864#return; {1368#false} is VALID [2022-02-20 22:02:13,584 INFO L290 TraceCheckUtils]: 70: Hoare triple {1368#false} havoc reset_card_#t~ret511#1; {1368#false} is VALID [2022-02-20 22:02:13,584 INFO L272 TraceCheckUtils]: 71: Hoare triple {1368#false} call msleep(10); {1367#true} is VALID [2022-02-20 22:02:13,584 INFO L290 TraceCheckUtils]: 72: Hoare triple {1367#true} ~arg0 := #in~arg0; {1367#true} is VALID [2022-02-20 22:02:13,584 INFO L290 TraceCheckUtils]: 73: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,585 INFO L284 TraceCheckUtils]: 74: Hoare quadruple {1367#true} {1368#false} #3866#return; {1368#false} is VALID [2022-02-20 22:02:13,585 INFO L272 TraceCheckUtils]: 75: Hoare triple {1368#false} call outw(0, (if (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 <= 2147483647 then (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 else (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,585 INFO L290 TraceCheckUtils]: 76: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,585 INFO L290 TraceCheckUtils]: 77: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,585 INFO L284 TraceCheckUtils]: 78: Hoare quadruple {1367#true} {1368#false} #3868#return; {1368#false} is VALID [2022-02-20 22:02:13,585 INFO L272 TraceCheckUtils]: 79: Hoare triple {1368#false} call msleep(1000); {1367#true} is VALID [2022-02-20 22:02:13,586 INFO L290 TraceCheckUtils]: 80: Hoare triple {1367#true} ~arg0 := #in~arg0; {1367#true} is VALID [2022-02-20 22:02:13,586 INFO L290 TraceCheckUtils]: 81: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,586 INFO L284 TraceCheckUtils]: 82: Hoare quadruple {1367#true} {1368#false} #3870#return; {1368#false} is VALID [2022-02-20 22:02:13,586 INFO L272 TraceCheckUtils]: 83: Hoare triple {1368#false} call reset_card_#t~ret512#1 := inw((if (4 + reset_card_~base~11#1) % 4294967296 % 4294967296 <= 2147483647 then (4 + reset_card_~base~11#1) % 4294967296 % 4294967296 else (4 + reset_card_~base~11#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,586 INFO L290 TraceCheckUtils]: 84: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,586 INFO L290 TraceCheckUtils]: 85: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,586 INFO L284 TraceCheckUtils]: 86: Hoare quadruple {1367#true} {1368#false} #3872#return; {1368#false} is VALID [2022-02-20 22:02:13,587 INFO L290 TraceCheckUtils]: 87: Hoare triple {1368#false} reset_card_~tmp___1~8#1 := reset_card_#t~ret512#1;havoc reset_card_#t~ret512#1; {1368#false} is VALID [2022-02-20 22:02:13,587 INFO L290 TraceCheckUtils]: 88: Hoare triple {1368#false} assume 0 == reset_card_~tmp___1~8#1 % 65536;reset_card_~sig~0#1 := 0; {1368#false} is VALID [2022-02-20 22:02:13,587 INFO L290 TraceCheckUtils]: 89: Hoare triple {1368#false} assume (((165 != reset_card_~sig~0#1 % 4294967296 && 187 != reset_card_~sig~0#1 % 4294967296) && 204 != reset_card_~sig~0#1 % 4294967296) && 221 != reset_card_~sig~0#1 % 4294967296) && 238 != reset_card_~sig~0#1 % 4294967296;havoc reset_card_#t~nondet514#1;call write~$Pointer$(62, 0, reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset, 8);call write~$Pointer$(63, 0, reset_card_~#descriptor___0~1#1.base, 8 + reset_card_~#descriptor___0~1#1.offset, 8);call write~$Pointer$(64, 0, reset_card_~#descriptor___0~1#1.base, 16 + reset_card_~#descriptor___0~1#1.offset, 8);call write~$Pointer$(65, 0, reset_card_~#descriptor___0~1#1.base, 24 + reset_card_~#descriptor___0~1#1.offset, 8);call write~int(1388, reset_card_~#descriptor___0~1#1.base, 32 + reset_card_~#descriptor___0~1#1.offset, 4);call write~int(0, reset_card_~#descriptor___0~1#1.base, 36 + reset_card_~#descriptor___0~1#1.offset, 1);call reset_card_#t~mem515#1 := read~int(reset_card_~#descriptor___0~1#1.base, 36 + reset_card_~#descriptor___0~1#1.offset, 1); {1368#false} is VALID [2022-02-20 22:02:13,587 INFO L272 TraceCheckUtils]: 90: Hoare triple {1368#false} call reset_card_#t~ret516#1 := ldv__builtin_expect(reset_card_#t~mem515#1 % 256, 0); {1367#true} is VALID [2022-02-20 22:02:13,587 INFO L290 TraceCheckUtils]: 91: Hoare triple {1367#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {1367#true} is VALID [2022-02-20 22:02:13,587 INFO L290 TraceCheckUtils]: 92: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,588 INFO L284 TraceCheckUtils]: 93: Hoare quadruple {1367#true} {1368#false} #3874#return; {1368#false} is VALID [2022-02-20 22:02:13,588 INFO L290 TraceCheckUtils]: 94: Hoare triple {1368#false} assume -9223372036854775808 <= reset_card_#t~ret516#1 && reset_card_#t~ret516#1 <= 9223372036854775807;reset_card_~tmp___2~6#1 := reset_card_#t~ret516#1;havoc reset_card_#t~mem515#1;havoc reset_card_#t~ret516#1; {1368#false} is VALID [2022-02-20 22:02:13,588 INFO L290 TraceCheckUtils]: 95: Hoare triple {1368#false} assume 0 != reset_card_~tmp___2~6#1;havoc reset_card_#t~nondet517#1; {1368#false} is VALID [2022-02-20 22:02:13,588 INFO L290 TraceCheckUtils]: 96: Hoare triple {1368#false} reset_card_~retval~0#1 := -5; {1368#false} is VALID [2022-02-20 22:02:13,588 INFO L290 TraceCheckUtils]: 97: Hoare triple {1368#false} reset_card_#res#1 := reset_card_~retval~0#1;call ULTIMATE.dealloc(reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset);havoc reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset;call ULTIMATE.dealloc(reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset);havoc reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset; {1368#false} is VALID [2022-02-20 22:02:13,588 INFO L290 TraceCheckUtils]: 98: Hoare triple {1368#false} isicom_probe_#t~ret593#1 := reset_card_#res#1;assume { :end_inline_reset_card } true;assume -2147483648 <= isicom_probe_#t~ret593#1 && isicom_probe_#t~ret593#1 <= 2147483647;isicom_probe_~retval~2#1 := isicom_probe_#t~ret593#1;havoc isicom_probe_#t~ret593#1; {1368#false} is VALID [2022-02-20 22:02:13,589 INFO L290 TraceCheckUtils]: 99: Hoare triple {1368#false} assume !(isicom_probe_~retval~2#1 < 0);call isicom_probe_#t~mem594#1 := read~int(isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset, 4);assume { :begin_inline_load_firmware } true;load_firmware_#in~pdev#1.base, load_firmware_#in~pdev#1.offset, load_firmware_#in~index#1, load_firmware_#in~signature#1 := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, isicom_probe_~index~0#1, isicom_probe_#t~mem594#1;havoc load_firmware_#res#1;havoc load_firmware_#t~ret524#1.base, load_firmware_#t~ret524#1.offset, load_firmware_#t~mem525#1, load_firmware_#t~switch526#1, load_firmware_#t~nondet527#1, load_firmware_#t~ret528#1, load_firmware_#t~mem529#1.base, load_firmware_#t~mem529#1.offset, load_firmware_#t~mem530#1.base, load_firmware_#t~mem530#1.offset, load_firmware_#t~ret531#1, load_firmware_#t~mem532#1, load_firmware_#t~mem533#1, load_firmware_#t~mem534#1, load_firmware_#t~ret535#1, load_firmware_#t~ret536#1, load_firmware_#t~nondet537#1, load_firmware_#t~mem538#1, load_firmware_#t~mem539#1, load_firmware_#t~ret540#1, load_firmware_#t~ret541#1, load_firmware_#t~nondet542#1, load_firmware_#t~mem543#1, load_firmware_#t~mem544#1.base, load_firmware_#t~mem544#1.offset, load_firmware_#t~mem546#1.base, load_firmware_#t~mem546#1.offset, load_firmware_#t~mem545#1.base, load_firmware_#t~mem545#1.offset, load_firmware_#t~mem547#1, load_firmware_#t~mem548#1.base, load_firmware_#t~mem548#1.offset, load_firmware_#t~mem549#1.base, load_firmware_#t~mem549#1.offset, load_firmware_#t~ret550#1, load_firmware_#t~mem551#1, load_firmware_#t~mem552#1, load_firmware_#t~mem553#1, load_firmware_#t~ret554#1, load_firmware_#t~ret555#1, load_firmware_#t~nondet556#1, load_firmware_#t~mem557#1, load_firmware_#t~mem558#1, load_firmware_#t~ret559#1.base, load_firmware_#t~ret559#1.offset, load_firmware_#t~nondet560#1, load_firmware_#t~ret561#1, load_firmware_#t~mem562#1, load_firmware_#t~mem563#1, load_firmware_#t~nondet564#1, load_firmware_#t~mem565#1, load_firmware_#t~ret566#1, load_firmware_#t~ret567#1, load_firmware_#t~nondet568#1, load_firmware_#t~mem569#1, load_firmware_#t~mem570#1.base, load_firmware_#t~mem570#1.offset, load_firmware_#t~mem572#1.base, load_firmware_#t~mem572#1.offset, load_firmware_#t~mem571#1.base, load_firmware_#t~mem571#1.offset, load_firmware_#t~mem573#1, load_firmware_#t~ret574#1, load_firmware_#t~mem575#1, load_firmware_#t~mem576#1.base, load_firmware_#t~mem576#1.offset, load_firmware_~pdev#1.base, load_firmware_~pdev#1.offset, load_firmware_~index#1, load_firmware_~signature#1, load_firmware_~board~2#1.base, load_firmware_~board~2#1.offset, load_firmware_~tmp~33#1.base, load_firmware_~tmp~33#1.offset, load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, load_firmware_~base~12#1, load_firmware_~a~2#1, load_firmware_~word_count~2#1, load_firmware_~status~1#1, load_firmware_~retval~1#1, load_firmware_~name~0#1.base, load_firmware_~name~0#1.offset, load_firmware_~data~0#1.base, load_firmware_~data~0#1.offset, load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset, load_firmware_~tmp___0~15#1, load_firmware_~tmp___1~9#1, load_firmware_~tmp___2~7#1, load_firmware_~tmp___3~4#1, load_firmware_~tmp___4~2#1, load_firmware_~tmp___5~1#1.base, load_firmware_~tmp___5~1#1.offset, load_firmware_~tmp___6~1#1, load_firmware_~tmp___7~1#1;load_firmware_~pdev#1.base, load_firmware_~pdev#1.offset := load_firmware_#in~pdev#1.base, load_firmware_#in~pdev#1.offset;load_firmware_~index#1 := load_firmware_#in~index#1;load_firmware_~signature#1 := load_firmware_#in~signature#1;havoc load_firmware_~board~2#1.base, load_firmware_~board~2#1.offset;havoc load_firmware_~tmp~33#1.base, load_firmware_~tmp~33#1.offset;call load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset := #Ultimate.allocOnStack(8);havoc load_firmware_~base~12#1;havoc load_firmware_~a~2#1;havoc load_firmware_~word_count~2#1;havoc load_firmware_~status~1#1;havoc load_firmware_~retval~1#1;havoc load_firmware_~name~0#1.base, load_firmware_~name~0#1.offset;havoc load_firmware_~data~0#1.base, load_firmware_~data~0#1.offset;havoc load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset;havoc load_firmware_~tmp___0~15#1;havoc load_firmware_~tmp___1~9#1;havoc load_firmware_~tmp___2~7#1;havoc load_firmware_~tmp___3~4#1;havoc load_firmware_~tmp___4~2#1;havoc load_firmware_~tmp___5~1#1.base, load_firmware_~tmp___5~1#1.offset;havoc load_firmware_~tmp___6~1#1;havoc load_firmware_~tmp___7~1#1; {1368#false} is VALID [2022-02-20 22:02:13,589 INFO L272 TraceCheckUtils]: 100: Hoare triple {1368#false} call load_firmware_#t~ret524#1.base, load_firmware_#t~ret524#1.offset := pci_get_drvdata(load_firmware_~pdev#1.base, load_firmware_~pdev#1.offset); {1367#true} is VALID [2022-02-20 22:02:13,589 INFO L290 TraceCheckUtils]: 101: Hoare triple {1367#true} ~pdev#1.base, ~pdev#1.offset := #in~pdev#1.base, #in~pdev#1.offset;havoc ~tmp~11#1.base, ~tmp~11#1.offset;assume { :begin_inline_dev_get_drvdata } true;dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset := ~pdev#1.base, 147 + ~pdev#1.offset;havoc dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset, dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset;dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset := dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset;call dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset := read~$Pointer$(dev_get_drvdata_~dev#1.base, 489 + dev_get_drvdata_~dev#1.offset, 8);dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset := dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset; {1367#true} is VALID [2022-02-20 22:02:13,589 INFO L290 TraceCheckUtils]: 102: Hoare triple {1367#true} #t~ret153#1.base, #t~ret153#1.offset := dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;assume { :end_inline_dev_get_drvdata } true;~tmp~11#1.base, ~tmp~11#1.offset := #t~ret153#1.base, #t~ret153#1.offset;havoc #t~ret153#1.base, #t~ret153#1.offset;#res#1.base, #res#1.offset := ~tmp~11#1.base, ~tmp~11#1.offset; {1367#true} is VALID [2022-02-20 22:02:13,589 INFO L290 TraceCheckUtils]: 103: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,590 INFO L284 TraceCheckUtils]: 104: Hoare quadruple {1367#true} {1368#false} #3882#return; {1368#false} is VALID [2022-02-20 22:02:13,590 INFO L290 TraceCheckUtils]: 105: Hoare triple {1368#false} load_firmware_~tmp~33#1.base, load_firmware_~tmp~33#1.offset := load_firmware_#t~ret524#1.base, load_firmware_#t~ret524#1.offset;havoc load_firmware_#t~ret524#1.base, load_firmware_#t~ret524#1.offset;load_firmware_~board~2#1.base, load_firmware_~board~2#1.offset := load_firmware_~tmp~33#1.base, load_firmware_~tmp~33#1.offset;call load_firmware_#t~mem525#1 := read~int(load_firmware_~board~2#1.base, load_firmware_~board~2#1.offset, 8);load_firmware_~base~12#1 := load_firmware_#t~mem525#1;havoc load_firmware_#t~mem525#1;load_firmware_~retval~1#1 := -5;load_firmware_#t~switch526#1 := 165 == load_firmware_~signature#1; {1368#false} is VALID [2022-02-20 22:02:13,590 INFO L290 TraceCheckUtils]: 106: Hoare triple {1368#false} assume load_firmware_#t~switch526#1;load_firmware_~name~0#1.base, load_firmware_~name~0#1.offset := 69, 0; {1368#false} is VALID [2022-02-20 22:02:13,590 INFO L290 TraceCheckUtils]: 107: Hoare triple {1368#false} assume { :begin_inline_request_firmware } true;request_firmware_#in~arg0#1.base, request_firmware_#in~arg0#1.offset, request_firmware_#in~arg1#1.base, request_firmware_#in~arg1#1.offset, request_firmware_#in~arg2#1.base, request_firmware_#in~arg2#1.offset := load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, load_firmware_~name~0#1.base, load_firmware_~name~0#1.offset, load_firmware_~pdev#1.base, 147 + load_firmware_~pdev#1.offset;havoc request_firmware_#res#1;havoc request_firmware_#t~nondet759#1, request_firmware_~arg0#1.base, request_firmware_~arg0#1.offset, request_firmware_~arg1#1.base, request_firmware_~arg1#1.offset, request_firmware_~arg2#1.base, request_firmware_~arg2#1.offset;request_firmware_~arg0#1.base, request_firmware_~arg0#1.offset := request_firmware_#in~arg0#1.base, request_firmware_#in~arg0#1.offset;request_firmware_~arg1#1.base, request_firmware_~arg1#1.offset := request_firmware_#in~arg1#1.base, request_firmware_#in~arg1#1.offset;request_firmware_~arg2#1.base, request_firmware_~arg2#1.offset := request_firmware_#in~arg2#1.base, request_firmware_#in~arg2#1.offset;assume -2147483648 <= request_firmware_#t~nondet759#1 && request_firmware_#t~nondet759#1 <= 2147483647;request_firmware_#res#1 := request_firmware_#t~nondet759#1;havoc request_firmware_#t~nondet759#1; {1368#false} is VALID [2022-02-20 22:02:13,590 INFO L290 TraceCheckUtils]: 108: Hoare triple {1368#false} load_firmware_#t~ret528#1 := request_firmware_#res#1;assume { :end_inline_request_firmware } true;assume -2147483648 <= load_firmware_#t~ret528#1 && load_firmware_#t~ret528#1 <= 2147483647;load_firmware_~retval~1#1 := load_firmware_#t~ret528#1;havoc load_firmware_#t~ret528#1; {1368#false} is VALID [2022-02-20 22:02:13,590 INFO L290 TraceCheckUtils]: 109: Hoare triple {1368#false} assume !(0 != load_firmware_~retval~1#1);load_firmware_~retval~1#1 := -5;call load_firmware_#t~mem529#1.base, load_firmware_#t~mem529#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem530#1.base, load_firmware_#t~mem530#1.offset := read~$Pointer$(load_firmware_#t~mem529#1.base, 8 + load_firmware_#t~mem529#1.offset, 8);load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset := load_firmware_#t~mem530#1.base, load_firmware_#t~mem530#1.offset;havoc load_firmware_#t~mem529#1.base, load_firmware_#t~mem529#1.offset;havoc load_firmware_#t~mem530#1.base, load_firmware_#t~mem530#1.offset; {1368#false} is VALID [2022-02-20 22:02:13,591 INFO L290 TraceCheckUtils]: 110: Hoare triple {1368#false} call load_firmware_#t~mem544#1.base, load_firmware_#t~mem544#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem546#1.base, load_firmware_#t~mem546#1.offset := read~$Pointer$(load_firmware_#t~mem544#1.base, 8 + load_firmware_#t~mem544#1.offset, 8);call load_firmware_#t~mem545#1.base, load_firmware_#t~mem545#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem547#1 := read~int(load_firmware_#t~mem545#1.base, load_firmware_#t~mem545#1.offset, 8); {1368#false} is VALID [2022-02-20 22:02:13,591 INFO L290 TraceCheckUtils]: 111: Hoare triple {1368#false} assume !((load_firmware_#t~mem546#1.base + (load_firmware_#t~mem546#1.offset + (if load_firmware_#t~mem547#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then load_firmware_#t~mem547#1 % 18446744073709551616 % 18446744073709551616 else load_firmware_#t~mem547#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616))) % 18446744073709551616 > (load_firmware_~frame~0#1.base + load_firmware_~frame~0#1.offset) % 18446744073709551616);havoc load_firmware_#t~mem544#1.base, load_firmware_#t~mem544#1.offset;havoc load_firmware_#t~mem546#1.base, load_firmware_#t~mem546#1.offset;havoc load_firmware_#t~mem545#1.base, load_firmware_#t~mem545#1.offset;havoc load_firmware_#t~mem547#1;call load_firmware_#t~mem548#1.base, load_firmware_#t~mem548#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem549#1.base, load_firmware_#t~mem549#1.offset := read~$Pointer$(load_firmware_#t~mem548#1.base, 8 + load_firmware_#t~mem548#1.offset, 8);load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset := load_firmware_#t~mem549#1.base, load_firmware_#t~mem549#1.offset;havoc load_firmware_#t~mem548#1.base, load_firmware_#t~mem548#1.offset;havoc load_firmware_#t~mem549#1.base, load_firmware_#t~mem549#1.offset; {1368#false} is VALID [2022-02-20 22:02:13,591 INFO L290 TraceCheckUtils]: 112: Hoare triple {1368#false} call load_firmware_#t~mem570#1.base, load_firmware_#t~mem570#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem572#1.base, load_firmware_#t~mem572#1.offset := read~$Pointer$(load_firmware_#t~mem570#1.base, 8 + load_firmware_#t~mem570#1.offset, 8);call load_firmware_#t~mem571#1.base, load_firmware_#t~mem571#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem573#1 := read~int(load_firmware_#t~mem571#1.base, load_firmware_#t~mem571#1.offset, 8); {1368#false} is VALID [2022-02-20 22:02:13,591 INFO L290 TraceCheckUtils]: 113: Hoare triple {1368#false} assume (load_firmware_#t~mem572#1.base + (load_firmware_#t~mem572#1.offset + (if load_firmware_#t~mem573#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then load_firmware_#t~mem573#1 % 18446744073709551616 % 18446744073709551616 else load_firmware_#t~mem573#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616))) % 18446744073709551616 > (load_firmware_~frame~0#1.base + load_firmware_~frame~0#1.offset) % 18446744073709551616;havoc load_firmware_#t~mem570#1.base, load_firmware_#t~mem570#1.offset;havoc load_firmware_#t~mem572#1.base, load_firmware_#t~mem572#1.offset;havoc load_firmware_#t~mem571#1.base, load_firmware_#t~mem571#1.offset;havoc load_firmware_#t~mem573#1; {1368#false} is VALID [2022-02-20 22:02:13,591 INFO L272 TraceCheckUtils]: 114: Hoare triple {1368#false} call load_firmware_#t~ret550#1 := WaitTillCardIsFree(load_firmware_~base~12#1); {1367#true} is VALID [2022-02-20 22:02:13,592 INFO L290 TraceCheckUtils]: 115: Hoare triple {1367#true} ~base#1 := #in~base#1;havoc ~count~0#1;havoc ~a~0#1;havoc ~tmp~12#1;havoc ~__ms~0#1;havoc ~tmp___0~6#1;havoc ~tmp___1~3#1;havoc ~tmp___2~2#1;havoc ~tmp___3~0#1;~count~0#1 := 0;assume { :begin_inline_preempt_count } true;havoc preempt_count_#res#1;havoc preempt_count_#t~switch11#1, preempt_count_~pfo_ret__~0#1;havoc preempt_count_~pfo_ret__~0#1;preempt_count_#t~switch11#1 := false; {1367#true} is VALID [2022-02-20 22:02:13,592 INFO L290 TraceCheckUtils]: 116: Hoare triple {1367#true} assume preempt_count_#t~switch11#1; {1367#true} is VALID [2022-02-20 22:02:13,592 INFO L290 TraceCheckUtils]: 117: Hoare triple {1367#true} preempt_count_#res#1 := (if 0 == preempt_count_~pfo_ret__~0#1 then 0 else (if 1 == preempt_count_~pfo_ret__~0#1 then 1 else ~bitwiseAnd(preempt_count_~pfo_ret__~0#1, 2147483647))); {1367#true} is VALID [2022-02-20 22:02:13,592 INFO L290 TraceCheckUtils]: 118: Hoare triple {1367#true} #t~ret154#1 := preempt_count_#res#1;assume { :end_inline_preempt_count } true;assume -2147483648 <= #t~ret154#1 && #t~ret154#1 <= 2147483647;~tmp~12#1 := #t~ret154#1;havoc #t~ret154#1;~a~0#1 := (if 0 != (if 0 == ~tmp~12#1 then 0 else (if 1 == ~tmp~12#1 then 1 else ~bitwiseAnd(~tmp~12#1, 18446744073707454463))) % 18446744073709551616 then 1 else 0); {1367#true} is VALID [2022-02-20 22:02:13,592 INFO L272 TraceCheckUtils]: 119: Hoare triple {1367#true} call #t~ret155#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,592 INFO L290 TraceCheckUtils]: 120: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,592 INFO L290 TraceCheckUtils]: 121: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,593 INFO L284 TraceCheckUtils]: 122: Hoare quadruple {1367#true} {1367#true} #3568#return; {1367#true} is VALID [2022-02-20 22:02:13,593 INFO L290 TraceCheckUtils]: 123: Hoare triple {1367#true} ~tmp___1~3#1 := #t~ret155#1;havoc #t~ret155#1; {1367#true} is VALID [2022-02-20 22:02:13,593 INFO L290 TraceCheckUtils]: 124: Hoare triple {1367#true} assume !(0 == ~tmp___1~3#1 % 65536); {1367#true} is VALID [2022-02-20 22:02:13,593 INFO L272 TraceCheckUtils]: 125: Hoare triple {1367#true} call #t~ret156#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,593 INFO L290 TraceCheckUtils]: 126: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,593 INFO L290 TraceCheckUtils]: 127: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,594 INFO L284 TraceCheckUtils]: 128: Hoare quadruple {1367#true} {1367#true} #3570#return; {1367#true} is VALID [2022-02-20 22:02:13,594 INFO L290 TraceCheckUtils]: 129: Hoare triple {1367#true} ~tmp___3~0#1 := #t~ret156#1;havoc #t~ret156#1;#res#1 := (if 0 == ~tmp___3~0#1 % 65536 then 1 else 0); {1367#true} is VALID [2022-02-20 22:02:13,594 INFO L290 TraceCheckUtils]: 130: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,594 INFO L284 TraceCheckUtils]: 131: Hoare quadruple {1367#true} {1368#false} #3912#return; {1368#false} is VALID [2022-02-20 22:02:13,594 INFO L290 TraceCheckUtils]: 132: Hoare triple {1368#false} assume -2147483648 <= load_firmware_#t~ret550#1 && load_firmware_#t~ret550#1 <= 2147483647;load_firmware_~tmp___3~4#1 := load_firmware_#t~ret550#1;havoc load_firmware_#t~ret550#1; {1368#false} is VALID [2022-02-20 22:02:13,594 INFO L290 TraceCheckUtils]: 133: Hoare triple {1368#false} assume !(0 != load_firmware_~tmp___3~4#1); {1368#false} is VALID [2022-02-20 22:02:13,594 INFO L272 TraceCheckUtils]: 134: Hoare triple {1368#false} call outw(241, (if load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 <= 2147483647 then load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 else load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,595 INFO L290 TraceCheckUtils]: 135: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,595 INFO L290 TraceCheckUtils]: 136: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,595 INFO L284 TraceCheckUtils]: 137: Hoare quadruple {1367#true} {1368#false} #3914#return; {1368#false} is VALID [2022-02-20 22:02:13,595 INFO L272 TraceCheckUtils]: 138: Hoare triple {1368#false} call outw(0, (if load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 <= 2147483647 then load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 else load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,595 INFO L290 TraceCheckUtils]: 139: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,595 INFO L290 TraceCheckUtils]: 140: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,596 INFO L284 TraceCheckUtils]: 141: Hoare quadruple {1367#true} {1368#false} #3916#return; {1368#false} is VALID [2022-02-20 22:02:13,596 INFO L290 TraceCheckUtils]: 142: Hoare triple {1368#false} call load_firmware_#t~mem551#1 := read~int(load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset, 2); {1368#false} is VALID [2022-02-20 22:02:13,596 INFO L272 TraceCheckUtils]: 143: Hoare triple {1368#false} call outw(load_firmware_#t~mem551#1 % 65536, (if load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 <= 2147483647 then load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 else load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,596 INFO L290 TraceCheckUtils]: 144: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,596 INFO L290 TraceCheckUtils]: 145: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,596 INFO L284 TraceCheckUtils]: 146: Hoare quadruple {1367#true} {1368#false} #3918#return; {1368#false} is VALID [2022-02-20 22:02:13,596 INFO L290 TraceCheckUtils]: 147: Hoare triple {1368#false} havoc load_firmware_#t~mem551#1;call load_firmware_#t~mem552#1 := read~int(load_firmware_~frame~0#1.base, 2 + load_firmware_~frame~0#1.offset, 2);call load_firmware_#t~mem553#1 := read~int(load_firmware_~frame~0#1.base, 2 + load_firmware_~frame~0#1.offset, 2);load_firmware_~word_count~2#1 := load_firmware_#t~mem552#1 % 65536 / 2 % 65536 + load_firmware_#t~mem553#1 % 65536;havoc load_firmware_#t~mem552#1;havoc load_firmware_#t~mem553#1; {1368#false} is VALID [2022-02-20 22:02:13,597 INFO L272 TraceCheckUtils]: 148: Hoare triple {1368#false} call outw((if (1 + load_firmware_~word_count~2#1 % 65536) % 4294967296 % 4294967296 <= 2147483647 then (1 + load_firmware_~word_count~2#1 % 65536) % 4294967296 % 4294967296 else (1 + load_firmware_~word_count~2#1 % 65536) % 4294967296 % 4294967296 - 4294967296), (if load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 <= 2147483647 then load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 else load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,597 INFO L290 TraceCheckUtils]: 149: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,597 INFO L290 TraceCheckUtils]: 150: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,597 INFO L284 TraceCheckUtils]: 151: Hoare quadruple {1367#true} {1368#false} #3920#return; {1368#false} is VALID [2022-02-20 22:02:13,597 INFO L272 TraceCheckUtils]: 152: Hoare triple {1368#false} call outw(0, (if (12 + load_firmware_~base~12#1) % 4294967296 % 4294967296 <= 2147483647 then (12 + load_firmware_~base~12#1) % 4294967296 % 4294967296 else (12 + load_firmware_~base~12#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,597 INFO L290 TraceCheckUtils]: 153: Hoare triple {1367#true} ~value := #in~value;~port := #in~port; {1367#true} is VALID [2022-02-20 22:02:13,598 INFO L290 TraceCheckUtils]: 154: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,598 INFO L284 TraceCheckUtils]: 155: Hoare quadruple {1367#true} {1368#false} #3922#return; {1368#false} is VALID [2022-02-20 22:02:13,598 INFO L272 TraceCheckUtils]: 156: Hoare triple {1368#false} call __const_udelay(214750); {1367#true} is VALID [2022-02-20 22:02:13,598 INFO L290 TraceCheckUtils]: 157: Hoare triple {1367#true} ~arg0 := #in~arg0; {1367#true} is VALID [2022-02-20 22:02:13,598 INFO L290 TraceCheckUtils]: 158: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,598 INFO L284 TraceCheckUtils]: 159: Hoare quadruple {1367#true} {1368#false} #3924#return; {1368#false} is VALID [2022-02-20 22:02:13,598 INFO L272 TraceCheckUtils]: 160: Hoare triple {1368#false} call load_firmware_#t~ret554#1 := WaitTillCardIsFree(load_firmware_~base~12#1); {1367#true} is VALID [2022-02-20 22:02:13,599 INFO L290 TraceCheckUtils]: 161: Hoare triple {1367#true} ~base#1 := #in~base#1;havoc ~count~0#1;havoc ~a~0#1;havoc ~tmp~12#1;havoc ~__ms~0#1;havoc ~tmp___0~6#1;havoc ~tmp___1~3#1;havoc ~tmp___2~2#1;havoc ~tmp___3~0#1;~count~0#1 := 0;assume { :begin_inline_preempt_count } true;havoc preempt_count_#res#1;havoc preempt_count_#t~switch11#1, preempt_count_~pfo_ret__~0#1;havoc preempt_count_~pfo_ret__~0#1;preempt_count_#t~switch11#1 := false; {1367#true} is VALID [2022-02-20 22:02:13,599 INFO L290 TraceCheckUtils]: 162: Hoare triple {1367#true} assume preempt_count_#t~switch11#1; {1367#true} is VALID [2022-02-20 22:02:13,599 INFO L290 TraceCheckUtils]: 163: Hoare triple {1367#true} preempt_count_#res#1 := (if 0 == preempt_count_~pfo_ret__~0#1 then 0 else (if 1 == preempt_count_~pfo_ret__~0#1 then 1 else ~bitwiseAnd(preempt_count_~pfo_ret__~0#1, 2147483647))); {1367#true} is VALID [2022-02-20 22:02:13,599 INFO L290 TraceCheckUtils]: 164: Hoare triple {1367#true} #t~ret154#1 := preempt_count_#res#1;assume { :end_inline_preempt_count } true;assume -2147483648 <= #t~ret154#1 && #t~ret154#1 <= 2147483647;~tmp~12#1 := #t~ret154#1;havoc #t~ret154#1;~a~0#1 := (if 0 != (if 0 == ~tmp~12#1 then 0 else (if 1 == ~tmp~12#1 then 1 else ~bitwiseAnd(~tmp~12#1, 18446744073707454463))) % 18446744073709551616 then 1 else 0); {1367#true} is VALID [2022-02-20 22:02:13,599 INFO L272 TraceCheckUtils]: 165: Hoare triple {1367#true} call #t~ret155#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,599 INFO L290 TraceCheckUtils]: 166: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,600 INFO L290 TraceCheckUtils]: 167: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,600 INFO L284 TraceCheckUtils]: 168: Hoare quadruple {1367#true} {1367#true} #3568#return; {1367#true} is VALID [2022-02-20 22:02:13,600 INFO L290 TraceCheckUtils]: 169: Hoare triple {1367#true} ~tmp___1~3#1 := #t~ret155#1;havoc #t~ret155#1; {1367#true} is VALID [2022-02-20 22:02:13,600 INFO L290 TraceCheckUtils]: 170: Hoare triple {1367#true} assume !(0 == ~tmp___1~3#1 % 65536); {1367#true} is VALID [2022-02-20 22:02:13,600 INFO L272 TraceCheckUtils]: 171: Hoare triple {1367#true} call #t~ret156#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,600 INFO L290 TraceCheckUtils]: 172: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,600 INFO L290 TraceCheckUtils]: 173: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,601 INFO L284 TraceCheckUtils]: 174: Hoare quadruple {1367#true} {1367#true} #3570#return; {1367#true} is VALID [2022-02-20 22:02:13,601 INFO L290 TraceCheckUtils]: 175: Hoare triple {1367#true} ~tmp___3~0#1 := #t~ret156#1;havoc #t~ret156#1;#res#1 := (if 0 == ~tmp___3~0#1 % 65536 then 1 else 0); {1367#true} is VALID [2022-02-20 22:02:13,601 INFO L290 TraceCheckUtils]: 176: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,601 INFO L284 TraceCheckUtils]: 177: Hoare quadruple {1367#true} {1368#false} #3926#return; {1368#false} is VALID [2022-02-20 22:02:13,601 INFO L290 TraceCheckUtils]: 178: Hoare triple {1368#false} assume -2147483648 <= load_firmware_#t~ret554#1 && load_firmware_#t~ret554#1 <= 2147483647;load_firmware_~tmp___4~2#1 := load_firmware_#t~ret554#1;havoc load_firmware_#t~ret554#1; {1368#false} is VALID [2022-02-20 22:02:13,601 INFO L290 TraceCheckUtils]: 179: Hoare triple {1368#false} assume !(0 != load_firmware_~tmp___4~2#1); {1368#false} is VALID [2022-02-20 22:02:13,601 INFO L272 TraceCheckUtils]: 180: Hoare triple {1368#false} call load_firmware_#t~ret555#1 := inw((if (4 + load_firmware_~base~12#1) % 4294967296 % 4294967296 <= 2147483647 then (4 + load_firmware_~base~12#1) % 4294967296 % 4294967296 else (4 + load_firmware_~base~12#1) % 4294967296 % 4294967296 - 4294967296)); {1367#true} is VALID [2022-02-20 22:02:13,602 INFO L290 TraceCheckUtils]: 181: Hoare triple {1367#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1367#true} is VALID [2022-02-20 22:02:13,602 INFO L290 TraceCheckUtils]: 182: Hoare triple {1367#true} assume true; {1367#true} is VALID [2022-02-20 22:02:13,602 INFO L284 TraceCheckUtils]: 183: Hoare quadruple {1367#true} {1368#false} #3928#return; {1368#false} is VALID [2022-02-20 22:02:13,602 INFO L290 TraceCheckUtils]: 184: Hoare triple {1368#false} load_firmware_~status~1#1 := load_firmware_#t~ret555#1;havoc load_firmware_#t~ret555#1; {1368#false} is VALID [2022-02-20 22:02:13,602 INFO L290 TraceCheckUtils]: 185: Hoare triple {1368#false} assume !(0 != load_firmware_~status~1#1 % 65536 % 4294967296);assume { :begin_inline_kmalloc } true;kmalloc_#in~size#1, kmalloc_#in~flags#1 := 2 * (load_firmware_~word_count~2#1 % 65536), 208;havoc kmalloc_#res#1.base, kmalloc_#res#1.offset;havoc kmalloc_#t~ret732#1.base, kmalloc_#t~ret732#1.offset, kmalloc_~size#1, kmalloc_~flags#1;kmalloc_~size#1 := kmalloc_#in~size#1;kmalloc_~flags#1 := kmalloc_#in~flags#1;assume { :begin_inline_ldv_check_alloc_flags } true;ldv_check_alloc_flags_#in~flags#1 := kmalloc_~flags#1;havoc ldv_check_alloc_flags_~flags#1;ldv_check_alloc_flags_~flags#1 := ldv_check_alloc_flags_#in~flags#1; {1368#false} is VALID [2022-02-20 22:02:13,602 INFO L290 TraceCheckUtils]: 186: Hoare triple {1368#false} assume !(0 == ~ldv_spin~0 || 0 == (if 0 == ldv_check_alloc_flags_~flags#1 then 0 else (if 1 == ldv_check_alloc_flags_~flags#1 then 0 else ~bitwiseAnd(ldv_check_alloc_flags_~flags#1, 16))) % 4294967296); {1368#false} is VALID [2022-02-20 22:02:13,603 INFO L272 TraceCheckUtils]: 187: Hoare triple {1368#false} call ldv_error(); {1368#false} is VALID [2022-02-20 22:02:13,603 INFO L290 TraceCheckUtils]: 188: Hoare triple {1368#false} assume !false; {1368#false} is VALID [2022-02-20 22:02:13,603 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2022-02-20 22:02:13,604 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:02:13,604 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421624162] [2022-02-20 22:02:13,605 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421624162] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:02:13,605 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:02:13,605 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-20 22:02:13,606 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1041627275] [2022-02-20 22:02:13,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:02:13,610 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 22.5) internal successors, (90), 3 states have internal predecessors, (90), 2 states have call successors, (25), 3 states have call predecessors, (25), 1 states have return successors, (24), 2 states have call predecessors, (24), 2 states have call successors, (24) Word has length 189 [2022-02-20 22:02:13,612 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:02:13,615 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 22.5) internal successors, (90), 3 states have internal predecessors, (90), 2 states have call successors, (25), 3 states have call predecessors, (25), 1 states have return successors, (24), 2 states have call predecessors, (24), 2 states have call successors, (24) [2022-02-20 22:02:13,755 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 139 edges. 139 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:02:13,755 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-02-20 22:02:13,755 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:02:13,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-20 22:02:13,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-20 22:02:13,776 INFO L87 Difference]: Start difference. First operand has 1364 states, 973 states have (on average 1.433710174717369) internal successors, (1395), 1004 states have internal predecessors, (1395), 330 states have call successors, (330), 61 states have call predecessors, (330), 60 states have return successors, (322), 320 states have call predecessors, (322), 322 states have call successors, (322) Second operand has 4 states, 4 states have (on average 22.5) internal successors, (90), 3 states have internal predecessors, (90), 2 states have call successors, (25), 3 states have call predecessors, (25), 1 states have return successors, (24), 2 states have call predecessors, (24), 2 states have call successors, (24) [2022-02-20 22:02:20,778 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:02:34,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:02:34,046 INFO L93 Difference]: Finished difference Result 3992 states and 6172 transitions. [2022-02-20 22:02:34,046 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-02-20 22:02:34,047 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 22.5) internal successors, (90), 3 states have internal predecessors, (90), 2 states have call successors, (25), 3 states have call predecessors, (25), 1 states have return successors, (24), 2 states have call predecessors, (24), 2 states have call successors, (24) Word has length 189 [2022-02-20 22:02:34,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:02:34,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 22.5) internal successors, (90), 3 states have internal predecessors, (90), 2 states have call successors, (25), 3 states have call predecessors, (25), 1 states have return successors, (24), 2 states have call predecessors, (24), 2 states have call successors, (24) [2022-02-20 22:02:34,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 6172 transitions. [2022-02-20 22:02:34,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 22.5) internal successors, (90), 3 states have internal predecessors, (90), 2 states have call successors, (25), 3 states have call predecessors, (25), 1 states have return successors, (24), 2 states have call predecessors, (24), 2 states have call successors, (24) [2022-02-20 22:02:34,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 6172 transitions. [2022-02-20 22:02:34,383 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 6172 transitions. [2022-02-20 22:02:39,414 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 6172 edges. 6172 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:02:39,844 INFO L225 Difference]: With dead ends: 3992 [2022-02-20 22:02:39,844 INFO L226 Difference]: Without dead ends: 2592 [2022-02-20 22:02:39,855 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-02-20 22:02:39,859 INFO L933 BasicCegarLoop]: 2112 mSDtfsCounter, 2054 mSDsluCounter, 2248 mSDsCounter, 0 mSdLazyCounter, 1599 mSolverCounterSat, 821 mSolverCounterUnsat, 1 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 5.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2298 SdHoareTripleChecker+Valid, 4360 SdHoareTripleChecker+Invalid, 2421 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 821 IncrementalHoareTripleChecker+Valid, 1599 IncrementalHoareTripleChecker+Invalid, 1 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 5.7s IncrementalHoareTripleChecker+Time [2022-02-20 22:02:39,860 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [2298 Valid, 4360 Invalid, 2421 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [821 Valid, 1599 Invalid, 1 Unknown, 0 Unchecked, 5.7s Time] [2022-02-20 22:02:39,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2592 states. [2022-02-20 22:02:40,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2592 to 2426. [2022-02-20 22:02:40,133 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:02:40,148 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2592 states. Second operand has 2426 states, 1745 states have (on average 1.4) internal successors, (2443), 1785 states have internal predecessors, (2443), 568 states have call successors, (568), 113 states have call predecessors, (568), 112 states have return successors, (567), 563 states have call predecessors, (567), 567 states have call successors, (567) [2022-02-20 22:02:40,156 INFO L74 IsIncluded]: Start isIncluded. First operand 2592 states. Second operand has 2426 states, 1745 states have (on average 1.4) internal successors, (2443), 1785 states have internal predecessors, (2443), 568 states have call successors, (568), 113 states have call predecessors, (568), 112 states have return successors, (567), 563 states have call predecessors, (567), 567 states have call successors, (567) [2022-02-20 22:02:40,163 INFO L87 Difference]: Start difference. First operand 2592 states. Second operand has 2426 states, 1745 states have (on average 1.4) internal successors, (2443), 1785 states have internal predecessors, (2443), 568 states have call successors, (568), 113 states have call predecessors, (568), 112 states have return successors, (567), 563 states have call predecessors, (567), 567 states have call successors, (567) [2022-02-20 22:02:40,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:02:40,375 INFO L93 Difference]: Finished difference Result 2592 states and 3894 transitions. [2022-02-20 22:02:40,375 INFO L276 IsEmpty]: Start isEmpty. Operand 2592 states and 3894 transitions. [2022-02-20 22:02:40,386 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:02:40,387 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:02:40,392 INFO L74 IsIncluded]: Start isIncluded. First operand has 2426 states, 1745 states have (on average 1.4) internal successors, (2443), 1785 states have internal predecessors, (2443), 568 states have call successors, (568), 113 states have call predecessors, (568), 112 states have return successors, (567), 563 states have call predecessors, (567), 567 states have call successors, (567) Second operand 2592 states. [2022-02-20 22:02:40,398 INFO L87 Difference]: Start difference. First operand has 2426 states, 1745 states have (on average 1.4) internal successors, (2443), 1785 states have internal predecessors, (2443), 568 states have call successors, (568), 113 states have call predecessors, (568), 112 states have return successors, (567), 563 states have call predecessors, (567), 567 states have call successors, (567) Second operand 2592 states. [2022-02-20 22:02:40,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:02:40,597 INFO L93 Difference]: Finished difference Result 2592 states and 3894 transitions. [2022-02-20 22:02:40,597 INFO L276 IsEmpty]: Start isEmpty. Operand 2592 states and 3894 transitions. [2022-02-20 22:02:40,607 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:02:40,607 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:02:40,607 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:02:40,608 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:02:40,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2426 states, 1745 states have (on average 1.4) internal successors, (2443), 1785 states have internal predecessors, (2443), 568 states have call successors, (568), 113 states have call predecessors, (568), 112 states have return successors, (567), 563 states have call predecessors, (567), 567 states have call successors, (567) [2022-02-20 22:02:40,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2426 states to 2426 states and 3578 transitions. [2022-02-20 22:02:40,893 INFO L78 Accepts]: Start accepts. Automaton has 2426 states and 3578 transitions. Word has length 189 [2022-02-20 22:02:40,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:02:40,893 INFO L470 AbstractCegarLoop]: Abstraction has 2426 states and 3578 transitions. [2022-02-20 22:02:40,894 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 22.5) internal successors, (90), 3 states have internal predecessors, (90), 2 states have call successors, (25), 3 states have call predecessors, (25), 1 states have return successors, (24), 2 states have call predecessors, (24), 2 states have call successors, (24) [2022-02-20 22:02:40,895 INFO L276 IsEmpty]: Start isEmpty. Operand 2426 states and 3578 transitions. [2022-02-20 22:02:40,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 250 [2022-02-20 22:02:40,907 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:02:40,908 INFO L514 BasicCegarLoop]: trace histogram [8, 8, 8, 7, 7, 6, 6, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:02:40,908 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-02-20 22:02:40,908 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:02:40,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:02:40,909 INFO L85 PathProgramCache]: Analyzing trace with hash -48267231, now seen corresponding path program 1 times [2022-02-20 22:02:40,909 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:02:40,909 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127788883] [2022-02-20 22:02:40,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:02:40,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:02:41,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,075 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:02:41,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,081 INFO L290 TraceCheckUtils]: 0: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,081 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,081 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,082 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15490#true} #3596#return; {15490#true} is VALID [2022-02-20 22:02:41,082 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 8 [2022-02-20 22:02:41,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,089 INFO L290 TraceCheckUtils]: 0: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,089 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,089 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,089 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15490#true} #3598#return; {15490#true} is VALID [2022-02-20 22:02:41,090 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 14 [2022-02-20 22:02:41,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,096 INFO L290 TraceCheckUtils]: 0: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,096 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,097 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,097 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15490#true} #3600#return; {15490#true} is VALID [2022-02-20 22:02:41,097 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 20 [2022-02-20 22:02:41,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,108 INFO L290 TraceCheckUtils]: 0: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,108 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,110 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,110 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15490#true} #3602#return; {15490#true} is VALID [2022-02-20 22:02:41,115 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2022-02-20 22:02:41,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,125 INFO L290 TraceCheckUtils]: 0: Hoare triple {15622#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~1.base, ~tmp~1.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet36 && #t~nondet36 <= 2147483647;~tmp___0~0 := #t~nondet36;havoc #t~nondet36; {15490#true} is VALID [2022-02-20 22:02:41,125 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,125 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,125 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15491#false} #3650#return; {15491#false} is VALID [2022-02-20 22:02:41,125 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 43 [2022-02-20 22:02:41,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,133 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:02:41,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,138 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {15490#true} is VALID [2022-02-20 22:02:41,139 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,140 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15490#true} #4020#return; {15490#true} is VALID [2022-02-20 22:02:41,140 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;havoc ~tmp~0; {15490#true} is VALID [2022-02-20 22:02:41,140 INFO L272 TraceCheckUtils]: 1: Hoare triple {15490#true} call #t~ret10 := ldv__builtin_expect((if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 18446744073709547520 then 1 else 0), 0); {15490#true} is VALID [2022-02-20 22:02:41,140 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {15490#true} is VALID [2022-02-20 22:02:41,140 INFO L290 TraceCheckUtils]: 3: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,145 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {15490#true} {15490#true} #4020#return; {15490#true} is VALID [2022-02-20 22:02:41,145 INFO L290 TraceCheckUtils]: 5: Hoare triple {15490#true} assume -9223372036854775808 <= #t~ret10 && #t~ret10 <= 9223372036854775807;~tmp~0 := #t~ret10;havoc #t~ret10;#res := (if 0 == (if 0 != ~tmp~0 then 1 else 0) then 0 else 1); {15490#true} is VALID [2022-02-20 22:02:41,145 INFO L290 TraceCheckUtils]: 6: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,145 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {15490#true} {15491#false} #3652#return; {15491#false} is VALID [2022-02-20 22:02:41,146 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 59 [2022-02-20 22:02:41,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,155 INFO L290 TraceCheckUtils]: 0: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,155 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,155 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,156 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15491#false} #3662#return; {15491#false} is VALID [2022-02-20 22:02:41,156 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 66 [2022-02-20 22:02:41,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,163 INFO L290 TraceCheckUtils]: 0: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,163 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,163 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,164 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15491#false} #3664#return; {15491#false} is VALID [2022-02-20 22:02:41,164 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 73 [2022-02-20 22:02:41,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,175 INFO L290 TraceCheckUtils]: 0: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,175 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,175 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,175 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15491#false} #3666#return; {15491#false} is VALID [2022-02-20 22:02:41,175 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 79 [2022-02-20 22:02:41,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,185 INFO L290 TraceCheckUtils]: 0: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,185 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,186 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,186 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15491#false} #3668#return; {15491#false} is VALID [2022-02-20 22:02:41,186 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 114 [2022-02-20 22:02:41,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,193 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~pdev#1.base, ~pdev#1.offset := #in~pdev#1.base, #in~pdev#1.offset;havoc ~tmp~11#1.base, ~tmp~11#1.offset;assume { :begin_inline_dev_get_drvdata } true;dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset := ~pdev#1.base, 147 + ~pdev#1.offset;havoc dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset, dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset;dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset := dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset;call dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset := read~$Pointer$(dev_get_drvdata_~dev#1.base, 489 + dev_get_drvdata_~dev#1.offset, 8);dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset := dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset; {15490#true} is VALID [2022-02-20 22:02:41,193 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} #t~ret153#1.base, #t~ret153#1.offset := dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;assume { :end_inline_dev_get_drvdata } true;~tmp~11#1.base, ~tmp~11#1.offset := #t~ret153#1.base, #t~ret153#1.offset;havoc #t~ret153#1.base, #t~ret153#1.offset;#res#1.base, #res#1.offset := ~tmp~11#1.base, ~tmp~11#1.offset; {15490#true} is VALID [2022-02-20 22:02:41,193 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,193 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15491#false} #3860#return; {15491#false} is VALID [2022-02-20 22:02:41,194 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 120 [2022-02-20 22:02:41,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,199 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {15490#true} is VALID [2022-02-20 22:02:41,200 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,200 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3862#return; {15491#false} is VALID [2022-02-20 22:02:41,200 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 126 [2022-02-20 22:02:41,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,205 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,206 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,206 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3864#return; {15491#false} is VALID [2022-02-20 22:02:41,206 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 131 [2022-02-20 22:02:41,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,211 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~arg0 := #in~arg0; {15490#true} is VALID [2022-02-20 22:02:41,211 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,212 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3866#return; {15491#false} is VALID [2022-02-20 22:02:41,212 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 135 [2022-02-20 22:02:41,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,222 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,223 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,223 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3868#return; {15491#false} is VALID [2022-02-20 22:02:41,223 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 139 [2022-02-20 22:02:41,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,229 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~arg0 := #in~arg0; {15490#true} is VALID [2022-02-20 22:02:41,229 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,229 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3870#return; {15491#false} is VALID [2022-02-20 22:02:41,230 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 143 [2022-02-20 22:02:41,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,236 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,236 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,236 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3872#return; {15491#false} is VALID [2022-02-20 22:02:41,236 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 150 [2022-02-20 22:02:41,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,242 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {15490#true} is VALID [2022-02-20 22:02:41,242 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,243 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3874#return; {15491#false} is VALID [2022-02-20 22:02:41,243 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 160 [2022-02-20 22:02:41,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,250 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~pdev#1.base, ~pdev#1.offset := #in~pdev#1.base, #in~pdev#1.offset;havoc ~tmp~11#1.base, ~tmp~11#1.offset;assume { :begin_inline_dev_get_drvdata } true;dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset := ~pdev#1.base, 147 + ~pdev#1.offset;havoc dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset, dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset;dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset := dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset;call dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset := read~$Pointer$(dev_get_drvdata_~dev#1.base, 489 + dev_get_drvdata_~dev#1.offset, 8);dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset := dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset; {15490#true} is VALID [2022-02-20 22:02:41,252 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} #t~ret153#1.base, #t~ret153#1.offset := dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;assume { :end_inline_dev_get_drvdata } true;~tmp~11#1.base, ~tmp~11#1.offset := #t~ret153#1.base, #t~ret153#1.offset;havoc #t~ret153#1.base, #t~ret153#1.offset;#res#1.base, #res#1.offset := ~tmp~11#1.base, ~tmp~11#1.offset; {15490#true} is VALID [2022-02-20 22:02:41,253 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,254 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {15490#true} {15491#false} #3882#return; {15491#false} is VALID [2022-02-20 22:02:41,255 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 174 [2022-02-20 22:02:41,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,269 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 22:02:41,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,274 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,274 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,274 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15490#true} #3568#return; {15490#true} is VALID [2022-02-20 22:02:41,274 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 10 [2022-02-20 22:02:41,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,278 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,279 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,279 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15490#true} #3570#return; {15490#true} is VALID [2022-02-20 22:02:41,279 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~base#1 := #in~base#1;havoc ~count~0#1;havoc ~a~0#1;havoc ~tmp~12#1;havoc ~__ms~0#1;havoc ~tmp___0~6#1;havoc ~tmp___1~3#1;havoc ~tmp___2~2#1;havoc ~tmp___3~0#1;~count~0#1 := 0;assume { :begin_inline_preempt_count } true;havoc preempt_count_#res#1;havoc preempt_count_#t~switch11#1, preempt_count_~pfo_ret__~0#1;havoc preempt_count_~pfo_ret__~0#1;preempt_count_#t~switch11#1 := false; {15490#true} is VALID [2022-02-20 22:02:41,279 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume preempt_count_#t~switch11#1; {15490#true} is VALID [2022-02-20 22:02:41,279 INFO L290 TraceCheckUtils]: 2: Hoare triple {15490#true} preempt_count_#res#1 := (if 0 == preempt_count_~pfo_ret__~0#1 then 0 else (if 1 == preempt_count_~pfo_ret__~0#1 then 1 else ~bitwiseAnd(preempt_count_~pfo_ret__~0#1, 2147483647))); {15490#true} is VALID [2022-02-20 22:02:41,280 INFO L290 TraceCheckUtils]: 3: Hoare triple {15490#true} #t~ret154#1 := preempt_count_#res#1;assume { :end_inline_preempt_count } true;assume -2147483648 <= #t~ret154#1 && #t~ret154#1 <= 2147483647;~tmp~12#1 := #t~ret154#1;havoc #t~ret154#1;~a~0#1 := (if 0 != (if 0 == ~tmp~12#1 then 0 else (if 1 == ~tmp~12#1 then 1 else ~bitwiseAnd(~tmp~12#1, 18446744073707454463))) % 18446744073709551616 then 1 else 0); {15490#true} is VALID [2022-02-20 22:02:41,280 INFO L272 TraceCheckUtils]: 4: Hoare triple {15490#true} call #t~ret155#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,280 INFO L290 TraceCheckUtils]: 5: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,280 INFO L290 TraceCheckUtils]: 6: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,280 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {15490#true} {15490#true} #3568#return; {15490#true} is VALID [2022-02-20 22:02:41,280 INFO L290 TraceCheckUtils]: 8: Hoare triple {15490#true} ~tmp___1~3#1 := #t~ret155#1;havoc #t~ret155#1; {15490#true} is VALID [2022-02-20 22:02:41,280 INFO L290 TraceCheckUtils]: 9: Hoare triple {15490#true} assume !(0 == ~tmp___1~3#1 % 65536); {15490#true} is VALID [2022-02-20 22:02:41,280 INFO L272 TraceCheckUtils]: 10: Hoare triple {15490#true} call #t~ret156#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,281 INFO L290 TraceCheckUtils]: 11: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,281 INFO L290 TraceCheckUtils]: 12: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,281 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {15490#true} {15490#true} #3570#return; {15490#true} is VALID [2022-02-20 22:02:41,281 INFO L290 TraceCheckUtils]: 14: Hoare triple {15490#true} ~tmp___3~0#1 := #t~ret156#1;havoc #t~ret156#1;#res#1 := (if 0 == ~tmp___3~0#1 % 65536 then 1 else 0); {15490#true} is VALID [2022-02-20 22:02:41,281 INFO L290 TraceCheckUtils]: 15: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,281 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {15490#true} {15491#false} #3912#return; {15491#false} is VALID [2022-02-20 22:02:41,281 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 194 [2022-02-20 22:02:41,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,287 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,288 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,288 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3914#return; {15491#false} is VALID [2022-02-20 22:02:41,288 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 198 [2022-02-20 22:02:41,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,294 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,294 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,294 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3916#return; {15491#false} is VALID [2022-02-20 22:02:41,294 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 203 [2022-02-20 22:02:41,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,300 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,300 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,300 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3918#return; {15491#false} is VALID [2022-02-20 22:02:41,300 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 208 [2022-02-20 22:02:41,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,306 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,306 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,306 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3920#return; {15491#false} is VALID [2022-02-20 22:02:41,306 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 212 [2022-02-20 22:02:41,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,315 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,315 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,315 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3922#return; {15491#false} is VALID [2022-02-20 22:02:41,315 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 216 [2022-02-20 22:02:41,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,321 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~arg0 := #in~arg0; {15490#true} is VALID [2022-02-20 22:02:41,321 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,321 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3924#return; {15491#false} is VALID [2022-02-20 22:02:41,321 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 220 [2022-02-20 22:02:41,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,344 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 22:02:41,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,364 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,364 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,364 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3568#return; {15491#false} is VALID [2022-02-20 22:02:41,364 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 10 [2022-02-20 22:02:41,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,368 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,368 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,368 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3570#return; {15491#false} is VALID [2022-02-20 22:02:41,369 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~base#1 := #in~base#1;havoc ~count~0#1;havoc ~a~0#1;havoc ~tmp~12#1;havoc ~__ms~0#1;havoc ~tmp___0~6#1;havoc ~tmp___1~3#1;havoc ~tmp___2~2#1;havoc ~tmp___3~0#1;~count~0#1 := 0;assume { :begin_inline_preempt_count } true;havoc preempt_count_#res#1;havoc preempt_count_#t~switch11#1, preempt_count_~pfo_ret__~0#1;havoc preempt_count_~pfo_ret__~0#1;preempt_count_#t~switch11#1 := false; {15632#(not |WaitTillCardIsFree_preempt_count_#t~switch11#1|)} is VALID [2022-02-20 22:02:41,369 INFO L290 TraceCheckUtils]: 1: Hoare triple {15632#(not |WaitTillCardIsFree_preempt_count_#t~switch11#1|)} assume preempt_count_#t~switch11#1; {15491#false} is VALID [2022-02-20 22:02:41,369 INFO L290 TraceCheckUtils]: 2: Hoare triple {15491#false} preempt_count_#res#1 := (if 0 == preempt_count_~pfo_ret__~0#1 then 0 else (if 1 == preempt_count_~pfo_ret__~0#1 then 1 else ~bitwiseAnd(preempt_count_~pfo_ret__~0#1, 2147483647))); {15491#false} is VALID [2022-02-20 22:02:41,369 INFO L290 TraceCheckUtils]: 3: Hoare triple {15491#false} #t~ret154#1 := preempt_count_#res#1;assume { :end_inline_preempt_count } true;assume -2147483648 <= #t~ret154#1 && #t~ret154#1 <= 2147483647;~tmp~12#1 := #t~ret154#1;havoc #t~ret154#1;~a~0#1 := (if 0 != (if 0 == ~tmp~12#1 then 0 else (if 1 == ~tmp~12#1 then 1 else ~bitwiseAnd(~tmp~12#1, 18446744073707454463))) % 18446744073709551616 then 1 else 0); {15491#false} is VALID [2022-02-20 22:02:41,369 INFO L272 TraceCheckUtils]: 4: Hoare triple {15491#false} call #t~ret155#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,369 INFO L290 TraceCheckUtils]: 5: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,369 INFO L290 TraceCheckUtils]: 6: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,369 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {15490#true} {15491#false} #3568#return; {15491#false} is VALID [2022-02-20 22:02:41,370 INFO L290 TraceCheckUtils]: 8: Hoare triple {15491#false} ~tmp___1~3#1 := #t~ret155#1;havoc #t~ret155#1; {15491#false} is VALID [2022-02-20 22:02:41,370 INFO L290 TraceCheckUtils]: 9: Hoare triple {15491#false} assume !(0 == ~tmp___1~3#1 % 65536); {15491#false} is VALID [2022-02-20 22:02:41,370 INFO L272 TraceCheckUtils]: 10: Hoare triple {15491#false} call #t~ret156#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,370 INFO L290 TraceCheckUtils]: 11: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,370 INFO L290 TraceCheckUtils]: 12: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,370 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {15490#true} {15491#false} #3570#return; {15491#false} is VALID [2022-02-20 22:02:41,370 INFO L290 TraceCheckUtils]: 14: Hoare triple {15491#false} ~tmp___3~0#1 := #t~ret156#1;havoc #t~ret156#1;#res#1 := (if 0 == ~tmp___3~0#1 % 65536 then 1 else 0); {15491#false} is VALID [2022-02-20 22:02:41,370 INFO L290 TraceCheckUtils]: 15: Hoare triple {15491#false} assume true; {15491#false} is VALID [2022-02-20 22:02:41,370 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {15491#false} {15491#false} #3926#return; {15491#false} is VALID [2022-02-20 22:02:41,370 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 240 [2022-02-20 22:02:41,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:02:41,375 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,376 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,376 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {15490#true} {15491#false} #3928#return; {15491#false} is VALID [2022-02-20 22:02:41,376 INFO L290 TraceCheckUtils]: 0: Hoare triple {15490#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(92, 2);call #Ultimate.allocInit(7, 3);call write~init~int(105, 3, 0, 1);call write~init~int(115, 3, 1, 1);call write~init~int(105, 3, 2, 1);call write~init~int(99, 3, 3, 1);call write~init~int(111, 3, 4, 1);call write~init~int(109, 3, 5, 1);call write~init~int(0, 3, 6, 1);call #Ultimate.allocInit(214, 4);call #Ultimate.allocInit(214, 5);call #Ultimate.allocInit(38, 6);call #Ultimate.allocInit(7, 7);call write~init~int(105, 7, 0, 1);call write~init~int(115, 7, 1, 1);call write~init~int(105, 7, 2, 1);call write~init~int(99, 7, 3, 1);call write~init~int(111, 7, 4, 1);call write~init~int(109, 7, 5, 1);call write~init~int(0, 7, 6, 1);call #Ultimate.allocInit(10, 8);call #Ultimate.allocInit(210, 9);call #Ultimate.allocInit(25, 10);call #Ultimate.allocInit(33, 11);call #Ultimate.allocInit(47, 12);call #Ultimate.allocInit(17, 13);call #Ultimate.allocInit(7, 14);call write~init~int(105, 14, 0, 1);call write~init~int(115, 14, 1, 1);call write~init~int(105, 14, 2, 1);call write~init~int(99, 14, 3, 1);call write~init~int(111, 14, 4, 1);call write~init~int(109, 14, 5, 1);call write~init~int(0, 14, 6, 1);call #Ultimate.allocInit(17, 15);call #Ultimate.allocInit(210, 16);call #Ultimate.allocInit(15, 17);call #Ultimate.allocInit(23, 18);call #Ultimate.allocInit(17, 19);call #Ultimate.allocInit(7, 20);call write~init~int(105, 20, 0, 1);call write~init~int(115, 20, 1, 1);call write~init~int(105, 20, 2, 1);call write~init~int(99, 20, 3, 1);call write~init~int(111, 20, 4, 1);call write~init~int(109, 20, 5, 1);call write~init~int(0, 20, 6, 1);call #Ultimate.allocInit(17, 21);call #Ultimate.allocInit(210, 22);call #Ultimate.allocInit(16, 23);call #Ultimate.allocInit(24, 24);call #Ultimate.allocInit(17, 25);call #Ultimate.allocInit(7, 26);call write~init~int(105, 26, 0, 1);call write~init~int(115, 26, 1, 1);call write~init~int(105, 26, 2, 1);call write~init~int(99, 26, 3, 1);call write~init~int(111, 26, 4, 1);call write~init~int(109, 26, 5, 1);call write~init~int(0, 26, 6, 1);call #Ultimate.allocInit(17, 27);call #Ultimate.allocInit(210, 28);call #Ultimate.allocInit(14, 29);call #Ultimate.allocInit(22, 30);call #Ultimate.allocInit(17, 31);call #Ultimate.allocInit(7, 32);call write~init~int(105, 32, 0, 1);call write~init~int(115, 32, 1, 1);call write~init~int(105, 32, 2, 1);call write~init~int(99, 32, 3, 1);call write~init~int(111, 32, 4, 1);call write~init~int(109, 32, 5, 1);call write~init~int(0, 32, 6, 1);call #Ultimate.allocInit(17, 33);call #Ultimate.allocInit(210, 34);call #Ultimate.allocInit(36, 35);call #Ultimate.allocInit(44, 36);call #Ultimate.allocInit(17, 37);call #Ultimate.allocInit(7, 38);call write~init~int(105, 38, 0, 1);call write~init~int(115, 38, 1, 1);call write~init~int(105, 38, 2, 1);call write~init~int(99, 38, 3, 1);call write~init~int(111, 38, 4, 1);call write~init~int(109, 38, 5, 1);call write~init~int(0, 38, 6, 1);call #Ultimate.allocInit(17, 39);call #Ultimate.allocInit(210, 40);call #Ultimate.allocInit(28, 41);call #Ultimate.allocInit(36, 42);call #Ultimate.allocInit(17, 43);call #Ultimate.allocInit(7, 44);call write~init~int(105, 44, 0, 1);call write~init~int(115, 44, 1, 1);call write~init~int(105, 44, 2, 1);call write~init~int(99, 44, 3, 1);call write~init~int(111, 44, 4, 1);call write~init~int(109, 44, 5, 1);call write~init~int(0, 44, 6, 1);call #Ultimate.allocInit(17, 45);call #Ultimate.allocInit(210, 46);call #Ultimate.allocInit(55, 47);call #Ultimate.allocInit(63, 48);call #Ultimate.allocInit(17, 49);call #Ultimate.allocInit(7, 50);call write~init~int(105, 50, 0, 1);call write~init~int(115, 50, 1, 1);call write~init~int(105, 50, 2, 1);call write~init~int(99, 50, 3, 1);call write~init~int(111, 50, 4, 1);call write~init~int(109, 50, 5, 1);call write~init~int(0, 50, 6, 1);call #Ultimate.allocInit(21, 51);call #Ultimate.allocInit(210, 52);call #Ultimate.allocInit(32, 53);call #Ultimate.allocInit(40, 54);call #Ultimate.allocInit(21, 55);call #Ultimate.allocInit(7, 56);call write~init~int(105, 56, 0, 1);call write~init~int(115, 56, 1, 1);call write~init~int(105, 56, 2, 1);call write~init~int(99, 56, 3, 1);call write~init~int(111, 56, 4, 1);call write~init~int(109, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(11, 57);call #Ultimate.allocInit(210, 58);call #Ultimate.allocInit(35, 59);call #Ultimate.allocInit(35, 60);call #Ultimate.allocInit(69, 61);call #Ultimate.allocInit(7, 62);call write~init~int(105, 62, 0, 1);call write~init~int(115, 62, 1, 1);call write~init~int(105, 62, 2, 1);call write~init~int(99, 62, 3, 1);call write~init~int(111, 62, 4, 1);call write~init~int(109, 62, 5, 1);call write~init~int(0, 62, 6, 1);call #Ultimate.allocInit(11, 63);call #Ultimate.allocInit(210, 64);call #Ultimate.allocInit(10, 65);call #Ultimate.allocInit(10, 66);call #Ultimate.allocInit(35, 67);call #Ultimate.allocInit(7, 68);call write~init~int(45, 68, 0, 1);call write~init~int(68, 68, 1, 1);call write~init~int(111, 68, 2, 1);call write~init~int(110, 68, 3, 1);call write~init~int(101, 68, 4, 1);call write~init~int(10, 68, 5, 1);call write~init~int(0, 68, 6, 1);call #Ultimate.allocInit(11, 69);call #Ultimate.allocInit(13, 70);call #Ultimate.allocInit(13, 71);call #Ultimate.allocInit(12, 72);call #Ultimate.allocInit(12, 73);call #Ultimate.allocInit(20, 74);call #Ultimate.allocInit(66, 75);call #Ultimate.allocInit(41, 76);call #Ultimate.allocInit(69, 77);call #Ultimate.allocInit(51, 78);call #Ultimate.allocInit(32, 79);call #Ultimate.allocInit(49, 80);call #Ultimate.allocInit(18, 81);call #Ultimate.allocInit(30, 82);call #Ultimate.allocInit(7, 83);call write~init~int(73, 83, 0, 1);call write~init~int(83, 83, 1, 1);call write~init~int(73, 83, 2, 1);call write~init~int(67, 83, 3, 1);call write~init~int(111, 83, 4, 1);call write~init~int(109, 83, 5, 1);call write~init~int(0, 83, 6, 1);call #Ultimate.allocInit(58, 84);call #Ultimate.allocInit(7, 85);call write~init~int(73, 85, 0, 1);call write~init~int(83, 85, 1, 1);call write~init~int(73, 85, 2, 1);call write~init~int(67, 85, 3, 1);call write~init~int(111, 85, 4, 1);call write~init~int(109, 85, 5, 1);call write~init~int(0, 85, 6, 1);call #Ultimate.allocInit(63, 86);call #Ultimate.allocInit(35, 87);call #Ultimate.allocInit(5, 88);call write~init~int(116, 88, 0, 1);call write~init~int(116, 88, 1, 1);call write~init~int(121, 88, 2, 1);call write~init~int(77, 88, 3, 1);call write~init~int(0, 88, 4, 1);call #Ultimate.allocInit(7, 89);call write~init~int(105, 89, 0, 1);call write~init~int(115, 89, 1, 1);call write~init~int(105, 89, 2, 1);call write~init~int(99, 89, 3, 1);call write~init~int(111, 89, 4, 1);call write~init~int(109, 89, 5, 1);call write~init~int(0, 89, 6, 1);call #Ultimate.allocInit(12, 90);call #Ultimate.allocInit(210, 91);call #Ultimate.allocInit(37, 92);call #Ultimate.allocInit(45, 93);call #Ultimate.allocInit(7, 94);call write~init~int(105, 94, 0, 1);call write~init~int(115, 94, 1, 1);call write~init~int(105, 94, 2, 1);call write~init~int(99, 94, 3, 1);call write~init~int(111, 94, 4, 1);call write~init~int(109, 94, 5, 1);call write~init~int(0, 94, 6, 1);call #Ultimate.allocInit(41, 95);~ldv_irq_1_3~0 := 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_0~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~ldv_state_variable_5~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~isicom_ops_group1~0.base, ~isicom_ops_group1~0.offset := 0, 0;~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~isicom_ops_group0~0.base, ~isicom_ops_group0~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_line_1_3~0 := 0;~isicom_port_ops_group1~0.base, ~isicom_port_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~ldv_state_variable_4~0 := 0;~isicom_driver_group0~0.base, ~isicom_driver_group0~0.offset := 0, 0;~#isicom_pci_tbl~0.base, ~#isicom_pci_tbl~0.offset := 96, 0;call #Ultimate.allocInit(320, 96);call write~init~int(4277, ~#isicom_pci_tbl~0.base, ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8232, ~#isicom_pci_tbl~0.base, 4 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 8 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 12 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 16 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 20 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 24 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 32 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8273, ~#isicom_pci_tbl~0.base, 36 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 40 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 44 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 48 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 52 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 56 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 64 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8274, ~#isicom_pci_tbl~0.base, 68 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 72 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 76 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 80 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 84 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 88 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 96 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8275, ~#isicom_pci_tbl~0.base, 100 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 104 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 108 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 112 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 116 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 120 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 128 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8276, ~#isicom_pci_tbl~0.base, 132 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 136 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 140 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 144 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 148 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 152 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 160 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8277, ~#isicom_pci_tbl~0.base, 164 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 168 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 172 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 176 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 180 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 184 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 192 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8278, ~#isicom_pci_tbl~0.base, 196 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 200 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 204 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 208 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 212 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 216 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 224 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8279, ~#isicom_pci_tbl~0.base, 228 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 232 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 236 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 240 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 244 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 248 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(4277, ~#isicom_pci_tbl~0.base, 256 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(8280, ~#isicom_pci_tbl~0.base, 260 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 264 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#isicom_pci_tbl~0.base, 268 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 272 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 276 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 280 + ~#isicom_pci_tbl~0.offset, 8);call write~init~int(0, ~#isicom_pci_tbl~0.base, 288 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 292 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 296 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 300 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 304 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 308 + ~#isicom_pci_tbl~0.offset, 4);call write~init~int(0, ~#isicom_pci_tbl~0.base, 312 + ~#isicom_pci_tbl~0.offset, 8);~__mod_pci__isicom_pci_tbl_device_table~0.vendor := 0;~__mod_pci__isicom_pci_tbl_device_table~0.device := 0;~__mod_pci__isicom_pci_tbl_device_table~0.subvendor := 0;~__mod_pci__isicom_pci_tbl_device_table~0.subdevice := 0;~__mod_pci__isicom_pci_tbl_device_table~0.class := 0;~__mod_pci__isicom_pci_tbl_device_table~0.class_mask := 0;~__mod_pci__isicom_pci_tbl_device_table~0.driver_data := 0;~#isicom_driver~0.base, ~#isicom_driver~0.offset := 97, 0;call #Ultimate.allocInit(301, 97);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 8 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(3, 0, ~#isicom_driver~0.base, 16 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(~#isicom_pci_tbl~0.base, ~#isicom_pci_tbl~0.offset, ~#isicom_driver~0.base, 24 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_probe.base, #funAddr~isicom_probe.offset, ~#isicom_driver~0.base, 32 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_remove.base, #funAddr~isicom_remove.offset, ~#isicom_driver~0.base, 40 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 48 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 56 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 64 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 72 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 80 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 88 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 96 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 104 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 112 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 120 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 128 + ~#isicom_driver~0.offset, 8);call write~init~int(0, ~#isicom_driver~0.base, 136 + ~#isicom_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 137 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 145 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 153 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 161 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 169 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 177 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 185 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 193 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 201 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 209 + ~#isicom_driver~0.offset, 8);call write~init~int(0, ~#isicom_driver~0.base, 217 + ~#isicom_driver~0.offset, 4);call write~init~int(0, ~#isicom_driver~0.base, 221 + ~#isicom_driver~0.offset, 4);call write~init~int(0, ~#isicom_driver~0.base, 225 + ~#isicom_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 229 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 237 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 245 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 253 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 261 + ~#isicom_driver~0.offset, 8);call write~init~int(0, ~#isicom_driver~0.base, 269 + ~#isicom_driver~0.offset, 4);call write~init~int(0, ~#isicom_driver~0.base, 273 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 285 + ~#isicom_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_driver~0.base, 293 + ~#isicom_driver~0.offset, 8);~prev_card~0 := 3;~isicom_normal~0.base, ~isicom_normal~0.offset := 0, 0;~#tx~0.base, ~#tx~0.offset := 98, 0;call #Ultimate.allocInit(124, 98);call write~init~$Pointer$(0, 0, ~#tx~0.base, ~#tx~0.offset, 8);call write~init~$Pointer$(0, 1953723489, ~#tx~0.base, 8 + ~#tx~0.offset, 8);call write~init~int(0, ~#tx~0.base, 16 + ~#tx~0.offset, 8);call write~init~$Pointer$(~#boot_tvec_bases~0.base, ~#boot_tvec_bases~0.offset, ~#tx~0.base, 24 + ~#tx~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_tx.base, #funAddr~isicom_tx.offset, ~#tx~0.base, 32 + ~#tx~0.offset, 8);call write~init~int(0, ~#tx~0.base, 40 + ~#tx~0.offset, 8);call write~init~int(-1, ~#tx~0.base, 48 + ~#tx~0.offset, 4);call write~init~int(0, ~#tx~0.base, 52 + ~#tx~0.offset, 4);call write~init~$Pointer$(0, 0, ~#tx~0.base, 56 + ~#tx~0.offset, 8);call write~init~int(0, ~#tx~0.base, 64 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 65 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 66 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 67 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 68 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 69 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 70 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 71 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 72 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 73 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 74 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 75 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 76 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 77 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 78 + ~#tx~0.offset, 1);call write~init~int(0, ~#tx~0.base, 79 + ~#tx~0.offset, 1);call write~init~$Pointer$(4, 0, ~#tx~0.base, 80 + ~#tx~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tx~0.base, 88 + ~#tx~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tx~0.base, 96 + ~#tx~0.offset, 8);call write~init~$Pointer$(5, 0, ~#tx~0.base, 104 + ~#tx~0.offset, 8);call write~init~int(0, ~#tx~0.base, 112 + ~#tx~0.offset, 4);call write~init~int(0, ~#tx~0.base, 116 + ~#tx~0.offset, 8);~#linuxb_to_isib~0.base, ~#linuxb_to_isib~0.offset := 99, 0;call #Ultimate.allocInit(20, 99);call write~init~int(-1, ~#linuxb_to_isib~0.base, ~#linuxb_to_isib~0.offset, 1);call write~init~int(0, ~#linuxb_to_isib~0.base, 1 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(1, ~#linuxb_to_isib~0.base, 2 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(2, ~#linuxb_to_isib~0.base, 3 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(3, ~#linuxb_to_isib~0.base, 4 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(4, ~#linuxb_to_isib~0.base, 5 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(5, ~#linuxb_to_isib~0.base, 6 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(6, ~#linuxb_to_isib~0.base, 7 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(7, ~#linuxb_to_isib~0.base, 8 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(8, ~#linuxb_to_isib~0.base, 9 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(9, ~#linuxb_to_isib~0.base, 10 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(11, ~#linuxb_to_isib~0.base, 11 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(13, ~#linuxb_to_isib~0.base, 12 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(15, ~#linuxb_to_isib~0.base, 13 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(16, ~#linuxb_to_isib~0.base, 14 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(17, ~#linuxb_to_isib~0.base, 15 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(18, ~#linuxb_to_isib~0.base, 16 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(19, ~#linuxb_to_isib~0.base, 17 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(20, ~#linuxb_to_isib~0.base, 18 + ~#linuxb_to_isib~0.offset, 1);call write~init~int(21, ~#linuxb_to_isib~0.base, 19 + ~#linuxb_to_isib~0.offset, 1);~#isi_card~0.base, ~#isi_card~0.offset := 100, 0;call #Ultimate.allocInit(432, 100);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#isi_card~0.base);#memory_$Pointer$.base, #memory_$Pointer$.offset := ~initToZeroAtPointerBaseAddress~$Pointer$.base(#memory_$Pointer$.base, #memory_$Pointer$.offset, ~#isi_card~0.base), ~initToZeroAtPointerBaseAddress~$Pointer$.offset(#memory_$Pointer$.base, #memory_$Pointer$.offset, ~#isi_card~0.base);~#isi_ports~0.base, ~#isi_ports~0.offset := 101, 0;call #Ultimate.allocInit(65792, 101);#memory_$Pointer$.base, #memory_$Pointer$.offset := ~initToZeroAtPointerBaseAddress~$Pointer$.base(#memory_$Pointer$.base, #memory_$Pointer$.offset, ~#isi_ports~0.base), ~initToZeroAtPointerBaseAddress~$Pointer$.offset(#memory_$Pointer$.base, #memory_$Pointer$.offset, ~#isi_ports~0.base);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#isi_ports~0.base);~#isicom_ops~0.base, ~#isicom_ops~0.offset := 102, 0;call #Ultimate.allocInit(272, 102);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 8 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 16 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_open.base, #funAddr~isicom_open.offset, ~#isicom_ops~0.base, 24 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_close.base, #funAddr~isicom_close.offset, ~#isicom_ops~0.base, 32 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 40 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 48 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_write.base, #funAddr~isicom_write.offset, ~#isicom_ops~0.base, 56 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_put_char.base, #funAddr~isicom_put_char.offset, ~#isicom_ops~0.base, 64 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_flush_chars.base, #funAddr~isicom_flush_chars.offset, ~#isicom_ops~0.base, 72 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_write_room.base, #funAddr~isicom_write_room.offset, ~#isicom_ops~0.base, 80 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_chars_in_buffer.base, #funAddr~isicom_chars_in_buffer.offset, ~#isicom_ops~0.base, 88 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_ioctl.base, #funAddr~isicom_ioctl.offset, ~#isicom_ops~0.base, 96 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 104 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_set_termios.base, #funAddr~isicom_set_termios.offset, ~#isicom_ops~0.base, 112 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_throttle.base, #funAddr~isicom_throttle.offset, ~#isicom_ops~0.base, 120 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_unthrottle.base, #funAddr~isicom_unthrottle.offset, ~#isicom_ops~0.base, 128 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_stop.base, #funAddr~isicom_stop.offset, ~#isicom_ops~0.base, 136 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_start.base, #funAddr~isicom_start.offset, ~#isicom_ops~0.base, 144 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_hangup.base, #funAddr~isicom_hangup.offset, ~#isicom_ops~0.base, 152 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_send_break.base, #funAddr~isicom_send_break.offset, ~#isicom_ops~0.base, 160 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_flush_buffer.base, #funAddr~isicom_flush_buffer.offset, ~#isicom_ops~0.base, 168 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 176 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 184 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 192 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_tiocmget.base, #funAddr~isicom_tiocmget.offset, ~#isicom_ops~0.base, 200 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_tiocmset.base, #funAddr~isicom_tiocmset.offset, ~#isicom_ops~0.base, 208 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 216 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 224 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 232 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 240 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 248 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 256 + ~#isicom_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_ops~0.base, 264 + ~#isicom_ops~0.offset, 8);~#isicom_port_ops~0.base, ~#isicom_port_ops~0.offset := 103, 0;call #Ultimate.allocInit(40, 103);call write~init~$Pointer$(#funAddr~isicom_carrier_raised.base, #funAddr~isicom_carrier_raised.offset, ~#isicom_port_ops~0.base, ~#isicom_port_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_dtr_rts.base, #funAddr~isicom_dtr_rts.offset, ~#isicom_port_ops~0.base, 8 + ~#isicom_port_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_shutdown.base, #funAddr~isicom_shutdown.offset, ~#isicom_port_ops~0.base, 16 + ~#isicom_port_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~isicom_activate.base, #funAddr~isicom_activate.offset, ~#isicom_port_ops~0.base, 24 + ~#isicom_port_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#isicom_port_ops~0.base, 32 + ~#isicom_port_ops~0.offset, 8);~card_count~0 := 0;~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_retval_3~0 := 0;~ldv_spin~0 := 0; {15490#true} is VALID [2022-02-20 22:02:41,377 INFO L290 TraceCheckUtils]: 1: Hoare triple {15490#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet658#1, main_#t~nondet659#1, main_#t~ret660#1.base, main_#t~ret660#1.offset, main_#t~nondet661#1, main_#t~nondet662#1, main_#t~nondet663#1, main_#t~ret664#1.base, main_#t~ret664#1.offset, main_#t~nondet665#1, main_#t~nondet666#1, main_#t~nondet667#1, main_#t~nondet668#1, main_#t~ret669#1.base, main_#t~ret669#1.offset, main_#t~ret670#1.base, main_#t~ret670#1.offset, main_#t~nondet671#1, main_#t~switch672#1, main_#t~nondet673#1, main_#t~switch674#1, main_#t~nondet675#1, main_#t~switch676#1, main_#t~ret677#1, main_#t~nondet678#1, main_#t~switch679#1, main_#t~ret680#1, main_#t~ret681#1, main_#t~ret682#1, main_#t~ret683#1, main_#t~ret684#1, main_#t~ret685#1, main_#t~ret686#1, main_#t~ret687#1, main_#t~ret688#1, main_#t~ret689#1, main_#t~ret690#1, main_#t~ret691#1, main_#t~ret692#1, main_#t~ret693#1, main_#t~ret694#1, main_#t~ret695#1, main_#t~ret696#1, main_#t~ret697#1, main_#t~ret698#1, main_#t~ret699#1, main_#t~ret700#1, main_#t~ret701#1, main_#t~ret702#1, main_#t~ret703#1, main_#t~ret704#1, main_#t~ret705#1, main_#t~ret706#1, main_#t~ret707#1, main_#t~ret708#1, main_#t~ret709#1, main_#t~ret710#1, main_#t~ret711#1, main_#t~ret712#1, main_#t~ret713#1, main_#t~ret714#1, main_#t~ret715#1, main_#t~ret716#1, main_#t~ret717#1, main_#t~ret718#1, main_#t~ret719#1, main_#t~ret720#1, main_#t~ret721#1, main_#t~nondet722#1, main_#t~switch723#1, main_#t~ret724#1, main_#t~ret725#1, main_#t~ret726#1, main_#t~ret727#1, main_#t~ret728#1, main_#t~nondet729#1, main_#t~switch730#1, main_#t~ret731#1, main_~ldvarg0~0#1, main_~tmp~41#1, main_~ldvarg7~0#1, main_~tmp___0~17#1, main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset, main_~tmp___1~10#1.base, main_~tmp___1~10#1.offset, main_~ldvarg5~0#1, main_~tmp___2~8#1, main_~ldvarg6~0#1, main_~tmp___3~5#1, main_~ldvarg1~0#1, main_~tmp___4~3#1, main_~ldvarg8~0#1.base, main_~ldvarg8~0#1.offset, main_~tmp___5~2#1.base, main_~tmp___5~2#1.offset, main_~ldvarg4~0#1, main_~tmp___6~2#1, main_~ldvarg9~0#1, main_~tmp___7~2#1, main_~ldvarg2~0#1, main_~tmp___8~1#1, main_~ldvarg11~0#1, main_~tmp___9~0#1, main_~ldvarg10~0#1.base, main_~ldvarg10~0#1.offset, main_~tmp___10~0#1.base, main_~tmp___10~0#1.offset, main_~ldvarg12~0#1.base, main_~ldvarg12~0#1.offset, main_~tmp___11~0#1.base, main_~tmp___11~0#1.offset, main_~tmp___12~0#1, main_~tmp___13~0#1, main_~tmp___14~0#1, main_~tmp___15~0#1, main_~tmp___16~0#1, main_~tmp___17~0#1;havoc main_~ldvarg0~0#1;havoc main_~tmp~41#1;havoc main_~ldvarg7~0#1;havoc main_~tmp___0~17#1;havoc main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset;havoc main_~tmp___1~10#1.base, main_~tmp___1~10#1.offset;havoc main_~ldvarg5~0#1;havoc main_~tmp___2~8#1;havoc main_~ldvarg6~0#1;havoc main_~tmp___3~5#1;havoc main_~ldvarg1~0#1;havoc main_~tmp___4~3#1;havoc main_~ldvarg8~0#1.base, main_~ldvarg8~0#1.offset;havoc main_~tmp___5~2#1.base, main_~tmp___5~2#1.offset;havoc main_~ldvarg4~0#1;havoc main_~tmp___6~2#1;havoc main_~ldvarg9~0#1;havoc main_~tmp___7~2#1;havoc main_~ldvarg2~0#1;havoc main_~tmp___8~1#1;havoc main_~ldvarg11~0#1;havoc main_~tmp___9~0#1;havoc main_~ldvarg10~0#1.base, main_~ldvarg10~0#1.offset;havoc main_~tmp___10~0#1.base, main_~tmp___10~0#1.offset;havoc main_~ldvarg12~0#1.base, main_~ldvarg12~0#1.offset;havoc main_~tmp___11~0#1.base, main_~tmp___11~0#1.offset;havoc main_~tmp___12~0#1;havoc main_~tmp___13~0#1;havoc main_~tmp___14~0#1;havoc main_~tmp___15~0#1;havoc main_~tmp___16~0#1;havoc main_~tmp___17~0#1;main_~tmp~41#1 := main_#t~nondet658#1;havoc main_#t~nondet658#1;main_~ldvarg0~0#1 := main_~tmp~41#1;main_~tmp___0~17#1 := main_#t~nondet659#1;havoc main_#t~nondet659#1;main_~ldvarg7~0#1 := main_~tmp___0~17#1; {15490#true} is VALID [2022-02-20 22:02:41,378 INFO L272 TraceCheckUtils]: 2: Hoare triple {15490#true} call main_#t~ret660#1.base, main_#t~ret660#1.offset := ldv_zalloc(1); {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:41,378 INFO L290 TraceCheckUtils]: 3: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,379 INFO L290 TraceCheckUtils]: 4: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,379 INFO L290 TraceCheckUtils]: 5: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,379 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {15490#true} {15490#true} #3596#return; {15490#true} is VALID [2022-02-20 22:02:41,379 INFO L290 TraceCheckUtils]: 7: Hoare triple {15490#true} main_~tmp___1~10#1.base, main_~tmp___1~10#1.offset := main_#t~ret660#1.base, main_#t~ret660#1.offset;havoc main_#t~ret660#1.base, main_#t~ret660#1.offset;main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset := main_~tmp___1~10#1.base, main_~tmp___1~10#1.offset;main_~tmp___2~8#1 := main_#t~nondet661#1;havoc main_#t~nondet661#1;main_~ldvarg5~0#1 := main_~tmp___2~8#1;main_~tmp___3~5#1 := main_#t~nondet662#1;havoc main_#t~nondet662#1;main_~ldvarg6~0#1 := main_~tmp___3~5#1;assume -2147483648 <= main_#t~nondet663#1 && main_#t~nondet663#1 <= 2147483647;main_~tmp___4~3#1 := main_#t~nondet663#1;havoc main_#t~nondet663#1;main_~ldvarg1~0#1 := main_~tmp___4~3#1; {15490#true} is VALID [2022-02-20 22:02:41,380 INFO L272 TraceCheckUtils]: 8: Hoare triple {15490#true} call main_#t~ret664#1.base, main_#t~ret664#1.offset := ldv_zalloc(44); {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:41,380 INFO L290 TraceCheckUtils]: 9: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,380 INFO L290 TraceCheckUtils]: 10: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,380 INFO L290 TraceCheckUtils]: 11: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,380 INFO L284 TraceCheckUtils]: 12: Hoare quadruple {15490#true} {15490#true} #3598#return; {15490#true} is VALID [2022-02-20 22:02:41,380 INFO L290 TraceCheckUtils]: 13: Hoare triple {15490#true} main_~tmp___5~2#1.base, main_~tmp___5~2#1.offset := main_#t~ret664#1.base, main_#t~ret664#1.offset;havoc main_#t~ret664#1.base, main_#t~ret664#1.offset;main_~ldvarg8~0#1.base, main_~ldvarg8~0#1.offset := main_~tmp___5~2#1.base, main_~tmp___5~2#1.offset;main_~tmp___6~2#1 := main_#t~nondet665#1;havoc main_#t~nondet665#1;main_~ldvarg4~0#1 := main_~tmp___6~2#1;main_~tmp___7~2#1 := main_#t~nondet666#1;havoc main_#t~nondet666#1;main_~ldvarg9~0#1 := main_~tmp___7~2#1;assume -2147483648 <= main_#t~nondet667#1 && main_#t~nondet667#1 <= 2147483647;main_~tmp___8~1#1 := main_#t~nondet667#1;havoc main_#t~nondet667#1;main_~ldvarg2~0#1 := main_~tmp___8~1#1;assume -2147483648 <= main_#t~nondet668#1 && main_#t~nondet668#1 <= 2147483647;main_~tmp___9~0#1 := main_#t~nondet668#1;havoc main_#t~nondet668#1;main_~ldvarg11~0#1 := main_~tmp___9~0#1; {15490#true} is VALID [2022-02-20 22:02:41,381 INFO L272 TraceCheckUtils]: 14: Hoare triple {15490#true} call main_#t~ret669#1.base, main_#t~ret669#1.offset := ldv_zalloc(1752); {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:41,381 INFO L290 TraceCheckUtils]: 15: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,381 INFO L290 TraceCheckUtils]: 16: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,381 INFO L290 TraceCheckUtils]: 17: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,381 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {15490#true} {15490#true} #3600#return; {15490#true} is VALID [2022-02-20 22:02:41,381 INFO L290 TraceCheckUtils]: 19: Hoare triple {15490#true} main_~tmp___10~0#1.base, main_~tmp___10~0#1.offset := main_#t~ret669#1.base, main_#t~ret669#1.offset;havoc main_#t~ret669#1.base, main_#t~ret669#1.offset;main_~ldvarg10~0#1.base, main_~ldvarg10~0#1.offset := main_~tmp___10~0#1.base, main_~tmp___10~0#1.offset; {15490#true} is VALID [2022-02-20 22:02:41,382 INFO L272 TraceCheckUtils]: 20: Hoare triple {15490#true} call main_#t~ret670#1.base, main_#t~ret670#1.offset := ldv_zalloc(32); {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:41,382 INFO L290 TraceCheckUtils]: 21: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,382 INFO L290 TraceCheckUtils]: 22: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,382 INFO L290 TraceCheckUtils]: 23: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,382 INFO L284 TraceCheckUtils]: 24: Hoare quadruple {15490#true} {15490#true} #3602#return; {15490#true} is VALID [2022-02-20 22:02:41,382 INFO L290 TraceCheckUtils]: 25: Hoare triple {15490#true} main_~tmp___11~0#1.base, main_~tmp___11~0#1.offset := main_#t~ret670#1.base, main_#t~ret670#1.offset;havoc main_#t~ret670#1.base, main_#t~ret670#1.offset;main_~ldvarg12~0#1.base, main_~ldvarg12~0#1.offset := main_~tmp___11~0#1.base, main_~tmp___11~0#1.offset;assume { :begin_inline_ldv_initialize } true; {15490#true} is VALID [2022-02-20 22:02:41,383 INFO L290 TraceCheckUtils]: 26: Hoare triple {15490#true} assume { :end_inline_ldv_initialize } true;~ldv_state_variable_4~0 := 0;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_state_variable_5~0 := 0; {15490#true} is VALID [2022-02-20 22:02:41,383 INFO L290 TraceCheckUtils]: 27: Hoare triple {15490#true} assume -2147483648 <= main_#t~nondet671#1 && main_#t~nondet671#1 <= 2147483647;main_~tmp___12~0#1 := main_#t~nondet671#1;havoc main_#t~nondet671#1;main_#t~switch672#1 := 0 == main_~tmp___12~0#1; {15490#true} is VALID [2022-02-20 22:02:41,383 INFO L290 TraceCheckUtils]: 28: Hoare triple {15490#true} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 1 == main_~tmp___12~0#1; {15490#true} is VALID [2022-02-20 22:02:41,383 INFO L290 TraceCheckUtils]: 29: Hoare triple {15490#true} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 2 == main_~tmp___12~0#1; {15490#true} is VALID [2022-02-20 22:02:41,383 INFO L290 TraceCheckUtils]: 30: Hoare triple {15490#true} assume main_#t~switch672#1; {15490#true} is VALID [2022-02-20 22:02:41,383 INFO L290 TraceCheckUtils]: 31: Hoare triple {15490#true} assume 0 != ~ldv_state_variable_0~0;assume -2147483648 <= main_#t~nondet675#1 && main_#t~nondet675#1 <= 2147483647;main_~tmp___14~0#1 := main_#t~nondet675#1;havoc main_#t~nondet675#1;main_#t~switch676#1 := 0 == main_~tmp___14~0#1; {15490#true} is VALID [2022-02-20 22:02:41,383 INFO L290 TraceCheckUtils]: 32: Hoare triple {15490#true} assume !main_#t~switch676#1;main_#t~switch676#1 := main_#t~switch676#1 || 1 == main_~tmp___14~0#1; {15490#true} is VALID [2022-02-20 22:02:41,384 INFO L290 TraceCheckUtils]: 33: Hoare triple {15490#true} assume main_#t~switch676#1; {15490#true} is VALID [2022-02-20 22:02:41,385 INFO L290 TraceCheckUtils]: 34: Hoare triple {15490#true} assume 1 == ~ldv_state_variable_0~0;assume { :begin_inline_isicom_init } true;havoc isicom_init_#res#1;havoc isicom_init_#t~ret606#1.base, isicom_init_#t~ret606#1.offset, isicom_init_#t~ret607#1.base, isicom_init_#t~ret607#1.offset, isicom_init_#t~mem608#1, isicom_init_#t~mem609#1, isicom_init_#t~mem610#1, isicom_init_#t~mem611#1, isicom_init_#t~mem612#1, isicom_init_#t~arrayCopy613#1, isicom_init_#t~mem614#1, isicom_init_#t~mem615#1, isicom_init_#t~mem616#1, isicom_init_#t~mem617#1, isicom_init_#t~mem618#1, isicom_init_#t~mem619#1, isicom_init_#t~mem620#1, isicom_init_#t~mem621#1, isicom_init_#t~mem622#1, isicom_init_#t~mem623#1, isicom_init_#t~mem624#1, isicom_init_#t~mem625#1, isicom_init_#t~mem626#1, isicom_init_#t~mem627#1, isicom_init_#t~mem628#1, isicom_init_#t~mem629#1, isicom_init_#t~mem630#1, isicom_init_#t~mem631#1, isicom_init_#t~mem632#1, isicom_init_#t~mem633#1, isicom_init_#t~mem634#1, isicom_init_#t~ret635#1, isicom_init_#t~mem636#1, isicom_init_#t~ret637#1, isicom_init_#t~nondet638#1, isicom_init_#t~ret639#1, isicom_init_#t~nondet640#1, isicom_init_#t~ret641#1, isicom_init_#t~ret642#1, isicom_init_~retval~3#1, isicom_init_~idx~0#1, isicom_init_~channel~9#1, isicom_init_~port~25#1.base, isicom_init_~port~25#1.offset, isicom_init_~#__key~0#1.base, isicom_init_~#__key~0#1.offset, isicom_init_~#descriptor~4#1.base, isicom_init_~#descriptor~4#1.offset, isicom_init_~tmp~35#1;havoc isicom_init_~retval~3#1;havoc isicom_init_~idx~0#1;havoc isicom_init_~channel~9#1;havoc isicom_init_~port~25#1.base, isicom_init_~port~25#1.offset;call isicom_init_~#__key~0#1.base, isicom_init_~#__key~0#1.offset := #Ultimate.allocOnStack(8);call isicom_init_~#descriptor~4#1.base, isicom_init_~#descriptor~4#1.offset := #Ultimate.allocOnStack(37);havoc isicom_init_~tmp~35#1;isicom_init_~idx~0#1 := 0; {15508#(= |ULTIMATE.start_isicom_init_~idx~0#1| 0)} is VALID [2022-02-20 22:02:41,385 INFO L290 TraceCheckUtils]: 35: Hoare triple {15508#(= |ULTIMATE.start_isicom_init_~idx~0#1| 0)} assume !(isicom_init_~idx~0#1 <= 3);assume { :begin_inline_alloc_tty_driver } true;alloc_tty_driver_#in~lines#1 := 64;havoc alloc_tty_driver_#res#1.base, alloc_tty_driver_#res#1.offset;havoc alloc_tty_driver_#t~ret71#1.base, alloc_tty_driver_#t~ret71#1.offset, alloc_tty_driver_#t~ret72#1, alloc_tty_driver_~lines#1, alloc_tty_driver_~ret~0#1.base, alloc_tty_driver_~ret~0#1.offset, alloc_tty_driver_~tmp~7#1.base, alloc_tty_driver_~tmp~7#1.offset, alloc_tty_driver_~tmp___0~4#1;alloc_tty_driver_~lines#1 := alloc_tty_driver_#in~lines#1;havoc alloc_tty_driver_~ret~0#1.base, alloc_tty_driver_~ret~0#1.offset;havoc alloc_tty_driver_~tmp~7#1.base, alloc_tty_driver_~tmp~7#1.offset;havoc alloc_tty_driver_~tmp___0~4#1;assume { :begin_inline___tty_alloc_driver } true;__tty_alloc_driver_#in~arg0#1, __tty_alloc_driver_#in~arg1#1.base, __tty_alloc_driver_#in~arg1#1.offset, __tty_alloc_driver_#in~arg2#1 := alloc_tty_driver_~lines#1, ~#__this_module~0.base, ~#__this_module~0.offset, 0;havoc __tty_alloc_driver_#res#1.base, __tty_alloc_driver_#res#1.offset;havoc __tty_alloc_driver_#t~ret740#1.base, __tty_alloc_driver_#t~ret740#1.offset, __tty_alloc_driver_~arg0#1, __tty_alloc_driver_~arg1#1.base, __tty_alloc_driver_~arg1#1.offset, __tty_alloc_driver_~arg2#1;__tty_alloc_driver_~arg0#1 := __tty_alloc_driver_#in~arg0#1;__tty_alloc_driver_~arg1#1.base, __tty_alloc_driver_~arg1#1.offset := __tty_alloc_driver_#in~arg1#1.base, __tty_alloc_driver_#in~arg1#1.offset;__tty_alloc_driver_~arg2#1 := __tty_alloc_driver_#in~arg2#1; {15491#false} is VALID [2022-02-20 22:02:41,385 INFO L272 TraceCheckUtils]: 36: Hoare triple {15491#false} call __tty_alloc_driver_#t~ret740#1.base, __tty_alloc_driver_#t~ret740#1.offset := ldv_malloc(184); {15622#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:41,385 INFO L290 TraceCheckUtils]: 37: Hoare triple {15622#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~1.base, ~tmp~1.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet36 && #t~nondet36 <= 2147483647;~tmp___0~0 := #t~nondet36;havoc #t~nondet36; {15490#true} is VALID [2022-02-20 22:02:41,386 INFO L290 TraceCheckUtils]: 38: Hoare triple {15490#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,386 INFO L290 TraceCheckUtils]: 39: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,386 INFO L284 TraceCheckUtils]: 40: Hoare quadruple {15490#true} {15491#false} #3650#return; {15491#false} is VALID [2022-02-20 22:02:41,386 INFO L290 TraceCheckUtils]: 41: Hoare triple {15491#false} __tty_alloc_driver_#res#1.base, __tty_alloc_driver_#res#1.offset := __tty_alloc_driver_#t~ret740#1.base, __tty_alloc_driver_#t~ret740#1.offset;havoc __tty_alloc_driver_#t~ret740#1.base, __tty_alloc_driver_#t~ret740#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,386 INFO L290 TraceCheckUtils]: 42: Hoare triple {15491#false} alloc_tty_driver_#t~ret71#1.base, alloc_tty_driver_#t~ret71#1.offset := __tty_alloc_driver_#res#1.base, __tty_alloc_driver_#res#1.offset;assume { :end_inline___tty_alloc_driver } true;alloc_tty_driver_~tmp~7#1.base, alloc_tty_driver_~tmp~7#1.offset := alloc_tty_driver_#t~ret71#1.base, alloc_tty_driver_#t~ret71#1.offset;havoc alloc_tty_driver_#t~ret71#1.base, alloc_tty_driver_#t~ret71#1.offset;alloc_tty_driver_~ret~0#1.base, alloc_tty_driver_~ret~0#1.offset := alloc_tty_driver_~tmp~7#1.base, alloc_tty_driver_~tmp~7#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,386 INFO L272 TraceCheckUtils]: 43: Hoare triple {15491#false} call alloc_tty_driver_#t~ret72#1 := IS_ERR(alloc_tty_driver_~ret~0#1.base, alloc_tty_driver_~ret~0#1.offset); {15490#true} is VALID [2022-02-20 22:02:41,386 INFO L290 TraceCheckUtils]: 44: Hoare triple {15490#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;havoc ~tmp~0; {15490#true} is VALID [2022-02-20 22:02:41,386 INFO L272 TraceCheckUtils]: 45: Hoare triple {15490#true} call #t~ret10 := ldv__builtin_expect((if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 18446744073709547520 then 1 else 0), 0); {15490#true} is VALID [2022-02-20 22:02:41,387 INFO L290 TraceCheckUtils]: 46: Hoare triple {15490#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {15490#true} is VALID [2022-02-20 22:02:41,387 INFO L290 TraceCheckUtils]: 47: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,387 INFO L284 TraceCheckUtils]: 48: Hoare quadruple {15490#true} {15490#true} #4020#return; {15490#true} is VALID [2022-02-20 22:02:41,387 INFO L290 TraceCheckUtils]: 49: Hoare triple {15490#true} assume -9223372036854775808 <= #t~ret10 && #t~ret10 <= 9223372036854775807;~tmp~0 := #t~ret10;havoc #t~ret10;#res := (if 0 == (if 0 != ~tmp~0 then 1 else 0) then 0 else 1); {15490#true} is VALID [2022-02-20 22:02:41,387 INFO L290 TraceCheckUtils]: 50: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,387 INFO L284 TraceCheckUtils]: 51: Hoare quadruple {15490#true} {15491#false} #3652#return; {15491#false} is VALID [2022-02-20 22:02:41,387 INFO L290 TraceCheckUtils]: 52: Hoare triple {15491#false} alloc_tty_driver_~tmp___0~4#1 := alloc_tty_driver_#t~ret72#1;havoc alloc_tty_driver_#t~ret72#1; {15491#false} is VALID [2022-02-20 22:02:41,387 INFO L290 TraceCheckUtils]: 53: Hoare triple {15491#false} assume 0 != alloc_tty_driver_~tmp___0~4#1 % 256;alloc_tty_driver_#res#1.base, alloc_tty_driver_#res#1.offset := 0, 0; {15491#false} is VALID [2022-02-20 22:02:41,388 INFO L290 TraceCheckUtils]: 54: Hoare triple {15491#false} isicom_init_#t~ret607#1.base, isicom_init_#t~ret607#1.offset := alloc_tty_driver_#res#1.base, alloc_tty_driver_#res#1.offset;assume { :end_inline_alloc_tty_driver } true;~isicom_normal~0.base, ~isicom_normal~0.offset := isicom_init_#t~ret607#1.base, isicom_init_#t~ret607#1.offset;havoc isicom_init_#t~ret607#1.base, isicom_init_#t~ret607#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,388 INFO L290 TraceCheckUtils]: 55: Hoare triple {15491#false} assume 0 == (~isicom_normal~0.base + ~isicom_normal~0.offset) % 18446744073709551616;isicom_init_~retval~3#1 := -12; {15491#false} is VALID [2022-02-20 22:02:41,388 INFO L290 TraceCheckUtils]: 56: Hoare triple {15491#false} isicom_init_#res#1 := isicom_init_~retval~3#1;call ULTIMATE.dealloc(isicom_init_~#__key~0#1.base, isicom_init_~#__key~0#1.offset);havoc isicom_init_~#__key~0#1.base, isicom_init_~#__key~0#1.offset;call ULTIMATE.dealloc(isicom_init_~#descriptor~4#1.base, isicom_init_~#descriptor~4#1.offset);havoc isicom_init_~#descriptor~4#1.base, isicom_init_~#descriptor~4#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,390 INFO L290 TraceCheckUtils]: 57: Hoare triple {15491#false} main_#t~ret677#1 := isicom_init_#res#1;assume { :end_inline_isicom_init } true;assume -2147483648 <= main_#t~ret677#1 && main_#t~ret677#1 <= 2147483647;~ldv_retval_0~0 := main_#t~ret677#1;havoc main_#t~ret677#1; {15491#false} is VALID [2022-02-20 22:02:41,390 INFO L290 TraceCheckUtils]: 58: Hoare triple {15491#false} assume 0 == ~ldv_retval_0~0;~ldv_state_variable_0~0 := 3;~ldv_state_variable_5~0 := 1;assume { :begin_inline_ldv_initialize_pci_driver_5 } true;havoc ldv_initialize_pci_driver_5_#t~ret647#1.base, ldv_initialize_pci_driver_5_#t~ret647#1.offset, ldv_initialize_pci_driver_5_~tmp~37#1.base, ldv_initialize_pci_driver_5_~tmp~37#1.offset;havoc ldv_initialize_pci_driver_5_~tmp~37#1.base, ldv_initialize_pci_driver_5_~tmp~37#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,391 INFO L272 TraceCheckUtils]: 59: Hoare triple {15491#false} call ldv_initialize_pci_driver_5_#t~ret647#1.base, ldv_initialize_pci_driver_5_#t~ret647#1.offset := ldv_zalloc(2976); {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:41,391 INFO L290 TraceCheckUtils]: 60: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,391 INFO L290 TraceCheckUtils]: 61: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,391 INFO L290 TraceCheckUtils]: 62: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,391 INFO L284 TraceCheckUtils]: 63: Hoare quadruple {15490#true} {15491#false} #3662#return; {15491#false} is VALID [2022-02-20 22:02:41,391 INFO L290 TraceCheckUtils]: 64: Hoare triple {15491#false} ldv_initialize_pci_driver_5_~tmp~37#1.base, ldv_initialize_pci_driver_5_~tmp~37#1.offset := ldv_initialize_pci_driver_5_#t~ret647#1.base, ldv_initialize_pci_driver_5_#t~ret647#1.offset;havoc ldv_initialize_pci_driver_5_#t~ret647#1.base, ldv_initialize_pci_driver_5_#t~ret647#1.offset;~isicom_driver_group0~0.base, ~isicom_driver_group0~0.offset := ldv_initialize_pci_driver_5_~tmp~37#1.base, ldv_initialize_pci_driver_5_~tmp~37#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,391 INFO L290 TraceCheckUtils]: 65: Hoare triple {15491#false} assume { :end_inline_ldv_initialize_pci_driver_5 } true;~ldv_state_variable_2~0 := 1;assume { :begin_inline_ldv_tty_port_operations_2 } true;havoc ldv_tty_port_operations_2_#t~ret657#1.base, ldv_tty_port_operations_2_#t~ret657#1.offset, ldv_tty_port_operations_2_~tmp~40#1.base, ldv_tty_port_operations_2_~tmp~40#1.offset;havoc ldv_tty_port_operations_2_~tmp~40#1.base, ldv_tty_port_operations_2_~tmp~40#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,391 INFO L272 TraceCheckUtils]: 66: Hoare triple {15491#false} call ldv_tty_port_operations_2_#t~ret657#1.base, ldv_tty_port_operations_2_#t~ret657#1.offset := ldv_zalloc(1064); {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:41,392 INFO L290 TraceCheckUtils]: 67: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,392 INFO L290 TraceCheckUtils]: 68: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,392 INFO L290 TraceCheckUtils]: 69: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,392 INFO L284 TraceCheckUtils]: 70: Hoare quadruple {15490#true} {15491#false} #3664#return; {15491#false} is VALID [2022-02-20 22:02:41,392 INFO L290 TraceCheckUtils]: 71: Hoare triple {15491#false} ldv_tty_port_operations_2_~tmp~40#1.base, ldv_tty_port_operations_2_~tmp~40#1.offset := ldv_tty_port_operations_2_#t~ret657#1.base, ldv_tty_port_operations_2_#t~ret657#1.offset;havoc ldv_tty_port_operations_2_#t~ret657#1.base, ldv_tty_port_operations_2_#t~ret657#1.offset;~isicom_port_ops_group1~0.base, ~isicom_port_ops_group1~0.offset := ldv_tty_port_operations_2_~tmp~40#1.base, ldv_tty_port_operations_2_~tmp~40#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,392 INFO L290 TraceCheckUtils]: 72: Hoare triple {15491#false} assume { :end_inline_ldv_tty_port_operations_2 } true;~ldv_state_variable_3~0 := 1;assume { :begin_inline_ldv_initialize_tty_operations_3 } true;havoc ldv_initialize_tty_operations_3_#t~ret645#1.base, ldv_initialize_tty_operations_3_#t~ret645#1.offset, ldv_initialize_tty_operations_3_#t~ret646#1.base, ldv_initialize_tty_operations_3_#t~ret646#1.offset, ldv_initialize_tty_operations_3_~tmp~36#1.base, ldv_initialize_tty_operations_3_~tmp~36#1.offset, ldv_initialize_tty_operations_3_~tmp___0~16#1.base, ldv_initialize_tty_operations_3_~tmp___0~16#1.offset;havoc ldv_initialize_tty_operations_3_~tmp~36#1.base, ldv_initialize_tty_operations_3_~tmp~36#1.offset;havoc ldv_initialize_tty_operations_3_~tmp___0~16#1.base, ldv_initialize_tty_operations_3_~tmp___0~16#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,392 INFO L272 TraceCheckUtils]: 73: Hoare triple {15491#false} call ldv_initialize_tty_operations_3_#t~ret645#1.base, ldv_initialize_tty_operations_3_#t~ret645#1.offset := ldv_zalloc(512); {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:41,392 INFO L290 TraceCheckUtils]: 74: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,393 INFO L290 TraceCheckUtils]: 75: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,393 INFO L290 TraceCheckUtils]: 76: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,393 INFO L284 TraceCheckUtils]: 77: Hoare quadruple {15490#true} {15491#false} #3666#return; {15491#false} is VALID [2022-02-20 22:02:41,393 INFO L290 TraceCheckUtils]: 78: Hoare triple {15491#false} ldv_initialize_tty_operations_3_~tmp~36#1.base, ldv_initialize_tty_operations_3_~tmp~36#1.offset := ldv_initialize_tty_operations_3_#t~ret645#1.base, ldv_initialize_tty_operations_3_#t~ret645#1.offset;havoc ldv_initialize_tty_operations_3_#t~ret645#1.base, ldv_initialize_tty_operations_3_#t~ret645#1.offset;~isicom_ops_group0~0.base, ~isicom_ops_group0~0.offset := ldv_initialize_tty_operations_3_~tmp~36#1.base, ldv_initialize_tty_operations_3_~tmp~36#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,393 INFO L272 TraceCheckUtils]: 79: Hoare triple {15491#false} call ldv_initialize_tty_operations_3_#t~ret646#1.base, ldv_initialize_tty_operations_3_#t~ret646#1.offset := ldv_zalloc(1752); {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:02:41,393 INFO L290 TraceCheckUtils]: 80: Hoare triple {15621#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~2#1.base, ~tmp~2#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet39#1 && #t~nondet39#1 <= 2147483647;~tmp___0~1#1 := #t~nondet39#1;havoc #t~nondet39#1; {15490#true} is VALID [2022-02-20 22:02:41,393 INFO L290 TraceCheckUtils]: 81: Hoare triple {15490#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {15490#true} is VALID [2022-02-20 22:02:41,394 INFO L290 TraceCheckUtils]: 82: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,394 INFO L284 TraceCheckUtils]: 83: Hoare quadruple {15490#true} {15491#false} #3668#return; {15491#false} is VALID [2022-02-20 22:02:41,394 INFO L290 TraceCheckUtils]: 84: Hoare triple {15491#false} ldv_initialize_tty_operations_3_~tmp___0~16#1.base, ldv_initialize_tty_operations_3_~tmp___0~16#1.offset := ldv_initialize_tty_operations_3_#t~ret646#1.base, ldv_initialize_tty_operations_3_#t~ret646#1.offset;havoc ldv_initialize_tty_operations_3_#t~ret646#1.base, ldv_initialize_tty_operations_3_#t~ret646#1.offset;~isicom_ops_group1~0.base, ~isicom_ops_group1~0.offset := ldv_initialize_tty_operations_3_~tmp___0~16#1.base, ldv_initialize_tty_operations_3_~tmp___0~16#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,394 INFO L290 TraceCheckUtils]: 85: Hoare triple {15491#false} assume { :end_inline_ldv_initialize_tty_operations_3 } true;~ldv_state_variable_4~0 := 1; {15491#false} is VALID [2022-02-20 22:02:41,394 INFO L290 TraceCheckUtils]: 86: Hoare triple {15491#false} assume !(0 != ~ldv_retval_0~0); {15491#false} is VALID [2022-02-20 22:02:41,394 INFO L290 TraceCheckUtils]: 87: Hoare triple {15491#false} assume -2147483648 <= main_#t~nondet671#1 && main_#t~nondet671#1 <= 2147483647;main_~tmp___12~0#1 := main_#t~nondet671#1;havoc main_#t~nondet671#1;main_#t~switch672#1 := 0 == main_~tmp___12~0#1; {15491#false} is VALID [2022-02-20 22:02:41,394 INFO L290 TraceCheckUtils]: 88: Hoare triple {15491#false} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 1 == main_~tmp___12~0#1; {15491#false} is VALID [2022-02-20 22:02:41,394 INFO L290 TraceCheckUtils]: 89: Hoare triple {15491#false} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 2 == main_~tmp___12~0#1; {15491#false} is VALID [2022-02-20 22:02:41,395 INFO L290 TraceCheckUtils]: 90: Hoare triple {15491#false} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 3 == main_~tmp___12~0#1; {15491#false} is VALID [2022-02-20 22:02:41,395 INFO L290 TraceCheckUtils]: 91: Hoare triple {15491#false} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 4 == main_~tmp___12~0#1; {15491#false} is VALID [2022-02-20 22:02:41,395 INFO L290 TraceCheckUtils]: 92: Hoare triple {15491#false} assume !main_#t~switch672#1;main_#t~switch672#1 := main_#t~switch672#1 || 5 == main_~tmp___12~0#1; {15491#false} is VALID [2022-02-20 22:02:41,395 INFO L290 TraceCheckUtils]: 93: Hoare triple {15491#false} assume main_#t~switch672#1; {15491#false} is VALID [2022-02-20 22:02:41,395 INFO L290 TraceCheckUtils]: 94: Hoare triple {15491#false} assume 0 != ~ldv_state_variable_5~0;assume -2147483648 <= main_#t~nondet729#1 && main_#t~nondet729#1 <= 2147483647;main_~tmp___17~0#1 := main_#t~nondet729#1;havoc main_#t~nondet729#1;main_#t~switch730#1 := 0 == main_~tmp___17~0#1; {15491#false} is VALID [2022-02-20 22:02:41,395 INFO L290 TraceCheckUtils]: 95: Hoare triple {15491#false} assume main_#t~switch730#1; {15491#false} is VALID [2022-02-20 22:02:41,395 INFO L290 TraceCheckUtils]: 96: Hoare triple {15491#false} assume 1 == ~ldv_state_variable_5~0;assume { :begin_inline_isicom_probe } true;isicom_probe_#in~pdev#1.base, isicom_probe_#in~pdev#1.offset, isicom_probe_#in~ent#1.base, isicom_probe_#in~ent#1.offset := ~isicom_driver_group0~0.base, ~isicom_driver_group0~0.offset, main_~ldvarg12~0#1.base, main_~ldvarg12~0#1.offset;havoc isicom_probe_#res#1;havoc isicom_probe_#t~mem577#1, isicom_probe_#t~ret578#1, isicom_probe_#t~nondet579#1, isicom_probe_#t~nondet580#1, isicom_probe_#t~mem581#1, isicom_probe_#t~mem582#1, isicom_probe_#t~mem583#1, isicom_probe_#t~mem584#1, isicom_probe_#t~ret585#1, isicom_probe_#t~nondet586#1, isicom_probe_#t~mem587#1, isicom_probe_#t~mem588#1, isicom_probe_#t~mem589#1, isicom_probe_#t~ret590#1, isicom_probe_#t~nondet591#1, isicom_probe_#t~mem592#1, isicom_probe_#t~ret593#1, isicom_probe_#t~mem594#1, isicom_probe_#t~ret595#1, isicom_probe_#t~mem596#1.base, isicom_probe_#t~mem596#1.offset, isicom_probe_#t~mem597#1, isicom_probe_#t~ret598#1.base, isicom_probe_#t~ret598#1.offset, isicom_probe_#t~mem599#1, isicom_probe_#t~mem600#1, isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, isicom_probe_~ent#1.base, isicom_probe_~ent#1.offset, isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset, isicom_probe_~index~0#1, isicom_probe_~retval~2#1, isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset, isicom_probe_~tport~1#1.base, isicom_probe_~tport~1#1.offset;isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset := isicom_probe_#in~pdev#1.base, isicom_probe_#in~pdev#1.offset;isicom_probe_~ent#1.base, isicom_probe_~ent#1.offset := isicom_probe_#in~ent#1.base, isicom_probe_#in~ent#1.offset;call isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset := #Ultimate.allocOnStack(4);havoc isicom_probe_~index~0#1;havoc isicom_probe_~retval~2#1;havoc isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset;havoc isicom_probe_~tport~1#1.base, isicom_probe_~tport~1#1.offset;call isicom_probe_#t~mem577#1 := read~int(isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset, 4);call write~int(isicom_probe_#t~mem577#1, isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset, 4);havoc isicom_probe_#t~mem577#1;isicom_probe_~retval~2#1 := -1;isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset := 0, 0; {15491#false} is VALID [2022-02-20 22:02:41,395 INFO L290 TraceCheckUtils]: 97: Hoare triple {15491#false} assume !(~card_count~0 % 4294967296 > 3);assume { :begin_inline_pci_enable_device } true;pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset;havoc pci_enable_device_#res#1;havoc pci_enable_device_#t~nondet756#1, pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset;pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset := pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset;assume -2147483648 <= pci_enable_device_#t~nondet756#1 && pci_enable_device_#t~nondet756#1 <= 2147483647;pci_enable_device_#res#1 := pci_enable_device_#t~nondet756#1;havoc pci_enable_device_#t~nondet756#1; {15491#false} is VALID [2022-02-20 22:02:41,396 INFO L290 TraceCheckUtils]: 98: Hoare triple {15491#false} isicom_probe_#t~ret578#1 := pci_enable_device_#res#1;assume { :end_inline_pci_enable_device } true;assume -2147483648 <= isicom_probe_#t~ret578#1 && isicom_probe_#t~ret578#1 <= 2147483647;isicom_probe_~retval~2#1 := isicom_probe_#t~ret578#1;havoc isicom_probe_#t~ret578#1; {15491#false} is VALID [2022-02-20 22:02:41,396 INFO L290 TraceCheckUtils]: 99: Hoare triple {15491#false} assume !(0 != isicom_probe_~retval~2#1);havoc isicom_probe_#t~nondet580#1;call isicom_probe_#t~mem581#1 := read~int(isicom_probe_~ent#1.base, 4 + isicom_probe_~ent#1.offset, 4);havoc isicom_probe_#t~mem581#1;isicom_probe_~index~0#1 := 0; {15491#false} is VALID [2022-02-20 22:02:41,396 INFO L290 TraceCheckUtils]: 100: Hoare triple {15491#false} assume !(isicom_probe_~index~0#1 % 4294967296 <= 3); {15491#false} is VALID [2022-02-20 22:02:41,396 INFO L290 TraceCheckUtils]: 101: Hoare triple {15491#false} assume !(4 == isicom_probe_~index~0#1 % 4294967296);call write~int(isicom_probe_~index~0#1, isicom_probe_~board~3#1.base, 104 + isicom_probe_~board~3#1.offset, 4);call isicom_probe_#t~mem583#1 := read~int(isicom_probe_~pdev#1.base, 1668 + isicom_probe_~pdev#1.offset, 8);call write~int(isicom_probe_#t~mem583#1, isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset, 8);havoc isicom_probe_#t~mem583#1;call isicom_probe_#t~mem584#1 := read~int(isicom_probe_~pdev#1.base, 1496 + isicom_probe_~pdev#1.offset, 4);call write~int((if isicom_probe_#t~mem584#1 % 4294967296 % 4294967296 <= 2147483647 then isicom_probe_#t~mem584#1 % 4294967296 % 4294967296 else isicom_probe_#t~mem584#1 % 4294967296 % 4294967296 - 4294967296), isicom_probe_~board~3#1.base, 8 + isicom_probe_~board~3#1.offset, 4);havoc isicom_probe_#t~mem584#1;~card_count~0 := 1 + ~card_count~0;assume { :begin_inline_pci_set_drvdata } true;pci_set_drvdata_#in~pdev#1.base, pci_set_drvdata_#in~pdev#1.offset, pci_set_drvdata_#in~data#1.base, pci_set_drvdata_#in~data#1.offset := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset;havoc pci_set_drvdata_~pdev#1.base, pci_set_drvdata_~pdev#1.offset, pci_set_drvdata_~data#1.base, pci_set_drvdata_~data#1.offset;pci_set_drvdata_~pdev#1.base, pci_set_drvdata_~pdev#1.offset := pci_set_drvdata_#in~pdev#1.base, pci_set_drvdata_#in~pdev#1.offset;pci_set_drvdata_~data#1.base, pci_set_drvdata_~data#1.offset := pci_set_drvdata_#in~data#1.base, pci_set_drvdata_#in~data#1.offset;assume { :begin_inline_dev_set_drvdata } true;dev_set_drvdata_#in~dev#1.base, dev_set_drvdata_#in~dev#1.offset, dev_set_drvdata_#in~data#1.base, dev_set_drvdata_#in~data#1.offset := pci_set_drvdata_~pdev#1.base, 147 + pci_set_drvdata_~pdev#1.offset, pci_set_drvdata_~data#1.base, pci_set_drvdata_~data#1.offset;havoc dev_set_drvdata_~dev#1.base, dev_set_drvdata_~dev#1.offset, dev_set_drvdata_~data#1.base, dev_set_drvdata_~data#1.offset;dev_set_drvdata_~dev#1.base, dev_set_drvdata_~dev#1.offset := dev_set_drvdata_#in~dev#1.base, dev_set_drvdata_#in~dev#1.offset;dev_set_drvdata_~data#1.base, dev_set_drvdata_~data#1.offset := dev_set_drvdata_#in~data#1.base, dev_set_drvdata_#in~data#1.offset;call write~$Pointer$(dev_set_drvdata_~data#1.base, dev_set_drvdata_~data#1.offset, dev_set_drvdata_~dev#1.base, 489 + dev_set_drvdata_~dev#1.offset, 8); {15491#false} is VALID [2022-02-20 22:02:41,396 INFO L290 TraceCheckUtils]: 102: Hoare triple {15491#false} assume { :end_inline_dev_set_drvdata } true; {15491#false} is VALID [2022-02-20 22:02:41,396 INFO L290 TraceCheckUtils]: 103: Hoare triple {15491#false} assume { :end_inline_pci_set_drvdata } true;assume { :begin_inline_pci_request_region } true;pci_request_region_#in~arg0#1.base, pci_request_region_#in~arg0#1.offset, pci_request_region_#in~arg1#1, pci_request_region_#in~arg2#1.base, pci_request_region_#in~arg2#1.offset := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, 3, 83, 0;havoc pci_request_region_#res#1;havoc pci_request_region_#t~nondet757#1, pci_request_region_~arg0#1.base, pci_request_region_~arg0#1.offset, pci_request_region_~arg1#1, pci_request_region_~arg2#1.base, pci_request_region_~arg2#1.offset;pci_request_region_~arg0#1.base, pci_request_region_~arg0#1.offset := pci_request_region_#in~arg0#1.base, pci_request_region_#in~arg0#1.offset;pci_request_region_~arg1#1 := pci_request_region_#in~arg1#1;pci_request_region_~arg2#1.base, pci_request_region_~arg2#1.offset := pci_request_region_#in~arg2#1.base, pci_request_region_#in~arg2#1.offset;assume -2147483648 <= pci_request_region_#t~nondet757#1 && pci_request_region_#t~nondet757#1 <= 2147483647;pci_request_region_#res#1 := pci_request_region_#t~nondet757#1;havoc pci_request_region_#t~nondet757#1; {15491#false} is VALID [2022-02-20 22:02:41,396 INFO L290 TraceCheckUtils]: 104: Hoare triple {15491#false} isicom_probe_#t~ret585#1 := pci_request_region_#res#1;assume { :end_inline_pci_request_region } true;assume -2147483648 <= isicom_probe_#t~ret585#1 && isicom_probe_#t~ret585#1 <= 2147483647;isicom_probe_~retval~2#1 := isicom_probe_#t~ret585#1;havoc isicom_probe_#t~ret585#1; {15491#false} is VALID [2022-02-20 22:02:41,396 INFO L290 TraceCheckUtils]: 105: Hoare triple {15491#false} assume !(0 != isicom_probe_~retval~2#1);call isicom_probe_#t~mem589#1 := read~int(isicom_probe_~board~3#1.base, 8 + isicom_probe_~board~3#1.offset, 4);assume { :begin_inline_ldv_request_irq_20 } true;ldv_request_irq_20_#in~irq#1, ldv_request_irq_20_#in~handler#1.base, ldv_request_irq_20_#in~handler#1.offset, ldv_request_irq_20_#in~flags#1, ldv_request_irq_20_#in~name#1.base, ldv_request_irq_20_#in~name#1.offset, ldv_request_irq_20_#in~dev#1.base, ldv_request_irq_20_#in~dev#1.offset := isicom_probe_#t~mem589#1, #funAddr~isicom_interrupt.base, #funAddr~isicom_interrupt.offset, 128, 85, 0, isicom_probe_~board~3#1.base, isicom_probe_~board~3#1.offset;havoc ldv_request_irq_20_#res#1;havoc ldv_request_irq_20_#t~ret733#1, ldv_request_irq_20_#t~ret734#1, ldv_request_irq_20_~irq#1, ldv_request_irq_20_~handler#1.base, ldv_request_irq_20_~handler#1.offset, ldv_request_irq_20_~flags#1, ldv_request_irq_20_~name#1.base, ldv_request_irq_20_~name#1.offset, ldv_request_irq_20_~dev#1.base, ldv_request_irq_20_~dev#1.offset, ldv_request_irq_20_~ldv_func_res~0#1, ldv_request_irq_20_~tmp~42#1, ldv_request_irq_20_~tmp___0~18#1;ldv_request_irq_20_~irq#1 := ldv_request_irq_20_#in~irq#1;ldv_request_irq_20_~handler#1.base, ldv_request_irq_20_~handler#1.offset := ldv_request_irq_20_#in~handler#1.base, ldv_request_irq_20_#in~handler#1.offset;ldv_request_irq_20_~flags#1 := ldv_request_irq_20_#in~flags#1;ldv_request_irq_20_~name#1.base, ldv_request_irq_20_~name#1.offset := ldv_request_irq_20_#in~name#1.base, ldv_request_irq_20_#in~name#1.offset;ldv_request_irq_20_~dev#1.base, ldv_request_irq_20_~dev#1.offset := ldv_request_irq_20_#in~dev#1.base, ldv_request_irq_20_#in~dev#1.offset;havoc ldv_request_irq_20_~ldv_func_res~0#1;havoc ldv_request_irq_20_~tmp~42#1;havoc ldv_request_irq_20_~tmp___0~18#1;assume { :begin_inline_request_irq } true;request_irq_#in~irq#1, request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset, request_irq_#in~flags#1, request_irq_#in~name#1.base, request_irq_#in~name#1.offset, request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset := ldv_request_irq_20_~irq#1, ldv_request_irq_20_~handler#1.base, ldv_request_irq_20_~handler#1.offset, ldv_request_irq_20_~flags#1, ldv_request_irq_20_~name#1.base, ldv_request_irq_20_~name#1.offset, ldv_request_irq_20_~dev#1.base, ldv_request_irq_20_~dev#1.offset;havoc request_irq_#res#1;havoc request_irq_#t~ret130#1, request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset, request_irq_~tmp~10#1;request_irq_~irq#1 := request_irq_#in~irq#1;request_irq_~handler#1.base, request_irq_~handler#1.offset := request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset;request_irq_~flags#1 := request_irq_#in~flags#1;request_irq_~name#1.base, request_irq_~name#1.offset := request_irq_#in~name#1.base, request_irq_#in~name#1.offset;request_irq_~dev#1.base, request_irq_~dev#1.offset := request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset;havoc request_irq_~tmp~10#1;assume { :begin_inline_request_threaded_irq } true;request_threaded_irq_#in~arg0#1, request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset, request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset, request_threaded_irq_#in~arg3#1, request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset, request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset := request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, 0, 0, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset;havoc request_threaded_irq_#res#1;havoc request_threaded_irq_#t~nondet760#1, request_threaded_irq_~arg0#1, request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset, request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset, request_threaded_irq_~arg3#1, request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset, request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset;request_threaded_irq_~arg0#1 := request_threaded_irq_#in~arg0#1;request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset := request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset;request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset := request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset;request_threaded_irq_~arg3#1 := request_threaded_irq_#in~arg3#1;request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset := request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset;request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset := request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset;assume -2147483648 <= request_threaded_irq_#t~nondet760#1 && request_threaded_irq_#t~nondet760#1 <= 2147483647;request_threaded_irq_#res#1 := request_threaded_irq_#t~nondet760#1;havoc request_threaded_irq_#t~nondet760#1; {15491#false} is VALID [2022-02-20 22:02:41,397 INFO L290 TraceCheckUtils]: 106: Hoare triple {15491#false} request_irq_#t~ret130#1 := request_threaded_irq_#res#1;assume { :end_inline_request_threaded_irq } true;assume -2147483648 <= request_irq_#t~ret130#1 && request_irq_#t~ret130#1 <= 2147483647;request_irq_~tmp~10#1 := request_irq_#t~ret130#1;havoc request_irq_#t~ret130#1;request_irq_#res#1 := request_irq_~tmp~10#1; {15491#false} is VALID [2022-02-20 22:02:41,397 INFO L290 TraceCheckUtils]: 107: Hoare triple {15491#false} ldv_request_irq_20_#t~ret733#1 := request_irq_#res#1;assume { :end_inline_request_irq } true;assume -2147483648 <= ldv_request_irq_20_#t~ret733#1 && ldv_request_irq_20_#t~ret733#1 <= 2147483647;ldv_request_irq_20_~tmp~42#1 := ldv_request_irq_20_#t~ret733#1;havoc ldv_request_irq_20_#t~ret733#1;ldv_request_irq_20_~ldv_func_res~0#1 := ldv_request_irq_20_~tmp~42#1;assume { :begin_inline_reg_check_1 } true;reg_check_1_#in~handler#1.base, reg_check_1_#in~handler#1.offset := ldv_request_irq_20_~handler#1.base, ldv_request_irq_20_~handler#1.offset;havoc reg_check_1_#res#1;havoc reg_check_1_~handler#1.base, reg_check_1_~handler#1.offset;reg_check_1_~handler#1.base, reg_check_1_~handler#1.offset := reg_check_1_#in~handler#1.base, reg_check_1_#in~handler#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,397 INFO L290 TraceCheckUtils]: 108: Hoare triple {15491#false} assume (reg_check_1_~handler#1.base + reg_check_1_~handler#1.offset) % 18446744073709551616 == (#funAddr~isicom_interrupt.base + #funAddr~isicom_interrupt.offset) % 18446744073709551616;reg_check_1_#res#1 := 1; {15491#false} is VALID [2022-02-20 22:02:41,397 INFO L290 TraceCheckUtils]: 109: Hoare triple {15491#false} ldv_request_irq_20_#t~ret734#1 := reg_check_1_#res#1;assume { :end_inline_reg_check_1 } true;assume -2147483648 <= ldv_request_irq_20_#t~ret734#1 && ldv_request_irq_20_#t~ret734#1 <= 2147483647;ldv_request_irq_20_~tmp___0~18#1 := ldv_request_irq_20_#t~ret734#1;havoc ldv_request_irq_20_#t~ret734#1; {15491#false} is VALID [2022-02-20 22:02:41,397 INFO L290 TraceCheckUtils]: 110: Hoare triple {15491#false} assume !(0 != ldv_request_irq_20_~tmp___0~18#1 && 0 == ldv_request_irq_20_~ldv_func_res~0#1); {15491#false} is VALID [2022-02-20 22:02:41,397 INFO L290 TraceCheckUtils]: 111: Hoare triple {15491#false} ldv_request_irq_20_#res#1 := ldv_request_irq_20_~ldv_func_res~0#1; {15491#false} is VALID [2022-02-20 22:02:41,397 INFO L290 TraceCheckUtils]: 112: Hoare triple {15491#false} isicom_probe_#t~ret590#1 := ldv_request_irq_20_#res#1;assume { :end_inline_ldv_request_irq_20 } true;assume -2147483648 <= isicom_probe_#t~ret590#1 && isicom_probe_#t~ret590#1 <= 2147483647;isicom_probe_~retval~2#1 := isicom_probe_#t~ret590#1;havoc isicom_probe_#t~mem589#1;havoc isicom_probe_#t~ret590#1; {15491#false} is VALID [2022-02-20 22:02:41,397 INFO L290 TraceCheckUtils]: 113: Hoare triple {15491#false} assume !(isicom_probe_~retval~2#1 < 0);assume { :begin_inline_reset_card } true;reset_card_#in~pdev#1.base, reset_card_#in~pdev#1.offset, reset_card_#in~card#1, reset_card_#in~signature#1.base, reset_card_#in~signature#1.offset := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, isicom_probe_~index~0#1, isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset;havoc reset_card_#res#1;havoc reset_card_#t~ret506#1.base, reset_card_#t~ret506#1.offset, reset_card_#t~mem507#1, reset_card_#t~mem508#1, reset_card_#t~ret509#1, reset_card_#t~nondet510#1, reset_card_#t~ret511#1, reset_card_#t~ret512#1, reset_card_#t~nondet514#1, reset_card_#t~mem515#1, reset_card_#t~ret516#1, reset_card_#t~nondet517#1, reset_card_#t~ret518#1, reset_card_#t~ret519#1, reset_card_#t~nondet520#1, reset_card_#t~switch521#1, reset_card_#t~ite522#1, reset_card_#t~nondet523#1, reset_card_#t~nondet513#1, reset_card_~pdev#1.base, reset_card_~pdev#1.offset, reset_card_~card#1, reset_card_~signature#1.base, reset_card_~signature#1.offset, reset_card_~board~1#1.base, reset_card_~board~1#1.offset, reset_card_~tmp~32#1.base, reset_card_~tmp~32#1.offset, reset_card_~base~11#1, reset_card_~sig~0#1, reset_card_~portcount~0#1, reset_card_~retval~0#1, reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset, reset_card_~tmp___0~14#1, reset_card_~tmp___1~8#1, reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset, reset_card_~tmp___2~6#1, reset_card_~tmp___3~3#1, reset_card_~tmp___4~1#1;reset_card_~pdev#1.base, reset_card_~pdev#1.offset := reset_card_#in~pdev#1.base, reset_card_#in~pdev#1.offset;reset_card_~card#1 := reset_card_#in~card#1;reset_card_~signature#1.base, reset_card_~signature#1.offset := reset_card_#in~signature#1.base, reset_card_#in~signature#1.offset;havoc reset_card_~board~1#1.base, reset_card_~board~1#1.offset;havoc reset_card_~tmp~32#1.base, reset_card_~tmp~32#1.offset;havoc reset_card_~base~11#1;havoc reset_card_~sig~0#1;havoc reset_card_~portcount~0#1;havoc reset_card_~retval~0#1;call reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset := #Ultimate.allocOnStack(37);havoc reset_card_~tmp___0~14#1;havoc reset_card_~tmp___1~8#1;call reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset := #Ultimate.allocOnStack(37);havoc reset_card_~tmp___2~6#1;havoc reset_card_~tmp___3~3#1;havoc reset_card_~tmp___4~1#1; {15491#false} is VALID [2022-02-20 22:02:41,398 INFO L272 TraceCheckUtils]: 114: Hoare triple {15491#false} call reset_card_#t~ret506#1.base, reset_card_#t~ret506#1.offset := pci_get_drvdata(reset_card_~pdev#1.base, reset_card_~pdev#1.offset); {15490#true} is VALID [2022-02-20 22:02:41,398 INFO L290 TraceCheckUtils]: 115: Hoare triple {15490#true} ~pdev#1.base, ~pdev#1.offset := #in~pdev#1.base, #in~pdev#1.offset;havoc ~tmp~11#1.base, ~tmp~11#1.offset;assume { :begin_inline_dev_get_drvdata } true;dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset := ~pdev#1.base, 147 + ~pdev#1.offset;havoc dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset, dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset;dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset := dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset;call dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset := read~$Pointer$(dev_get_drvdata_~dev#1.base, 489 + dev_get_drvdata_~dev#1.offset, 8);dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset := dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset; {15490#true} is VALID [2022-02-20 22:02:41,398 INFO L290 TraceCheckUtils]: 116: Hoare triple {15490#true} #t~ret153#1.base, #t~ret153#1.offset := dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;assume { :end_inline_dev_get_drvdata } true;~tmp~11#1.base, ~tmp~11#1.offset := #t~ret153#1.base, #t~ret153#1.offset;havoc #t~ret153#1.base, #t~ret153#1.offset;#res#1.base, #res#1.offset := ~tmp~11#1.base, ~tmp~11#1.offset; {15490#true} is VALID [2022-02-20 22:02:41,398 INFO L290 TraceCheckUtils]: 117: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,398 INFO L284 TraceCheckUtils]: 118: Hoare quadruple {15490#true} {15491#false} #3860#return; {15491#false} is VALID [2022-02-20 22:02:41,398 INFO L290 TraceCheckUtils]: 119: Hoare triple {15491#false} reset_card_~tmp~32#1.base, reset_card_~tmp~32#1.offset := reset_card_#t~ret506#1.base, reset_card_#t~ret506#1.offset;havoc reset_card_#t~ret506#1.base, reset_card_#t~ret506#1.offset;reset_card_~board~1#1.base, reset_card_~board~1#1.offset := reset_card_~tmp~32#1.base, reset_card_~tmp~32#1.offset;call reset_card_#t~mem507#1 := read~int(reset_card_~board~1#1.base, reset_card_~board~1#1.offset, 8);reset_card_~base~11#1 := reset_card_#t~mem507#1;havoc reset_card_#t~mem507#1;reset_card_~portcount~0#1 := 0;reset_card_~retval~0#1 := 0;call write~$Pointer$(56, 0, reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset, 8);call write~$Pointer$(57, 0, reset_card_~#descriptor~3#1.base, 8 + reset_card_~#descriptor~3#1.offset, 8);call write~$Pointer$(58, 0, reset_card_~#descriptor~3#1.base, 16 + reset_card_~#descriptor~3#1.offset, 8);call write~$Pointer$(59, 0, reset_card_~#descriptor~3#1.base, 24 + reset_card_~#descriptor~3#1.offset, 8);call write~int(1372, reset_card_~#descriptor~3#1.base, 32 + reset_card_~#descriptor~3#1.offset, 4);call write~int(0, reset_card_~#descriptor~3#1.base, 36 + reset_card_~#descriptor~3#1.offset, 1);call reset_card_#t~mem508#1 := read~int(reset_card_~#descriptor~3#1.base, 36 + reset_card_~#descriptor~3#1.offset, 1); {15491#false} is VALID [2022-02-20 22:02:41,398 INFO L272 TraceCheckUtils]: 120: Hoare triple {15491#false} call reset_card_#t~ret509#1 := ldv__builtin_expect(reset_card_#t~mem508#1 % 256, 0); {15490#true} is VALID [2022-02-20 22:02:41,398 INFO L290 TraceCheckUtils]: 121: Hoare triple {15490#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {15490#true} is VALID [2022-02-20 22:02:41,399 INFO L290 TraceCheckUtils]: 122: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,399 INFO L284 TraceCheckUtils]: 123: Hoare quadruple {15490#true} {15491#false} #3862#return; {15491#false} is VALID [2022-02-20 22:02:41,399 INFO L290 TraceCheckUtils]: 124: Hoare triple {15491#false} assume -9223372036854775808 <= reset_card_#t~ret509#1 && reset_card_#t~ret509#1 <= 9223372036854775807;reset_card_~tmp___0~14#1 := reset_card_#t~ret509#1;havoc reset_card_#t~mem508#1;havoc reset_card_#t~ret509#1; {15491#false} is VALID [2022-02-20 22:02:41,399 INFO L290 TraceCheckUtils]: 125: Hoare triple {15491#false} assume 0 != reset_card_~tmp___0~14#1;havoc reset_card_#t~nondet510#1; {15491#false} is VALID [2022-02-20 22:02:41,399 INFO L272 TraceCheckUtils]: 126: Hoare triple {15491#false} call reset_card_#t~ret511#1 := inw((if (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 <= 2147483647 then (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 else (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,399 INFO L290 TraceCheckUtils]: 127: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,399 INFO L290 TraceCheckUtils]: 128: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,399 INFO L284 TraceCheckUtils]: 129: Hoare quadruple {15490#true} {15491#false} #3864#return; {15491#false} is VALID [2022-02-20 22:02:41,400 INFO L290 TraceCheckUtils]: 130: Hoare triple {15491#false} havoc reset_card_#t~ret511#1; {15491#false} is VALID [2022-02-20 22:02:41,400 INFO L272 TraceCheckUtils]: 131: Hoare triple {15491#false} call msleep(10); {15490#true} is VALID [2022-02-20 22:02:41,400 INFO L290 TraceCheckUtils]: 132: Hoare triple {15490#true} ~arg0 := #in~arg0; {15490#true} is VALID [2022-02-20 22:02:41,400 INFO L290 TraceCheckUtils]: 133: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,400 INFO L284 TraceCheckUtils]: 134: Hoare quadruple {15490#true} {15491#false} #3866#return; {15491#false} is VALID [2022-02-20 22:02:41,400 INFO L272 TraceCheckUtils]: 135: Hoare triple {15491#false} call outw(0, (if (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 <= 2147483647 then (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 else (8 + reset_card_~base~11#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,400 INFO L290 TraceCheckUtils]: 136: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,400 INFO L290 TraceCheckUtils]: 137: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,401 INFO L284 TraceCheckUtils]: 138: Hoare quadruple {15490#true} {15491#false} #3868#return; {15491#false} is VALID [2022-02-20 22:02:41,401 INFO L272 TraceCheckUtils]: 139: Hoare triple {15491#false} call msleep(1000); {15490#true} is VALID [2022-02-20 22:02:41,401 INFO L290 TraceCheckUtils]: 140: Hoare triple {15490#true} ~arg0 := #in~arg0; {15490#true} is VALID [2022-02-20 22:02:41,401 INFO L290 TraceCheckUtils]: 141: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,401 INFO L284 TraceCheckUtils]: 142: Hoare quadruple {15490#true} {15491#false} #3870#return; {15491#false} is VALID [2022-02-20 22:02:41,401 INFO L272 TraceCheckUtils]: 143: Hoare triple {15491#false} call reset_card_#t~ret512#1 := inw((if (4 + reset_card_~base~11#1) % 4294967296 % 4294967296 <= 2147483647 then (4 + reset_card_~base~11#1) % 4294967296 % 4294967296 else (4 + reset_card_~base~11#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,401 INFO L290 TraceCheckUtils]: 144: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,401 INFO L290 TraceCheckUtils]: 145: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,401 INFO L284 TraceCheckUtils]: 146: Hoare quadruple {15490#true} {15491#false} #3872#return; {15491#false} is VALID [2022-02-20 22:02:41,402 INFO L290 TraceCheckUtils]: 147: Hoare triple {15491#false} reset_card_~tmp___1~8#1 := reset_card_#t~ret512#1;havoc reset_card_#t~ret512#1; {15491#false} is VALID [2022-02-20 22:02:41,402 INFO L290 TraceCheckUtils]: 148: Hoare triple {15491#false} assume 0 == reset_card_~tmp___1~8#1 % 65536;reset_card_~sig~0#1 := 0; {15491#false} is VALID [2022-02-20 22:02:41,402 INFO L290 TraceCheckUtils]: 149: Hoare triple {15491#false} assume (((165 != reset_card_~sig~0#1 % 4294967296 && 187 != reset_card_~sig~0#1 % 4294967296) && 204 != reset_card_~sig~0#1 % 4294967296) && 221 != reset_card_~sig~0#1 % 4294967296) && 238 != reset_card_~sig~0#1 % 4294967296;havoc reset_card_#t~nondet514#1;call write~$Pointer$(62, 0, reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset, 8);call write~$Pointer$(63, 0, reset_card_~#descriptor___0~1#1.base, 8 + reset_card_~#descriptor___0~1#1.offset, 8);call write~$Pointer$(64, 0, reset_card_~#descriptor___0~1#1.base, 16 + reset_card_~#descriptor___0~1#1.offset, 8);call write~$Pointer$(65, 0, reset_card_~#descriptor___0~1#1.base, 24 + reset_card_~#descriptor___0~1#1.offset, 8);call write~int(1388, reset_card_~#descriptor___0~1#1.base, 32 + reset_card_~#descriptor___0~1#1.offset, 4);call write~int(0, reset_card_~#descriptor___0~1#1.base, 36 + reset_card_~#descriptor___0~1#1.offset, 1);call reset_card_#t~mem515#1 := read~int(reset_card_~#descriptor___0~1#1.base, 36 + reset_card_~#descriptor___0~1#1.offset, 1); {15491#false} is VALID [2022-02-20 22:02:41,402 INFO L272 TraceCheckUtils]: 150: Hoare triple {15491#false} call reset_card_#t~ret516#1 := ldv__builtin_expect(reset_card_#t~mem515#1 % 256, 0); {15490#true} is VALID [2022-02-20 22:02:41,402 INFO L290 TraceCheckUtils]: 151: Hoare triple {15490#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {15490#true} is VALID [2022-02-20 22:02:41,402 INFO L290 TraceCheckUtils]: 152: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,402 INFO L284 TraceCheckUtils]: 153: Hoare quadruple {15490#true} {15491#false} #3874#return; {15491#false} is VALID [2022-02-20 22:02:41,402 INFO L290 TraceCheckUtils]: 154: Hoare triple {15491#false} assume -9223372036854775808 <= reset_card_#t~ret516#1 && reset_card_#t~ret516#1 <= 9223372036854775807;reset_card_~tmp___2~6#1 := reset_card_#t~ret516#1;havoc reset_card_#t~mem515#1;havoc reset_card_#t~ret516#1; {15491#false} is VALID [2022-02-20 22:02:41,403 INFO L290 TraceCheckUtils]: 155: Hoare triple {15491#false} assume 0 != reset_card_~tmp___2~6#1;havoc reset_card_#t~nondet517#1; {15491#false} is VALID [2022-02-20 22:02:41,403 INFO L290 TraceCheckUtils]: 156: Hoare triple {15491#false} reset_card_~retval~0#1 := -5; {15491#false} is VALID [2022-02-20 22:02:41,403 INFO L290 TraceCheckUtils]: 157: Hoare triple {15491#false} reset_card_#res#1 := reset_card_~retval~0#1;call ULTIMATE.dealloc(reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset);havoc reset_card_~#descriptor~3#1.base, reset_card_~#descriptor~3#1.offset;call ULTIMATE.dealloc(reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset);havoc reset_card_~#descriptor___0~1#1.base, reset_card_~#descriptor___0~1#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,403 INFO L290 TraceCheckUtils]: 158: Hoare triple {15491#false} isicom_probe_#t~ret593#1 := reset_card_#res#1;assume { :end_inline_reset_card } true;assume -2147483648 <= isicom_probe_#t~ret593#1 && isicom_probe_#t~ret593#1 <= 2147483647;isicom_probe_~retval~2#1 := isicom_probe_#t~ret593#1;havoc isicom_probe_#t~ret593#1; {15491#false} is VALID [2022-02-20 22:02:41,403 INFO L290 TraceCheckUtils]: 159: Hoare triple {15491#false} assume !(isicom_probe_~retval~2#1 < 0);call isicom_probe_#t~mem594#1 := read~int(isicom_probe_~#signature~0#1.base, isicom_probe_~#signature~0#1.offset, 4);assume { :begin_inline_load_firmware } true;load_firmware_#in~pdev#1.base, load_firmware_#in~pdev#1.offset, load_firmware_#in~index#1, load_firmware_#in~signature#1 := isicom_probe_~pdev#1.base, isicom_probe_~pdev#1.offset, isicom_probe_~index~0#1, isicom_probe_#t~mem594#1;havoc load_firmware_#res#1;havoc load_firmware_#t~ret524#1.base, load_firmware_#t~ret524#1.offset, load_firmware_#t~mem525#1, load_firmware_#t~switch526#1, load_firmware_#t~nondet527#1, load_firmware_#t~ret528#1, load_firmware_#t~mem529#1.base, load_firmware_#t~mem529#1.offset, load_firmware_#t~mem530#1.base, load_firmware_#t~mem530#1.offset, load_firmware_#t~ret531#1, load_firmware_#t~mem532#1, load_firmware_#t~mem533#1, load_firmware_#t~mem534#1, load_firmware_#t~ret535#1, load_firmware_#t~ret536#1, load_firmware_#t~nondet537#1, load_firmware_#t~mem538#1, load_firmware_#t~mem539#1, load_firmware_#t~ret540#1, load_firmware_#t~ret541#1, load_firmware_#t~nondet542#1, load_firmware_#t~mem543#1, load_firmware_#t~mem544#1.base, load_firmware_#t~mem544#1.offset, load_firmware_#t~mem546#1.base, load_firmware_#t~mem546#1.offset, load_firmware_#t~mem545#1.base, load_firmware_#t~mem545#1.offset, load_firmware_#t~mem547#1, load_firmware_#t~mem548#1.base, load_firmware_#t~mem548#1.offset, load_firmware_#t~mem549#1.base, load_firmware_#t~mem549#1.offset, load_firmware_#t~ret550#1, load_firmware_#t~mem551#1, load_firmware_#t~mem552#1, load_firmware_#t~mem553#1, load_firmware_#t~ret554#1, load_firmware_#t~ret555#1, load_firmware_#t~nondet556#1, load_firmware_#t~mem557#1, load_firmware_#t~mem558#1, load_firmware_#t~ret559#1.base, load_firmware_#t~ret559#1.offset, load_firmware_#t~nondet560#1, load_firmware_#t~ret561#1, load_firmware_#t~mem562#1, load_firmware_#t~mem563#1, load_firmware_#t~nondet564#1, load_firmware_#t~mem565#1, load_firmware_#t~ret566#1, load_firmware_#t~ret567#1, load_firmware_#t~nondet568#1, load_firmware_#t~mem569#1, load_firmware_#t~mem570#1.base, load_firmware_#t~mem570#1.offset, load_firmware_#t~mem572#1.base, load_firmware_#t~mem572#1.offset, load_firmware_#t~mem571#1.base, load_firmware_#t~mem571#1.offset, load_firmware_#t~mem573#1, load_firmware_#t~ret574#1, load_firmware_#t~mem575#1, load_firmware_#t~mem576#1.base, load_firmware_#t~mem576#1.offset, load_firmware_~pdev#1.base, load_firmware_~pdev#1.offset, load_firmware_~index#1, load_firmware_~signature#1, load_firmware_~board~2#1.base, load_firmware_~board~2#1.offset, load_firmware_~tmp~33#1.base, load_firmware_~tmp~33#1.offset, load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, load_firmware_~base~12#1, load_firmware_~a~2#1, load_firmware_~word_count~2#1, load_firmware_~status~1#1, load_firmware_~retval~1#1, load_firmware_~name~0#1.base, load_firmware_~name~0#1.offset, load_firmware_~data~0#1.base, load_firmware_~data~0#1.offset, load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset, load_firmware_~tmp___0~15#1, load_firmware_~tmp___1~9#1, load_firmware_~tmp___2~7#1, load_firmware_~tmp___3~4#1, load_firmware_~tmp___4~2#1, load_firmware_~tmp___5~1#1.base, load_firmware_~tmp___5~1#1.offset, load_firmware_~tmp___6~1#1, load_firmware_~tmp___7~1#1;load_firmware_~pdev#1.base, load_firmware_~pdev#1.offset := load_firmware_#in~pdev#1.base, load_firmware_#in~pdev#1.offset;load_firmware_~index#1 := load_firmware_#in~index#1;load_firmware_~signature#1 := load_firmware_#in~signature#1;havoc load_firmware_~board~2#1.base, load_firmware_~board~2#1.offset;havoc load_firmware_~tmp~33#1.base, load_firmware_~tmp~33#1.offset;call load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset := #Ultimate.allocOnStack(8);havoc load_firmware_~base~12#1;havoc load_firmware_~a~2#1;havoc load_firmware_~word_count~2#1;havoc load_firmware_~status~1#1;havoc load_firmware_~retval~1#1;havoc load_firmware_~name~0#1.base, load_firmware_~name~0#1.offset;havoc load_firmware_~data~0#1.base, load_firmware_~data~0#1.offset;havoc load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset;havoc load_firmware_~tmp___0~15#1;havoc load_firmware_~tmp___1~9#1;havoc load_firmware_~tmp___2~7#1;havoc load_firmware_~tmp___3~4#1;havoc load_firmware_~tmp___4~2#1;havoc load_firmware_~tmp___5~1#1.base, load_firmware_~tmp___5~1#1.offset;havoc load_firmware_~tmp___6~1#1;havoc load_firmware_~tmp___7~1#1; {15491#false} is VALID [2022-02-20 22:02:41,403 INFO L272 TraceCheckUtils]: 160: Hoare triple {15491#false} call load_firmware_#t~ret524#1.base, load_firmware_#t~ret524#1.offset := pci_get_drvdata(load_firmware_~pdev#1.base, load_firmware_~pdev#1.offset); {15490#true} is VALID [2022-02-20 22:02:41,403 INFO L290 TraceCheckUtils]: 161: Hoare triple {15490#true} ~pdev#1.base, ~pdev#1.offset := #in~pdev#1.base, #in~pdev#1.offset;havoc ~tmp~11#1.base, ~tmp~11#1.offset;assume { :begin_inline_dev_get_drvdata } true;dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset := ~pdev#1.base, 147 + ~pdev#1.offset;havoc dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset, dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset;dev_get_drvdata_~dev#1.base, dev_get_drvdata_~dev#1.offset := dev_get_drvdata_#in~dev#1.base, dev_get_drvdata_#in~dev#1.offset;call dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset := read~$Pointer$(dev_get_drvdata_~dev#1.base, 489 + dev_get_drvdata_~dev#1.offset, 8);dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset := dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset;havoc dev_get_drvdata_#t~mem135#1.base, dev_get_drvdata_#t~mem135#1.offset; {15490#true} is VALID [2022-02-20 22:02:41,403 INFO L290 TraceCheckUtils]: 162: Hoare triple {15490#true} #t~ret153#1.base, #t~ret153#1.offset := dev_get_drvdata_#res#1.base, dev_get_drvdata_#res#1.offset;assume { :end_inline_dev_get_drvdata } true;~tmp~11#1.base, ~tmp~11#1.offset := #t~ret153#1.base, #t~ret153#1.offset;havoc #t~ret153#1.base, #t~ret153#1.offset;#res#1.base, #res#1.offset := ~tmp~11#1.base, ~tmp~11#1.offset; {15490#true} is VALID [2022-02-20 22:02:41,404 INFO L290 TraceCheckUtils]: 163: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,404 INFO L284 TraceCheckUtils]: 164: Hoare quadruple {15490#true} {15491#false} #3882#return; {15491#false} is VALID [2022-02-20 22:02:41,404 INFO L290 TraceCheckUtils]: 165: Hoare triple {15491#false} load_firmware_~tmp~33#1.base, load_firmware_~tmp~33#1.offset := load_firmware_#t~ret524#1.base, load_firmware_#t~ret524#1.offset;havoc load_firmware_#t~ret524#1.base, load_firmware_#t~ret524#1.offset;load_firmware_~board~2#1.base, load_firmware_~board~2#1.offset := load_firmware_~tmp~33#1.base, load_firmware_~tmp~33#1.offset;call load_firmware_#t~mem525#1 := read~int(load_firmware_~board~2#1.base, load_firmware_~board~2#1.offset, 8);load_firmware_~base~12#1 := load_firmware_#t~mem525#1;havoc load_firmware_#t~mem525#1;load_firmware_~retval~1#1 := -5;load_firmware_#t~switch526#1 := 165 == load_firmware_~signature#1; {15491#false} is VALID [2022-02-20 22:02:41,404 INFO L290 TraceCheckUtils]: 166: Hoare triple {15491#false} assume load_firmware_#t~switch526#1;load_firmware_~name~0#1.base, load_firmware_~name~0#1.offset := 69, 0; {15491#false} is VALID [2022-02-20 22:02:41,404 INFO L290 TraceCheckUtils]: 167: Hoare triple {15491#false} assume { :begin_inline_request_firmware } true;request_firmware_#in~arg0#1.base, request_firmware_#in~arg0#1.offset, request_firmware_#in~arg1#1.base, request_firmware_#in~arg1#1.offset, request_firmware_#in~arg2#1.base, request_firmware_#in~arg2#1.offset := load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, load_firmware_~name~0#1.base, load_firmware_~name~0#1.offset, load_firmware_~pdev#1.base, 147 + load_firmware_~pdev#1.offset;havoc request_firmware_#res#1;havoc request_firmware_#t~nondet759#1, request_firmware_~arg0#1.base, request_firmware_~arg0#1.offset, request_firmware_~arg1#1.base, request_firmware_~arg1#1.offset, request_firmware_~arg2#1.base, request_firmware_~arg2#1.offset;request_firmware_~arg0#1.base, request_firmware_~arg0#1.offset := request_firmware_#in~arg0#1.base, request_firmware_#in~arg0#1.offset;request_firmware_~arg1#1.base, request_firmware_~arg1#1.offset := request_firmware_#in~arg1#1.base, request_firmware_#in~arg1#1.offset;request_firmware_~arg2#1.base, request_firmware_~arg2#1.offset := request_firmware_#in~arg2#1.base, request_firmware_#in~arg2#1.offset;assume -2147483648 <= request_firmware_#t~nondet759#1 && request_firmware_#t~nondet759#1 <= 2147483647;request_firmware_#res#1 := request_firmware_#t~nondet759#1;havoc request_firmware_#t~nondet759#1; {15491#false} is VALID [2022-02-20 22:02:41,404 INFO L290 TraceCheckUtils]: 168: Hoare triple {15491#false} load_firmware_#t~ret528#1 := request_firmware_#res#1;assume { :end_inline_request_firmware } true;assume -2147483648 <= load_firmware_#t~ret528#1 && load_firmware_#t~ret528#1 <= 2147483647;load_firmware_~retval~1#1 := load_firmware_#t~ret528#1;havoc load_firmware_#t~ret528#1; {15491#false} is VALID [2022-02-20 22:02:41,404 INFO L290 TraceCheckUtils]: 169: Hoare triple {15491#false} assume !(0 != load_firmware_~retval~1#1);load_firmware_~retval~1#1 := -5;call load_firmware_#t~mem529#1.base, load_firmware_#t~mem529#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem530#1.base, load_firmware_#t~mem530#1.offset := read~$Pointer$(load_firmware_#t~mem529#1.base, 8 + load_firmware_#t~mem529#1.offset, 8);load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset := load_firmware_#t~mem530#1.base, load_firmware_#t~mem530#1.offset;havoc load_firmware_#t~mem529#1.base, load_firmware_#t~mem529#1.offset;havoc load_firmware_#t~mem530#1.base, load_firmware_#t~mem530#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,404 INFO L290 TraceCheckUtils]: 170: Hoare triple {15491#false} call load_firmware_#t~mem544#1.base, load_firmware_#t~mem544#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem546#1.base, load_firmware_#t~mem546#1.offset := read~$Pointer$(load_firmware_#t~mem544#1.base, 8 + load_firmware_#t~mem544#1.offset, 8);call load_firmware_#t~mem545#1.base, load_firmware_#t~mem545#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem547#1 := read~int(load_firmware_#t~mem545#1.base, load_firmware_#t~mem545#1.offset, 8); {15491#false} is VALID [2022-02-20 22:02:41,405 INFO L290 TraceCheckUtils]: 171: Hoare triple {15491#false} assume !((load_firmware_#t~mem546#1.base + (load_firmware_#t~mem546#1.offset + (if load_firmware_#t~mem547#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then load_firmware_#t~mem547#1 % 18446744073709551616 % 18446744073709551616 else load_firmware_#t~mem547#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616))) % 18446744073709551616 > (load_firmware_~frame~0#1.base + load_firmware_~frame~0#1.offset) % 18446744073709551616);havoc load_firmware_#t~mem544#1.base, load_firmware_#t~mem544#1.offset;havoc load_firmware_#t~mem546#1.base, load_firmware_#t~mem546#1.offset;havoc load_firmware_#t~mem545#1.base, load_firmware_#t~mem545#1.offset;havoc load_firmware_#t~mem547#1;call load_firmware_#t~mem548#1.base, load_firmware_#t~mem548#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem549#1.base, load_firmware_#t~mem549#1.offset := read~$Pointer$(load_firmware_#t~mem548#1.base, 8 + load_firmware_#t~mem548#1.offset, 8);load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset := load_firmware_#t~mem549#1.base, load_firmware_#t~mem549#1.offset;havoc load_firmware_#t~mem548#1.base, load_firmware_#t~mem548#1.offset;havoc load_firmware_#t~mem549#1.base, load_firmware_#t~mem549#1.offset; {15491#false} is VALID [2022-02-20 22:02:41,405 INFO L290 TraceCheckUtils]: 172: Hoare triple {15491#false} call load_firmware_#t~mem570#1.base, load_firmware_#t~mem570#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem572#1.base, load_firmware_#t~mem572#1.offset := read~$Pointer$(load_firmware_#t~mem570#1.base, 8 + load_firmware_#t~mem570#1.offset, 8);call load_firmware_#t~mem571#1.base, load_firmware_#t~mem571#1.offset := read~$Pointer$(load_firmware_~#fw~0#1.base, load_firmware_~#fw~0#1.offset, 8);call load_firmware_#t~mem573#1 := read~int(load_firmware_#t~mem571#1.base, load_firmware_#t~mem571#1.offset, 8); {15491#false} is VALID [2022-02-20 22:02:41,405 INFO L290 TraceCheckUtils]: 173: Hoare triple {15491#false} assume (load_firmware_#t~mem572#1.base + (load_firmware_#t~mem572#1.offset + (if load_firmware_#t~mem573#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then load_firmware_#t~mem573#1 % 18446744073709551616 % 18446744073709551616 else load_firmware_#t~mem573#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616))) % 18446744073709551616 > (load_firmware_~frame~0#1.base + load_firmware_~frame~0#1.offset) % 18446744073709551616;havoc load_firmware_#t~mem570#1.base, load_firmware_#t~mem570#1.offset;havoc load_firmware_#t~mem572#1.base, load_firmware_#t~mem572#1.offset;havoc load_firmware_#t~mem571#1.base, load_firmware_#t~mem571#1.offset;havoc load_firmware_#t~mem573#1; {15491#false} is VALID [2022-02-20 22:02:41,405 INFO L272 TraceCheckUtils]: 174: Hoare triple {15491#false} call load_firmware_#t~ret550#1 := WaitTillCardIsFree(load_firmware_~base~12#1); {15490#true} is VALID [2022-02-20 22:02:41,405 INFO L290 TraceCheckUtils]: 175: Hoare triple {15490#true} ~base#1 := #in~base#1;havoc ~count~0#1;havoc ~a~0#1;havoc ~tmp~12#1;havoc ~__ms~0#1;havoc ~tmp___0~6#1;havoc ~tmp___1~3#1;havoc ~tmp___2~2#1;havoc ~tmp___3~0#1;~count~0#1 := 0;assume { :begin_inline_preempt_count } true;havoc preempt_count_#res#1;havoc preempt_count_#t~switch11#1, preempt_count_~pfo_ret__~0#1;havoc preempt_count_~pfo_ret__~0#1;preempt_count_#t~switch11#1 := false; {15490#true} is VALID [2022-02-20 22:02:41,405 INFO L290 TraceCheckUtils]: 176: Hoare triple {15490#true} assume preempt_count_#t~switch11#1; {15490#true} is VALID [2022-02-20 22:02:41,405 INFO L290 TraceCheckUtils]: 177: Hoare triple {15490#true} preempt_count_#res#1 := (if 0 == preempt_count_~pfo_ret__~0#1 then 0 else (if 1 == preempt_count_~pfo_ret__~0#1 then 1 else ~bitwiseAnd(preempt_count_~pfo_ret__~0#1, 2147483647))); {15490#true} is VALID [2022-02-20 22:02:41,405 INFO L290 TraceCheckUtils]: 178: Hoare triple {15490#true} #t~ret154#1 := preempt_count_#res#1;assume { :end_inline_preempt_count } true;assume -2147483648 <= #t~ret154#1 && #t~ret154#1 <= 2147483647;~tmp~12#1 := #t~ret154#1;havoc #t~ret154#1;~a~0#1 := (if 0 != (if 0 == ~tmp~12#1 then 0 else (if 1 == ~tmp~12#1 then 1 else ~bitwiseAnd(~tmp~12#1, 18446744073707454463))) % 18446744073709551616 then 1 else 0); {15490#true} is VALID [2022-02-20 22:02:41,406 INFO L272 TraceCheckUtils]: 179: Hoare triple {15490#true} call #t~ret155#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,406 INFO L290 TraceCheckUtils]: 180: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,406 INFO L290 TraceCheckUtils]: 181: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,406 INFO L284 TraceCheckUtils]: 182: Hoare quadruple {15490#true} {15490#true} #3568#return; {15490#true} is VALID [2022-02-20 22:02:41,406 INFO L290 TraceCheckUtils]: 183: Hoare triple {15490#true} ~tmp___1~3#1 := #t~ret155#1;havoc #t~ret155#1; {15490#true} is VALID [2022-02-20 22:02:41,406 INFO L290 TraceCheckUtils]: 184: Hoare triple {15490#true} assume !(0 == ~tmp___1~3#1 % 65536); {15490#true} is VALID [2022-02-20 22:02:41,406 INFO L272 TraceCheckUtils]: 185: Hoare triple {15490#true} call #t~ret156#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,406 INFO L290 TraceCheckUtils]: 186: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,406 INFO L290 TraceCheckUtils]: 187: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,407 INFO L284 TraceCheckUtils]: 188: Hoare quadruple {15490#true} {15490#true} #3570#return; {15490#true} is VALID [2022-02-20 22:02:41,407 INFO L290 TraceCheckUtils]: 189: Hoare triple {15490#true} ~tmp___3~0#1 := #t~ret156#1;havoc #t~ret156#1;#res#1 := (if 0 == ~tmp___3~0#1 % 65536 then 1 else 0); {15490#true} is VALID [2022-02-20 22:02:41,407 INFO L290 TraceCheckUtils]: 190: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,407 INFO L284 TraceCheckUtils]: 191: Hoare quadruple {15490#true} {15491#false} #3912#return; {15491#false} is VALID [2022-02-20 22:02:41,407 INFO L290 TraceCheckUtils]: 192: Hoare triple {15491#false} assume -2147483648 <= load_firmware_#t~ret550#1 && load_firmware_#t~ret550#1 <= 2147483647;load_firmware_~tmp___3~4#1 := load_firmware_#t~ret550#1;havoc load_firmware_#t~ret550#1; {15491#false} is VALID [2022-02-20 22:02:41,407 INFO L290 TraceCheckUtils]: 193: Hoare triple {15491#false} assume !(0 != load_firmware_~tmp___3~4#1); {15491#false} is VALID [2022-02-20 22:02:41,407 INFO L272 TraceCheckUtils]: 194: Hoare triple {15491#false} call outw(241, (if load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 <= 2147483647 then load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 else load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,407 INFO L290 TraceCheckUtils]: 195: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,408 INFO L290 TraceCheckUtils]: 196: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,408 INFO L284 TraceCheckUtils]: 197: Hoare quadruple {15490#true} {15491#false} #3914#return; {15491#false} is VALID [2022-02-20 22:02:41,408 INFO L272 TraceCheckUtils]: 198: Hoare triple {15491#false} call outw(0, (if load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 <= 2147483647 then load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 else load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,408 INFO L290 TraceCheckUtils]: 199: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,408 INFO L290 TraceCheckUtils]: 200: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,408 INFO L284 TraceCheckUtils]: 201: Hoare quadruple {15490#true} {15491#false} #3916#return; {15491#false} is VALID [2022-02-20 22:02:41,408 INFO L290 TraceCheckUtils]: 202: Hoare triple {15491#false} call load_firmware_#t~mem551#1 := read~int(load_firmware_~frame~0#1.base, load_firmware_~frame~0#1.offset, 2); {15491#false} is VALID [2022-02-20 22:02:41,408 INFO L272 TraceCheckUtils]: 203: Hoare triple {15491#false} call outw(load_firmware_#t~mem551#1 % 65536, (if load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 <= 2147483647 then load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 else load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,409 INFO L290 TraceCheckUtils]: 204: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,409 INFO L290 TraceCheckUtils]: 205: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,409 INFO L284 TraceCheckUtils]: 206: Hoare quadruple {15490#true} {15491#false} #3918#return; {15491#false} is VALID [2022-02-20 22:02:41,409 INFO L290 TraceCheckUtils]: 207: Hoare triple {15491#false} havoc load_firmware_#t~mem551#1;call load_firmware_#t~mem552#1 := read~int(load_firmware_~frame~0#1.base, 2 + load_firmware_~frame~0#1.offset, 2);call load_firmware_#t~mem553#1 := read~int(load_firmware_~frame~0#1.base, 2 + load_firmware_~frame~0#1.offset, 2);load_firmware_~word_count~2#1 := load_firmware_#t~mem552#1 % 65536 / 2 % 65536 + load_firmware_#t~mem553#1 % 65536;havoc load_firmware_#t~mem552#1;havoc load_firmware_#t~mem553#1; {15491#false} is VALID [2022-02-20 22:02:41,409 INFO L272 TraceCheckUtils]: 208: Hoare triple {15491#false} call outw((if (1 + load_firmware_~word_count~2#1 % 65536) % 4294967296 % 4294967296 <= 2147483647 then (1 + load_firmware_~word_count~2#1 % 65536) % 4294967296 % 4294967296 else (1 + load_firmware_~word_count~2#1 % 65536) % 4294967296 % 4294967296 - 4294967296), (if load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 <= 2147483647 then load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 else load_firmware_~base~12#1 % 18446744073709551616 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,409 INFO L290 TraceCheckUtils]: 209: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,409 INFO L290 TraceCheckUtils]: 210: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,409 INFO L284 TraceCheckUtils]: 211: Hoare quadruple {15490#true} {15491#false} #3920#return; {15491#false} is VALID [2022-02-20 22:02:41,409 INFO L272 TraceCheckUtils]: 212: Hoare triple {15491#false} call outw(0, (if (12 + load_firmware_~base~12#1) % 4294967296 % 4294967296 <= 2147483647 then (12 + load_firmware_~base~12#1) % 4294967296 % 4294967296 else (12 + load_firmware_~base~12#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,410 INFO L290 TraceCheckUtils]: 213: Hoare triple {15490#true} ~value := #in~value;~port := #in~port; {15490#true} is VALID [2022-02-20 22:02:41,410 INFO L290 TraceCheckUtils]: 214: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,410 INFO L284 TraceCheckUtils]: 215: Hoare quadruple {15490#true} {15491#false} #3922#return; {15491#false} is VALID [2022-02-20 22:02:41,410 INFO L272 TraceCheckUtils]: 216: Hoare triple {15491#false} call __const_udelay(214750); {15490#true} is VALID [2022-02-20 22:02:41,410 INFO L290 TraceCheckUtils]: 217: Hoare triple {15490#true} ~arg0 := #in~arg0; {15490#true} is VALID [2022-02-20 22:02:41,410 INFO L290 TraceCheckUtils]: 218: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,410 INFO L284 TraceCheckUtils]: 219: Hoare quadruple {15490#true} {15491#false} #3924#return; {15491#false} is VALID [2022-02-20 22:02:41,410 INFO L272 TraceCheckUtils]: 220: Hoare triple {15491#false} call load_firmware_#t~ret554#1 := WaitTillCardIsFree(load_firmware_~base~12#1); {15490#true} is VALID [2022-02-20 22:02:41,411 INFO L290 TraceCheckUtils]: 221: Hoare triple {15490#true} ~base#1 := #in~base#1;havoc ~count~0#1;havoc ~a~0#1;havoc ~tmp~12#1;havoc ~__ms~0#1;havoc ~tmp___0~6#1;havoc ~tmp___1~3#1;havoc ~tmp___2~2#1;havoc ~tmp___3~0#1;~count~0#1 := 0;assume { :begin_inline_preempt_count } true;havoc preempt_count_#res#1;havoc preempt_count_#t~switch11#1, preempt_count_~pfo_ret__~0#1;havoc preempt_count_~pfo_ret__~0#1;preempt_count_#t~switch11#1 := false; {15632#(not |WaitTillCardIsFree_preempt_count_#t~switch11#1|)} is VALID [2022-02-20 22:02:41,411 INFO L290 TraceCheckUtils]: 222: Hoare triple {15632#(not |WaitTillCardIsFree_preempt_count_#t~switch11#1|)} assume preempt_count_#t~switch11#1; {15491#false} is VALID [2022-02-20 22:02:41,411 INFO L290 TraceCheckUtils]: 223: Hoare triple {15491#false} preempt_count_#res#1 := (if 0 == preempt_count_~pfo_ret__~0#1 then 0 else (if 1 == preempt_count_~pfo_ret__~0#1 then 1 else ~bitwiseAnd(preempt_count_~pfo_ret__~0#1, 2147483647))); {15491#false} is VALID [2022-02-20 22:02:41,411 INFO L290 TraceCheckUtils]: 224: Hoare triple {15491#false} #t~ret154#1 := preempt_count_#res#1;assume { :end_inline_preempt_count } true;assume -2147483648 <= #t~ret154#1 && #t~ret154#1 <= 2147483647;~tmp~12#1 := #t~ret154#1;havoc #t~ret154#1;~a~0#1 := (if 0 != (if 0 == ~tmp~12#1 then 0 else (if 1 == ~tmp~12#1 then 1 else ~bitwiseAnd(~tmp~12#1, 18446744073707454463))) % 18446744073709551616 then 1 else 0); {15491#false} is VALID [2022-02-20 22:02:41,412 INFO L272 TraceCheckUtils]: 225: Hoare triple {15491#false} call #t~ret155#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,412 INFO L290 TraceCheckUtils]: 226: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,412 INFO L290 TraceCheckUtils]: 227: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,412 INFO L284 TraceCheckUtils]: 228: Hoare quadruple {15490#true} {15491#false} #3568#return; {15491#false} is VALID [2022-02-20 22:02:41,412 INFO L290 TraceCheckUtils]: 229: Hoare triple {15491#false} ~tmp___1~3#1 := #t~ret155#1;havoc #t~ret155#1; {15491#false} is VALID [2022-02-20 22:02:41,412 INFO L290 TraceCheckUtils]: 230: Hoare triple {15491#false} assume !(0 == ~tmp___1~3#1 % 65536); {15491#false} is VALID [2022-02-20 22:02:41,412 INFO L272 TraceCheckUtils]: 231: Hoare triple {15491#false} call #t~ret156#1 := inw((if (14 + ~base#1) % 4294967296 % 4294967296 <= 2147483647 then (14 + ~base#1) % 4294967296 % 4294967296 else (14 + ~base#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,412 INFO L290 TraceCheckUtils]: 232: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,413 INFO L290 TraceCheckUtils]: 233: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,413 INFO L284 TraceCheckUtils]: 234: Hoare quadruple {15490#true} {15491#false} #3570#return; {15491#false} is VALID [2022-02-20 22:02:41,413 INFO L290 TraceCheckUtils]: 235: Hoare triple {15491#false} ~tmp___3~0#1 := #t~ret156#1;havoc #t~ret156#1;#res#1 := (if 0 == ~tmp___3~0#1 % 65536 then 1 else 0); {15491#false} is VALID [2022-02-20 22:02:41,413 INFO L290 TraceCheckUtils]: 236: Hoare triple {15491#false} assume true; {15491#false} is VALID [2022-02-20 22:02:41,413 INFO L284 TraceCheckUtils]: 237: Hoare quadruple {15491#false} {15491#false} #3926#return; {15491#false} is VALID [2022-02-20 22:02:41,413 INFO L290 TraceCheckUtils]: 238: Hoare triple {15491#false} assume -2147483648 <= load_firmware_#t~ret554#1 && load_firmware_#t~ret554#1 <= 2147483647;load_firmware_~tmp___4~2#1 := load_firmware_#t~ret554#1;havoc load_firmware_#t~ret554#1; {15491#false} is VALID [2022-02-20 22:02:41,413 INFO L290 TraceCheckUtils]: 239: Hoare triple {15491#false} assume !(0 != load_firmware_~tmp___4~2#1); {15491#false} is VALID [2022-02-20 22:02:41,413 INFO L272 TraceCheckUtils]: 240: Hoare triple {15491#false} call load_firmware_#t~ret555#1 := inw((if (4 + load_firmware_~base~12#1) % 4294967296 % 4294967296 <= 2147483647 then (4 + load_firmware_~base~12#1) % 4294967296 % 4294967296 else (4 + load_firmware_~base~12#1) % 4294967296 % 4294967296 - 4294967296)); {15490#true} is VALID [2022-02-20 22:02:41,413 INFO L290 TraceCheckUtils]: 241: Hoare triple {15490#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {15490#true} is VALID [2022-02-20 22:02:41,414 INFO L290 TraceCheckUtils]: 242: Hoare triple {15490#true} assume true; {15490#true} is VALID [2022-02-20 22:02:41,414 INFO L284 TraceCheckUtils]: 243: Hoare quadruple {15490#true} {15491#false} #3928#return; {15491#false} is VALID [2022-02-20 22:02:41,414 INFO L290 TraceCheckUtils]: 244: Hoare triple {15491#false} load_firmware_~status~1#1 := load_firmware_#t~ret555#1;havoc load_firmware_#t~ret555#1; {15491#false} is VALID [2022-02-20 22:02:41,414 INFO L290 TraceCheckUtils]: 245: Hoare triple {15491#false} assume !(0 != load_firmware_~status~1#1 % 65536 % 4294967296);assume { :begin_inline_kmalloc } true;kmalloc_#in~size#1, kmalloc_#in~flags#1 := 2 * (load_firmware_~word_count~2#1 % 65536), 208;havoc kmalloc_#res#1.base, kmalloc_#res#1.offset;havoc kmalloc_#t~ret732#1.base, kmalloc_#t~ret732#1.offset, kmalloc_~size#1, kmalloc_~flags#1;kmalloc_~size#1 := kmalloc_#in~size#1;kmalloc_~flags#1 := kmalloc_#in~flags#1;assume { :begin_inline_ldv_check_alloc_flags } true;ldv_check_alloc_flags_#in~flags#1 := kmalloc_~flags#1;havoc ldv_check_alloc_flags_~flags#1;ldv_check_alloc_flags_~flags#1 := ldv_check_alloc_flags_#in~flags#1; {15491#false} is VALID [2022-02-20 22:02:41,414 INFO L290 TraceCheckUtils]: 246: Hoare triple {15491#false} assume !(0 == ~ldv_spin~0 || 0 == (if 0 == ldv_check_alloc_flags_~flags#1 then 0 else (if 1 == ldv_check_alloc_flags_~flags#1 then 0 else ~bitwiseAnd(ldv_check_alloc_flags_~flags#1, 16))) % 4294967296); {15491#false} is VALID [2022-02-20 22:02:41,414 INFO L272 TraceCheckUtils]: 247: Hoare triple {15491#false} call ldv_error(); {15491#false} is VALID [2022-02-20 22:02:41,414 INFO L290 TraceCheckUtils]: 248: Hoare triple {15491#false} assume !false; {15491#false} is VALID [2022-02-20 22:02:41,415 INFO L134 CoverageAnalysis]: Checked inductivity of 251 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 237 trivial. 0 not checked. [2022-02-20 22:02:41,415 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:02:41,415 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127788883] [2022-02-20 22:02:41,416 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127788883] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:02:41,416 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:02:41,416 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-02-20 22:02:41,416 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [535046179] [2022-02-20 22:02:41,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:02:41,418 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 21.666666666666668) internal successors, (130), 4 states have internal predecessors, (130), 2 states have call successors, (34), 4 states have call predecessors, (34), 2 states have return successors, (33), 2 states have call predecessors, (33), 2 states have call successors, (33) Word has length 249 [2022-02-20 22:02:41,418 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:02:41,419 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 21.666666666666668) internal successors, (130), 4 states have internal predecessors, (130), 2 states have call successors, (34), 4 states have call predecessors, (34), 2 states have return successors, (33), 2 states have call predecessors, (33), 2 states have call successors, (33) [2022-02-20 22:02:41,583 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 197 edges. 197 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:02:41,583 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-02-20 22:02:41,584 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:02:41,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-02-20 22:02:41,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-02-20 22:02:41,585 INFO L87 Difference]: Start difference. First operand 2426 states and 3578 transitions. Second operand has 6 states, 6 states have (on average 21.666666666666668) internal successors, (130), 4 states have internal predecessors, (130), 2 states have call successors, (34), 4 states have call predecessors, (34), 2 states have return successors, (33), 2 states have call predecessors, (33), 2 states have call successors, (33)