./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-ethernet-hp-hp100.cil.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-ethernet-hp-hp100.cil.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash c76818fb304a0b40bd70831524c213fb48469a57ba59c902bf604bd33d1e93eb --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 22:37:37,267 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 22:37:37,269 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 22:37:37,297 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 22:37:37,297 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 22:37:37,300 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 22:37:37,302 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 22:37:37,308 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 22:37:37,310 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 22:37:37,315 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 22:37:37,315 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 22:37:37,316 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 22:37:37,317 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 22:37:37,319 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 22:37:37,320 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 22:37:37,322 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 22:37:37,323 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 22:37:37,323 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 22:37:37,328 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 22:37:37,333 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 22:37:37,335 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 22:37:37,336 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 22:37:37,337 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 22:37:37,338 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 22:37:37,340 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 22:37:37,340 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 22:37:37,341 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 22:37:37,342 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 22:37:37,342 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 22:37:37,343 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 22:37:37,344 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 22:37:37,344 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 22:37:37,346 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 22:37:37,346 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 22:37:37,347 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 22:37:37,348 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 22:37:37,348 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 22:37:37,348 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 22:37:37,348 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 22:37:37,349 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 22:37:37,349 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 22:37:37,350 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 22:37:37,382 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 22:37:37,383 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 22:37:37,383 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 22:37:37,383 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 22:37:37,384 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 22:37:37,384 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 22:37:37,384 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 22:37:37,385 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 22:37:37,385 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 22:37:37,385 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 22:37:37,385 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 22:37:37,386 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 22:37:37,386 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 22:37:37,386 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 22:37:37,386 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 22:37:37,386 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 22:37:37,386 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 22:37:37,387 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 22:37:37,387 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 22:37:37,387 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 22:37:37,387 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 22:37:37,387 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:37:37,387 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 22:37:37,387 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 22:37:37,388 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 22:37:37,388 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 22:37:37,388 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 22:37:37,388 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 22:37:37,388 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 22:37:37,388 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 22:37:37,388 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c76818fb304a0b40bd70831524c213fb48469a57ba59c902bf604bd33d1e93eb [2022-02-20 22:37:37,598 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 22:37:37,613 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 22:37:37,615 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 22:37:37,616 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 22:37:37,617 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 22:37:37,618 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-ethernet-hp-hp100.cil.i [2022-02-20 22:37:37,688 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6135c28fa/f3a92a388976431d812f9522b438f085/FLAGc6f193742 [2022-02-20 22:37:38,288 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 22:37:38,289 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-ethernet-hp-hp100.cil.i [2022-02-20 22:37:38,333 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6135c28fa/f3a92a388976431d812f9522b438f085/FLAGc6f193742 [2022-02-20 22:37:38,419 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6135c28fa/f3a92a388976431d812f9522b438f085 [2022-02-20 22:37:38,422 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 22:37:38,423 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 22:37:38,424 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 22:37:38,424 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 22:37:38,426 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 22:37:38,427 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:37:38" (1/1) ... [2022-02-20 22:37:38,427 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@22786f49 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:38, skipping insertion in model container [2022-02-20 22:37:38,427 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:37:38" (1/1) ... [2022-02-20 22:37:38,432 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 22:37:38,503 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 22:37:40,309 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-ethernet-hp-hp100.cil.i[315653,315666] [2022-02-20 22:37:40,311 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-ethernet-hp-hp100.cil.i[315798,315811] [2022-02-20 22:37:40,330 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:37:40,370 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 22:37:40,637 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-ethernet-hp-hp100.cil.i[315653,315666] [2022-02-20 22:37:40,638 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-ethernet-hp-hp100.cil.i[315798,315811] [2022-02-20 22:37:40,642 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:37:40,753 INFO L208 MainTranslator]: Completed translation [2022-02-20 22:37:40,753 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40 WrapperNode [2022-02-20 22:37:40,753 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 22:37:40,755 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 22:37:40,755 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 22:37:40,755 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 22:37:40,760 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:40,845 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:41,015 INFO L137 Inliner]: procedures = 390, calls = 1855, calls flagged for inlining = 177, calls inlined = 157, statements flattened = 4389 [2022-02-20 22:37:41,016 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 22:37:41,017 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 22:37:41,017 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 22:37:41,017 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 22:37:41,023 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:41,024 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:41,059 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:41,060 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:41,142 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:41,160 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:41,175 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:41,197 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 22:37:41,198 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 22:37:41,198 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 22:37:41,198 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 22:37:41,199 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (1/1) ... [2022-02-20 22:37:41,220 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:37:41,228 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:37:41,239 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 22:37:41,254 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 22:37:41,266 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2022-02-20 22:37:41,266 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2022-02-20 22:37:41,266 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_alloc_skb [2022-02-20 22:37:41,266 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_alloc_skb [2022-02-20 22:37:41,266 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_89 [2022-02-20 22:37:41,266 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_89 [2022-02-20 22:37:41,266 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 22:37:41,267 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 22:37:41,267 INFO L130 BoogieDeclarations]: Found specification of procedure valid_dma_direction [2022-02-20 22:37:41,267 INFO L138 BoogieDeclarations]: Found implementation of procedure valid_dma_direction [2022-02-20 22:37:41,267 INFO L130 BoogieDeclarations]: Found specification of procedure dev_trans_start [2022-02-20 22:37:41,267 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_trans_start [2022-02-20 22:37:41,267 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_open [2022-02-20 22:37:41,267 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_open [2022-02-20 22:37:41,267 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_load_eeprom [2022-02-20 22:37:41,268 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_load_eeprom [2022-02-20 22:37:41,268 INFO L130 BoogieDeclarations]: Found specification of procedure memcmp [2022-02-20 22:37:41,268 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_sense_lan [2022-02-20 22:37:41,268 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_sense_lan [2022-02-20 22:37:41,268 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_xmalloc [2022-02-20 22:37:41,268 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_xmalloc [2022-02-20 22:37:41,268 INFO L130 BoogieDeclarations]: Found specification of procedure netif_rx [2022-02-20 22:37:41,268 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_rx [2022-02-20 22:37:41,268 INFO L130 BoogieDeclarations]: Found specification of procedure eth_validate_addr [2022-02-20 22:37:41,269 INFO L138 BoogieDeclarations]: Found implementation of procedure eth_validate_addr [2022-02-20 22:37:41,269 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_is_err [2022-02-20 22:37:41,269 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_is_err [2022-02-20 22:37:41,269 INFO L130 BoogieDeclarations]: Found specification of procedure pci_unmap_single [2022-02-20 22:37:41,269 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_unmap_single [2022-02-20 22:37:41,269 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 22:37:41,269 INFO L130 BoogieDeclarations]: Found specification of procedure iounmap [2022-02-20 22:37:41,269 INFO L138 BoogieDeclarations]: Found implementation of procedure iounmap [2022-02-20 22:37:41,269 INFO L130 BoogieDeclarations]: Found specification of procedure pci_write_config_word [2022-02-20 22:37:41,270 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_write_config_word [2022-02-20 22:37:41,270 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_103 [2022-02-20 22:37:41,270 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_103 [2022-02-20 22:37:41,270 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_get_tx_queue [2022-02-20 22:37:41,270 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_get_tx_queue [2022-02-20 22:37:41,270 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_cascade_reset [2022-02-20 22:37:41,271 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_cascade_reset [2022-02-20 22:37:41,271 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2022-02-20 22:37:41,271 INFO L130 BoogieDeclarations]: Found specification of procedure get_dma_ops [2022-02-20 22:37:41,271 INFO L138 BoogieDeclarations]: Found implementation of procedure get_dma_ops [2022-02-20 22:37:41,271 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2022-02-20 22:37:41,271 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assume [2022-02-20 22:37:41,271 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assume [2022-02-20 22:37:41,271 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 22:37:41,272 INFO L130 BoogieDeclarations]: Found specification of procedure __phys_addr [2022-02-20 22:37:41,272 INFO L138 BoogieDeclarations]: Found implementation of procedure __phys_addr [2022-02-20 22:37:41,272 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2022-02-20 22:37:41,272 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2022-02-20 22:37:41,272 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_rx_bm [2022-02-20 22:37:41,272 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_rx_bm [2022-02-20 22:37:41,273 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_BM_shutdown [2022-02-20 22:37:41,273 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_BM_shutdown [2022-02-20 22:37:41,273 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2022-02-20 22:37:41,274 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2022-02-20 22:37:41,274 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_err_code [2022-02-20 22:37:41,274 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_err_code [2022-02-20 22:37:41,275 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_alloc_flags [2022-02-20 22:37:41,275 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_alloc_flags [2022-02-20 22:37:41,275 INFO L130 BoogieDeclarations]: Found specification of procedure wait [2022-02-20 22:37:41,275 INFO L138 BoogieDeclarations]: Found implementation of procedure wait [2022-02-20 22:37:41,275 INFO L130 BoogieDeclarations]: Found specification of procedure pci_free_consistent [2022-02-20 22:37:41,275 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_free_consistent [2022-02-20 22:37:41,275 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_hwinit [2022-02-20 22:37:41,276 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_hwinit [2022-02-20 22:37:41,276 INFO L130 BoogieDeclarations]: Found specification of procedure pci_disable_device [2022-02-20 22:37:41,276 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_disable_device [2022-02-20 22:37:41,276 INFO L130 BoogieDeclarations]: Found specification of procedure virt_to_whatever [2022-02-20 22:37:41,276 INFO L138 BoogieDeclarations]: Found implementation of procedure virt_to_whatever [2022-02-20 22:37:41,276 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_close [2022-02-20 22:37:41,277 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_close [2022-02-20 22:37:41,277 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 22:37:41,277 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_stop_interface [2022-02-20 22:37:41,277 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_stop_interface [2022-02-20 22:37:41,277 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_check_lan [2022-02-20 22:37:41,277 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_check_lan [2022-02-20 22:37:41,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_switch_1 [2022-02-20 22:37:41,277 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_switch_1 [2022-02-20 22:37:41,277 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 22:37:41,278 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_int [2022-02-20 22:37:41,278 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_int [2022-02-20 22:37:41,278 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2022-02-20 22:37:41,278 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2022-02-20 22:37:41,278 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-02-20 22:37:41,278 INFO L130 BoogieDeclarations]: Found specification of procedure __bad_percpu_size [2022-02-20 22:37:41,278 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 22:37:41,279 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 22:37:41,279 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~int [2022-02-20 22:37:41,279 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~int [2022-02-20 22:37:41,279 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_exclusive_spin_is_locked [2022-02-20 22:37:41,279 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_exclusive_spin_is_locked [2022-02-20 22:37:41,279 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assert [2022-02-20 22:37:41,280 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assert [2022-02-20 22:37:41,280 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_spin_lock [2022-02-20 22:37:41,280 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_spin_lock [2022-02-20 22:37:41,280 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_rxfill [2022-02-20 22:37:41,280 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_rxfill [2022-02-20 22:37:41,280 INFO L130 BoogieDeclarations]: Found specification of procedure warn_slowpath_null [2022-02-20 22:37:41,281 INFO L138 BoogieDeclarations]: Found implementation of procedure warn_slowpath_null [2022-02-20 22:37:41,281 INFO L130 BoogieDeclarations]: Found specification of procedure skb_put [2022-02-20 22:37:41,281 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_put [2022-02-20 22:37:41,281 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_netdev [2022-02-20 22:37:41,281 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_netdev [2022-02-20 22:37:41,281 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 22:37:41,281 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 22:37:41,281 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_update_stats [2022-02-20 22:37:41,281 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_update_stats [2022-02-20 22:37:41,282 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2022-02-20 22:37:41,282 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2022-02-20 22:37:41,282 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 22:37:41,282 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 22:37:41,282 INFO L130 BoogieDeclarations]: Found specification of procedure pci_map_single [2022-02-20 22:37:41,282 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_map_single [2022-02-20 22:37:41,282 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-02-20 22:37:41,283 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-02-20 22:37:41,283 INFO L130 BoogieDeclarations]: Found specification of procedure consume_skb [2022-02-20 22:37:41,285 INFO L138 BoogieDeclarations]: Found implementation of procedure consume_skb [2022-02-20 22:37:41,285 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 22:37:41,285 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 22:37:41,285 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 22:37:41,286 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 22:37:41,287 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 22:37:41,287 INFO L130 BoogieDeclarations]: Found specification of procedure outw [2022-02-20 22:37:41,287 INFO L138 BoogieDeclarations]: Found implementation of procedure outw [2022-02-20 22:37:41,287 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_priv [2022-02-20 22:37:41,291 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_priv [2022-02-20 22:37:41,291 INFO L130 BoogieDeclarations]: Found specification of procedure outb [2022-02-20 22:37:41,291 INFO L138 BoogieDeclarations]: Found implementation of procedure outb [2022-02-20 22:37:41,291 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_positive_int [2022-02-20 22:37:41,291 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_positive_int [2022-02-20 22:37:41,291 INFO L130 BoogieDeclarations]: Found specification of procedure outl [2022-02-20 22:37:41,292 INFO L138 BoogieDeclarations]: Found implementation of procedure outl [2022-02-20 22:37:41,292 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_pci_remove [2022-02-20 22:37:41,292 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_pci_remove [2022-02-20 22:37:41,292 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_build_rx_pdl [2022-02-20 22:37:41,292 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_build_rx_pdl [2022-02-20 22:37:41,292 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reserve [2022-02-20 22:37:41,292 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reserve [2022-02-20 22:37:41,292 INFO L130 BoogieDeclarations]: Found specification of procedure free_netdev [2022-02-20 22:37:41,292 INFO L138 BoogieDeclarations]: Found implementation of procedure free_netdev [2022-02-20 22:37:41,292 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2022-02-20 22:37:41,293 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2022-02-20 22:37:41,293 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_lock_of_hp100_private [2022-02-20 22:37:41,293 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_lock_of_hp100_private [2022-02-20 22:37:41,293 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 22:37:41,293 INFO L130 BoogieDeclarations]: Found specification of procedure eth_type_trans [2022-02-20 22:37:41,293 INFO L138 BoogieDeclarations]: Found implementation of procedure eth_type_trans [2022-02-20 22:37:41,293 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2022-02-20 22:37:41,293 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2022-02-20 22:37:41,293 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_lock_of_hp100_private [2022-02-20 22:37:41,293 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_lock_of_hp100_private [2022-02-20 22:37:41,294 INFO L130 BoogieDeclarations]: Found specification of procedure schedule_timeout_interruptible [2022-02-20 22:37:41,294 INFO L138 BoogieDeclarations]: Found implementation of procedure schedule_timeout_interruptible [2022-02-20 22:37:41,294 INFO L130 BoogieDeclarations]: Found specification of procedure dev_kfree_skb_any [2022-02-20 22:37:41,294 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_kfree_skb_any [2022-02-20 22:37:41,294 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free [2022-02-20 22:37:41,294 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free [2022-02-20 22:37:41,294 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_set_multicast_list [2022-02-20 22:37:41,294 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_set_multicast_list [2022-02-20 22:37:41,294 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_start_interface [2022-02-20 22:37:41,294 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_start_interface [2022-02-20 22:37:41,295 INFO L130 BoogieDeclarations]: Found specification of procedure inb [2022-02-20 22:37:41,295 INFO L138 BoogieDeclarations]: Found implementation of procedure inb [2022-02-20 22:37:41,295 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_clean_txring [2022-02-20 22:37:41,295 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_clean_txring [2022-02-20 22:37:41,295 INFO L130 BoogieDeclarations]: Found specification of procedure inl [2022-02-20 22:37:41,295 INFO L138 BoogieDeclarations]: Found implementation of procedure inl [2022-02-20 22:37:41,295 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 22:37:41,295 INFO L130 BoogieDeclarations]: Found specification of procedure inw [2022-02-20 22:37:41,295 INFO L138 BoogieDeclarations]: Found implementation of procedure inw [2022-02-20 22:37:41,295 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2022-02-20 22:37:41,296 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2022-02-20 22:37:41,296 INFO L130 BoogieDeclarations]: Found specification of procedure hp100_login_to_vg_hub [2022-02-20 22:37:41,296 INFO L138 BoogieDeclarations]: Found implementation of procedure hp100_login_to_vg_hub [2022-02-20 22:37:41,296 INFO L130 BoogieDeclarations]: Found specification of procedure preempt_count [2022-02-20 22:37:41,296 INFO L138 BoogieDeclarations]: Found implementation of procedure preempt_count [2022-02-20 22:37:41,818 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 22:37:41,820 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 22:37:42,073 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 22:37:44,576 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ULTIMATE.startFINAL: assume true; [2022-02-20 22:37:44,577 WARN L813 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2022-02-20 22:37:44,791 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint L8566-1: assume -9223372036854775808 <= #t~ret695#1 && #t~ret695#1 <= 9223372036854775807;havoc #t~ret695#1; [2022-02-20 22:37:44,791 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint L8566: SUMMARY for call #t~ret695#1 := schedule_timeout_interruptible(1); srcloc: null [2022-02-20 22:37:44,791 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##8: assume 0 == (if 0 == ~tmp___4~7#1 then 0 else (if 1 == ~tmp___4~7#1 then 0 else ~bitwiseAnd(~tmp___4~7#1, 2096896))) % 18446744073709551616; [2022-02-20 22:37:44,791 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##9: assume !(0 == (if 0 == ~tmp___4~7#1 then 0 else (if 1 == ~tmp___4~7#1 then 0 else ~bitwiseAnd(~tmp___4~7#1, 2096896))) % 18446744073709551616); [2022-02-20 22:37:44,792 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint L8570: assume (if (~jiffies~0 - ~time~2#1) % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then (~jiffies~0 - ~time~2#1) % 18446744073709551616 % 18446744073709551616 else (~jiffies~0 - ~time~2#1) % 18446744073709551616 % 18446744073709551616 - 18446744073709551616) < 0; [2022-02-20 22:37:44,792 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint L8570: assume !((if (~jiffies~0 - ~time~2#1) % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then (~jiffies~0 - ~time~2#1) % 18446744073709551616 % 18446744073709551616 else (~jiffies~0 - ~time~2#1) % 18446744073709551616 % 18446744073709551616 - 18446744073709551616) < 0); [2022-02-20 22:37:44,870 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 22:37:44,885 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 22:37:44,885 INFO L299 CfgBuilder]: Removed 2 assume(true) statements. [2022-02-20 22:37:44,887 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:37:44 BoogieIcfgContainer [2022-02-20 22:37:44,888 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 22:37:44,889 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 22:37:44,889 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 22:37:44,891 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 22:37:44,892 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 10:37:38" (1/3) ... [2022-02-20 22:37:44,892 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31d99b48 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:37:44, skipping insertion in model container [2022-02-20 22:37:44,892 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:37:40" (2/3) ... [2022-02-20 22:37:44,892 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@31d99b48 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:37:44, skipping insertion in model container [2022-02-20 22:37:44,893 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:37:44" (3/3) ... [2022-02-20 22:37:44,894 INFO L111 eAbstractionObserver]: Analyzing ICFG linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-ethernet-hp-hp100.cil.i [2022-02-20 22:37:44,897 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 22:37:44,897 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-02-20 22:37:44,933 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 22:37:44,938 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 22:37:44,938 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-02-20 22:37:44,988 INFO L276 IsEmpty]: Start isEmpty. Operand has 1805 states, 1157 states have (on average 1.3267070008643043) internal successors, (1535), 1205 states have internal predecessors, (1535), 569 states have call successors, (569), 80 states have call predecessors, (569), 79 states have return successors, (564), 548 states have call predecessors, (564), 564 states have call successors, (564) [2022-02-20 22:37:45,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2022-02-20 22:37:45,004 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:37:45,004 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 4, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:37:45,005 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:37:45,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:37:45,009 INFO L85 PathProgramCache]: Analyzing trace with hash 861348699, now seen corresponding path program 1 times [2022-02-20 22:37:45,015 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:37:45,015 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654110766] [2022-02-20 22:37:45,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:37:45,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:37:45,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,395 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-02-20 22:37:45,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,423 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:37:45,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,438 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,438 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,438 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,439 INFO L290 TraceCheckUtils]: 0: Hoare triple {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {1808#true} is VALID [2022-02-20 22:37:45,439 INFO L272 TraceCheckUtils]: 1: Hoare triple {1808#true} call #t~ret868 := ldv_undef_int(); {1808#true} is VALID [2022-02-20 22:37:45,439 INFO L290 TraceCheckUtils]: 2: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,440 INFO L290 TraceCheckUtils]: 3: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,440 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,440 INFO L290 TraceCheckUtils]: 5: Hoare triple {1808#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {1808#true} is VALID [2022-02-20 22:37:45,440 INFO L290 TraceCheckUtils]: 6: Hoare triple {1808#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {1808#true} is VALID [2022-02-20 22:37:45,441 INFO L290 TraceCheckUtils]: 7: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,441 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1808#true} {1808#true} #4324#return; {1808#true} is VALID [2022-02-20 22:37:45,441 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 14 [2022-02-20 22:37:45,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,456 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:37:45,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,464 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,465 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,465 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,465 INFO L290 TraceCheckUtils]: 0: Hoare triple {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {1808#true} is VALID [2022-02-20 22:37:45,466 INFO L272 TraceCheckUtils]: 1: Hoare triple {1808#true} call #t~ret868 := ldv_undef_int(); {1808#true} is VALID [2022-02-20 22:37:45,468 INFO L290 TraceCheckUtils]: 2: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,468 INFO L290 TraceCheckUtils]: 3: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,469 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,469 INFO L290 TraceCheckUtils]: 5: Hoare triple {1808#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {1808#true} is VALID [2022-02-20 22:37:45,469 INFO L290 TraceCheckUtils]: 6: Hoare triple {1808#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {1808#true} is VALID [2022-02-20 22:37:45,469 INFO L290 TraceCheckUtils]: 7: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,469 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1808#true} {1808#true} #4326#return; {1808#true} is VALID [2022-02-20 22:37:45,470 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 25 [2022-02-20 22:37:45,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,481 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:37:45,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,495 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,495 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,495 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,495 INFO L290 TraceCheckUtils]: 0: Hoare triple {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {1808#true} is VALID [2022-02-20 22:37:45,496 INFO L272 TraceCheckUtils]: 1: Hoare triple {1808#true} call #t~ret868 := ldv_undef_int(); {1808#true} is VALID [2022-02-20 22:37:45,496 INFO L290 TraceCheckUtils]: 2: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,496 INFO L290 TraceCheckUtils]: 3: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,496 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,496 INFO L290 TraceCheckUtils]: 5: Hoare triple {1808#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {1808#true} is VALID [2022-02-20 22:37:45,497 INFO L290 TraceCheckUtils]: 6: Hoare triple {1808#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {1808#true} is VALID [2022-02-20 22:37:45,497 INFO L290 TraceCheckUtils]: 7: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,497 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1808#true} {1808#true} #4328#return; {1808#true} is VALID [2022-02-20 22:37:45,497 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2022-02-20 22:37:45,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,510 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:37:45,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,518 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,518 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,518 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,519 INFO L290 TraceCheckUtils]: 0: Hoare triple {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {1808#true} is VALID [2022-02-20 22:37:45,519 INFO L272 TraceCheckUtils]: 1: Hoare triple {1808#true} call #t~ret868 := ldv_undef_int(); {1808#true} is VALID [2022-02-20 22:37:45,519 INFO L290 TraceCheckUtils]: 2: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,519 INFO L290 TraceCheckUtils]: 3: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,519 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,520 INFO L290 TraceCheckUtils]: 5: Hoare triple {1808#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {1808#true} is VALID [2022-02-20 22:37:45,520 INFO L290 TraceCheckUtils]: 6: Hoare triple {1808#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {1808#true} is VALID [2022-02-20 22:37:45,520 INFO L290 TraceCheckUtils]: 7: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,522 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1808#true} {1808#true} #4330#return; {1808#true} is VALID [2022-02-20 22:37:45,523 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 49 [2022-02-20 22:37:45,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,537 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,537 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,538 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1846#(= 6 ~ldv_statevar_0~0)} #4332#return; {1846#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:37:45,538 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 62 [2022-02-20 22:37:45,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,545 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1808#true} is VALID [2022-02-20 22:37:45,546 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,546 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1809#false} #4368#return; {1809#false} is VALID [2022-02-20 22:37:45,549 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 68 [2022-02-20 22:37:45,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,561 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-02-20 22:37:45,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,568 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {1808#true} is VALID [2022-02-20 22:37:45,569 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,570 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1893#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} #4016#return; {1808#true} is VALID [2022-02-20 22:37:45,570 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 22:37:45,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,580 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} ~expression := #in~expression; {1808#true} is VALID [2022-02-20 22:37:45,580 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume !(0 == ~expression); {1808#true} is VALID [2022-02-20 22:37:45,580 INFO L290 TraceCheckUtils]: 2: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,580 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1808#true} {1808#true} #4018#return; {1808#true} is VALID [2022-02-20 22:37:45,581 INFO L272 TraceCheckUtils]: 0: Hoare triple {1893#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} call ldv_assert(87, 0, (if 1 == ~ldv_spin_lock_of_hp100_private~0 then 1 else 0)); {1808#true} is VALID [2022-02-20 22:37:45,581 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {1808#true} is VALID [2022-02-20 22:37:45,581 INFO L290 TraceCheckUtils]: 2: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,581 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1808#true} {1893#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} #4016#return; {1808#true} is VALID [2022-02-20 22:37:45,581 INFO L272 TraceCheckUtils]: 4: Hoare triple {1808#true} call ldv_assume((if 1 == ~ldv_spin_lock_of_hp100_private~0 then 1 else 0)); {1808#true} is VALID [2022-02-20 22:37:45,581 INFO L290 TraceCheckUtils]: 5: Hoare triple {1808#true} ~expression := #in~expression; {1808#true} is VALID [2022-02-20 22:37:45,582 INFO L290 TraceCheckUtils]: 6: Hoare triple {1808#true} assume !(0 == ~expression); {1808#true} is VALID [2022-02-20 22:37:45,582 INFO L290 TraceCheckUtils]: 7: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,582 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1808#true} {1808#true} #4018#return; {1808#true} is VALID [2022-02-20 22:37:45,582 INFO L290 TraceCheckUtils]: 9: Hoare triple {1808#true} ~ldv_spin_lock_of_hp100_private~0 := 2; {1808#true} is VALID [2022-02-20 22:37:45,582 INFO L290 TraceCheckUtils]: 10: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,582 INFO L284 TraceCheckUtils]: 11: Hoare quadruple {1808#true} {1809#false} #4370#return; {1809#false} is VALID [2022-02-20 22:37:45,583 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 85 [2022-02-20 22:37:45,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,592 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} ~value := #in~value;~port := #in~port; {1808#true} is VALID [2022-02-20 22:37:45,593 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,593 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1809#false} #4372#return; {1809#false} is VALID [2022-02-20 22:37:45,593 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 89 [2022-02-20 22:37:45,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,600 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} ~port := #in~port;havoc ~value~1;#res := ~value~1; {1808#true} is VALID [2022-02-20 22:37:45,601 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,601 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1809#false} #4374#return; {1809#false} is VALID [2022-02-20 22:37:45,601 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 98 [2022-02-20 22:37:45,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,608 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1808#true} is VALID [2022-02-20 22:37:45,608 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,608 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1809#false} #4382#return; {1809#false} is VALID [2022-02-20 22:37:45,609 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 103 [2022-02-20 22:37:45,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,615 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1808#true} is VALID [2022-02-20 22:37:45,616 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,616 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1809#false} #4384#return; {1809#false} is VALID [2022-02-20 22:37:45,616 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 121 [2022-02-20 22:37:45,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:37:45,624 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} assume 2 == ~ldv_spin__xmit_lock_of_netdev_queue~0;#res := 1; {1808#true} is VALID [2022-02-20 22:37:45,624 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,624 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1808#true} {1809#false} #3826#return; {1809#false} is VALID [2022-02-20 22:37:45,633 INFO L290 TraceCheckUtils]: 0: Hoare triple {1808#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(190, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(5, 4);call write~init~int(37, 4, 0, 1);call write~init~int(48, 4, 1, 1);call write~init~int(52, 4, 2, 1);call write~init~int(88, 4, 3, 1);call write~init~int(0, 4, 4, 1);call #Ultimate.allocInit(6, 5);call write~init~int(104, 5, 0, 1);call write~init~int(112, 5, 1, 1);call write~init~int(49, 5, 2, 1);call write~init~int(48, 5, 3, 1);call write~init~int(48, 5, 4, 1);call write~init~int(0, 5, 5, 1);call #Ultimate.allocInit(49, 6);call #Ultimate.allocInit(54, 7);call #Ultimate.allocInit(31, 8);call #Ultimate.allocInit(38, 9);call #Ultimate.allocInit(34, 10);call #Ultimate.allocInit(32, 11);call #Ultimate.allocInit(42, 12);call #Ultimate.allocInit(81, 13);call #Ultimate.allocInit(42, 14);call #Ultimate.allocInit(20, 15);call #Ultimate.allocInit(25, 16);call #Ultimate.allocInit(5, 17);call write~init~int(69, 17, 0, 1);call write~init~int(73, 17, 1, 1);call write~init~int(83, 17, 2, 1);call write~init~int(65, 17, 3, 1);call write~init~int(0, 17, 4, 1);call #Ultimate.allocInit(4, 18);call write~init~int(80, 18, 0, 1);call write~init~int(67, 18, 1, 1);call write~init~int(73, 18, 2, 1);call write~init~int(0, 18, 3, 1);call #Ultimate.allocInit(4, 19);call write~init~int(73, 19, 0, 1);call write~init~int(83, 19, 1, 1);call write~init~int(65, 19, 2, 1);call write~init~int(0, 19, 3, 1);call #Ultimate.allocInit(30, 20);call #Ultimate.allocInit(34, 21);call #Ultimate.allocInit(19, 22);call #Ultimate.allocInit(3, 23);call write~init~int(46, 23, 0, 1);call write~init~int(10, 23, 1, 1);call write~init~int(0, 23, 2, 1);call #Ultimate.allocInit(8, 24);call #Ultimate.allocInit(24, 25);call #Ultimate.allocInit(37, 26);call #Ultimate.allocInit(27, 27);call #Ultimate.allocInit(24, 28);call #Ultimate.allocInit(21, 29);call #Ultimate.allocInit(33, 30);call #Ultimate.allocInit(58, 31);call #Ultimate.allocInit(48, 32);call #Ultimate.allocInit(48, 33);call #Ultimate.allocInit(31, 34);call #Ultimate.allocInit(45, 35);call #Ultimate.allocInit(39, 36);call #Ultimate.allocInit(31, 37);call #Ultimate.allocInit(53, 38);call #Ultimate.allocInit(28, 39);call #Ultimate.allocInit(39, 40);call #Ultimate.allocInit(31, 41);call #Ultimate.allocInit(53, 42);call #Ultimate.allocInit(28, 43);call #Ultimate.allocInit(28, 44);call #Ultimate.allocInit(64, 45);call #Ultimate.allocInit(43, 46);call #Ultimate.allocInit(40, 47);call #Ultimate.allocInit(8, 48);call #Ultimate.allocInit(42, 49);call #Ultimate.allocInit(31, 50);call #Ultimate.allocInit(64, 51);call #Ultimate.allocInit(50, 52);call #Ultimate.allocInit(29, 53);call #Ultimate.allocInit(6, 54);call write~init~int(104, 54, 0, 1);call write~init~int(112, 54, 1, 1);call write~init~int(49, 54, 2, 1);call write~init~int(48, 54, 3, 1);call write~init~int(48, 54, 4, 1);call write~init~int(0, 54, 5, 1);call #Ultimate.allocInit(6, 55);call write~init~int(104, 55, 0, 1);call write~init~int(112, 55, 1, 1);call write~init~int(49, 55, 2, 1);call write~init~int(48, 55, 3, 1);call write~init~int(48, 55, 4, 1);call write~init~int(0, 55, 5, 1);call #Ultimate.allocInit(1, 56);call write~init~int(0, 56, 0, 1);call #Ultimate.allocInit(54, 57);call #Ultimate.allocInit(56, 58);call #Ultimate.allocInit(58, 59);call #Ultimate.allocInit(58, 60);call #Ultimate.allocInit(58, 61);call #Ultimate.allocInit(54, 62);call #Ultimate.allocInit(56, 63);call #Ultimate.allocInit(58, 64);call #Ultimate.allocInit(58, 65);call #Ultimate.allocInit(58, 66);call #Ultimate.allocInit(54, 67);call #Ultimate.allocInit(56, 68);call #Ultimate.allocInit(58, 69);call #Ultimate.allocInit(58, 70);call #Ultimate.allocInit(58, 71);call #Ultimate.allocInit(54, 72);call #Ultimate.allocInit(56, 73);call #Ultimate.allocInit(58, 74);call #Ultimate.allocInit(58, 75);call #Ultimate.allocInit(58, 76);call #Ultimate.allocInit(54, 77);call #Ultimate.allocInit(56, 78);call #Ultimate.allocInit(58, 79);call #Ultimate.allocInit(58, 80);call #Ultimate.allocInit(58, 81);call #Ultimate.allocInit(54, 82);call #Ultimate.allocInit(56, 83);call #Ultimate.allocInit(58, 84);call #Ultimate.allocInit(58, 85);call #Ultimate.allocInit(58, 86);call #Ultimate.allocInit(54, 87);call #Ultimate.allocInit(56, 88);call #Ultimate.allocInit(58, 89);call #Ultimate.allocInit(58, 90);call #Ultimate.allocInit(58, 91);call #Ultimate.allocInit(54, 92);call #Ultimate.allocInit(56, 93);call #Ultimate.allocInit(58, 94);call #Ultimate.allocInit(58, 95);call #Ultimate.allocInit(58, 96);call #Ultimate.allocInit(54, 97);call #Ultimate.allocInit(56, 98);call #Ultimate.allocInit(58, 99);call #Ultimate.allocInit(58, 100);call #Ultimate.allocInit(58, 101);call #Ultimate.allocInit(54, 102);call #Ultimate.allocInit(56, 103);call #Ultimate.allocInit(58, 104);call #Ultimate.allocInit(58, 105);call #Ultimate.allocInit(58, 106);call #Ultimate.allocInit(54, 107);call #Ultimate.allocInit(56, 108);call #Ultimate.allocInit(58, 109);call #Ultimate.allocInit(58, 110);call #Ultimate.allocInit(58, 111);call #Ultimate.allocInit(54, 112);call #Ultimate.allocInit(56, 113);call #Ultimate.allocInit(58, 114);call #Ultimate.allocInit(58, 115);call #Ultimate.allocInit(58, 116);call #Ultimate.allocInit(57, 117);call #Ultimate.allocInit(57, 118);call #Ultimate.allocInit(57, 119);call #Ultimate.allocInit(57, 120);call #Ultimate.allocInit(57, 121);call #Ultimate.allocInit(57, 122);call #Ultimate.allocInit(57, 123);call #Ultimate.allocInit(57, 124);call #Ultimate.allocInit(57, 125);call #Ultimate.allocInit(57, 126);call #Ultimate.allocInit(57, 127);call #Ultimate.allocInit(57, 128);call #Ultimate.allocInit(2, 129);call write~init~int(48, 129, 0, 1);call write~init~int(0, 129, 1, 1);call #Ultimate.allocInit(80, 130);~#hp100_pci_tbl~0.base, ~#hp100_pci_tbl~0.offset := 131, 0;call #Ultimate.allocInit(224, 131);call write~init~int(4156, ~#hp100_pci_tbl~0.base, ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4144, ~#hp100_pci_tbl~0.base, 4 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 8 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 12 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 16 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 20 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 24 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4156, ~#hp100_pci_tbl~0.base, 32 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4145, ~#hp100_pci_tbl~0.base, 36 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 40 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 44 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 48 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 52 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 56 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4156, ~#hp100_pci_tbl~0.base, 64 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4162, ~#hp100_pci_tbl~0.base, 68 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 72 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 76 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 80 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 84 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 88 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4156, ~#hp100_pci_tbl~0.base, 96 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4160, ~#hp100_pci_tbl~0.base, 100 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 104 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 108 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 112 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 116 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 120 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4598, ~#hp100_pci_tbl~0.base, 128 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(274, ~#hp100_pci_tbl~0.base, 132 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 136 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 140 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 144 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 148 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 152 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4122, ~#hp100_pci_tbl~0.base, 160 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(5, ~#hp100_pci_tbl~0.base, 164 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 168 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 172 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 176 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 180 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 184 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(0, ~#hp100_pci_tbl~0.base, 192 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 196 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 200 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 204 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 208 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 212 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 216 + ~#hp100_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~hp100_rx_ratio~0 := 75;~hp100_priority_tx~0 := 0;~hp100_mode~0 := 1;~#hp100_bm_netdev_ops~0.base, ~#hp100_bm_netdev_ops~0.offset := 132, 0;call #Ultimate.allocInit(472, 132);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 8 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_open.base, #funAddr~hp100_open.offset, ~#hp100_bm_netdev_ops~0.base, 16 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_close.base, #funAddr~hp100_close.offset, ~#hp100_bm_netdev_ops~0.base, 24 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_start_xmit_bm.base, #funAddr~hp100_start_xmit_bm.offset, ~#hp100_bm_netdev_ops~0.base, 32 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 40 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 48 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_set_multicast_list.base, #funAddr~hp100_set_multicast_list.offset, ~#hp100_bm_netdev_ops~0.base, 56 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset, ~#hp100_bm_netdev_ops~0.base, 64 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset, ~#hp100_bm_netdev_ops~0.base, 72 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 80 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 88 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset, ~#hp100_bm_netdev_ops~0.base, 96 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 104 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 112 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 120 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_get_stats.base, #funAddr~hp100_get_stats.offset, ~#hp100_bm_netdev_ops~0.base, 128 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 136 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 144 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 152 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 160 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 168 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 176 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 184 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 192 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 200 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 208 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 216 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 224 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 232 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 240 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 248 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 256 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 264 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 272 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 280 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 288 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 296 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 304 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 312 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 320 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 328 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 336 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 344 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 352 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 360 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 368 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 376 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 384 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 392 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 400 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 408 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 416 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 424 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 432 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 440 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 448 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 456 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 464 + ~#hp100_bm_netdev_ops~0.offset, 8);~#hp100_netdev_ops~0.base, ~#hp100_netdev_ops~0.offset := 133, 0;call #Ultimate.allocInit(472, 133);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 8 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_open.base, #funAddr~hp100_open.offset, ~#hp100_netdev_ops~0.base, 16 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_close.base, #funAddr~hp100_close.offset, ~#hp100_netdev_ops~0.base, 24 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_start_xmit.base, #funAddr~hp100_start_xmit.offset, ~#hp100_netdev_ops~0.base, 32 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 40 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 48 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_set_multicast_list.base, #funAddr~hp100_set_multicast_list.offset, ~#hp100_netdev_ops~0.base, 56 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset, ~#hp100_netdev_ops~0.base, 64 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset, ~#hp100_netdev_ops~0.base, 72 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 80 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 88 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset, ~#hp100_netdev_ops~0.base, 96 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 104 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 112 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 120 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_get_stats.base, #funAddr~hp100_get_stats.offset, ~#hp100_netdev_ops~0.base, 128 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 136 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 144 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 152 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 160 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 168 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 176 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 184 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 192 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 200 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 208 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 216 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 224 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 232 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 240 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 248 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 256 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 264 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 272 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 280 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 288 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 296 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 304 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 312 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 320 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 328 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 336 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 344 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 352 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 360 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 368 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 376 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 384 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 392 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 400 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 408 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 416 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 424 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 432 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 440 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 448 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 456 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 464 + ~#hp100_netdev_ops~0.offset, 8);~#hp100_pci_driver~0.base, ~#hp100_pci_driver~0.offset := 134, 0;call #Ultimate.allocInit(301, 134);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 8 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(54, 0, ~#hp100_pci_driver~0.base, 16 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(~#hp100_pci_tbl~0.base, ~#hp100_pci_tbl~0.offset, ~#hp100_pci_driver~0.base, 24 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_pci_probe.base, #funAddr~hp100_pci_probe.offset, ~#hp100_pci_driver~0.base, 32 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_pci_remove.base, #funAddr~hp100_pci_remove.offset, ~#hp100_pci_driver~0.base, 40 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 48 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 56 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 64 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 72 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 80 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 88 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 96 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 104 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 112 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 120 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 128 + ~#hp100_pci_driver~0.offset, 8);call write~init~int(0, ~#hp100_pci_driver~0.base, 136 + ~#hp100_pci_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 137 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 145 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 153 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 161 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 169 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 177 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 185 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 193 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 201 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 209 + ~#hp100_pci_driver~0.offset, 8);call write~init~int(0, ~#hp100_pci_driver~0.base, 217 + ~#hp100_pci_driver~0.offset, 4);call write~init~int(0, ~#hp100_pci_driver~0.base, 221 + ~#hp100_pci_driver~0.offset, 4);call write~init~int(0, ~#hp100_pci_driver~0.base, 225 + ~#hp100_pci_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 229 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 237 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 245 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 253 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 261 + ~#hp100_pci_driver~0.offset, 8);call write~init~int(0, ~#hp100_pci_driver~0.base, 269 + ~#hp100_pci_driver~0.offset, 4);call write~init~int(0, ~#hp100_pci_driver~0.base, 273 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 285 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 293 + ~#hp100_pci_driver~0.offset, 8);~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset := 0, 0;~ldv_0_line_line~0 := 0;~ldv_0_ret_val_default~0 := 0;~ldv_0_thread_thread~0.base, ~ldv_0_thread_thread~0.offset := 0, 0;~ldv_11_ret_default~0 := 0;~ldv_1_container_net_device~0.base, ~ldv_1_container_net_device~0.offset := 0, 0;~ldv_1_container_struct_sk_buff_ptr~0.base, ~ldv_1_container_struct_sk_buff_ptr~0.offset := 0, 0;~ldv_1_ldv_param_3_1_default~0 := 0;~ldv_2_container_pci_driver~0.base, ~ldv_2_container_pci_driver~0.offset := 0, 0;~ldv_2_resource_dev~0.base, ~ldv_2_resource_dev~0.offset := 0, 0;~#ldv_2_resource_pm_message~0.base, ~#ldv_2_resource_pm_message~0.offset := 135, 0;call #Ultimate.allocInit(4, 135);call write~init~int(0, ~#ldv_2_resource_pm_message~0.base, ~#ldv_2_resource_pm_message~0.offset, 4);~ldv_2_resource_struct_pci_device_id_ptr~0.base, ~ldv_2_resource_struct_pci_device_id_ptr~0.offset := 0, 0;~ldv_2_ret_default~0 := 0;~ldv_statevar_0~0 := 0;~ldv_statevar_1~0 := 0;~ldv_statevar_11~0 := 0;~ldv_statevar_2~0 := 0;~ldv_0_callback_handler~0.base, ~ldv_0_callback_handler~0.offset := #funAddr~hp100_interrupt.base, #funAddr~hp100_interrupt.offset;~ldv_11_exit_hp100_module_exit_default~0.base, ~ldv_11_exit_hp100_module_exit_default~0.offset := #funAddr~hp100_module_exit.base, #funAddr~hp100_module_exit.offset;~ldv_11_init_hp100_module_init_default~0.base, ~ldv_11_init_hp100_module_init_default~0.offset := #funAddr~hp100_module_init.base, #funAddr~hp100_module_init.offset;~ldv_1_callback_ndo_change_mtu~0.base, ~ldv_1_callback_ndo_change_mtu~0.offset := #funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset;~ldv_1_callback_ndo_get_stats~0.base, ~ldv_1_callback_ndo_get_stats~0.offset := #funAddr~hp100_get_stats.base, #funAddr~hp100_get_stats.offset;~ldv_1_callback_ndo_set_mac_address~0.base, ~ldv_1_callback_ndo_set_mac_address~0.offset := #funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset;~ldv_1_callback_ndo_set_rx_mode~0.base, ~ldv_1_callback_ndo_set_rx_mode~0.offset := #funAddr~hp100_set_multicast_list.base, #funAddr~hp100_set_multicast_list.offset;~ldv_1_callback_ndo_start_xmit~0.base, ~ldv_1_callback_ndo_start_xmit~0.offset := #funAddr~hp100_start_xmit_bm.base, #funAddr~hp100_start_xmit_bm.offset;~ldv_1_callback_ndo_validate_addr~0.base, ~ldv_1_callback_ndo_validate_addr~0.offset := #funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_hp100_private~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1; {1808#true} is VALID [2022-02-20 22:37:45,634 INFO L290 TraceCheckUtils]: 1: Hoare triple {1808#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret769#1, main_~tmp~59#1;havoc main_~tmp~59#1;assume { :begin_inline_ldv_initialize } true; {1808#true} is VALID [2022-02-20 22:37:45,634 INFO L290 TraceCheckUtils]: 2: Hoare triple {1808#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_initialize_external_data } true;assume { :begin_inline_ldv_allocate_external_0 } true;havoc ldv_allocate_external_0_#t~ret757#1.base, ldv_allocate_external_0_#t~ret757#1.offset, ldv_allocate_external_0_#t~ret758#1.base, ldv_allocate_external_0_#t~ret758#1.offset, ldv_allocate_external_0_#t~ret759#1.base, ldv_allocate_external_0_#t~ret759#1.offset, ldv_allocate_external_0_#t~ret760#1.base, ldv_allocate_external_0_#t~ret760#1.offset; {1808#true} is VALID [2022-02-20 22:37:45,635 INFO L272 TraceCheckUtils]: 3: Hoare triple {1808#true} call ldv_allocate_external_0_#t~ret757#1.base, ldv_allocate_external_0_#t~ret757#1.offset := ldv_malloc(0); {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:37:45,635 INFO L290 TraceCheckUtils]: 4: Hoare triple {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {1808#true} is VALID [2022-02-20 22:37:45,635 INFO L272 TraceCheckUtils]: 5: Hoare triple {1808#true} call #t~ret868 := ldv_undef_int(); {1808#true} is VALID [2022-02-20 22:37:45,636 INFO L290 TraceCheckUtils]: 6: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,636 INFO L290 TraceCheckUtils]: 7: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,636 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,636 INFO L290 TraceCheckUtils]: 9: Hoare triple {1808#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {1808#true} is VALID [2022-02-20 22:37:45,636 INFO L290 TraceCheckUtils]: 10: Hoare triple {1808#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {1808#true} is VALID [2022-02-20 22:37:45,636 INFO L290 TraceCheckUtils]: 11: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,637 INFO L284 TraceCheckUtils]: 12: Hoare quadruple {1808#true} {1808#true} #4324#return; {1808#true} is VALID [2022-02-20 22:37:45,637 INFO L290 TraceCheckUtils]: 13: Hoare triple {1808#true} ~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset := ldv_allocate_external_0_#t~ret757#1.base, ldv_allocate_external_0_#t~ret757#1.offset;havoc ldv_allocate_external_0_#t~ret757#1.base, ldv_allocate_external_0_#t~ret757#1.offset;~ldv_0_thread_thread~0.base, ~ldv_0_thread_thread~0.offset := 0, 0; {1808#true} is VALID [2022-02-20 22:37:45,637 INFO L272 TraceCheckUtils]: 14: Hoare triple {1808#true} call ldv_allocate_external_0_#t~ret758#1.base, ldv_allocate_external_0_#t~ret758#1.offset := ldv_malloc(3027); {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:37:45,638 INFO L290 TraceCheckUtils]: 15: Hoare triple {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {1808#true} is VALID [2022-02-20 22:37:45,638 INFO L272 TraceCheckUtils]: 16: Hoare triple {1808#true} call #t~ret868 := ldv_undef_int(); {1808#true} is VALID [2022-02-20 22:37:45,638 INFO L290 TraceCheckUtils]: 17: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,638 INFO L290 TraceCheckUtils]: 18: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,638 INFO L284 TraceCheckUtils]: 19: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,638 INFO L290 TraceCheckUtils]: 20: Hoare triple {1808#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {1808#true} is VALID [2022-02-20 22:37:45,639 INFO L290 TraceCheckUtils]: 21: Hoare triple {1808#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {1808#true} is VALID [2022-02-20 22:37:45,639 INFO L290 TraceCheckUtils]: 22: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,639 INFO L284 TraceCheckUtils]: 23: Hoare quadruple {1808#true} {1808#true} #4326#return; {1808#true} is VALID [2022-02-20 22:37:45,639 INFO L290 TraceCheckUtils]: 24: Hoare triple {1808#true} ~ldv_1_container_net_device~0.base, ~ldv_1_container_net_device~0.offset := ldv_allocate_external_0_#t~ret758#1.base, ldv_allocate_external_0_#t~ret758#1.offset;havoc ldv_allocate_external_0_#t~ret758#1.base, ldv_allocate_external_0_#t~ret758#1.offset; {1808#true} is VALID [2022-02-20 22:37:45,640 INFO L272 TraceCheckUtils]: 25: Hoare triple {1808#true} call ldv_allocate_external_0_#t~ret759#1.base, ldv_allocate_external_0_#t~ret759#1.offset := ldv_malloc(245); {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:37:45,640 INFO L290 TraceCheckUtils]: 26: Hoare triple {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {1808#true} is VALID [2022-02-20 22:37:45,640 INFO L272 TraceCheckUtils]: 27: Hoare triple {1808#true} call #t~ret868 := ldv_undef_int(); {1808#true} is VALID [2022-02-20 22:37:45,640 INFO L290 TraceCheckUtils]: 28: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,640 INFO L290 TraceCheckUtils]: 29: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,641 INFO L284 TraceCheckUtils]: 30: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,641 INFO L290 TraceCheckUtils]: 31: Hoare triple {1808#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {1808#true} is VALID [2022-02-20 22:37:45,641 INFO L290 TraceCheckUtils]: 32: Hoare triple {1808#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {1808#true} is VALID [2022-02-20 22:37:45,641 INFO L290 TraceCheckUtils]: 33: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,641 INFO L284 TraceCheckUtils]: 34: Hoare quadruple {1808#true} {1808#true} #4328#return; {1808#true} is VALID [2022-02-20 22:37:45,666 INFO L290 TraceCheckUtils]: 35: Hoare triple {1808#true} ~ldv_1_container_struct_sk_buff_ptr~0.base, ~ldv_1_container_struct_sk_buff_ptr~0.offset := ldv_allocate_external_0_#t~ret759#1.base, ldv_allocate_external_0_#t~ret759#1.offset;havoc ldv_allocate_external_0_#t~ret759#1.base, ldv_allocate_external_0_#t~ret759#1.offset; {1808#true} is VALID [2022-02-20 22:37:45,673 INFO L272 TraceCheckUtils]: 36: Hoare triple {1808#true} call ldv_allocate_external_0_#t~ret760#1.base, ldv_allocate_external_0_#t~ret760#1.offset := ldv_malloc(3018); {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:37:45,673 INFO L290 TraceCheckUtils]: 37: Hoare triple {1880#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {1808#true} is VALID [2022-02-20 22:37:45,673 INFO L272 TraceCheckUtils]: 38: Hoare triple {1808#true} call #t~ret868 := ldv_undef_int(); {1808#true} is VALID [2022-02-20 22:37:45,673 INFO L290 TraceCheckUtils]: 39: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,673 INFO L290 TraceCheckUtils]: 40: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,673 INFO L284 TraceCheckUtils]: 41: Hoare quadruple {1808#true} {1808#true} #3758#return; {1808#true} is VALID [2022-02-20 22:37:45,673 INFO L290 TraceCheckUtils]: 42: Hoare triple {1808#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {1808#true} is VALID [2022-02-20 22:37:45,674 INFO L290 TraceCheckUtils]: 43: Hoare triple {1808#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {1808#true} is VALID [2022-02-20 22:37:45,674 INFO L290 TraceCheckUtils]: 44: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,674 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {1808#true} {1808#true} #4330#return; {1808#true} is VALID [2022-02-20 22:37:45,674 INFO L290 TraceCheckUtils]: 46: Hoare triple {1808#true} ~ldv_2_resource_dev~0.base, ~ldv_2_resource_dev~0.offset := ldv_allocate_external_0_#t~ret760#1.base, ldv_allocate_external_0_#t~ret760#1.offset;havoc ldv_allocate_external_0_#t~ret760#1.base, ldv_allocate_external_0_#t~ret760#1.offset; {1808#true} is VALID [2022-02-20 22:37:45,674 INFO L290 TraceCheckUtils]: 47: Hoare triple {1808#true} assume { :end_inline_ldv_allocate_external_0 } true; {1808#true} is VALID [2022-02-20 22:37:45,675 INFO L290 TraceCheckUtils]: 48: Hoare triple {1808#true} assume { :end_inline_ldv_initialize_external_data } true;~ldv_statevar_11~0 := 7;~ldv_statevar_0~0 := 6;~ldv_statevar_1~0 := 5;~ldv_2_ret_default~0 := 1;~ldv_statevar_2~0 := 20; {1846#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:37:45,675 INFO L272 TraceCheckUtils]: 49: Hoare triple {1846#(= 6 ~ldv_statevar_0~0)} call main_#t~ret769#1 := ldv_undef_int(); {1808#true} is VALID [2022-02-20 22:37:45,675 INFO L290 TraceCheckUtils]: 50: Hoare triple {1808#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {1808#true} is VALID [2022-02-20 22:37:45,675 INFO L290 TraceCheckUtils]: 51: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,676 INFO L284 TraceCheckUtils]: 52: Hoare quadruple {1808#true} {1846#(= 6 ~ldv_statevar_0~0)} #4332#return; {1846#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:37:45,676 INFO L290 TraceCheckUtils]: 53: Hoare triple {1846#(= 6 ~ldv_statevar_0~0)} assume -2147483648 <= main_#t~ret769#1 && main_#t~ret769#1 <= 2147483647;main_~tmp~59#1 := main_#t~ret769#1;havoc main_#t~ret769#1; {1846#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:37:45,677 INFO L290 TraceCheckUtils]: 54: Hoare triple {1846#(= 6 ~ldv_statevar_0~0)} assume !(0 == main_~tmp~59#1); {1846#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:37:45,677 INFO L290 TraceCheckUtils]: 55: Hoare triple {1846#(= 6 ~ldv_statevar_0~0)} assume 1 == main_~tmp~59#1; {1846#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:37:45,677 INFO L290 TraceCheckUtils]: 56: Hoare triple {1846#(= 6 ~ldv_statevar_0~0)} assume { :begin_inline_ldv_interrupt_interrupt_instance_0 } true;ldv_interrupt_interrupt_instance_0_#in~arg0#1.base, ldv_interrupt_interrupt_instance_0_#in~arg0#1.offset := 0, 0;havoc ldv_interrupt_interrupt_instance_0_#t~ret774#1, ldv_interrupt_interrupt_instance_0_#t~ret775#1, ldv_interrupt_interrupt_instance_0_~arg0#1.base, ldv_interrupt_interrupt_instance_0_~arg0#1.offset, ldv_interrupt_interrupt_instance_0_~tmp~61#1;ldv_interrupt_interrupt_instance_0_~arg0#1.base, ldv_interrupt_interrupt_instance_0_~arg0#1.offset := ldv_interrupt_interrupt_instance_0_#in~arg0#1.base, ldv_interrupt_interrupt_instance_0_#in~arg0#1.offset;havoc ldv_interrupt_interrupt_instance_0_~tmp~61#1; {1846#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:37:45,678 INFO L290 TraceCheckUtils]: 57: Hoare triple {1846#(= 6 ~ldv_statevar_0~0)} assume !(2 == ~ldv_statevar_0~0); {1846#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:37:45,678 INFO L290 TraceCheckUtils]: 58: Hoare triple {1846#(= 6 ~ldv_statevar_0~0)} assume !(4 == ~ldv_statevar_0~0); {1846#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:37:45,679 INFO L290 TraceCheckUtils]: 59: Hoare triple {1846#(= 6 ~ldv_statevar_0~0)} assume 5 == ~ldv_statevar_0~0; {1809#false} is VALID [2022-02-20 22:37:45,679 INFO L290 TraceCheckUtils]: 60: Hoare triple {1809#false} assume { :begin_inline_ldv_switch_to_interrupt_context } true; {1809#false} is VALID [2022-02-20 22:37:45,679 INFO L290 TraceCheckUtils]: 61: Hoare triple {1809#false} assume { :end_inline_ldv_switch_to_interrupt_context } true;assume { :begin_inline_ldv_interrupt_instance_handler_0_5 } true;ldv_interrupt_instance_handler_0_5_#in~arg0#1.base, ldv_interrupt_instance_handler_0_5_#in~arg0#1.offset, ldv_interrupt_instance_handler_0_5_#in~arg1#1, ldv_interrupt_instance_handler_0_5_#in~arg2#1.base, ldv_interrupt_instance_handler_0_5_#in~arg2#1.offset := ~ldv_0_callback_handler~0.base, ~ldv_0_callback_handler~0.offset, ~ldv_0_line_line~0, ~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset;havoc ldv_interrupt_instance_handler_0_5_#res#1;havoc ldv_interrupt_instance_handler_0_5_#t~ret770#1, ldv_interrupt_instance_handler_0_5_~arg0#1.base, ldv_interrupt_instance_handler_0_5_~arg0#1.offset, ldv_interrupt_instance_handler_0_5_~arg1#1, ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset, ldv_interrupt_instance_handler_0_5_~tmp~60#1;ldv_interrupt_instance_handler_0_5_~arg0#1.base, ldv_interrupt_instance_handler_0_5_~arg0#1.offset := ldv_interrupt_instance_handler_0_5_#in~arg0#1.base, ldv_interrupt_instance_handler_0_5_#in~arg0#1.offset;ldv_interrupt_instance_handler_0_5_~arg1#1 := ldv_interrupt_instance_handler_0_5_#in~arg1#1;ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset := ldv_interrupt_instance_handler_0_5_#in~arg2#1.base, ldv_interrupt_instance_handler_0_5_#in~arg2#1.offset;havoc ldv_interrupt_instance_handler_0_5_~tmp~60#1;assume { :begin_inline_hp100_interrupt } true;hp100_interrupt_#in~irq#1, hp100_interrupt_#in~dev_id#1.base, hp100_interrupt_#in~dev_id#1.offset := ldv_interrupt_instance_handler_0_5_~arg1#1, ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset;havoc hp100_interrupt_#res#1;havoc hp100_interrupt_#t~ret613#1.base, hp100_interrupt_#t~ret613#1.offset, hp100_interrupt_#t~mem614#1, hp100_interrupt_#t~ret615#1, hp100_interrupt_#t~mem616#1, hp100_interrupt_#t~nondet617#1, hp100_interrupt_#t~mem618#1, hp100_interrupt_#t~mem619#1, hp100_interrupt_#t~mem620#1, hp100_interrupt_#t~mem621#1, hp100_interrupt_#t~mem622#1, hp100_interrupt_~irq#1, hp100_interrupt_~dev_id#1.base, hp100_interrupt_~dev_id#1.offset, hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset, hp100_interrupt_~lp~17#1.base, hp100_interrupt_~lp~17#1.offset, hp100_interrupt_~tmp~44#1.base, hp100_interrupt_~tmp~44#1.offset, hp100_interrupt_~ioaddr~13#1, hp100_interrupt_~val~2#1, hp100_interrupt_~tmp___0~22#1;hp100_interrupt_~irq#1 := hp100_interrupt_#in~irq#1;hp100_interrupt_~dev_id#1.base, hp100_interrupt_~dev_id#1.offset := hp100_interrupt_#in~dev_id#1.base, hp100_interrupt_#in~dev_id#1.offset;havoc hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset;havoc hp100_interrupt_~lp~17#1.base, hp100_interrupt_~lp~17#1.offset;havoc hp100_interrupt_~tmp~44#1.base, hp100_interrupt_~tmp~44#1.offset;havoc hp100_interrupt_~ioaddr~13#1;havoc hp100_interrupt_~val~2#1;havoc hp100_interrupt_~tmp___0~22#1;hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset := hp100_interrupt_~dev_id#1.base, hp100_interrupt_~dev_id#1.offset; {1809#false} is VALID [2022-02-20 22:37:45,679 INFO L272 TraceCheckUtils]: 62: Hoare triple {1809#false} call hp100_interrupt_#t~ret613#1.base, hp100_interrupt_#t~ret613#1.offset := netdev_priv(hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset); {1808#true} is VALID [2022-02-20 22:37:45,680 INFO L290 TraceCheckUtils]: 63: Hoare triple {1808#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1808#true} is VALID [2022-02-20 22:37:45,680 INFO L290 TraceCheckUtils]: 64: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,680 INFO L284 TraceCheckUtils]: 65: Hoare quadruple {1808#true} {1809#false} #4368#return; {1809#false} is VALID [2022-02-20 22:37:45,680 INFO L290 TraceCheckUtils]: 66: Hoare triple {1809#false} hp100_interrupt_~tmp~44#1.base, hp100_interrupt_~tmp~44#1.offset := hp100_interrupt_#t~ret613#1.base, hp100_interrupt_#t~ret613#1.offset;havoc hp100_interrupt_#t~ret613#1.base, hp100_interrupt_#t~ret613#1.offset;hp100_interrupt_~lp~17#1.base, hp100_interrupt_~lp~17#1.offset := hp100_interrupt_~tmp~44#1.base, hp100_interrupt_~tmp~44#1.offset; {1809#false} is VALID [2022-02-20 22:37:45,680 INFO L290 TraceCheckUtils]: 67: Hoare triple {1809#false} assume !(0 == (hp100_interrupt_~dev~0#1.base + hp100_interrupt_~dev~0#1.offset) % 18446744073709551616);call hp100_interrupt_#t~mem614#1 := read~int(hp100_interrupt_~dev~0#1.base, 56 + hp100_interrupt_~dev~0#1.offset, 8);hp100_interrupt_~ioaddr~13#1 := (if hp100_interrupt_#t~mem614#1 % 18446744073709551616 % 4294967296 <= 2147483647 then hp100_interrupt_#t~mem614#1 % 18446744073709551616 % 4294967296 else hp100_interrupt_#t~mem614#1 % 18446744073709551616 % 4294967296 - 4294967296);havoc hp100_interrupt_#t~mem614#1;assume { :begin_inline_ldv_spin_lock_102 } true;ldv_spin_lock_102_#in~lock#1.base, ldv_spin_lock_102_#in~lock#1.offset := hp100_interrupt_~lp~17#1.base, hp100_interrupt_~lp~17#1.offset;havoc ldv_spin_lock_102_~lock#1.base, ldv_spin_lock_102_~lock#1.offset;ldv_spin_lock_102_~lock#1.base, ldv_spin_lock_102_~lock#1.offset := ldv_spin_lock_102_#in~lock#1.base, ldv_spin_lock_102_#in~lock#1.offset; {1809#false} is VALID [2022-02-20 22:37:45,680 INFO L272 TraceCheckUtils]: 68: Hoare triple {1809#false} call ldv_spin_lock_lock_of_hp100_private(); {1893#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} is VALID [2022-02-20 22:37:45,681 INFO L272 TraceCheckUtils]: 69: Hoare triple {1893#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} call ldv_assert(87, 0, (if 1 == ~ldv_spin_lock_of_hp100_private~0 then 1 else 0)); {1808#true} is VALID [2022-02-20 22:37:45,681 INFO L290 TraceCheckUtils]: 70: Hoare triple {1808#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {1808#true} is VALID [2022-02-20 22:37:45,681 INFO L290 TraceCheckUtils]: 71: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,681 INFO L284 TraceCheckUtils]: 72: Hoare quadruple {1808#true} {1893#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} #4016#return; {1808#true} is VALID [2022-02-20 22:37:45,681 INFO L272 TraceCheckUtils]: 73: Hoare triple {1808#true} call ldv_assume((if 1 == ~ldv_spin_lock_of_hp100_private~0 then 1 else 0)); {1808#true} is VALID [2022-02-20 22:37:45,681 INFO L290 TraceCheckUtils]: 74: Hoare triple {1808#true} ~expression := #in~expression; {1808#true} is VALID [2022-02-20 22:37:45,682 INFO L290 TraceCheckUtils]: 75: Hoare triple {1808#true} assume !(0 == ~expression); {1808#true} is VALID [2022-02-20 22:37:45,682 INFO L290 TraceCheckUtils]: 76: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,682 INFO L284 TraceCheckUtils]: 77: Hoare quadruple {1808#true} {1808#true} #4018#return; {1808#true} is VALID [2022-02-20 22:37:45,682 INFO L290 TraceCheckUtils]: 78: Hoare triple {1808#true} ~ldv_spin_lock_of_hp100_private~0 := 2; {1808#true} is VALID [2022-02-20 22:37:45,682 INFO L290 TraceCheckUtils]: 79: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,682 INFO L284 TraceCheckUtils]: 80: Hoare quadruple {1808#true} {1809#false} #4370#return; {1809#false} is VALID [2022-02-20 22:37:45,682 INFO L290 TraceCheckUtils]: 81: Hoare triple {1809#false} assume { :begin_inline_spin_lock } true;spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset := ldv_spin_lock_102_~lock#1.base, ldv_spin_lock_102_~lock#1.offset;havoc spin_lock_~lock#1.base, spin_lock_~lock#1.offset;spin_lock_~lock#1.base, spin_lock_~lock#1.offset := spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset;assume { :begin_inline__raw_spin_lock } true;_raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset := spin_lock_~lock#1.base, spin_lock_~lock#1.offset;havoc _raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset;_raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset := _raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset; {1809#false} is VALID [2022-02-20 22:37:45,683 INFO L290 TraceCheckUtils]: 82: Hoare triple {1809#false} assume { :end_inline__raw_spin_lock } true; {1809#false} is VALID [2022-02-20 22:37:45,683 INFO L290 TraceCheckUtils]: 83: Hoare triple {1809#false} assume { :end_inline_spin_lock } true; {1809#false} is VALID [2022-02-20 22:37:45,683 INFO L290 TraceCheckUtils]: 84: Hoare triple {1809#false} assume { :end_inline_ldv_spin_lock_102 } true; {1809#false} is VALID [2022-02-20 22:37:45,683 INFO L272 TraceCheckUtils]: 85: Hoare triple {1809#false} call outw(4, 4 + hp100_interrupt_~ioaddr~13#1); {1808#true} is VALID [2022-02-20 22:37:45,683 INFO L290 TraceCheckUtils]: 86: Hoare triple {1808#true} ~value := #in~value;~port := #in~port; {1808#true} is VALID [2022-02-20 22:37:45,683 INFO L290 TraceCheckUtils]: 87: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,684 INFO L284 TraceCheckUtils]: 88: Hoare quadruple {1808#true} {1809#false} #4372#return; {1809#false} is VALID [2022-02-20 22:37:45,684 INFO L272 TraceCheckUtils]: 89: Hoare triple {1809#false} call hp100_interrupt_#t~ret615#1 := inw(8 + hp100_interrupt_~ioaddr~13#1); {1808#true} is VALID [2022-02-20 22:37:45,684 INFO L290 TraceCheckUtils]: 90: Hoare triple {1808#true} ~port := #in~port;havoc ~value~1;#res := ~value~1; {1808#true} is VALID [2022-02-20 22:37:45,684 INFO L290 TraceCheckUtils]: 91: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,684 INFO L284 TraceCheckUtils]: 92: Hoare quadruple {1808#true} {1809#false} #4374#return; {1809#false} is VALID [2022-02-20 22:37:45,684 INFO L290 TraceCheckUtils]: 93: Hoare triple {1809#false} hp100_interrupt_~tmp___0~22#1 := hp100_interrupt_#t~ret615#1;havoc hp100_interrupt_#t~ret615#1;hp100_interrupt_~val~2#1 := hp100_interrupt_~tmp___0~22#1 % 65536; {1809#false} is VALID [2022-02-20 22:37:45,685 INFO L290 TraceCheckUtils]: 94: Hoare triple {1809#false} assume !(0 == hp100_interrupt_~val~2#1 % 4294967296); {1809#false} is VALID [2022-02-20 22:37:45,685 INFO L290 TraceCheckUtils]: 95: Hoare triple {1809#false} assume !(0 != (if 0 == hp100_interrupt_~val~2#1 then 0 else (if 1 == hp100_interrupt_~val~2#1 then 0 else ~bitwiseAnd(hp100_interrupt_~val~2#1, 2048))) % 4294967296); {1809#false} is VALID [2022-02-20 22:37:45,685 INFO L290 TraceCheckUtils]: 96: Hoare triple {1809#false} assume 0 != (if 0 == hp100_interrupt_~val~2#1 then 0 else (if 1 == hp100_interrupt_~val~2#1 then 0 else ~bitwiseAnd(hp100_interrupt_~val~2#1, 1024))) % 4294967296;call hp100_interrupt_#t~mem618#1 := read~int(hp100_interrupt_~lp~17#1.base, 92 + hp100_interrupt_~lp~17#1.offset, 2); {1809#false} is VALID [2022-02-20 22:37:45,685 INFO L290 TraceCheckUtils]: 97: Hoare triple {1809#false} assume 1 != hp100_interrupt_#t~mem618#1 % 65536 % 4294967296;havoc hp100_interrupt_#t~mem618#1;assume { :begin_inline_hp100_rx } true;hp100_rx_#in~dev#1.base, hp100_rx_#in~dev#1.offset := hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset;havoc hp100_rx_#t~mem514#1, hp100_rx_#t~ret515#1.base, hp100_rx_#t~ret515#1.offset, hp100_rx_#t~ret516#1, hp100_rx_#t~ret517#1, hp100_rx_#t~mem518#1, hp100_rx_#t~mem519#1.base, hp100_rx_#t~mem519#1.offset, hp100_rx_#t~ret520#1, hp100_rx_#t~ret521#1, hp100_rx_#t~ret523#1.base, hp100_rx_#t~ret523#1.offset, hp100_rx_#t~nondet522#1, hp100_rx_#t~mem524#1, hp100_rx_#t~ret525#1.base, hp100_rx_#t~ret525#1.offset, hp100_rx_#t~mem526#1.base, hp100_rx_#t~mem526#1.offset, hp100_rx_#t~mem527#1, hp100_rx_#t~mem528#1.base, hp100_rx_#t~mem528#1.offset, hp100_rx_#t~ret529#1, hp100_rx_#t~ret530#1, hp100_rx_#t~mem531#1, hp100_rx_#t~mem532#1, hp100_rx_#t~mem533#1, hp100_rx_~dev#1.base, hp100_rx_~dev#1.offset, hp100_rx_~packets~0#1, hp100_rx_~pkt_len~0#1, hp100_rx_~ioaddr~8#1, hp100_rx_~lp~13#1.base, hp100_rx_~lp~13#1.offset, hp100_rx_~tmp~39#1.base, hp100_rx_~tmp~39#1.offset, hp100_rx_~header~0#1, hp100_rx_~skb~0#1.base, hp100_rx_~skb~0#1.offset, hp100_rx_~tmp___0~18#1, hp100_rx_~tmp___1~12#1, hp100_rx_~ptr~0#1.base, hp100_rx_~ptr~0#1.offset, hp100_rx_~tmp___2~7#1;hp100_rx_~dev#1.base, hp100_rx_~dev#1.offset := hp100_rx_#in~dev#1.base, hp100_rx_#in~dev#1.offset;havoc hp100_rx_~packets~0#1;havoc hp100_rx_~pkt_len~0#1;havoc hp100_rx_~ioaddr~8#1;havoc hp100_rx_~lp~13#1.base, hp100_rx_~lp~13#1.offset;havoc hp100_rx_~tmp~39#1.base, hp100_rx_~tmp~39#1.offset;havoc hp100_rx_~header~0#1;havoc hp100_rx_~skb~0#1.base, hp100_rx_~skb~0#1.offset;havoc hp100_rx_~tmp___0~18#1;havoc hp100_rx_~tmp___1~12#1;havoc hp100_rx_~ptr~0#1.base, hp100_rx_~ptr~0#1.offset;havoc hp100_rx_~tmp___2~7#1;call hp100_rx_#t~mem514#1 := read~int(hp100_rx_~dev#1.base, 56 + hp100_rx_~dev#1.offset, 8);hp100_rx_~ioaddr~8#1 := (if hp100_rx_#t~mem514#1 % 18446744073709551616 % 4294967296 <= 2147483647 then hp100_rx_#t~mem514#1 % 18446744073709551616 % 4294967296 else hp100_rx_#t~mem514#1 % 18446744073709551616 % 4294967296 - 4294967296);havoc hp100_rx_#t~mem514#1; {1809#false} is VALID [2022-02-20 22:37:45,685 INFO L272 TraceCheckUtils]: 98: Hoare triple {1809#false} call hp100_rx_#t~ret515#1.base, hp100_rx_#t~ret515#1.offset := netdev_priv(hp100_rx_~dev#1.base, hp100_rx_~dev#1.offset); {1808#true} is VALID [2022-02-20 22:37:45,685 INFO L290 TraceCheckUtils]: 99: Hoare triple {1808#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1808#true} is VALID [2022-02-20 22:37:45,686 INFO L290 TraceCheckUtils]: 100: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,686 INFO L284 TraceCheckUtils]: 101: Hoare quadruple {1808#true} {1809#false} #4382#return; {1809#false} is VALID [2022-02-20 22:37:45,686 INFO L290 TraceCheckUtils]: 102: Hoare triple {1809#false} hp100_rx_~tmp~39#1.base, hp100_rx_~tmp~39#1.offset := hp100_rx_#t~ret515#1.base, hp100_rx_#t~ret515#1.offset;havoc hp100_rx_#t~ret515#1.base, hp100_rx_#t~ret515#1.offset;hp100_rx_~lp~13#1.base, hp100_rx_~lp~13#1.offset := hp100_rx_~tmp~39#1.base, hp100_rx_~tmp~39#1.offset; {1809#false} is VALID [2022-02-20 22:37:45,686 INFO L272 TraceCheckUtils]: 103: Hoare triple {1809#false} call hp100_rx_#t~ret516#1 := inb(24 + hp100_rx_~ioaddr~8#1); {1808#true} is VALID [2022-02-20 22:37:45,686 INFO L290 TraceCheckUtils]: 104: Hoare triple {1808#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1808#true} is VALID [2022-02-20 22:37:45,686 INFO L290 TraceCheckUtils]: 105: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,687 INFO L284 TraceCheckUtils]: 106: Hoare quadruple {1808#true} {1809#false} #4384#return; {1809#false} is VALID [2022-02-20 22:37:45,687 INFO L290 TraceCheckUtils]: 107: Hoare triple {1809#false} hp100_rx_~tmp___0~18#1 := hp100_rx_#t~ret516#1;havoc hp100_rx_#t~ret516#1;hp100_rx_~packets~0#1 := hp100_rx_~tmp___0~18#1 % 256; {1809#false} is VALID [2022-02-20 22:37:45,687 INFO L290 TraceCheckUtils]: 108: Hoare triple {1809#false} hp100_rx_~tmp___2~7#1 := hp100_rx_~packets~0#1;hp100_rx_~packets~0#1 := hp100_rx_~packets~0#1 - 1; {1809#false} is VALID [2022-02-20 22:37:45,687 INFO L290 TraceCheckUtils]: 109: Hoare triple {1809#false} assume hp100_rx_~tmp___2~7#1 > 0; {1809#false} is VALID [2022-02-20 22:37:45,687 INFO L290 TraceCheckUtils]: 110: Hoare triple {1809#false} hp100_rx_~pkt_len~0#1 := 0; {1809#false} is VALID [2022-02-20 22:37:45,687 INFO L290 TraceCheckUtils]: 111: Hoare triple {1809#false} assume !(hp100_rx_~pkt_len~0#1 <= 5999); {1809#false} is VALID [2022-02-20 22:37:45,688 INFO L290 TraceCheckUtils]: 112: Hoare triple {1809#false} call hp100_rx_#t~mem518#1 := read~int(hp100_rx_~lp~13#1.base, 92 + hp100_rx_~lp~13#1.offset, 2); {1809#false} is VALID [2022-02-20 22:37:45,688 INFO L290 TraceCheckUtils]: 113: Hoare triple {1809#false} assume 2 == hp100_rx_#t~mem518#1 % 65536 % 4294967296;havoc hp100_rx_#t~mem518#1;call hp100_rx_#t~mem519#1.base, hp100_rx_#t~mem519#1.offset := read~$Pointer$(hp100_rx_~lp~13#1.base, 105 + hp100_rx_~lp~13#1.offset, 8);assume { :begin_inline_readl } true;readl_#in~addr#1.base, readl_#in~addr#1.offset := hp100_rx_#t~mem519#1.base, hp100_rx_#t~mem519#1.offset;havoc readl_#res#1;havoc readl_~addr#1.base, readl_~addr#1.offset, readl_~ret~0#1;readl_~addr#1.base, readl_~addr#1.offset := readl_#in~addr#1.base, readl_#in~addr#1.offset;havoc readl_~ret~0#1;readl_#res#1 := readl_~ret~0#1; {1809#false} is VALID [2022-02-20 22:37:45,688 INFO L290 TraceCheckUtils]: 114: Hoare triple {1809#false} hp100_rx_#t~ret520#1 := readl_#res#1;assume { :end_inline_readl } true;hp100_rx_~header~0#1 := hp100_rx_#t~ret520#1;havoc hp100_rx_#t~mem519#1.base, hp100_rx_#t~mem519#1.offset;havoc hp100_rx_#t~ret520#1; {1809#false} is VALID [2022-02-20 22:37:45,688 INFO L290 TraceCheckUtils]: 115: Hoare triple {1809#false} assume 0 == (if (3 + (if 0 == hp100_rx_~header~0#1 then 0 else (if 1 == hp100_rx_~header~0#1 then 1 else ~bitwiseAnd(hp100_rx_~header~0#1, 8191)))) % 4294967296 % 4294967296 <= 2147483647 then (3 + (if 0 == hp100_rx_~header~0#1 then 0 else (if 1 == hp100_rx_~header~0#1 then 1 else ~bitwiseAnd(hp100_rx_~header~0#1, 8191)))) % 4294967296 % 4294967296 else (3 + (if 0 == hp100_rx_~header~0#1 then 0 else (if 1 == hp100_rx_~header~0#1 then 1 else ~bitwiseAnd(hp100_rx_~header~0#1, 8191)))) % 4294967296 % 4294967296 - 4294967296);hp100_rx_~pkt_len~0#1 := 0; {1809#false} is VALID [2022-02-20 22:37:45,688 INFO L272 TraceCheckUtils]: 116: Hoare triple {1809#false} call hp100_rx_#t~ret523#1.base, hp100_rx_#t~ret523#1.offset := netdev_alloc_skb(hp100_rx_~dev#1.base, hp100_rx_~dev#1.offset, 2 + hp100_rx_~pkt_len~0#1); {1809#false} is VALID [2022-02-20 22:37:45,688 INFO L290 TraceCheckUtils]: 117: Hoare triple {1809#false} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;~length#1 := #in~length#1;havoc ~tmp~8#1.base, ~tmp~8#1.offset;assume { :begin_inline_ldv___netdev_alloc_skb_57 } true;ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_57_#in~ldv_func_arg2#1, ldv___netdev_alloc_skb_57_#in~flags#1 := ~dev#1.base, ~dev#1.offset, ~length#1, 32;havoc ldv___netdev_alloc_skb_57_#res#1.base, ldv___netdev_alloc_skb_57_#res#1.offset;havoc ldv___netdev_alloc_skb_57_#t~ret835#1.base, ldv___netdev_alloc_skb_57_#t~ret835#1.offset, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_57_~ldv_func_arg2#1, ldv___netdev_alloc_skb_57_~flags#1, ldv___netdev_alloc_skb_57_~tmp~72#1.base, ldv___netdev_alloc_skb_57_~tmp~72#1.offset;ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.offset := ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.offset;ldv___netdev_alloc_skb_57_~ldv_func_arg2#1 := ldv___netdev_alloc_skb_57_#in~ldv_func_arg2#1;ldv___netdev_alloc_skb_57_~flags#1 := ldv___netdev_alloc_skb_57_#in~flags#1;havoc ldv___netdev_alloc_skb_57_~tmp~72#1.base, ldv___netdev_alloc_skb_57_~tmp~72#1.offset; {1809#false} is VALID [2022-02-20 22:37:45,689 INFO L272 TraceCheckUtils]: 118: Hoare triple {1809#false} call ldv_check_alloc_flags(ldv___netdev_alloc_skb_57_~flags#1); {1809#false} is VALID [2022-02-20 22:37:45,689 INFO L290 TraceCheckUtils]: 119: Hoare triple {1809#false} ~flags#1 := #in~flags#1;havoc ~tmp~79#1; {1809#false} is VALID [2022-02-20 22:37:45,689 INFO L290 TraceCheckUtils]: 120: Hoare triple {1809#false} assume 32 != ~flags#1 % 4294967296 && 0 != ~flags#1 % 4294967296; {1809#false} is VALID [2022-02-20 22:37:45,689 INFO L272 TraceCheckUtils]: 121: Hoare triple {1809#false} call #t~ret846#1 := ldv_exclusive_spin_is_locked(); {1808#true} is VALID [2022-02-20 22:37:45,689 INFO L290 TraceCheckUtils]: 122: Hoare triple {1808#true} assume 2 == ~ldv_spin__xmit_lock_of_netdev_queue~0;#res := 1; {1808#true} is VALID [2022-02-20 22:37:45,689 INFO L290 TraceCheckUtils]: 123: Hoare triple {1808#true} assume true; {1808#true} is VALID [2022-02-20 22:37:45,689 INFO L284 TraceCheckUtils]: 124: Hoare quadruple {1808#true} {1809#false} #3826#return; {1809#false} is VALID [2022-02-20 22:37:45,690 INFO L290 TraceCheckUtils]: 125: Hoare triple {1809#false} assume -2147483648 <= #t~ret846#1 && #t~ret846#1 <= 2147483647;~tmp~79#1 := #t~ret846#1;havoc #t~ret846#1;assume { :begin_inline_ldv_assert_linux_alloc_spinlock__wrong_flags } true;ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1 := (if 0 == ~tmp~79#1 then 1 else 0);havoc ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1;ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1 := ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1; {1809#false} is VALID [2022-02-20 22:37:45,690 INFO L290 TraceCheckUtils]: 126: Hoare triple {1809#false} assume 0 == ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1; {1809#false} is VALID [2022-02-20 22:37:45,690 INFO L290 TraceCheckUtils]: 127: Hoare triple {1809#false} assume !false; {1809#false} is VALID [2022-02-20 22:37:45,691 INFO L134 CoverageAnalysis]: Checked inductivity of 69 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 69 trivial. 0 not checked. [2022-02-20 22:37:45,691 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:37:45,691 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654110766] [2022-02-20 22:37:45,692 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654110766] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:37:45,692 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:37:45,692 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-20 22:37:45,693 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301127718] [2022-02-20 22:37:45,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:37:45,697 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 4 states have call successors, (17), 4 states have call predecessors, (17), 1 states have return successors, (15), 3 states have call predecessors, (15), 4 states have call successors, (15) Word has length 128 [2022-02-20 22:37:45,699 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:37:45,701 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 4 states have call successors, (17), 4 states have call predecessors, (17), 1 states have return successors, (15), 3 states have call predecessors, (15), 4 states have call successors, (15) [2022-02-20 22:37:45,801 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 100 edges. 100 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:37:45,801 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-02-20 22:37:45,801 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:37:45,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-20 22:37:45,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-20 22:37:45,822 INFO L87 Difference]: Start difference. First operand has 1805 states, 1157 states have (on average 1.3267070008643043) internal successors, (1535), 1205 states have internal predecessors, (1535), 569 states have call successors, (569), 80 states have call predecessors, (569), 79 states have return successors, (564), 548 states have call predecessors, (564), 564 states have call successors, (564) Second operand has 5 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 4 states have call successors, (17), 4 states have call predecessors, (17), 1 states have return successors, (15), 3 states have call predecessors, (15), 4 states have call successors, (15) [2022-02-20 22:38:14,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:38:14,957 INFO L93 Difference]: Finished difference Result 5270 states and 7957 transitions. [2022-02-20 22:38:14,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-02-20 22:38:14,958 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 4 states have call successors, (17), 4 states have call predecessors, (17), 1 states have return successors, (15), 3 states have call predecessors, (15), 4 states have call successors, (15) Word has length 128 [2022-02-20 22:38:14,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:38:14,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 4 states have call successors, (17), 4 states have call predecessors, (17), 1 states have return successors, (15), 3 states have call predecessors, (15), 4 states have call successors, (15) [2022-02-20 22:38:15,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 7957 transitions. [2022-02-20 22:38:15,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 4 states have call successors, (17), 4 states have call predecessors, (17), 1 states have return successors, (15), 3 states have call predecessors, (15), 4 states have call successors, (15) [2022-02-20 22:38:15,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 7957 transitions. [2022-02-20 22:38:15,800 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 9 states and 7957 transitions. [2022-02-20 22:38:22,314 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 7957 edges. 7957 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:38:22,946 INFO L225 Difference]: With dead ends: 5270 [2022-02-20 22:38:22,947 INFO L226 Difference]: Without dead ends: 3410 [2022-02-20 22:38:22,963 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2022-02-20 22:38:22,967 INFO L933 BasicCegarLoop]: 2820 mSDtfsCounter, 4053 mSDsluCounter, 2511 mSDsCounter, 0 mSdLazyCounter, 3330 mSolverCounterSat, 3966 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 8.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4264 SdHoareTripleChecker+Valid, 5331 SdHoareTripleChecker+Invalid, 7296 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 3966 IncrementalHoareTripleChecker+Valid, 3330 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 8.1s IncrementalHoareTripleChecker+Time [2022-02-20 22:38:22,968 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [4264 Valid, 5331 Invalid, 7296 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [3966 Valid, 3330 Invalid, 0 Unknown, 0 Unchecked, 8.1s Time] [2022-02-20 22:38:22,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3410 states. [2022-02-20 22:38:23,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3410 to 3285. [2022-02-20 22:38:23,165 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:38:23,178 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3410 states. Second operand has 3285 states, 2105 states have (on average 1.2897862232779098) internal successors, (2715), 2195 states have internal predecessors, (2715), 1030 states have call successors, (1030), 148 states have call predecessors, (1030), 149 states have return successors, (1042), 995 states have call predecessors, (1042), 1030 states have call successors, (1042) [2022-02-20 22:38:23,188 INFO L74 IsIncluded]: Start isIncluded. First operand 3410 states. Second operand has 3285 states, 2105 states have (on average 1.2897862232779098) internal successors, (2715), 2195 states have internal predecessors, (2715), 1030 states have call successors, (1030), 148 states have call predecessors, (1030), 149 states have return successors, (1042), 995 states have call predecessors, (1042), 1030 states have call successors, (1042) [2022-02-20 22:38:23,198 INFO L87 Difference]: Start difference. First operand 3410 states. Second operand has 3285 states, 2105 states have (on average 1.2897862232779098) internal successors, (2715), 2195 states have internal predecessors, (2715), 1030 states have call successors, (1030), 148 states have call predecessors, (1030), 149 states have return successors, (1042), 995 states have call predecessors, (1042), 1030 states have call successors, (1042) [2022-02-20 22:38:23,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:38:23,612 INFO L93 Difference]: Finished difference Result 3410 states and 4986 transitions. [2022-02-20 22:38:23,612 INFO L276 IsEmpty]: Start isEmpty. Operand 3410 states and 4986 transitions. [2022-02-20 22:38:23,632 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:38:23,632 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:38:23,642 INFO L74 IsIncluded]: Start isIncluded. First operand has 3285 states, 2105 states have (on average 1.2897862232779098) internal successors, (2715), 2195 states have internal predecessors, (2715), 1030 states have call successors, (1030), 148 states have call predecessors, (1030), 149 states have return successors, (1042), 995 states have call predecessors, (1042), 1030 states have call successors, (1042) Second operand 3410 states. [2022-02-20 22:38:23,652 INFO L87 Difference]: Start difference. First operand has 3285 states, 2105 states have (on average 1.2897862232779098) internal successors, (2715), 2195 states have internal predecessors, (2715), 1030 states have call successors, (1030), 148 states have call predecessors, (1030), 149 states have return successors, (1042), 995 states have call predecessors, (1042), 1030 states have call successors, (1042) Second operand 3410 states. [2022-02-20 22:38:24,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:38:24,053 INFO L93 Difference]: Finished difference Result 3410 states and 4986 transitions. [2022-02-20 22:38:24,053 INFO L276 IsEmpty]: Start isEmpty. Operand 3410 states and 4986 transitions. [2022-02-20 22:38:24,071 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:38:24,071 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:38:24,071 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:38:24,071 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:38:24,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3285 states, 2105 states have (on average 1.2897862232779098) internal successors, (2715), 2195 states have internal predecessors, (2715), 1030 states have call successors, (1030), 148 states have call predecessors, (1030), 149 states have return successors, (1042), 995 states have call predecessors, (1042), 1030 states have call successors, (1042) [2022-02-20 22:38:24,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3285 states to 3285 states and 4787 transitions. [2022-02-20 22:38:24,644 INFO L78 Accepts]: Start accepts. Automaton has 3285 states and 4787 transitions. Word has length 128 [2022-02-20 22:38:24,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:38:24,645 INFO L470 AbstractCegarLoop]: Abstraction has 3285 states and 4787 transitions. [2022-02-20 22:38:24,646 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 4 states have call successors, (17), 4 states have call predecessors, (17), 1 states have return successors, (15), 3 states have call predecessors, (15), 4 states have call successors, (15) [2022-02-20 22:38:24,646 INFO L276 IsEmpty]: Start isEmpty. Operand 3285 states and 4787 transitions. [2022-02-20 22:38:24,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2022-02-20 22:38:24,655 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:38:24,656 INFO L514 BasicCegarLoop]: trace histogram [7, 7, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:38:24,656 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-02-20 22:38:24,656 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:38:24,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:38:24,657 INFO L85 PathProgramCache]: Analyzing trace with hash -1043063430, now seen corresponding path program 1 times [2022-02-20 22:38:24,657 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:38:24,657 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39398579] [2022-02-20 22:38:24,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:38:24,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:38:24,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,839 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-02-20 22:38:24,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,848 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:24,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,858 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:24,859 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,859 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:24,859 INFO L290 TraceCheckUtils]: 0: Hoare triple {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {21481#true} is VALID [2022-02-20 22:38:24,860 INFO L272 TraceCheckUtils]: 1: Hoare triple {21481#true} call #t~ret868 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:24,860 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:24,860 INFO L290 TraceCheckUtils]: 3: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,860 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:24,860 INFO L290 TraceCheckUtils]: 5: Hoare triple {21481#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {21481#true} is VALID [2022-02-20 22:38:24,860 INFO L290 TraceCheckUtils]: 6: Hoare triple {21481#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {21481#true} is VALID [2022-02-20 22:38:24,860 INFO L290 TraceCheckUtils]: 7: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,861 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {21481#true} {21481#true} #4324#return; {21481#true} is VALID [2022-02-20 22:38:24,861 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 14 [2022-02-20 22:38:24,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,868 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:24,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,873 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:24,874 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,874 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:24,874 INFO L290 TraceCheckUtils]: 0: Hoare triple {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {21481#true} is VALID [2022-02-20 22:38:24,874 INFO L272 TraceCheckUtils]: 1: Hoare triple {21481#true} call #t~ret868 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:24,875 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:24,875 INFO L290 TraceCheckUtils]: 3: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,875 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:24,875 INFO L290 TraceCheckUtils]: 5: Hoare triple {21481#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {21481#true} is VALID [2022-02-20 22:38:24,875 INFO L290 TraceCheckUtils]: 6: Hoare triple {21481#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {21481#true} is VALID [2022-02-20 22:38:24,875 INFO L290 TraceCheckUtils]: 7: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,875 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {21481#true} {21481#true} #4326#return; {21481#true} is VALID [2022-02-20 22:38:24,876 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 25 [2022-02-20 22:38:24,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,895 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:24,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,902 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:24,902 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,902 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:24,902 INFO L290 TraceCheckUtils]: 0: Hoare triple {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {21481#true} is VALID [2022-02-20 22:38:24,902 INFO L272 TraceCheckUtils]: 1: Hoare triple {21481#true} call #t~ret868 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:24,903 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:24,904 INFO L290 TraceCheckUtils]: 3: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,905 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:24,910 INFO L290 TraceCheckUtils]: 5: Hoare triple {21481#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {21481#true} is VALID [2022-02-20 22:38:24,910 INFO L290 TraceCheckUtils]: 6: Hoare triple {21481#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {21481#true} is VALID [2022-02-20 22:38:24,911 INFO L290 TraceCheckUtils]: 7: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,911 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {21481#true} {21481#true} #4328#return; {21481#true} is VALID [2022-02-20 22:38:24,912 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2022-02-20 22:38:24,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,919 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:24,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,965 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:24,965 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,965 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:24,965 INFO L290 TraceCheckUtils]: 0: Hoare triple {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {21481#true} is VALID [2022-02-20 22:38:24,965 INFO L272 TraceCheckUtils]: 1: Hoare triple {21481#true} call #t~ret868 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:24,965 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:24,966 INFO L290 TraceCheckUtils]: 3: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,966 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:24,966 INFO L290 TraceCheckUtils]: 5: Hoare triple {21481#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {21481#true} is VALID [2022-02-20 22:38:24,966 INFO L290 TraceCheckUtils]: 6: Hoare triple {21481#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {21481#true} is VALID [2022-02-20 22:38:24,966 INFO L290 TraceCheckUtils]: 7: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,966 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {21481#true} {21481#true} #4330#return; {21481#true} is VALID [2022-02-20 22:38:24,966 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 49 [2022-02-20 22:38:24,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:24,976 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:24,976 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:24,977 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21519#(= 20 ~ldv_statevar_2~0)} #4332#return; {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,009 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 67 [2022-02-20 22:38:25,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,035 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-02-20 22:38:25,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,053 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:25,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,059 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21481#true} is VALID [2022-02-20 22:38:25,059 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,059 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21481#true} #4078#return; {21481#true} is VALID [2022-02-20 22:38:25,059 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 10 [2022-02-20 22:38:25,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,065 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,065 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,065 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21481#true} #4080#return; {21481#true} is VALID [2022-02-20 22:38:25,066 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 16 [2022-02-20 22:38:25,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,071 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,071 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,071 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,071 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21481#true} {21481#true} #4082#return; {21481#true} is VALID [2022-02-20 22:38:25,072 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 22 [2022-02-20 22:38:25,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,077 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,077 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,077 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,077 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21481#true} {21481#true} #4084#return; {21481#true} is VALID [2022-02-20 22:38:25,078 INFO L290 TraceCheckUtils]: 0: Hoare triple {21612#(and (= |old(#length)| |#length|) (= ~ldv_0_callback_handler~0.offset |old(~ldv_0_callback_handler~0.offset)|) (= |old(abs_6727)| abs_6727) (= |old(~ldv_0_thread_thread~0.base)| ~ldv_0_thread_thread~0.base) (= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0) (= |old(abs_8416)| abs_8416) (= |old(~ldv_0_thread_thread~0.offset)| ~ldv_0_thread_thread~0.offset) (= |#memory_int| |old(#memory_int)|) (= |old(~ldv_0_data_data~0.base)| ~ldv_0_data_data~0.base) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|) (= |old(abs_6728)| abs_6728) (= ~ldv_0_data_data~0.offset |old(~ldv_0_data_data~0.offset)|) (= ~ldv_0_callback_handler~0.base |old(~ldv_0_callback_handler~0.base)|) (= |old(abs_6733)| abs_6733) (= ~ldv_0_line_line~0 |old(~ldv_0_line_line~0)|) (= |old(#valid)| |#valid|) (= |old(abs_8415)| abs_8415) (= ~ldv_statevar_0~0 |old(~ldv_statevar_0~0)|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~lp~4#1.base, ~lp~4#1.offset;havoc ~tmp~27#1.base, ~tmp~27#1.offset;havoc ~tmp___0~9#1;havoc ~tmp___1~6#1; {21481#true} is VALID [2022-02-20 22:38:25,078 INFO L272 TraceCheckUtils]: 1: Hoare triple {21481#true} call #t~ret341#1.base, #t~ret341#1.offset := netdev_priv(~dev#1.base, ~dev#1.offset); {21481#true} is VALID [2022-02-20 22:38:25,078 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21481#true} is VALID [2022-02-20 22:38:25,078 INFO L290 TraceCheckUtils]: 3: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,078 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {21481#true} {21481#true} #4078#return; {21481#true} is VALID [2022-02-20 22:38:25,078 INFO L290 TraceCheckUtils]: 5: Hoare triple {21481#true} ~tmp~27#1.base, ~tmp~27#1.offset := #t~ret341#1.base, #t~ret341#1.offset;havoc #t~ret341#1.base, #t~ret341#1.offset;~lp~4#1.base, ~lp~4#1.offset := ~tmp~27#1.base, ~tmp~27#1.offset;call #t~mem342#1 := read~int(~dev#1.base, 64 + ~dev#1.offset, 4);call #t~mem343#1 := read~int(~lp~4#1.base, 94 + ~lp~4#1.offset, 1); {21481#true} is VALID [2022-02-20 22:38:25,079 INFO L290 TraceCheckUtils]: 6: Hoare triple {21481#true} assume (#t~mem343#1 % 256 - 1) % 4294967296 <= 1;#t~ite344#1 := 128; {21481#true} is VALID [2022-02-20 22:38:25,079 INFO L290 TraceCheckUtils]: 7: Hoare triple {21481#true} assume { :begin_inline_ldv_request_irq_86 } true;ldv_request_irq_86_#in~irq#1, ldv_request_irq_86_#in~handler#1.base, ldv_request_irq_86_#in~handler#1.offset, ldv_request_irq_86_#in~flags#1, ldv_request_irq_86_#in~name#1.base, ldv_request_irq_86_#in~name#1.offset, ldv_request_irq_86_#in~dev#1.base, ldv_request_irq_86_#in~dev#1.offset := #t~mem342#1, #funAddr~hp100_interrupt.base, #funAddr~hp100_interrupt.offset, #t~ite344#1, ~dev#1.base, ~dev#1.offset, ~dev#1.base, ~dev#1.offset;havoc ldv_request_irq_86_#res#1;havoc ldv_request_irq_86_#t~ret840#1, ldv_request_irq_86_#t~ret841#1, ldv_request_irq_86_~irq#1, ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset, ldv_request_irq_86_~flags#1, ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset, ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset, ldv_request_irq_86_~ldv_func_res~1#1, ldv_request_irq_86_~tmp~76#1, ldv_request_irq_86_~tmp___0~36#1;ldv_request_irq_86_~irq#1 := ldv_request_irq_86_#in~irq#1;ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset := ldv_request_irq_86_#in~handler#1.base, ldv_request_irq_86_#in~handler#1.offset;ldv_request_irq_86_~flags#1 := ldv_request_irq_86_#in~flags#1;ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset := ldv_request_irq_86_#in~name#1.base, ldv_request_irq_86_#in~name#1.offset;ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset := ldv_request_irq_86_#in~dev#1.base, ldv_request_irq_86_#in~dev#1.offset;havoc ldv_request_irq_86_~ldv_func_res~1#1;havoc ldv_request_irq_86_~tmp~76#1;havoc ldv_request_irq_86_~tmp___0~36#1;assume { :begin_inline_request_irq } true;request_irq_#in~irq#1, request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset, request_irq_#in~flags#1, request_irq_#in~name#1.base, request_irq_#in~name#1.offset, request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset := ldv_request_irq_86_~irq#1, ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset, ldv_request_irq_86_~flags#1, ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset, ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset;havoc request_irq_#res#1;havoc request_irq_#t~ret195#1, request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset, request_irq_~tmp~19#1;request_irq_~irq#1 := request_irq_#in~irq#1;request_irq_~handler#1.base, request_irq_~handler#1.offset := request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset;request_irq_~flags#1 := request_irq_#in~flags#1;request_irq_~name#1.base, request_irq_~name#1.offset := request_irq_#in~name#1.base, request_irq_#in~name#1.offset;request_irq_~dev#1.base, request_irq_~dev#1.offset := request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset;havoc request_irq_~tmp~19#1;assume { :begin_inline_request_threaded_irq } true;request_threaded_irq_#in~arg0#1, request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset, request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset, request_threaded_irq_#in~arg3#1, request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset, request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset := request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, 0, 0, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset;havoc request_threaded_irq_#res#1;havoc request_threaded_irq_#t~nondet965#1, request_threaded_irq_~arg0#1, request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset, request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset, request_threaded_irq_~arg3#1, request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset, request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset;request_threaded_irq_~arg0#1 := request_threaded_irq_#in~arg0#1;request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset := request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset;request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset := request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset;request_threaded_irq_~arg3#1 := request_threaded_irq_#in~arg3#1;request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset := request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset;request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset := request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset;assume -2147483648 <= request_threaded_irq_#t~nondet965#1 && request_threaded_irq_#t~nondet965#1 <= 2147483647;request_threaded_irq_#res#1 := request_threaded_irq_#t~nondet965#1;havoc request_threaded_irq_#t~nondet965#1; {21481#true} is VALID [2022-02-20 22:38:25,079 INFO L290 TraceCheckUtils]: 8: Hoare triple {21481#true} request_irq_#t~ret195#1 := request_threaded_irq_#res#1;assume { :end_inline_request_threaded_irq } true;assume -2147483648 <= request_irq_#t~ret195#1 && request_irq_#t~ret195#1 <= 2147483647;request_irq_~tmp~19#1 := request_irq_#t~ret195#1;havoc request_irq_#t~ret195#1;request_irq_#res#1 := request_irq_~tmp~19#1; {21481#true} is VALID [2022-02-20 22:38:25,079 INFO L290 TraceCheckUtils]: 9: Hoare triple {21481#true} ldv_request_irq_86_#t~ret840#1 := request_irq_#res#1;assume { :end_inline_request_irq } true;assume -2147483648 <= ldv_request_irq_86_#t~ret840#1 && ldv_request_irq_86_#t~ret840#1 <= 2147483647;ldv_request_irq_86_~tmp~76#1 := ldv_request_irq_86_#t~ret840#1;havoc ldv_request_irq_86_#t~ret840#1;ldv_request_irq_86_~ldv_func_res~1#1 := ldv_request_irq_86_~tmp~76#1;assume { :begin_inline_ldv_request_irq } true;ldv_request_irq_#in~arg0#1, ldv_request_irq_#in~arg1#1, ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset, ldv_request_irq_#in~arg3#1, ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset, ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset := ldv_request_irq_86_~ldv_func_res~1#1, ldv_request_irq_86_~irq#1, ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset, ldv_request_irq_86_~flags#1, ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset, ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset;havoc ldv_request_irq_#res#1;havoc ldv_request_irq_#t~ret829#1, ldv_request_irq_~arg0#1, ldv_request_irq_~arg1#1, ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset, ldv_request_irq_~arg3#1, ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset, ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset, ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset, ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset, ldv_request_irq_~ldv_7_line_line~0#1, ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset, ldv_request_irq_~tmp~69#1;ldv_request_irq_~arg0#1 := ldv_request_irq_#in~arg0#1;ldv_request_irq_~arg1#1 := ldv_request_irq_#in~arg1#1;ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset := ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset;ldv_request_irq_~arg3#1 := ldv_request_irq_#in~arg3#1;ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset := ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset;ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset := ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset;havoc ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset;havoc ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset;havoc ldv_request_irq_~ldv_7_line_line~0#1;havoc ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset;havoc ldv_request_irq_~tmp~69#1; {21481#true} is VALID [2022-02-20 22:38:25,079 INFO L272 TraceCheckUtils]: 10: Hoare triple {21481#true} call ldv_request_irq_#t~ret829#1 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:25,080 INFO L290 TraceCheckUtils]: 11: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,080 INFO L290 TraceCheckUtils]: 12: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,080 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {21481#true} {21481#true} #4080#return; {21481#true} is VALID [2022-02-20 22:38:25,080 INFO L290 TraceCheckUtils]: 14: Hoare triple {21481#true} assume -2147483648 <= ldv_request_irq_#t~ret829#1 && ldv_request_irq_#t~ret829#1 <= 2147483647;ldv_request_irq_~tmp~69#1 := ldv_request_irq_#t~ret829#1;havoc ldv_request_irq_#t~ret829#1; {21481#true} is VALID [2022-02-20 22:38:25,080 INFO L290 TraceCheckUtils]: 15: Hoare triple {21481#true} assume 0 != ldv_request_irq_~tmp~69#1; {21481#true} is VALID [2022-02-20 22:38:25,080 INFO L272 TraceCheckUtils]: 16: Hoare triple {21481#true} call ldv_assume((if 0 == ldv_request_irq_~arg0#1 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,081 INFO L290 TraceCheckUtils]: 17: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,081 INFO L290 TraceCheckUtils]: 18: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,081 INFO L290 TraceCheckUtils]: 19: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,081 INFO L284 TraceCheckUtils]: 20: Hoare quadruple {21481#true} {21481#true} #4082#return; {21481#true} is VALID [2022-02-20 22:38:25,081 INFO L290 TraceCheckUtils]: 21: Hoare triple {21481#true} ldv_request_irq_~ldv_7_line_line~0#1 := (if ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 <= 2147483647 then ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 else ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 - 4294967296);ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset := ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset;ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset := 0, 0;ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset := ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset; {21481#true} is VALID [2022-02-20 22:38:25,081 INFO L272 TraceCheckUtils]: 22: Hoare triple {21481#true} call ldv_assume((if 6 == ~ldv_statevar_0~0 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,082 INFO L290 TraceCheckUtils]: 23: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,082 INFO L290 TraceCheckUtils]: 24: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,082 INFO L290 TraceCheckUtils]: 25: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,082 INFO L284 TraceCheckUtils]: 26: Hoare quadruple {21481#true} {21481#true} #4084#return; {21481#true} is VALID [2022-02-20 22:38:25,082 INFO L290 TraceCheckUtils]: 27: Hoare triple {21481#true} assume { :begin_inline_ldv_dispatch_irq_register_7_2 } true;ldv_dispatch_irq_register_7_2_#in~arg0#1, ldv_dispatch_irq_register_7_2_#in~arg1#1.base, ldv_dispatch_irq_register_7_2_#in~arg1#1.offset, ldv_dispatch_irq_register_7_2_#in~arg2#1.base, ldv_dispatch_irq_register_7_2_#in~arg2#1.offset, ldv_dispatch_irq_register_7_2_#in~arg3#1.base, ldv_dispatch_irq_register_7_2_#in~arg3#1.offset := ldv_request_irq_~ldv_7_line_line~0#1, ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset, ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset, ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset;havoc ldv_dispatch_irq_register_7_2_~arg0#1, ldv_dispatch_irq_register_7_2_~arg1#1.base, ldv_dispatch_irq_register_7_2_~arg1#1.offset, ldv_dispatch_irq_register_7_2_~arg2#1.base, ldv_dispatch_irq_register_7_2_~arg2#1.offset, ldv_dispatch_irq_register_7_2_~arg3#1.base, ldv_dispatch_irq_register_7_2_~arg3#1.offset;ldv_dispatch_irq_register_7_2_~arg0#1 := ldv_dispatch_irq_register_7_2_#in~arg0#1;ldv_dispatch_irq_register_7_2_~arg1#1.base, ldv_dispatch_irq_register_7_2_~arg1#1.offset := ldv_dispatch_irq_register_7_2_#in~arg1#1.base, ldv_dispatch_irq_register_7_2_#in~arg1#1.offset;ldv_dispatch_irq_register_7_2_~arg2#1.base, ldv_dispatch_irq_register_7_2_~arg2#1.offset := ldv_dispatch_irq_register_7_2_#in~arg2#1.base, ldv_dispatch_irq_register_7_2_#in~arg2#1.offset;ldv_dispatch_irq_register_7_2_~arg3#1.base, ldv_dispatch_irq_register_7_2_~arg3#1.offset := ldv_dispatch_irq_register_7_2_#in~arg3#1.base, ldv_dispatch_irq_register_7_2_#in~arg3#1.offset;~ldv_0_line_line~0 := ldv_dispatch_irq_register_7_2_~arg0#1;~ldv_0_callback_handler~0.base, ~ldv_0_callback_handler~0.offset := ldv_dispatch_irq_register_7_2_~arg1#1.base, ldv_dispatch_irq_register_7_2_~arg1#1.offset;~ldv_0_thread_thread~0.base, ~ldv_0_thread_thread~0.offset := ldv_dispatch_irq_register_7_2_~arg2#1.base, ldv_dispatch_irq_register_7_2_~arg2#1.offset;~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset := ldv_dispatch_irq_register_7_2_~arg3#1.base, ldv_dispatch_irq_register_7_2_~arg3#1.offset;assume { :begin_inline_ldv_switch_automaton_state_0_6 } true;~ldv_statevar_0~0 := 5; {21481#true} is VALID [2022-02-20 22:38:25,082 INFO L290 TraceCheckUtils]: 28: Hoare triple {21481#true} assume { :end_inline_ldv_switch_automaton_state_0_6 } true; {21481#true} is VALID [2022-02-20 22:38:25,083 INFO L290 TraceCheckUtils]: 29: Hoare triple {21481#true} assume { :end_inline_ldv_dispatch_irq_register_7_2 } true;ldv_request_irq_#res#1 := ldv_request_irq_~arg0#1; {21481#true} is VALID [2022-02-20 22:38:25,083 INFO L290 TraceCheckUtils]: 30: Hoare triple {21481#true} ldv_request_irq_86_#t~ret841#1 := ldv_request_irq_#res#1;assume { :end_inline_ldv_request_irq } true;assume -2147483648 <= ldv_request_irq_86_#t~ret841#1 && ldv_request_irq_86_#t~ret841#1 <= 2147483647;ldv_request_irq_86_~tmp___0~36#1 := ldv_request_irq_86_#t~ret841#1;havoc ldv_request_irq_86_#t~ret841#1;ldv_request_irq_86_#res#1 := ldv_request_irq_86_~tmp___0~36#1; {21481#true} is VALID [2022-02-20 22:38:25,083 INFO L290 TraceCheckUtils]: 31: Hoare triple {21481#true} #t~ret345#1 := ldv_request_irq_86_#res#1;assume { :end_inline_ldv_request_irq_86 } true;assume -2147483648 <= #t~ret345#1 && #t~ret345#1 <= 2147483647;~tmp___0~9#1 := #t~ret345#1;havoc #t~mem342#1;havoc #t~mem343#1;havoc #t~ite344#1;havoc #t~ret345#1; {21481#true} is VALID [2022-02-20 22:38:25,083 INFO L290 TraceCheckUtils]: 32: Hoare triple {21481#true} assume 0 != ~tmp___0~9#1;havoc #t~nondet346#1;call #t~mem347#1 := read~int(~dev#1.base, 64 + ~dev#1.offset, 4);havoc #t~mem347#1;#res#1 := -11; {21481#true} is VALID [2022-02-20 22:38:25,083 INFO L290 TraceCheckUtils]: 33: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,083 INFO L284 TraceCheckUtils]: 34: Hoare quadruple {21481#true} {21481#true} #4120#return; {21481#true} is VALID [2022-02-20 22:38:25,084 INFO L290 TraceCheckUtils]: 0: Hoare triple {21612#(and (= |old(#length)| |#length|) (= ~ldv_0_callback_handler~0.offset |old(~ldv_0_callback_handler~0.offset)|) (= |old(abs_6727)| abs_6727) (= |old(~ldv_0_thread_thread~0.base)| ~ldv_0_thread_thread~0.base) (= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0) (= |old(abs_8416)| abs_8416) (= |old(~ldv_0_thread_thread~0.offset)| ~ldv_0_thread_thread~0.offset) (= |#memory_int| |old(#memory_int)|) (= |old(~ldv_0_data_data~0.base)| ~ldv_0_data_data~0.base) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|) (= |old(abs_6728)| abs_6728) (= ~ldv_0_data_data~0.offset |old(~ldv_0_data_data~0.offset)|) (= ~ldv_0_callback_handler~0.base |old(~ldv_0_callback_handler~0.base)|) (= |old(abs_6733)| abs_6733) (= ~ldv_0_line_line~0 |old(~ldv_0_line_line~0)|) (= |old(#valid)| |#valid|) (= |old(abs_8415)| abs_8415) (= ~ldv_statevar_0~0 |old(~ldv_statevar_0~0)|))} #~782.base, #~782.offset := #in~782.base, #in~782.offset; {21481#true} is VALID [2022-02-20 22:38:25,084 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume !(#in~#fp.base == #funAddr~eth_validate_addr.base && #in~#fp.offset == #funAddr~eth_validate_addr.offset); {21481#true} is VALID [2022-02-20 22:38:25,084 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} assume !(#in~#fp.base == #funAddr~hp100_close.base && #in~#fp.offset == #funAddr~hp100_close.offset); {21481#true} is VALID [2022-02-20 22:38:25,086 INFO L272 TraceCheckUtils]: 3: Hoare triple {21481#true} call #t~ret975 := hp100_open(#~782.base, #~782.offset); {21612#(and (= |old(#length)| |#length|) (= ~ldv_0_callback_handler~0.offset |old(~ldv_0_callback_handler~0.offset)|) (= |old(abs_6727)| abs_6727) (= |old(~ldv_0_thread_thread~0.base)| ~ldv_0_thread_thread~0.base) (= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0) (= |old(abs_8416)| abs_8416) (= |old(~ldv_0_thread_thread~0.offset)| ~ldv_0_thread_thread~0.offset) (= |#memory_int| |old(#memory_int)|) (= |old(~ldv_0_data_data~0.base)| ~ldv_0_data_data~0.base) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|) (= |old(abs_6728)| abs_6728) (= ~ldv_0_data_data~0.offset |old(~ldv_0_data_data~0.offset)|) (= ~ldv_0_callback_handler~0.base |old(~ldv_0_callback_handler~0.base)|) (= |old(abs_6733)| abs_6733) (= ~ldv_0_line_line~0 |old(~ldv_0_line_line~0)|) (= |old(#valid)| |#valid|) (= |old(abs_8415)| abs_8415) (= ~ldv_statevar_0~0 |old(~ldv_statevar_0~0)|))} is VALID [2022-02-20 22:38:25,086 INFO L290 TraceCheckUtils]: 4: Hoare triple {21612#(and (= |old(#length)| |#length|) (= ~ldv_0_callback_handler~0.offset |old(~ldv_0_callback_handler~0.offset)|) (= |old(abs_6727)| abs_6727) (= |old(~ldv_0_thread_thread~0.base)| ~ldv_0_thread_thread~0.base) (= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0) (= |old(abs_8416)| abs_8416) (= |old(~ldv_0_thread_thread~0.offset)| ~ldv_0_thread_thread~0.offset) (= |#memory_int| |old(#memory_int)|) (= |old(~ldv_0_data_data~0.base)| ~ldv_0_data_data~0.base) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|) (= |old(abs_6728)| abs_6728) (= ~ldv_0_data_data~0.offset |old(~ldv_0_data_data~0.offset)|) (= ~ldv_0_callback_handler~0.base |old(~ldv_0_callback_handler~0.base)|) (= |old(abs_6733)| abs_6733) (= ~ldv_0_line_line~0 |old(~ldv_0_line_line~0)|) (= |old(#valid)| |#valid|) (= |old(abs_8415)| abs_8415) (= ~ldv_statevar_0~0 |old(~ldv_statevar_0~0)|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~lp~4#1.base, ~lp~4#1.offset;havoc ~tmp~27#1.base, ~tmp~27#1.offset;havoc ~tmp___0~9#1;havoc ~tmp___1~6#1; {21481#true} is VALID [2022-02-20 22:38:25,086 INFO L272 TraceCheckUtils]: 5: Hoare triple {21481#true} call #t~ret341#1.base, #t~ret341#1.offset := netdev_priv(~dev#1.base, ~dev#1.offset); {21481#true} is VALID [2022-02-20 22:38:25,087 INFO L290 TraceCheckUtils]: 6: Hoare triple {21481#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21481#true} is VALID [2022-02-20 22:38:25,087 INFO L290 TraceCheckUtils]: 7: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,087 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {21481#true} {21481#true} #4078#return; {21481#true} is VALID [2022-02-20 22:38:25,087 INFO L290 TraceCheckUtils]: 9: Hoare triple {21481#true} ~tmp~27#1.base, ~tmp~27#1.offset := #t~ret341#1.base, #t~ret341#1.offset;havoc #t~ret341#1.base, #t~ret341#1.offset;~lp~4#1.base, ~lp~4#1.offset := ~tmp~27#1.base, ~tmp~27#1.offset;call #t~mem342#1 := read~int(~dev#1.base, 64 + ~dev#1.offset, 4);call #t~mem343#1 := read~int(~lp~4#1.base, 94 + ~lp~4#1.offset, 1); {21481#true} is VALID [2022-02-20 22:38:25,087 INFO L290 TraceCheckUtils]: 10: Hoare triple {21481#true} assume (#t~mem343#1 % 256 - 1) % 4294967296 <= 1;#t~ite344#1 := 128; {21481#true} is VALID [2022-02-20 22:38:25,087 INFO L290 TraceCheckUtils]: 11: Hoare triple {21481#true} assume { :begin_inline_ldv_request_irq_86 } true;ldv_request_irq_86_#in~irq#1, ldv_request_irq_86_#in~handler#1.base, ldv_request_irq_86_#in~handler#1.offset, ldv_request_irq_86_#in~flags#1, ldv_request_irq_86_#in~name#1.base, ldv_request_irq_86_#in~name#1.offset, ldv_request_irq_86_#in~dev#1.base, ldv_request_irq_86_#in~dev#1.offset := #t~mem342#1, #funAddr~hp100_interrupt.base, #funAddr~hp100_interrupt.offset, #t~ite344#1, ~dev#1.base, ~dev#1.offset, ~dev#1.base, ~dev#1.offset;havoc ldv_request_irq_86_#res#1;havoc ldv_request_irq_86_#t~ret840#1, ldv_request_irq_86_#t~ret841#1, ldv_request_irq_86_~irq#1, ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset, ldv_request_irq_86_~flags#1, ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset, ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset, ldv_request_irq_86_~ldv_func_res~1#1, ldv_request_irq_86_~tmp~76#1, ldv_request_irq_86_~tmp___0~36#1;ldv_request_irq_86_~irq#1 := ldv_request_irq_86_#in~irq#1;ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset := ldv_request_irq_86_#in~handler#1.base, ldv_request_irq_86_#in~handler#1.offset;ldv_request_irq_86_~flags#1 := ldv_request_irq_86_#in~flags#1;ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset := ldv_request_irq_86_#in~name#1.base, ldv_request_irq_86_#in~name#1.offset;ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset := ldv_request_irq_86_#in~dev#1.base, ldv_request_irq_86_#in~dev#1.offset;havoc ldv_request_irq_86_~ldv_func_res~1#1;havoc ldv_request_irq_86_~tmp~76#1;havoc ldv_request_irq_86_~tmp___0~36#1;assume { :begin_inline_request_irq } true;request_irq_#in~irq#1, request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset, request_irq_#in~flags#1, request_irq_#in~name#1.base, request_irq_#in~name#1.offset, request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset := ldv_request_irq_86_~irq#1, ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset, ldv_request_irq_86_~flags#1, ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset, ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset;havoc request_irq_#res#1;havoc request_irq_#t~ret195#1, request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset, request_irq_~tmp~19#1;request_irq_~irq#1 := request_irq_#in~irq#1;request_irq_~handler#1.base, request_irq_~handler#1.offset := request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset;request_irq_~flags#1 := request_irq_#in~flags#1;request_irq_~name#1.base, request_irq_~name#1.offset := request_irq_#in~name#1.base, request_irq_#in~name#1.offset;request_irq_~dev#1.base, request_irq_~dev#1.offset := request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset;havoc request_irq_~tmp~19#1;assume { :begin_inline_request_threaded_irq } true;request_threaded_irq_#in~arg0#1, request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset, request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset, request_threaded_irq_#in~arg3#1, request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset, request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset := request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, 0, 0, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset;havoc request_threaded_irq_#res#1;havoc request_threaded_irq_#t~nondet965#1, request_threaded_irq_~arg0#1, request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset, request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset, request_threaded_irq_~arg3#1, request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset, request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset;request_threaded_irq_~arg0#1 := request_threaded_irq_#in~arg0#1;request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset := request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset;request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset := request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset;request_threaded_irq_~arg3#1 := request_threaded_irq_#in~arg3#1;request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset := request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset;request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset := request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset;assume -2147483648 <= request_threaded_irq_#t~nondet965#1 && request_threaded_irq_#t~nondet965#1 <= 2147483647;request_threaded_irq_#res#1 := request_threaded_irq_#t~nondet965#1;havoc request_threaded_irq_#t~nondet965#1; {21481#true} is VALID [2022-02-20 22:38:25,088 INFO L290 TraceCheckUtils]: 12: Hoare triple {21481#true} request_irq_#t~ret195#1 := request_threaded_irq_#res#1;assume { :end_inline_request_threaded_irq } true;assume -2147483648 <= request_irq_#t~ret195#1 && request_irq_#t~ret195#1 <= 2147483647;request_irq_~tmp~19#1 := request_irq_#t~ret195#1;havoc request_irq_#t~ret195#1;request_irq_#res#1 := request_irq_~tmp~19#1; {21481#true} is VALID [2022-02-20 22:38:25,088 INFO L290 TraceCheckUtils]: 13: Hoare triple {21481#true} ldv_request_irq_86_#t~ret840#1 := request_irq_#res#1;assume { :end_inline_request_irq } true;assume -2147483648 <= ldv_request_irq_86_#t~ret840#1 && ldv_request_irq_86_#t~ret840#1 <= 2147483647;ldv_request_irq_86_~tmp~76#1 := ldv_request_irq_86_#t~ret840#1;havoc ldv_request_irq_86_#t~ret840#1;ldv_request_irq_86_~ldv_func_res~1#1 := ldv_request_irq_86_~tmp~76#1;assume { :begin_inline_ldv_request_irq } true;ldv_request_irq_#in~arg0#1, ldv_request_irq_#in~arg1#1, ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset, ldv_request_irq_#in~arg3#1, ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset, ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset := ldv_request_irq_86_~ldv_func_res~1#1, ldv_request_irq_86_~irq#1, ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset, ldv_request_irq_86_~flags#1, ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset, ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset;havoc ldv_request_irq_#res#1;havoc ldv_request_irq_#t~ret829#1, ldv_request_irq_~arg0#1, ldv_request_irq_~arg1#1, ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset, ldv_request_irq_~arg3#1, ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset, ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset, ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset, ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset, ldv_request_irq_~ldv_7_line_line~0#1, ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset, ldv_request_irq_~tmp~69#1;ldv_request_irq_~arg0#1 := ldv_request_irq_#in~arg0#1;ldv_request_irq_~arg1#1 := ldv_request_irq_#in~arg1#1;ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset := ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset;ldv_request_irq_~arg3#1 := ldv_request_irq_#in~arg3#1;ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset := ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset;ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset := ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset;havoc ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset;havoc ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset;havoc ldv_request_irq_~ldv_7_line_line~0#1;havoc ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset;havoc ldv_request_irq_~tmp~69#1; {21481#true} is VALID [2022-02-20 22:38:25,088 INFO L272 TraceCheckUtils]: 14: Hoare triple {21481#true} call ldv_request_irq_#t~ret829#1 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:25,088 INFO L290 TraceCheckUtils]: 15: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,088 INFO L290 TraceCheckUtils]: 16: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,088 INFO L284 TraceCheckUtils]: 17: Hoare quadruple {21481#true} {21481#true} #4080#return; {21481#true} is VALID [2022-02-20 22:38:25,089 INFO L290 TraceCheckUtils]: 18: Hoare triple {21481#true} assume -2147483648 <= ldv_request_irq_#t~ret829#1 && ldv_request_irq_#t~ret829#1 <= 2147483647;ldv_request_irq_~tmp~69#1 := ldv_request_irq_#t~ret829#1;havoc ldv_request_irq_#t~ret829#1; {21481#true} is VALID [2022-02-20 22:38:25,089 INFO L290 TraceCheckUtils]: 19: Hoare triple {21481#true} assume 0 != ldv_request_irq_~tmp~69#1; {21481#true} is VALID [2022-02-20 22:38:25,089 INFO L272 TraceCheckUtils]: 20: Hoare triple {21481#true} call ldv_assume((if 0 == ldv_request_irq_~arg0#1 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,089 INFO L290 TraceCheckUtils]: 21: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,089 INFO L290 TraceCheckUtils]: 22: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,089 INFO L290 TraceCheckUtils]: 23: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,089 INFO L284 TraceCheckUtils]: 24: Hoare quadruple {21481#true} {21481#true} #4082#return; {21481#true} is VALID [2022-02-20 22:38:25,090 INFO L290 TraceCheckUtils]: 25: Hoare triple {21481#true} ldv_request_irq_~ldv_7_line_line~0#1 := (if ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 <= 2147483647 then ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 else ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 - 4294967296);ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset := ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset;ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset := 0, 0;ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset := ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset; {21481#true} is VALID [2022-02-20 22:38:25,090 INFO L272 TraceCheckUtils]: 26: Hoare triple {21481#true} call ldv_assume((if 6 == ~ldv_statevar_0~0 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,090 INFO L290 TraceCheckUtils]: 27: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,090 INFO L290 TraceCheckUtils]: 28: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,090 INFO L290 TraceCheckUtils]: 29: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,090 INFO L284 TraceCheckUtils]: 30: Hoare quadruple {21481#true} {21481#true} #4084#return; {21481#true} is VALID [2022-02-20 22:38:25,091 INFO L290 TraceCheckUtils]: 31: Hoare triple {21481#true} assume { :begin_inline_ldv_dispatch_irq_register_7_2 } true;ldv_dispatch_irq_register_7_2_#in~arg0#1, ldv_dispatch_irq_register_7_2_#in~arg1#1.base, ldv_dispatch_irq_register_7_2_#in~arg1#1.offset, ldv_dispatch_irq_register_7_2_#in~arg2#1.base, ldv_dispatch_irq_register_7_2_#in~arg2#1.offset, ldv_dispatch_irq_register_7_2_#in~arg3#1.base, ldv_dispatch_irq_register_7_2_#in~arg3#1.offset := ldv_request_irq_~ldv_7_line_line~0#1, ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset, ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset, ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset;havoc ldv_dispatch_irq_register_7_2_~arg0#1, ldv_dispatch_irq_register_7_2_~arg1#1.base, ldv_dispatch_irq_register_7_2_~arg1#1.offset, ldv_dispatch_irq_register_7_2_~arg2#1.base, ldv_dispatch_irq_register_7_2_~arg2#1.offset, ldv_dispatch_irq_register_7_2_~arg3#1.base, ldv_dispatch_irq_register_7_2_~arg3#1.offset;ldv_dispatch_irq_register_7_2_~arg0#1 := ldv_dispatch_irq_register_7_2_#in~arg0#1;ldv_dispatch_irq_register_7_2_~arg1#1.base, ldv_dispatch_irq_register_7_2_~arg1#1.offset := ldv_dispatch_irq_register_7_2_#in~arg1#1.base, ldv_dispatch_irq_register_7_2_#in~arg1#1.offset;ldv_dispatch_irq_register_7_2_~arg2#1.base, ldv_dispatch_irq_register_7_2_~arg2#1.offset := ldv_dispatch_irq_register_7_2_#in~arg2#1.base, ldv_dispatch_irq_register_7_2_#in~arg2#1.offset;ldv_dispatch_irq_register_7_2_~arg3#1.base, ldv_dispatch_irq_register_7_2_~arg3#1.offset := ldv_dispatch_irq_register_7_2_#in~arg3#1.base, ldv_dispatch_irq_register_7_2_#in~arg3#1.offset;~ldv_0_line_line~0 := ldv_dispatch_irq_register_7_2_~arg0#1;~ldv_0_callback_handler~0.base, ~ldv_0_callback_handler~0.offset := ldv_dispatch_irq_register_7_2_~arg1#1.base, ldv_dispatch_irq_register_7_2_~arg1#1.offset;~ldv_0_thread_thread~0.base, ~ldv_0_thread_thread~0.offset := ldv_dispatch_irq_register_7_2_~arg2#1.base, ldv_dispatch_irq_register_7_2_~arg2#1.offset;~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset := ldv_dispatch_irq_register_7_2_~arg3#1.base, ldv_dispatch_irq_register_7_2_~arg3#1.offset;assume { :begin_inline_ldv_switch_automaton_state_0_6 } true;~ldv_statevar_0~0 := 5; {21481#true} is VALID [2022-02-20 22:38:25,091 INFO L290 TraceCheckUtils]: 32: Hoare triple {21481#true} assume { :end_inline_ldv_switch_automaton_state_0_6 } true; {21481#true} is VALID [2022-02-20 22:38:25,091 INFO L290 TraceCheckUtils]: 33: Hoare triple {21481#true} assume { :end_inline_ldv_dispatch_irq_register_7_2 } true;ldv_request_irq_#res#1 := ldv_request_irq_~arg0#1; {21481#true} is VALID [2022-02-20 22:38:25,091 INFO L290 TraceCheckUtils]: 34: Hoare triple {21481#true} ldv_request_irq_86_#t~ret841#1 := ldv_request_irq_#res#1;assume { :end_inline_ldv_request_irq } true;assume -2147483648 <= ldv_request_irq_86_#t~ret841#1 && ldv_request_irq_86_#t~ret841#1 <= 2147483647;ldv_request_irq_86_~tmp___0~36#1 := ldv_request_irq_86_#t~ret841#1;havoc ldv_request_irq_86_#t~ret841#1;ldv_request_irq_86_#res#1 := ldv_request_irq_86_~tmp___0~36#1; {21481#true} is VALID [2022-02-20 22:38:25,091 INFO L290 TraceCheckUtils]: 35: Hoare triple {21481#true} #t~ret345#1 := ldv_request_irq_86_#res#1;assume { :end_inline_ldv_request_irq_86 } true;assume -2147483648 <= #t~ret345#1 && #t~ret345#1 <= 2147483647;~tmp___0~9#1 := #t~ret345#1;havoc #t~mem342#1;havoc #t~mem343#1;havoc #t~ite344#1;havoc #t~ret345#1; {21481#true} is VALID [2022-02-20 22:38:25,091 INFO L290 TraceCheckUtils]: 36: Hoare triple {21481#true} assume 0 != ~tmp___0~9#1;havoc #t~nondet346#1;call #t~mem347#1 := read~int(~dev#1.base, 64 + ~dev#1.offset, 4);havoc #t~mem347#1;#res#1 := -11; {21481#true} is VALID [2022-02-20 22:38:25,092 INFO L290 TraceCheckUtils]: 37: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,092 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {21481#true} {21481#true} #4120#return; {21481#true} is VALID [2022-02-20 22:38:25,092 INFO L290 TraceCheckUtils]: 39: Hoare triple {21481#true} assume -2147483648 <= #t~ret975 && #t~ret975 <= 2147483647;#t~funptrres974 := #t~ret975; {21481#true} is VALID [2022-02-20 22:38:25,092 INFO L290 TraceCheckUtils]: 40: Hoare triple {21481#true} #res := #t~funptrres974;havoc #t~funptrres974;havoc #t~ret975;havoc #t~ret976;havoc #t~ret977; {21481#true} is VALID [2022-02-20 22:38:25,092 INFO L290 TraceCheckUtils]: 41: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,092 INFO L284 TraceCheckUtils]: 42: Hoare quadruple {21481#true} {21482#false} #4516#return; {21482#false} is VALID [2022-02-20 22:38:25,093 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 115 [2022-02-20 22:38:25,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,099 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,099 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,099 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21482#false} #4332#return; {21482#false} is VALID [2022-02-20 22:38:25,100 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 128 [2022-02-20 22:38:25,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,105 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21481#true} is VALID [2022-02-20 22:38:25,106 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,106 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21482#false} #4368#return; {21482#false} is VALID [2022-02-20 22:38:25,110 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 134 [2022-02-20 22:38:25,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,117 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-02-20 22:38:25,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,124 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {21481#true} is VALID [2022-02-20 22:38:25,124 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,124 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21662#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} #4016#return; {21481#true} is VALID [2022-02-20 22:38:25,124 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 22:38:25,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,129 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,130 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,130 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,130 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21481#true} {21481#true} #4018#return; {21481#true} is VALID [2022-02-20 22:38:25,130 INFO L272 TraceCheckUtils]: 0: Hoare triple {21662#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} call ldv_assert(87, 0, (if 1 == ~ldv_spin_lock_of_hp100_private~0 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,130 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {21481#true} is VALID [2022-02-20 22:38:25,130 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,131 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21481#true} {21662#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} #4016#return; {21481#true} is VALID [2022-02-20 22:38:25,131 INFO L272 TraceCheckUtils]: 4: Hoare triple {21481#true} call ldv_assume((if 1 == ~ldv_spin_lock_of_hp100_private~0 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,131 INFO L290 TraceCheckUtils]: 5: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,131 INFO L290 TraceCheckUtils]: 6: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,131 INFO L290 TraceCheckUtils]: 7: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,131 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {21481#true} {21481#true} #4018#return; {21481#true} is VALID [2022-02-20 22:38:25,132 INFO L290 TraceCheckUtils]: 9: Hoare triple {21481#true} ~ldv_spin_lock_of_hp100_private~0 := 2; {21481#true} is VALID [2022-02-20 22:38:25,132 INFO L290 TraceCheckUtils]: 10: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,132 INFO L284 TraceCheckUtils]: 11: Hoare quadruple {21481#true} {21482#false} #4370#return; {21482#false} is VALID [2022-02-20 22:38:25,132 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 151 [2022-02-20 22:38:25,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,139 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~value := #in~value;~port := #in~port; {21481#true} is VALID [2022-02-20 22:38:25,139 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,139 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21482#false} #4372#return; {21482#false} is VALID [2022-02-20 22:38:25,139 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 155 [2022-02-20 22:38:25,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,145 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~port := #in~port;havoc ~value~1;#res := ~value~1; {21481#true} is VALID [2022-02-20 22:38:25,145 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,145 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21482#false} #4374#return; {21482#false} is VALID [2022-02-20 22:38:25,146 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 164 [2022-02-20 22:38:25,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,152 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21481#true} is VALID [2022-02-20 22:38:25,152 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,152 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21482#false} #4382#return; {21482#false} is VALID [2022-02-20 22:38:25,152 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 169 [2022-02-20 22:38:25,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,158 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {21481#true} is VALID [2022-02-20 22:38:25,158 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,159 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21482#false} #4384#return; {21482#false} is VALID [2022-02-20 22:38:25,159 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 187 [2022-02-20 22:38:25,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:25,164 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} assume 2 == ~ldv_spin__xmit_lock_of_netdev_queue~0;#res := 1; {21481#true} is VALID [2022-02-20 22:38:25,164 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,164 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21481#true} {21482#false} #3826#return; {21482#false} is VALID [2022-02-20 22:38:25,164 INFO L290 TraceCheckUtils]: 0: Hoare triple {21481#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(190, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(5, 4);call write~init~int(37, 4, 0, 1);call write~init~int(48, 4, 1, 1);call write~init~int(52, 4, 2, 1);call write~init~int(88, 4, 3, 1);call write~init~int(0, 4, 4, 1);call #Ultimate.allocInit(6, 5);call write~init~int(104, 5, 0, 1);call write~init~int(112, 5, 1, 1);call write~init~int(49, 5, 2, 1);call write~init~int(48, 5, 3, 1);call write~init~int(48, 5, 4, 1);call write~init~int(0, 5, 5, 1);call #Ultimate.allocInit(49, 6);call #Ultimate.allocInit(54, 7);call #Ultimate.allocInit(31, 8);call #Ultimate.allocInit(38, 9);call #Ultimate.allocInit(34, 10);call #Ultimate.allocInit(32, 11);call #Ultimate.allocInit(42, 12);call #Ultimate.allocInit(81, 13);call #Ultimate.allocInit(42, 14);call #Ultimate.allocInit(20, 15);call #Ultimate.allocInit(25, 16);call #Ultimate.allocInit(5, 17);call write~init~int(69, 17, 0, 1);call write~init~int(73, 17, 1, 1);call write~init~int(83, 17, 2, 1);call write~init~int(65, 17, 3, 1);call write~init~int(0, 17, 4, 1);call #Ultimate.allocInit(4, 18);call write~init~int(80, 18, 0, 1);call write~init~int(67, 18, 1, 1);call write~init~int(73, 18, 2, 1);call write~init~int(0, 18, 3, 1);call #Ultimate.allocInit(4, 19);call write~init~int(73, 19, 0, 1);call write~init~int(83, 19, 1, 1);call write~init~int(65, 19, 2, 1);call write~init~int(0, 19, 3, 1);call #Ultimate.allocInit(30, 20);call #Ultimate.allocInit(34, 21);call #Ultimate.allocInit(19, 22);call #Ultimate.allocInit(3, 23);call write~init~int(46, 23, 0, 1);call write~init~int(10, 23, 1, 1);call write~init~int(0, 23, 2, 1);call #Ultimate.allocInit(8, 24);call #Ultimate.allocInit(24, 25);call #Ultimate.allocInit(37, 26);call #Ultimate.allocInit(27, 27);call #Ultimate.allocInit(24, 28);call #Ultimate.allocInit(21, 29);call #Ultimate.allocInit(33, 30);call #Ultimate.allocInit(58, 31);call #Ultimate.allocInit(48, 32);call #Ultimate.allocInit(48, 33);call #Ultimate.allocInit(31, 34);call #Ultimate.allocInit(45, 35);call #Ultimate.allocInit(39, 36);call #Ultimate.allocInit(31, 37);call #Ultimate.allocInit(53, 38);call #Ultimate.allocInit(28, 39);call #Ultimate.allocInit(39, 40);call #Ultimate.allocInit(31, 41);call #Ultimate.allocInit(53, 42);call #Ultimate.allocInit(28, 43);call #Ultimate.allocInit(28, 44);call #Ultimate.allocInit(64, 45);call #Ultimate.allocInit(43, 46);call #Ultimate.allocInit(40, 47);call #Ultimate.allocInit(8, 48);call #Ultimate.allocInit(42, 49);call #Ultimate.allocInit(31, 50);call #Ultimate.allocInit(64, 51);call #Ultimate.allocInit(50, 52);call #Ultimate.allocInit(29, 53);call #Ultimate.allocInit(6, 54);call write~init~int(104, 54, 0, 1);call write~init~int(112, 54, 1, 1);call write~init~int(49, 54, 2, 1);call write~init~int(48, 54, 3, 1);call write~init~int(48, 54, 4, 1);call write~init~int(0, 54, 5, 1);call #Ultimate.allocInit(6, 55);call write~init~int(104, 55, 0, 1);call write~init~int(112, 55, 1, 1);call write~init~int(49, 55, 2, 1);call write~init~int(48, 55, 3, 1);call write~init~int(48, 55, 4, 1);call write~init~int(0, 55, 5, 1);call #Ultimate.allocInit(1, 56);call write~init~int(0, 56, 0, 1);call #Ultimate.allocInit(54, 57);call #Ultimate.allocInit(56, 58);call #Ultimate.allocInit(58, 59);call #Ultimate.allocInit(58, 60);call #Ultimate.allocInit(58, 61);call #Ultimate.allocInit(54, 62);call #Ultimate.allocInit(56, 63);call #Ultimate.allocInit(58, 64);call #Ultimate.allocInit(58, 65);call #Ultimate.allocInit(58, 66);call #Ultimate.allocInit(54, 67);call #Ultimate.allocInit(56, 68);call #Ultimate.allocInit(58, 69);call #Ultimate.allocInit(58, 70);call #Ultimate.allocInit(58, 71);call #Ultimate.allocInit(54, 72);call #Ultimate.allocInit(56, 73);call #Ultimate.allocInit(58, 74);call #Ultimate.allocInit(58, 75);call #Ultimate.allocInit(58, 76);call #Ultimate.allocInit(54, 77);call #Ultimate.allocInit(56, 78);call #Ultimate.allocInit(58, 79);call #Ultimate.allocInit(58, 80);call #Ultimate.allocInit(58, 81);call #Ultimate.allocInit(54, 82);call #Ultimate.allocInit(56, 83);call #Ultimate.allocInit(58, 84);call #Ultimate.allocInit(58, 85);call #Ultimate.allocInit(58, 86);call #Ultimate.allocInit(54, 87);call #Ultimate.allocInit(56, 88);call #Ultimate.allocInit(58, 89);call #Ultimate.allocInit(58, 90);call #Ultimate.allocInit(58, 91);call #Ultimate.allocInit(54, 92);call #Ultimate.allocInit(56, 93);call #Ultimate.allocInit(58, 94);call #Ultimate.allocInit(58, 95);call #Ultimate.allocInit(58, 96);call #Ultimate.allocInit(54, 97);call #Ultimate.allocInit(56, 98);call #Ultimate.allocInit(58, 99);call #Ultimate.allocInit(58, 100);call #Ultimate.allocInit(58, 101);call #Ultimate.allocInit(54, 102);call #Ultimate.allocInit(56, 103);call #Ultimate.allocInit(58, 104);call #Ultimate.allocInit(58, 105);call #Ultimate.allocInit(58, 106);call #Ultimate.allocInit(54, 107);call #Ultimate.allocInit(56, 108);call #Ultimate.allocInit(58, 109);call #Ultimate.allocInit(58, 110);call #Ultimate.allocInit(58, 111);call #Ultimate.allocInit(54, 112);call #Ultimate.allocInit(56, 113);call #Ultimate.allocInit(58, 114);call #Ultimate.allocInit(58, 115);call #Ultimate.allocInit(58, 116);call #Ultimate.allocInit(57, 117);call #Ultimate.allocInit(57, 118);call #Ultimate.allocInit(57, 119);call #Ultimate.allocInit(57, 120);call #Ultimate.allocInit(57, 121);call #Ultimate.allocInit(57, 122);call #Ultimate.allocInit(57, 123);call #Ultimate.allocInit(57, 124);call #Ultimate.allocInit(57, 125);call #Ultimate.allocInit(57, 126);call #Ultimate.allocInit(57, 127);call #Ultimate.allocInit(57, 128);call #Ultimate.allocInit(2, 129);call write~init~int(48, 129, 0, 1);call write~init~int(0, 129, 1, 1);call #Ultimate.allocInit(80, 130);~#hp100_pci_tbl~0.base, ~#hp100_pci_tbl~0.offset := 131, 0;call #Ultimate.allocInit(224, 131);call write~init~int(4156, ~#hp100_pci_tbl~0.base, ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4144, ~#hp100_pci_tbl~0.base, 4 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 8 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 12 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 16 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 20 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 24 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4156, ~#hp100_pci_tbl~0.base, 32 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4145, ~#hp100_pci_tbl~0.base, 36 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 40 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 44 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 48 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 52 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 56 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4156, ~#hp100_pci_tbl~0.base, 64 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4162, ~#hp100_pci_tbl~0.base, 68 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 72 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 76 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 80 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 84 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 88 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4156, ~#hp100_pci_tbl~0.base, 96 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4160, ~#hp100_pci_tbl~0.base, 100 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 104 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 108 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 112 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 116 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 120 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4598, ~#hp100_pci_tbl~0.base, 128 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(274, ~#hp100_pci_tbl~0.base, 132 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 136 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 140 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 144 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 148 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 152 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(4122, ~#hp100_pci_tbl~0.base, 160 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(5, ~#hp100_pci_tbl~0.base, 164 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 168 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#hp100_pci_tbl~0.base, 172 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 176 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 180 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 184 + ~#hp100_pci_tbl~0.offset, 8);call write~init~int(0, ~#hp100_pci_tbl~0.base, 192 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 196 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 200 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 204 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 208 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 212 + ~#hp100_pci_tbl~0.offset, 4);call write~init~int(0, ~#hp100_pci_tbl~0.base, 216 + ~#hp100_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~hp100_rx_ratio~0 := 75;~hp100_priority_tx~0 := 0;~hp100_mode~0 := 1;~#hp100_bm_netdev_ops~0.base, ~#hp100_bm_netdev_ops~0.offset := 132, 0;call #Ultimate.allocInit(472, 132);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 8 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_open.base, #funAddr~hp100_open.offset, ~#hp100_bm_netdev_ops~0.base, 16 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_close.base, #funAddr~hp100_close.offset, ~#hp100_bm_netdev_ops~0.base, 24 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_start_xmit_bm.base, #funAddr~hp100_start_xmit_bm.offset, ~#hp100_bm_netdev_ops~0.base, 32 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 40 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 48 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_set_multicast_list.base, #funAddr~hp100_set_multicast_list.offset, ~#hp100_bm_netdev_ops~0.base, 56 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset, ~#hp100_bm_netdev_ops~0.base, 64 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset, ~#hp100_bm_netdev_ops~0.base, 72 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 80 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 88 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset, ~#hp100_bm_netdev_ops~0.base, 96 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 104 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 112 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 120 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_get_stats.base, #funAddr~hp100_get_stats.offset, ~#hp100_bm_netdev_ops~0.base, 128 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 136 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 144 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 152 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 160 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 168 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 176 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 184 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 192 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 200 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 208 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 216 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 224 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 232 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 240 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 248 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 256 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 264 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 272 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 280 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 288 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 296 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 304 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 312 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 320 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 328 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 336 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 344 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 352 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 360 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 368 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 376 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 384 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 392 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 400 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 408 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 416 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 424 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 432 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 440 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 448 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 456 + ~#hp100_bm_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_bm_netdev_ops~0.base, 464 + ~#hp100_bm_netdev_ops~0.offset, 8);~#hp100_netdev_ops~0.base, ~#hp100_netdev_ops~0.offset := 133, 0;call #Ultimate.allocInit(472, 133);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 8 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_open.base, #funAddr~hp100_open.offset, ~#hp100_netdev_ops~0.base, 16 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_close.base, #funAddr~hp100_close.offset, ~#hp100_netdev_ops~0.base, 24 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_start_xmit.base, #funAddr~hp100_start_xmit.offset, ~#hp100_netdev_ops~0.base, 32 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 40 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 48 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_set_multicast_list.base, #funAddr~hp100_set_multicast_list.offset, ~#hp100_netdev_ops~0.base, 56 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset, ~#hp100_netdev_ops~0.base, 64 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset, ~#hp100_netdev_ops~0.base, 72 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 80 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 88 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset, ~#hp100_netdev_ops~0.base, 96 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 104 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 112 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 120 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_get_stats.base, #funAddr~hp100_get_stats.offset, ~#hp100_netdev_ops~0.base, 128 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 136 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 144 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 152 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 160 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 168 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 176 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 184 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 192 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 200 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 208 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 216 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 224 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 232 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 240 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 248 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 256 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 264 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 272 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 280 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 288 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 296 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 304 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 312 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 320 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 328 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 336 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 344 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 352 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 360 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 368 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 376 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 384 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 392 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 400 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 408 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 416 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 424 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 432 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 440 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 448 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 456 + ~#hp100_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_netdev_ops~0.base, 464 + ~#hp100_netdev_ops~0.offset, 8);~#hp100_pci_driver~0.base, ~#hp100_pci_driver~0.offset := 134, 0;call #Ultimate.allocInit(301, 134);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 8 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(54, 0, ~#hp100_pci_driver~0.base, 16 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(~#hp100_pci_tbl~0.base, ~#hp100_pci_tbl~0.offset, ~#hp100_pci_driver~0.base, 24 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_pci_probe.base, #funAddr~hp100_pci_probe.offset, ~#hp100_pci_driver~0.base, 32 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~hp100_pci_remove.base, #funAddr~hp100_pci_remove.offset, ~#hp100_pci_driver~0.base, 40 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 48 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 56 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 64 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 72 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 80 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 88 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 96 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 104 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 112 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 120 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 128 + ~#hp100_pci_driver~0.offset, 8);call write~init~int(0, ~#hp100_pci_driver~0.base, 136 + ~#hp100_pci_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 137 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 145 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 153 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 161 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 169 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 177 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 185 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 193 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 201 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 209 + ~#hp100_pci_driver~0.offset, 8);call write~init~int(0, ~#hp100_pci_driver~0.base, 217 + ~#hp100_pci_driver~0.offset, 4);call write~init~int(0, ~#hp100_pci_driver~0.base, 221 + ~#hp100_pci_driver~0.offset, 4);call write~init~int(0, ~#hp100_pci_driver~0.base, 225 + ~#hp100_pci_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 229 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 237 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 245 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 253 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 261 + ~#hp100_pci_driver~0.offset, 8);call write~init~int(0, ~#hp100_pci_driver~0.base, 269 + ~#hp100_pci_driver~0.offset, 4);call write~init~int(0, ~#hp100_pci_driver~0.base, 273 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 285 + ~#hp100_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#hp100_pci_driver~0.base, 293 + ~#hp100_pci_driver~0.offset, 8);~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset := 0, 0;~ldv_0_line_line~0 := 0;~ldv_0_ret_val_default~0 := 0;~ldv_0_thread_thread~0.base, ~ldv_0_thread_thread~0.offset := 0, 0;~ldv_11_ret_default~0 := 0;~ldv_1_container_net_device~0.base, ~ldv_1_container_net_device~0.offset := 0, 0;~ldv_1_container_struct_sk_buff_ptr~0.base, ~ldv_1_container_struct_sk_buff_ptr~0.offset := 0, 0;~ldv_1_ldv_param_3_1_default~0 := 0;~ldv_2_container_pci_driver~0.base, ~ldv_2_container_pci_driver~0.offset := 0, 0;~ldv_2_resource_dev~0.base, ~ldv_2_resource_dev~0.offset := 0, 0;~#ldv_2_resource_pm_message~0.base, ~#ldv_2_resource_pm_message~0.offset := 135, 0;call #Ultimate.allocInit(4, 135);call write~init~int(0, ~#ldv_2_resource_pm_message~0.base, ~#ldv_2_resource_pm_message~0.offset, 4);~ldv_2_resource_struct_pci_device_id_ptr~0.base, ~ldv_2_resource_struct_pci_device_id_ptr~0.offset := 0, 0;~ldv_2_ret_default~0 := 0;~ldv_statevar_0~0 := 0;~ldv_statevar_1~0 := 0;~ldv_statevar_11~0 := 0;~ldv_statevar_2~0 := 0;~ldv_0_callback_handler~0.base, ~ldv_0_callback_handler~0.offset := #funAddr~hp100_interrupt.base, #funAddr~hp100_interrupt.offset;~ldv_11_exit_hp100_module_exit_default~0.base, ~ldv_11_exit_hp100_module_exit_default~0.offset := #funAddr~hp100_module_exit.base, #funAddr~hp100_module_exit.offset;~ldv_11_init_hp100_module_init_default~0.base, ~ldv_11_init_hp100_module_init_default~0.offset := #funAddr~hp100_module_init.base, #funAddr~hp100_module_init.offset;~ldv_1_callback_ndo_change_mtu~0.base, ~ldv_1_callback_ndo_change_mtu~0.offset := #funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset;~ldv_1_callback_ndo_get_stats~0.base, ~ldv_1_callback_ndo_get_stats~0.offset := #funAddr~hp100_get_stats.base, #funAddr~hp100_get_stats.offset;~ldv_1_callback_ndo_set_mac_address~0.base, ~ldv_1_callback_ndo_set_mac_address~0.offset := #funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset;~ldv_1_callback_ndo_set_rx_mode~0.base, ~ldv_1_callback_ndo_set_rx_mode~0.offset := #funAddr~hp100_set_multicast_list.base, #funAddr~hp100_set_multicast_list.offset;~ldv_1_callback_ndo_start_xmit~0.base, ~ldv_1_callback_ndo_start_xmit~0.offset := #funAddr~hp100_start_xmit_bm.base, #funAddr~hp100_start_xmit_bm.offset;~ldv_1_callback_ndo_validate_addr~0.base, ~ldv_1_callback_ndo_validate_addr~0.offset := #funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_hp100_private~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1; {21481#true} is VALID [2022-02-20 22:38:25,165 INFO L290 TraceCheckUtils]: 1: Hoare triple {21481#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret769#1, main_~tmp~59#1;havoc main_~tmp~59#1;assume { :begin_inline_ldv_initialize } true; {21481#true} is VALID [2022-02-20 22:38:25,165 INFO L290 TraceCheckUtils]: 2: Hoare triple {21481#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_initialize_external_data } true;assume { :begin_inline_ldv_allocate_external_0 } true;havoc ldv_allocate_external_0_#t~ret757#1.base, ldv_allocate_external_0_#t~ret757#1.offset, ldv_allocate_external_0_#t~ret758#1.base, ldv_allocate_external_0_#t~ret758#1.offset, ldv_allocate_external_0_#t~ret759#1.base, ldv_allocate_external_0_#t~ret759#1.offset, ldv_allocate_external_0_#t~ret760#1.base, ldv_allocate_external_0_#t~ret760#1.offset; {21481#true} is VALID [2022-02-20 22:38:25,166 INFO L272 TraceCheckUtils]: 3: Hoare triple {21481#true} call ldv_allocate_external_0_#t~ret757#1.base, ldv_allocate_external_0_#t~ret757#1.offset := ldv_malloc(0); {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:38:25,166 INFO L290 TraceCheckUtils]: 4: Hoare triple {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {21481#true} is VALID [2022-02-20 22:38:25,166 INFO L272 TraceCheckUtils]: 5: Hoare triple {21481#true} call #t~ret868 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:25,166 INFO L290 TraceCheckUtils]: 6: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,166 INFO L290 TraceCheckUtils]: 7: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,167 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:25,167 INFO L290 TraceCheckUtils]: 9: Hoare triple {21481#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {21481#true} is VALID [2022-02-20 22:38:25,167 INFO L290 TraceCheckUtils]: 10: Hoare triple {21481#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {21481#true} is VALID [2022-02-20 22:38:25,167 INFO L290 TraceCheckUtils]: 11: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,167 INFO L284 TraceCheckUtils]: 12: Hoare quadruple {21481#true} {21481#true} #4324#return; {21481#true} is VALID [2022-02-20 22:38:25,167 INFO L290 TraceCheckUtils]: 13: Hoare triple {21481#true} ~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset := ldv_allocate_external_0_#t~ret757#1.base, ldv_allocate_external_0_#t~ret757#1.offset;havoc ldv_allocate_external_0_#t~ret757#1.base, ldv_allocate_external_0_#t~ret757#1.offset;~ldv_0_thread_thread~0.base, ~ldv_0_thread_thread~0.offset := 0, 0; {21481#true} is VALID [2022-02-20 22:38:25,168 INFO L272 TraceCheckUtils]: 14: Hoare triple {21481#true} call ldv_allocate_external_0_#t~ret758#1.base, ldv_allocate_external_0_#t~ret758#1.offset := ldv_malloc(3027); {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:38:25,168 INFO L290 TraceCheckUtils]: 15: Hoare triple {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {21481#true} is VALID [2022-02-20 22:38:25,168 INFO L272 TraceCheckUtils]: 16: Hoare triple {21481#true} call #t~ret868 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:25,168 INFO L290 TraceCheckUtils]: 17: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,168 INFO L290 TraceCheckUtils]: 18: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,169 INFO L284 TraceCheckUtils]: 19: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:25,169 INFO L290 TraceCheckUtils]: 20: Hoare triple {21481#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {21481#true} is VALID [2022-02-20 22:38:25,169 INFO L290 TraceCheckUtils]: 21: Hoare triple {21481#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {21481#true} is VALID [2022-02-20 22:38:25,169 INFO L290 TraceCheckUtils]: 22: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,169 INFO L284 TraceCheckUtils]: 23: Hoare quadruple {21481#true} {21481#true} #4326#return; {21481#true} is VALID [2022-02-20 22:38:25,169 INFO L290 TraceCheckUtils]: 24: Hoare triple {21481#true} ~ldv_1_container_net_device~0.base, ~ldv_1_container_net_device~0.offset := ldv_allocate_external_0_#t~ret758#1.base, ldv_allocate_external_0_#t~ret758#1.offset;havoc ldv_allocate_external_0_#t~ret758#1.base, ldv_allocate_external_0_#t~ret758#1.offset; {21481#true} is VALID [2022-02-20 22:38:25,170 INFO L272 TraceCheckUtils]: 25: Hoare triple {21481#true} call ldv_allocate_external_0_#t~ret759#1.base, ldv_allocate_external_0_#t~ret759#1.offset := ldv_malloc(245); {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:38:25,170 INFO L290 TraceCheckUtils]: 26: Hoare triple {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {21481#true} is VALID [2022-02-20 22:38:25,170 INFO L272 TraceCheckUtils]: 27: Hoare triple {21481#true} call #t~ret868 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:25,170 INFO L290 TraceCheckUtils]: 28: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,170 INFO L290 TraceCheckUtils]: 29: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,170 INFO L284 TraceCheckUtils]: 30: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:25,171 INFO L290 TraceCheckUtils]: 31: Hoare triple {21481#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {21481#true} is VALID [2022-02-20 22:38:25,171 INFO L290 TraceCheckUtils]: 32: Hoare triple {21481#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {21481#true} is VALID [2022-02-20 22:38:25,171 INFO L290 TraceCheckUtils]: 33: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,171 INFO L284 TraceCheckUtils]: 34: Hoare quadruple {21481#true} {21481#true} #4328#return; {21481#true} is VALID [2022-02-20 22:38:25,171 INFO L290 TraceCheckUtils]: 35: Hoare triple {21481#true} ~ldv_1_container_struct_sk_buff_ptr~0.base, ~ldv_1_container_struct_sk_buff_ptr~0.offset := ldv_allocate_external_0_#t~ret759#1.base, ldv_allocate_external_0_#t~ret759#1.offset;havoc ldv_allocate_external_0_#t~ret759#1.base, ldv_allocate_external_0_#t~ret759#1.offset; {21481#true} is VALID [2022-02-20 22:38:25,172 INFO L272 TraceCheckUtils]: 36: Hoare triple {21481#true} call ldv_allocate_external_0_#t~ret760#1.base, ldv_allocate_external_0_#t~ret760#1.offset := ldv_malloc(3018); {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:38:25,172 INFO L290 TraceCheckUtils]: 37: Hoare triple {21599#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~87.base, ~tmp~87.offset;havoc ~tmp___0~40;havoc ~tmp___1~23; {21481#true} is VALID [2022-02-20 22:38:25,172 INFO L272 TraceCheckUtils]: 38: Hoare triple {21481#true} call #t~ret868 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:25,172 INFO L290 TraceCheckUtils]: 39: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,172 INFO L290 TraceCheckUtils]: 40: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,172 INFO L284 TraceCheckUtils]: 41: Hoare quadruple {21481#true} {21481#true} #3758#return; {21481#true} is VALID [2022-02-20 22:38:25,173 INFO L290 TraceCheckUtils]: 42: Hoare triple {21481#true} assume -2147483648 <= #t~ret868 && #t~ret868 <= 2147483647;~tmp___1~23 := #t~ret868;havoc #t~ret868; {21481#true} is VALID [2022-02-20 22:38:25,173 INFO L290 TraceCheckUtils]: 43: Hoare triple {21481#true} assume !(0 != ~tmp___1~23);#res.base, #res.offset := 0, 0; {21481#true} is VALID [2022-02-20 22:38:25,173 INFO L290 TraceCheckUtils]: 44: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,173 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {21481#true} {21481#true} #4330#return; {21481#true} is VALID [2022-02-20 22:38:25,173 INFO L290 TraceCheckUtils]: 46: Hoare triple {21481#true} ~ldv_2_resource_dev~0.base, ~ldv_2_resource_dev~0.offset := ldv_allocate_external_0_#t~ret760#1.base, ldv_allocate_external_0_#t~ret760#1.offset;havoc ldv_allocate_external_0_#t~ret760#1.base, ldv_allocate_external_0_#t~ret760#1.offset; {21481#true} is VALID [2022-02-20 22:38:25,173 INFO L290 TraceCheckUtils]: 47: Hoare triple {21481#true} assume { :end_inline_ldv_allocate_external_0 } true; {21481#true} is VALID [2022-02-20 22:38:25,174 INFO L290 TraceCheckUtils]: 48: Hoare triple {21481#true} assume { :end_inline_ldv_initialize_external_data } true;~ldv_statevar_11~0 := 7;~ldv_statevar_0~0 := 6;~ldv_statevar_1~0 := 5;~ldv_2_ret_default~0 := 1;~ldv_statevar_2~0 := 20; {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,174 INFO L272 TraceCheckUtils]: 49: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} call main_#t~ret769#1 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:25,174 INFO L290 TraceCheckUtils]: 50: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,174 INFO L290 TraceCheckUtils]: 51: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,175 INFO L284 TraceCheckUtils]: 52: Hoare quadruple {21481#true} {21519#(= 20 ~ldv_statevar_2~0)} #4332#return; {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,175 INFO L290 TraceCheckUtils]: 53: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume -2147483648 <= main_#t~ret769#1 && main_#t~ret769#1 <= 2147483647;main_~tmp~59#1 := main_#t~ret769#1;havoc main_#t~ret769#1; {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,175 INFO L290 TraceCheckUtils]: 54: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume !(0 == main_~tmp~59#1); {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,176 INFO L290 TraceCheckUtils]: 55: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume !(1 == main_~tmp~59#1); {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,176 INFO L290 TraceCheckUtils]: 56: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume !(2 == main_~tmp~59#1); {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,176 INFO L290 TraceCheckUtils]: 57: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume 3 == main_~tmp~59#1; {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,177 INFO L290 TraceCheckUtils]: 58: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume { :begin_inline_ldv_pci_pci_instance_2 } true;ldv_pci_pci_instance_2_#in~arg0#1.base, ldv_pci_pci_instance_2_#in~arg0#1.offset := 0, 0;havoc ldv_pci_pci_instance_2_#t~ret793#1, ldv_pci_pci_instance_2_#t~mem794#1.base, ldv_pci_pci_instance_2_#t~mem794#1.offset, ldv_pci_pci_instance_2_#t~mem795#1.base, ldv_pci_pci_instance_2_#t~mem795#1.offset, ldv_pci_pci_instance_2_#t~mem796#1.base, ldv_pci_pci_instance_2_#t~mem796#1.offset, ldv_pci_pci_instance_2_#t~ret797#1, ldv_pci_pci_instance_2_#t~mem798#1.base, ldv_pci_pci_instance_2_#t~mem798#1.offset, ldv_pci_pci_instance_2_#t~mem799#1.base, ldv_pci_pci_instance_2_#t~mem799#1.offset, ldv_pci_pci_instance_2_#t~mem800#1.base, ldv_pci_pci_instance_2_#t~mem800#1.offset, ldv_pci_pci_instance_2_#t~mem801#1.base, ldv_pci_pci_instance_2_#t~mem801#1.offset, ldv_pci_pci_instance_2_#t~mem802#1.base, ldv_pci_pci_instance_2_#t~mem802#1.offset, ldv_pci_pci_instance_2_#t~mem803#1.base, ldv_pci_pci_instance_2_#t~mem803#1.offset, ldv_pci_pci_instance_2_#t~mem804#1, ldv_pci_pci_instance_2_#t~ret805#1, ldv_pci_pci_instance_2_#t~ret806#1, ldv_pci_pci_instance_2_#t~mem807#1.base, ldv_pci_pci_instance_2_#t~mem807#1.offset, ldv_pci_pci_instance_2_#t~mem808#1.base, ldv_pci_pci_instance_2_#t~mem808#1.offset, ldv_pci_pci_instance_2_#t~mem809#1, ldv_pci_pci_instance_2_#t~ret810#1, ldv_pci_pci_instance_2_#t~ret811#1, ldv_pci_pci_instance_2_#t~ret812#1, ldv_pci_pci_instance_2_#t~ret813#1, ldv_pci_pci_instance_2_#t~ret814#1, ldv_pci_pci_instance_2_#t~mem815#1.base, ldv_pci_pci_instance_2_#t~mem815#1.offset, ldv_pci_pci_instance_2_#t~ret816#1, ldv_pci_pci_instance_2_#t~ret817#1, ldv_pci_pci_instance_2_#t~ret818#1, ldv_pci_pci_instance_2_#t~ret819#1.base, ldv_pci_pci_instance_2_#t~ret819#1.offset, ldv_pci_pci_instance_2_#t~ret820#1.base, ldv_pci_pci_instance_2_#t~ret820#1.offset, ldv_pci_pci_instance_2_#t~ret821#1, ldv_pci_pci_instance_2_~arg0#1.base, ldv_pci_pci_instance_2_~arg0#1.offset, ldv_pci_pci_instance_2_~tmp~66#1, ldv_pci_pci_instance_2_~tmp___0~33#1, ldv_pci_pci_instance_2_~tmp___1~22#1, ldv_pci_pci_instance_2_~tmp___2~14#1.base, ldv_pci_pci_instance_2_~tmp___2~14#1.offset, ldv_pci_pci_instance_2_~tmp___3~10#1.base, ldv_pci_pci_instance_2_~tmp___3~10#1.offset, ldv_pci_pci_instance_2_~tmp___4~8#1;ldv_pci_pci_instance_2_~arg0#1.base, ldv_pci_pci_instance_2_~arg0#1.offset := ldv_pci_pci_instance_2_#in~arg0#1.base, ldv_pci_pci_instance_2_#in~arg0#1.offset;havoc ldv_pci_pci_instance_2_~tmp~66#1;havoc ldv_pci_pci_instance_2_~tmp___0~33#1;havoc ldv_pci_pci_instance_2_~tmp___1~22#1;havoc ldv_pci_pci_instance_2_~tmp___2~14#1.base, ldv_pci_pci_instance_2_~tmp___2~14#1.offset;havoc ldv_pci_pci_instance_2_~tmp___3~10#1.base, ldv_pci_pci_instance_2_~tmp___3~10#1.offset;havoc ldv_pci_pci_instance_2_~tmp___4~8#1; {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,177 INFO L290 TraceCheckUtils]: 59: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume !(1 == ~ldv_statevar_2~0); {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,177 INFO L290 TraceCheckUtils]: 60: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume !(2 == ~ldv_statevar_2~0); {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,177 INFO L290 TraceCheckUtils]: 61: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume !(3 == ~ldv_statevar_2~0); {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,178 INFO L290 TraceCheckUtils]: 62: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume !(4 == ~ldv_statevar_2~0); {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,178 INFO L290 TraceCheckUtils]: 63: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume !(5 == ~ldv_statevar_2~0); {21519#(= 20 ~ldv_statevar_2~0)} is VALID [2022-02-20 22:38:25,178 INFO L290 TraceCheckUtils]: 64: Hoare triple {21519#(= 20 ~ldv_statevar_2~0)} assume 6 == ~ldv_statevar_2~0; {21482#false} is VALID [2022-02-20 22:38:25,179 INFO L290 TraceCheckUtils]: 65: Hoare triple {21482#false} call ldv_pci_pci_instance_2_#t~mem800#1.base, ldv_pci_pci_instance_2_#t~mem800#1.offset := read~$Pointer$(~ldv_2_container_pci_driver~0.base, 64 + ~ldv_2_container_pci_driver~0.offset, 8); {21482#false} is VALID [2022-02-20 22:38:25,179 INFO L290 TraceCheckUtils]: 66: Hoare triple {21482#false} assume 0 != (ldv_pci_pci_instance_2_#t~mem800#1.base + ldv_pci_pci_instance_2_#t~mem800#1.offset) % 18446744073709551616;havoc ldv_pci_pci_instance_2_#t~mem800#1.base, ldv_pci_pci_instance_2_#t~mem800#1.offset;call ldv_pci_pci_instance_2_#t~mem801#1.base, ldv_pci_pci_instance_2_#t~mem801#1.offset := read~$Pointer$(~ldv_2_container_pci_driver~0.base, 64 + ~ldv_2_container_pci_driver~0.offset, 8);assume { :begin_inline_ldv_pci_instance_resume_early_2_6 } true;ldv_pci_instance_resume_early_2_6_#in~arg0#1.base, ldv_pci_instance_resume_early_2_6_#in~arg0#1.offset, ldv_pci_instance_resume_early_2_6_#in~arg1#1.base, ldv_pci_instance_resume_early_2_6_#in~arg1#1.offset := ldv_pci_pci_instance_2_#t~mem801#1.base, ldv_pci_pci_instance_2_#t~mem801#1.offset, ~ldv_2_resource_dev~0.base, ~ldv_2_resource_dev~0.offset;havoc ldv_pci_instance_resume_early_2_6_#t~ret783#1, ldv_pci_instance_resume_early_2_6_~arg0#1.base, ldv_pci_instance_resume_early_2_6_~arg0#1.offset, ldv_pci_instance_resume_early_2_6_~arg1#1.base, ldv_pci_instance_resume_early_2_6_~arg1#1.offset;ldv_pci_instance_resume_early_2_6_~arg0#1.base, ldv_pci_instance_resume_early_2_6_~arg0#1.offset := ldv_pci_instance_resume_early_2_6_#in~arg0#1.base, ldv_pci_instance_resume_early_2_6_#in~arg0#1.offset;ldv_pci_instance_resume_early_2_6_~arg1#1.base, ldv_pci_instance_resume_early_2_6_~arg1#1.offset := ldv_pci_instance_resume_early_2_6_#in~arg1#1.base, ldv_pci_instance_resume_early_2_6_#in~arg1#1.offset; {21482#false} is VALID [2022-02-20 22:38:25,179 INFO L272 TraceCheckUtils]: 67: Hoare triple {21482#false} call ldv_pci_instance_resume_early_2_6_#t~ret783#1 := ##fun~$Pointer$~TO~int(ldv_pci_instance_resume_early_2_6_~arg1#1.base, ldv_pci_instance_resume_early_2_6_~arg1#1.offset, ldv_pci_instance_resume_early_2_6_~arg0#1.base, ldv_pci_instance_resume_early_2_6_~arg0#1.offset); {21612#(and (= |old(#length)| |#length|) (= ~ldv_0_callback_handler~0.offset |old(~ldv_0_callback_handler~0.offset)|) (= |old(abs_6727)| abs_6727) (= |old(~ldv_0_thread_thread~0.base)| ~ldv_0_thread_thread~0.base) (= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0) (= |old(abs_8416)| abs_8416) (= |old(~ldv_0_thread_thread~0.offset)| ~ldv_0_thread_thread~0.offset) (= |#memory_int| |old(#memory_int)|) (= |old(~ldv_0_data_data~0.base)| ~ldv_0_data_data~0.base) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|) (= |old(abs_6728)| abs_6728) (= ~ldv_0_data_data~0.offset |old(~ldv_0_data_data~0.offset)|) (= ~ldv_0_callback_handler~0.base |old(~ldv_0_callback_handler~0.base)|) (= |old(abs_6733)| abs_6733) (= ~ldv_0_line_line~0 |old(~ldv_0_line_line~0)|) (= |old(#valid)| |#valid|) (= |old(abs_8415)| abs_8415) (= ~ldv_statevar_0~0 |old(~ldv_statevar_0~0)|))} is VALID [2022-02-20 22:38:25,179 INFO L290 TraceCheckUtils]: 68: Hoare triple {21612#(and (= |old(#length)| |#length|) (= ~ldv_0_callback_handler~0.offset |old(~ldv_0_callback_handler~0.offset)|) (= |old(abs_6727)| abs_6727) (= |old(~ldv_0_thread_thread~0.base)| ~ldv_0_thread_thread~0.base) (= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0) (= |old(abs_8416)| abs_8416) (= |old(~ldv_0_thread_thread~0.offset)| ~ldv_0_thread_thread~0.offset) (= |#memory_int| |old(#memory_int)|) (= |old(~ldv_0_data_data~0.base)| ~ldv_0_data_data~0.base) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|) (= |old(abs_6728)| abs_6728) (= ~ldv_0_data_data~0.offset |old(~ldv_0_data_data~0.offset)|) (= ~ldv_0_callback_handler~0.base |old(~ldv_0_callback_handler~0.base)|) (= |old(abs_6733)| abs_6733) (= ~ldv_0_line_line~0 |old(~ldv_0_line_line~0)|) (= |old(#valid)| |#valid|) (= |old(abs_8415)| abs_8415) (= ~ldv_statevar_0~0 |old(~ldv_statevar_0~0)|))} #~782.base, #~782.offset := #in~782.base, #in~782.offset; {21481#true} is VALID [2022-02-20 22:38:25,179 INFO L290 TraceCheckUtils]: 69: Hoare triple {21481#true} assume !(#in~#fp.base == #funAddr~eth_validate_addr.base && #in~#fp.offset == #funAddr~eth_validate_addr.offset); {21481#true} is VALID [2022-02-20 22:38:25,179 INFO L290 TraceCheckUtils]: 70: Hoare triple {21481#true} assume !(#in~#fp.base == #funAddr~hp100_close.base && #in~#fp.offset == #funAddr~hp100_close.offset); {21481#true} is VALID [2022-02-20 22:38:25,181 INFO L272 TraceCheckUtils]: 71: Hoare triple {21481#true} call #t~ret975 := hp100_open(#~782.base, #~782.offset); {21612#(and (= |old(#length)| |#length|) (= ~ldv_0_callback_handler~0.offset |old(~ldv_0_callback_handler~0.offset)|) (= |old(abs_6727)| abs_6727) (= |old(~ldv_0_thread_thread~0.base)| ~ldv_0_thread_thread~0.base) (= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0) (= |old(abs_8416)| abs_8416) (= |old(~ldv_0_thread_thread~0.offset)| ~ldv_0_thread_thread~0.offset) (= |#memory_int| |old(#memory_int)|) (= |old(~ldv_0_data_data~0.base)| ~ldv_0_data_data~0.base) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|) (= |old(abs_6728)| abs_6728) (= ~ldv_0_data_data~0.offset |old(~ldv_0_data_data~0.offset)|) (= ~ldv_0_callback_handler~0.base |old(~ldv_0_callback_handler~0.base)|) (= |old(abs_6733)| abs_6733) (= ~ldv_0_line_line~0 |old(~ldv_0_line_line~0)|) (= |old(#valid)| |#valid|) (= |old(abs_8415)| abs_8415) (= ~ldv_statevar_0~0 |old(~ldv_statevar_0~0)|))} is VALID [2022-02-20 22:38:25,181 INFO L290 TraceCheckUtils]: 72: Hoare triple {21612#(and (= |old(#length)| |#length|) (= ~ldv_0_callback_handler~0.offset |old(~ldv_0_callback_handler~0.offset)|) (= |old(abs_6727)| abs_6727) (= |old(~ldv_0_thread_thread~0.base)| ~ldv_0_thread_thread~0.base) (= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0) (= |old(abs_8416)| abs_8416) (= |old(~ldv_0_thread_thread~0.offset)| ~ldv_0_thread_thread~0.offset) (= |#memory_int| |old(#memory_int)|) (= |old(~ldv_0_data_data~0.base)| ~ldv_0_data_data~0.base) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|) (= |old(abs_6728)| abs_6728) (= ~ldv_0_data_data~0.offset |old(~ldv_0_data_data~0.offset)|) (= ~ldv_0_callback_handler~0.base |old(~ldv_0_callback_handler~0.base)|) (= |old(abs_6733)| abs_6733) (= ~ldv_0_line_line~0 |old(~ldv_0_line_line~0)|) (= |old(#valid)| |#valid|) (= |old(abs_8415)| abs_8415) (= ~ldv_statevar_0~0 |old(~ldv_statevar_0~0)|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~lp~4#1.base, ~lp~4#1.offset;havoc ~tmp~27#1.base, ~tmp~27#1.offset;havoc ~tmp___0~9#1;havoc ~tmp___1~6#1; {21481#true} is VALID [2022-02-20 22:38:25,181 INFO L272 TraceCheckUtils]: 73: Hoare triple {21481#true} call #t~ret341#1.base, #t~ret341#1.offset := netdev_priv(~dev#1.base, ~dev#1.offset); {21481#true} is VALID [2022-02-20 22:38:25,181 INFO L290 TraceCheckUtils]: 74: Hoare triple {21481#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21481#true} is VALID [2022-02-20 22:38:25,181 INFO L290 TraceCheckUtils]: 75: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,181 INFO L284 TraceCheckUtils]: 76: Hoare quadruple {21481#true} {21481#true} #4078#return; {21481#true} is VALID [2022-02-20 22:38:25,182 INFO L290 TraceCheckUtils]: 77: Hoare triple {21481#true} ~tmp~27#1.base, ~tmp~27#1.offset := #t~ret341#1.base, #t~ret341#1.offset;havoc #t~ret341#1.base, #t~ret341#1.offset;~lp~4#1.base, ~lp~4#1.offset := ~tmp~27#1.base, ~tmp~27#1.offset;call #t~mem342#1 := read~int(~dev#1.base, 64 + ~dev#1.offset, 4);call #t~mem343#1 := read~int(~lp~4#1.base, 94 + ~lp~4#1.offset, 1); {21481#true} is VALID [2022-02-20 22:38:25,182 INFO L290 TraceCheckUtils]: 78: Hoare triple {21481#true} assume (#t~mem343#1 % 256 - 1) % 4294967296 <= 1;#t~ite344#1 := 128; {21481#true} is VALID [2022-02-20 22:38:25,182 INFO L290 TraceCheckUtils]: 79: Hoare triple {21481#true} assume { :begin_inline_ldv_request_irq_86 } true;ldv_request_irq_86_#in~irq#1, ldv_request_irq_86_#in~handler#1.base, ldv_request_irq_86_#in~handler#1.offset, ldv_request_irq_86_#in~flags#1, ldv_request_irq_86_#in~name#1.base, ldv_request_irq_86_#in~name#1.offset, ldv_request_irq_86_#in~dev#1.base, ldv_request_irq_86_#in~dev#1.offset := #t~mem342#1, #funAddr~hp100_interrupt.base, #funAddr~hp100_interrupt.offset, #t~ite344#1, ~dev#1.base, ~dev#1.offset, ~dev#1.base, ~dev#1.offset;havoc ldv_request_irq_86_#res#1;havoc ldv_request_irq_86_#t~ret840#1, ldv_request_irq_86_#t~ret841#1, ldv_request_irq_86_~irq#1, ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset, ldv_request_irq_86_~flags#1, ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset, ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset, ldv_request_irq_86_~ldv_func_res~1#1, ldv_request_irq_86_~tmp~76#1, ldv_request_irq_86_~tmp___0~36#1;ldv_request_irq_86_~irq#1 := ldv_request_irq_86_#in~irq#1;ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset := ldv_request_irq_86_#in~handler#1.base, ldv_request_irq_86_#in~handler#1.offset;ldv_request_irq_86_~flags#1 := ldv_request_irq_86_#in~flags#1;ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset := ldv_request_irq_86_#in~name#1.base, ldv_request_irq_86_#in~name#1.offset;ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset := ldv_request_irq_86_#in~dev#1.base, ldv_request_irq_86_#in~dev#1.offset;havoc ldv_request_irq_86_~ldv_func_res~1#1;havoc ldv_request_irq_86_~tmp~76#1;havoc ldv_request_irq_86_~tmp___0~36#1;assume { :begin_inline_request_irq } true;request_irq_#in~irq#1, request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset, request_irq_#in~flags#1, request_irq_#in~name#1.base, request_irq_#in~name#1.offset, request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset := ldv_request_irq_86_~irq#1, ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset, ldv_request_irq_86_~flags#1, ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset, ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset;havoc request_irq_#res#1;havoc request_irq_#t~ret195#1, request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset, request_irq_~tmp~19#1;request_irq_~irq#1 := request_irq_#in~irq#1;request_irq_~handler#1.base, request_irq_~handler#1.offset := request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset;request_irq_~flags#1 := request_irq_#in~flags#1;request_irq_~name#1.base, request_irq_~name#1.offset := request_irq_#in~name#1.base, request_irq_#in~name#1.offset;request_irq_~dev#1.base, request_irq_~dev#1.offset := request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset;havoc request_irq_~tmp~19#1;assume { :begin_inline_request_threaded_irq } true;request_threaded_irq_#in~arg0#1, request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset, request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset, request_threaded_irq_#in~arg3#1, request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset, request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset := request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, 0, 0, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset;havoc request_threaded_irq_#res#1;havoc request_threaded_irq_#t~nondet965#1, request_threaded_irq_~arg0#1, request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset, request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset, request_threaded_irq_~arg3#1, request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset, request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset;request_threaded_irq_~arg0#1 := request_threaded_irq_#in~arg0#1;request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset := request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset;request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset := request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset;request_threaded_irq_~arg3#1 := request_threaded_irq_#in~arg3#1;request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset := request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset;request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset := request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset;assume -2147483648 <= request_threaded_irq_#t~nondet965#1 && request_threaded_irq_#t~nondet965#1 <= 2147483647;request_threaded_irq_#res#1 := request_threaded_irq_#t~nondet965#1;havoc request_threaded_irq_#t~nondet965#1; {21481#true} is VALID [2022-02-20 22:38:25,182 INFO L290 TraceCheckUtils]: 80: Hoare triple {21481#true} request_irq_#t~ret195#1 := request_threaded_irq_#res#1;assume { :end_inline_request_threaded_irq } true;assume -2147483648 <= request_irq_#t~ret195#1 && request_irq_#t~ret195#1 <= 2147483647;request_irq_~tmp~19#1 := request_irq_#t~ret195#1;havoc request_irq_#t~ret195#1;request_irq_#res#1 := request_irq_~tmp~19#1; {21481#true} is VALID [2022-02-20 22:38:25,182 INFO L290 TraceCheckUtils]: 81: Hoare triple {21481#true} ldv_request_irq_86_#t~ret840#1 := request_irq_#res#1;assume { :end_inline_request_irq } true;assume -2147483648 <= ldv_request_irq_86_#t~ret840#1 && ldv_request_irq_86_#t~ret840#1 <= 2147483647;ldv_request_irq_86_~tmp~76#1 := ldv_request_irq_86_#t~ret840#1;havoc ldv_request_irq_86_#t~ret840#1;ldv_request_irq_86_~ldv_func_res~1#1 := ldv_request_irq_86_~tmp~76#1;assume { :begin_inline_ldv_request_irq } true;ldv_request_irq_#in~arg0#1, ldv_request_irq_#in~arg1#1, ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset, ldv_request_irq_#in~arg3#1, ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset, ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset := ldv_request_irq_86_~ldv_func_res~1#1, ldv_request_irq_86_~irq#1, ldv_request_irq_86_~handler#1.base, ldv_request_irq_86_~handler#1.offset, ldv_request_irq_86_~flags#1, ldv_request_irq_86_~name#1.base, ldv_request_irq_86_~name#1.offset, ldv_request_irq_86_~dev#1.base, ldv_request_irq_86_~dev#1.offset;havoc ldv_request_irq_#res#1;havoc ldv_request_irq_#t~ret829#1, ldv_request_irq_~arg0#1, ldv_request_irq_~arg1#1, ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset, ldv_request_irq_~arg3#1, ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset, ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset, ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset, ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset, ldv_request_irq_~ldv_7_line_line~0#1, ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset, ldv_request_irq_~tmp~69#1;ldv_request_irq_~arg0#1 := ldv_request_irq_#in~arg0#1;ldv_request_irq_~arg1#1 := ldv_request_irq_#in~arg1#1;ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset := ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset;ldv_request_irq_~arg3#1 := ldv_request_irq_#in~arg3#1;ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset := ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset;ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset := ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset;havoc ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset;havoc ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset;havoc ldv_request_irq_~ldv_7_line_line~0#1;havoc ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset;havoc ldv_request_irq_~tmp~69#1; {21481#true} is VALID [2022-02-20 22:38:25,182 INFO L272 TraceCheckUtils]: 82: Hoare triple {21481#true} call ldv_request_irq_#t~ret829#1 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:25,183 INFO L290 TraceCheckUtils]: 83: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,183 INFO L290 TraceCheckUtils]: 84: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,183 INFO L284 TraceCheckUtils]: 85: Hoare quadruple {21481#true} {21481#true} #4080#return; {21481#true} is VALID [2022-02-20 22:38:25,183 INFO L290 TraceCheckUtils]: 86: Hoare triple {21481#true} assume -2147483648 <= ldv_request_irq_#t~ret829#1 && ldv_request_irq_#t~ret829#1 <= 2147483647;ldv_request_irq_~tmp~69#1 := ldv_request_irq_#t~ret829#1;havoc ldv_request_irq_#t~ret829#1; {21481#true} is VALID [2022-02-20 22:38:25,183 INFO L290 TraceCheckUtils]: 87: Hoare triple {21481#true} assume 0 != ldv_request_irq_~tmp~69#1; {21481#true} is VALID [2022-02-20 22:38:25,183 INFO L272 TraceCheckUtils]: 88: Hoare triple {21481#true} call ldv_assume((if 0 == ldv_request_irq_~arg0#1 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,183 INFO L290 TraceCheckUtils]: 89: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,184 INFO L290 TraceCheckUtils]: 90: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,184 INFO L290 TraceCheckUtils]: 91: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,184 INFO L284 TraceCheckUtils]: 92: Hoare quadruple {21481#true} {21481#true} #4082#return; {21481#true} is VALID [2022-02-20 22:38:25,184 INFO L290 TraceCheckUtils]: 93: Hoare triple {21481#true} ldv_request_irq_~ldv_7_line_line~0#1 := (if ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 <= 2147483647 then ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 else ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 - 4294967296);ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset := ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset;ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset := 0, 0;ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset := ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset; {21481#true} is VALID [2022-02-20 22:38:25,184 INFO L272 TraceCheckUtils]: 94: Hoare triple {21481#true} call ldv_assume((if 6 == ~ldv_statevar_0~0 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,184 INFO L290 TraceCheckUtils]: 95: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,184 INFO L290 TraceCheckUtils]: 96: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,185 INFO L290 TraceCheckUtils]: 97: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,185 INFO L284 TraceCheckUtils]: 98: Hoare quadruple {21481#true} {21481#true} #4084#return; {21481#true} is VALID [2022-02-20 22:38:25,185 INFO L290 TraceCheckUtils]: 99: Hoare triple {21481#true} assume { :begin_inline_ldv_dispatch_irq_register_7_2 } true;ldv_dispatch_irq_register_7_2_#in~arg0#1, ldv_dispatch_irq_register_7_2_#in~arg1#1.base, ldv_dispatch_irq_register_7_2_#in~arg1#1.offset, ldv_dispatch_irq_register_7_2_#in~arg2#1.base, ldv_dispatch_irq_register_7_2_#in~arg2#1.offset, ldv_dispatch_irq_register_7_2_#in~arg3#1.base, ldv_dispatch_irq_register_7_2_#in~arg3#1.offset := ldv_request_irq_~ldv_7_line_line~0#1, ldv_request_irq_~ldv_7_callback_handler~0#1.base, ldv_request_irq_~ldv_7_callback_handler~0#1.offset, ldv_request_irq_~ldv_7_thread_thread~0#1.base, ldv_request_irq_~ldv_7_thread_thread~0#1.offset, ldv_request_irq_~ldv_7_data_data~0#1.base, ldv_request_irq_~ldv_7_data_data~0#1.offset;havoc ldv_dispatch_irq_register_7_2_~arg0#1, ldv_dispatch_irq_register_7_2_~arg1#1.base, ldv_dispatch_irq_register_7_2_~arg1#1.offset, ldv_dispatch_irq_register_7_2_~arg2#1.base, ldv_dispatch_irq_register_7_2_~arg2#1.offset, ldv_dispatch_irq_register_7_2_~arg3#1.base, ldv_dispatch_irq_register_7_2_~arg3#1.offset;ldv_dispatch_irq_register_7_2_~arg0#1 := ldv_dispatch_irq_register_7_2_#in~arg0#1;ldv_dispatch_irq_register_7_2_~arg1#1.base, ldv_dispatch_irq_register_7_2_~arg1#1.offset := ldv_dispatch_irq_register_7_2_#in~arg1#1.base, ldv_dispatch_irq_register_7_2_#in~arg1#1.offset;ldv_dispatch_irq_register_7_2_~arg2#1.base, ldv_dispatch_irq_register_7_2_~arg2#1.offset := ldv_dispatch_irq_register_7_2_#in~arg2#1.base, ldv_dispatch_irq_register_7_2_#in~arg2#1.offset;ldv_dispatch_irq_register_7_2_~arg3#1.base, ldv_dispatch_irq_register_7_2_~arg3#1.offset := ldv_dispatch_irq_register_7_2_#in~arg3#1.base, ldv_dispatch_irq_register_7_2_#in~arg3#1.offset;~ldv_0_line_line~0 := ldv_dispatch_irq_register_7_2_~arg0#1;~ldv_0_callback_handler~0.base, ~ldv_0_callback_handler~0.offset := ldv_dispatch_irq_register_7_2_~arg1#1.base, ldv_dispatch_irq_register_7_2_~arg1#1.offset;~ldv_0_thread_thread~0.base, ~ldv_0_thread_thread~0.offset := ldv_dispatch_irq_register_7_2_~arg2#1.base, ldv_dispatch_irq_register_7_2_~arg2#1.offset;~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset := ldv_dispatch_irq_register_7_2_~arg3#1.base, ldv_dispatch_irq_register_7_2_~arg3#1.offset;assume { :begin_inline_ldv_switch_automaton_state_0_6 } true;~ldv_statevar_0~0 := 5; {21481#true} is VALID [2022-02-20 22:38:25,185 INFO L290 TraceCheckUtils]: 100: Hoare triple {21481#true} assume { :end_inline_ldv_switch_automaton_state_0_6 } true; {21481#true} is VALID [2022-02-20 22:38:25,185 INFO L290 TraceCheckUtils]: 101: Hoare triple {21481#true} assume { :end_inline_ldv_dispatch_irq_register_7_2 } true;ldv_request_irq_#res#1 := ldv_request_irq_~arg0#1; {21481#true} is VALID [2022-02-20 22:38:25,185 INFO L290 TraceCheckUtils]: 102: Hoare triple {21481#true} ldv_request_irq_86_#t~ret841#1 := ldv_request_irq_#res#1;assume { :end_inline_ldv_request_irq } true;assume -2147483648 <= ldv_request_irq_86_#t~ret841#1 && ldv_request_irq_86_#t~ret841#1 <= 2147483647;ldv_request_irq_86_~tmp___0~36#1 := ldv_request_irq_86_#t~ret841#1;havoc ldv_request_irq_86_#t~ret841#1;ldv_request_irq_86_#res#1 := ldv_request_irq_86_~tmp___0~36#1; {21481#true} is VALID [2022-02-20 22:38:25,185 INFO L290 TraceCheckUtils]: 103: Hoare triple {21481#true} #t~ret345#1 := ldv_request_irq_86_#res#1;assume { :end_inline_ldv_request_irq_86 } true;assume -2147483648 <= #t~ret345#1 && #t~ret345#1 <= 2147483647;~tmp___0~9#1 := #t~ret345#1;havoc #t~mem342#1;havoc #t~mem343#1;havoc #t~ite344#1;havoc #t~ret345#1; {21481#true} is VALID [2022-02-20 22:38:25,186 INFO L290 TraceCheckUtils]: 104: Hoare triple {21481#true} assume 0 != ~tmp___0~9#1;havoc #t~nondet346#1;call #t~mem347#1 := read~int(~dev#1.base, 64 + ~dev#1.offset, 4);havoc #t~mem347#1;#res#1 := -11; {21481#true} is VALID [2022-02-20 22:38:25,186 INFO L290 TraceCheckUtils]: 105: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,186 INFO L284 TraceCheckUtils]: 106: Hoare quadruple {21481#true} {21481#true} #4120#return; {21481#true} is VALID [2022-02-20 22:38:25,186 INFO L290 TraceCheckUtils]: 107: Hoare triple {21481#true} assume -2147483648 <= #t~ret975 && #t~ret975 <= 2147483647;#t~funptrres974 := #t~ret975; {21481#true} is VALID [2022-02-20 22:38:25,186 INFO L290 TraceCheckUtils]: 108: Hoare triple {21481#true} #res := #t~funptrres974;havoc #t~funptrres974;havoc #t~ret975;havoc #t~ret976;havoc #t~ret977; {21481#true} is VALID [2022-02-20 22:38:25,186 INFO L290 TraceCheckUtils]: 109: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,187 INFO L284 TraceCheckUtils]: 110: Hoare quadruple {21481#true} {21482#false} #4516#return; {21482#false} is VALID [2022-02-20 22:38:25,187 INFO L290 TraceCheckUtils]: 111: Hoare triple {21482#false} assume -2147483648 <= ldv_pci_instance_resume_early_2_6_#t~ret783#1 && ldv_pci_instance_resume_early_2_6_#t~ret783#1 <= 2147483647;havoc ldv_pci_instance_resume_early_2_6_#t~ret783#1; {21482#false} is VALID [2022-02-20 22:38:25,187 INFO L290 TraceCheckUtils]: 112: Hoare triple {21482#false} assume { :end_inline_ldv_pci_instance_resume_early_2_6 } true;havoc ldv_pci_pci_instance_2_#t~mem801#1.base, ldv_pci_pci_instance_2_#t~mem801#1.offset; {21482#false} is VALID [2022-02-20 22:38:25,187 INFO L290 TraceCheckUtils]: 113: Hoare triple {21482#false} ~ldv_statevar_2~0 := 5; {21482#false} is VALID [2022-02-20 22:38:25,187 INFO L290 TraceCheckUtils]: 114: Hoare triple {21482#false} assume { :end_inline_ldv_pci_pci_instance_2 } true; {21482#false} is VALID [2022-02-20 22:38:25,187 INFO L272 TraceCheckUtils]: 115: Hoare triple {21482#false} call main_#t~ret769#1 := ldv_undef_int(); {21481#true} is VALID [2022-02-20 22:38:25,187 INFO L290 TraceCheckUtils]: 116: Hoare triple {21481#true} havoc ~tmp~92;assume -2147483648 <= #t~nondet879 && #t~nondet879 <= 2147483647;~tmp~92 := #t~nondet879;havoc #t~nondet879;#res := ~tmp~92; {21481#true} is VALID [2022-02-20 22:38:25,188 INFO L290 TraceCheckUtils]: 117: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,188 INFO L284 TraceCheckUtils]: 118: Hoare quadruple {21481#true} {21482#false} #4332#return; {21482#false} is VALID [2022-02-20 22:38:25,188 INFO L290 TraceCheckUtils]: 119: Hoare triple {21482#false} assume -2147483648 <= main_#t~ret769#1 && main_#t~ret769#1 <= 2147483647;main_~tmp~59#1 := main_#t~ret769#1;havoc main_#t~ret769#1; {21482#false} is VALID [2022-02-20 22:38:25,188 INFO L290 TraceCheckUtils]: 120: Hoare triple {21482#false} assume !(0 == main_~tmp~59#1); {21482#false} is VALID [2022-02-20 22:38:25,188 INFO L290 TraceCheckUtils]: 121: Hoare triple {21482#false} assume 1 == main_~tmp~59#1; {21482#false} is VALID [2022-02-20 22:38:25,188 INFO L290 TraceCheckUtils]: 122: Hoare triple {21482#false} assume { :begin_inline_ldv_interrupt_interrupt_instance_0 } true;ldv_interrupt_interrupt_instance_0_#in~arg0#1.base, ldv_interrupt_interrupt_instance_0_#in~arg0#1.offset := 0, 0;havoc ldv_interrupt_interrupt_instance_0_#t~ret774#1, ldv_interrupt_interrupt_instance_0_#t~ret775#1, ldv_interrupt_interrupt_instance_0_~arg0#1.base, ldv_interrupt_interrupt_instance_0_~arg0#1.offset, ldv_interrupt_interrupt_instance_0_~tmp~61#1;ldv_interrupt_interrupt_instance_0_~arg0#1.base, ldv_interrupt_interrupt_instance_0_~arg0#1.offset := ldv_interrupt_interrupt_instance_0_#in~arg0#1.base, ldv_interrupt_interrupt_instance_0_#in~arg0#1.offset;havoc ldv_interrupt_interrupt_instance_0_~tmp~61#1; {21482#false} is VALID [2022-02-20 22:38:25,188 INFO L290 TraceCheckUtils]: 123: Hoare triple {21482#false} assume !(2 == ~ldv_statevar_0~0); {21482#false} is VALID [2022-02-20 22:38:25,189 INFO L290 TraceCheckUtils]: 124: Hoare triple {21482#false} assume !(4 == ~ldv_statevar_0~0); {21482#false} is VALID [2022-02-20 22:38:25,189 INFO L290 TraceCheckUtils]: 125: Hoare triple {21482#false} assume 5 == ~ldv_statevar_0~0; {21482#false} is VALID [2022-02-20 22:38:25,189 INFO L290 TraceCheckUtils]: 126: Hoare triple {21482#false} assume { :begin_inline_ldv_switch_to_interrupt_context } true; {21482#false} is VALID [2022-02-20 22:38:25,189 INFO L290 TraceCheckUtils]: 127: Hoare triple {21482#false} assume { :end_inline_ldv_switch_to_interrupt_context } true;assume { :begin_inline_ldv_interrupt_instance_handler_0_5 } true;ldv_interrupt_instance_handler_0_5_#in~arg0#1.base, ldv_interrupt_instance_handler_0_5_#in~arg0#1.offset, ldv_interrupt_instance_handler_0_5_#in~arg1#1, ldv_interrupt_instance_handler_0_5_#in~arg2#1.base, ldv_interrupt_instance_handler_0_5_#in~arg2#1.offset := ~ldv_0_callback_handler~0.base, ~ldv_0_callback_handler~0.offset, ~ldv_0_line_line~0, ~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset;havoc ldv_interrupt_instance_handler_0_5_#res#1;havoc ldv_interrupt_instance_handler_0_5_#t~ret770#1, ldv_interrupt_instance_handler_0_5_~arg0#1.base, ldv_interrupt_instance_handler_0_5_~arg0#1.offset, ldv_interrupt_instance_handler_0_5_~arg1#1, ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset, ldv_interrupt_instance_handler_0_5_~tmp~60#1;ldv_interrupt_instance_handler_0_5_~arg0#1.base, ldv_interrupt_instance_handler_0_5_~arg0#1.offset := ldv_interrupt_instance_handler_0_5_#in~arg0#1.base, ldv_interrupt_instance_handler_0_5_#in~arg0#1.offset;ldv_interrupt_instance_handler_0_5_~arg1#1 := ldv_interrupt_instance_handler_0_5_#in~arg1#1;ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset := ldv_interrupt_instance_handler_0_5_#in~arg2#1.base, ldv_interrupt_instance_handler_0_5_#in~arg2#1.offset;havoc ldv_interrupt_instance_handler_0_5_~tmp~60#1;assume { :begin_inline_hp100_interrupt } true;hp100_interrupt_#in~irq#1, hp100_interrupt_#in~dev_id#1.base, hp100_interrupt_#in~dev_id#1.offset := ldv_interrupt_instance_handler_0_5_~arg1#1, ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset;havoc hp100_interrupt_#res#1;havoc hp100_interrupt_#t~ret613#1.base, hp100_interrupt_#t~ret613#1.offset, hp100_interrupt_#t~mem614#1, hp100_interrupt_#t~ret615#1, hp100_interrupt_#t~mem616#1, hp100_interrupt_#t~nondet617#1, hp100_interrupt_#t~mem618#1, hp100_interrupt_#t~mem619#1, hp100_interrupt_#t~mem620#1, hp100_interrupt_#t~mem621#1, hp100_interrupt_#t~mem622#1, hp100_interrupt_~irq#1, hp100_interrupt_~dev_id#1.base, hp100_interrupt_~dev_id#1.offset, hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset, hp100_interrupt_~lp~17#1.base, hp100_interrupt_~lp~17#1.offset, hp100_interrupt_~tmp~44#1.base, hp100_interrupt_~tmp~44#1.offset, hp100_interrupt_~ioaddr~13#1, hp100_interrupt_~val~2#1, hp100_interrupt_~tmp___0~22#1;hp100_interrupt_~irq#1 := hp100_interrupt_#in~irq#1;hp100_interrupt_~dev_id#1.base, hp100_interrupt_~dev_id#1.offset := hp100_interrupt_#in~dev_id#1.base, hp100_interrupt_#in~dev_id#1.offset;havoc hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset;havoc hp100_interrupt_~lp~17#1.base, hp100_interrupt_~lp~17#1.offset;havoc hp100_interrupt_~tmp~44#1.base, hp100_interrupt_~tmp~44#1.offset;havoc hp100_interrupt_~ioaddr~13#1;havoc hp100_interrupt_~val~2#1;havoc hp100_interrupt_~tmp___0~22#1;hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset := hp100_interrupt_~dev_id#1.base, hp100_interrupt_~dev_id#1.offset; {21482#false} is VALID [2022-02-20 22:38:25,189 INFO L272 TraceCheckUtils]: 128: Hoare triple {21482#false} call hp100_interrupt_#t~ret613#1.base, hp100_interrupt_#t~ret613#1.offset := netdev_priv(hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset); {21481#true} is VALID [2022-02-20 22:38:25,189 INFO L290 TraceCheckUtils]: 129: Hoare triple {21481#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21481#true} is VALID [2022-02-20 22:38:25,189 INFO L290 TraceCheckUtils]: 130: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,190 INFO L284 TraceCheckUtils]: 131: Hoare quadruple {21481#true} {21482#false} #4368#return; {21482#false} is VALID [2022-02-20 22:38:25,190 INFO L290 TraceCheckUtils]: 132: Hoare triple {21482#false} hp100_interrupt_~tmp~44#1.base, hp100_interrupt_~tmp~44#1.offset := hp100_interrupt_#t~ret613#1.base, hp100_interrupt_#t~ret613#1.offset;havoc hp100_interrupt_#t~ret613#1.base, hp100_interrupt_#t~ret613#1.offset;hp100_interrupt_~lp~17#1.base, hp100_interrupt_~lp~17#1.offset := hp100_interrupt_~tmp~44#1.base, hp100_interrupt_~tmp~44#1.offset; {21482#false} is VALID [2022-02-20 22:38:25,190 INFO L290 TraceCheckUtils]: 133: Hoare triple {21482#false} assume !(0 == (hp100_interrupt_~dev~0#1.base + hp100_interrupt_~dev~0#1.offset) % 18446744073709551616);call hp100_interrupt_#t~mem614#1 := read~int(hp100_interrupt_~dev~0#1.base, 56 + hp100_interrupt_~dev~0#1.offset, 8);hp100_interrupt_~ioaddr~13#1 := (if hp100_interrupt_#t~mem614#1 % 18446744073709551616 % 4294967296 <= 2147483647 then hp100_interrupt_#t~mem614#1 % 18446744073709551616 % 4294967296 else hp100_interrupt_#t~mem614#1 % 18446744073709551616 % 4294967296 - 4294967296);havoc hp100_interrupt_#t~mem614#1;assume { :begin_inline_ldv_spin_lock_102 } true;ldv_spin_lock_102_#in~lock#1.base, ldv_spin_lock_102_#in~lock#1.offset := hp100_interrupt_~lp~17#1.base, hp100_interrupt_~lp~17#1.offset;havoc ldv_spin_lock_102_~lock#1.base, ldv_spin_lock_102_~lock#1.offset;ldv_spin_lock_102_~lock#1.base, ldv_spin_lock_102_~lock#1.offset := ldv_spin_lock_102_#in~lock#1.base, ldv_spin_lock_102_#in~lock#1.offset; {21482#false} is VALID [2022-02-20 22:38:25,190 INFO L272 TraceCheckUtils]: 134: Hoare triple {21482#false} call ldv_spin_lock_lock_of_hp100_private(); {21662#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} is VALID [2022-02-20 22:38:25,190 INFO L272 TraceCheckUtils]: 135: Hoare triple {21662#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} call ldv_assert(87, 0, (if 1 == ~ldv_spin_lock_of_hp100_private~0 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,190 INFO L290 TraceCheckUtils]: 136: Hoare triple {21481#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {21481#true} is VALID [2022-02-20 22:38:25,190 INFO L290 TraceCheckUtils]: 137: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,191 INFO L284 TraceCheckUtils]: 138: Hoare quadruple {21481#true} {21662#(= |old(~ldv_spin_lock_of_hp100_private~0)| ~ldv_spin_lock_of_hp100_private~0)} #4016#return; {21481#true} is VALID [2022-02-20 22:38:25,191 INFO L272 TraceCheckUtils]: 139: Hoare triple {21481#true} call ldv_assume((if 1 == ~ldv_spin_lock_of_hp100_private~0 then 1 else 0)); {21481#true} is VALID [2022-02-20 22:38:25,191 INFO L290 TraceCheckUtils]: 140: Hoare triple {21481#true} ~expression := #in~expression; {21481#true} is VALID [2022-02-20 22:38:25,191 INFO L290 TraceCheckUtils]: 141: Hoare triple {21481#true} assume !(0 == ~expression); {21481#true} is VALID [2022-02-20 22:38:25,191 INFO L290 TraceCheckUtils]: 142: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,191 INFO L284 TraceCheckUtils]: 143: Hoare quadruple {21481#true} {21481#true} #4018#return; {21481#true} is VALID [2022-02-20 22:38:25,191 INFO L290 TraceCheckUtils]: 144: Hoare triple {21481#true} ~ldv_spin_lock_of_hp100_private~0 := 2; {21481#true} is VALID [2022-02-20 22:38:25,192 INFO L290 TraceCheckUtils]: 145: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,192 INFO L284 TraceCheckUtils]: 146: Hoare quadruple {21481#true} {21482#false} #4370#return; {21482#false} is VALID [2022-02-20 22:38:25,192 INFO L290 TraceCheckUtils]: 147: Hoare triple {21482#false} assume { :begin_inline_spin_lock } true;spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset := ldv_spin_lock_102_~lock#1.base, ldv_spin_lock_102_~lock#1.offset;havoc spin_lock_~lock#1.base, spin_lock_~lock#1.offset;spin_lock_~lock#1.base, spin_lock_~lock#1.offset := spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset;assume { :begin_inline__raw_spin_lock } true;_raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset := spin_lock_~lock#1.base, spin_lock_~lock#1.offset;havoc _raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset;_raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset := _raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset; {21482#false} is VALID [2022-02-20 22:38:25,192 INFO L290 TraceCheckUtils]: 148: Hoare triple {21482#false} assume { :end_inline__raw_spin_lock } true; {21482#false} is VALID [2022-02-20 22:38:25,192 INFO L290 TraceCheckUtils]: 149: Hoare triple {21482#false} assume { :end_inline_spin_lock } true; {21482#false} is VALID [2022-02-20 22:38:25,192 INFO L290 TraceCheckUtils]: 150: Hoare triple {21482#false} assume { :end_inline_ldv_spin_lock_102 } true; {21482#false} is VALID [2022-02-20 22:38:25,192 INFO L272 TraceCheckUtils]: 151: Hoare triple {21482#false} call outw(4, 4 + hp100_interrupt_~ioaddr~13#1); {21481#true} is VALID [2022-02-20 22:38:25,193 INFO L290 TraceCheckUtils]: 152: Hoare triple {21481#true} ~value := #in~value;~port := #in~port; {21481#true} is VALID [2022-02-20 22:38:25,193 INFO L290 TraceCheckUtils]: 153: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,193 INFO L284 TraceCheckUtils]: 154: Hoare quadruple {21481#true} {21482#false} #4372#return; {21482#false} is VALID [2022-02-20 22:38:25,193 INFO L272 TraceCheckUtils]: 155: Hoare triple {21482#false} call hp100_interrupt_#t~ret615#1 := inw(8 + hp100_interrupt_~ioaddr~13#1); {21481#true} is VALID [2022-02-20 22:38:25,193 INFO L290 TraceCheckUtils]: 156: Hoare triple {21481#true} ~port := #in~port;havoc ~value~1;#res := ~value~1; {21481#true} is VALID [2022-02-20 22:38:25,193 INFO L290 TraceCheckUtils]: 157: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,193 INFO L284 TraceCheckUtils]: 158: Hoare quadruple {21481#true} {21482#false} #4374#return; {21482#false} is VALID [2022-02-20 22:38:25,194 INFO L290 TraceCheckUtils]: 159: Hoare triple {21482#false} hp100_interrupt_~tmp___0~22#1 := hp100_interrupt_#t~ret615#1;havoc hp100_interrupt_#t~ret615#1;hp100_interrupt_~val~2#1 := hp100_interrupt_~tmp___0~22#1 % 65536; {21482#false} is VALID [2022-02-20 22:38:25,194 INFO L290 TraceCheckUtils]: 160: Hoare triple {21482#false} assume !(0 == hp100_interrupt_~val~2#1 % 4294967296); {21482#false} is VALID [2022-02-20 22:38:25,194 INFO L290 TraceCheckUtils]: 161: Hoare triple {21482#false} assume !(0 != (if 0 == hp100_interrupt_~val~2#1 then 0 else (if 1 == hp100_interrupt_~val~2#1 then 0 else ~bitwiseAnd(hp100_interrupt_~val~2#1, 2048))) % 4294967296); {21482#false} is VALID [2022-02-20 22:38:25,194 INFO L290 TraceCheckUtils]: 162: Hoare triple {21482#false} assume 0 != (if 0 == hp100_interrupt_~val~2#1 then 0 else (if 1 == hp100_interrupt_~val~2#1 then 0 else ~bitwiseAnd(hp100_interrupt_~val~2#1, 1024))) % 4294967296;call hp100_interrupt_#t~mem618#1 := read~int(hp100_interrupt_~lp~17#1.base, 92 + hp100_interrupt_~lp~17#1.offset, 2); {21482#false} is VALID [2022-02-20 22:38:25,194 INFO L290 TraceCheckUtils]: 163: Hoare triple {21482#false} assume 1 != hp100_interrupt_#t~mem618#1 % 65536 % 4294967296;havoc hp100_interrupt_#t~mem618#1;assume { :begin_inline_hp100_rx } true;hp100_rx_#in~dev#1.base, hp100_rx_#in~dev#1.offset := hp100_interrupt_~dev~0#1.base, hp100_interrupt_~dev~0#1.offset;havoc hp100_rx_#t~mem514#1, hp100_rx_#t~ret515#1.base, hp100_rx_#t~ret515#1.offset, hp100_rx_#t~ret516#1, hp100_rx_#t~ret517#1, hp100_rx_#t~mem518#1, hp100_rx_#t~mem519#1.base, hp100_rx_#t~mem519#1.offset, hp100_rx_#t~ret520#1, hp100_rx_#t~ret521#1, hp100_rx_#t~ret523#1.base, hp100_rx_#t~ret523#1.offset, hp100_rx_#t~nondet522#1, hp100_rx_#t~mem524#1, hp100_rx_#t~ret525#1.base, hp100_rx_#t~ret525#1.offset, hp100_rx_#t~mem526#1.base, hp100_rx_#t~mem526#1.offset, hp100_rx_#t~mem527#1, hp100_rx_#t~mem528#1.base, hp100_rx_#t~mem528#1.offset, hp100_rx_#t~ret529#1, hp100_rx_#t~ret530#1, hp100_rx_#t~mem531#1, hp100_rx_#t~mem532#1, hp100_rx_#t~mem533#1, hp100_rx_~dev#1.base, hp100_rx_~dev#1.offset, hp100_rx_~packets~0#1, hp100_rx_~pkt_len~0#1, hp100_rx_~ioaddr~8#1, hp100_rx_~lp~13#1.base, hp100_rx_~lp~13#1.offset, hp100_rx_~tmp~39#1.base, hp100_rx_~tmp~39#1.offset, hp100_rx_~header~0#1, hp100_rx_~skb~0#1.base, hp100_rx_~skb~0#1.offset, hp100_rx_~tmp___0~18#1, hp100_rx_~tmp___1~12#1, hp100_rx_~ptr~0#1.base, hp100_rx_~ptr~0#1.offset, hp100_rx_~tmp___2~7#1;hp100_rx_~dev#1.base, hp100_rx_~dev#1.offset := hp100_rx_#in~dev#1.base, hp100_rx_#in~dev#1.offset;havoc hp100_rx_~packets~0#1;havoc hp100_rx_~pkt_len~0#1;havoc hp100_rx_~ioaddr~8#1;havoc hp100_rx_~lp~13#1.base, hp100_rx_~lp~13#1.offset;havoc hp100_rx_~tmp~39#1.base, hp100_rx_~tmp~39#1.offset;havoc hp100_rx_~header~0#1;havoc hp100_rx_~skb~0#1.base, hp100_rx_~skb~0#1.offset;havoc hp100_rx_~tmp___0~18#1;havoc hp100_rx_~tmp___1~12#1;havoc hp100_rx_~ptr~0#1.base, hp100_rx_~ptr~0#1.offset;havoc hp100_rx_~tmp___2~7#1;call hp100_rx_#t~mem514#1 := read~int(hp100_rx_~dev#1.base, 56 + hp100_rx_~dev#1.offset, 8);hp100_rx_~ioaddr~8#1 := (if hp100_rx_#t~mem514#1 % 18446744073709551616 % 4294967296 <= 2147483647 then hp100_rx_#t~mem514#1 % 18446744073709551616 % 4294967296 else hp100_rx_#t~mem514#1 % 18446744073709551616 % 4294967296 - 4294967296);havoc hp100_rx_#t~mem514#1; {21482#false} is VALID [2022-02-20 22:38:25,194 INFO L272 TraceCheckUtils]: 164: Hoare triple {21482#false} call hp100_rx_#t~ret515#1.base, hp100_rx_#t~ret515#1.offset := netdev_priv(hp100_rx_~dev#1.base, hp100_rx_~dev#1.offset); {21481#true} is VALID [2022-02-20 22:38:25,194 INFO L290 TraceCheckUtils]: 165: Hoare triple {21481#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21481#true} is VALID [2022-02-20 22:38:25,195 INFO L290 TraceCheckUtils]: 166: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,195 INFO L284 TraceCheckUtils]: 167: Hoare quadruple {21481#true} {21482#false} #4382#return; {21482#false} is VALID [2022-02-20 22:38:25,195 INFO L290 TraceCheckUtils]: 168: Hoare triple {21482#false} hp100_rx_~tmp~39#1.base, hp100_rx_~tmp~39#1.offset := hp100_rx_#t~ret515#1.base, hp100_rx_#t~ret515#1.offset;havoc hp100_rx_#t~ret515#1.base, hp100_rx_#t~ret515#1.offset;hp100_rx_~lp~13#1.base, hp100_rx_~lp~13#1.offset := hp100_rx_~tmp~39#1.base, hp100_rx_~tmp~39#1.offset; {21482#false} is VALID [2022-02-20 22:38:25,195 INFO L272 TraceCheckUtils]: 169: Hoare triple {21482#false} call hp100_rx_#t~ret516#1 := inb(24 + hp100_rx_~ioaddr~8#1); {21481#true} is VALID [2022-02-20 22:38:25,195 INFO L290 TraceCheckUtils]: 170: Hoare triple {21481#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {21481#true} is VALID [2022-02-20 22:38:25,195 INFO L290 TraceCheckUtils]: 171: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,195 INFO L284 TraceCheckUtils]: 172: Hoare quadruple {21481#true} {21482#false} #4384#return; {21482#false} is VALID [2022-02-20 22:38:25,195 INFO L290 TraceCheckUtils]: 173: Hoare triple {21482#false} hp100_rx_~tmp___0~18#1 := hp100_rx_#t~ret516#1;havoc hp100_rx_#t~ret516#1;hp100_rx_~packets~0#1 := hp100_rx_~tmp___0~18#1 % 256; {21482#false} is VALID [2022-02-20 22:38:25,196 INFO L290 TraceCheckUtils]: 174: Hoare triple {21482#false} hp100_rx_~tmp___2~7#1 := hp100_rx_~packets~0#1;hp100_rx_~packets~0#1 := hp100_rx_~packets~0#1 - 1; {21482#false} is VALID [2022-02-20 22:38:25,196 INFO L290 TraceCheckUtils]: 175: Hoare triple {21482#false} assume hp100_rx_~tmp___2~7#1 > 0; {21482#false} is VALID [2022-02-20 22:38:25,196 INFO L290 TraceCheckUtils]: 176: Hoare triple {21482#false} hp100_rx_~pkt_len~0#1 := 0; {21482#false} is VALID [2022-02-20 22:38:25,196 INFO L290 TraceCheckUtils]: 177: Hoare triple {21482#false} assume !(hp100_rx_~pkt_len~0#1 <= 5999); {21482#false} is VALID [2022-02-20 22:38:25,196 INFO L290 TraceCheckUtils]: 178: Hoare triple {21482#false} call hp100_rx_#t~mem518#1 := read~int(hp100_rx_~lp~13#1.base, 92 + hp100_rx_~lp~13#1.offset, 2); {21482#false} is VALID [2022-02-20 22:38:25,196 INFO L290 TraceCheckUtils]: 179: Hoare triple {21482#false} assume 2 == hp100_rx_#t~mem518#1 % 65536 % 4294967296;havoc hp100_rx_#t~mem518#1;call hp100_rx_#t~mem519#1.base, hp100_rx_#t~mem519#1.offset := read~$Pointer$(hp100_rx_~lp~13#1.base, 105 + hp100_rx_~lp~13#1.offset, 8);assume { :begin_inline_readl } true;readl_#in~addr#1.base, readl_#in~addr#1.offset := hp100_rx_#t~mem519#1.base, hp100_rx_#t~mem519#1.offset;havoc readl_#res#1;havoc readl_~addr#1.base, readl_~addr#1.offset, readl_~ret~0#1;readl_~addr#1.base, readl_~addr#1.offset := readl_#in~addr#1.base, readl_#in~addr#1.offset;havoc readl_~ret~0#1;readl_#res#1 := readl_~ret~0#1; {21482#false} is VALID [2022-02-20 22:38:25,196 INFO L290 TraceCheckUtils]: 180: Hoare triple {21482#false} hp100_rx_#t~ret520#1 := readl_#res#1;assume { :end_inline_readl } true;hp100_rx_~header~0#1 := hp100_rx_#t~ret520#1;havoc hp100_rx_#t~mem519#1.base, hp100_rx_#t~mem519#1.offset;havoc hp100_rx_#t~ret520#1; {21482#false} is VALID [2022-02-20 22:38:25,197 INFO L290 TraceCheckUtils]: 181: Hoare triple {21482#false} assume 0 == (if (3 + (if 0 == hp100_rx_~header~0#1 then 0 else (if 1 == hp100_rx_~header~0#1 then 1 else ~bitwiseAnd(hp100_rx_~header~0#1, 8191)))) % 4294967296 % 4294967296 <= 2147483647 then (3 + (if 0 == hp100_rx_~header~0#1 then 0 else (if 1 == hp100_rx_~header~0#1 then 1 else ~bitwiseAnd(hp100_rx_~header~0#1, 8191)))) % 4294967296 % 4294967296 else (3 + (if 0 == hp100_rx_~header~0#1 then 0 else (if 1 == hp100_rx_~header~0#1 then 1 else ~bitwiseAnd(hp100_rx_~header~0#1, 8191)))) % 4294967296 % 4294967296 - 4294967296);hp100_rx_~pkt_len~0#1 := 0; {21482#false} is VALID [2022-02-20 22:38:25,197 INFO L272 TraceCheckUtils]: 182: Hoare triple {21482#false} call hp100_rx_#t~ret523#1.base, hp100_rx_#t~ret523#1.offset := netdev_alloc_skb(hp100_rx_~dev#1.base, hp100_rx_~dev#1.offset, 2 + hp100_rx_~pkt_len~0#1); {21482#false} is VALID [2022-02-20 22:38:25,197 INFO L290 TraceCheckUtils]: 183: Hoare triple {21482#false} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;~length#1 := #in~length#1;havoc ~tmp~8#1.base, ~tmp~8#1.offset;assume { :begin_inline_ldv___netdev_alloc_skb_57 } true;ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_57_#in~ldv_func_arg2#1, ldv___netdev_alloc_skb_57_#in~flags#1 := ~dev#1.base, ~dev#1.offset, ~length#1, 32;havoc ldv___netdev_alloc_skb_57_#res#1.base, ldv___netdev_alloc_skb_57_#res#1.offset;havoc ldv___netdev_alloc_skb_57_#t~ret835#1.base, ldv___netdev_alloc_skb_57_#t~ret835#1.offset, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_57_~ldv_func_arg2#1, ldv___netdev_alloc_skb_57_~flags#1, ldv___netdev_alloc_skb_57_~tmp~72#1.base, ldv___netdev_alloc_skb_57_~tmp~72#1.offset;ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.offset := ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.offset;ldv___netdev_alloc_skb_57_~ldv_func_arg2#1 := ldv___netdev_alloc_skb_57_#in~ldv_func_arg2#1;ldv___netdev_alloc_skb_57_~flags#1 := ldv___netdev_alloc_skb_57_#in~flags#1;havoc ldv___netdev_alloc_skb_57_~tmp~72#1.base, ldv___netdev_alloc_skb_57_~tmp~72#1.offset; {21482#false} is VALID [2022-02-20 22:38:25,197 INFO L272 TraceCheckUtils]: 184: Hoare triple {21482#false} call ldv_check_alloc_flags(ldv___netdev_alloc_skb_57_~flags#1); {21482#false} is VALID [2022-02-20 22:38:25,197 INFO L290 TraceCheckUtils]: 185: Hoare triple {21482#false} ~flags#1 := #in~flags#1;havoc ~tmp~79#1; {21482#false} is VALID [2022-02-20 22:38:25,197 INFO L290 TraceCheckUtils]: 186: Hoare triple {21482#false} assume 32 != ~flags#1 % 4294967296 && 0 != ~flags#1 % 4294967296; {21482#false} is VALID [2022-02-20 22:38:25,197 INFO L272 TraceCheckUtils]: 187: Hoare triple {21482#false} call #t~ret846#1 := ldv_exclusive_spin_is_locked(); {21481#true} is VALID [2022-02-20 22:38:25,198 INFO L290 TraceCheckUtils]: 188: Hoare triple {21481#true} assume 2 == ~ldv_spin__xmit_lock_of_netdev_queue~0;#res := 1; {21481#true} is VALID [2022-02-20 22:38:25,198 INFO L290 TraceCheckUtils]: 189: Hoare triple {21481#true} assume true; {21481#true} is VALID [2022-02-20 22:38:25,198 INFO L284 TraceCheckUtils]: 190: Hoare quadruple {21481#true} {21482#false} #3826#return; {21482#false} is VALID [2022-02-20 22:38:25,198 INFO L290 TraceCheckUtils]: 191: Hoare triple {21482#false} assume -2147483648 <= #t~ret846#1 && #t~ret846#1 <= 2147483647;~tmp~79#1 := #t~ret846#1;havoc #t~ret846#1;assume { :begin_inline_ldv_assert_linux_alloc_spinlock__wrong_flags } true;ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1 := (if 0 == ~tmp~79#1 then 1 else 0);havoc ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1;ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1 := ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1; {21482#false} is VALID [2022-02-20 22:38:25,198 INFO L290 TraceCheckUtils]: 192: Hoare triple {21482#false} assume 0 == ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1; {21482#false} is VALID [2022-02-20 22:38:25,198 INFO L290 TraceCheckUtils]: 193: Hoare triple {21482#false} assume !false; {21482#false} is VALID [2022-02-20 22:38:25,199 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 120 trivial. 0 not checked. [2022-02-20 22:38:25,199 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:38:25,199 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39398579] [2022-02-20 22:38:25,200 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39398579] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:38:25,200 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:38:25,200 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-02-20 22:38:25,200 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1001274315] [2022-02-20 22:38:25,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:38:25,201 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 21.6) internal successors, (108), 3 states have internal predecessors, (108), 4 states have call successors, (24), 5 states have call predecessors, (24), 1 states have return successors, (22), 3 states have call predecessors, (22), 4 states have call successors, (22) Word has length 194 [2022-02-20 22:38:25,202 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:38:25,202 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 6 states, 5 states have (on average 21.6) internal successors, (108), 3 states have internal predecessors, (108), 4 states have call successors, (24), 5 states have call predecessors, (24), 1 states have return successors, (22), 3 states have call predecessors, (22), 4 states have call successors, (22) [2022-02-20 22:38:25,325 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 154 edges. 154 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:38:25,325 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-02-20 22:38:25,326 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:38:25,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-02-20 22:38:25,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-02-20 22:38:25,327 INFO L87 Difference]: Start difference. First operand 3285 states and 4787 transitions. Second operand has 6 states, 5 states have (on average 21.6) internal successors, (108), 3 states have internal predecessors, (108), 4 states have call successors, (24), 5 states have call predecessors, (24), 1 states have return successors, (22), 3 states have call predecessors, (22), 4 states have call successors, (22)