./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash c727ee56ff8cf558c3dc08b64ebc267261ea17bdfb88e50734daf71ad89adc7d --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 22:38:40,273 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 22:38:40,275 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 22:38:40,322 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 22:38:40,323 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 22:38:40,326 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 22:38:40,333 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 22:38:40,336 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 22:38:40,338 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 22:38:40,343 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 22:38:40,343 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 22:38:40,360 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 22:38:40,360 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 22:38:40,363 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 22:38:40,364 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 22:38:40,367 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 22:38:40,368 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 22:38:40,369 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 22:38:40,371 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 22:38:40,376 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 22:38:40,378 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 22:38:40,379 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 22:38:40,380 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 22:38:40,381 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 22:38:40,382 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 22:38:40,383 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 22:38:40,383 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 22:38:40,384 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 22:38:40,384 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 22:38:40,385 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 22:38:40,385 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 22:38:40,386 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 22:38:40,387 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 22:38:40,388 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 22:38:40,389 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 22:38:40,403 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 22:38:40,404 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 22:38:40,404 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 22:38:40,404 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 22:38:40,405 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 22:38:40,405 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 22:38:40,406 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 22:38:40,452 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 22:38:40,452 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 22:38:40,453 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 22:38:40,453 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 22:38:40,454 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 22:38:40,454 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 22:38:40,454 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 22:38:40,454 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 22:38:40,455 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 22:38:40,455 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 22:38:40,455 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 22:38:40,456 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 22:38:40,456 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 22:38:40,456 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 22:38:40,456 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 22:38:40,456 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 22:38:40,456 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 22:38:40,456 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 22:38:40,457 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 22:38:40,457 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 22:38:40,457 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 22:38:40,457 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:38:40,457 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 22:38:40,457 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 22:38:40,457 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 22:38:40,458 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 22:38:40,458 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 22:38:40,459 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 22:38:40,459 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 22:38:40,459 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 22:38:40,459 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c727ee56ff8cf558c3dc08b64ebc267261ea17bdfb88e50734daf71ad89adc7d [2022-02-20 22:38:40,833 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 22:38:40,873 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 22:38:40,874 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 22:38:40,875 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 22:38:40,877 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 22:38:40,878 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i [2022-02-20 22:38:40,929 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0ca23d5a5/b447e675a78247d19b8c1dde6acdb0e2/FLAG9b7f4d8e5 [2022-02-20 22:38:41,454 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 22:38:41,454 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i [2022-02-20 22:38:41,488 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0ca23d5a5/b447e675a78247d19b8c1dde6acdb0e2/FLAG9b7f4d8e5 [2022-02-20 22:38:41,698 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0ca23d5a5/b447e675a78247d19b8c1dde6acdb0e2 [2022-02-20 22:38:41,702 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 22:38:41,703 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 22:38:41,704 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 22:38:41,704 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 22:38:41,706 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 22:38:41,707 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:38:41" (1/1) ... [2022-02-20 22:38:41,708 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@35a8d1ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:41, skipping insertion in model container [2022-02-20 22:38:41,708 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:38:41" (1/1) ... [2022-02-20 22:38:41,712 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 22:38:41,818 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 22:38:43,914 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i[328445,328458] [2022-02-20 22:38:43,916 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i[328590,328603] [2022-02-20 22:38:43,938 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:38:43,977 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 22:38:44,306 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i[328445,328458] [2022-02-20 22:38:44,307 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i[328590,328603] [2022-02-20 22:38:44,310 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:38:44,381 INFO L208 MainTranslator]: Completed translation [2022-02-20 22:38:44,381 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44 WrapperNode [2022-02-20 22:38:44,381 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 22:38:44,382 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 22:38:44,383 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 22:38:44,383 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 22:38:44,388 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,458 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,565 INFO L137 Inliner]: procedures = 388, calls = 2109, calls flagged for inlining = 154, calls inlined = 135, statements flattened = 4406 [2022-02-20 22:38:44,566 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 22:38:44,566 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 22:38:44,566 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 22:38:44,567 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 22:38:44,573 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,574 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,591 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,592 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,724 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,744 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,759 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,776 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 22:38:44,777 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 22:38:44,777 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 22:38:44,777 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 22:38:44,778 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (1/1) ... [2022-02-20 22:38:44,783 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:38:44,790 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:38:44,807 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 22:38:44,827 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 22:38:44,837 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_97 [2022-02-20 22:38:44,837 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_97 [2022-02-20 22:38:44,837 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2022-02-20 22:38:44,838 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2022-02-20 22:38:44,838 INFO L130 BoogieDeclarations]: Found specification of procedure RxCurCount [2022-02-20 22:38:44,838 INFO L138 BoogieDeclarations]: Found implementation of procedure RxCurCount [2022-02-20 22:38:44,838 INFO L130 BoogieDeclarations]: Found specification of procedure irda_setup_dma [2022-02-20 22:38:44,838 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_setup_dma [2022-02-20 22:38:44,838 INFO L130 BoogieDeclarations]: Found specification of procedure netif_wake_queue [2022-02-20 22:38:44,838 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_wake_queue [2022-02-20 22:38:44,839 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 22:38:44,839 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 22:38:44,839 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2022-02-20 22:38:44,839 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2022-02-20 22:38:44,839 INFO L130 BoogieDeclarations]: Found specification of procedure CheckRegBit [2022-02-20 22:38:44,839 INFO L138 BoogieDeclarations]: Found implementation of procedure CheckRegBit [2022-02-20 22:38:44,839 INFO L130 BoogieDeclarations]: Found specification of procedure via_remove_one [2022-02-20 22:38:44,839 INFO L138 BoogieDeclarations]: Found implementation of procedure via_remove_one [2022-02-20 22:38:44,840 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_speed [2022-02-20 22:38:44,840 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_speed [2022-02-20 22:38:44,840 INFO L130 BoogieDeclarations]: Found specification of procedure dma_zalloc_coherent [2022-02-20 22:38:44,840 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_zalloc_coherent [2022-02-20 22:38:44,840 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_xmalloc [2022-02-20 22:38:44,840 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_xmalloc [2022-02-20 22:38:44,840 INFO L130 BoogieDeclarations]: Found specification of procedure SetPulseWidth [2022-02-20 22:38:44,840 INFO L138 BoogieDeclarations]: Found implementation of procedure SetPulseWidth [2022-02-20 22:38:44,841 INFO L130 BoogieDeclarations]: Found specification of procedure Tdelay [2022-02-20 22:38:44,841 INFO L138 BoogieDeclarations]: Found implementation of procedure Tdelay [2022-02-20 22:38:44,841 INFO L130 BoogieDeclarations]: Found specification of procedure netif_rx [2022-02-20 22:38:44,841 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_rx [2022-02-20 22:38:44,841 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_is_err [2022-02-20 22:38:44,841 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_is_err [2022-02-20 22:38:44,841 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 22:38:44,841 INFO L130 BoogieDeclarations]: Found specification of procedure ClkTx [2022-02-20 22:38:44,842 INFO L138 BoogieDeclarations]: Found implementation of procedure ClkTx [2022-02-20 22:38:44,842 INFO L130 BoogieDeclarations]: Found specification of procedure WriteLPCReg [2022-02-20 22:38:44,842 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteLPCReg [2022-02-20 22:38:44,842 INFO L130 BoogieDeclarations]: Found specification of procedure capable [2022-02-20 22:38:44,842 INFO L138 BoogieDeclarations]: Found implementation of procedure capable [2022-02-20 22:38:44,842 INFO L130 BoogieDeclarations]: Found specification of procedure CommonInit [2022-02-20 22:38:44,842 INFO L138 BoogieDeclarations]: Found implementation of procedure CommonInit [2022-02-20 22:38:44,842 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_get_tx_queue [2022-02-20 22:38:44,843 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_get_tx_queue [2022-02-20 22:38:44,843 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_dongle_speed [2022-02-20 22:38:44,843 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_dongle_speed [2022-02-20 22:38:44,843 INFO L130 BoogieDeclarations]: Found specification of procedure ReadLPCReg [2022-02-20 22:38:44,843 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadLPCReg [2022-02-20 22:38:44,843 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2022-02-20 22:38:44,843 INFO L130 BoogieDeclarations]: Found specification of procedure free_dma [2022-02-20 22:38:44,844 INFO L138 BoogieDeclarations]: Found implementation of procedure free_dma [2022-02-20 22:38:44,844 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_lock_of_via_ircc_cb [2022-02-20 22:38:44,844 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_lock_of_via_ircc_cb [2022-02-20 22:38:44,844 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_receive [2022-02-20 22:38:44,844 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_receive [2022-02-20 22:38:44,844 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2022-02-20 22:38:44,844 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assume [2022-02-20 22:38:44,844 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assume [2022-02-20 22:38:44,845 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_close [2022-02-20 22:38:44,845 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_close [2022-02-20 22:38:44,845 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 22:38:44,845 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2022-02-20 22:38:44,845 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2022-02-20 22:38:44,845 INFO L130 BoogieDeclarations]: Found specification of procedure CkRxRecv [2022-02-20 22:38:44,845 INFO L138 BoogieDeclarations]: Found implementation of procedure CkRxRecv [2022-02-20 22:38:44,846 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2022-02-20 22:38:44,846 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2022-02-20 22:38:44,846 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_err_code [2022-02-20 22:38:44,846 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_err_code [2022-02-20 22:38:44,846 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_alloc_flags [2022-02-20 22:38:44,846 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_alloc_flags [2022-02-20 22:38:44,846 INFO L130 BoogieDeclarations]: Found specification of procedure irda_get_next_speed [2022-02-20 22:38:44,846 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_get_next_speed [2022-02-20 22:38:44,847 INFO L130 BoogieDeclarations]: Found specification of procedure ReadReg [2022-02-20 22:38:44,847 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadReg [2022-02-20 22:38:44,847 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_open [2022-02-20 22:38:44,847 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_open [2022-02-20 22:38:44,847 INFO L130 BoogieDeclarations]: Found specification of procedure WriteRegBit [2022-02-20 22:38:44,847 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteRegBit [2022-02-20 22:38:44,847 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 22:38:44,847 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_switch_0 [2022-02-20 22:38:44,848 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_switch_0 [2022-02-20 22:38:44,848 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Indx [2022-02-20 22:38:44,848 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Indx [2022-02-20 22:38:44,848 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 22:38:44,848 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_int [2022-02-20 22:38:44,848 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_int [2022-02-20 22:38:44,848 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2022-02-20 22:38:44,848 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2022-02-20 22:38:44,849 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-02-20 22:38:44,849 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 22:38:44,849 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 22:38:44,849 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~int [2022-02-20 22:38:44,849 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~int [2022-02-20 22:38:44,849 INFO L130 BoogieDeclarations]: Found specification of procedure WriteReg [2022-02-20 22:38:44,849 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteReg [2022-02-20 22:38:44,849 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_exclusive_spin_is_locked [2022-02-20 22:38:44,850 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_exclusive_spin_is_locked [2022-02-20 22:38:44,850 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assert [2022-02-20 22:38:44,850 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assert [2022-02-20 22:38:44,850 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_spin_lock [2022-02-20 22:38:44,850 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_spin_lock [2022-02-20 22:38:44,850 INFO L130 BoogieDeclarations]: Found specification of procedure warn_slowpath_null [2022-02-20 22:38:44,850 INFO L138 BoogieDeclarations]: Found implementation of procedure warn_slowpath_null [2022-02-20 22:38:44,850 INFO L130 BoogieDeclarations]: Found specification of procedure SetBaudRate [2022-02-20 22:38:44,851 INFO L138 BoogieDeclarations]: Found implementation of procedure SetBaudRate [2022-02-20 22:38:44,851 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Byte [2022-02-20 22:38:44,851 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Byte [2022-02-20 22:38:44,851 INFO L130 BoogieDeclarations]: Found specification of procedure skb_put [2022-02-20 22:38:44,851 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_put [2022-02-20 22:38:44,851 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_netdev [2022-02-20 22:38:44,851 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_netdev [2022-02-20 22:38:44,851 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_open [2022-02-20 22:38:44,852 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_open [2022-02-20 22:38:44,852 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 22:38:44,852 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 22:38:44,852 INFO L130 BoogieDeclarations]: Found specification of procedure ResetChip [2022-02-20 22:38:44,852 INFO L138 BoogieDeclarations]: Found implementation of procedure ResetChip [2022-02-20 22:38:44,852 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2022-02-20 22:38:44,852 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2022-02-20 22:38:44,853 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 22:38:44,853 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 22:38:44,853 INFO L130 BoogieDeclarations]: Found specification of procedure irda_device_txqueue_empty [2022-02-20 22:38:44,853 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_device_txqueue_empty [2022-02-20 22:38:44,853 INFO L130 BoogieDeclarations]: Found specification of procedure pci_read_config_byte [2022-02-20 22:38:44,853 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_read_config_byte [2022-02-20 22:38:44,853 INFO L130 BoogieDeclarations]: Found specification of procedure Sdelay [2022-02-20 22:38:44,853 INFO L138 BoogieDeclarations]: Found implementation of procedure Sdelay [2022-02-20 22:38:44,854 INFO L130 BoogieDeclarations]: Found specification of procedure SetSIR [2022-02-20 22:38:44,854 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSIR [2022-02-20 22:38:44,854 INFO L130 BoogieDeclarations]: Found specification of procedure netif_stop_queue [2022-02-20 22:38:44,854 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_stop_queue [2022-02-20 22:38:44,854 INFO L130 BoogieDeclarations]: Found specification of procedure SetMaxRxPacketSize [2022-02-20 22:38:44,854 INFO L138 BoogieDeclarations]: Found implementation of procedure SetMaxRxPacketSize [2022-02-20 22:38:44,854 INFO L130 BoogieDeclarations]: Found specification of procedure GetRecvByte [2022-02-20 22:38:44,854 INFO L138 BoogieDeclarations]: Found implementation of procedure GetRecvByte [2022-02-20 22:38:44,855 INFO L130 BoogieDeclarations]: Found specification of procedure consume_skb [2022-02-20 22:38:44,855 INFO L138 BoogieDeclarations]: Found implementation of procedure consume_skb [2022-02-20 22:38:44,855 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 22:38:44,855 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 22:38:44,855 INFO L130 BoogieDeclarations]: Found specification of procedure hwreset [2022-02-20 22:38:44,855 INFO L138 BoogieDeclarations]: Found implementation of procedure hwreset [2022-02-20 22:38:44,855 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 22:38:44,855 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 22:38:44,856 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 22:38:44,856 INFO L130 BoogieDeclarations]: Found specification of procedure pci_write_config_byte [2022-02-20 22:38:44,856 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_write_config_byte [2022-02-20 22:38:44,856 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_priv [2022-02-20 22:38:44,856 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_priv [2022-02-20 22:38:44,856 INFO L130 BoogieDeclarations]: Found specification of procedure outb [2022-02-20 22:38:44,856 INFO L138 BoogieDeclarations]: Found implementation of procedure outb [2022-02-20 22:38:44,856 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_positive_int [2022-02-20 22:38:44,856 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_positive_int [2022-02-20 22:38:44,857 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq [2022-02-20 22:38:44,857 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq [2022-02-20 22:38:44,857 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2022-02-20 22:38:44,857 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2022-02-20 22:38:44,857 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_xmit [2022-02-20 22:38:44,857 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_xmit [2022-02-20 22:38:44,857 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reserve [2022-02-20 22:38:44,857 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reserve [2022-02-20 22:38:44,858 INFO L130 BoogieDeclarations]: Found specification of procedure dma_free_attrs [2022-02-20 22:38:44,858 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_free_attrs [2022-02-20 22:38:44,858 INFO L130 BoogieDeclarations]: Found specification of procedure netif_tx_start_queue [2022-02-20 22:38:44,858 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_tx_start_queue [2022-02-20 22:38:44,858 INFO L130 BoogieDeclarations]: Found specification of procedure free_netdev [2022-02-20 22:38:44,858 INFO L138 BoogieDeclarations]: Found implementation of procedure free_netdev [2022-02-20 22:38:44,858 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2022-02-20 22:38:44,858 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2022-02-20 22:38:44,858 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 22:38:44,859 INFO L130 BoogieDeclarations]: Found specification of procedure net_ratelimit [2022-02-20 22:38:44,859 INFO L138 BoogieDeclarations]: Found implementation of procedure net_ratelimit [2022-02-20 22:38:44,859 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendByte [2022-02-20 22:38:44,859 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendByte [2022-02-20 22:38:44,859 INFO L130 BoogieDeclarations]: Found specification of procedure dev_alloc_skb [2022-02-20 22:38:44,859 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_alloc_skb [2022-02-20 22:38:44,859 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2022-02-20 22:38:44,859 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2022-02-20 22:38:44,860 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_lock_of_via_ircc_cb [2022-02-20 22:38:44,860 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_lock_of_via_ircc_cb [2022-02-20 22:38:44,860 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendPreambleCount [2022-02-20 22:38:44,860 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendPreambleCount [2022-02-20 22:38:44,860 INFO L130 BoogieDeclarations]: Found specification of procedure InitCard [2022-02-20 22:38:44,860 INFO L138 BoogieDeclarations]: Found implementation of procedure InitCard [2022-02-20 22:38:44,860 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free [2022-02-20 22:38:44,860 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free [2022-02-20 22:38:44,860 INFO L130 BoogieDeclarations]: Found specification of procedure SetTimer [2022-02-20 22:38:44,861 INFO L138 BoogieDeclarations]: Found implementation of procedure SetTimer [2022-02-20 22:38:44,861 INFO L130 BoogieDeclarations]: Found specification of procedure ActClk [2022-02-20 22:38:44,861 INFO L138 BoogieDeclarations]: Found implementation of procedure ActClk [2022-02-20 22:38:44,861 INFO L130 BoogieDeclarations]: Found specification of procedure request_dma [2022-02-20 22:38:44,861 INFO L138 BoogieDeclarations]: Found implementation of procedure request_dma [2022-02-20 22:38:44,861 INFO L130 BoogieDeclarations]: Found specification of procedure inb [2022-02-20 22:38:44,861 INFO L138 BoogieDeclarations]: Found implementation of procedure inb [2022-02-20 22:38:44,861 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 22:38:44,862 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reset_mac_header [2022-02-20 22:38:44,862 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reset_mac_header [2022-02-20 22:38:44,862 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2022-02-20 22:38:44,862 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2022-02-20 22:38:44,862 INFO L130 BoogieDeclarations]: Found specification of procedure skb_copy_to_linear_data [2022-02-20 22:38:44,862 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_copy_to_linear_data [2022-02-20 22:38:45,322 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 22:38:45,324 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 22:38:45,501 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 22:38:48,742 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ULTIMATE.startFINAL: assume true; [2022-02-20 22:38:49,329 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 22:38:49,346 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 22:38:49,346 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-02-20 22:38:49,349 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:38:49 BoogieIcfgContainer [2022-02-20 22:38:49,349 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 22:38:49,350 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 22:38:49,350 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 22:38:49,353 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 22:38:49,353 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 10:38:41" (1/3) ... [2022-02-20 22:38:49,354 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@23decb46 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:38:49, skipping insertion in model container [2022-02-20 22:38:49,354 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:38:44" (2/3) ... [2022-02-20 22:38:49,354 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@23decb46 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:38:49, skipping insertion in model container [2022-02-20 22:38:49,354 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:38:49" (3/3) ... [2022-02-20 22:38:49,355 INFO L111 eAbstractionObserver]: Analyzing ICFG linux-3.14_complex_emg_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i [2022-02-20 22:38:49,359 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 22:38:49,359 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-02-20 22:38:49,395 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 22:38:49,400 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 22:38:49,401 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-02-20 22:38:49,455 INFO L276 IsEmpty]: Start isEmpty. Operand has 1987 states, 1235 states have (on average 1.3036437246963564) internal successors, (1610), 1259 states have internal predecessors, (1610), 660 states have call successors, (660), 92 states have call predecessors, (660), 91 states have return successors, (656), 644 states have call predecessors, (656), 656 states have call successors, (656) [2022-02-20 22:38:49,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-02-20 22:38:49,536 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:38:49,537 INFO L514 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:38:49,538 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:38:49,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:38:49,542 INFO L85 PathProgramCache]: Analyzing trace with hash 648572882, now seen corresponding path program 1 times [2022-02-20 22:38:49,549 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:38:49,549 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794771802] [2022-02-20 22:38:49,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:38:49,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:38:49,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,002 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 3 [2022-02-20 22:38:50,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,013 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,025 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,025 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,025 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,026 INFO L290 TraceCheckUtils]: 0: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,026 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,027 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,027 INFO L290 TraceCheckUtils]: 3: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,027 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,027 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,027 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,028 INFO L290 TraceCheckUtils]: 7: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,028 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1990#true} {1990#true} #4690#return; {1990#true} is VALID [2022-02-20 22:38:50,028 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 14 [2022-02-20 22:38:50,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,037 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,042 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,043 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,043 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,043 INFO L290 TraceCheckUtils]: 0: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,044 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,044 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,044 INFO L290 TraceCheckUtils]: 3: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,044 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,044 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,044 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,045 INFO L290 TraceCheckUtils]: 7: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,045 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1990#true} {1990#true} #4692#return; {1990#true} is VALID [2022-02-20 22:38:50,045 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 25 [2022-02-20 22:38:50,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,053 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,059 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,060 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,060 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,060 INFO L290 TraceCheckUtils]: 0: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,060 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,060 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,061 INFO L290 TraceCheckUtils]: 3: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,061 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,061 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,061 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,061 INFO L290 TraceCheckUtils]: 7: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,061 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1990#true} {1990#true} #4694#return; {1990#true} is VALID [2022-02-20 22:38:50,062 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2022-02-20 22:38:50,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,070 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,076 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,076 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,076 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,076 INFO L290 TraceCheckUtils]: 0: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,077 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,077 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,077 INFO L290 TraceCheckUtils]: 3: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,077 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,077 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,077 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,078 INFO L290 TraceCheckUtils]: 7: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,078 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1990#true} {1990#true} #4696#return; {1990#true} is VALID [2022-02-20 22:38:50,078 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 47 [2022-02-20 22:38:50,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,087 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,093 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,093 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,093 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,093 INFO L290 TraceCheckUtils]: 0: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,093 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,094 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,094 INFO L290 TraceCheckUtils]: 3: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,094 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,094 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,094 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,095 INFO L290 TraceCheckUtils]: 7: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,095 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1990#true} {1990#true} #4698#return; {1990#true} is VALID [2022-02-20 22:38:50,095 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 60 [2022-02-20 22:38:50,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,104 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,104 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,105 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {2037#(= 6 ~ldv_statevar_0~0)} #4700#return; {2037#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:38:50,105 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 73 [2022-02-20 22:38:50,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,111 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1990#true} is VALID [2022-02-20 22:38:50,111 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,111 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1991#false} #4736#return; {1991#false} is VALID [2022-02-20 22:38:50,114 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 78 [2022-02-20 22:38:50,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,122 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-02-20 22:38:50,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,127 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {1990#true} is VALID [2022-02-20 22:38:50,127 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,128 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {2116#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} #4686#return; {1990#true} is VALID [2022-02-20 22:38:50,128 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 22:38:50,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,133 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~expression := #in~expression; {1990#true} is VALID [2022-02-20 22:38:50,133 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume !(0 == ~expression); {1990#true} is VALID [2022-02-20 22:38:50,133 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,133 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1990#true} {1990#true} #4688#return; {1990#true} is VALID [2022-02-20 22:38:50,134 INFO L272 TraceCheckUtils]: 0: Hoare triple {2116#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} call ldv_assert(191, 0, (if 1 == ~ldv_spin_lock_of_via_ircc_cb~0 then 1 else 0)); {1990#true} is VALID [2022-02-20 22:38:50,134 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {1990#true} is VALID [2022-02-20 22:38:50,134 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,134 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1990#true} {2116#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} #4686#return; {1990#true} is VALID [2022-02-20 22:38:50,134 INFO L272 TraceCheckUtils]: 4: Hoare triple {1990#true} call ldv_assume((if 1 == ~ldv_spin_lock_of_via_ircc_cb~0 then 1 else 0)); {1990#true} is VALID [2022-02-20 22:38:50,135 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} ~expression := #in~expression; {1990#true} is VALID [2022-02-20 22:38:50,135 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume !(0 == ~expression); {1990#true} is VALID [2022-02-20 22:38:50,135 INFO L290 TraceCheckUtils]: 7: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,135 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1990#true} {1990#true} #4688#return; {1990#true} is VALID [2022-02-20 22:38:50,135 INFO L290 TraceCheckUtils]: 9: Hoare triple {1990#true} ~ldv_spin_lock_of_via_ircc_cb~0 := 2; {1990#true} is VALID [2022-02-20 22:38:50,135 INFO L290 TraceCheckUtils]: 10: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,136 INFO L284 TraceCheckUtils]: 11: Hoare quadruple {1990#true} {1991#false} #4738#return; {1991#false} is VALID [2022-02-20 22:38:50,136 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 95 [2022-02-20 22:38:50,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,145 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,150 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,150 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,150 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,150 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,151 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,151 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,151 INFO L290 TraceCheckUtils]: 3: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,151 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,151 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,152 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,152 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1990#true} {1991#false} #4740#return; {1991#false} is VALID [2022-02-20 22:38:50,152 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 109 [2022-02-20 22:38:50,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,161 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,166 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,167 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,167 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,167 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,167 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,168 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,168 INFO L290 TraceCheckUtils]: 3: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,168 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,168 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,168 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,168 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1990#true} {1991#false} #4824#return; {1991#false} is VALID [2022-02-20 22:38:50,175 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 123 [2022-02-20 22:38:50,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,193 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,199 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,205 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,205 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,205 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,205 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,205 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,206 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,206 INFO L290 TraceCheckUtils]: 3: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,206 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,206 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,206 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,207 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1990#true} {1990#true} #4188#return; {1990#true} is VALID [2022-02-20 22:38:50,207 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 22:38:50,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,215 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:38:50,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,220 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,221 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,221 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,221 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,221 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,222 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,222 INFO L290 TraceCheckUtils]: 3: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,222 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,222 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,222 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,222 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1990#true} {1990#true} #4190#return; {1990#true} is VALID [2022-02-20 22:38:50,223 INFO L290 TraceCheckUtils]: 0: Hoare triple {2130#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~iobase := #in~iobase;~self.base, ~self.offset := #in~self.base, #in~self.offset;havoc ~low~4;havoc ~high~4;havoc ~wTmp~2;havoc ~wTmp1~2;havoc ~ret~0; {1990#true} is VALID [2022-02-20 22:38:50,223 INFO L272 TraceCheckUtils]: 1: Hoare triple {1990#true} call #t~ret159 := ReadReg(~iobase % 65536, 44); {1990#true} is VALID [2022-02-20 22:38:50,223 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,223 INFO L272 TraceCheckUtils]: 3: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,223 INFO L290 TraceCheckUtils]: 4: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,224 INFO L290 TraceCheckUtils]: 5: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,224 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,224 INFO L290 TraceCheckUtils]: 7: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,224 INFO L290 TraceCheckUtils]: 8: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,224 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1990#true} {1990#true} #4188#return; {1990#true} is VALID [2022-02-20 22:38:50,224 INFO L290 TraceCheckUtils]: 10: Hoare triple {1990#true} ~low~4 := #t~ret159;havoc #t~ret159; {1990#true} is VALID [2022-02-20 22:38:50,225 INFO L272 TraceCheckUtils]: 11: Hoare triple {1990#true} call #t~ret160 := ReadReg(~iobase % 65536, 45); {1990#true} is VALID [2022-02-20 22:38:50,225 INFO L290 TraceCheckUtils]: 12: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,225 INFO L272 TraceCheckUtils]: 13: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,225 INFO L290 TraceCheckUtils]: 14: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,225 INFO L290 TraceCheckUtils]: 15: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,225 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,226 INFO L290 TraceCheckUtils]: 17: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,226 INFO L290 TraceCheckUtils]: 18: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,226 INFO L284 TraceCheckUtils]: 19: Hoare quadruple {1990#true} {1990#true} #4190#return; {1990#true} is VALID [2022-02-20 22:38:50,226 INFO L290 TraceCheckUtils]: 20: Hoare triple {1990#true} ~high~4 := #t~ret160;havoc #t~ret160;~wTmp1~2 := ~high~4 % 256;~wTmp~2 := (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 0 == ~low~4 % 256 then (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) else (if 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256) then ~low~4 % 256 else (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256)) || ((1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 1 == ~low~4 % 256) then 1 else ~bitwiseOr((if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536), ~low~4 % 256))));call #t~mem161 := read~int(~self.base, 596 + ~self.offset, 4); {1990#true} is VALID [2022-02-20 22:38:50,226 INFO L290 TraceCheckUtils]: 21: Hoare triple {1990#true} assume ~wTmp~2 % 65536 % 4294967296 >= #t~mem161 % 4294967296;havoc #t~mem161;call #t~mem162 := read~int(~self.base, 596 + ~self.offset, 4);~ret~0 := ~wTmp~2 % 65536 - #t~mem162 % 65536;havoc #t~mem162; {1990#true} is VALID [2022-02-20 22:38:50,227 INFO L290 TraceCheckUtils]: 22: Hoare triple {1990#true} call write~int(~wTmp~2 % 65536, ~self.base, 596 + ~self.offset, 4);#res := ~ret~0; {1990#true} is VALID [2022-02-20 22:38:50,227 INFO L290 TraceCheckUtils]: 23: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,227 INFO L284 TraceCheckUtils]: 24: Hoare quadruple {1990#true} {1991#false} #4826#return; {1991#false} is VALID [2022-02-20 22:38:50,227 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 155 [2022-02-20 22:38:50,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:38:50,232 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} assume 2 == ~ldv_spin_NOT_ARG_SIGN~0;#res := 1; {1990#true} is VALID [2022-02-20 22:38:50,233 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,233 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1990#true} {1991#false} #3910#return; {1991#false} is VALID [2022-02-20 22:38:50,235 INFO L290 TraceCheckUtils]: 0: Hoare triple {1990#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(190, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(9, 4);call #Ultimate.allocInit(9, 5);call #Ultimate.allocInit(7, 6);call write~init~int(15, 6, 0, 1);call write~init~int(37, 6, 1, 1);call write~init~int(115, 6, 2, 1);call write~init~int(40, 6, 3, 1);call write~init~int(41, 6, 4, 1);call write~init~int(10, 6, 5, 1);call write~init~int(0, 6, 6, 1);call #Ultimate.allocInit(14, 7);call #Ultimate.allocInit(9, 8);call #Ultimate.allocInit(45, 9);call #Ultimate.allocInit(14, 10);call #Ultimate.allocInit(25, 11);call #Ultimate.allocInit(13, 12);call #Ultimate.allocInit(22, 13);call #Ultimate.allocInit(13, 14);call #Ultimate.allocInit(23, 15);call #Ultimate.allocInit(13, 16);call #Ultimate.allocInit(23, 17);call #Ultimate.allocInit(13, 18);call #Ultimate.allocInit(22, 19);call #Ultimate.allocInit(13, 20);call #Ultimate.allocInit(7, 21);call write~init~int(15, 21, 0, 1);call write~init~int(37, 21, 1, 1);call write~init~int(115, 21, 2, 1);call write~init~int(40, 21, 3, 1);call write~init~int(41, 21, 4, 1);call write~init~int(10, 21, 5, 1);call write~init~int(0, 21, 6, 1);call #Ultimate.allocInit(17, 22);call #Ultimate.allocInit(7, 23);call write~init~int(15, 23, 0, 1);call write~init~int(37, 23, 1, 1);call write~init~int(115, 23, 2, 1);call write~init~int(40, 23, 3, 1);call write~init~int(41, 23, 4, 1);call write~init~int(10, 23, 5, 1);call write~init~int(0, 23, 6, 1);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(22, 25);call #Ultimate.allocInit(35, 26);call #Ultimate.allocInit(14, 27);call #Ultimate.allocInit(40, 28);call #Ultimate.allocInit(7, 29);call write~init~int(15, 29, 0, 1);call write~init~int(37, 29, 1, 1);call write~init~int(115, 29, 2, 1);call write~init~int(40, 29, 3, 1);call write~init~int(41, 29, 4, 1);call write~init~int(10, 29, 5, 1);call write~init~int(0, 29, 6, 1);call #Ultimate.allocInit(15, 30);call #Ultimate.allocInit(30, 31);call #Ultimate.allocInit(15, 32);call #Ultimate.allocInit(7, 33);call write~init~int(15, 33, 0, 1);call write~init~int(37, 33, 1, 1);call write~init~int(115, 33, 2, 1);call write~init~int(40, 33, 3, 1);call write~init~int(41, 33, 4, 1);call write~init~int(10, 33, 5, 1);call write~init~int(0, 33, 6, 1);call #Ultimate.allocInit(12, 34);call #Ultimate.allocInit(85, 35);call #Ultimate.allocInit(47, 36);call #Ultimate.allocInit(29, 37);call #Ultimate.allocInit(58, 38);call #Ultimate.allocInit(29, 39);call #Ultimate.allocInit(50, 40);call #Ultimate.allocInit(29, 41);call #Ultimate.allocInit(40, 42);call #Ultimate.allocInit(29, 43);call #Ultimate.allocInit(30, 44);call #Ultimate.allocInit(22, 45);call #Ultimate.allocInit(31, 46);call #Ultimate.allocInit(28, 47);call #Ultimate.allocInit(23, 48);call #Ultimate.allocInit(13, 49);call #Ultimate.allocInit(45, 50);call #Ultimate.allocInit(18, 51);call #Ultimate.allocInit(7, 52);call write~init~int(15, 52, 0, 1);call write~init~int(37, 52, 1, 1);call write~init~int(115, 52, 2, 1);call write~init~int(40, 52, 3, 1);call write~init~int(41, 52, 4, 1);call write~init~int(10, 52, 5, 1);call write~init~int(0, 52, 6, 1);call #Ultimate.allocInit(27, 53);call #Ultimate.allocInit(56, 54);call #Ultimate.allocInit(27, 55);call #Ultimate.allocInit(7, 56);call write~init~int(15, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(40, 56, 3, 1);call write~init~int(41, 56, 4, 1);call write~init~int(10, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(21, 57);call #Ultimate.allocInit(50, 58);call #Ultimate.allocInit(30, 59);call #Ultimate.allocInit(41, 60);call #Ultimate.allocInit(30, 61);call #Ultimate.allocInit(26, 62);call #Ultimate.allocInit(30, 63);call #Ultimate.allocInit(15, 64);call #Ultimate.allocInit(14, 65);call #Ultimate.allocInit(23, 66);call #Ultimate.allocInit(15, 67);call #Ultimate.allocInit(48, 68);call #Ultimate.allocInit(15, 69);call #Ultimate.allocInit(43, 70);call #Ultimate.allocInit(19, 71);call #Ultimate.allocInit(6, 72);call write~init~int(84, 72, 0, 1);call write~init~int(105, 72, 1, 1);call write~init~int(109, 72, 2, 1);call write~init~int(101, 72, 3, 1);call write~init~int(114, 72, 4, 1);call write~init~int(0, 72, 5, 1);call #Ultimate.allocInit(1, 73);call write~init~int(0, 73, 0, 1);call #Ultimate.allocInit(3, 74);call write~init~int(84, 74, 0, 1);call write~init~int(120, 74, 1, 1);call write~init~int(0, 74, 2, 1);call #Ultimate.allocInit(1, 75);call write~init~int(0, 75, 0, 1);call #Ultimate.allocInit(3, 76);call write~init~int(82, 76, 0, 1);call write~init~int(120, 76, 1, 1);call write~init~int(0, 76, 2, 1);call #Ultimate.allocInit(1, 77);call write~init~int(0, 77, 0, 1);call #Ultimate.allocInit(38, 78);call #Ultimate.allocInit(19, 79);call #Ultimate.allocInit(13, 80);call #Ultimate.allocInit(1, 81);call write~init~int(0, 81, 0, 1);call #Ultimate.allocInit(4, 82);call write~init~int(69, 82, 0, 1);call write~init~int(79, 82, 1, 1);call write~init~int(77, 82, 2, 1);call write~init~int(0, 82, 3, 1);call #Ultimate.allocInit(1, 83);call write~init~int(0, 83, 0, 1);call #Ultimate.allocInit(11, 84);call #Ultimate.allocInit(1, 85);call write~init~int(0, 85, 0, 1);call #Ultimate.allocInit(10, 86);call #Ultimate.allocInit(1, 87);call write~init~int(0, 87, 0, 1);call #Ultimate.allocInit(47, 88);call #Ultimate.allocInit(19, 89);call #Ultimate.allocInit(9, 90);call #Ultimate.allocInit(1, 91);call write~init~int(0, 91, 0, 1);call #Ultimate.allocInit(8, 92);call #Ultimate.allocInit(1, 93);call write~init~int(0, 93, 0, 1);call #Ultimate.allocInit(12, 94);call #Ultimate.allocInit(1, 95);call write~init~int(0, 95, 0, 1);call #Ultimate.allocInit(4, 96);call write~init~int(69, 96, 0, 1);call write~init~int(79, 96, 1, 1);call write~init~int(70, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(1, 97);call write~init~int(0, 97, 0, 1);call #Ultimate.allocInit(7, 98);call write~init~int(82, 98, 0, 1);call write~init~int(120, 98, 1, 1);call write~init~int(68, 98, 2, 1);call write~init~int(97, 98, 3, 1);call write~init~int(116, 98, 4, 1);call write~init~int(97, 98, 5, 1);call write~init~int(0, 98, 6, 1);call #Ultimate.allocInit(1, 99);call write~init~int(0, 99, 0, 1);call #Ultimate.allocInit(9, 100);call #Ultimate.allocInit(1, 101);call write~init~int(0, 101, 0, 1);call #Ultimate.allocInit(8, 102);call #Ultimate.allocInit(1, 103);call write~init~int(0, 103, 0, 1);call #Ultimate.allocInit(17, 104);call #Ultimate.allocInit(19, 105);call #Ultimate.allocInit(79, 106);call #Ultimate.allocInit(19, 107);call #Ultimate.allocInit(7, 108);call write~init~int(15, 108, 0, 1);call write~init~int(37, 108, 1, 1);call write~init~int(115, 108, 2, 1);call write~init~int(40, 108, 3, 1);call write~init~int(41, 108, 4, 1);call write~init~int(10, 108, 5, 1);call write~init~int(0, 108, 6, 1);call #Ultimate.allocInit(8, 109);call #Ultimate.allocInit(31, 110);call #Ultimate.allocInit(28, 111);call #Ultimate.allocInit(22, 112);call #Ultimate.allocInit(13, 113);call #Ultimate.allocInit(22, 114);call #Ultimate.allocInit(22, 115);call #Ultimate.allocInit(7, 116);call write~init~int(15, 116, 0, 1);call write~init~int(37, 116, 1, 1);call write~init~int(115, 116, 2, 1);call write~init~int(40, 116, 3, 1);call write~init~int(41, 116, 4, 1);call write~init~int(10, 116, 5, 1);call write~init~int(0, 116, 6, 1);call #Ultimate.allocInit(18, 117);call #Ultimate.allocInit(31, 118);call #Ultimate.allocInit(28, 119);call #Ultimate.allocInit(18, 120);call #Ultimate.allocInit(12, 121);call #Ultimate.allocInit(31, 122);call #Ultimate.allocInit(28, 123);call #Ultimate.allocInit(18, 124);call #Ultimate.allocInit(13, 125);call #Ultimate.allocInit(32, 126);call #Ultimate.allocInit(32, 127);call #Ultimate.allocInit(33, 128);call #Ultimate.allocInit(11, 129);call #Ultimate.allocInit(7, 130);call write~init~int(15, 130, 0, 1);call write~init~int(37, 130, 1, 1);call write~init~int(115, 130, 2, 1);call write~init~int(40, 130, 3, 1);call write~init~int(41, 130, 4, 1);call write~init~int(10, 130, 5, 1);call write~init~int(0, 130, 6, 1);call #Ultimate.allocInit(19, 131);call #Ultimate.allocInit(31, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(19, 134);call #Ultimate.allocInit(12, 135);call #Ultimate.allocInit(31, 136);call #Ultimate.allocInit(28, 137);call #Ultimate.allocInit(19, 138);call #Ultimate.allocInit(13, 139);call #Ultimate.allocInit(31, 140);call #Ultimate.allocInit(28, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(12, 143);call #Ultimate.allocInit(31, 144);call #Ultimate.allocInit(28, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(13, 147);call #Ultimate.allocInit(23, 148);call #Ultimate.allocInit(19, 149);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(54, 151);call #Ultimate.allocInit(56, 152);call #Ultimate.allocInit(58, 153);call #Ultimate.allocInit(58, 154);call #Ultimate.allocInit(58, 155);call #Ultimate.allocInit(54, 156);call #Ultimate.allocInit(56, 157);call #Ultimate.allocInit(58, 158);call #Ultimate.allocInit(58, 159);call #Ultimate.allocInit(58, 160);call #Ultimate.allocInit(54, 161);call #Ultimate.allocInit(56, 162);call #Ultimate.allocInit(58, 163);call #Ultimate.allocInit(58, 164);call #Ultimate.allocInit(58, 165);call #Ultimate.allocInit(54, 166);call #Ultimate.allocInit(56, 167);call #Ultimate.allocInit(58, 168);call #Ultimate.allocInit(58, 169);call #Ultimate.allocInit(58, 170);call #Ultimate.allocInit(54, 171);call #Ultimate.allocInit(56, 172);call #Ultimate.allocInit(58, 173);call #Ultimate.allocInit(58, 174);call #Ultimate.allocInit(58, 175);call #Ultimate.allocInit(54, 176);call #Ultimate.allocInit(56, 177);call #Ultimate.allocInit(58, 178);call #Ultimate.allocInit(58, 179);call #Ultimate.allocInit(58, 180);call #Ultimate.allocInit(54, 181);call #Ultimate.allocInit(56, 182);call #Ultimate.allocInit(58, 183);call #Ultimate.allocInit(58, 184);call #Ultimate.allocInit(58, 185);call #Ultimate.allocInit(54, 186);call #Ultimate.allocInit(56, 187);call #Ultimate.allocInit(58, 188);call #Ultimate.allocInit(58, 189);call #Ultimate.allocInit(58, 190);call #Ultimate.allocInit(54, 191);call #Ultimate.allocInit(56, 192);call #Ultimate.allocInit(58, 193);call #Ultimate.allocInit(58, 194);call #Ultimate.allocInit(58, 195);call #Ultimate.allocInit(54, 196);call #Ultimate.allocInit(56, 197);call #Ultimate.allocInit(58, 198);call #Ultimate.allocInit(58, 199);call #Ultimate.allocInit(58, 200);call #Ultimate.allocInit(54, 201);call #Ultimate.allocInit(56, 202);call #Ultimate.allocInit(58, 203);call #Ultimate.allocInit(58, 204);call #Ultimate.allocInit(58, 205);call #Ultimate.allocInit(54, 206);call #Ultimate.allocInit(56, 207);call #Ultimate.allocInit(58, 208);call #Ultimate.allocInit(58, 209);call #Ultimate.allocInit(58, 210);call #Ultimate.allocInit(54, 211);call #Ultimate.allocInit(56, 212);call #Ultimate.allocInit(58, 213);call #Ultimate.allocInit(58, 214);call #Ultimate.allocInit(58, 215);call #Ultimate.allocInit(54, 216);call #Ultimate.allocInit(56, 217);call #Ultimate.allocInit(58, 218);call #Ultimate.allocInit(58, 219);call #Ultimate.allocInit(58, 220);call #Ultimate.allocInit(57, 221);call #Ultimate.allocInit(57, 222);call #Ultimate.allocInit(57, 223);call #Ultimate.allocInit(57, 224);call #Ultimate.allocInit(57, 225);call #Ultimate.allocInit(57, 226);call #Ultimate.allocInit(57, 227);call #Ultimate.allocInit(57, 228);call #Ultimate.allocInit(57, 229);call #Ultimate.allocInit(57, 230);call #Ultimate.allocInit(57, 231);call #Ultimate.allocInit(57, 232);call #Ultimate.allocInit(57, 233);call #Ultimate.allocInit(57, 234);call #Ultimate.allocInit(2, 235);call write~init~int(48, 235, 0, 1);call write~init~int(0, 235, 1, 1);call #Ultimate.allocInit(76, 236);~driver_name~0.base, ~driver_name~0.offset := 4, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 237, 0;call #Ultimate.allocInit(192, 237);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#via_driver~0.base, ~#via_driver~0.offset := 238, 0;call #Ultimate.allocInit(301, 238);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(5, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 145 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 153 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 161 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 169 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 177 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 185 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 193 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 201 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 209 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 217 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 237 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 245 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 253 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 261 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 269 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 285 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 293 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 239, 0;call #Ultimate.allocInit(472, 239);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 240, 0;call #Ultimate.allocInit(472, 240);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset := 0, 0;~ldv_0_line_line~0 := 0;~ldv_0_ret_val_default~0 := 0;~ldv_0_thread_thread~0.base, ~ldv_0_thread_thread~0.offset := 0, 0;~ldv_10_ret_default~0 := 0;~ldv_1_container_net_device~0.base, ~ldv_1_container_net_device~0.offset := 0, 0;~ldv_1_container_struct_ifreq_ptr~0.base, ~ldv_1_container_struct_ifreq_ptr~0.offset := 0, 0;~ldv_1_container_struct_sk_buff_ptr~0.base, ~ldv_1_container_struct_sk_buff_ptr~0.offset := 0, 0;~ldv_1_ldv_param_3_2_default~0 := 0;~ldv_2_container_pci_driver~0.base, ~ldv_2_container_pci_driver~0.offset := 0, 0;~ldv_2_resource_dev~0.base, ~ldv_2_resource_dev~0.offset := 0, 0;~#ldv_2_resource_pm_message~0.base, ~#ldv_2_resource_pm_message~0.offset := 241, 0;call #Ultimate.allocInit(4, 241);call write~init~int(0, ~#ldv_2_resource_pm_message~0.base, ~#ldv_2_resource_pm_message~0.offset, 4);~ldv_2_resource_struct_pci_device_id_ptr~0.base, ~ldv_2_resource_struct_pci_device_id_ptr~0.offset := 0, 0;~ldv_2_ret_default~0 := 0;~ldv_statevar_0~0 := 0;~ldv_statevar_1~0 := 0;~ldv_statevar_10~0 := 0;~ldv_statevar_2~0 := 0;~ldv_0_callback_handler~0.base, ~ldv_0_callback_handler~0.offset := #funAddr~via_ircc_interrupt.base, #funAddr~via_ircc_interrupt.offset;~ldv_10_exit_via_ircc_cleanup_default~0.base, ~ldv_10_exit_via_ircc_cleanup_default~0.offset := #funAddr~via_ircc_cleanup.base, #funAddr~via_ircc_cleanup.offset;~ldv_10_init_via_ircc_init_default~0.base, ~ldv_10_init_via_ircc_init_default~0.offset := #funAddr~via_ircc_init.base, #funAddr~via_ircc_init.offset;~ldv_1_callback_ndo_do_ioctl~0.base, ~ldv_1_callback_ndo_do_ioctl~0.offset := #funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset;~ldv_1_callback_ndo_start_xmit~0.base, ~ldv_1_callback_ndo_start_xmit~0.offset := #funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset;~ldv_spin_NOT_ARG_SIGN~0 := 1;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_dma_spin_lock~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_via_ircc_cb~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1; {1990#true} is VALID [2022-02-20 22:38:50,236 INFO L290 TraceCheckUtils]: 1: Hoare triple {1990#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret805#1, main_~tmp~47#1;havoc main_~tmp~47#1;assume { :begin_inline_ldv_initialize } true; {1990#true} is VALID [2022-02-20 22:38:50,236 INFO L290 TraceCheckUtils]: 2: Hoare triple {1990#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_initialize_external_data } true;assume { :begin_inline_ldv_allocate_external_0 } true;havoc ldv_allocate_external_0_#t~ret795#1.base, ldv_allocate_external_0_#t~ret795#1.offset, ldv_allocate_external_0_#t~ret796#1.base, ldv_allocate_external_0_#t~ret796#1.offset, ldv_allocate_external_0_#t~ret797#1.base, ldv_allocate_external_0_#t~ret797#1.offset, ldv_allocate_external_0_#t~ret798#1.base, ldv_allocate_external_0_#t~ret798#1.offset, ldv_allocate_external_0_#t~ret799#1.base, ldv_allocate_external_0_#t~ret799#1.offset; {1990#true} is VALID [2022-02-20 22:38:50,237 INFO L272 TraceCheckUtils]: 3: Hoare triple {1990#true} call ldv_allocate_external_0_#t~ret795#1.base, ldv_allocate_external_0_#t~ret795#1.offset := ldv_malloc(0); {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:38:50,238 INFO L290 TraceCheckUtils]: 4: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,238 INFO L272 TraceCheckUtils]: 5: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,238 INFO L290 TraceCheckUtils]: 6: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,238 INFO L290 TraceCheckUtils]: 7: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,238 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,239 INFO L290 TraceCheckUtils]: 9: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,239 INFO L290 TraceCheckUtils]: 10: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,239 INFO L290 TraceCheckUtils]: 11: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,239 INFO L284 TraceCheckUtils]: 12: Hoare quadruple {1990#true} {1990#true} #4690#return; {1990#true} is VALID [2022-02-20 22:38:50,239 INFO L290 TraceCheckUtils]: 13: Hoare triple {1990#true} ~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset := ldv_allocate_external_0_#t~ret795#1.base, ldv_allocate_external_0_#t~ret795#1.offset;havoc ldv_allocate_external_0_#t~ret795#1.base, ldv_allocate_external_0_#t~ret795#1.offset;~ldv_0_thread_thread~0.base, ~ldv_0_thread_thread~0.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,240 INFO L272 TraceCheckUtils]: 14: Hoare triple {1990#true} call ldv_allocate_external_0_#t~ret796#1.base, ldv_allocate_external_0_#t~ret796#1.offset := ldv_malloc(3027); {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:38:50,240 INFO L290 TraceCheckUtils]: 15: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,241 INFO L272 TraceCheckUtils]: 16: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,241 INFO L290 TraceCheckUtils]: 17: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,241 INFO L290 TraceCheckUtils]: 18: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,241 INFO L284 TraceCheckUtils]: 19: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,241 INFO L290 TraceCheckUtils]: 20: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,241 INFO L290 TraceCheckUtils]: 21: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,242 INFO L290 TraceCheckUtils]: 22: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,242 INFO L284 TraceCheckUtils]: 23: Hoare quadruple {1990#true} {1990#true} #4692#return; {1990#true} is VALID [2022-02-20 22:38:50,242 INFO L290 TraceCheckUtils]: 24: Hoare triple {1990#true} ~ldv_1_container_net_device~0.base, ~ldv_1_container_net_device~0.offset := ldv_allocate_external_0_#t~ret796#1.base, ldv_allocate_external_0_#t~ret796#1.offset;havoc ldv_allocate_external_0_#t~ret796#1.base, ldv_allocate_external_0_#t~ret796#1.offset; {1990#true} is VALID [2022-02-20 22:38:50,243 INFO L272 TraceCheckUtils]: 25: Hoare triple {1990#true} call ldv_allocate_external_0_#t~ret797#1.base, ldv_allocate_external_0_#t~ret797#1.offset := ldv_malloc(37); {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:38:50,243 INFO L290 TraceCheckUtils]: 26: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,243 INFO L272 TraceCheckUtils]: 27: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,243 INFO L290 TraceCheckUtils]: 28: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,243 INFO L290 TraceCheckUtils]: 29: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,243 INFO L284 TraceCheckUtils]: 30: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,244 INFO L290 TraceCheckUtils]: 31: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,244 INFO L290 TraceCheckUtils]: 32: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,244 INFO L290 TraceCheckUtils]: 33: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,244 INFO L284 TraceCheckUtils]: 34: Hoare quadruple {1990#true} {1990#true} #4694#return; {1990#true} is VALID [2022-02-20 22:38:50,244 INFO L290 TraceCheckUtils]: 35: Hoare triple {1990#true} ~ldv_1_container_struct_ifreq_ptr~0.base, ~ldv_1_container_struct_ifreq_ptr~0.offset := ldv_allocate_external_0_#t~ret797#1.base, ldv_allocate_external_0_#t~ret797#1.offset;havoc ldv_allocate_external_0_#t~ret797#1.base, ldv_allocate_external_0_#t~ret797#1.offset; {1990#true} is VALID [2022-02-20 22:38:50,245 INFO L272 TraceCheckUtils]: 36: Hoare triple {1990#true} call ldv_allocate_external_0_#t~ret798#1.base, ldv_allocate_external_0_#t~ret798#1.offset := ldv_malloc(245); {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:38:50,245 INFO L290 TraceCheckUtils]: 37: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,245 INFO L272 TraceCheckUtils]: 38: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,245 INFO L290 TraceCheckUtils]: 39: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,245 INFO L290 TraceCheckUtils]: 40: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,246 INFO L284 TraceCheckUtils]: 41: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,246 INFO L290 TraceCheckUtils]: 42: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,246 INFO L290 TraceCheckUtils]: 43: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,246 INFO L290 TraceCheckUtils]: 44: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,246 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {1990#true} {1990#true} #4696#return; {1990#true} is VALID [2022-02-20 22:38:50,246 INFO L290 TraceCheckUtils]: 46: Hoare triple {1990#true} ~ldv_1_container_struct_sk_buff_ptr~0.base, ~ldv_1_container_struct_sk_buff_ptr~0.offset := ldv_allocate_external_0_#t~ret798#1.base, ldv_allocate_external_0_#t~ret798#1.offset;havoc ldv_allocate_external_0_#t~ret798#1.base, ldv_allocate_external_0_#t~ret798#1.offset; {1990#true} is VALID [2022-02-20 22:38:50,247 INFO L272 TraceCheckUtils]: 47: Hoare triple {1990#true} call ldv_allocate_external_0_#t~ret799#1.base, ldv_allocate_external_0_#t~ret799#1.offset := ldv_malloc(3018); {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:38:50,247 INFO L290 TraceCheckUtils]: 48: Hoare triple {2100#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~1.base, ~res~1.offset;havoc ~tmp~74.base, ~tmp~74.offset;havoc ~tmp___0~23;havoc ~tmp___1~14; {1990#true} is VALID [2022-02-20 22:38:50,247 INFO L272 TraceCheckUtils]: 49: Hoare triple {1990#true} call #t~ret905 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,248 INFO L290 TraceCheckUtils]: 50: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,248 INFO L290 TraceCheckUtils]: 51: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,248 INFO L284 TraceCheckUtils]: 52: Hoare quadruple {1990#true} {1990#true} #3892#return; {1990#true} is VALID [2022-02-20 22:38:50,248 INFO L290 TraceCheckUtils]: 53: Hoare triple {1990#true} assume -2147483648 <= #t~ret905 && #t~ret905 <= 2147483647;~tmp___1~14 := #t~ret905;havoc #t~ret905; {1990#true} is VALID [2022-02-20 22:38:50,248 INFO L290 TraceCheckUtils]: 54: Hoare triple {1990#true} assume !(0 != ~tmp___1~14);#res.base, #res.offset := 0, 0; {1990#true} is VALID [2022-02-20 22:38:50,248 INFO L290 TraceCheckUtils]: 55: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,248 INFO L284 TraceCheckUtils]: 56: Hoare quadruple {1990#true} {1990#true} #4698#return; {1990#true} is VALID [2022-02-20 22:38:50,249 INFO L290 TraceCheckUtils]: 57: Hoare triple {1990#true} ~ldv_2_resource_dev~0.base, ~ldv_2_resource_dev~0.offset := ldv_allocate_external_0_#t~ret799#1.base, ldv_allocate_external_0_#t~ret799#1.offset;havoc ldv_allocate_external_0_#t~ret799#1.base, ldv_allocate_external_0_#t~ret799#1.offset; {1990#true} is VALID [2022-02-20 22:38:50,249 INFO L290 TraceCheckUtils]: 58: Hoare triple {1990#true} assume { :end_inline_ldv_allocate_external_0 } true; {1990#true} is VALID [2022-02-20 22:38:50,249 INFO L290 TraceCheckUtils]: 59: Hoare triple {1990#true} assume { :end_inline_ldv_initialize_external_data } true;~ldv_statevar_10~0 := 7;~ldv_statevar_0~0 := 6;~ldv_statevar_1~0 := 5;~ldv_2_ret_default~0 := 1;~ldv_statevar_2~0 := 20; {2037#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:38:50,250 INFO L272 TraceCheckUtils]: 60: Hoare triple {2037#(= 6 ~ldv_statevar_0~0)} call main_#t~ret805#1 := ldv_undef_int(); {1990#true} is VALID [2022-02-20 22:38:50,250 INFO L290 TraceCheckUtils]: 61: Hoare triple {1990#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet916 && #t~nondet916 <= 2147483647;~tmp~79 := #t~nondet916;havoc #t~nondet916;#res := ~tmp~79; {1990#true} is VALID [2022-02-20 22:38:50,250 INFO L290 TraceCheckUtils]: 62: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,250 INFO L284 TraceCheckUtils]: 63: Hoare quadruple {1990#true} {2037#(= 6 ~ldv_statevar_0~0)} #4700#return; {2037#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:38:50,251 INFO L290 TraceCheckUtils]: 64: Hoare triple {2037#(= 6 ~ldv_statevar_0~0)} assume -2147483648 <= main_#t~ret805#1 && main_#t~ret805#1 <= 2147483647;main_~tmp~47#1 := main_#t~ret805#1;havoc main_#t~ret805#1; {2037#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:38:50,251 INFO L290 TraceCheckUtils]: 65: Hoare triple {2037#(= 6 ~ldv_statevar_0~0)} assume !(0 == main_~tmp~47#1); {2037#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:38:50,252 INFO L290 TraceCheckUtils]: 66: Hoare triple {2037#(= 6 ~ldv_statevar_0~0)} assume 1 == main_~tmp~47#1; {2037#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:38:50,252 INFO L290 TraceCheckUtils]: 67: Hoare triple {2037#(= 6 ~ldv_statevar_0~0)} assume { :begin_inline_ldv_interrupt_interrupt_instance_0 } true;ldv_interrupt_interrupt_instance_0_#in~arg0#1.base, ldv_interrupt_interrupt_instance_0_#in~arg0#1.offset := 0, 0;havoc ldv_interrupt_interrupt_instance_0_#t~ret810#1, ldv_interrupt_interrupt_instance_0_#t~ret811#1, ldv_interrupt_interrupt_instance_0_~arg0#1.base, ldv_interrupt_interrupt_instance_0_~arg0#1.offset, ldv_interrupt_interrupt_instance_0_~tmp~49#1;ldv_interrupt_interrupt_instance_0_~arg0#1.base, ldv_interrupt_interrupt_instance_0_~arg0#1.offset := ldv_interrupt_interrupt_instance_0_#in~arg0#1.base, ldv_interrupt_interrupt_instance_0_#in~arg0#1.offset;havoc ldv_interrupt_interrupt_instance_0_~tmp~49#1; {2037#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:38:50,252 INFO L290 TraceCheckUtils]: 68: Hoare triple {2037#(= 6 ~ldv_statevar_0~0)} assume !(2 == ~ldv_statevar_0~0); {2037#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:38:50,253 INFO L290 TraceCheckUtils]: 69: Hoare triple {2037#(= 6 ~ldv_statevar_0~0)} assume !(4 == ~ldv_statevar_0~0); {2037#(= 6 ~ldv_statevar_0~0)} is VALID [2022-02-20 22:38:50,253 INFO L290 TraceCheckUtils]: 70: Hoare triple {2037#(= 6 ~ldv_statevar_0~0)} assume 5 == ~ldv_statevar_0~0; {1991#false} is VALID [2022-02-20 22:38:50,253 INFO L290 TraceCheckUtils]: 71: Hoare triple {1991#false} assume { :begin_inline_ldv_switch_to_interrupt_context } true; {1991#false} is VALID [2022-02-20 22:38:50,253 INFO L290 TraceCheckUtils]: 72: Hoare triple {1991#false} assume { :end_inline_ldv_switch_to_interrupt_context } true;assume { :begin_inline_ldv_interrupt_instance_handler_0_5 } true;ldv_interrupt_instance_handler_0_5_#in~arg0#1.base, ldv_interrupt_instance_handler_0_5_#in~arg0#1.offset, ldv_interrupt_instance_handler_0_5_#in~arg1#1, ldv_interrupt_instance_handler_0_5_#in~arg2#1.base, ldv_interrupt_instance_handler_0_5_#in~arg2#1.offset := ~ldv_0_callback_handler~0.base, ~ldv_0_callback_handler~0.offset, ~ldv_0_line_line~0, ~ldv_0_data_data~0.base, ~ldv_0_data_data~0.offset;havoc ldv_interrupt_instance_handler_0_5_#res#1;havoc ldv_interrupt_instance_handler_0_5_#t~ret806#1, ldv_interrupt_instance_handler_0_5_~arg0#1.base, ldv_interrupt_instance_handler_0_5_~arg0#1.offset, ldv_interrupt_instance_handler_0_5_~arg1#1, ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset, ldv_interrupt_instance_handler_0_5_~tmp~48#1;ldv_interrupt_instance_handler_0_5_~arg0#1.base, ldv_interrupt_instance_handler_0_5_~arg0#1.offset := ldv_interrupt_instance_handler_0_5_#in~arg0#1.base, ldv_interrupt_instance_handler_0_5_#in~arg0#1.offset;ldv_interrupt_instance_handler_0_5_~arg1#1 := ldv_interrupt_instance_handler_0_5_#in~arg1#1;ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset := ldv_interrupt_instance_handler_0_5_#in~arg2#1.base, ldv_interrupt_instance_handler_0_5_#in~arg2#1.offset;havoc ldv_interrupt_instance_handler_0_5_~tmp~48#1;assume { :begin_inline_via_ircc_interrupt } true;via_ircc_interrupt_#in~dummy#1, via_ircc_interrupt_#in~dev_id#1.base, via_ircc_interrupt_#in~dev_id#1.offset := ldv_interrupt_instance_handler_0_5_~arg1#1, ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset;havoc via_ircc_interrupt_#res#1;havoc via_ircc_interrupt_#t~ret675#1.base, via_ircc_interrupt_#t~ret675#1.offset, via_ircc_interrupt_#t~mem676#1, via_ircc_interrupt_#t~ret677#1, via_ircc_interrupt_#t~nondet678#1, via_ircc_interrupt_#t~ite679#1.base, via_ircc_interrupt_#t~ite679#1.offset, via_ircc_interrupt_#t~ite680#1.base, via_ircc_interrupt_#t~ite680#1.offset, via_ircc_interrupt_#t~ite681#1.base, via_ircc_interrupt_#t~ite681#1.offset, via_ircc_interrupt_#t~mem682#1, via_ircc_interrupt_#t~ret683#1, via_ircc_interrupt_#t~mem684#1, via_ircc_interrupt_#t~ret685#1, via_ircc_interrupt_#t~mem686#1, via_ircc_interrupt_#t~mem687#1, via_ircc_interrupt_#t~mem688#1.base, via_ircc_interrupt_#t~mem688#1.offset, via_ircc_interrupt_#t~ret689#1, via_ircc_interrupt_#t~ret690#1, via_ircc_interrupt_#t~ret691#1, via_ircc_interrupt_#t~ret692#1, via_ircc_interrupt_#t~nondet693#1, via_ircc_interrupt_#t~ite694#1.base, via_ircc_interrupt_#t~ite694#1.offset, via_ircc_interrupt_#t~ite695#1.base, via_ircc_interrupt_#t~ite695#1.offset, via_ircc_interrupt_#t~ite696#1.base, via_ircc_interrupt_#t~ite696#1.offset, via_ircc_interrupt_#t~ite697#1.base, via_ircc_interrupt_#t~ite697#1.offset, via_ircc_interrupt_#t~mem698#1, via_ircc_interrupt_#t~ret699#1, via_ircc_interrupt_#t~mem700#1.base, via_ircc_interrupt_#t~mem700#1.offset, via_ircc_interrupt_#t~ret701#1, via_ircc_interrupt_#t~ret702#1, via_ircc_interrupt_#t~mem703#1, via_ircc_interrupt_#t~ret704#1, via_ircc_interrupt_#t~nondet705#1, via_ircc_interrupt_#t~ite706#1.base, via_ircc_interrupt_#t~ite706#1.offset, via_ircc_interrupt_#t~ite707#1.base, via_ircc_interrupt_#t~ite707#1.offset, via_ircc_interrupt_#t~ite708#1.base, via_ircc_interrupt_#t~ite708#1.offset, via_ircc_interrupt_#t~ite709#1.base, via_ircc_interrupt_#t~ite709#1.offset, via_ircc_interrupt_#t~ite710#1.base, via_ircc_interrupt_#t~ite710#1.offset, via_ircc_interrupt_#t~ite711#1.base, via_ircc_interrupt_#t~ite711#1.offset, via_ircc_interrupt_#t~ite712#1.base, via_ircc_interrupt_#t~ite712#1.offset, via_ircc_interrupt_#t~nondet713#1, via_ircc_interrupt_#t~ret714#1, via_ircc_interrupt_#t~ret715#1, via_ircc_interrupt_#t~ret716#1, via_ircc_interrupt_#t~nondet717#1, via_ircc_interrupt_#t~mem718#1, via_ircc_interrupt_#t~ret719#1, via_ircc_interrupt_~dummy#1, via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset, via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset, via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset, via_ircc_interrupt_~tmp~39#1.base, via_ircc_interrupt_~tmp~39#1.offset, via_ircc_interrupt_~iobase~7#1, via_ircc_interrupt_~iHostIntType~0#1, via_ircc_interrupt_~iRxIntType~0#1, via_ircc_interrupt_~iTxIntType~0#1, via_ircc_interrupt_~tmp___0~13#1, via_ircc_interrupt_~tmp___1~9#1, via_ircc_interrupt_~tmp___2~7#1, via_ircc_interrupt_~tmp___3~4#1, via_ircc_interrupt_~tmp___4~4#1;via_ircc_interrupt_~dummy#1 := via_ircc_interrupt_#in~dummy#1;via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset := via_ircc_interrupt_#in~dev_id#1.base, via_ircc_interrupt_#in~dev_id#1.offset;havoc via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset;havoc via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset;havoc via_ircc_interrupt_~tmp~39#1.base, via_ircc_interrupt_~tmp~39#1.offset;havoc via_ircc_interrupt_~iobase~7#1;havoc via_ircc_interrupt_~iHostIntType~0#1;havoc via_ircc_interrupt_~iRxIntType~0#1;havoc via_ircc_interrupt_~iTxIntType~0#1;havoc via_ircc_interrupt_~tmp___0~13#1;havoc via_ircc_interrupt_~tmp___1~9#1;havoc via_ircc_interrupt_~tmp___2~7#1;havoc via_ircc_interrupt_~tmp___3~4#1;havoc via_ircc_interrupt_~tmp___4~4#1;via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset := via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset; {1991#false} is VALID [2022-02-20 22:38:50,253 INFO L272 TraceCheckUtils]: 73: Hoare triple {1991#false} call via_ircc_interrupt_#t~ret675#1.base, via_ircc_interrupt_#t~ret675#1.offset := netdev_priv(via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset); {1990#true} is VALID [2022-02-20 22:38:50,254 INFO L290 TraceCheckUtils]: 74: Hoare triple {1990#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1990#true} is VALID [2022-02-20 22:38:50,254 INFO L290 TraceCheckUtils]: 75: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,254 INFO L284 TraceCheckUtils]: 76: Hoare quadruple {1990#true} {1991#false} #4736#return; {1991#false} is VALID [2022-02-20 22:38:50,254 INFO L290 TraceCheckUtils]: 77: Hoare triple {1991#false} via_ircc_interrupt_~tmp~39#1.base, via_ircc_interrupt_~tmp~39#1.offset := via_ircc_interrupt_#t~ret675#1.base, via_ircc_interrupt_#t~ret675#1.offset;havoc via_ircc_interrupt_#t~ret675#1.base, via_ircc_interrupt_#t~ret675#1.offset;via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset := via_ircc_interrupt_~tmp~39#1.base, via_ircc_interrupt_~tmp~39#1.offset;call via_ircc_interrupt_#t~mem676#1 := read~int(via_ircc_interrupt_~self~4#1.base, 292 + via_ircc_interrupt_~self~4#1.offset, 4);via_ircc_interrupt_~iobase~7#1 := via_ircc_interrupt_#t~mem676#1;havoc via_ircc_interrupt_#t~mem676#1;assume { :begin_inline_ldv_spin_lock_100 } true;ldv_spin_lock_100_#in~lock#1.base, ldv_spin_lock_100_#in~lock#1.offset := via_ircc_interrupt_~self~4#1.base, 489 + via_ircc_interrupt_~self~4#1.offset;havoc ldv_spin_lock_100_~lock#1.base, ldv_spin_lock_100_~lock#1.offset;ldv_spin_lock_100_~lock#1.base, ldv_spin_lock_100_~lock#1.offset := ldv_spin_lock_100_#in~lock#1.base, ldv_spin_lock_100_#in~lock#1.offset; {1991#false} is VALID [2022-02-20 22:38:50,254 INFO L272 TraceCheckUtils]: 78: Hoare triple {1991#false} call ldv_spin_lock_lock_of_via_ircc_cb(); {2116#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} is VALID [2022-02-20 22:38:50,254 INFO L272 TraceCheckUtils]: 79: Hoare triple {2116#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} call ldv_assert(191, 0, (if 1 == ~ldv_spin_lock_of_via_ircc_cb~0 then 1 else 0)); {1990#true} is VALID [2022-02-20 22:38:50,255 INFO L290 TraceCheckUtils]: 80: Hoare triple {1990#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {1990#true} is VALID [2022-02-20 22:38:50,255 INFO L290 TraceCheckUtils]: 81: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,255 INFO L284 TraceCheckUtils]: 82: Hoare quadruple {1990#true} {2116#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} #4686#return; {1990#true} is VALID [2022-02-20 22:38:50,256 INFO L272 TraceCheckUtils]: 83: Hoare triple {1990#true} call ldv_assume((if 1 == ~ldv_spin_lock_of_via_ircc_cb~0 then 1 else 0)); {1990#true} is VALID [2022-02-20 22:38:50,256 INFO L290 TraceCheckUtils]: 84: Hoare triple {1990#true} ~expression := #in~expression; {1990#true} is VALID [2022-02-20 22:38:50,256 INFO L290 TraceCheckUtils]: 85: Hoare triple {1990#true} assume !(0 == ~expression); {1990#true} is VALID [2022-02-20 22:38:50,257 INFO L290 TraceCheckUtils]: 86: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,257 INFO L284 TraceCheckUtils]: 87: Hoare quadruple {1990#true} {1990#true} #4688#return; {1990#true} is VALID [2022-02-20 22:38:50,257 INFO L290 TraceCheckUtils]: 88: Hoare triple {1990#true} ~ldv_spin_lock_of_via_ircc_cb~0 := 2; {1990#true} is VALID [2022-02-20 22:38:50,257 INFO L290 TraceCheckUtils]: 89: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,258 INFO L284 TraceCheckUtils]: 90: Hoare quadruple {1990#true} {1991#false} #4738#return; {1991#false} is VALID [2022-02-20 22:38:50,259 INFO L290 TraceCheckUtils]: 91: Hoare triple {1991#false} assume { :begin_inline_spin_lock } true;spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset := ldv_spin_lock_100_~lock#1.base, ldv_spin_lock_100_~lock#1.offset;havoc spin_lock_~lock#1.base, spin_lock_~lock#1.offset;spin_lock_~lock#1.base, spin_lock_~lock#1.offset := spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset;assume { :begin_inline__raw_spin_lock } true;_raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset := spin_lock_~lock#1.base, spin_lock_~lock#1.offset;havoc _raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset;_raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset := _raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset; {1991#false} is VALID [2022-02-20 22:38:50,260 INFO L290 TraceCheckUtils]: 92: Hoare triple {1991#false} assume { :end_inline__raw_spin_lock } true; {1991#false} is VALID [2022-02-20 22:38:50,260 INFO L290 TraceCheckUtils]: 93: Hoare triple {1991#false} assume { :end_inline_spin_lock } true; {1991#false} is VALID [2022-02-20 22:38:50,260 INFO L290 TraceCheckUtils]: 94: Hoare triple {1991#false} assume { :end_inline_ldv_spin_lock_100 } true; {1991#false} is VALID [2022-02-20 22:38:50,260 INFO L272 TraceCheckUtils]: 95: Hoare triple {1991#false} call via_ircc_interrupt_#t~ret677#1 := ReadReg(via_ircc_interrupt_~iobase~7#1, 33); {1990#true} is VALID [2022-02-20 22:38:50,260 INFO L290 TraceCheckUtils]: 96: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,260 INFO L272 TraceCheckUtils]: 97: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,260 INFO L290 TraceCheckUtils]: 98: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,261 INFO L290 TraceCheckUtils]: 99: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,261 INFO L284 TraceCheckUtils]: 100: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,261 INFO L290 TraceCheckUtils]: 101: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,261 INFO L290 TraceCheckUtils]: 102: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,262 INFO L284 TraceCheckUtils]: 103: Hoare quadruple {1990#true} {1991#false} #4740#return; {1991#false} is VALID [2022-02-20 22:38:50,262 INFO L290 TraceCheckUtils]: 104: Hoare triple {1991#false} via_ircc_interrupt_~iHostIntType~0#1 := via_ircc_interrupt_#t~ret677#1;havoc via_ircc_interrupt_#t~ret677#1; {1991#false} is VALID [2022-02-20 22:38:50,262 INFO L290 TraceCheckUtils]: 105: Hoare triple {1991#false} assume !(~irda_debug~0 % 4294967296 > 3); {1991#false} is VALID [2022-02-20 22:38:50,262 INFO L290 TraceCheckUtils]: 106: Hoare triple {1991#false} assume !(0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 64)))); {1991#false} is VALID [2022-02-20 22:38:50,262 INFO L290 TraceCheckUtils]: 107: Hoare triple {1991#false} assume !(0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 32)))); {1991#false} is VALID [2022-02-20 22:38:50,262 INFO L290 TraceCheckUtils]: 108: Hoare triple {1991#false} assume 0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 16))); {1991#false} is VALID [2022-02-20 22:38:50,263 INFO L272 TraceCheckUtils]: 109: Hoare triple {1991#false} call via_ircc_interrupt_#t~ret704#1 := ReadReg(via_ircc_interrupt_~iobase~7#1, 39); {1990#true} is VALID [2022-02-20 22:38:50,263 INFO L290 TraceCheckUtils]: 110: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,263 INFO L272 TraceCheckUtils]: 111: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,263 INFO L290 TraceCheckUtils]: 112: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,263 INFO L290 TraceCheckUtils]: 113: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,263 INFO L284 TraceCheckUtils]: 114: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,263 INFO L290 TraceCheckUtils]: 115: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,264 INFO L290 TraceCheckUtils]: 116: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,264 INFO L284 TraceCheckUtils]: 117: Hoare quadruple {1990#true} {1991#false} #4824#return; {1991#false} is VALID [2022-02-20 22:38:50,264 INFO L290 TraceCheckUtils]: 118: Hoare triple {1991#false} via_ircc_interrupt_~iRxIntType~0#1 := via_ircc_interrupt_#t~ret704#1;havoc via_ircc_interrupt_#t~ret704#1; {1991#false} is VALID [2022-02-20 22:38:50,264 INFO L290 TraceCheckUtils]: 119: Hoare triple {1991#false} assume !(~irda_debug~0 % 4294967296 > 3); {1991#false} is VALID [2022-02-20 22:38:50,264 INFO L290 TraceCheckUtils]: 120: Hoare triple {1991#false} assume !(0 == via_ircc_interrupt_~iRxIntType~0#1 % 256 % 4294967296); {1991#false} is VALID [2022-02-20 22:38:50,264 INFO L290 TraceCheckUtils]: 121: Hoare triple {1991#false} assume 0 != (if 0 == via_ircc_interrupt_~iRxIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iRxIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iRxIntType~0#1 % 256, 16)));assume { :begin_inline_via_ircc_dma_receive_complete } true;via_ircc_dma_receive_complete_#in~self#1.base, via_ircc_dma_receive_complete_#in~self#1.offset, via_ircc_dma_receive_complete_#in~iobase#1 := via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset, via_ircc_interrupt_~iobase~7#1;havoc via_ircc_dma_receive_complete_#res#1;havoc via_ircc_dma_receive_complete_#t~mem533#1, via_ircc_dma_receive_complete_#t~mem534#1, via_ircc_dma_receive_complete_#t~ret535#1, via_ircc_dma_receive_complete_#t~ret536#1.base, via_ircc_dma_receive_complete_#t~ret536#1.offset, via_ircc_dma_receive_complete_#t~ret537#1.base, via_ircc_dma_receive_complete_#t~ret537#1.offset, via_ircc_dma_receive_complete_#t~mem538#1, via_ircc_dma_receive_complete_#t~mem539#1.base, via_ircc_dma_receive_complete_#t~mem539#1.offset, via_ircc_dma_receive_complete_#t~mem540#1.base, via_ircc_dma_receive_complete_#t~mem540#1.offset, via_ircc_dma_receive_complete_#t~mem541#1, via_ircc_dma_receive_complete_#t~mem542#1, via_ircc_dma_receive_complete_#t~mem543#1.base, via_ircc_dma_receive_complete_#t~mem543#1.offset, via_ircc_dma_receive_complete_#t~mem544#1.base, via_ircc_dma_receive_complete_#t~mem544#1.offset, via_ircc_dma_receive_complete_#t~mem545#1, via_ircc_dma_receive_complete_#t~mem546#1.base, via_ircc_dma_receive_complete_#t~mem546#1.offset, via_ircc_dma_receive_complete_#t~mem547#1.base, via_ircc_dma_receive_complete_#t~mem547#1.offset, via_ircc_dma_receive_complete_#t~mem548#1.base, via_ircc_dma_receive_complete_#t~mem548#1.offset, via_ircc_dma_receive_complete_#t~mem549#1, via_ircc_dma_receive_complete_#t~mem550#1.base, via_ircc_dma_receive_complete_#t~mem550#1.offset, via_ircc_dma_receive_complete_#t~mem551#1.base, via_ircc_dma_receive_complete_#t~mem551#1.offset, via_ircc_dma_receive_complete_#t~mem552#1, via_ircc_dma_receive_complete_#t~mem553#1.base, via_ircc_dma_receive_complete_#t~mem553#1.offset, via_ircc_dma_receive_complete_#t~ret554#1, via_ircc_dma_receive_complete_#t~ret555#1, via_ircc_dma_receive_complete_#t~ret556#1, via_ircc_dma_receive_complete_#t~nondet557#1, via_ircc_dma_receive_complete_#t~mem558#1, via_ircc_dma_receive_complete_#t~ret559#1, via_ircc_dma_receive_complete_#t~nondet560#1, via_ircc_dma_receive_complete_#t~mem561#1, via_ircc_dma_receive_complete_#t~mem562#1, via_ircc_dma_receive_complete_#t~mem563#1, via_ircc_dma_receive_complete_#t~mem564#1, via_ircc_dma_receive_complete_#t~mem565#1, via_ircc_dma_receive_complete_#t~mem566#1, via_ircc_dma_receive_complete_#t~mem567#1, via_ircc_dma_receive_complete_#t~ret568#1, via_ircc_dma_receive_complete_#t~ret569#1, via_ircc_dma_receive_complete_#t~ret570#1, via_ircc_dma_receive_complete_#t~mem571#1, via_ircc_dma_receive_complete_#t~mem572#1, via_ircc_dma_receive_complete_#t~mem573#1, via_ircc_dma_receive_complete_#t~mem574#1, via_ircc_dma_receive_complete_#t~mem575#1, via_ircc_dma_receive_complete_#t~mem576#1, via_ircc_dma_receive_complete_#t~mem577#1, via_ircc_dma_receive_complete_#t~ret578#1.base, via_ircc_dma_receive_complete_#t~ret578#1.offset, via_ircc_dma_receive_complete_#t~mem579#1.base, via_ircc_dma_receive_complete_#t~mem579#1.offset, via_ircc_dma_receive_complete_#t~short580#1, via_ircc_dma_receive_complete_#t~mem581#1.base, via_ircc_dma_receive_complete_#t~mem581#1.offset, via_ircc_dma_receive_complete_#t~short582#1, via_ircc_dma_receive_complete_#t~mem583#1.base, via_ircc_dma_receive_complete_#t~mem583#1.offset, via_ircc_dma_receive_complete_#t~mem584#1.base, via_ircc_dma_receive_complete_#t~mem584#1.offset, via_ircc_dma_receive_complete_#t~mem585#1, via_ircc_dma_receive_complete_#t~ret586#1.base, via_ircc_dma_receive_complete_#t~ret586#1.offset, via_ircc_dma_receive_complete_#t~mem587#1.base, via_ircc_dma_receive_complete_#t~mem587#1.offset, via_ircc_dma_receive_complete_#t~nondet588#1, via_ircc_dma_receive_complete_#t~mem589#1.base, via_ircc_dma_receive_complete_#t~mem589#1.offset, via_ircc_dma_receive_complete_#t~mem590#1.base, via_ircc_dma_receive_complete_#t~mem590#1.offset, via_ircc_dma_receive_complete_#t~mem591#1.base, via_ircc_dma_receive_complete_#t~mem591#1.offset, via_ircc_dma_receive_complete_#t~mem592#1.base, via_ircc_dma_receive_complete_#t~mem592#1.offset, via_ircc_dma_receive_complete_#t~mem593#1, via_ircc_dma_receive_complete_#t~mem594#1.base, via_ircc_dma_receive_complete_#t~mem594#1.offset, via_ircc_dma_receive_complete_#t~mem595#1.base, via_ircc_dma_receive_complete_#t~mem595#1.offset, via_ircc_dma_receive_complete_#t~mem596#1, via_ircc_dma_receive_complete_#t~mem597#1.base, via_ircc_dma_receive_complete_#t~mem597#1.offset, via_ircc_dma_receive_complete_#t~ret598#1, via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset, via_ircc_dma_receive_complete_~iobase#1, via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset, via_ircc_dma_receive_complete_~skb~0#1.base, via_ircc_dma_receive_complete_~skb~0#1.offset, via_ircc_dma_receive_complete_~len~0#1, via_ircc_dma_receive_complete_~i~8#1, via_ircc_dma_receive_complete_~status~0#1, via_ircc_dma_receive_complete_~tmp~36#1, via_ircc_dma_receive_complete_~tmp___0~11#1, via_ircc_dma_receive_complete_~tmp___1~7#1, via_ircc_dma_receive_complete_~tmp___2~5#1;via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset := via_ircc_dma_receive_complete_#in~self#1.base, via_ircc_dma_receive_complete_#in~self#1.offset;via_ircc_dma_receive_complete_~iobase#1 := via_ircc_dma_receive_complete_#in~iobase#1;havoc via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset;havoc via_ircc_dma_receive_complete_~skb~0#1.base, via_ircc_dma_receive_complete_~skb~0#1.offset;havoc via_ircc_dma_receive_complete_~len~0#1;havoc via_ircc_dma_receive_complete_~i~8#1;havoc via_ircc_dma_receive_complete_~status~0#1;havoc via_ircc_dma_receive_complete_~tmp~36#1;havoc via_ircc_dma_receive_complete_~tmp___0~11#1;havoc via_ircc_dma_receive_complete_~tmp___1~7#1;havoc via_ircc_dma_receive_complete_~tmp___2~5#1;via_ircc_dma_receive_complete_~status~0#1 := 0;call via_ircc_dma_receive_complete_#t~mem533#1 := read~int(via_ircc_dma_receive_complete_~self#1.base, 292 + via_ircc_dma_receive_complete_~self#1.offset, 4);via_ircc_dma_receive_complete_~iobase#1 := via_ircc_dma_receive_complete_#t~mem533#1;havoc via_ircc_dma_receive_complete_#t~mem533#1;via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset := via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset;call via_ircc_dma_receive_complete_#t~mem534#1 := read~int(via_ircc_dma_receive_complete_~self#1.base, 344 + via_ircc_dma_receive_complete_~self#1.offset, 4); {1991#false} is VALID [2022-02-20 22:38:50,265 INFO L290 TraceCheckUtils]: 122: Hoare triple {1991#false} assume via_ircc_dma_receive_complete_#t~mem534#1 % 4294967296 <= 3999999;havoc via_ircc_dma_receive_complete_#t~mem534#1; {1991#false} is VALID [2022-02-20 22:38:50,265 INFO L272 TraceCheckUtils]: 123: Hoare triple {1991#false} call via_ircc_dma_receive_complete_#t~ret535#1 := GetRecvByte(via_ircc_dma_receive_complete_~iobase#1 % 65536, via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset); {2130#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:38:50,265 INFO L290 TraceCheckUtils]: 124: Hoare triple {2130#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~iobase := #in~iobase;~self.base, ~self.offset := #in~self.base, #in~self.offset;havoc ~low~4;havoc ~high~4;havoc ~wTmp~2;havoc ~wTmp1~2;havoc ~ret~0; {1990#true} is VALID [2022-02-20 22:38:50,266 INFO L272 TraceCheckUtils]: 125: Hoare triple {1990#true} call #t~ret159 := ReadReg(~iobase % 65536, 44); {1990#true} is VALID [2022-02-20 22:38:50,266 INFO L290 TraceCheckUtils]: 126: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,266 INFO L272 TraceCheckUtils]: 127: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,266 INFO L290 TraceCheckUtils]: 128: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,266 INFO L290 TraceCheckUtils]: 129: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,267 INFO L284 TraceCheckUtils]: 130: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,267 INFO L290 TraceCheckUtils]: 131: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,267 INFO L290 TraceCheckUtils]: 132: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,267 INFO L284 TraceCheckUtils]: 133: Hoare quadruple {1990#true} {1990#true} #4188#return; {1990#true} is VALID [2022-02-20 22:38:50,267 INFO L290 TraceCheckUtils]: 134: Hoare triple {1990#true} ~low~4 := #t~ret159;havoc #t~ret159; {1990#true} is VALID [2022-02-20 22:38:50,267 INFO L272 TraceCheckUtils]: 135: Hoare triple {1990#true} call #t~ret160 := ReadReg(~iobase % 65536, 45); {1990#true} is VALID [2022-02-20 22:38:50,268 INFO L290 TraceCheckUtils]: 136: Hoare triple {1990#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,268 INFO L272 TraceCheckUtils]: 137: Hoare triple {1990#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1990#true} is VALID [2022-02-20 22:38:50,268 INFO L290 TraceCheckUtils]: 138: Hoare triple {1990#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1990#true} is VALID [2022-02-20 22:38:50,268 INFO L290 TraceCheckUtils]: 139: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,268 INFO L284 TraceCheckUtils]: 140: Hoare quadruple {1990#true} {1990#true} #3952#return; {1990#true} is VALID [2022-02-20 22:38:50,268 INFO L290 TraceCheckUtils]: 141: Hoare triple {1990#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1990#true} is VALID [2022-02-20 22:38:50,268 INFO L290 TraceCheckUtils]: 142: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,269 INFO L284 TraceCheckUtils]: 143: Hoare quadruple {1990#true} {1990#true} #4190#return; {1990#true} is VALID [2022-02-20 22:38:50,269 INFO L290 TraceCheckUtils]: 144: Hoare triple {1990#true} ~high~4 := #t~ret160;havoc #t~ret160;~wTmp1~2 := ~high~4 % 256;~wTmp~2 := (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 0 == ~low~4 % 256 then (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) else (if 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256) then ~low~4 % 256 else (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256)) || ((1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 1 == ~low~4 % 256) then 1 else ~bitwiseOr((if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536), ~low~4 % 256))));call #t~mem161 := read~int(~self.base, 596 + ~self.offset, 4); {1990#true} is VALID [2022-02-20 22:38:50,269 INFO L290 TraceCheckUtils]: 145: Hoare triple {1990#true} assume ~wTmp~2 % 65536 % 4294967296 >= #t~mem161 % 4294967296;havoc #t~mem161;call #t~mem162 := read~int(~self.base, 596 + ~self.offset, 4);~ret~0 := ~wTmp~2 % 65536 - #t~mem162 % 65536;havoc #t~mem162; {1990#true} is VALID [2022-02-20 22:38:50,270 INFO L290 TraceCheckUtils]: 146: Hoare triple {1990#true} call write~int(~wTmp~2 % 65536, ~self.base, 596 + ~self.offset, 4);#res := ~ret~0; {1990#true} is VALID [2022-02-20 22:38:50,271 INFO L290 TraceCheckUtils]: 147: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,271 INFO L284 TraceCheckUtils]: 148: Hoare quadruple {1990#true} {1991#false} #4826#return; {1991#false} is VALID [2022-02-20 22:38:50,271 INFO L290 TraceCheckUtils]: 149: Hoare triple {1991#false} via_ircc_dma_receive_complete_~tmp~36#1 := via_ircc_dma_receive_complete_#t~ret535#1;havoc via_ircc_dma_receive_complete_#t~ret535#1;via_ircc_dma_receive_complete_~len~0#1 := via_ircc_dma_receive_complete_~tmp~36#1 % 65536; {1991#false} is VALID [2022-02-20 22:38:50,271 INFO L272 TraceCheckUtils]: 150: Hoare triple {1991#false} call via_ircc_dma_receive_complete_#t~ret536#1.base, via_ircc_dma_receive_complete_#t~ret536#1.offset := dev_alloc_skb(1 + via_ircc_dma_receive_complete_~len~0#1); {1991#false} is VALID [2022-02-20 22:38:50,271 INFO L290 TraceCheckUtils]: 151: Hoare triple {1991#false} ~length#1 := #in~length#1;havoc ~tmp~4#1.base, ~tmp~4#1.offset;assume { :begin_inline_netdev_alloc_skb } true;netdev_alloc_skb_#in~dev#1.base, netdev_alloc_skb_#in~dev#1.offset, netdev_alloc_skb_#in~length#1 := 0, 0, ~length#1;havoc netdev_alloc_skb_#res#1.base, netdev_alloc_skb_#res#1.offset;havoc netdev_alloc_skb_#t~ret57#1.base, netdev_alloc_skb_#t~ret57#1.offset, netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset, netdev_alloc_skb_~length#1, netdev_alloc_skb_~tmp~3#1.base, netdev_alloc_skb_~tmp~3#1.offset;netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset := netdev_alloc_skb_#in~dev#1.base, netdev_alloc_skb_#in~dev#1.offset;netdev_alloc_skb_~length#1 := netdev_alloc_skb_#in~length#1;havoc netdev_alloc_skb_~tmp~3#1.base, netdev_alloc_skb_~tmp~3#1.offset;assume { :begin_inline_ldv___netdev_alloc_skb_57 } true;ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_57_#in~ldv_func_arg2#1, ldv___netdev_alloc_skb_57_#in~flags#1 := netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset, netdev_alloc_skb_~length#1, 32;havoc ldv___netdev_alloc_skb_57_#res#1.base, ldv___netdev_alloc_skb_57_#res#1.offset;havoc ldv___netdev_alloc_skb_57_#t~ret871#1.base, ldv___netdev_alloc_skb_57_#t~ret871#1.offset, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_57_~ldv_func_arg2#1, ldv___netdev_alloc_skb_57_~flags#1, ldv___netdev_alloc_skb_57_~tmp~60#1.base, ldv___netdev_alloc_skb_57_~tmp~60#1.offset;ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.offset := ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.offset;ldv___netdev_alloc_skb_57_~ldv_func_arg2#1 := ldv___netdev_alloc_skb_57_#in~ldv_func_arg2#1;ldv___netdev_alloc_skb_57_~flags#1 := ldv___netdev_alloc_skb_57_#in~flags#1;havoc ldv___netdev_alloc_skb_57_~tmp~60#1.base, ldv___netdev_alloc_skb_57_~tmp~60#1.offset; {1991#false} is VALID [2022-02-20 22:38:50,271 INFO L272 TraceCheckUtils]: 152: Hoare triple {1991#false} call ldv_check_alloc_flags(ldv___netdev_alloc_skb_57_~flags#1); {1991#false} is VALID [2022-02-20 22:38:50,272 INFO L290 TraceCheckUtils]: 153: Hoare triple {1991#false} ~flags#1 := #in~flags#1;havoc ~tmp~66#1; {1991#false} is VALID [2022-02-20 22:38:50,272 INFO L290 TraceCheckUtils]: 154: Hoare triple {1991#false} assume 32 != ~flags#1 % 4294967296 && 0 != ~flags#1 % 4294967296; {1991#false} is VALID [2022-02-20 22:38:50,272 INFO L272 TraceCheckUtils]: 155: Hoare triple {1991#false} call #t~ret880#1 := ldv_exclusive_spin_is_locked(); {1990#true} is VALID [2022-02-20 22:38:50,272 INFO L290 TraceCheckUtils]: 156: Hoare triple {1990#true} assume 2 == ~ldv_spin_NOT_ARG_SIGN~0;#res := 1; {1990#true} is VALID [2022-02-20 22:38:50,272 INFO L290 TraceCheckUtils]: 157: Hoare triple {1990#true} assume true; {1990#true} is VALID [2022-02-20 22:38:50,272 INFO L284 TraceCheckUtils]: 158: Hoare quadruple {1990#true} {1991#false} #3910#return; {1991#false} is VALID [2022-02-20 22:38:50,272 INFO L290 TraceCheckUtils]: 159: Hoare triple {1991#false} assume -2147483648 <= #t~ret880#1 && #t~ret880#1 <= 2147483647;~tmp~66#1 := #t~ret880#1;havoc #t~ret880#1;assume { :begin_inline_ldv_assert_linux_alloc_spinlock__wrong_flags } true;ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1 := (if 0 == ~tmp~66#1 then 1 else 0);havoc ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1;ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1 := ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1; {1991#false} is VALID [2022-02-20 22:38:50,273 INFO L290 TraceCheckUtils]: 160: Hoare triple {1991#false} assume 0 == ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1; {1991#false} is VALID [2022-02-20 22:38:50,273 INFO L290 TraceCheckUtils]: 161: Hoare triple {1991#false} assume !false; {1991#false} is VALID [2022-02-20 22:38:50,275 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2022-02-20 22:38:50,276 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:38:50,276 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794771802] [2022-02-20 22:38:50,276 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1794771802] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:38:50,277 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:38:50,277 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-02-20 22:38:50,279 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855832367] [2022-02-20 22:38:50,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:38:50,284 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 13.8) internal successors, (69), 3 states have internal predecessors, (69), 4 states have call successors, (20), 5 states have call predecessors, (20), 1 states have return successors, (18), 3 states have call predecessors, (18), 4 states have call successors, (18) Word has length 162 [2022-02-20 22:38:50,286 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:38:50,289 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 6 states, 5 states have (on average 13.8) internal successors, (69), 3 states have internal predecessors, (69), 4 states have call successors, (20), 5 states have call predecessors, (20), 1 states have return successors, (18), 3 states have call predecessors, (18), 4 states have call successors, (18) [2022-02-20 22:38:50,414 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 107 edges. 107 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:38:50,415 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-02-20 22:38:50,415 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:38:50,435 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-02-20 22:38:50,436 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-02-20 22:38:50,452 INFO L87 Difference]: Start difference. First operand has 1987 states, 1235 states have (on average 1.3036437246963564) internal successors, (1610), 1259 states have internal predecessors, (1610), 660 states have call successors, (660), 92 states have call predecessors, (660), 91 states have return successors, (656), 644 states have call predecessors, (656), 656 states have call successors, (656) Second operand has 6 states, 5 states have (on average 13.8) internal successors, (69), 3 states have internal predecessors, (69), 4 states have call successors, (20), 5 states have call predecessors, (20), 1 states have return successors, (18), 3 states have call predecessors, (18), 4 states have call successors, (18) [2022-02-20 22:39:00,344 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.05s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:39:41,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:39:41,720 INFO L93 Difference]: Finished difference Result 5598 states and 8413 transitions. [2022-02-20 22:39:41,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-02-20 22:39:41,721 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 13.8) internal successors, (69), 3 states have internal predecessors, (69), 4 states have call successors, (20), 5 states have call predecessors, (20), 1 states have return successors, (18), 3 states have call predecessors, (18), 4 states have call successors, (18) Word has length 162 [2022-02-20 22:39:41,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:39:41,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 5 states have (on average 13.8) internal successors, (69), 3 states have internal predecessors, (69), 4 states have call successors, (20), 5 states have call predecessors, (20), 1 states have return successors, (18), 3 states have call predecessors, (18), 4 states have call successors, (18) [2022-02-20 22:39:42,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 8413 transitions. [2022-02-20 22:39:42,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 5 states have (on average 13.8) internal successors, (69), 3 states have internal predecessors, (69), 4 states have call successors, (20), 5 states have call predecessors, (20), 1 states have return successors, (18), 3 states have call predecessors, (18), 4 states have call successors, (18) [2022-02-20 22:39:42,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 8413 transitions. [2022-02-20 22:39:42,812 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 13 states and 8413 transitions. [2022-02-20 22:39:49,183 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 8413 edges. 8413 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:39:49,961 INFO L225 Difference]: With dead ends: 5598 [2022-02-20 22:39:49,961 INFO L226 Difference]: Without dead ends: 3551 [2022-02-20 22:39:49,976 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 56 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=67, Invalid=143, Unknown=0, NotChecked=0, Total=210 [2022-02-20 22:39:49,978 INFO L933 BasicCegarLoop]: 2592 mSDtfsCounter, 5728 mSDsluCounter, 2479 mSDsCounter, 0 mSdLazyCounter, 5191 mSolverCounterSat, 6558 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 19.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5919 SdHoareTripleChecker+Valid, 5071 SdHoareTripleChecker+Invalid, 11749 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 6558 IncrementalHoareTripleChecker+Valid, 5191 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 19.3s IncrementalHoareTripleChecker+Time [2022-02-20 22:39:49,979 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [5919 Valid, 5071 Invalid, 11749 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [6558 Valid, 5191 Invalid, 0 Unknown, 0 Unchecked, 19.3s Time] [2022-02-20 22:39:49,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3551 states. [2022-02-20 22:39:50,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3551 to 3510. [2022-02-20 22:39:50,192 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:39:50,202 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3551 states. Second operand has 3510 states, 2186 states have (on average 1.2598353156450137) internal successors, (2754), 2236 states have internal predecessors, (2754), 1149 states have call successors, (1149), 166 states have call predecessors, (1149), 174 states have return successors, (1183), 1127 states have call predecessors, (1183), 1149 states have call successors, (1183) [2022-02-20 22:39:50,211 INFO L74 IsIncluded]: Start isIncluded. First operand 3551 states. Second operand has 3510 states, 2186 states have (on average 1.2598353156450137) internal successors, (2754), 2236 states have internal predecessors, (2754), 1149 states have call successors, (1149), 166 states have call predecessors, (1149), 174 states have return successors, (1183), 1127 states have call predecessors, (1183), 1149 states have call successors, (1183) [2022-02-20 22:39:50,220 INFO L87 Difference]: Start difference. First operand 3551 states. Second operand has 3510 states, 2186 states have (on average 1.2598353156450137) internal successors, (2754), 2236 states have internal predecessors, (2754), 1149 states have call successors, (1149), 166 states have call predecessors, (1149), 174 states have return successors, (1183), 1127 states have call predecessors, (1183), 1149 states have call successors, (1183) [2022-02-20 22:39:50,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:39:50,681 INFO L93 Difference]: Finished difference Result 3551 states and 5150 transitions. [2022-02-20 22:39:50,681 INFO L276 IsEmpty]: Start isEmpty. Operand 3551 states and 5150 transitions. [2022-02-20 22:39:50,701 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:39:50,701 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:39:50,709 INFO L74 IsIncluded]: Start isIncluded. First operand has 3510 states, 2186 states have (on average 1.2598353156450137) internal successors, (2754), 2236 states have internal predecessors, (2754), 1149 states have call successors, (1149), 166 states have call predecessors, (1149), 174 states have return successors, (1183), 1127 states have call predecessors, (1183), 1149 states have call successors, (1183) Second operand 3551 states. [2022-02-20 22:39:50,716 INFO L87 Difference]: Start difference. First operand has 3510 states, 2186 states have (on average 1.2598353156450137) internal successors, (2754), 2236 states have internal predecessors, (2754), 1149 states have call successors, (1149), 166 states have call predecessors, (1149), 174 states have return successors, (1183), 1127 states have call predecessors, (1183), 1149 states have call successors, (1183) Second operand 3551 states. [2022-02-20 22:39:51,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:39:51,231 INFO L93 Difference]: Finished difference Result 3551 states and 5150 transitions. [2022-02-20 22:39:51,231 INFO L276 IsEmpty]: Start isEmpty. Operand 3551 states and 5150 transitions. [2022-02-20 22:39:51,253 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:39:51,253 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:39:51,253 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:39:51,254 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:39:51,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3510 states, 2186 states have (on average 1.2598353156450137) internal successors, (2754), 2236 states have internal predecessors, (2754), 1149 states have call successors, (1149), 166 states have call predecessors, (1149), 174 states have return successors, (1183), 1127 states have call predecessors, (1183), 1149 states have call successors, (1183)