./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-challenges/linux-3.14_linux-alloc-spinlock_drivers-net-ethernet-3com-3c59x.cil.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-challenges/linux-3.14_linux-alloc-spinlock_drivers-net-ethernet-3com-3c59x.cil.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 004fcd1800da3fcc8c5839d85d0662ed24df5100e10ec8a5024be56f561eab28 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 23:12:24,287 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 23:12:24,289 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 23:12:24,324 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 23:12:24,324 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 23:12:24,327 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 23:12:24,328 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 23:12:24,330 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 23:12:24,331 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 23:12:24,335 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 23:12:24,336 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 23:12:24,337 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 23:12:24,337 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 23:12:24,339 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 23:12:24,340 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 23:12:24,342 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 23:12:24,343 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 23:12:24,344 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 23:12:24,345 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 23:12:24,349 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 23:12:24,350 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 23:12:24,351 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 23:12:24,352 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 23:12:24,353 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 23:12:24,358 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 23:12:24,358 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 23:12:24,358 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 23:12:24,359 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 23:12:24,360 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 23:12:24,360 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 23:12:24,361 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 23:12:24,361 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 23:12:24,363 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 23:12:24,364 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 23:12:24,365 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 23:12:24,365 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 23:12:24,365 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 23:12:24,366 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 23:12:24,366 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 23:12:24,366 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 23:12:24,367 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 23:12:24,367 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 23:12:24,391 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 23:12:24,392 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 23:12:24,392 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 23:12:24,392 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 23:12:24,393 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 23:12:24,393 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 23:12:24,393 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 23:12:24,394 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 23:12:24,394 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 23:12:24,394 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 23:12:24,395 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 23:12:24,395 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 23:12:24,395 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 23:12:24,395 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 23:12:24,395 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 23:12:24,395 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 23:12:24,395 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 23:12:24,396 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 23:12:24,396 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 23:12:24,396 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 23:12:24,396 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 23:12:24,396 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 23:12:24,397 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 23:12:24,397 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 23:12:24,398 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 23:12:24,398 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 23:12:24,398 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 23:12:24,398 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 23:12:24,398 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 23:12:24,399 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 23:12:24,399 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 004fcd1800da3fcc8c5839d85d0662ed24df5100e10ec8a5024be56f561eab28 [2022-02-20 23:12:24,579 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 23:12:24,600 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 23:12:24,602 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 23:12:24,602 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 23:12:24,605 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 23:12:24,606 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-challenges/linux-3.14_linux-alloc-spinlock_drivers-net-ethernet-3com-3c59x.cil.i [2022-02-20 23:12:24,649 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6991e5c71/d680795a22904d558e1f56f4ee8569b6/FLAG62ffcfc68 [2022-02-20 23:12:25,312 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 23:12:25,313 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-challenges/linux-3.14_linux-alloc-spinlock_drivers-net-ethernet-3com-3c59x.cil.i [2022-02-20 23:12:25,361 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6991e5c71/d680795a22904d558e1f56f4ee8569b6/FLAG62ffcfc68 [2022-02-20 23:12:25,402 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6991e5c71/d680795a22904d558e1f56f4ee8569b6 [2022-02-20 23:12:25,405 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 23:12:25,407 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 23:12:25,409 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 23:12:25,409 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 23:12:25,412 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 23:12:25,412 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 11:12:25" (1/1) ... [2022-02-20 23:12:25,414 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@96828f5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:25, skipping insertion in model container [2022-02-20 23:12:25,414 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 11:12:25" (1/1) ... [2022-02-20 23:12:25,419 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 23:12:25,531 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 23:12:27,706 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-challenges/linux-3.14_linux-alloc-spinlock_drivers-net-ethernet-3com-3c59x.cil.i[452511,452524] [2022-02-20 23:12:27,709 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-challenges/linux-3.14_linux-alloc-spinlock_drivers-net-ethernet-3com-3c59x.cil.i[452656,452669] [2022-02-20 23:12:27,731 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 23:12:27,793 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 23:12:28,238 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-challenges/linux-3.14_linux-alloc-spinlock_drivers-net-ethernet-3com-3c59x.cil.i[452511,452524] [2022-02-20 23:12:28,238 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-challenges/linux-3.14_linux-alloc-spinlock_drivers-net-ethernet-3com-3c59x.cil.i[452656,452669] [2022-02-20 23:12:28,246 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 23:12:28,439 INFO L208 MainTranslator]: Completed translation [2022-02-20 23:12:28,440 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28 WrapperNode [2022-02-20 23:12:28,440 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 23:12:28,441 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 23:12:28,441 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 23:12:28,441 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 23:12:28,445 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:28,595 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:28,839 INFO L137 Inliner]: procedures = 548, calls = 4417, calls flagged for inlining = 251, calls inlined = 230, statements flattened = 8995 [2022-02-20 23:12:28,840 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 23:12:28,840 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 23:12:28,840 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 23:12:28,841 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 23:12:28,846 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:28,846 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:28,886 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:28,887 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:29,027 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:29,051 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:29,156 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:29,203 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 23:12:29,204 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 23:12:29,204 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 23:12:29,205 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 23:12:29,206 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (1/1) ... [2022-02-20 23:12:29,210 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 23:12:29,216 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 23:12:29,226 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 23:12:29,239 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 23:12:29,259 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_mod_timer_122 [2022-02-20 23:12:29,260 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_mod_timer_122 [2022-02-20 23:12:29,260 INFO L130 BoogieDeclarations]: Found specification of procedure pci_release_regions [2022-02-20 23:12:29,260 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_release_regions [2022-02-20 23:12:29,260 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2022-02-20 23:12:29,260 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2022-02-20 23:12:29,260 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_alloc_skb [2022-02-20 23:12:29,260 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_alloc_skb [2022-02-20 23:12:29,260 INFO L130 BoogieDeclarations]: Found specification of procedure netif_device_present [2022-02-20 23:12:29,260 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_device_present [2022-02-20 23:12:29,261 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_nway_reset [2022-02-20 23:12:29,261 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_nway_reset [2022-02-20 23:12:29,261 INFO L130 BoogieDeclarations]: Found specification of procedure netif_wake_queue [2022-02-20 23:12:29,261 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_wake_queue [2022-02-20 23:12:29,261 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_88 [2022-02-20 23:12:29,261 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_88 [2022-02-20 23:12:29,261 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_mod_timer_107 [2022-02-20 23:12:29,261 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_mod_timer_107 [2022-02-20 23:12:29,262 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 23:12:29,262 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 23:12:29,262 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2022-02-20 23:12:29,262 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2022-02-20 23:12:29,262 INFO L130 BoogieDeclarations]: Found specification of procedure set_8021q_mode [2022-02-20 23:12:29,262 INFO L138 BoogieDeclarations]: Found implementation of procedure set_8021q_mode [2022-02-20 23:12:29,262 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_remove_one [2022-02-20 23:12:29,262 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_remove_one [2022-02-20 23:12:29,262 INFO L130 BoogieDeclarations]: Found specification of procedure arch_local_irq_restore [2022-02-20 23:12:29,263 INFO L138 BoogieDeclarations]: Found implementation of procedure arch_local_irq_restore [2022-02-20 23:12:29,263 INFO L130 BoogieDeclarations]: Found specification of procedure issue_and_wait [2022-02-20 23:12:29,263 INFO L138 BoogieDeclarations]: Found implementation of procedure issue_and_wait [2022-02-20 23:12:29,263 INFO L130 BoogieDeclarations]: Found specification of procedure valid_dma_direction [2022-02-20 23:12:29,263 INFO L138 BoogieDeclarations]: Found implementation of procedure valid_dma_direction [2022-02-20 23:12:29,263 INFO L130 BoogieDeclarations]: Found specification of procedure iowrite16 [2022-02-20 23:12:29,263 INFO L138 BoogieDeclarations]: Found implementation of procedure iowrite16 [2022-02-20 23:12:29,263 INFO L130 BoogieDeclarations]: Found specification of procedure iowrite8 [2022-02-20 23:12:29,263 INFO L138 BoogieDeclarations]: Found implementation of procedure iowrite8 [2022-02-20 23:12:29,263 INFO L130 BoogieDeclarations]: Found specification of procedure window_write32 [2022-02-20 23:12:29,264 INFO L138 BoogieDeclarations]: Found implementation of procedure window_write32 [2022-02-20 23:12:29,264 INFO L130 BoogieDeclarations]: Found specification of procedure ioread32 [2022-02-20 23:12:29,264 INFO L138 BoogieDeclarations]: Found implementation of procedure ioread32 [2022-02-20 23:12:29,264 INFO L130 BoogieDeclarations]: Found specification of procedure pci_name [2022-02-20 23:12:29,264 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_name [2022-02-20 23:12:29,264 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_timer_timer_instance_5 [2022-02-20 23:12:29,264 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_timer_timer_instance_5 [2022-02-20 23:12:29,264 INFO L130 BoogieDeclarations]: Found specification of procedure spinlock_check [2022-02-20 23:12:29,264 INFO L138 BoogieDeclarations]: Found implementation of procedure spinlock_check [2022-02-20 23:12:29,265 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_window_lock_of_vortex_private [2022-02-20 23:12:29,265 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_window_lock_of_vortex_private [2022-02-20 23:12:29,265 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_lock_of_vortex_private [2022-02-20 23:12:29,265 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_lock_of_vortex_private [2022-02-20 23:12:29,265 INFO L130 BoogieDeclarations]: Found specification of procedure window_set [2022-02-20 23:12:29,265 INFO L138 BoogieDeclarations]: Found implementation of procedure window_set [2022-02-20 23:12:29,265 INFO L130 BoogieDeclarations]: Found specification of procedure pci_get_drvdata [2022-02-20 23:12:29,265 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_get_drvdata [2022-02-20 23:12:29,265 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_xmalloc [2022-02-20 23:12:29,266 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_xmalloc [2022-02-20 23:12:29,266 INFO L130 BoogieDeclarations]: Found specification of procedure strlcpy [2022-02-20 23:12:29,266 INFO L138 BoogieDeclarations]: Found implementation of procedure strlcpy [2022-02-20 23:12:29,266 INFO L130 BoogieDeclarations]: Found specification of procedure iowrite32 [2022-02-20 23:12:29,266 INFO L138 BoogieDeclarations]: Found implementation of procedure iowrite32 [2022-02-20 23:12:29,266 INFO L130 BoogieDeclarations]: Found specification of procedure skb_end_pointer [2022-02-20 23:12:29,266 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_end_pointer [2022-02-20 23:12:29,266 INFO L130 BoogieDeclarations]: Found specification of procedure netif_rx [2022-02-20 23:12:29,267 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_rx [2022-02-20 23:12:29,267 INFO L130 BoogieDeclarations]: Found specification of procedure eth_validate_addr [2022-02-20 23:12:29,267 INFO L138 BoogieDeclarations]: Found implementation of procedure eth_validate_addr [2022-02-20 23:12:29,267 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_is_err [2022-02-20 23:12:29,267 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_is_err [2022-02-20 23:12:29,267 INFO L130 BoogieDeclarations]: Found specification of procedure arch_irqs_disabled_flags [2022-02-20 23:12:29,267 INFO L138 BoogieDeclarations]: Found implementation of procedure arch_irqs_disabled_flags [2022-02-20 23:12:29,267 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2022-02-20 23:12:29,267 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2022-02-20 23:12:29,268 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_timer_instance_callback_5_2 [2022-02-20 23:12:29,268 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_timer_instance_callback_5_2 [2022-02-20 23:12:29,268 INFO L130 BoogieDeclarations]: Found specification of procedure pci_unmap_single [2022-02-20 23:12:29,268 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_unmap_single [2022-02-20 23:12:29,268 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 23:12:29,268 INFO L130 BoogieDeclarations]: Found specification of procedure skb_tx_timestamp [2022-02-20 23:12:29,268 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_tx_timestamp [2022-02-20 23:12:29,268 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_del_timer_sync [2022-02-20 23:12:29,268 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_del_timer_sync [2022-02-20 23:12:29,268 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_get_tx_queue [2022-02-20 23:12:29,269 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_get_tx_queue [2022-02-20 23:12:29,269 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_118 [2022-02-20 23:12:29,269 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_118 [2022-02-20 23:12:29,269 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock [2022-02-20 23:12:29,269 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock [2022-02-20 23:12:29,269 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_114 [2022-02-20 23:12:29,269 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_114 [2022-02-20 23:12:29,269 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2022-02-20 23:12:29,269 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_tx_timeout [2022-02-20 23:12:29,270 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_tx_timeout [2022-02-20 23:12:29,270 INFO L130 BoogieDeclarations]: Found specification of procedure pci_save_state [2022-02-20 23:12:29,270 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_save_state [2022-02-20 23:12:29,270 INFO L130 BoogieDeclarations]: Found specification of procedure ioport_map [2022-02-20 23:12:29,270 INFO L138 BoogieDeclarations]: Found implementation of procedure ioport_map [2022-02-20 23:12:29,270 INFO L130 BoogieDeclarations]: Found specification of procedure get_dma_ops [2022-02-20 23:12:29,270 INFO L138 BoogieDeclarations]: Found implementation of procedure get_dma_ops [2022-02-20 23:12:29,270 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_unregister_netdev [2022-02-20 23:12:29,270 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_unregister_netdev [2022-02-20 23:12:29,271 INFO L130 BoogieDeclarations]: Found specification of procedure __raw_spin_lock_init [2022-02-20 23:12:29,271 INFO L138 BoogieDeclarations]: Found implementation of procedure __raw_spin_lock_init [2022-02-20 23:12:29,271 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2022-02-20 23:12:29,271 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irq_106 [2022-02-20 23:12:29,271 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irq_106 [2022-02-20 23:12:29,271 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assume [2022-02-20 23:12:29,271 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assume [2022-02-20 23:12:29,271 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 23:12:29,271 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_interrupt [2022-02-20 23:12:29,271 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_interrupt [2022-02-20 23:12:29,272 INFO L130 BoogieDeclarations]: Found specification of procedure set_rx_mode [2022-02-20 23:12:29,272 INFO L138 BoogieDeclarations]: Found implementation of procedure set_rx_mode [2022-02-20 23:12:29,272 INFO L130 BoogieDeclarations]: Found specification of procedure __phys_addr [2022-02-20 23:12:29,272 INFO L138 BoogieDeclarations]: Found implementation of procedure __phys_addr [2022-02-20 23:12:29,272 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2022-02-20 23:12:29,272 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2022-02-20 23:12:29,272 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_switch_to_interrupt_context [2022-02-20 23:12:29,272 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_switch_to_interrupt_context [2022-02-20 23:12:29,272 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2022-02-20 23:12:29,273 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2022-02-20 23:12:29,273 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_err_code [2022-02-20 23:12:29,273 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_err_code [2022-02-20 23:12:29,273 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_alloc_flags [2022-02-20 23:12:29,273 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_alloc_flags [2022-02-20 23:12:29,273 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_set_duplex [2022-02-20 23:12:29,273 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_set_duplex [2022-02-20 23:12:29,273 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_bh_132 [2022-02-20 23:12:29,273 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_bh_132 [2022-02-20 23:12:29,274 INFO L130 BoogieDeclarations]: Found specification of procedure pci_iomap [2022-02-20 23:12:29,274 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_iomap [2022-02-20 23:12:29,274 INFO L130 BoogieDeclarations]: Found specification of procedure pci_free_consistent [2022-02-20 23:12:29,274 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_free_consistent [2022-02-20 23:12:29,274 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_error [2022-02-20 23:12:29,274 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_error [2022-02-20 23:12:29,274 INFO L130 BoogieDeclarations]: Found specification of procedure pci_disable_device [2022-02-20 23:12:29,274 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_disable_device [2022-02-20 23:12:29,274 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_close [2022-02-20 23:12:29,275 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_close [2022-02-20 23:12:29,275 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 23:12:29,275 INFO L130 BoogieDeclarations]: Found specification of procedure arch_local_irq_save [2022-02-20 23:12:29,275 INFO L138 BoogieDeclarations]: Found implementation of procedure arch_local_irq_save [2022-02-20 23:12:29,275 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_mod_timer [2022-02-20 23:12:29,275 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_mod_timer [2022-02-20 23:12:29,275 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 23:12:29,275 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_int [2022-02-20 23:12:29,275 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_int [2022-02-20 23:12:29,275 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2022-02-20 23:12:29,276 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2022-02-20 23:12:29,276 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-02-20 23:12:29,276 INFO L130 BoogieDeclarations]: Found specification of procedure ioread16 [2022-02-20 23:12:29,276 INFO L138 BoogieDeclarations]: Found implementation of procedure ioread16 [2022-02-20 23:12:29,276 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 23:12:29,276 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 23:12:29,276 INFO L130 BoogieDeclarations]: Found specification of procedure spin_lock_irq [2022-02-20 23:12:29,276 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_lock_irq [2022-02-20 23:12:29,276 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~int [2022-02-20 23:12:29,276 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~int [2022-02-20 23:12:29,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_exclusive_spin_is_locked [2022-02-20 23:12:29,277 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_exclusive_spin_is_locked [2022-02-20 23:12:29,277 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assert [2022-02-20 23:12:29,277 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assert [2022-02-20 23:12:29,277 INFO L130 BoogieDeclarations]: Found specification of procedure acpi_set_WOL [2022-02-20 23:12:29,277 INFO L138 BoogieDeclarations]: Found implementation of procedure acpi_set_WOL [2022-02-20 23:12:29,277 INFO L130 BoogieDeclarations]: Found specification of procedure mod_timer [2022-02-20 23:12:29,277 INFO L138 BoogieDeclarations]: Found implementation of procedure mod_timer [2022-02-20 23:12:29,277 INFO L130 BoogieDeclarations]: Found specification of procedure window_write16 [2022-02-20 23:12:29,277 INFO L138 BoogieDeclarations]: Found implementation of procedure window_write16 [2022-02-20 23:12:29,278 INFO L130 BoogieDeclarations]: Found specification of procedure ioread8 [2022-02-20 23:12:29,278 INFO L138 BoogieDeclarations]: Found implementation of procedure ioread8 [2022-02-20 23:12:29,278 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~~dma_addr_t~0~X~int~X~int~TO~VOID [2022-02-20 23:12:29,278 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~~dma_addr_t~0~X~int~X~int~TO~VOID [2022-02-20 23:12:29,278 INFO L130 BoogieDeclarations]: Found specification of procedure window_read8 [2022-02-20 23:12:29,278 INFO L138 BoogieDeclarations]: Found implementation of procedure window_read8 [2022-02-20 23:12:29,278 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_spin_lock [2022-02-20 23:12:29,278 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_spin_lock [2022-02-20 23:12:29,278 INFO L130 BoogieDeclarations]: Found specification of procedure update_stats [2022-02-20 23:12:29,279 INFO L138 BoogieDeclarations]: Found implementation of procedure update_stats [2022-02-20 23:12:29,279 INFO L130 BoogieDeclarations]: Found specification of procedure warn_slowpath_null [2022-02-20 23:12:29,279 INFO L138 BoogieDeclarations]: Found implementation of procedure warn_slowpath_null [2022-02-20 23:12:29,279 INFO L130 BoogieDeclarations]: Found specification of procedure skb_put [2022-02-20 23:12:29,279 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_put [2022-02-20 23:12:29,279 INFO L130 BoogieDeclarations]: Found specification of procedure poll_vortex [2022-02-20 23:12:29,279 INFO L138 BoogieDeclarations]: Found implementation of procedure poll_vortex [2022-02-20 23:12:29,279 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_netdev [2022-02-20 23:12:29,279 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_netdev [2022-02-20 23:12:29,279 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_window_lock_of_vortex_private [2022-02-20 23:12:29,280 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_window_lock_of_vortex_private [2022-02-20 23:12:29,280 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_check_media [2022-02-20 23:12:29,280 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_check_media [2022-02-20 23:12:29,280 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~int~TO~VOID [2022-02-20 23:12:29,280 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~int~TO~VOID [2022-02-20 23:12:29,280 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2022-02-20 23:12:29,280 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2022-02-20 23:12:29,280 INFO L130 BoogieDeclarations]: Found specification of procedure boomerang_rx [2022-02-20 23:12:29,280 INFO L138 BoogieDeclarations]: Found implementation of procedure boomerang_rx [2022-02-20 23:12:29,281 INFO L130 BoogieDeclarations]: Found specification of procedure arch_local_save_flags [2022-02-20 23:12:29,281 INFO L138 BoogieDeclarations]: Found implementation of procedure arch_local_save_flags [2022-02-20 23:12:29,281 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_open [2022-02-20 23:12:29,281 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_open [2022-02-20 23:12:29,281 INFO L130 BoogieDeclarations]: Found specification of procedure dump_tx_ring [2022-02-20 23:12:29,281 INFO L138 BoogieDeclarations]: Found implementation of procedure dump_tx_ring [2022-02-20 23:12:29,281 INFO L130 BoogieDeclarations]: Found specification of procedure mdio_read [2022-02-20 23:12:29,281 INFO L138 BoogieDeclarations]: Found implementation of procedure mdio_read [2022-02-20 23:12:29,281 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 23:12:29,281 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 23:12:29,282 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_probe1 [2022-02-20 23:12:29,282 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_probe1 [2022-02-20 23:12:29,282 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2022-02-20 23:12:29,282 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2022-02-20 23:12:29,282 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 23:12:29,282 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 23:12:29,282 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_switch_to_process_context [2022-02-20 23:12:29,282 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_switch_to_process_context [2022-02-20 23:12:29,282 INFO L130 BoogieDeclarations]: Found specification of procedure trace_hardirqs_on [2022-02-20 23:12:29,282 INFO L138 BoogieDeclarations]: Found implementation of procedure trace_hardirqs_on [2022-02-20 23:12:29,283 INFO L130 BoogieDeclarations]: Found specification of procedure pci_map_single [2022-02-20 23:12:29,283 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_map_single [2022-02-20 23:12:29,283 INFO L130 BoogieDeclarations]: Found specification of procedure netif_stop_queue [2022-02-20 23:12:29,283 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_stop_queue [2022-02-20 23:12:29,283 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_post_probe [2022-02-20 23:12:29,283 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_post_probe [2022-02-20 23:12:29,283 INFO L130 BoogieDeclarations]: Found specification of procedure consume_skb [2022-02-20 23:12:29,283 INFO L138 BoogieDeclarations]: Found implementation of procedure consume_skb [2022-02-20 23:12:29,283 INFO L130 BoogieDeclarations]: Found specification of procedure netif_start_queue [2022-02-20 23:12:29,283 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_start_queue [2022-02-20 23:12:29,284 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 23:12:29,284 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_111 [2022-02-20 23:12:29,284 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_111 [2022-02-20 23:12:29,284 INFO L130 BoogieDeclarations]: Found specification of procedure trace_hardirqs_off [2022-02-20 23:12:29,284 INFO L138 BoogieDeclarations]: Found implementation of procedure trace_hardirqs_off [2022-02-20 23:12:29,284 INFO L130 BoogieDeclarations]: Found specification of procedure netif_running [2022-02-20 23:12:29,284 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_running [2022-02-20 23:12:29,284 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 23:12:29,284 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_suspend [2022-02-20 23:12:29,284 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_suspend [2022-02-20 23:12:29,285 INFO L130 BoogieDeclarations]: Found specification of procedure boomerang_interrupt [2022-02-20 23:12:29,285 INFO L138 BoogieDeclarations]: Found implementation of procedure boomerang_interrupt [2022-02-20 23:12:29,285 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 23:12:29,285 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 23:12:29,285 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 23:12:29,285 INFO L130 BoogieDeclarations]: Found specification of procedure rx_oom_timer [2022-02-20 23:12:29,285 INFO L138 BoogieDeclarations]: Found implementation of procedure rx_oom_timer [2022-02-20 23:12:29,285 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_pre_probe [2022-02-20 23:12:29,285 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_pre_probe [2022-02-20 23:12:29,286 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_priv [2022-02-20 23:12:29,286 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_priv [2022-02-20 23:12:29,286 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_positive_int [2022-02-20 23:12:29,286 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_positive_int [2022-02-20 23:12:29,286 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq [2022-02-20 23:12:29,286 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq [2022-02-20 23:12:29,286 INFO L130 BoogieDeclarations]: Found specification of procedure dev_kfree_skb_irq [2022-02-20 23:12:29,286 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_kfree_skb_irq [2022-02-20 23:12:29,286 INFO L130 BoogieDeclarations]: Found specification of procedure mdio_sync [2022-02-20 23:12:29,286 INFO L138 BoogieDeclarations]: Found implementation of procedure mdio_sync [2022-02-20 23:12:29,287 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_resume [2022-02-20 23:12:29,287 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_resume [2022-02-20 23:12:29,287 INFO L130 BoogieDeclarations]: Found specification of procedure pci_restore_state [2022-02-20 23:12:29,287 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_restore_state [2022-02-20 23:12:29,287 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reserve [2022-02-20 23:12:29,287 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reserve [2022-02-20 23:12:29,287 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_rx [2022-02-20 23:12:29,287 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_rx [2022-02-20 23:12:29,287 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_irq_105 [2022-02-20 23:12:29,287 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_irq_105 [2022-02-20 23:12:29,288 INFO L130 BoogieDeclarations]: Found specification of procedure netif_tx_start_queue [2022-02-20 23:12:29,288 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_tx_start_queue [2022-02-20 23:12:29,288 INFO L130 BoogieDeclarations]: Found specification of procedure free_netdev [2022-02-20 23:12:29,288 INFO L138 BoogieDeclarations]: Found implementation of procedure free_netdev [2022-02-20 23:12:29,288 INFO L130 BoogieDeclarations]: Found specification of procedure del_timer_sync [2022-02-20 23:12:29,288 INFO L138 BoogieDeclarations]: Found implementation of procedure del_timer_sync [2022-02-20 23:12:29,288 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_bh_133 [2022-02-20 23:12:29,288 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_bh_133 [2022-02-20 23:12:29,288 INFO L130 BoogieDeclarations]: Found specification of procedure constant_test_bit [2022-02-20 23:12:29,288 INFO L138 BoogieDeclarations]: Found implementation of procedure constant_test_bit [2022-02-20 23:12:29,289 INFO L130 BoogieDeclarations]: Found specification of procedure mdio_delay [2022-02-20 23:12:29,289 INFO L138 BoogieDeclarations]: Found implementation of procedure mdio_delay [2022-02-20 23:12:29,289 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_timer [2022-02-20 23:12:29,289 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_timer [2022-02-20 23:12:29,289 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 23:12:29,289 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_down [2022-02-20 23:12:29,289 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_down [2022-02-20 23:12:29,289 INFO L130 BoogieDeclarations]: Found specification of procedure eth_type_trans [2022-02-20 23:12:29,289 INFO L138 BoogieDeclarations]: Found implementation of procedure eth_type_trans [2022-02-20 23:12:29,290 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irq [2022-02-20 23:12:29,290 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irq [2022-02-20 23:12:29,290 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2022-02-20 23:12:29,290 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2022-02-20 23:12:29,290 INFO L130 BoogieDeclarations]: Found specification of procedure window_write8 [2022-02-20 23:12:29,290 INFO L138 BoogieDeclarations]: Found implementation of procedure window_write8 [2022-02-20 23:12:29,290 INFO L130 BoogieDeclarations]: Found specification of procedure window_read32 [2022-02-20 23:12:29,290 INFO L138 BoogieDeclarations]: Found implementation of procedure window_read32 [2022-02-20 23:12:29,290 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dispatch_instance_register_10_2 [2022-02-20 23:12:29,290 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dispatch_instance_register_10_2 [2022-02-20 23:12:29,291 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~int~X~$Pointer$~TO~int [2022-02-20 23:12:29,291 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~int~X~$Pointer$~TO~int [2022-02-20 23:12:29,291 INFO L130 BoogieDeclarations]: Found specification of procedure ioread32_rep [2022-02-20 23:12:29,291 INFO L138 BoogieDeclarations]: Found implementation of procedure ioread32_rep [2022-02-20 23:12:29,291 INFO L130 BoogieDeclarations]: Found specification of procedure pci_enable_device [2022-02-20 23:12:29,291 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_enable_device [2022-02-20 23:12:29,291 INFO L130 BoogieDeclarations]: Found specification of procedure vortex_up [2022-02-20 23:12:29,291 INFO L138 BoogieDeclarations]: Found implementation of procedure vortex_up [2022-02-20 23:12:29,291 INFO L130 BoogieDeclarations]: Found specification of procedure window_read16 [2022-02-20 23:12:29,291 INFO L138 BoogieDeclarations]: Found implementation of procedure window_read16 [2022-02-20 23:12:29,292 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free [2022-02-20 23:12:29,292 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free [2022-02-20 23:12:29,292 INFO L130 BoogieDeclarations]: Found specification of procedure init_timer_key [2022-02-20 23:12:29,292 INFO L138 BoogieDeclarations]: Found implementation of procedure init_timer_key [2022-02-20 23:12:29,292 INFO L130 BoogieDeclarations]: Found specification of procedure pci_iounmap [2022-02-20 23:12:29,292 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_iounmap [2022-02-20 23:12:29,292 INFO L130 BoogieDeclarations]: Found specification of procedure pci_set_power_state [2022-02-20 23:12:29,292 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_set_power_state [2022-02-20 23:12:29,292 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_lock_of_vortex_private [2022-02-20 23:12:29,292 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_lock_of_vortex_private [2022-02-20 23:12:29,293 INFO L130 BoogieDeclarations]: Found specification of procedure spin_lock [2022-02-20 23:12:29,293 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_lock [2022-02-20 23:12:29,293 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_112 [2022-02-20 23:12:29,293 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_112 [2022-02-20 23:12:29,293 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_113 [2022-02-20 23:12:29,293 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_113 [2022-02-20 23:12:29,293 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 23:12:29,293 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2022-02-20 23:12:29,293 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2022-02-20 23:12:29,293 INFO L130 BoogieDeclarations]: Found specification of procedure unregister_netdev [2022-02-20 23:12:29,294 INFO L138 BoogieDeclarations]: Found implementation of procedure unregister_netdev [2022-02-20 23:12:29,998 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 23:12:30,000 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 23:12:31,418 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 23:12:35,837 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 23:12:35,858 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 23:12:35,858 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-02-20 23:12:35,861 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 11:12:35 BoogieIcfgContainer [2022-02-20 23:12:35,862 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 23:12:35,863 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 23:12:35,863 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 23:12:35,876 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 23:12:35,877 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 11:12:25" (1/3) ... [2022-02-20 23:12:35,877 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5fb9fb14 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 11:12:35, skipping insertion in model container [2022-02-20 23:12:35,877 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:12:28" (2/3) ... [2022-02-20 23:12:35,878 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5fb9fb14 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 11:12:35, skipping insertion in model container [2022-02-20 23:12:35,878 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 11:12:35" (3/3) ... [2022-02-20 23:12:35,879 INFO L111 eAbstractionObserver]: Analyzing ICFG linux-3.14_linux-alloc-spinlock_drivers-net-ethernet-3com-3c59x.cil.i [2022-02-20 23:12:35,882 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 23:12:35,882 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-02-20 23:12:35,917 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 23:12:35,921 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 23:12:35,922 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-02-20 23:12:35,985 INFO L276 IsEmpty]: Start isEmpty. Operand has 2965 states, 2050 states have (on average 1.3682926829268294) internal successors, (2805), 2136 states have internal predecessors, (2805), 760 states have call successors, (760), 154 states have call predecessors, (760), 153 states have return successors, (753), 735 states have call predecessors, (753), 753 states have call successors, (753) [2022-02-20 23:12:36,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2022-02-20 23:12:36,006 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 23:12:36,007 INFO L514 BasicCegarLoop]: trace histogram [8, 8, 8, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 23:12:36,007 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 23:12:36,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 23:12:36,011 INFO L85 PathProgramCache]: Analyzing trace with hash -60610364, now seen corresponding path program 1 times [2022-02-20 23:12:36,017 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 23:12:36,017 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239184062] [2022-02-20 23:12:36,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 23:12:36,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 23:12:36,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,654 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 23:12:36,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,743 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:36,743 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,744 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7987#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,744 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 10 [2022-02-20 23:12:36,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,758 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,758 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,759 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,759 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8049#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,761 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 27 [2022-02-20 23:12:36,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,775 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:12:36,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,785 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,786 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,786 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,787 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2968#true} {2968#true} #7811#return; {2968#true} is VALID [2022-02-20 23:12:36,787 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~val := #in~val; {2968#true} is VALID [2022-02-20 23:12:36,788 INFO L272 TraceCheckUtils]: 1: Hoare triple {2968#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:36,788 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,788 INFO L290 TraceCheckUtils]: 3: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,789 INFO L290 TraceCheckUtils]: 4: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,789 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {2968#true} {2968#true} #7811#return; {2968#true} is VALID [2022-02-20 23:12:36,792 INFO L290 TraceCheckUtils]: 6: Hoare triple {2968#true} #res := ~val; {2968#true} is VALID [2022-02-20 23:12:36,792 INFO L290 TraceCheckUtils]: 7: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,793 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8055#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,793 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 39 [2022-02-20 23:12:36,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,808 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:36,808 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,810 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8057#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,810 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 45 [2022-02-20 23:12:36,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,824 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,825 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,825 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,826 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8065#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,827 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 50 [2022-02-20 23:12:36,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,839 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:36,839 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,840 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8067#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,844 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 56 [2022-02-20 23:12:36,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,867 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:12:36,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,873 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,874 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,874 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,874 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2968#true} {2968#true} #7545#return; {2968#true} is VALID [2022-02-20 23:12:36,874 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 23:12:36,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,882 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {2968#true} is VALID [2022-02-20 23:12:36,883 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,883 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2968#true} {2968#true} #7547#return; {2968#true} is VALID [2022-02-20 23:12:36,883 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 23:12:36,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,892 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,892 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,893 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,893 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2968#true} {2968#true} #7549#return; {2968#true} is VALID [2022-02-20 23:12:36,893 INFO L290 TraceCheckUtils]: 0: Hoare triple {3057#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~127.base, ~tmp~127.offset;havoc ~tmp___0~64;call #t~malloc1675.base, #t~malloc1675.offset := #Ultimate.allocOnHeap(~size);~tmp~127.base, ~tmp~127.offset := #t~malloc1675.base, #t~malloc1675.offset;havoc #t~malloc1675.base, #t~malloc1675.offset;~res~3.base, ~res~3.offset := ~tmp~127.base, ~tmp~127.offset; {2968#true} is VALID [2022-02-20 23:12:36,893 INFO L272 TraceCheckUtils]: 1: Hoare triple {2968#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:36,893 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,894 INFO L290 TraceCheckUtils]: 3: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,894 INFO L290 TraceCheckUtils]: 4: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,894 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {2968#true} {2968#true} #7545#return; {2968#true} is VALID [2022-02-20 23:12:36,897 INFO L272 TraceCheckUtils]: 6: Hoare triple {2968#true} call #t~ret1676 := ldv_is_err(~res~3.base, ~res~3.offset); {2968#true} is VALID [2022-02-20 23:12:36,897 INFO L290 TraceCheckUtils]: 7: Hoare triple {2968#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {2968#true} is VALID [2022-02-20 23:12:36,897 INFO L290 TraceCheckUtils]: 8: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,897 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {2968#true} {2968#true} #7547#return; {2968#true} is VALID [2022-02-20 23:12:36,897 INFO L290 TraceCheckUtils]: 10: Hoare triple {2968#true} assume -9223372036854775808 <= #t~ret1676 && #t~ret1676 <= 9223372036854775807;~tmp___0~64 := #t~ret1676;havoc #t~ret1676; {2968#true} is VALID [2022-02-20 23:12:36,898 INFO L272 TraceCheckUtils]: 11: Hoare triple {2968#true} call ldv_assume((if 0 == ~tmp___0~64 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:36,898 INFO L290 TraceCheckUtils]: 12: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,898 INFO L290 TraceCheckUtils]: 13: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,911 INFO L290 TraceCheckUtils]: 14: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,911 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {2968#true} {2968#true} #7549#return; {2968#true} is VALID [2022-02-20 23:12:36,912 INFO L290 TraceCheckUtils]: 16: Hoare triple {2968#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {2968#true} is VALID [2022-02-20 23:12:36,912 INFO L290 TraceCheckUtils]: 17: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,913 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8069#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,913 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 77 [2022-02-20 23:12:36,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,923 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:36,923 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,924 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8071#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,924 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 83 [2022-02-20 23:12:36,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,939 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:12:36,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,947 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,947 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,947 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,948 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2968#true} {2968#true} #7545#return; {2968#true} is VALID [2022-02-20 23:12:36,948 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 23:12:36,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,955 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {2968#true} is VALID [2022-02-20 23:12:36,955 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,955 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2968#true} {2968#true} #7547#return; {2968#true} is VALID [2022-02-20 23:12:36,956 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 23:12:36,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,969 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,969 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,969 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,969 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2968#true} {2968#true} #7549#return; {2968#true} is VALID [2022-02-20 23:12:36,970 INFO L290 TraceCheckUtils]: 0: Hoare triple {3057#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~127.base, ~tmp~127.offset;havoc ~tmp___0~64;call #t~malloc1675.base, #t~malloc1675.offset := #Ultimate.allocOnHeap(~size);~tmp~127.base, ~tmp~127.offset := #t~malloc1675.base, #t~malloc1675.offset;havoc #t~malloc1675.base, #t~malloc1675.offset;~res~3.base, ~res~3.offset := ~tmp~127.base, ~tmp~127.offset; {2968#true} is VALID [2022-02-20 23:12:36,972 INFO L272 TraceCheckUtils]: 1: Hoare triple {2968#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:36,972 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,972 INFO L290 TraceCheckUtils]: 3: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,972 INFO L290 TraceCheckUtils]: 4: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,973 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {2968#true} {2968#true} #7545#return; {2968#true} is VALID [2022-02-20 23:12:36,973 INFO L272 TraceCheckUtils]: 6: Hoare triple {2968#true} call #t~ret1676 := ldv_is_err(~res~3.base, ~res~3.offset); {2968#true} is VALID [2022-02-20 23:12:36,973 INFO L290 TraceCheckUtils]: 7: Hoare triple {2968#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {2968#true} is VALID [2022-02-20 23:12:36,973 INFO L290 TraceCheckUtils]: 8: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,973 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {2968#true} {2968#true} #7547#return; {2968#true} is VALID [2022-02-20 23:12:36,974 INFO L290 TraceCheckUtils]: 10: Hoare triple {2968#true} assume -9223372036854775808 <= #t~ret1676 && #t~ret1676 <= 9223372036854775807;~tmp___0~64 := #t~ret1676;havoc #t~ret1676; {2968#true} is VALID [2022-02-20 23:12:36,974 INFO L272 TraceCheckUtils]: 11: Hoare triple {2968#true} call ldv_assume((if 0 == ~tmp___0~64 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:36,974 INFO L290 TraceCheckUtils]: 12: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:36,974 INFO L290 TraceCheckUtils]: 13: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:36,974 INFO L290 TraceCheckUtils]: 14: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,975 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {2968#true} {2968#true} #7549#return; {2968#true} is VALID [2022-02-20 23:12:36,975 INFO L290 TraceCheckUtils]: 16: Hoare triple {2968#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {2968#true} is VALID [2022-02-20 23:12:36,975 INFO L290 TraceCheckUtils]: 17: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,976 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8073#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,976 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 104 [2022-02-20 23:12:36,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,983 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,983 INFO L284 TraceCheckUtils]: 1: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8075#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,983 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 117 [2022-02-20 23:12:36,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:36,992 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {2968#true} is VALID [2022-02-20 23:12:36,992 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:36,993 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7851#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:36,994 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 126 [2022-02-20 23:12:36,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:37,007 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:37,007 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,008 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7853#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,009 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 132 [2022-02-20 23:12:37,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:37,030 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:37,030 INFO L290 TraceCheckUtils]: 1: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:37,030 INFO L290 TraceCheckUtils]: 2: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,031 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7875#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,031 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 149 [2022-02-20 23:12:37,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:12:37,044 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} assume 2 == ~ldv_spin__xmit_lock_of_netdev_queue~0;#res := 1; {3080#(<= 2 ~ldv_spin__xmit_lock_of_netdev_queue~0)} is VALID [2022-02-20 23:12:37,045 INFO L290 TraceCheckUtils]: 1: Hoare triple {3080#(<= 2 ~ldv_spin__xmit_lock_of_netdev_queue~0)} assume true; {3080#(<= 2 ~ldv_spin__xmit_lock_of_netdev_queue~0)} is VALID [2022-02-20 23:12:37,045 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3080#(<= 2 ~ldv_spin__xmit_lock_of_netdev_queue~0)} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7101#return; {2969#false} is VALID [2022-02-20 23:12:37,059 INFO L290 TraceCheckUtils]: 0: Hoare triple {2968#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(190, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(20, 4);call #Ultimate.allocInit(31, 5);call #Ultimate.allocInit(29, 6);call #Ultimate.allocInit(23, 7);call #Ultimate.allocInit(23, 8);call #Ultimate.allocInit(25, 9);call #Ultimate.allocInit(24, 10);call #Ultimate.allocInit(29, 11);call #Ultimate.allocInit(25, 12);call #Ultimate.allocInit(27, 13);call #Ultimate.allocInit(25, 14);call #Ultimate.allocInit(28, 15);call #Ultimate.allocInit(26, 16);call #Ultimate.allocInit(26, 17);call #Ultimate.allocInit(32, 18);call #Ultimate.allocInit(25, 19);call #Ultimate.allocInit(26, 20);call #Ultimate.allocInit(28, 21);call #Ultimate.allocInit(15, 22);call #Ultimate.allocInit(37, 23);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(16, 25);call #Ultimate.allocInit(23, 26);call #Ultimate.allocInit(23, 27);call #Ultimate.allocInit(21, 28);call #Ultimate.allocInit(24, 29);call #Ultimate.allocInit(38, 30);call #Ultimate.allocInit(24, 31);call #Ultimate.allocInit(27, 32);call #Ultimate.allocInit(27, 33);call #Ultimate.allocInit(25, 34);call #Ultimate.allocInit(36, 35);call #Ultimate.allocInit(36, 36);call #Ultimate.allocInit(22, 37);call #Ultimate.allocInit(14, 38);call #Ultimate.allocInit(24, 39);call #Ultimate.allocInit(24, 40);call #Ultimate.allocInit(10, 41);call #Ultimate.allocInit(23, 42);call #Ultimate.allocInit(8, 43);call #Ultimate.allocInit(10, 44);call #Ultimate.allocInit(10, 45);call #Ultimate.allocInit(8, 46);call #Ultimate.allocInit(10, 47);call #Ultimate.allocInit(10, 48);call #Ultimate.allocInit(4, 49);call write~init~int(77, 49, 0, 1);call write~init~int(73, 49, 1, 1);call write~init~int(73, 49, 2, 1);call write~init~int(0, 49, 3, 1);call #Ultimate.allocInit(10, 50);call #Ultimate.allocInit(14, 51);call #Ultimate.allocInit(13, 52);call #Ultimate.allocInit(8, 53);call #Ultimate.allocInit(6, 54);call write~init~int(51, 54, 0, 1);call write~init~int(99, 54, 1, 1);call write~init~int(53, 54, 2, 1);call write~init~int(57, 54, 3, 1);call write~init~int(120, 54, 4, 1);call write~init~int(0, 54, 5, 1);call #Ultimate.allocInit(6, 55);call write~init~int(51, 55, 0, 1);call write~init~int(99, 55, 1, 1);call write~init~int(53, 55, 2, 1);call write~init~int(57, 55, 3, 1);call write~init~int(120, 55, 4, 1);call write~init~int(0, 55, 5, 1);call #Ultimate.allocInit(4, 56);call write~init~int(14, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(0, 56, 3, 1);call #Ultimate.allocInit(42, 57);call #Ultimate.allocInit(24, 58);call #Ultimate.allocInit(4, 59);call write~init~int(80, 59, 0, 1);call write~init~int(67, 59, 1, 1);call write~init~int(73, 59, 2, 1);call write~init~int(0, 59, 3, 1);call #Ultimate.allocInit(5, 60);call write~init~int(69, 60, 0, 1);call write~init~int(73, 60, 1, 1);call write~init~int(83, 60, 2, 1);call write~init~int(65, 60, 3, 1);call write~init~int(0, 60, 4, 1);call #Ultimate.allocInit(74, 61);call #Ultimate.allocInit(20, 62);call #Ultimate.allocInit(24, 63);call #Ultimate.allocInit(27, 64);call #Ultimate.allocInit(31, 65);call #Ultimate.allocInit(5, 66);call write~init~int(32, 66, 0, 1);call write~init~int(37, 66, 1, 1);call write~init~int(112, 66, 2, 1);call write~init~int(77, 66, 3, 1);call write~init~int(0, 66, 4, 1);call #Ultimate.allocInit(37, 67);call #Ultimate.allocInit(10, 68);call #Ultimate.allocInit(48, 69);call #Ultimate.allocInit(58, 70);call #Ultimate.allocInit(45, 71);call #Ultimate.allocInit(22, 72);call #Ultimate.allocInit(4, 73);call write~init~int(53, 73, 0, 1);call write~init~int(58, 73, 1, 1);call write~init~int(51, 73, 2, 1);call write~init~int(0, 73, 3, 1);call #Ultimate.allocInit(4, 74);call write~init~int(51, 74, 0, 1);call write~init~int(58, 74, 1, 1);call write~init~int(49, 74, 2, 1);call write~init~int(0, 74, 3, 1);call #Ultimate.allocInit(4, 75);call write~init~int(49, 75, 0, 1);call write~init~int(58, 75, 1, 1);call write~init~int(49, 75, 2, 1);call write~init~int(0, 75, 3, 1);call #Ultimate.allocInit(4, 76);call write~init~int(51, 76, 0, 1);call write~init~int(58, 76, 1, 1);call write~init~int(53, 76, 2, 1);call write~init~int(0, 76, 3, 1);call #Ultimate.allocInit(6, 77);call write~init~int(51, 77, 0, 1);call write~init~int(99, 77, 1, 1);call write~init~int(53, 77, 2, 1);call write~init~int(57, 77, 3, 1);call write~init~int(120, 77, 4, 1);call write~init~int(0, 77, 5, 1);call #Ultimate.allocInit(14, 78);call #Ultimate.allocInit(34, 79);call #Ultimate.allocInit(56, 80);call #Ultimate.allocInit(56, 81);call #Ultimate.allocInit(52, 82);call #Ultimate.allocInit(5, 83);call write~init~int(119, 83, 0, 1);call write~init~int(111, 83, 1, 1);call write~init~int(114, 83, 2, 1);call write~init~int(100, 83, 3, 1);call write~init~int(0, 83, 4, 1);call #Ultimate.allocInit(5, 84);call write~init~int(98, 84, 0, 1);call write~init~int(121, 84, 1, 1);call write~init~int(116, 84, 2, 1);call write~init~int(101, 84, 3, 1);call write~init~int(0, 84, 4, 1);call #Ultimate.allocInit(12, 85);call #Ultimate.allocInit(1, 86);call write~init~int(0, 86, 0, 1);call #Ultimate.allocInit(22, 87);call #Ultimate.allocInit(51, 88);call #Ultimate.allocInit(53, 89);call #Ultimate.allocInit(45, 90);call #Ultimate.allocInit(51, 91);call #Ultimate.allocInit(6, 92);call write~init~int(101, 92, 0, 1);call write~init~int(97, 92, 1, 1);call write~init~int(114, 92, 2, 1);call write~init~int(108, 92, 3, 1);call write~init~int(121, 92, 4, 1);call write~init~int(0, 92, 5, 1);call #Ultimate.allocInit(12, 93);call #Ultimate.allocInit(52, 94);call #Ultimate.allocInit(3, 95);call write~init~int(101, 95, 0, 1);call write~init~int(110, 95, 1, 1);call write~init~int(0, 95, 2, 1);call #Ultimate.allocInit(4, 96);call write~init~int(100, 96, 0, 1);call write~init~int(105, 96, 1, 1);call write~init~int(115, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(3, 97);call write~init~int(101, 97, 0, 1);call write~init~int(110, 97, 1, 1);call write~init~int(0, 97, 2, 1);call #Ultimate.allocInit(4, 98);call write~init~int(100, 98, 0, 1);call write~init~int(105, 98, 1, 1);call write~init~int(115, 98, 2, 1);call write~init~int(0, 98, 3, 1);call #Ultimate.allocInit(41, 99);call #Ultimate.allocInit(35, 100);call #Ultimate.allocInit(51, 101);call #Ultimate.allocInit(26, 102);call #Ultimate.allocInit(5, 103);call write~init~int(102, 103, 0, 1);call write~init~int(117, 103, 1, 1);call write~init~int(108, 103, 2, 1);call write~init~int(108, 103, 3, 1);call write~init~int(0, 103, 4, 1);call #Ultimate.allocInit(5, 104);call write~init~int(104, 104, 0, 1);call write~init~int(97, 104, 1, 1);call write~init~int(108, 104, 2, 1);call write~init~int(102, 104, 3, 1);call write~init~int(0, 104, 4, 1);call #Ultimate.allocInit(30, 105);call #Ultimate.allocInit(45, 106);call #Ultimate.allocInit(38, 107);call #Ultimate.allocInit(37, 108);call #Ultimate.allocInit(29, 109);call #Ultimate.allocInit(13, 110);call #Ultimate.allocInit(20, 111);call #Ultimate.allocInit(6, 112);call write~init~int(51, 112, 0, 1);call write~init~int(99, 112, 1, 1);call write~init~int(53, 112, 2, 1);call write~init~int(57, 112, 3, 1);call write~init~int(120, 112, 4, 1);call write~init~int(0, 112, 5, 1);call #Ultimate.allocInit(10, 113);call #Ultimate.allocInit(34, 114);call #Ultimate.allocInit(28, 115);call #Ultimate.allocInit(28, 116);call #Ultimate.allocInit(6, 117);call write~init~int(51, 117, 0, 1);call write~init~int(99, 117, 1, 1);call write~init~int(53, 117, 2, 1);call write~init~int(57, 117, 3, 1);call write~init~int(120, 117, 4, 1);call write~init~int(0, 117, 5, 1);call #Ultimate.allocInit(10, 118);call #Ultimate.allocInit(34, 119);call #Ultimate.allocInit(45, 120);call #Ultimate.allocInit(45, 121);call #Ultimate.allocInit(6, 122);call write~init~int(51, 122, 0, 1);call write~init~int(99, 122, 1, 1);call write~init~int(53, 122, 2, 1);call write~init~int(57, 122, 3, 1);call write~init~int(120, 122, 4, 1);call write~init~int(0, 122, 5, 1);call #Ultimate.allocInit(10, 123);call #Ultimate.allocInit(34, 124);call #Ultimate.allocInit(44, 125);call #Ultimate.allocInit(44, 126);call #Ultimate.allocInit(31, 127);call #Ultimate.allocInit(6, 128);call write~init~int(51, 128, 0, 1);call write~init~int(99, 128, 1, 1);call write~init~int(53, 128, 2, 1);call write~init~int(57, 128, 3, 1);call write~init~int(120, 128, 4, 1);call write~init~int(0, 128, 5, 1);call #Ultimate.allocInit(12, 129);call #Ultimate.allocInit(34, 130);call #Ultimate.allocInit(30, 131);call #Ultimate.allocInit(30, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(40, 134);call #Ultimate.allocInit(6, 135);call write~init~int(51, 135, 0, 1);call write~init~int(99, 135, 1, 1);call write~init~int(53, 135, 2, 1);call write~init~int(57, 135, 3, 1);call write~init~int(120, 135, 4, 1);call write~init~int(0, 135, 5, 1);call #Ultimate.allocInit(13, 136);call #Ultimate.allocInit(34, 137);call #Ultimate.allocInit(46, 138);call #Ultimate.allocInit(46, 139);call #Ultimate.allocInit(6, 140);call write~init~int(51, 140, 0, 1);call write~init~int(99, 140, 1, 1);call write~init~int(53, 140, 2, 1);call write~init~int(57, 140, 3, 1);call write~init~int(120, 140, 4, 1);call write~init~int(0, 140, 5, 1);call #Ultimate.allocInit(13, 141);call #Ultimate.allocInit(34, 142);call #Ultimate.allocInit(24, 143);call #Ultimate.allocInit(24, 144);call #Ultimate.allocInit(6, 145);call write~init~int(51, 145, 0, 1);call write~init~int(99, 145, 1, 1);call write~init~int(53, 145, 2, 1);call write~init~int(57, 145, 3, 1);call write~init~int(120, 145, 4, 1);call write~init~int(0, 145, 5, 1);call #Ultimate.allocInit(13, 146);call #Ultimate.allocInit(34, 147);call #Ultimate.allocInit(33, 148);call #Ultimate.allocInit(33, 149);call #Ultimate.allocInit(6, 150);call write~init~int(51, 150, 0, 1);call write~init~int(99, 150, 1, 1);call write~init~int(53, 150, 2, 1);call write~init~int(57, 150, 3, 1);call write~init~int(120, 150, 4, 1);call write~init~int(0, 150, 5, 1);call #Ultimate.allocInit(13, 151);call #Ultimate.allocInit(34, 152);call #Ultimate.allocInit(36, 153);call #Ultimate.allocInit(36, 154);call #Ultimate.allocInit(6, 155);call write~init~int(51, 155, 0, 1);call write~init~int(99, 155, 1, 1);call write~init~int(53, 155, 2, 1);call write~init~int(57, 155, 3, 1);call write~init~int(120, 155, 4, 1);call write~init~int(0, 155, 5, 1);call #Ultimate.allocInit(13, 156);call #Ultimate.allocInit(34, 157);call #Ultimate.allocInit(37, 158);call #Ultimate.allocInit(37, 159);call #Ultimate.allocInit(6, 160);call write~init~int(51, 160, 0, 1);call write~init~int(99, 160, 1, 1);call write~init~int(53, 160, 2, 1);call write~init~int(57, 160, 3, 1);call write~init~int(120, 160, 4, 1);call write~init~int(0, 160, 5, 1);call #Ultimate.allocInit(13, 161);call #Ultimate.allocInit(34, 162);call #Ultimate.allocInit(53, 163);call #Ultimate.allocInit(53, 164);call #Ultimate.allocInit(6, 165);call write~init~int(51, 165, 0, 1);call write~init~int(99, 165, 1, 1);call write~init~int(53, 165, 2, 1);call write~init~int(57, 165, 3, 1);call write~init~int(120, 165, 4, 1);call write~init~int(0, 165, 5, 1);call #Ultimate.allocInit(13, 166);call #Ultimate.allocInit(34, 167);call #Ultimate.allocInit(49, 168);call #Ultimate.allocInit(49, 169);call #Ultimate.allocInit(6, 170);call write~init~int(51, 170, 0, 1);call write~init~int(99, 170, 1, 1);call write~init~int(53, 170, 2, 1);call write~init~int(57, 170, 3, 1);call write~init~int(120, 170, 4, 1);call write~init~int(0, 170, 5, 1);call #Ultimate.allocInit(13, 171);call #Ultimate.allocInit(34, 172);call #Ultimate.allocInit(28, 173);call #Ultimate.allocInit(28, 174);call #Ultimate.allocInit(6, 175);call write~init~int(51, 175, 0, 1);call write~init~int(99, 175, 1, 1);call write~init~int(53, 175, 2, 1);call write~init~int(57, 175, 3, 1);call write~init~int(120, 175, 4, 1);call write~init~int(0, 175, 5, 1);call #Ultimate.allocInit(13, 176);call #Ultimate.allocInit(34, 177);call #Ultimate.allocInit(41, 178);call #Ultimate.allocInit(41, 179);call #Ultimate.allocInit(56, 180);call #Ultimate.allocInit(56, 181);call #Ultimate.allocInit(70, 182);call #Ultimate.allocInit(75, 183);call #Ultimate.allocInit(6, 184);call write~init~int(51, 184, 0, 1);call write~init~int(99, 184, 1, 1);call write~init~int(53, 184, 2, 1);call write~init~int(57, 184, 3, 1);call write~init~int(120, 184, 4, 1);call write~init~int(0, 184, 5, 1);call #Ultimate.allocInit(18, 185);call #Ultimate.allocInit(34, 186);call #Ultimate.allocInit(36, 187);call #Ultimate.allocInit(36, 188);call #Ultimate.allocInit(34, 189);call #Ultimate.allocInit(48, 190);call #Ultimate.allocInit(71, 191);call #Ultimate.allocInit(6, 192);call write~init~int(51, 192, 0, 1);call write~init~int(99, 192, 1, 1);call write~init~int(53, 192, 2, 1);call write~init~int(57, 192, 3, 1);call write~init~int(120, 192, 4, 1);call write~init~int(0, 192, 5, 1);call #Ultimate.allocInit(13, 193);call #Ultimate.allocInit(34, 194);call #Ultimate.allocInit(21, 195);call #Ultimate.allocInit(21, 196);call #Ultimate.allocInit(74, 197);call #Ultimate.allocInit(50, 198);call #Ultimate.allocInit(38, 199);call #Ultimate.allocInit(6, 200);call write~init~int(51, 200, 0, 1);call write~init~int(99, 200, 1, 1);call write~init~int(53, 200, 2, 1);call write~init~int(57, 200, 3, 1);call write~init~int(120, 200, 4, 1);call write~init~int(0, 200, 5, 1);call #Ultimate.allocInit(18, 201);call #Ultimate.allocInit(34, 202);call #Ultimate.allocInit(29, 203);call #Ultimate.allocInit(29, 204);call #Ultimate.allocInit(6, 205);call write~init~int(51, 205, 0, 1);call write~init~int(99, 205, 1, 1);call write~init~int(53, 205, 2, 1);call write~init~int(57, 205, 3, 1);call write~init~int(120, 205, 4, 1);call write~init~int(0, 205, 5, 1);call #Ultimate.allocInit(21, 206);call #Ultimate.allocInit(34, 207);call #Ultimate.allocInit(24, 208);call #Ultimate.allocInit(24, 209);call #Ultimate.allocInit(6, 210);call write~init~int(51, 210, 0, 1);call write~init~int(99, 210, 1, 1);call write~init~int(53, 210, 2, 1);call write~init~int(57, 210, 3, 1);call write~init~int(120, 210, 4, 1);call write~init~int(0, 210, 5, 1);call #Ultimate.allocInit(21, 211);call #Ultimate.allocInit(34, 212);call #Ultimate.allocInit(43, 213);call #Ultimate.allocInit(43, 214);call #Ultimate.allocInit(50, 215);call #Ultimate.allocInit(6, 216);call write~init~int(51, 216, 0, 1);call write~init~int(99, 216, 1, 1);call write~init~int(53, 216, 2, 1);call write~init~int(57, 216, 3, 1);call write~init~int(120, 216, 4, 1);call write~init~int(0, 216, 5, 1);call #Ultimate.allocInit(17, 217);call #Ultimate.allocInit(34, 218);call #Ultimate.allocInit(34, 219);call #Ultimate.allocInit(34, 220);call #Ultimate.allocInit(6, 221);call write~init~int(51, 221, 0, 1);call write~init~int(99, 221, 1, 1);call write~init~int(53, 221, 2, 1);call write~init~int(57, 221, 3, 1);call write~init~int(120, 221, 4, 1);call write~init~int(0, 221, 5, 1);call #Ultimate.allocInit(17, 222);call #Ultimate.allocInit(34, 223);call #Ultimate.allocInit(48, 224);call #Ultimate.allocInit(48, 225);call #Ultimate.allocInit(6, 226);call write~init~int(51, 226, 0, 1);call write~init~int(99, 226, 1, 1);call write~init~int(53, 226, 2, 1);call write~init~int(57, 226, 3, 1);call write~init~int(120, 226, 4, 1);call write~init~int(0, 226, 5, 1);call #Ultimate.allocInit(17, 227);call #Ultimate.allocInit(34, 228);call #Ultimate.allocInit(38, 229);call #Ultimate.allocInit(38, 230);call #Ultimate.allocInit(6, 231);call write~init~int(51, 231, 0, 1);call write~init~int(99, 231, 1, 1);call write~init~int(53, 231, 2, 1);call write~init~int(57, 231, 3, 1);call write~init~int(120, 231, 4, 1);call write~init~int(0, 231, 5, 1);call #Ultimate.allocInit(17, 232);call #Ultimate.allocInit(34, 233);call #Ultimate.allocInit(27, 234);call #Ultimate.allocInit(27, 235);call #Ultimate.allocInit(48, 236);call #Ultimate.allocInit(6, 237);call write~init~int(51, 237, 0, 1);call write~init~int(99, 237, 1, 1);call write~init~int(53, 237, 2, 1);call write~init~int(57, 237, 3, 1);call write~init~int(120, 237, 4, 1);call write~init~int(0, 237, 5, 1);call #Ultimate.allocInit(17, 238);call #Ultimate.allocInit(34, 239);call #Ultimate.allocInit(38, 240);call #Ultimate.allocInit(38, 241);call #Ultimate.allocInit(6, 242);call write~init~int(51, 242, 0, 1);call write~init~int(99, 242, 1, 1);call write~init~int(53, 242, 2, 1);call write~init~int(57, 242, 3, 1);call write~init~int(120, 242, 4, 1);call write~init~int(0, 242, 5, 1);call #Ultimate.allocInit(20, 243);call #Ultimate.allocInit(34, 244);call #Ultimate.allocInit(35, 245);call #Ultimate.allocInit(35, 246);call #Ultimate.allocInit(6, 247);call write~init~int(51, 247, 0, 1);call write~init~int(99, 247, 1, 1);call write~init~int(53, 247, 2, 1);call write~init~int(57, 247, 3, 1);call write~init~int(120, 247, 4, 1);call write~init~int(0, 247, 5, 1);call #Ultimate.allocInit(20, 248);call #Ultimate.allocInit(34, 249);call #Ultimate.allocInit(41, 250);call #Ultimate.allocInit(41, 251);call #Ultimate.allocInit(6, 252);call write~init~int(51, 252, 0, 1);call write~init~int(99, 252, 1, 1);call write~init~int(53, 252, 2, 1);call write~init~int(57, 252, 3, 1);call write~init~int(120, 252, 4, 1);call write~init~int(0, 252, 5, 1);call #Ultimate.allocInit(20, 253);call #Ultimate.allocInit(34, 254);call #Ultimate.allocInit(48, 255);call #Ultimate.allocInit(48, 256);call #Ultimate.allocInit(6, 257);call write~init~int(51, 257, 0, 1);call write~init~int(99, 257, 1, 1);call write~init~int(53, 257, 2, 1);call write~init~int(57, 257, 3, 1);call write~init~int(120, 257, 4, 1);call write~init~int(0, 257, 5, 1);call #Ultimate.allocInit(20, 258);call #Ultimate.allocInit(34, 259);call #Ultimate.allocInit(38, 260);call #Ultimate.allocInit(38, 261);call #Ultimate.allocInit(6, 262);call write~init~int(51, 262, 0, 1);call write~init~int(99, 262, 1, 1);call write~init~int(53, 262, 2, 1);call write~init~int(57, 262, 3, 1);call write~init~int(120, 262, 4, 1);call write~init~int(0, 262, 5, 1);call #Ultimate.allocInit(20, 263);call #Ultimate.allocInit(34, 264);call #Ultimate.allocInit(35, 265);call #Ultimate.allocInit(35, 266);call #Ultimate.allocInit(6, 267);call write~init~int(51, 267, 0, 1);call write~init~int(99, 267, 1, 1);call write~init~int(53, 267, 2, 1);call write~init~int(57, 267, 3, 1);call write~init~int(120, 267, 4, 1);call write~init~int(0, 267, 5, 1);call #Ultimate.allocInit(20, 268);call #Ultimate.allocInit(34, 269);call #Ultimate.allocInit(30, 270);call #Ultimate.allocInit(30, 271);call #Ultimate.allocInit(6, 272);call write~init~int(51, 272, 0, 1);call write~init~int(99, 272, 1, 1);call write~init~int(53, 272, 2, 1);call write~init~int(57, 272, 3, 1);call write~init~int(120, 272, 4, 1);call write~init~int(0, 272, 5, 1);call #Ultimate.allocInit(20, 273);call #Ultimate.allocInit(34, 274);call #Ultimate.allocInit(33, 275);call #Ultimate.allocInit(33, 276);call #Ultimate.allocInit(48, 277);call #Ultimate.allocInit(6, 278);call write~init~int(51, 278, 0, 1);call write~init~int(99, 278, 1, 1);call write~init~int(53, 278, 2, 1);call write~init~int(57, 278, 3, 1);call write~init~int(120, 278, 4, 1);call write~init~int(0, 278, 5, 1);call #Ultimate.allocInit(20, 279);call #Ultimate.allocInit(34, 280);call #Ultimate.allocInit(38, 281);call #Ultimate.allocInit(38, 282);call #Ultimate.allocInit(6, 283);call write~init~int(51, 283, 0, 1);call write~init~int(99, 283, 1, 1);call write~init~int(53, 283, 2, 1);call write~init~int(57, 283, 3, 1);call write~init~int(120, 283, 4, 1);call write~init~int(0, 283, 5, 1);call #Ultimate.allocInit(10, 284);call #Ultimate.allocInit(34, 285);call #Ultimate.allocInit(45, 286);call #Ultimate.allocInit(45, 287);call #Ultimate.allocInit(6, 288);call write~init~int(51, 288, 0, 1);call write~init~int(99, 288, 1, 1);call write~init~int(53, 288, 2, 1);call write~init~int(57, 288, 3, 1);call write~init~int(120, 288, 4, 1);call write~init~int(0, 288, 5, 1);call #Ultimate.allocInit(10, 289);call #Ultimate.allocInit(34, 290);call #Ultimate.allocInit(26, 291);call #Ultimate.allocInit(26, 292);call #Ultimate.allocInit(6, 293);call write~init~int(51, 293, 0, 1);call write~init~int(99, 293, 1, 1);call write~init~int(53, 293, 2, 1);call write~init~int(57, 293, 3, 1);call write~init~int(120, 293, 4, 1);call write~init~int(0, 293, 5, 1);call #Ultimate.allocInit(10, 294);call #Ultimate.allocInit(34, 295);call #Ultimate.allocInit(40, 296);call #Ultimate.allocInit(40, 297);call #Ultimate.allocInit(50, 298);call #Ultimate.allocInit(6, 299);call write~init~int(51, 299, 0, 1);call write~init~int(99, 299, 1, 1);call write~init~int(53, 299, 2, 1);call write~init~int(57, 299, 3, 1);call write~init~int(120, 299, 4, 1);call write~init~int(0, 299, 5, 1);call #Ultimate.allocInit(13, 300);call #Ultimate.allocInit(34, 301);call #Ultimate.allocInit(30, 302);call #Ultimate.allocInit(30, 303);call #Ultimate.allocInit(6, 304);call write~init~int(51, 304, 0, 1);call write~init~int(99, 304, 1, 1);call write~init~int(53, 304, 2, 1);call write~init~int(57, 304, 3, 1);call write~init~int(120, 304, 4, 1);call write~init~int(0, 304, 5, 1);call #Ultimate.allocInit(13, 305);call #Ultimate.allocInit(34, 306);call #Ultimate.allocInit(26, 307);call #Ultimate.allocInit(26, 308);call #Ultimate.allocInit(6, 309);call write~init~int(51, 309, 0, 1);call write~init~int(99, 309, 1, 1);call write~init~int(53, 309, 2, 1);call write~init~int(57, 309, 3, 1);call write~init~int(120, 309, 4, 1);call write~init~int(0, 309, 5, 1);call #Ultimate.allocInit(13, 310);call #Ultimate.allocInit(34, 311);call #Ultimate.allocInit(40, 312);call #Ultimate.allocInit(40, 313);call #Ultimate.allocInit(22, 314);call #Ultimate.allocInit(6, 315);call write~init~int(51, 315, 0, 1);call write~init~int(99, 315, 1, 1);call write~init~int(53, 315, 2, 1);call write~init~int(57, 315, 3, 1);call write~init~int(120, 315, 4, 1);call write~init~int(0, 315, 5, 1);call #Ultimate.allocInit(13, 316);call #Ultimate.allocInit(34, 317);call #Ultimate.allocInit(21, 318);call #Ultimate.allocInit(21, 319);call #Ultimate.allocInit(10, 320);call #Ultimate.allocInit(9, 321);call #Ultimate.allocInit(6, 322);call write~init~int(51, 322, 0, 1);call write~init~int(99, 322, 1, 1);call write~init~int(53, 322, 2, 1);call write~init~int(57, 322, 3, 1);call write~init~int(120, 322, 4, 1);call write~init~int(0, 322, 5, 1);call #Ultimate.allocInit(13, 323);call #Ultimate.allocInit(34, 324);call #Ultimate.allocInit(51, 325);call #Ultimate.allocInit(51, 326);call #Ultimate.allocInit(6, 327);call write~init~int(51, 327, 0, 1);call write~init~int(99, 327, 1, 1);call write~init~int(53, 327, 2, 1);call write~init~int(57, 327, 3, 1);call write~init~int(120, 327, 4, 1);call write~init~int(0, 327, 5, 1);call #Ultimate.allocInit(13, 328);call #Ultimate.allocInit(34, 329);call #Ultimate.allocInit(85, 330);call #Ultimate.allocInit(85, 331);call #Ultimate.allocInit(60, 332);call #Ultimate.allocInit(54, 333);call #Ultimate.allocInit(32, 334);call #Ultimate.allocInit(39, 335);call #Ultimate.allocInit(34, 336);call #Ultimate.allocInit(6, 337);call write~init~int(51, 337, 0, 1);call write~init~int(99, 337, 1, 1);call write~init~int(53, 337, 2, 1);call write~init~int(57, 337, 3, 1);call write~init~int(120, 337, 4, 1);call write~init~int(0, 337, 5, 1);call #Ultimate.allocInit(14, 338);call #Ultimate.allocInit(14, 339);call #Ultimate.allocInit(14, 340);call #Ultimate.allocInit(32, 341);call #Ultimate.allocInit(25, 342);call #Ultimate.allocInit(46, 343);call #Ultimate.allocInit(6, 344);call write~init~int(51, 344, 0, 1);call write~init~int(99, 344, 1, 1);call write~init~int(53, 344, 2, 1);call write~init~int(57, 344, 3, 1);call write~init~int(120, 344, 4, 1);call write~init~int(0, 344, 5, 1);call #Ultimate.allocInit(6, 345);call write~init~int(51, 345, 0, 1);call write~init~int(99, 345, 1, 1);call write~init~int(53, 345, 2, 1);call write~init~int(57, 345, 3, 1);call write~init~int(120, 345, 4, 1);call write~init~int(0, 345, 5, 1);call #Ultimate.allocInit(1, 346);call write~init~int(0, 346, 0, 1);call #Ultimate.allocInit(54, 347);call #Ultimate.allocInit(56, 348);call #Ultimate.allocInit(58, 349);call #Ultimate.allocInit(58, 350);call #Ultimate.allocInit(58, 351);call #Ultimate.allocInit(54, 352);call #Ultimate.allocInit(56, 353);call #Ultimate.allocInit(58, 354);call #Ultimate.allocInit(58, 355);call #Ultimate.allocInit(58, 356);call #Ultimate.allocInit(54, 357);call #Ultimate.allocInit(56, 358);call #Ultimate.allocInit(58, 359);call #Ultimate.allocInit(58, 360);call #Ultimate.allocInit(58, 361);call #Ultimate.allocInit(54, 362);call #Ultimate.allocInit(56, 363);call #Ultimate.allocInit(58, 364);call #Ultimate.allocInit(58, 365);call #Ultimate.allocInit(58, 366);call #Ultimate.allocInit(54, 367);call #Ultimate.allocInit(56, 368);call #Ultimate.allocInit(58, 369);call #Ultimate.allocInit(58, 370);call #Ultimate.allocInit(58, 371);call #Ultimate.allocInit(54, 372);call #Ultimate.allocInit(56, 373);call #Ultimate.allocInit(58, 374);call #Ultimate.allocInit(58, 375);call #Ultimate.allocInit(58, 376);call #Ultimate.allocInit(54, 377);call #Ultimate.allocInit(56, 378);call #Ultimate.allocInit(58, 379);call #Ultimate.allocInit(58, 380);call #Ultimate.allocInit(58, 381);call #Ultimate.allocInit(54, 382);call #Ultimate.allocInit(56, 383);call #Ultimate.allocInit(58, 384);call #Ultimate.allocInit(58, 385);call #Ultimate.allocInit(58, 386);call #Ultimate.allocInit(54, 387);call #Ultimate.allocInit(56, 388);call #Ultimate.allocInit(58, 389);call #Ultimate.allocInit(58, 390);call #Ultimate.allocInit(58, 391);call #Ultimate.allocInit(54, 392);call #Ultimate.allocInit(56, 393);call #Ultimate.allocInit(58, 394);call #Ultimate.allocInit(58, 395);call #Ultimate.allocInit(58, 396);call #Ultimate.allocInit(54, 397);call #Ultimate.allocInit(56, 398);call #Ultimate.allocInit(58, 399);call #Ultimate.allocInit(58, 400);call #Ultimate.allocInit(58, 401);call #Ultimate.allocInit(54, 402);call #Ultimate.allocInit(56, 403);call #Ultimate.allocInit(58, 404);call #Ultimate.allocInit(58, 405);call #Ultimate.allocInit(58, 406);call #Ultimate.allocInit(54, 407);call #Ultimate.allocInit(56, 408);call #Ultimate.allocInit(58, 409);call #Ultimate.allocInit(58, 410);call #Ultimate.allocInit(58, 411);call #Ultimate.allocInit(54, 412);call #Ultimate.allocInit(56, 413);call #Ultimate.allocInit(58, 414);call #Ultimate.allocInit(58, 415);call #Ultimate.allocInit(58, 416);call #Ultimate.allocInit(57, 417);call #Ultimate.allocInit(57, 418);call #Ultimate.allocInit(57, 419);call #Ultimate.allocInit(57, 420);call #Ultimate.allocInit(57, 421);call #Ultimate.allocInit(57, 422);call #Ultimate.allocInit(57, 423);call #Ultimate.allocInit(57, 424);call #Ultimate.allocInit(57, 425);call #Ultimate.allocInit(57, 426);call #Ultimate.allocInit(57, 427);call #Ultimate.allocInit(57, 428);call #Ultimate.allocInit(57, 429);call #Ultimate.allocInit(57, 430);call #Ultimate.allocInit(2, 431);call write~init~int(48, 431, 0, 1);call write~init~int(0, 431, 1, 1);call #Ultimate.allocInit(70, 432);~rx_copybreak~0 := 200;~mtu~0 := 1500;~max_interrupt_work~0 := 32;~watchdog~0 := 5000;~debug~0 := 1;~#version~0.base, ~#version~0.offset := 433, 0;call #Ultimate.allocInit(34, 433);call write~init~int(51, ~#version~0.base, ~#version~0.offset, 1);call write~init~int(99, ~#version~0.base, 1 + ~#version~0.offset, 1);call write~init~int(53, ~#version~0.base, 2 + ~#version~0.offset, 1);call write~init~int(57, ~#version~0.base, 3 + ~#version~0.offset, 1);call write~init~int(120, ~#version~0.base, 4 + ~#version~0.offset, 1);call write~init~int(58, ~#version~0.base, 5 + ~#version~0.offset, 1);call write~init~int(32, ~#version~0.base, 6 + ~#version~0.offset, 1);call write~init~int(68, ~#version~0.base, 7 + ~#version~0.offset, 1);call write~init~int(111, ~#version~0.base, 8 + ~#version~0.offset, 1);call write~init~int(110, ~#version~0.base, 9 + ~#version~0.offset, 1);call write~init~int(97, ~#version~0.base, 10 + ~#version~0.offset, 1);call write~init~int(108, ~#version~0.base, 11 + ~#version~0.offset, 1);call write~init~int(100, ~#version~0.base, 12 + ~#version~0.offset, 1);call write~init~int(32, ~#version~0.base, 13 + ~#version~0.offset, 1);call write~init~int(66, ~#version~0.base, 14 + ~#version~0.offset, 1);call write~init~int(101, ~#version~0.base, 15 + ~#version~0.offset, 1);call write~init~int(99, ~#version~0.base, 16 + ~#version~0.offset, 1);call write~init~int(107, ~#version~0.base, 17 + ~#version~0.offset, 1);call write~init~int(101, ~#version~0.base, 18 + ~#version~0.offset, 1);call write~init~int(114, ~#version~0.base, 19 + ~#version~0.offset, 1);call write~init~int(32, ~#version~0.base, 20 + ~#version~0.offset, 1);call write~init~int(97, ~#version~0.base, 21 + ~#version~0.offset, 1);call write~init~int(110, ~#version~0.base, 22 + ~#version~0.offset, 1);call write~init~int(100, ~#version~0.base, 23 + ~#version~0.offset, 1);call write~init~int(32, ~#version~0.base, 24 + ~#version~0.offset, 1);call write~init~int(111, ~#version~0.base, 25 + ~#version~0.offset, 1);call write~init~int(116, ~#version~0.base, 26 + ~#version~0.offset, 1);call write~init~int(104, ~#version~0.base, 27 + ~#version~0.offset, 1);call write~init~int(101, ~#version~0.base, 28 + ~#version~0.offset, 1);call write~init~int(114, ~#version~0.base, 29 + ~#version~0.offset, 1);call write~init~int(115, ~#version~0.base, 30 + ~#version~0.offset, 1);call write~init~int(46, ~#version~0.base, 31 + ~#version~0.offset, 1);call write~init~int(10, ~#version~0.base, 32 + ~#version~0.offset, 1);call write~init~int(0, ~#version~0.base, 33 + ~#version~0.offset, 1);~mii_preamble_required~0 := 0;~#vortex_info_tbl~0.base, ~#vortex_info_tbl~0.offset := 434, 0;call #Ultimate.allocInit(800, 434);call write~init~$Pointer$(4, 0, ~#vortex_info_tbl~0.base, ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 8 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 12 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 16 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(5, 0, ~#vortex_info_tbl~0.base, 20 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 28 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 32 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 36 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(6, 0, ~#vortex_info_tbl~0.base, 40 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 48 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 52 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 56 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(7, 0, ~#vortex_info_tbl~0.base, 60 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 68 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 72 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 76 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(8, 0, ~#vortex_info_tbl~0.base, 80 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 88 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 92 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 96 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(9, 0, ~#vortex_info_tbl~0.base, 100 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 108 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 112 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 116 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(10, 0, ~#vortex_info_tbl~0.base, 120 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 128 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(65538, ~#vortex_info_tbl~0.base, 132 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(64, ~#vortex_info_tbl~0.base, 136 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(11, 0, ~#vortex_info_tbl~0.base, 140 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 148 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(65538, ~#vortex_info_tbl~0.base, 152 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(64, ~#vortex_info_tbl~0.base, 156 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(12, 0, ~#vortex_info_tbl~0.base, 160 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 168 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 172 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 176 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(13, 0, ~#vortex_info_tbl~0.base, 180 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 188 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 192 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 196 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(14, 0, ~#vortex_info_tbl~0.base, 200 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 208 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 212 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 216 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(15, 0, ~#vortex_info_tbl~0.base, 220 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 228 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 232 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 236 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(16, 0, ~#vortex_info_tbl~0.base, 240 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 248 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(65602, ~#vortex_info_tbl~0.base, 252 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(64, ~#vortex_info_tbl~0.base, 256 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(17, 0, ~#vortex_info_tbl~0.base, 260 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 268 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(65602, ~#vortex_info_tbl~0.base, 272 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(64, ~#vortex_info_tbl~0.base, 276 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(18, 0, ~#vortex_info_tbl~0.base, 280 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 288 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41092, ~#vortex_info_tbl~0.base, 292 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 296 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(19, 0, ~#vortex_info_tbl~0.base, 300 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 308 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41092, ~#vortex_info_tbl~0.base, 312 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 316 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(20, 0, ~#vortex_info_tbl~0.base, 320 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 328 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8324, ~#vortex_info_tbl~0.base, 332 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 336 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(21, 0, ~#vortex_info_tbl~0.base, 340 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 348 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 352 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 356 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(22, 0, ~#vortex_info_tbl~0.base, 360 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 368 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41096, ~#vortex_info_tbl~0.base, 372 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 376 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(23, 0, ~#vortex_info_tbl~0.base, 380 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 388 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8264, ~#vortex_info_tbl~0.base, 392 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 396 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(24, 0, ~#vortex_info_tbl~0.base, 400 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 408 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(40964, ~#vortex_info_tbl~0.base, 412 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 416 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(25, 0, ~#vortex_info_tbl~0.base, 420 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 428 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8324, ~#vortex_info_tbl~0.base, 432 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 436 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(26, 0, ~#vortex_info_tbl~0.base, 440 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 448 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41092, ~#vortex_info_tbl~0.base, 452 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 456 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(27, 0, ~#vortex_info_tbl~0.base, 460 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 468 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8212, ~#vortex_info_tbl~0.base, 472 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 476 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(28, 0, ~#vortex_info_tbl~0.base, 480 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 488 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(9112, ~#vortex_info_tbl~0.base, 492 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 496 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(29, 0, ~#vortex_info_tbl~0.base, 500 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 508 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(29576, ~#vortex_info_tbl~0.base, 512 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 516 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(30, 0, ~#vortex_info_tbl~0.base, 520 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 528 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(82, ~#vortex_info_tbl~0.base, 532 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 536 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(31, 0, ~#vortex_info_tbl~0.base, 540 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 548 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(82, ~#vortex_info_tbl~0.base, 552 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 556 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(32, 0, ~#vortex_info_tbl~0.base, 560 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 568 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(9620, ~#vortex_info_tbl~0.base, 572 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 576 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(33, 0, ~#vortex_info_tbl~0.base, 580 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 588 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(11160, ~#vortex_info_tbl~0.base, 592 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 596 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(34, 0, ~#vortex_info_tbl~0.base, 600 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 608 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(10132, ~#vortex_info_tbl~0.base, 612 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 616 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(35, 0, ~#vortex_info_tbl~0.base, 620 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 628 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(10132, ~#vortex_info_tbl~0.base, 632 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 636 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(36, 0, ~#vortex_info_tbl~0.base, 640 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 648 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(11160, ~#vortex_info_tbl~0.base, 652 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 656 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(37, 0, ~#vortex_info_tbl~0.base, 660 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 668 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 672 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 676 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(38, 0, ~#vortex_info_tbl~0.base, 680 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 688 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 692 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 696 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(39, 0, ~#vortex_info_tbl~0.base, 700 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 708 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 712 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 716 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(40, 0, ~#vortex_info_tbl~0.base, 720 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 728 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 732 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 736 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(41, 0, ~#vortex_info_tbl~0.base, 740 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 748 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41092, ~#vortex_info_tbl~0.base, 752 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 756 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(42, 0, ~#vortex_info_tbl~0.base, 760 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 768 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 772 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 776 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(0, 0, ~#vortex_info_tbl~0.base, 780 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(0, ~#vortex_info_tbl~0.base, 788 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(0, ~#vortex_info_tbl~0.base, 792 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(0, ~#vortex_info_tbl~0.base, 796 + ~#vortex_info_tbl~0.offset, 4);~#vortex_pci_tbl~0.base, ~#vortex_pci_tbl~0.offset := 435, 0;call #Ultimate.allocInit(1280, 435);call write~init~int(4279, ~#vortex_pci_tbl~0.base, ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22784, ~#vortex_pci_tbl~0.base, 4 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 8 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 12 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 16 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 20 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 24 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 32 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22816, ~#vortex_pci_tbl~0.base, 36 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 40 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 44 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 48 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 52 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(1, ~#vortex_pci_tbl~0.base, 56 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 64 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22896, ~#vortex_pci_tbl~0.base, 68 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 72 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 76 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 80 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 84 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(2, ~#vortex_pci_tbl~0.base, 88 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 96 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22864, ~#vortex_pci_tbl~0.base, 100 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 104 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 108 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 112 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 116 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(3, ~#vortex_pci_tbl~0.base, 120 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 128 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22865, ~#vortex_pci_tbl~0.base, 132 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 136 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 140 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 144 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 148 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4, ~#vortex_pci_tbl~0.base, 152 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 160 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22866, ~#vortex_pci_tbl~0.base, 164 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 168 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 172 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 176 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 180 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(5, ~#vortex_pci_tbl~0.base, 184 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 192 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36864, ~#vortex_pci_tbl~0.base, 196 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 200 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 204 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 208 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 212 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(6, ~#vortex_pci_tbl~0.base, 216 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 224 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36865, ~#vortex_pci_tbl~0.base, 228 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 232 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 236 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 240 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 244 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(7, ~#vortex_pci_tbl~0.base, 248 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 256 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36868, ~#vortex_pci_tbl~0.base, 260 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 264 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 268 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 272 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 276 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(8, ~#vortex_pci_tbl~0.base, 280 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 288 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36869, ~#vortex_pci_tbl~0.base, 292 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 296 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 300 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 304 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 308 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(9, ~#vortex_pci_tbl~0.base, 312 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 320 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36870, ~#vortex_pci_tbl~0.base, 324 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 328 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 332 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 336 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 340 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(10, ~#vortex_pci_tbl~0.base, 344 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 352 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36874, ~#vortex_pci_tbl~0.base, 356 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 360 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 364 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 368 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 372 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(11, ~#vortex_pci_tbl~0.base, 376 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 384 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36944, ~#vortex_pci_tbl~0.base, 388 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 392 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 396 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 400 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 404 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(12, ~#vortex_pci_tbl~0.base, 408 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 416 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36945, ~#vortex_pci_tbl~0.base, 420 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 424 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 428 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 432 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 436 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(13, ~#vortex_pci_tbl~0.base, 440 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 448 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36948, ~#vortex_pci_tbl~0.base, 452 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 456 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 460 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 464 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 468 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(14, ~#vortex_pci_tbl~0.base, 472 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 480 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36949, ~#vortex_pci_tbl~0.base, 484 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 488 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 492 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 496 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 500 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(15, ~#vortex_pci_tbl~0.base, 504 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 512 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36952, ~#vortex_pci_tbl~0.base, 516 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 520 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 524 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 528 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 532 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(16, ~#vortex_pci_tbl~0.base, 536 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 544 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36954, ~#vortex_pci_tbl~0.base, 548 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 552 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 556 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 560 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 564 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(17, ~#vortex_pci_tbl~0.base, 568 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 576 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37376, ~#vortex_pci_tbl~0.base, 580 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 584 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 588 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 592 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 596 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(18, ~#vortex_pci_tbl~0.base, 600 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 608 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37378, ~#vortex_pci_tbl~0.base, 612 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 616 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 620 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 624 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 628 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(19, ~#vortex_pci_tbl~0.base, 632 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 640 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(38912, ~#vortex_pci_tbl~0.base, 644 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 648 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 652 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 656 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 660 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(20, ~#vortex_pci_tbl~0.base, 664 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 672 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(38917, ~#vortex_pci_tbl~0.base, 676 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 680 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 684 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 688 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 692 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(21, ~#vortex_pci_tbl~0.base, 696 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 704 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(30278, ~#vortex_pci_tbl~0.base, 708 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 712 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 716 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 720 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 724 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22, ~#vortex_pci_tbl~0.base, 728 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 736 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(20565, ~#vortex_pci_tbl~0.base, 740 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 744 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 748 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 752 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 756 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(23, ~#vortex_pci_tbl~0.base, 760 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 768 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(24661, ~#vortex_pci_tbl~0.base, 772 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 776 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 780 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 784 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 788 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(24, ~#vortex_pci_tbl~0.base, 792 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 800 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(24662, ~#vortex_pci_tbl~0.base, 804 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 808 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 812 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 816 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 820 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(25, ~#vortex_pci_tbl~0.base, 824 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 832 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(23383, ~#vortex_pci_tbl~0.base, 836 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 840 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 844 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 848 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 852 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(26, ~#vortex_pci_tbl~0.base, 856 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 864 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(20567, ~#vortex_pci_tbl~0.base, 868 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 872 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 876 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 880 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 884 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(27, ~#vortex_pci_tbl~0.base, 888 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 896 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(20823, ~#vortex_pci_tbl~0.base, 900 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 904 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 908 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 912 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 916 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(28, ~#vortex_pci_tbl~0.base, 920 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 928 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(21079, ~#vortex_pci_tbl~0.base, 932 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 936 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 940 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 944 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 948 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(29, ~#vortex_pci_tbl~0.base, 952 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 960 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(25952, ~#vortex_pci_tbl~0.base, 964 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 968 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 972 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 976 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 980 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(30, ~#vortex_pci_tbl~0.base, 984 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 992 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(25954, ~#vortex_pci_tbl~0.base, 996 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1000 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1004 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1008 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1012 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(31, ~#vortex_pci_tbl~0.base, 1016 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1024 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(25956, ~#vortex_pci_tbl~0.base, 1028 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1032 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1036 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1040 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1044 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(32, ~#vortex_pci_tbl~0.base, 1048 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1056 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(17664, ~#vortex_pci_tbl~0.base, 1060 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1064 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1068 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1072 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1076 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(33, ~#vortex_pci_tbl~0.base, 1080 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1088 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37377, ~#vortex_pci_tbl~0.base, 1092 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1096 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1100 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1104 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1108 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(34, ~#vortex_pci_tbl~0.base, 1112 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1120 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4609, ~#vortex_pci_tbl~0.base, 1124 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1128 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1132 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1136 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1140 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(35, ~#vortex_pci_tbl~0.base, 1144 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1152 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4610, ~#vortex_pci_tbl~0.base, 1156 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1160 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1164 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1168 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1172 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36, ~#vortex_pci_tbl~0.base, 1176 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1184 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36950, ~#vortex_pci_tbl~0.base, 1188 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1192 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1196 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1200 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1204 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37, ~#vortex_pci_tbl~0.base, 1208 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1216 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37392, ~#vortex_pci_tbl~0.base, 1220 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1224 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1228 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1232 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1236 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(38, ~#vortex_pci_tbl~0.base, 1240 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1248 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1252 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1256 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1260 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1264 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1268 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1272 + ~#vortex_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#media_tbl~0.base, ~#media_tbl~0.offset := 436, 0;call #Ultimate.allocInit(264, 436);call write~init~$Pointer$(43, 0, ~#media_tbl~0.base, ~#media_tbl~0.offset, 8);call write~init~int(192, ~#media_tbl~0.base, 8 + ~#media_tbl~0.offset, 4);call write~init~int(8, ~#media_tbl~0.base, 12 + ~#media_tbl~0.offset, 4);call write~init~int(3, ~#media_tbl~0.base, 16 + ~#media_tbl~0.offset, 4);call write~init~int(350, ~#media_tbl~0.base, 20 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(44, 0, ~#media_tbl~0.base, 24 + ~#media_tbl~0.offset, 8);call write~init~int(8, ~#media_tbl~0.base, 32 + ~#media_tbl~0.offset, 4);call write~init~int(32, ~#media_tbl~0.base, 36 + ~#media_tbl~0.offset, 4);call write~init~int(10, ~#media_tbl~0.base, 40 + ~#media_tbl~0.offset, 4);call write~init~int(25, ~#media_tbl~0.base, 44 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(45, 0, ~#media_tbl~0.base, 48 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 56 + ~#media_tbl~0.offset, 4);call write~init~int(128, ~#media_tbl~0.base, 60 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 64 + ~#media_tbl~0.offset, 4);call write~init~int(10000, ~#media_tbl~0.base, 68 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(46, 0, ~#media_tbl~0.base, 72 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 80 + ~#media_tbl~0.offset, 4);call write~init~int(16, ~#media_tbl~0.base, 84 + ~#media_tbl~0.offset, 4);call write~init~int(1, ~#media_tbl~0.base, 88 + ~#media_tbl~0.offset, 4);call write~init~int(25, ~#media_tbl~0.base, 92 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(47, 0, ~#media_tbl~0.base, 96 + ~#media_tbl~0.offset, 8);call write~init~int(128, ~#media_tbl~0.base, 104 + ~#media_tbl~0.offset, 4);call write~init~int(2, ~#media_tbl~0.base, 108 + ~#media_tbl~0.offset, 4);call write~init~int(5, ~#media_tbl~0.base, 112 + ~#media_tbl~0.offset, 4);call write~init~int(350, ~#media_tbl~0.base, 116 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(48, 0, ~#media_tbl~0.base, 120 + ~#media_tbl~0.offset, 8);call write~init~int(128, ~#media_tbl~0.base, 128 + ~#media_tbl~0.offset, 4);call write~init~int(4, ~#media_tbl~0.base, 132 + ~#media_tbl~0.offset, 4);call write~init~int(6, ~#media_tbl~0.base, 136 + ~#media_tbl~0.offset, 4);call write~init~int(350, ~#media_tbl~0.base, 140 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(49, 0, ~#media_tbl~0.base, 144 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 152 + ~#media_tbl~0.offset, 4);call write~init~int(65, ~#media_tbl~0.base, 156 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 160 + ~#media_tbl~0.offset, 4);call write~init~int(750, ~#media_tbl~0.base, 164 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(50, 0, ~#media_tbl~0.base, 168 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 176 + ~#media_tbl~0.offset, 4);call write~init~int(1, ~#media_tbl~0.base, 180 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 184 + ~#media_tbl~0.offset, 4);call write~init~int(10000, ~#media_tbl~0.base, 188 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(51, 0, ~#media_tbl~0.base, 192 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 200 + ~#media_tbl~0.offset, 4);call write~init~int(65, ~#media_tbl~0.base, 204 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 208 + ~#media_tbl~0.offset, 4);call write~init~int(750, ~#media_tbl~0.base, 212 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(52, 0, ~#media_tbl~0.base, 216 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 224 + ~#media_tbl~0.offset, 4);call write~init~int(65, ~#media_tbl~0.base, 228 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 232 + ~#media_tbl~0.offset, 4);call write~init~int(750, ~#media_tbl~0.base, 236 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(53, 0, ~#media_tbl~0.base, 240 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 248 + ~#media_tbl~0.offset, 4);call write~init~int(255, ~#media_tbl~0.base, 252 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 256 + ~#media_tbl~0.offset, 4);call write~init~int(10000, ~#media_tbl~0.base, 260 + ~#media_tbl~0.offset, 4);~#ethtool_stats_keys~0.base, ~#ethtool_stats_keys~0.offset := 437, 0;call #Ultimate.allocInit(160, 437);call write~init~int(116, ~#ethtool_stats_keys~0.base, ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 1 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 2 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(100, ~#ethtool_stats_keys~0.base, 3 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 4 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(102, ~#ethtool_stats_keys~0.base, 5 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 6 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(114, ~#ethtool_stats_keys~0.base, 7 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(114, ~#ethtool_stats_keys~0.base, 8 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 9 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(100, ~#ethtool_stats_keys~0.base, 10 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 11 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 12 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 13 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 14 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 15 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 16 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 17 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 18 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 19 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 20 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 21 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 22 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 23 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 24 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 25 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 26 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 27 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 28 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 29 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 30 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 31 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(116, ~#ethtool_stats_keys~0.base, 32 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 33 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 34 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(109, ~#ethtool_stats_keys~0.base, 35 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(97, ~#ethtool_stats_keys~0.base, 36 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 37 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 38 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(99, ~#ethtool_stats_keys~0.base, 39 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 40 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 41 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 42 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 43 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 44 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 45 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 46 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(110, ~#ethtool_stats_keys~0.base, 47 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 48 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 49 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 50 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 51 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 52 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 53 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 54 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 55 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 56 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 57 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 58 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 59 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 60 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 61 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 62 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 63 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(116, ~#ethtool_stats_keys~0.base, 64 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 65 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 66 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(109, ~#ethtool_stats_keys~0.base, 67 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(117, ~#ethtool_stats_keys~0.base, 68 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 69 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(116, ~#ethtool_stats_keys~0.base, 70 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 71 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(112, ~#ethtool_stats_keys~0.base, 72 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 73 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 74 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 75 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(99, ~#ethtool_stats_keys~0.base, 76 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 77 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 78 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 79 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 80 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 81 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 82 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 83 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(110, ~#ethtool_stats_keys~0.base, 84 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 85 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 86 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 87 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 88 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 89 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 90 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 91 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 92 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 93 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 94 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 95 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(116, ~#ethtool_stats_keys~0.base, 96 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 97 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 98 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 99 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 100 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(110, ~#ethtool_stats_keys~0.base, 101 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(103, ~#ethtool_stats_keys~0.base, 102 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 103 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 104 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 105 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(99, ~#ethtool_stats_keys~0.base, 106 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 107 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 108 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 109 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 110 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 111 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 112 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 113 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(110, ~#ethtool_stats_keys~0.base, 114 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 115 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 116 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 117 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 118 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 119 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 120 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 121 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 122 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 123 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 124 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 125 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 126 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 127 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(114, ~#ethtool_stats_keys~0.base, 128 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 129 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 130 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(98, ~#ethtool_stats_keys~0.base, 131 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(97, ~#ethtool_stats_keys~0.base, 132 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(100, ~#ethtool_stats_keys~0.base, 133 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 134 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 135 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 136 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(100, ~#ethtool_stats_keys~0.base, 137 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 138 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 139 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 140 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 141 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 142 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 143 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 144 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 145 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 146 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 147 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 148 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 149 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 150 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 151 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 152 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 153 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 154 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 155 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 156 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 157 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 158 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 159 + ~#ethtool_stats_keys~0.offset, 1);~#options~0.base, ~#options~0.offset := 438, 0;call #Ultimate.allocInit(32, 438);call write~init~int(-1, ~#options~0.base, ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 4 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 8 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 12 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 16 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 20 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 24 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 28 + ~#options~0.offset, 4);~#full_duplex~0.base, ~#full_duplex~0.offset := 439, 0;call #Ultimate.allocInit(32, 439);call write~init~int(-1, ~#full_duplex~0.base, ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 4 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 8 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 12 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 16 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 20 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 24 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 28 + ~#full_duplex~0.offset, 4);~#hw_checksums~0.base, ~#hw_checksums~0.offset := 440, 0;call #Ultimate.allocInit(32, 440);call write~init~int(-1, ~#hw_checksums~0.base, ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 4 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 8 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 12 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 16 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 20 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 24 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 28 + ~#hw_checksums~0.offset, 4);~#flow_ctrl~0.base, ~#flow_ctrl~0.offset := 441, 0;call #Ultimate.allocInit(32, 441);call write~init~int(-1, ~#flow_ctrl~0.base, ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 4 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 8 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 12 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 16 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 20 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 24 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 28 + ~#flow_ctrl~0.offset, 4);~#enable_wol~0.base, ~#enable_wol~0.offset := 442, 0;call #Ultimate.allocInit(32, 442);call write~init~int(-1, ~#enable_wol~0.base, ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 4 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 8 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 12 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 16 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 20 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 24 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 28 + ~#enable_wol~0.offset, 4);~#use_mmio~0.base, ~#use_mmio~0.offset := 443, 0;call #Ultimate.allocInit(32, 443);call write~init~int(-1, ~#use_mmio~0.base, ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 4 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 8 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 12 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 16 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 20 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 24 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 28 + ~#use_mmio~0.offset, 4);~global_options~0 := -1;~global_full_duplex~0 := -1;~global_enable_wol~0 := -1;~global_use_mmio~0 := -1;~compaq_ioaddr~0 := 0;~compaq_irq~0 := 0;~compaq_device_id~0 := 22784;~compaq_net_device~0.base, ~compaq_net_device~0.offset := 0, 0;~vortex_cards_found~0 := 0;~#vortex_pm_ops~0.base, ~#vortex_pm_ops~0.offset := 444, 0;call #Ultimate.allocInit(184, 444);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 8 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_suspend.base, #funAddr~vortex_suspend.offset, ~#vortex_pm_ops~0.base, 16 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_resume.base, #funAddr~vortex_resume.offset, ~#vortex_pm_ops~0.base, 24 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_suspend.base, #funAddr~vortex_suspend.offset, ~#vortex_pm_ops~0.base, 32 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_resume.base, #funAddr~vortex_resume.offset, ~#vortex_pm_ops~0.base, 40 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_suspend.base, #funAddr~vortex_suspend.offset, ~#vortex_pm_ops~0.base, 48 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_resume.base, #funAddr~vortex_resume.offset, ~#vortex_pm_ops~0.base, 56 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 64 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 72 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 80 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 88 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 96 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 104 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 112 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 120 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 128 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 136 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 144 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 152 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 160 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 168 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 176 + ~#vortex_pm_ops~0.offset, 8);~#boomrang_netdev_ops~0.base, ~#boomrang_netdev_ops~0.offset := 445, 0;call #Ultimate.allocInit(472, 445);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 8 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_open.base, #funAddr~vortex_open.offset, ~#boomrang_netdev_ops~0.base, 16 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_close.base, #funAddr~vortex_close.offset, ~#boomrang_netdev_ops~0.base, 24 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~boomerang_start_xmit.base, #funAddr~boomerang_start_xmit.offset, ~#boomrang_netdev_ops~0.base, 32 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 40 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 48 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~set_rx_mode.base, #funAddr~set_rx_mode.offset, ~#boomrang_netdev_ops~0.base, 56 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset, ~#boomrang_netdev_ops~0.base, 64 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset, ~#boomrang_netdev_ops~0.base, 72 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_ioctl.base, #funAddr~vortex_ioctl.offset, ~#boomrang_netdev_ops~0.base, 80 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 88 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset, ~#boomrang_netdev_ops~0.base, 96 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 104 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_tx_timeout.base, #funAddr~vortex_tx_timeout.offset, ~#boomrang_netdev_ops~0.base, 112 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 120 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_stats.base, #funAddr~vortex_get_stats.offset, ~#boomrang_netdev_ops~0.base, 128 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 136 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 144 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~poll_vortex.base, #funAddr~poll_vortex.offset, ~#boomrang_netdev_ops~0.base, 152 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 160 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 168 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 176 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 184 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 192 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 200 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 208 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 216 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 224 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 232 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 240 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 248 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 256 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 264 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 272 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 280 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 288 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 296 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 304 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 312 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 320 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 328 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 336 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 344 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 352 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 360 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 368 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 376 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 384 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 392 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 400 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 408 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 416 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 424 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 432 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 440 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 448 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 456 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 464 + ~#boomrang_netdev_ops~0.offset, 8);~#vortex_netdev_ops~0.base, ~#vortex_netdev_ops~0.offset := 446, 0;call #Ultimate.allocInit(472, 446);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 8 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_open.base, #funAddr~vortex_open.offset, ~#vortex_netdev_ops~0.base, 16 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_close.base, #funAddr~vortex_close.offset, ~#vortex_netdev_ops~0.base, 24 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_start_xmit.base, #funAddr~vortex_start_xmit.offset, ~#vortex_netdev_ops~0.base, 32 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 40 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 48 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~set_rx_mode.base, #funAddr~set_rx_mode.offset, ~#vortex_netdev_ops~0.base, 56 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset, ~#vortex_netdev_ops~0.base, 64 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset, ~#vortex_netdev_ops~0.base, 72 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_ioctl.base, #funAddr~vortex_ioctl.offset, ~#vortex_netdev_ops~0.base, 80 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 88 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset, ~#vortex_netdev_ops~0.base, 96 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 104 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_tx_timeout.base, #funAddr~vortex_tx_timeout.offset, ~#vortex_netdev_ops~0.base, 112 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 120 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_stats.base, #funAddr~vortex_get_stats.offset, ~#vortex_netdev_ops~0.base, 128 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 136 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 144 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~poll_vortex.base, #funAddr~poll_vortex.offset, ~#vortex_netdev_ops~0.base, 152 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 160 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 168 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 176 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 184 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 192 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 200 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 208 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 216 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 224 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 232 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 240 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 248 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 256 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 264 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 272 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 280 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 288 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 296 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 304 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 312 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 320 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 328 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 336 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 344 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 352 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 360 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 368 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 376 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 384 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 392 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 400 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 408 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 416 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 424 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 432 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 440 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 448 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 456 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 464 + ~#vortex_netdev_ops~0.offset, 8);~#vortex_ethtool_ops~0.base, ~#vortex_ethtool_ops~0.offset := 447, 0;call #Ultimate.allocInit(368, 447);call write~init~$Pointer$(#funAddr~vortex_get_settings.base, #funAddr~vortex_get_settings.offset, ~#vortex_ethtool_ops~0.base, ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_set_settings.base, #funAddr~vortex_set_settings.offset, ~#vortex_ethtool_ops~0.base, 8 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_drvinfo.base, #funAddr~vortex_get_drvinfo.offset, ~#vortex_ethtool_ops~0.base, 16 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 24 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 32 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_wol.base, #funAddr~vortex_get_wol.offset, ~#vortex_ethtool_ops~0.base, 40 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_set_wol.base, #funAddr~vortex_set_wol.offset, ~#vortex_ethtool_ops~0.base, 48 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_msglevel.base, #funAddr~vortex_get_msglevel.offset, ~#vortex_ethtool_ops~0.base, 56 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_set_msglevel.base, #funAddr~vortex_set_msglevel.offset, ~#vortex_ethtool_ops~0.base, 64 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_nway_reset.base, #funAddr~vortex_nway_reset.offset, ~#vortex_ethtool_ops~0.base, 72 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~ethtool_op_get_link.base, #funAddr~ethtool_op_get_link.offset, ~#vortex_ethtool_ops~0.base, 80 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 88 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 96 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 104 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 112 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 120 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 128 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 136 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 144 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 152 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 160 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_strings.base, #funAddr~vortex_get_strings.offset, ~#vortex_ethtool_ops~0.base, 168 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 176 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_ethtool_stats.base, #funAddr~vortex_get_ethtool_stats.offset, ~#vortex_ethtool_ops~0.base, 184 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 192 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 200 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 208 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 216 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_sset_count.base, #funAddr~vortex_get_sset_count.offset, ~#vortex_ethtool_ops~0.base, 224 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 232 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 240 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 248 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 256 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 264 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 272 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 280 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 288 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 296 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 304 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 312 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 320 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~ethtool_op_get_ts_info.base, #funAddr~ethtool_op_get_ts_info.offset, ~#vortex_ethtool_ops~0.base, 328 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 336 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 344 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 352 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 360 + ~#vortex_ethtool_ops~0.offset, 8);~#vortex_driver~0.base, ~#vortex_driver~0.offset := 448, 0;call #Ultimate.allocInit(301, 448);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 8 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(344, 0, ~#vortex_driver~0.base, 16 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(~#vortex_pci_tbl~0.base, ~#vortex_pci_tbl~0.offset, ~#vortex_driver~0.base, 24 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_init_one.base, #funAddr~vortex_init_one.offset, ~#vortex_driver~0.base, 32 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_remove_one.base, #funAddr~vortex_remove_one.offset, ~#vortex_driver~0.base, 40 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 48 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 56 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 64 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 72 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 80 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 88 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 96 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 104 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 112 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 120 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 128 + ~#vortex_driver~0.offset, 8);call write~init~int(0, ~#vortex_driver~0.base, 136 + ~#vortex_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 137 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 145 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 153 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 161 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 169 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 177 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 185 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 193 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(~#vortex_pm_ops~0.base, ~#vortex_pm_ops~0.offset, ~#vortex_driver~0.base, 201 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 209 + ~#vortex_driver~0.offset, 8);call write~init~int(0, ~#vortex_driver~0.base, 217 + ~#vortex_driver~0.offset, 4);call write~init~int(0, ~#vortex_driver~0.base, 221 + ~#vortex_driver~0.offset, 4);call write~init~int(0, ~#vortex_driver~0.base, 225 + ~#vortex_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 229 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 237 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 245 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 253 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 261 + ~#vortex_driver~0.offset, 8);call write~init~int(0, ~#vortex_driver~0.base, 269 + ~#vortex_driver~0.offset, 4);call write~init~int(0, ~#vortex_driver~0.base, 273 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 285 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 293 + ~#vortex_driver~0.offset, 8);~vortex_have_pci~0 := 0;~vortex_have_eisa~0 := 0;~ldv_thread_0~0.identifier := 0;~ldv_thread_0~0.function.base, ~ldv_thread_0~0.function.offset := 0, 0;~ldv_thread_1~0.identifier := 0;~ldv_thread_1~0.function.base, ~ldv_thread_1~0.function.offset := 0, 0;~ldv_thread_16~0.identifier := 0;~ldv_thread_16~0.function.base, ~ldv_thread_16~0.function.offset := 0, 0;~ldv_thread_2~0.identifier := 0;~ldv_thread_2~0.function.base, ~ldv_thread_2~0.function.offset := 0, 0;~ldv_thread_3~0.identifier := 0;~ldv_thread_3~0.function.base, ~ldv_thread_3~0.function.offset := 0, 0;~ldv_thread_4~0.identifier := 0;~ldv_thread_4~0.function.base, ~ldv_thread_4~0.function.offset := 0, 0;~ldv_thread_5~0.identifier := 0;~ldv_thread_5~0.function.base, ~ldv_thread_5~0.function.offset := 0, 0;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_vortex_private~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_mii_lock_of_vortex_private~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1;~ldv_spin_window_lock_of_vortex_private~0 := 1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,061 INFO L290 TraceCheckUtils]: 1: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_ldv_initialize } true; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,063 INFO L290 TraceCheckUtils]: 2: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_entry_EMGentry_16 } true;ldv_entry_EMGentry_16_#in~arg0#1.base, ldv_entry_EMGentry_16_#in~arg0#1.offset := 0, 0;havoc ldv_entry_EMGentry_16_#t~ret1441#1, ldv_entry_EMGentry_16_#t~ret1442#1, ldv_entry_EMGentry_16_#t~ret1443#1, ldv_entry_EMGentry_16_#t~ret1444#1, ldv_entry_EMGentry_16_~arg0#1.base, ldv_entry_EMGentry_16_~arg0#1.offset, ldv_entry_EMGentry_16_~ldv_16_exit_vortex_cleanup_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_exit_vortex_cleanup_default~0#1.offset, ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.offset, ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1, ldv_entry_EMGentry_16_~tmp~85#1, ldv_entry_EMGentry_16_~tmp___0~45#1;ldv_entry_EMGentry_16_~arg0#1.base, ldv_entry_EMGentry_16_~arg0#1.offset := ldv_entry_EMGentry_16_#in~arg0#1.base, ldv_entry_EMGentry_16_#in~arg0#1.offset;havoc ldv_entry_EMGentry_16_~ldv_16_exit_vortex_cleanup_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_exit_vortex_cleanup_default~0#1.offset;havoc ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.offset;havoc ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1;havoc ldv_entry_EMGentry_16_~tmp~85#1;havoc ldv_entry_EMGentry_16_~tmp___0~45#1;assume { :begin_inline_ldv_EMGentry_init_vortex_init_16_9 } true;ldv_EMGentry_init_vortex_init_16_9_#in~arg0#1.base, ldv_EMGentry_init_vortex_init_16_9_#in~arg0#1.offset := ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.offset;havoc ldv_EMGentry_init_vortex_init_16_9_#res#1;havoc ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1, ldv_EMGentry_init_vortex_init_16_9_~arg0#1.base, ldv_EMGentry_init_vortex_init_16_9_~arg0#1.offset, ldv_EMGentry_init_vortex_init_16_9_~tmp~76#1;ldv_EMGentry_init_vortex_init_16_9_~arg0#1.base, ldv_EMGentry_init_vortex_init_16_9_~arg0#1.offset := ldv_EMGentry_init_vortex_init_16_9_#in~arg0#1.base, ldv_EMGentry_init_vortex_init_16_9_#in~arg0#1.offset;havoc ldv_EMGentry_init_vortex_init_16_9_~tmp~76#1;assume { :begin_inline_vortex_init } true;havoc vortex_init_#res#1;havoc vortex_init_#t~ret1411#1, vortex_init_#t~ret1412#1, vortex_init_#t~ite1413#1, vortex_init_~pci_rc~0#1, vortex_init_~eisa_rc~0#1;havoc vortex_init_~pci_rc~0#1;havoc vortex_init_~eisa_rc~0#1;assume { :begin_inline_ldv___pci_register_driver_138 } true;ldv___pci_register_driver_138_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg1#1.offset, ldv___pci_register_driver_138_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg2#1.offset, ldv___pci_register_driver_138_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg3#1.offset := ~#vortex_driver~0.base, ~#vortex_driver~0.offset, ~#__this_module~0.base, ~#__this_module~0.offset, 345, 0;havoc ldv___pci_register_driver_138_#res#1;havoc ldv___pci_register_driver_138_#t~ret1641#1, ldv___pci_register_driver_138_#t~ret1642#1, ldv___pci_register_driver_138_~ldv_func_arg1#1.base, ldv___pci_register_driver_138_~ldv_func_arg1#1.offset, ldv___pci_register_driver_138_~ldv_func_arg2#1.base, ldv___pci_register_driver_138_~ldv_func_arg2#1.offset, ldv___pci_register_driver_138_~ldv_func_arg3#1.base, ldv___pci_register_driver_138_~ldv_func_arg3#1.offset, ldv___pci_register_driver_138_~ldv_func_res~9#1, ldv___pci_register_driver_138_~tmp~115#1, ldv___pci_register_driver_138_~tmp___0~60#1;ldv___pci_register_driver_138_~ldv_func_arg1#1.base, ldv___pci_register_driver_138_~ldv_func_arg1#1.offset := ldv___pci_register_driver_138_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg1#1.offset;ldv___pci_register_driver_138_~ldv_func_arg2#1.base, ldv___pci_register_driver_138_~ldv_func_arg2#1.offset := ldv___pci_register_driver_138_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg2#1.offset;ldv___pci_register_driver_138_~ldv_func_arg3#1.base, ldv___pci_register_driver_138_~ldv_func_arg3#1.offset := ldv___pci_register_driver_138_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_138_~ldv_func_res~9#1;havoc ldv___pci_register_driver_138_~tmp~115#1;havoc ldv___pci_register_driver_138_~tmp___0~60#1;assume { :begin_inline___pci_register_driver } true;__pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset, __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset, __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset := ldv___pci_register_driver_138_~ldv_func_arg1#1.base, ldv___pci_register_driver_138_~ldv_func_arg1#1.offset, ldv___pci_register_driver_138_~ldv_func_arg2#1.base, ldv___pci_register_driver_138_~ldv_func_arg2#1.offset, ldv___pci_register_driver_138_~ldv_func_arg3#1.base, ldv___pci_register_driver_138_~ldv_func_arg3#1.offset;havoc __pci_register_driver_#res#1;havoc __pci_register_driver_#t~nondet1759#1, __pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset, __pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset, __pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset;__pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset := __pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset;__pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset := __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset;__pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset := __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset;assume -2147483648 <= __pci_register_driver_#t~nondet1759#1 && __pci_register_driver_#t~nondet1759#1 <= 2147483647;__pci_register_driver_#res#1 := __pci_register_driver_#t~nondet1759#1;havoc __pci_register_driver_#t~nondet1759#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,063 INFO L290 TraceCheckUtils]: 3: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv___pci_register_driver_138_#t~ret1641#1 := __pci_register_driver_#res#1;assume { :end_inline___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_138_#t~ret1641#1 && ldv___pci_register_driver_138_#t~ret1641#1 <= 2147483647;ldv___pci_register_driver_138_~tmp~115#1 := ldv___pci_register_driver_138_#t~ret1641#1;havoc ldv___pci_register_driver_138_#t~ret1641#1;ldv___pci_register_driver_138_~ldv_func_res~9#1 := ldv___pci_register_driver_138_~tmp~115#1;assume { :begin_inline_ldv___pci_register_driver } true;ldv___pci_register_driver_#in~arg0#1, ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset, ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset, ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset := ldv___pci_register_driver_138_~ldv_func_res~9#1, ldv___pci_register_driver_138_~ldv_func_arg1#1.base, ldv___pci_register_driver_138_~ldv_func_arg1#1.offset, ldv___pci_register_driver_138_~ldv_func_arg2#1.base, ldv___pci_register_driver_138_~ldv_func_arg2#1.offset, ldv___pci_register_driver_138_~ldv_func_arg3#1.base, ldv___pci_register_driver_138_~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_#res#1;havoc ldv___pci_register_driver_#t~ret1418#1, ldv___pci_register_driver_~arg0#1, ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset, ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset, ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset, ldv___pci_register_driver_~ldv_15_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_15_pci_driver_pci_driver~0#1.offset, ldv___pci_register_driver_~tmp~77#1;ldv___pci_register_driver_~arg0#1 := ldv___pci_register_driver_#in~arg0#1;ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset := ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset;ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset := ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset;ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset := ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset;havoc ldv___pci_register_driver_~ldv_15_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_15_pci_driver_pci_driver~0#1.offset;havoc ldv___pci_register_driver_~tmp~77#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,063 INFO L272 TraceCheckUtils]: 4: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv___pci_register_driver_#t~ret1418#1 := ldv_undef_int(); {2968#true} is VALID [2022-02-20 23:12:37,064 INFO L290 TraceCheckUtils]: 5: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:37,065 INFO L290 TraceCheckUtils]: 6: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,065 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7987#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,066 INFO L290 TraceCheckUtils]: 8: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume -2147483648 <= ldv___pci_register_driver_#t~ret1418#1 && ldv___pci_register_driver_#t~ret1418#1 <= 2147483647;ldv___pci_register_driver_~tmp~77#1 := ldv___pci_register_driver_#t~ret1418#1;havoc ldv___pci_register_driver_#t~ret1418#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,067 INFO L290 TraceCheckUtils]: 9: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(0 != ldv___pci_register_driver_~tmp~77#1); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,067 INFO L272 TraceCheckUtils]: 10: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_assume((if 0 != ldv___pci_register_driver_~arg0#1 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:37,074 INFO L290 TraceCheckUtils]: 11: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:37,074 INFO L290 TraceCheckUtils]: 12: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:37,074 INFO L290 TraceCheckUtils]: 13: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,077 INFO L284 TraceCheckUtils]: 14: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8049#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,077 INFO L290 TraceCheckUtils]: 15: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv___pci_register_driver_#res#1 := ldv___pci_register_driver_~arg0#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,078 INFO L290 TraceCheckUtils]: 16: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv___pci_register_driver_138_#t~ret1642#1 := ldv___pci_register_driver_#res#1;assume { :end_inline_ldv___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_138_#t~ret1642#1 && ldv___pci_register_driver_138_#t~ret1642#1 <= 2147483647;ldv___pci_register_driver_138_~tmp___0~60#1 := ldv___pci_register_driver_138_#t~ret1642#1;havoc ldv___pci_register_driver_138_#t~ret1642#1;ldv___pci_register_driver_138_#res#1 := ldv___pci_register_driver_138_~tmp___0~60#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,078 INFO L290 TraceCheckUtils]: 17: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} vortex_init_#t~ret1411#1 := ldv___pci_register_driver_138_#res#1;assume { :end_inline_ldv___pci_register_driver_138 } true;assume -2147483648 <= vortex_init_#t~ret1411#1 && vortex_init_#t~ret1411#1 <= 2147483647;vortex_init_~pci_rc~0#1 := vortex_init_#t~ret1411#1;havoc vortex_init_#t~ret1411#1;assume { :begin_inline_vortex_eisa_init } true;havoc vortex_eisa_init_#res#1;havoc vortex_eisa_init_#t~ret345#1.base, vortex_eisa_init_#t~ret345#1.offset, vortex_eisa_init_#t~ret346#1, vortex_eisa_init_~eisa_found~0#1, vortex_eisa_init_~orig_cards_found~0#1, vortex_eisa_init_~tmp~39#1, vortex_eisa_init_~tmp___0~14#1.base, vortex_eisa_init_~tmp___0~14#1.offset;havoc vortex_eisa_init_~eisa_found~0#1;havoc vortex_eisa_init_~orig_cards_found~0#1;havoc vortex_eisa_init_~tmp~39#1;havoc vortex_eisa_init_~tmp___0~14#1.base, vortex_eisa_init_~tmp___0~14#1.offset;vortex_eisa_init_~eisa_found~0#1 := 0;vortex_eisa_init_~orig_cards_found~0#1 := ~vortex_cards_found~0; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,078 INFO L290 TraceCheckUtils]: 18: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(0 != ~compaq_ioaddr~0); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,079 INFO L290 TraceCheckUtils]: 19: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} vortex_eisa_init_#res#1 := ~vortex_cards_found~0 - vortex_eisa_init_~orig_cards_found~0#1 + vortex_eisa_init_~eisa_found~0#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,079 INFO L290 TraceCheckUtils]: 20: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} vortex_init_#t~ret1412#1 := vortex_eisa_init_#res#1;assume { :end_inline_vortex_eisa_init } true;assume -2147483648 <= vortex_init_#t~ret1412#1 && vortex_init_#t~ret1412#1 <= 2147483647;vortex_init_~eisa_rc~0#1 := vortex_init_#t~ret1412#1;havoc vortex_init_#t~ret1412#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,080 INFO L290 TraceCheckUtils]: 21: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume 0 == vortex_init_~pci_rc~0#1;~vortex_have_pci~0 := 1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,080 INFO L290 TraceCheckUtils]: 22: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume vortex_init_~eisa_rc~0#1 > 0;~vortex_have_eisa~0 := 1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,080 INFO L290 TraceCheckUtils]: 23: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume 0 != ~vortex_have_pci~0 + ~vortex_have_eisa~0;vortex_init_#t~ite1413#1 := 0; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,081 INFO L290 TraceCheckUtils]: 24: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} vortex_init_#res#1 := vortex_init_#t~ite1413#1;havoc vortex_init_#t~ite1413#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,081 INFO L290 TraceCheckUtils]: 25: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1 := vortex_init_#res#1;assume { :end_inline_vortex_init } true;assume -2147483648 <= ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1 && ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1 <= 2147483647;ldv_EMGentry_init_vortex_init_16_9_~tmp~76#1 := ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1;havoc ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1;ldv_EMGentry_init_vortex_init_16_9_#res#1 := ldv_EMGentry_init_vortex_init_16_9_~tmp~76#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,081 INFO L290 TraceCheckUtils]: 26: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_entry_EMGentry_16_#t~ret1441#1 := ldv_EMGentry_init_vortex_init_16_9_#res#1;assume { :end_inline_ldv_EMGentry_init_vortex_init_16_9 } true;assume -2147483648 <= ldv_entry_EMGentry_16_#t~ret1441#1 && ldv_entry_EMGentry_16_#t~ret1441#1 <= 2147483647;ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1 := ldv_entry_EMGentry_16_#t~ret1441#1;havoc ldv_entry_EMGentry_16_#t~ret1441#1;assume { :begin_inline_ldv_post_init } true;ldv_post_init_#in~init_ret_val#1 := ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1;havoc ldv_post_init_#res#1;havoc ldv_post_init_#t~ret1654#1, ldv_post_init_~init_ret_val#1, ldv_post_init_~tmp~121#1;ldv_post_init_~init_ret_val#1 := ldv_post_init_#in~init_ret_val#1;havoc ldv_post_init_~tmp~121#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,082 INFO L272 TraceCheckUtils]: 27: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_post_init_#t~ret1654#1 := ldv_filter_positive_int(ldv_post_init_~init_ret_val#1); {2968#true} is VALID [2022-02-20 23:12:37,082 INFO L290 TraceCheckUtils]: 28: Hoare triple {2968#true} ~val := #in~val; {2968#true} is VALID [2022-02-20 23:12:37,082 INFO L272 TraceCheckUtils]: 29: Hoare triple {2968#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:37,082 INFO L290 TraceCheckUtils]: 30: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:37,082 INFO L290 TraceCheckUtils]: 31: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:37,082 INFO L290 TraceCheckUtils]: 32: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,083 INFO L284 TraceCheckUtils]: 33: Hoare quadruple {2968#true} {2968#true} #7811#return; {2968#true} is VALID [2022-02-20 23:12:37,083 INFO L290 TraceCheckUtils]: 34: Hoare triple {2968#true} #res := ~val; {2968#true} is VALID [2022-02-20 23:12:37,083 INFO L290 TraceCheckUtils]: 35: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,084 INFO L284 TraceCheckUtils]: 36: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8055#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,084 INFO L290 TraceCheckUtils]: 37: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume -2147483648 <= ldv_post_init_#t~ret1654#1 && ldv_post_init_#t~ret1654#1 <= 2147483647;ldv_post_init_~tmp~121#1 := ldv_post_init_#t~ret1654#1;havoc ldv_post_init_#t~ret1654#1;ldv_post_init_#res#1 := ldv_post_init_~tmp~121#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,084 INFO L290 TraceCheckUtils]: 38: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_entry_EMGentry_16_#t~ret1442#1 := ldv_post_init_#res#1;assume { :end_inline_ldv_post_init } true;assume -2147483648 <= ldv_entry_EMGentry_16_#t~ret1442#1 && ldv_entry_EMGentry_16_#t~ret1442#1 <= 2147483647;ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1 := ldv_entry_EMGentry_16_#t~ret1442#1;havoc ldv_entry_EMGentry_16_#t~ret1442#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,084 INFO L272 TraceCheckUtils]: 39: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_entry_EMGentry_16_#t~ret1443#1 := ldv_undef_int(); {2968#true} is VALID [2022-02-20 23:12:37,085 INFO L290 TraceCheckUtils]: 40: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:37,085 INFO L290 TraceCheckUtils]: 41: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,085 INFO L284 TraceCheckUtils]: 42: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8057#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,086 INFO L290 TraceCheckUtils]: 43: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume -2147483648 <= ldv_entry_EMGentry_16_#t~ret1443#1 && ldv_entry_EMGentry_16_#t~ret1443#1 <= 2147483647;ldv_entry_EMGentry_16_~tmp___0~45#1 := ldv_entry_EMGentry_16_#t~ret1443#1;havoc ldv_entry_EMGentry_16_#t~ret1443#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,086 INFO L290 TraceCheckUtils]: 44: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(0 != ldv_entry_EMGentry_16_~tmp___0~45#1); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,086 INFO L272 TraceCheckUtils]: 45: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_assume((if 0 == ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:37,086 INFO L290 TraceCheckUtils]: 46: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:37,086 INFO L290 TraceCheckUtils]: 47: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:37,087 INFO L290 TraceCheckUtils]: 48: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,087 INFO L284 TraceCheckUtils]: 49: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8065#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,087 INFO L272 TraceCheckUtils]: 50: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_entry_EMGentry_16_#t~ret1444#1 := ldv_undef_int(); {2968#true} is VALID [2022-02-20 23:12:37,087 INFO L290 TraceCheckUtils]: 51: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:37,088 INFO L290 TraceCheckUtils]: 52: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,088 INFO L284 TraceCheckUtils]: 53: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8067#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,088 INFO L290 TraceCheckUtils]: 54: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume -2147483648 <= ldv_entry_EMGentry_16_#t~ret1444#1 && ldv_entry_EMGentry_16_#t~ret1444#1 <= 2147483647;ldv_entry_EMGentry_16_~tmp~85#1 := ldv_entry_EMGentry_16_#t~ret1444#1;havoc ldv_entry_EMGentry_16_#t~ret1444#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,089 INFO L290 TraceCheckUtils]: 55: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume 0 != ldv_entry_EMGentry_16_~tmp~85#1;assume { :begin_inline_ldv_dispatch_register_platform_instance_15_16_5 } true;havoc ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.base, ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.offset, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.base, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.offset, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.base, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.offset;havoc ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.base, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.offset;havoc ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.base, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.offset; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,089 INFO L272 TraceCheckUtils]: 56: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.base, ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.offset := ldv_xmalloc(4); {3057#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 23:12:37,090 INFO L290 TraceCheckUtils]: 57: Hoare triple {3057#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~127.base, ~tmp~127.offset;havoc ~tmp___0~64;call #t~malloc1675.base, #t~malloc1675.offset := #Ultimate.allocOnHeap(~size);~tmp~127.base, ~tmp~127.offset := #t~malloc1675.base, #t~malloc1675.offset;havoc #t~malloc1675.base, #t~malloc1675.offset;~res~3.base, ~res~3.offset := ~tmp~127.base, ~tmp~127.offset; {2968#true} is VALID [2022-02-20 23:12:37,090 INFO L272 TraceCheckUtils]: 58: Hoare triple {2968#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:37,090 INFO L290 TraceCheckUtils]: 59: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:37,090 INFO L290 TraceCheckUtils]: 60: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:37,090 INFO L290 TraceCheckUtils]: 61: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,090 INFO L284 TraceCheckUtils]: 62: Hoare quadruple {2968#true} {2968#true} #7545#return; {2968#true} is VALID [2022-02-20 23:12:37,091 INFO L272 TraceCheckUtils]: 63: Hoare triple {2968#true} call #t~ret1676 := ldv_is_err(~res~3.base, ~res~3.offset); {2968#true} is VALID [2022-02-20 23:12:37,091 INFO L290 TraceCheckUtils]: 64: Hoare triple {2968#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {2968#true} is VALID [2022-02-20 23:12:37,091 INFO L290 TraceCheckUtils]: 65: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,091 INFO L284 TraceCheckUtils]: 66: Hoare quadruple {2968#true} {2968#true} #7547#return; {2968#true} is VALID [2022-02-20 23:12:37,091 INFO L290 TraceCheckUtils]: 67: Hoare triple {2968#true} assume -9223372036854775808 <= #t~ret1676 && #t~ret1676 <= 9223372036854775807;~tmp___0~64 := #t~ret1676;havoc #t~ret1676; {2968#true} is VALID [2022-02-20 23:12:37,091 INFO L272 TraceCheckUtils]: 68: Hoare triple {2968#true} call ldv_assume((if 0 == ~tmp___0~64 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:37,092 INFO L290 TraceCheckUtils]: 69: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:37,092 INFO L290 TraceCheckUtils]: 70: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:37,092 INFO L290 TraceCheckUtils]: 71: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,092 INFO L284 TraceCheckUtils]: 72: Hoare quadruple {2968#true} {2968#true} #7549#return; {2968#true} is VALID [2022-02-20 23:12:37,092 INFO L290 TraceCheckUtils]: 73: Hoare triple {2968#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {2968#true} is VALID [2022-02-20 23:12:37,093 INFO L290 TraceCheckUtils]: 74: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,094 INFO L284 TraceCheckUtils]: 75: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8069#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,094 INFO L290 TraceCheckUtils]: 76: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.base, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.offset := ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.base, ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.offset;havoc ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.base, ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.offset;ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.base, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.offset := ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.base, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.offset;assume { :begin_inline_ldv_pm_platform_instance_4 } true;ldv_pm_platform_instance_4_#in~arg0#1.base, ldv_pm_platform_instance_4_#in~arg0#1.offset := ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.base, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.offset;havoc ldv_pm_platform_instance_4_#t~ret1545#1, ldv_pm_platform_instance_4_#t~ret1546#1.base, ldv_pm_platform_instance_4_#t~ret1546#1.offset, ldv_pm_platform_instance_4_#t~mem1547#1.base, ldv_pm_platform_instance_4_#t~mem1547#1.offset, ldv_pm_platform_instance_4_#t~mem1548#1.base, ldv_pm_platform_instance_4_#t~mem1548#1.offset, ldv_pm_platform_instance_4_#t~ret1549#1, ldv_pm_platform_instance_4_#t~ret1550#1, ldv_pm_platform_instance_4_#t~ret1551#1, ldv_pm_platform_instance_4_#t~ret1552#1, ldv_pm_platform_instance_4_#t~ret1553#1.base, ldv_pm_platform_instance_4_#t~ret1553#1.offset, ldv_pm_platform_instance_4_#t~mem1554#1.base, ldv_pm_platform_instance_4_#t~mem1554#1.offset, ldv_pm_platform_instance_4_#t~mem1555#1.base, ldv_pm_platform_instance_4_#t~mem1555#1.offset, ldv_pm_platform_instance_4_~arg0#1.base, ldv_pm_platform_instance_4_~arg0#1.offset, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.base, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.offset, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.offset, ldv_pm_platform_instance_4_~ldv_4_ldv_param_3_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_3_0_default~0#1.offset, ldv_pm_platform_instance_4_~ldv_4_probed_default~0#1, ldv_pm_platform_instance_4_~tmp~95#1.base, ldv_pm_platform_instance_4_~tmp~95#1.offset, ldv_pm_platform_instance_4_~tmp___0~48#1, ldv_pm_platform_instance_4_~tmp___1~31#1, ldv_pm_platform_instance_4_~tmp___2~21#1, ldv_pm_platform_instance_4_~tmp___3~19#1.base, ldv_pm_platform_instance_4_~tmp___3~19#1.offset;ldv_pm_platform_instance_4_~arg0#1.base, ldv_pm_platform_instance_4_~arg0#1.offset := ldv_pm_platform_instance_4_#in~arg0#1.base, ldv_pm_platform_instance_4_#in~arg0#1.offset;havoc ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.base, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.offset;havoc ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.offset;havoc ldv_pm_platform_instance_4_~ldv_4_ldv_param_3_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_3_0_default~0#1.offset;havoc ldv_pm_platform_instance_4_~ldv_4_probed_default~0#1;havoc ldv_pm_platform_instance_4_~tmp~95#1.base, ldv_pm_platform_instance_4_~tmp~95#1.offset;havoc ldv_pm_platform_instance_4_~tmp___0~48#1;havoc ldv_pm_platform_instance_4_~tmp___1~31#1;havoc ldv_pm_platform_instance_4_~tmp___2~21#1;havoc ldv_pm_platform_instance_4_~tmp___3~19#1.base, ldv_pm_platform_instance_4_~tmp___3~19#1.offset;ldv_pm_platform_instance_4_~ldv_4_probed_default~0#1 := 1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,095 INFO L272 TraceCheckUtils]: 77: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_pm_platform_instance_4_#t~ret1545#1 := ldv_undef_int(); {2968#true} is VALID [2022-02-20 23:12:37,095 INFO L290 TraceCheckUtils]: 78: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:37,095 INFO L290 TraceCheckUtils]: 79: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,096 INFO L284 TraceCheckUtils]: 80: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8071#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,096 INFO L290 TraceCheckUtils]: 81: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume -2147483648 <= ldv_pm_platform_instance_4_#t~ret1545#1 && ldv_pm_platform_instance_4_#t~ret1545#1 <= 2147483647;ldv_pm_platform_instance_4_~tmp___1~31#1 := ldv_pm_platform_instance_4_#t~ret1545#1;havoc ldv_pm_platform_instance_4_#t~ret1545#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,096 INFO L290 TraceCheckUtils]: 82: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume 0 != ldv_pm_platform_instance_4_~tmp___1~31#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,097 INFO L272 TraceCheckUtils]: 83: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_pm_platform_instance_4_#t~ret1546#1.base, ldv_pm_platform_instance_4_#t~ret1546#1.offset := ldv_xmalloc(1432); {3057#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 23:12:37,097 INFO L290 TraceCheckUtils]: 84: Hoare triple {3057#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~127.base, ~tmp~127.offset;havoc ~tmp___0~64;call #t~malloc1675.base, #t~malloc1675.offset := #Ultimate.allocOnHeap(~size);~tmp~127.base, ~tmp~127.offset := #t~malloc1675.base, #t~malloc1675.offset;havoc #t~malloc1675.base, #t~malloc1675.offset;~res~3.base, ~res~3.offset := ~tmp~127.base, ~tmp~127.offset; {2968#true} is VALID [2022-02-20 23:12:37,097 INFO L272 TraceCheckUtils]: 85: Hoare triple {2968#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:37,097 INFO L290 TraceCheckUtils]: 86: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:37,098 INFO L290 TraceCheckUtils]: 87: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:37,098 INFO L290 TraceCheckUtils]: 88: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,098 INFO L284 TraceCheckUtils]: 89: Hoare quadruple {2968#true} {2968#true} #7545#return; {2968#true} is VALID [2022-02-20 23:12:37,098 INFO L272 TraceCheckUtils]: 90: Hoare triple {2968#true} call #t~ret1676 := ldv_is_err(~res~3.base, ~res~3.offset); {2968#true} is VALID [2022-02-20 23:12:37,098 INFO L290 TraceCheckUtils]: 91: Hoare triple {2968#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {2968#true} is VALID [2022-02-20 23:12:37,098 INFO L290 TraceCheckUtils]: 92: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,099 INFO L284 TraceCheckUtils]: 93: Hoare quadruple {2968#true} {2968#true} #7547#return; {2968#true} is VALID [2022-02-20 23:12:37,099 INFO L290 TraceCheckUtils]: 94: Hoare triple {2968#true} assume -9223372036854775808 <= #t~ret1676 && #t~ret1676 <= 9223372036854775807;~tmp___0~64 := #t~ret1676;havoc #t~ret1676; {2968#true} is VALID [2022-02-20 23:12:37,099 INFO L272 TraceCheckUtils]: 95: Hoare triple {2968#true} call ldv_assume((if 0 == ~tmp___0~64 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:37,099 INFO L290 TraceCheckUtils]: 96: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:37,099 INFO L290 TraceCheckUtils]: 97: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:37,099 INFO L290 TraceCheckUtils]: 98: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,100 INFO L284 TraceCheckUtils]: 99: Hoare quadruple {2968#true} {2968#true} #7549#return; {2968#true} is VALID [2022-02-20 23:12:37,100 INFO L290 TraceCheckUtils]: 100: Hoare triple {2968#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {2968#true} is VALID [2022-02-20 23:12:37,100 INFO L290 TraceCheckUtils]: 101: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,101 INFO L284 TraceCheckUtils]: 102: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8073#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,101 INFO L290 TraceCheckUtils]: 103: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_pm_platform_instance_4_~tmp~95#1.base, ldv_pm_platform_instance_4_~tmp~95#1.offset := ldv_pm_platform_instance_4_#t~ret1546#1.base, ldv_pm_platform_instance_4_#t~ret1546#1.offset;havoc ldv_pm_platform_instance_4_#t~ret1546#1.base, ldv_pm_platform_instance_4_#t~ret1546#1.offset;ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.offset := ldv_pm_platform_instance_4_~tmp~95#1.base, ldv_pm_platform_instance_4_~tmp~95#1.offset; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,101 INFO L272 TraceCheckUtils]: 104: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_pre_probe(); {2968#true} is VALID [2022-02-20 23:12:37,101 INFO L290 TraceCheckUtils]: 105: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,102 INFO L284 TraceCheckUtils]: 106: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #8075#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,102 INFO L290 TraceCheckUtils]: 107: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_pm_platform_instance_4_#t~mem1547#1.base, ldv_pm_platform_instance_4_#t~mem1547#1.offset := read~$Pointer$(ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.base, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.offset, 8); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,102 INFO L290 TraceCheckUtils]: 108: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume 0 != (ldv_pm_platform_instance_4_#t~mem1547#1.base + ldv_pm_platform_instance_4_#t~mem1547#1.offset) % 18446744073709551616;havoc ldv_pm_platform_instance_4_#t~mem1547#1.base, ldv_pm_platform_instance_4_#t~mem1547#1.offset;call ldv_pm_platform_instance_4_#t~mem1548#1.base, ldv_pm_platform_instance_4_#t~mem1548#1.offset := read~$Pointer$(ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.base, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.offset, 8);assume { :begin_inline_ldv_platform_instance_probe_4_14 } true;ldv_platform_instance_probe_4_14_#in~arg0#1.base, ldv_platform_instance_probe_4_14_#in~arg0#1.offset, ldv_platform_instance_probe_4_14_#in~arg1#1.base, ldv_platform_instance_probe_4_14_#in~arg1#1.offset := ldv_pm_platform_instance_4_#t~mem1548#1.base, ldv_pm_platform_instance_4_#t~mem1548#1.offset, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.offset;havoc ldv_platform_instance_probe_4_14_#res#1;havoc ldv_platform_instance_probe_4_14_#t~ret1503#1, ldv_platform_instance_probe_4_14_~arg0#1.base, ldv_platform_instance_probe_4_14_~arg0#1.offset, ldv_platform_instance_probe_4_14_~arg1#1.base, ldv_platform_instance_probe_4_14_~arg1#1.offset, ldv_platform_instance_probe_4_14_~tmp~94#1;ldv_platform_instance_probe_4_14_~arg0#1.base, ldv_platform_instance_probe_4_14_~arg0#1.offset := ldv_platform_instance_probe_4_14_#in~arg0#1.base, ldv_platform_instance_probe_4_14_#in~arg0#1.offset;ldv_platform_instance_probe_4_14_~arg1#1.base, ldv_platform_instance_probe_4_14_~arg1#1.offset := ldv_platform_instance_probe_4_14_#in~arg1#1.base, ldv_platform_instance_probe_4_14_#in~arg1#1.offset;havoc ldv_platform_instance_probe_4_14_~tmp~94#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,103 INFO L272 TraceCheckUtils]: 109: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_platform_instance_probe_4_14_#t~ret1503#1 := ##fun~$Pointer$~TO~int(ldv_platform_instance_probe_4_14_~arg1#1.base, ldv_platform_instance_probe_4_14_~arg1#1.offset, ldv_platform_instance_probe_4_14_~arg0#1.base, ldv_platform_instance_probe_4_14_~arg0#1.offset); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,103 INFO L290 TraceCheckUtils]: 110: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #~1543.base, #~1543.offset := #in~1543.base, #in~1543.offset; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,104 INFO L290 TraceCheckUtils]: 111: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(#in~#fp.base == #funAddr~vortex_nway_reset.base && #in~#fp.offset == #funAddr~vortex_nway_reset.offset); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,104 INFO L290 TraceCheckUtils]: 112: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(#in~#fp.base == #funAddr~eth_validate_addr.base && #in~#fp.offset == #funAddr~eth_validate_addr.offset); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,105 INFO L290 TraceCheckUtils]: 113: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(#in~#fp.base == #funAddr~vortex_close.base && #in~#fp.offset == #funAddr~vortex_close.offset); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,105 INFO L290 TraceCheckUtils]: 114: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume #in~#fp.base == #funAddr~vortex_open.base && #in~#fp.offset == #funAddr~vortex_open.offset; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,105 INFO L272 TraceCheckUtils]: 115: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call #t~ret1805 := vortex_open(#~1543.base, #~1543.offset); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,106 INFO L290 TraceCheckUtils]: 116: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~vp~6#1.base, ~vp~6#1.offset;havoc ~tmp~45#1.base, ~tmp~45#1.offset;havoc ~i~3#1;havoc ~retval~1#1;call ~#descriptor~2#1.base, ~#descriptor~2#1.offset := #Ultimate.allocOnStack(40);havoc ~tmp___0~19#1;havoc ~skb~1#1.base, ~skb~1#1.offset;havoc ~__mptr~4#1.base, ~__mptr~4#1.offset;havoc ~tmp___1~12#1.base, ~tmp___1~12#1.offset;havoc ~tmp___2~5#1.base, ~tmp___2~5#1.offset;havoc ~tmp___3~4#1;havoc ~j~0#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,106 INFO L272 TraceCheckUtils]: 117: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call #t~ret654#1.base, #t~ret654#1.offset := netdev_priv(~dev#1.base, ~dev#1.offset); {2968#true} is VALID [2022-02-20 23:12:37,106 INFO L290 TraceCheckUtils]: 118: Hoare triple {2968#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {2968#true} is VALID [2022-02-20 23:12:37,106 INFO L290 TraceCheckUtils]: 119: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,107 INFO L284 TraceCheckUtils]: 120: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7851#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,107 INFO L290 TraceCheckUtils]: 121: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ~tmp~45#1.base, ~tmp~45#1.offset := #t~ret654#1.base, #t~ret654#1.offset;havoc #t~ret654#1.base, #t~ret654#1.offset;~vp~6#1.base, ~vp~6#1.offset := ~tmp~45#1.base, ~tmp~45#1.offset;call #t~mem655#1 := read~int(~dev#1.base, 64 + ~dev#1.offset, 4);call #t~mem656#1 := read~int(~vp~6#1.base, 797 + ~vp~6#1.offset, 1); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,108 INFO L290 TraceCheckUtils]: 122: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume 0 != #t~mem656#1 % 256 % 4294967296;#t~ite657#1.base, #t~ite657#1.offset := #funAddr~boomerang_interrupt.base, #funAddr~boomerang_interrupt.offset; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,109 INFO L290 TraceCheckUtils]: 123: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume { :begin_inline_ldv_request_irq_102 } true;ldv_request_irq_102_#in~irq#1, ldv_request_irq_102_#in~handler#1.base, ldv_request_irq_102_#in~handler#1.offset, ldv_request_irq_102_#in~flags#1, ldv_request_irq_102_#in~name#1.base, ldv_request_irq_102_#in~name#1.offset, ldv_request_irq_102_#in~dev#1.base, ldv_request_irq_102_#in~dev#1.offset := #t~mem655#1, #t~ite657#1.base, #t~ite657#1.offset, 128, ~dev#1.base, ~dev#1.offset, ~dev#1.base, ~dev#1.offset;havoc ldv_request_irq_102_#res#1;havoc ldv_request_irq_102_#t~ret1626#1, ldv_request_irq_102_#t~ret1627#1, ldv_request_irq_102_~irq#1, ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset, ldv_request_irq_102_~flags#1, ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset, ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset, ldv_request_irq_102_~ldv_func_res~2#1, ldv_request_irq_102_~tmp~107#1, ldv_request_irq_102_~tmp___0~53#1;ldv_request_irq_102_~irq#1 := ldv_request_irq_102_#in~irq#1;ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset := ldv_request_irq_102_#in~handler#1.base, ldv_request_irq_102_#in~handler#1.offset;ldv_request_irq_102_~flags#1 := ldv_request_irq_102_#in~flags#1;ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset := ldv_request_irq_102_#in~name#1.base, ldv_request_irq_102_#in~name#1.offset;ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset := ldv_request_irq_102_#in~dev#1.base, ldv_request_irq_102_#in~dev#1.offset;havoc ldv_request_irq_102_~ldv_func_res~2#1;havoc ldv_request_irq_102_~tmp~107#1;havoc ldv_request_irq_102_~tmp___0~53#1;assume { :begin_inline_request_irq } true;request_irq_#in~irq#1, request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset, request_irq_#in~flags#1, request_irq_#in~name#1.base, request_irq_#in~name#1.offset, request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset := ldv_request_irq_102_~irq#1, ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset, ldv_request_irq_102_~flags#1, ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset, ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset;havoc request_irq_#res#1;havoc request_irq_#t~ret289#1, request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset, request_irq_~tmp~32#1;request_irq_~irq#1 := request_irq_#in~irq#1;request_irq_~handler#1.base, request_irq_~handler#1.offset := request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset;request_irq_~flags#1 := request_irq_#in~flags#1;request_irq_~name#1.base, request_irq_~name#1.offset := request_irq_#in~name#1.base, request_irq_#in~name#1.offset;request_irq_~dev#1.base, request_irq_~dev#1.offset := request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset;havoc request_irq_~tmp~32#1;assume { :begin_inline_request_threaded_irq } true;request_threaded_irq_#in~arg0#1, request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset, request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset, request_threaded_irq_#in~arg3#1, request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset, request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset := request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, 0, 0, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset;havoc request_threaded_irq_#res#1;havoc request_threaded_irq_#t~nondet1792#1, request_threaded_irq_~arg0#1, request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset, request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset, request_threaded_irq_~arg3#1, request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset, request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset;request_threaded_irq_~arg0#1 := request_threaded_irq_#in~arg0#1;request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset := request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset;request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset := request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset;request_threaded_irq_~arg3#1 := request_threaded_irq_#in~arg3#1;request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset := request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset;request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset := request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset;assume -2147483648 <= request_threaded_irq_#t~nondet1792#1 && request_threaded_irq_#t~nondet1792#1 <= 2147483647;request_threaded_irq_#res#1 := request_threaded_irq_#t~nondet1792#1;havoc request_threaded_irq_#t~nondet1792#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,110 INFO L290 TraceCheckUtils]: 124: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} request_irq_#t~ret289#1 := request_threaded_irq_#res#1;assume { :end_inline_request_threaded_irq } true;assume -2147483648 <= request_irq_#t~ret289#1 && request_irq_#t~ret289#1 <= 2147483647;request_irq_~tmp~32#1 := request_irq_#t~ret289#1;havoc request_irq_#t~ret289#1;request_irq_#res#1 := request_irq_~tmp~32#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,110 INFO L290 TraceCheckUtils]: 125: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_request_irq_102_#t~ret1626#1 := request_irq_#res#1;assume { :end_inline_request_irq } true;assume -2147483648 <= ldv_request_irq_102_#t~ret1626#1 && ldv_request_irq_102_#t~ret1626#1 <= 2147483647;ldv_request_irq_102_~tmp~107#1 := ldv_request_irq_102_#t~ret1626#1;havoc ldv_request_irq_102_#t~ret1626#1;ldv_request_irq_102_~ldv_func_res~2#1 := ldv_request_irq_102_~tmp~107#1;assume { :begin_inline_ldv_request_irq } true;ldv_request_irq_#in~arg0#1, ldv_request_irq_#in~arg1#1, ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset, ldv_request_irq_#in~arg3#1, ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset, ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset := ldv_request_irq_102_~ldv_func_res~2#1, ldv_request_irq_102_~irq#1, ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset, ldv_request_irq_102_~flags#1, ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset, ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset;havoc ldv_request_irq_#res#1;havoc ldv_request_irq_#t~ret1608#1, ldv_request_irq_~arg0#1, ldv_request_irq_~arg1#1, ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset, ldv_request_irq_~arg3#1, ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset, ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset, ldv_request_irq_~ldv_12_callback_handler~0#1.base, ldv_request_irq_~ldv_12_callback_handler~0#1.offset, ldv_request_irq_~ldv_12_data_data~0#1.base, ldv_request_irq_~ldv_12_data_data~0#1.offset, ldv_request_irq_~ldv_12_line_line~0#1, ldv_request_irq_~ldv_12_thread_thread~0#1.base, ldv_request_irq_~ldv_12_thread_thread~0#1.offset, ldv_request_irq_~tmp~99#1;ldv_request_irq_~arg0#1 := ldv_request_irq_#in~arg0#1;ldv_request_irq_~arg1#1 := ldv_request_irq_#in~arg1#1;ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset := ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset;ldv_request_irq_~arg3#1 := ldv_request_irq_#in~arg3#1;ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset := ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset;ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset := ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset;havoc ldv_request_irq_~ldv_12_callback_handler~0#1.base, ldv_request_irq_~ldv_12_callback_handler~0#1.offset;havoc ldv_request_irq_~ldv_12_data_data~0#1.base, ldv_request_irq_~ldv_12_data_data~0#1.offset;havoc ldv_request_irq_~ldv_12_line_line~0#1;havoc ldv_request_irq_~ldv_12_thread_thread~0#1.base, ldv_request_irq_~ldv_12_thread_thread~0#1.offset;havoc ldv_request_irq_~tmp~99#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,110 INFO L272 TraceCheckUtils]: 126: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_request_irq_#t~ret1608#1 := ldv_undef_int(); {2968#true} is VALID [2022-02-20 23:12:37,110 INFO L290 TraceCheckUtils]: 127: Hoare triple {2968#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {2968#true} is VALID [2022-02-20 23:12:37,111 INFO L290 TraceCheckUtils]: 128: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,111 INFO L284 TraceCheckUtils]: 129: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7853#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,112 INFO L290 TraceCheckUtils]: 130: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume -2147483648 <= ldv_request_irq_#t~ret1608#1 && ldv_request_irq_#t~ret1608#1 <= 2147483647;ldv_request_irq_~tmp~99#1 := ldv_request_irq_#t~ret1608#1;havoc ldv_request_irq_#t~ret1608#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,112 INFO L290 TraceCheckUtils]: 131: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(0 != ldv_request_irq_~tmp~99#1); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,112 INFO L272 TraceCheckUtils]: 132: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_assume((if 0 != ldv_request_irq_~arg0#1 then 1 else 0)); {2968#true} is VALID [2022-02-20 23:12:37,112 INFO L290 TraceCheckUtils]: 133: Hoare triple {2968#true} ~expression := #in~expression; {2968#true} is VALID [2022-02-20 23:12:37,113 INFO L290 TraceCheckUtils]: 134: Hoare triple {2968#true} assume !(0 == ~expression); {2968#true} is VALID [2022-02-20 23:12:37,113 INFO L290 TraceCheckUtils]: 135: Hoare triple {2968#true} assume true; {2968#true} is VALID [2022-02-20 23:12:37,114 INFO L284 TraceCheckUtils]: 136: Hoare quadruple {2968#true} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7875#return; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,114 INFO L290 TraceCheckUtils]: 137: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_request_irq_#res#1 := ldv_request_irq_~arg0#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,118 INFO L290 TraceCheckUtils]: 138: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_request_irq_102_#t~ret1627#1 := ldv_request_irq_#res#1;assume { :end_inline_ldv_request_irq } true;assume -2147483648 <= ldv_request_irq_102_#t~ret1627#1 && ldv_request_irq_102_#t~ret1627#1 <= 2147483647;ldv_request_irq_102_~tmp___0~53#1 := ldv_request_irq_102_#t~ret1627#1;havoc ldv_request_irq_102_#t~ret1627#1;ldv_request_irq_102_#res#1 := ldv_request_irq_102_~tmp___0~53#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,119 INFO L290 TraceCheckUtils]: 139: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #t~ret658#1 := ldv_request_irq_102_#res#1;assume { :end_inline_ldv_request_irq_102 } true;assume -2147483648 <= #t~ret658#1 && #t~ret658#1 <= 2147483647;~retval~1#1 := #t~ret658#1;havoc #t~mem655#1;havoc #t~mem656#1;havoc #t~ite657#1.base, #t~ite657#1.offset;havoc #t~ret658#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,119 INFO L290 TraceCheckUtils]: 140: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(0 != ~retval~1#1);call #t~mem661#1 := read~int(~vp~6#1.base, 797 + ~vp~6#1.offset, 1); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,120 INFO L290 TraceCheckUtils]: 141: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume 0 != #t~mem661#1 % 256 % 4294967296;havoc #t~mem661#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,120 INFO L290 TraceCheckUtils]: 142: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(~debug~0 > 2); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,120 INFO L290 TraceCheckUtils]: 143: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ~i~3#1 := 0; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,121 INFO L290 TraceCheckUtils]: 144: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume ~i~3#1 <= 31; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,121 INFO L290 TraceCheckUtils]: 145: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call #t~mem665#1.base, #t~mem665#1.offset := read~$Pointer$(~vp~6#1.base, ~vp~6#1.offset, 8);call #t~mem666#1 := read~int(~vp~6#1.base, 16 + ~vp~6#1.offset, 8);call write~int(#t~mem666#1 + 16 * (1 + ~i~3#1), #t~mem665#1.base, #t~mem665#1.offset + 16 * (if ~i~3#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then ~i~3#1 % 18446744073709551616 % 18446744073709551616 else ~i~3#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616), 4);havoc #t~mem665#1.base, #t~mem665#1.offset;havoc #t~mem666#1;call #t~mem667#1.base, #t~mem667#1.offset := read~$Pointer$(~vp~6#1.base, ~vp~6#1.offset, 8);call write~int(0, #t~mem667#1.base, 4 + (#t~mem667#1.offset + 16 * (if ~i~3#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then ~i~3#1 % 18446744073709551616 % 18446744073709551616 else ~i~3#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616)), 4);havoc #t~mem667#1.base, #t~mem667#1.offset;call #t~mem668#1.base, #t~mem668#1.offset := read~$Pointer$(~vp~6#1.base, ~vp~6#1.offset, 8);call write~int(2147485184, #t~mem668#1.base, 12 + (#t~mem668#1.offset + 16 * (if ~i~3#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then ~i~3#1 % 18446744073709551616 % 18446744073709551616 else ~i~3#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616)), 4);havoc #t~mem668#1.base, #t~mem668#1.offset;assume { :begin_inline_ldv___netdev_alloc_skb_103 } true;ldv___netdev_alloc_skb_103_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_103_#in~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_103_#in~ldv_func_arg2#1, ldv___netdev_alloc_skb_103_#in~flags#1 := ~dev#1.base, ~dev#1.offset, 1536, 208;havoc ldv___netdev_alloc_skb_103_#res#1.base, ldv___netdev_alloc_skb_103_#res#1.offset;havoc ldv___netdev_alloc_skb_103_#t~ret1628#1.base, ldv___netdev_alloc_skb_103_#t~ret1628#1.offset, ldv___netdev_alloc_skb_103_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_103_~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_103_~ldv_func_arg2#1, ldv___netdev_alloc_skb_103_~flags#1, ldv___netdev_alloc_skb_103_~tmp~108#1.base, ldv___netdev_alloc_skb_103_~tmp~108#1.offset;ldv___netdev_alloc_skb_103_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_103_~ldv_func_arg1#1.offset := ldv___netdev_alloc_skb_103_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_103_#in~ldv_func_arg1#1.offset;ldv___netdev_alloc_skb_103_~ldv_func_arg2#1 := ldv___netdev_alloc_skb_103_#in~ldv_func_arg2#1;ldv___netdev_alloc_skb_103_~flags#1 := ldv___netdev_alloc_skb_103_#in~flags#1;havoc ldv___netdev_alloc_skb_103_~tmp~108#1.base, ldv___netdev_alloc_skb_103_~tmp~108#1.offset; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,122 INFO L272 TraceCheckUtils]: 146: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_check_alloc_flags(ldv___netdev_alloc_skb_103_~flags#1); {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,122 INFO L290 TraceCheckUtils]: 147: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ~flags#1 := #in~flags#1;havoc ~tmp~116#1; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,122 INFO L290 TraceCheckUtils]: 148: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume 32 != ~flags#1 % 4294967296 && 0 != ~flags#1 % 4294967296; {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 23:12:37,123 INFO L272 TraceCheckUtils]: 149: Hoare triple {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call #t~ret1643#1 := ldv_exclusive_spin_is_locked(); {2968#true} is VALID [2022-02-20 23:12:37,123 INFO L290 TraceCheckUtils]: 150: Hoare triple {2968#true} assume 2 == ~ldv_spin__xmit_lock_of_netdev_queue~0;#res := 1; {3080#(<= 2 ~ldv_spin__xmit_lock_of_netdev_queue~0)} is VALID [2022-02-20 23:12:37,123 INFO L290 TraceCheckUtils]: 151: Hoare triple {3080#(<= 2 ~ldv_spin__xmit_lock_of_netdev_queue~0)} assume true; {3080#(<= 2 ~ldv_spin__xmit_lock_of_netdev_queue~0)} is VALID [2022-02-20 23:12:37,124 INFO L284 TraceCheckUtils]: 152: Hoare quadruple {3080#(<= 2 ~ldv_spin__xmit_lock_of_netdev_queue~0)} {2970#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #7101#return; {2969#false} is VALID [2022-02-20 23:12:37,124 INFO L290 TraceCheckUtils]: 153: Hoare triple {2969#false} assume -2147483648 <= #t~ret1643#1 && #t~ret1643#1 <= 2147483647;~tmp~116#1 := #t~ret1643#1;havoc #t~ret1643#1;assume { :begin_inline_ldv_assert_linux_alloc_spinlock__wrong_flags } true;ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1 := (if 0 == ~tmp~116#1 then 1 else 0);havoc ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1;ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1 := ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1; {2969#false} is VALID [2022-02-20 23:12:37,124 INFO L290 TraceCheckUtils]: 154: Hoare triple {2969#false} assume 0 == ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1; {2969#false} is VALID [2022-02-20 23:12:37,125 INFO L290 TraceCheckUtils]: 155: Hoare triple {2969#false} assume !false; {2969#false} is VALID [2022-02-20 23:12:37,125 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2022-02-20 23:12:37,126 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 23:12:37,126 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239184062] [2022-02-20 23:12:37,126 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239184062] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 23:12:37,127 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 23:12:37,127 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-20 23:12:37,128 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517860797] [2022-02-20 23:12:37,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 23:12:37,132 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 15.2) internal successors, (76), 4 states have internal predecessors, (76), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) Word has length 156 [2022-02-20 23:12:37,134 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 23:12:37,136 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 15.2) internal successors, (76), 4 states have internal predecessors, (76), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) [2022-02-20 23:12:37,281 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 23:12:37,281 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-02-20 23:12:37,281 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 23:12:37,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-20 23:12:37,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-20 23:12:37,319 INFO L87 Difference]: Start difference. First operand has 2965 states, 2050 states have (on average 1.3682926829268294) internal successors, (2805), 2136 states have internal predecessors, (2805), 760 states have call successors, (760), 154 states have call predecessors, (760), 153 states have return successors, (753), 735 states have call predecessors, (753), 753 states have call successors, (753) Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 4 states have internal predecessors, (76), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) [2022-02-20 23:13:00,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 23:13:00,428 INFO L93 Difference]: Finished difference Result 5936 states and 8778 transitions. [2022-02-20 23:13:00,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-20 23:13:00,429 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 15.2) internal successors, (76), 4 states have internal predecessors, (76), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) Word has length 156 [2022-02-20 23:13:00,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 23:13:00,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 4 states have internal predecessors, (76), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) [2022-02-20 23:13:01,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 8778 transitions. [2022-02-20 23:13:01,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 4 states have internal predecessors, (76), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) [2022-02-20 23:13:01,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 8778 transitions. [2022-02-20 23:13:01,717 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 8778 transitions. [2022-02-20 23:13:07,866 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 8778 edges. 8778 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 23:13:08,399 INFO L225 Difference]: With dead ends: 5936 [2022-02-20 23:13:08,400 INFO L226 Difference]: Without dead ends: 2942 [2022-02-20 23:13:08,420 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 42 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-02-20 23:13:08,424 INFO L933 BasicCegarLoop]: 3998 mSDtfsCounter, 4048 mSDsluCounter, 4104 mSDsCounter, 0 mSdLazyCounter, 2971 mSolverCounterSat, 1454 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 4.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4506 SdHoareTripleChecker+Valid, 8102 SdHoareTripleChecker+Invalid, 4425 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 1454 IncrementalHoareTripleChecker+Valid, 2971 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 4.9s IncrementalHoareTripleChecker+Time [2022-02-20 23:13:08,424 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [4506 Valid, 8102 Invalid, 4425 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [1454 Valid, 2971 Invalid, 0 Unknown, 0 Unchecked, 4.9s Time] [2022-02-20 23:13:08,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2942 states. [2022-02-20 23:13:08,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2942 to 2907. [2022-02-20 23:13:08,596 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 23:13:08,605 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2942 states. Second operand has 2907 states, 2024 states have (on average 1.33300395256917) internal successors, (2698), 2104 states have internal predecessors, (2698), 730 states have call successors, (730), 152 states have call predecessors, (730), 152 states have return successors, (730), 712 states have call predecessors, (730), 730 states have call successors, (730) [2022-02-20 23:13:08,610 INFO L74 IsIncluded]: Start isIncluded. First operand 2942 states. Second operand has 2907 states, 2024 states have (on average 1.33300395256917) internal successors, (2698), 2104 states have internal predecessors, (2698), 730 states have call successors, (730), 152 states have call predecessors, (730), 152 states have return successors, (730), 712 states have call predecessors, (730), 730 states have call successors, (730) [2022-02-20 23:13:08,615 INFO L87 Difference]: Start difference. First operand 2942 states. Second operand has 2907 states, 2024 states have (on average 1.33300395256917) internal successors, (2698), 2104 states have internal predecessors, (2698), 730 states have call successors, (730), 152 states have call predecessors, (730), 152 states have return successors, (730), 712 states have call predecessors, (730), 730 states have call successors, (730) [2022-02-20 23:13:08,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 23:13:08,901 INFO L93 Difference]: Finished difference Result 2942 states and 4231 transitions. [2022-02-20 23:13:08,901 INFO L276 IsEmpty]: Start isEmpty. Operand 2942 states and 4231 transitions. [2022-02-20 23:13:08,915 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 23:13:08,915 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 23:13:08,922 INFO L74 IsIncluded]: Start isIncluded. First operand has 2907 states, 2024 states have (on average 1.33300395256917) internal successors, (2698), 2104 states have internal predecessors, (2698), 730 states have call successors, (730), 152 states have call predecessors, (730), 152 states have return successors, (730), 712 states have call predecessors, (730), 730 states have call successors, (730) Second operand 2942 states. [2022-02-20 23:13:08,927 INFO L87 Difference]: Start difference. First operand has 2907 states, 2024 states have (on average 1.33300395256917) internal successors, (2698), 2104 states have internal predecessors, (2698), 730 states have call successors, (730), 152 states have call predecessors, (730), 152 states have return successors, (730), 712 states have call predecessors, (730), 730 states have call successors, (730) Second operand 2942 states. [2022-02-20 23:13:09,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 23:13:09,203 INFO L93 Difference]: Finished difference Result 2942 states and 4231 transitions. [2022-02-20 23:13:09,203 INFO L276 IsEmpty]: Start isEmpty. Operand 2942 states and 4231 transitions. [2022-02-20 23:13:09,220 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 23:13:09,220 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 23:13:09,221 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 23:13:09,221 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 23:13:09,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2907 states, 2024 states have (on average 1.33300395256917) internal successors, (2698), 2104 states have internal predecessors, (2698), 730 states have call successors, (730), 152 states have call predecessors, (730), 152 states have return successors, (730), 712 states have call predecessors, (730), 730 states have call successors, (730) [2022-02-20 23:13:09,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2907 states to 2907 states and 4158 transitions. [2022-02-20 23:13:09,671 INFO L78 Accepts]: Start accepts. Automaton has 2907 states and 4158 transitions. Word has length 156 [2022-02-20 23:13:09,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 23:13:09,672 INFO L470 AbstractCegarLoop]: Abstraction has 2907 states and 4158 transitions. [2022-02-20 23:13:09,673 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 15.2) internal successors, (76), 4 states have internal predecessors, (76), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) [2022-02-20 23:13:09,673 INFO L276 IsEmpty]: Start isEmpty. Operand 2907 states and 4158 transitions. [2022-02-20 23:13:09,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 158 [2022-02-20 23:13:09,683 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 23:13:09,683 INFO L514 BasicCegarLoop]: trace histogram [8, 8, 8, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 23:13:09,684 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-02-20 23:13:09,684 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 23:13:09,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 23:13:09,684 INFO L85 PathProgramCache]: Analyzing trace with hash -617333662, now seen corresponding path program 1 times [2022-02-20 23:13:09,685 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 23:13:09,685 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387672438] [2022-02-20 23:13:09,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 23:13:09,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 23:13:09,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,066 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 23:13:10,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,081 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,081 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,082 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7987#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,082 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 10 [2022-02-20 23:13:10,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,088 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,088 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,088 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,089 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8049#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,089 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 27 [2022-02-20 23:13:10,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,097 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:13:10,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,102 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,102 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,102 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,102 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21501#true} {21501#true} #7811#return; {21501#true} is VALID [2022-02-20 23:13:10,102 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~val := #in~val; {21501#true} is VALID [2022-02-20 23:13:10,103 INFO L272 TraceCheckUtils]: 1: Hoare triple {21501#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,103 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,103 INFO L290 TraceCheckUtils]: 3: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,103 INFO L290 TraceCheckUtils]: 4: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,104 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {21501#true} {21501#true} #7811#return; {21501#true} is VALID [2022-02-20 23:13:10,104 INFO L290 TraceCheckUtils]: 6: Hoare triple {21501#true} #res := ~val; {21501#true} is VALID [2022-02-20 23:13:10,104 INFO L290 TraceCheckUtils]: 7: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,105 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8055#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,106 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 39 [2022-02-20 23:13:10,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,113 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,113 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,114 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8057#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,114 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 45 [2022-02-20 23:13:10,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,120 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,120 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,120 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,121 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8065#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,121 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 50 [2022-02-20 23:13:10,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,133 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,133 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,133 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8067#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,137 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 56 [2022-02-20 23:13:10,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,148 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:13:10,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,154 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,154 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,154 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,155 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21501#true} {21501#true} #7545#return; {21501#true} is VALID [2022-02-20 23:13:10,155 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 23:13:10,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,159 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {21501#true} is VALID [2022-02-20 23:13:10,160 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,160 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21501#true} {21501#true} #7547#return; {21501#true} is VALID [2022-02-20 23:13:10,160 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 23:13:10,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,164 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,164 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,164 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,164 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21501#true} {21501#true} #7549#return; {21501#true} is VALID [2022-02-20 23:13:10,164 INFO L290 TraceCheckUtils]: 0: Hoare triple {21591#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~127.base, ~tmp~127.offset;havoc ~tmp___0~64;call #t~malloc1675.base, #t~malloc1675.offset := #Ultimate.allocOnHeap(~size);~tmp~127.base, ~tmp~127.offset := #t~malloc1675.base, #t~malloc1675.offset;havoc #t~malloc1675.base, #t~malloc1675.offset;~res~3.base, ~res~3.offset := ~tmp~127.base, ~tmp~127.offset; {21501#true} is VALID [2022-02-20 23:13:10,165 INFO L272 TraceCheckUtils]: 1: Hoare triple {21501#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,165 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,165 INFO L290 TraceCheckUtils]: 3: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,165 INFO L290 TraceCheckUtils]: 4: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,165 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {21501#true} {21501#true} #7545#return; {21501#true} is VALID [2022-02-20 23:13:10,165 INFO L272 TraceCheckUtils]: 6: Hoare triple {21501#true} call #t~ret1676 := ldv_is_err(~res~3.base, ~res~3.offset); {21501#true} is VALID [2022-02-20 23:13:10,165 INFO L290 TraceCheckUtils]: 7: Hoare triple {21501#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {21501#true} is VALID [2022-02-20 23:13:10,166 INFO L290 TraceCheckUtils]: 8: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,166 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {21501#true} {21501#true} #7547#return; {21501#true} is VALID [2022-02-20 23:13:10,166 INFO L290 TraceCheckUtils]: 10: Hoare triple {21501#true} assume -9223372036854775808 <= #t~ret1676 && #t~ret1676 <= 9223372036854775807;~tmp___0~64 := #t~ret1676;havoc #t~ret1676; {21501#true} is VALID [2022-02-20 23:13:10,166 INFO L272 TraceCheckUtils]: 11: Hoare triple {21501#true} call ldv_assume((if 0 == ~tmp___0~64 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,166 INFO L290 TraceCheckUtils]: 12: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,166 INFO L290 TraceCheckUtils]: 13: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,166 INFO L290 TraceCheckUtils]: 14: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,167 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {21501#true} {21501#true} #7549#return; {21501#true} is VALID [2022-02-20 23:13:10,167 INFO L290 TraceCheckUtils]: 16: Hoare triple {21501#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {21501#true} is VALID [2022-02-20 23:13:10,167 INFO L290 TraceCheckUtils]: 17: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,167 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8069#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,168 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 77 [2022-02-20 23:13:10,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,176 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,176 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,177 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8071#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,177 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 83 [2022-02-20 23:13:10,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,187 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:13:10,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,191 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,191 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,191 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,191 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21501#true} {21501#true} #7545#return; {21501#true} is VALID [2022-02-20 23:13:10,191 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 23:13:10,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,196 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {21501#true} is VALID [2022-02-20 23:13:10,196 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,196 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21501#true} {21501#true} #7547#return; {21501#true} is VALID [2022-02-20 23:13:10,196 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 23:13:10,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,200 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,200 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,201 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,201 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21501#true} {21501#true} #7549#return; {21501#true} is VALID [2022-02-20 23:13:10,201 INFO L290 TraceCheckUtils]: 0: Hoare triple {21591#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~127.base, ~tmp~127.offset;havoc ~tmp___0~64;call #t~malloc1675.base, #t~malloc1675.offset := #Ultimate.allocOnHeap(~size);~tmp~127.base, ~tmp~127.offset := #t~malloc1675.base, #t~malloc1675.offset;havoc #t~malloc1675.base, #t~malloc1675.offset;~res~3.base, ~res~3.offset := ~tmp~127.base, ~tmp~127.offset; {21501#true} is VALID [2022-02-20 23:13:10,201 INFO L272 TraceCheckUtils]: 1: Hoare triple {21501#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,201 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,201 INFO L290 TraceCheckUtils]: 3: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,202 INFO L290 TraceCheckUtils]: 4: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,202 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {21501#true} {21501#true} #7545#return; {21501#true} is VALID [2022-02-20 23:13:10,202 INFO L272 TraceCheckUtils]: 6: Hoare triple {21501#true} call #t~ret1676 := ldv_is_err(~res~3.base, ~res~3.offset); {21501#true} is VALID [2022-02-20 23:13:10,202 INFO L290 TraceCheckUtils]: 7: Hoare triple {21501#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {21501#true} is VALID [2022-02-20 23:13:10,202 INFO L290 TraceCheckUtils]: 8: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,202 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {21501#true} {21501#true} #7547#return; {21501#true} is VALID [2022-02-20 23:13:10,202 INFO L290 TraceCheckUtils]: 10: Hoare triple {21501#true} assume -9223372036854775808 <= #t~ret1676 && #t~ret1676 <= 9223372036854775807;~tmp___0~64 := #t~ret1676;havoc #t~ret1676; {21501#true} is VALID [2022-02-20 23:13:10,203 INFO L272 TraceCheckUtils]: 11: Hoare triple {21501#true} call ldv_assume((if 0 == ~tmp___0~64 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,203 INFO L290 TraceCheckUtils]: 12: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,203 INFO L290 TraceCheckUtils]: 13: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,203 INFO L290 TraceCheckUtils]: 14: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,203 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {21501#true} {21501#true} #7549#return; {21501#true} is VALID [2022-02-20 23:13:10,203 INFO L290 TraceCheckUtils]: 16: Hoare triple {21501#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {21501#true} is VALID [2022-02-20 23:13:10,203 INFO L290 TraceCheckUtils]: 17: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,204 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8073#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,204 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 104 [2022-02-20 23:13:10,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,210 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,210 INFO L284 TraceCheckUtils]: 1: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8075#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,210 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 117 [2022-02-20 23:13:10,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,218 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21501#true} is VALID [2022-02-20 23:13:10,219 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,219 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7851#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,219 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 126 [2022-02-20 23:13:10,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,225 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,225 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,225 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7853#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,226 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 132 [2022-02-20 23:13:10,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,230 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,231 INFO L290 TraceCheckUtils]: 1: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,231 INFO L290 TraceCheckUtils]: 2: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,231 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7875#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,231 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 149 [2022-02-20 23:13:10,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:13:10,281 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} assume !(2 == ~ldv_spin__xmit_lock_of_netdev_queue~0); {21614#(or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)))} is VALID [2022-02-20 23:13:10,282 INFO L290 TraceCheckUtils]: 1: Hoare triple {21614#(or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)))} assume 2 == ~ldv_spin_addr_list_lock_of_net_device~0;#res := 1; {21615#(and (or (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)) (<= 2 ~ldv_spin_addr_list_lock_of_net_device~0)) (or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (and (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)) (<= ~ldv_spin_addr_list_lock_of_net_device~0 2))))} is VALID [2022-02-20 23:13:10,282 INFO L290 TraceCheckUtils]: 2: Hoare triple {21615#(and (or (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)) (<= 2 ~ldv_spin_addr_list_lock_of_net_device~0)) (or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (and (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)) (<= ~ldv_spin_addr_list_lock_of_net_device~0 2))))} assume true; {21615#(and (or (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)) (<= 2 ~ldv_spin_addr_list_lock_of_net_device~0)) (or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (and (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)) (<= ~ldv_spin_addr_list_lock_of_net_device~0 2))))} is VALID [2022-02-20 23:13:10,283 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21615#(and (or (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)) (<= 2 ~ldv_spin_addr_list_lock_of_net_device~0)) (or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (and (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)) (<= ~ldv_spin_addr_list_lock_of_net_device~0 2))))} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7101#return; {21502#false} is VALID [2022-02-20 23:13:10,327 INFO L290 TraceCheckUtils]: 0: Hoare triple {21501#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(190, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(20, 4);call #Ultimate.allocInit(31, 5);call #Ultimate.allocInit(29, 6);call #Ultimate.allocInit(23, 7);call #Ultimate.allocInit(23, 8);call #Ultimate.allocInit(25, 9);call #Ultimate.allocInit(24, 10);call #Ultimate.allocInit(29, 11);call #Ultimate.allocInit(25, 12);call #Ultimate.allocInit(27, 13);call #Ultimate.allocInit(25, 14);call #Ultimate.allocInit(28, 15);call #Ultimate.allocInit(26, 16);call #Ultimate.allocInit(26, 17);call #Ultimate.allocInit(32, 18);call #Ultimate.allocInit(25, 19);call #Ultimate.allocInit(26, 20);call #Ultimate.allocInit(28, 21);call #Ultimate.allocInit(15, 22);call #Ultimate.allocInit(37, 23);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(16, 25);call #Ultimate.allocInit(23, 26);call #Ultimate.allocInit(23, 27);call #Ultimate.allocInit(21, 28);call #Ultimate.allocInit(24, 29);call #Ultimate.allocInit(38, 30);call #Ultimate.allocInit(24, 31);call #Ultimate.allocInit(27, 32);call #Ultimate.allocInit(27, 33);call #Ultimate.allocInit(25, 34);call #Ultimate.allocInit(36, 35);call #Ultimate.allocInit(36, 36);call #Ultimate.allocInit(22, 37);call #Ultimate.allocInit(14, 38);call #Ultimate.allocInit(24, 39);call #Ultimate.allocInit(24, 40);call #Ultimate.allocInit(10, 41);call #Ultimate.allocInit(23, 42);call #Ultimate.allocInit(8, 43);call #Ultimate.allocInit(10, 44);call #Ultimate.allocInit(10, 45);call #Ultimate.allocInit(8, 46);call #Ultimate.allocInit(10, 47);call #Ultimate.allocInit(10, 48);call #Ultimate.allocInit(4, 49);call write~init~int(77, 49, 0, 1);call write~init~int(73, 49, 1, 1);call write~init~int(73, 49, 2, 1);call write~init~int(0, 49, 3, 1);call #Ultimate.allocInit(10, 50);call #Ultimate.allocInit(14, 51);call #Ultimate.allocInit(13, 52);call #Ultimate.allocInit(8, 53);call #Ultimate.allocInit(6, 54);call write~init~int(51, 54, 0, 1);call write~init~int(99, 54, 1, 1);call write~init~int(53, 54, 2, 1);call write~init~int(57, 54, 3, 1);call write~init~int(120, 54, 4, 1);call write~init~int(0, 54, 5, 1);call #Ultimate.allocInit(6, 55);call write~init~int(51, 55, 0, 1);call write~init~int(99, 55, 1, 1);call write~init~int(53, 55, 2, 1);call write~init~int(57, 55, 3, 1);call write~init~int(120, 55, 4, 1);call write~init~int(0, 55, 5, 1);call #Ultimate.allocInit(4, 56);call write~init~int(14, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(0, 56, 3, 1);call #Ultimate.allocInit(42, 57);call #Ultimate.allocInit(24, 58);call #Ultimate.allocInit(4, 59);call write~init~int(80, 59, 0, 1);call write~init~int(67, 59, 1, 1);call write~init~int(73, 59, 2, 1);call write~init~int(0, 59, 3, 1);call #Ultimate.allocInit(5, 60);call write~init~int(69, 60, 0, 1);call write~init~int(73, 60, 1, 1);call write~init~int(83, 60, 2, 1);call write~init~int(65, 60, 3, 1);call write~init~int(0, 60, 4, 1);call #Ultimate.allocInit(74, 61);call #Ultimate.allocInit(20, 62);call #Ultimate.allocInit(24, 63);call #Ultimate.allocInit(27, 64);call #Ultimate.allocInit(31, 65);call #Ultimate.allocInit(5, 66);call write~init~int(32, 66, 0, 1);call write~init~int(37, 66, 1, 1);call write~init~int(112, 66, 2, 1);call write~init~int(77, 66, 3, 1);call write~init~int(0, 66, 4, 1);call #Ultimate.allocInit(37, 67);call #Ultimate.allocInit(10, 68);call #Ultimate.allocInit(48, 69);call #Ultimate.allocInit(58, 70);call #Ultimate.allocInit(45, 71);call #Ultimate.allocInit(22, 72);call #Ultimate.allocInit(4, 73);call write~init~int(53, 73, 0, 1);call write~init~int(58, 73, 1, 1);call write~init~int(51, 73, 2, 1);call write~init~int(0, 73, 3, 1);call #Ultimate.allocInit(4, 74);call write~init~int(51, 74, 0, 1);call write~init~int(58, 74, 1, 1);call write~init~int(49, 74, 2, 1);call write~init~int(0, 74, 3, 1);call #Ultimate.allocInit(4, 75);call write~init~int(49, 75, 0, 1);call write~init~int(58, 75, 1, 1);call write~init~int(49, 75, 2, 1);call write~init~int(0, 75, 3, 1);call #Ultimate.allocInit(4, 76);call write~init~int(51, 76, 0, 1);call write~init~int(58, 76, 1, 1);call write~init~int(53, 76, 2, 1);call write~init~int(0, 76, 3, 1);call #Ultimate.allocInit(6, 77);call write~init~int(51, 77, 0, 1);call write~init~int(99, 77, 1, 1);call write~init~int(53, 77, 2, 1);call write~init~int(57, 77, 3, 1);call write~init~int(120, 77, 4, 1);call write~init~int(0, 77, 5, 1);call #Ultimate.allocInit(14, 78);call #Ultimate.allocInit(34, 79);call #Ultimate.allocInit(56, 80);call #Ultimate.allocInit(56, 81);call #Ultimate.allocInit(52, 82);call #Ultimate.allocInit(5, 83);call write~init~int(119, 83, 0, 1);call write~init~int(111, 83, 1, 1);call write~init~int(114, 83, 2, 1);call write~init~int(100, 83, 3, 1);call write~init~int(0, 83, 4, 1);call #Ultimate.allocInit(5, 84);call write~init~int(98, 84, 0, 1);call write~init~int(121, 84, 1, 1);call write~init~int(116, 84, 2, 1);call write~init~int(101, 84, 3, 1);call write~init~int(0, 84, 4, 1);call #Ultimate.allocInit(12, 85);call #Ultimate.allocInit(1, 86);call write~init~int(0, 86, 0, 1);call #Ultimate.allocInit(22, 87);call #Ultimate.allocInit(51, 88);call #Ultimate.allocInit(53, 89);call #Ultimate.allocInit(45, 90);call #Ultimate.allocInit(51, 91);call #Ultimate.allocInit(6, 92);call write~init~int(101, 92, 0, 1);call write~init~int(97, 92, 1, 1);call write~init~int(114, 92, 2, 1);call write~init~int(108, 92, 3, 1);call write~init~int(121, 92, 4, 1);call write~init~int(0, 92, 5, 1);call #Ultimate.allocInit(12, 93);call #Ultimate.allocInit(52, 94);call #Ultimate.allocInit(3, 95);call write~init~int(101, 95, 0, 1);call write~init~int(110, 95, 1, 1);call write~init~int(0, 95, 2, 1);call #Ultimate.allocInit(4, 96);call write~init~int(100, 96, 0, 1);call write~init~int(105, 96, 1, 1);call write~init~int(115, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(3, 97);call write~init~int(101, 97, 0, 1);call write~init~int(110, 97, 1, 1);call write~init~int(0, 97, 2, 1);call #Ultimate.allocInit(4, 98);call write~init~int(100, 98, 0, 1);call write~init~int(105, 98, 1, 1);call write~init~int(115, 98, 2, 1);call write~init~int(0, 98, 3, 1);call #Ultimate.allocInit(41, 99);call #Ultimate.allocInit(35, 100);call #Ultimate.allocInit(51, 101);call #Ultimate.allocInit(26, 102);call #Ultimate.allocInit(5, 103);call write~init~int(102, 103, 0, 1);call write~init~int(117, 103, 1, 1);call write~init~int(108, 103, 2, 1);call write~init~int(108, 103, 3, 1);call write~init~int(0, 103, 4, 1);call #Ultimate.allocInit(5, 104);call write~init~int(104, 104, 0, 1);call write~init~int(97, 104, 1, 1);call write~init~int(108, 104, 2, 1);call write~init~int(102, 104, 3, 1);call write~init~int(0, 104, 4, 1);call #Ultimate.allocInit(30, 105);call #Ultimate.allocInit(45, 106);call #Ultimate.allocInit(38, 107);call #Ultimate.allocInit(37, 108);call #Ultimate.allocInit(29, 109);call #Ultimate.allocInit(13, 110);call #Ultimate.allocInit(20, 111);call #Ultimate.allocInit(6, 112);call write~init~int(51, 112, 0, 1);call write~init~int(99, 112, 1, 1);call write~init~int(53, 112, 2, 1);call write~init~int(57, 112, 3, 1);call write~init~int(120, 112, 4, 1);call write~init~int(0, 112, 5, 1);call #Ultimate.allocInit(10, 113);call #Ultimate.allocInit(34, 114);call #Ultimate.allocInit(28, 115);call #Ultimate.allocInit(28, 116);call #Ultimate.allocInit(6, 117);call write~init~int(51, 117, 0, 1);call write~init~int(99, 117, 1, 1);call write~init~int(53, 117, 2, 1);call write~init~int(57, 117, 3, 1);call write~init~int(120, 117, 4, 1);call write~init~int(0, 117, 5, 1);call #Ultimate.allocInit(10, 118);call #Ultimate.allocInit(34, 119);call #Ultimate.allocInit(45, 120);call #Ultimate.allocInit(45, 121);call #Ultimate.allocInit(6, 122);call write~init~int(51, 122, 0, 1);call write~init~int(99, 122, 1, 1);call write~init~int(53, 122, 2, 1);call write~init~int(57, 122, 3, 1);call write~init~int(120, 122, 4, 1);call write~init~int(0, 122, 5, 1);call #Ultimate.allocInit(10, 123);call #Ultimate.allocInit(34, 124);call #Ultimate.allocInit(44, 125);call #Ultimate.allocInit(44, 126);call #Ultimate.allocInit(31, 127);call #Ultimate.allocInit(6, 128);call write~init~int(51, 128, 0, 1);call write~init~int(99, 128, 1, 1);call write~init~int(53, 128, 2, 1);call write~init~int(57, 128, 3, 1);call write~init~int(120, 128, 4, 1);call write~init~int(0, 128, 5, 1);call #Ultimate.allocInit(12, 129);call #Ultimate.allocInit(34, 130);call #Ultimate.allocInit(30, 131);call #Ultimate.allocInit(30, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(40, 134);call #Ultimate.allocInit(6, 135);call write~init~int(51, 135, 0, 1);call write~init~int(99, 135, 1, 1);call write~init~int(53, 135, 2, 1);call write~init~int(57, 135, 3, 1);call write~init~int(120, 135, 4, 1);call write~init~int(0, 135, 5, 1);call #Ultimate.allocInit(13, 136);call #Ultimate.allocInit(34, 137);call #Ultimate.allocInit(46, 138);call #Ultimate.allocInit(46, 139);call #Ultimate.allocInit(6, 140);call write~init~int(51, 140, 0, 1);call write~init~int(99, 140, 1, 1);call write~init~int(53, 140, 2, 1);call write~init~int(57, 140, 3, 1);call write~init~int(120, 140, 4, 1);call write~init~int(0, 140, 5, 1);call #Ultimate.allocInit(13, 141);call #Ultimate.allocInit(34, 142);call #Ultimate.allocInit(24, 143);call #Ultimate.allocInit(24, 144);call #Ultimate.allocInit(6, 145);call write~init~int(51, 145, 0, 1);call write~init~int(99, 145, 1, 1);call write~init~int(53, 145, 2, 1);call write~init~int(57, 145, 3, 1);call write~init~int(120, 145, 4, 1);call write~init~int(0, 145, 5, 1);call #Ultimate.allocInit(13, 146);call #Ultimate.allocInit(34, 147);call #Ultimate.allocInit(33, 148);call #Ultimate.allocInit(33, 149);call #Ultimate.allocInit(6, 150);call write~init~int(51, 150, 0, 1);call write~init~int(99, 150, 1, 1);call write~init~int(53, 150, 2, 1);call write~init~int(57, 150, 3, 1);call write~init~int(120, 150, 4, 1);call write~init~int(0, 150, 5, 1);call #Ultimate.allocInit(13, 151);call #Ultimate.allocInit(34, 152);call #Ultimate.allocInit(36, 153);call #Ultimate.allocInit(36, 154);call #Ultimate.allocInit(6, 155);call write~init~int(51, 155, 0, 1);call write~init~int(99, 155, 1, 1);call write~init~int(53, 155, 2, 1);call write~init~int(57, 155, 3, 1);call write~init~int(120, 155, 4, 1);call write~init~int(0, 155, 5, 1);call #Ultimate.allocInit(13, 156);call #Ultimate.allocInit(34, 157);call #Ultimate.allocInit(37, 158);call #Ultimate.allocInit(37, 159);call #Ultimate.allocInit(6, 160);call write~init~int(51, 160, 0, 1);call write~init~int(99, 160, 1, 1);call write~init~int(53, 160, 2, 1);call write~init~int(57, 160, 3, 1);call write~init~int(120, 160, 4, 1);call write~init~int(0, 160, 5, 1);call #Ultimate.allocInit(13, 161);call #Ultimate.allocInit(34, 162);call #Ultimate.allocInit(53, 163);call #Ultimate.allocInit(53, 164);call #Ultimate.allocInit(6, 165);call write~init~int(51, 165, 0, 1);call write~init~int(99, 165, 1, 1);call write~init~int(53, 165, 2, 1);call write~init~int(57, 165, 3, 1);call write~init~int(120, 165, 4, 1);call write~init~int(0, 165, 5, 1);call #Ultimate.allocInit(13, 166);call #Ultimate.allocInit(34, 167);call #Ultimate.allocInit(49, 168);call #Ultimate.allocInit(49, 169);call #Ultimate.allocInit(6, 170);call write~init~int(51, 170, 0, 1);call write~init~int(99, 170, 1, 1);call write~init~int(53, 170, 2, 1);call write~init~int(57, 170, 3, 1);call write~init~int(120, 170, 4, 1);call write~init~int(0, 170, 5, 1);call #Ultimate.allocInit(13, 171);call #Ultimate.allocInit(34, 172);call #Ultimate.allocInit(28, 173);call #Ultimate.allocInit(28, 174);call #Ultimate.allocInit(6, 175);call write~init~int(51, 175, 0, 1);call write~init~int(99, 175, 1, 1);call write~init~int(53, 175, 2, 1);call write~init~int(57, 175, 3, 1);call write~init~int(120, 175, 4, 1);call write~init~int(0, 175, 5, 1);call #Ultimate.allocInit(13, 176);call #Ultimate.allocInit(34, 177);call #Ultimate.allocInit(41, 178);call #Ultimate.allocInit(41, 179);call #Ultimate.allocInit(56, 180);call #Ultimate.allocInit(56, 181);call #Ultimate.allocInit(70, 182);call #Ultimate.allocInit(75, 183);call #Ultimate.allocInit(6, 184);call write~init~int(51, 184, 0, 1);call write~init~int(99, 184, 1, 1);call write~init~int(53, 184, 2, 1);call write~init~int(57, 184, 3, 1);call write~init~int(120, 184, 4, 1);call write~init~int(0, 184, 5, 1);call #Ultimate.allocInit(18, 185);call #Ultimate.allocInit(34, 186);call #Ultimate.allocInit(36, 187);call #Ultimate.allocInit(36, 188);call #Ultimate.allocInit(34, 189);call #Ultimate.allocInit(48, 190);call #Ultimate.allocInit(71, 191);call #Ultimate.allocInit(6, 192);call write~init~int(51, 192, 0, 1);call write~init~int(99, 192, 1, 1);call write~init~int(53, 192, 2, 1);call write~init~int(57, 192, 3, 1);call write~init~int(120, 192, 4, 1);call write~init~int(0, 192, 5, 1);call #Ultimate.allocInit(13, 193);call #Ultimate.allocInit(34, 194);call #Ultimate.allocInit(21, 195);call #Ultimate.allocInit(21, 196);call #Ultimate.allocInit(74, 197);call #Ultimate.allocInit(50, 198);call #Ultimate.allocInit(38, 199);call #Ultimate.allocInit(6, 200);call write~init~int(51, 200, 0, 1);call write~init~int(99, 200, 1, 1);call write~init~int(53, 200, 2, 1);call write~init~int(57, 200, 3, 1);call write~init~int(120, 200, 4, 1);call write~init~int(0, 200, 5, 1);call #Ultimate.allocInit(18, 201);call #Ultimate.allocInit(34, 202);call #Ultimate.allocInit(29, 203);call #Ultimate.allocInit(29, 204);call #Ultimate.allocInit(6, 205);call write~init~int(51, 205, 0, 1);call write~init~int(99, 205, 1, 1);call write~init~int(53, 205, 2, 1);call write~init~int(57, 205, 3, 1);call write~init~int(120, 205, 4, 1);call write~init~int(0, 205, 5, 1);call #Ultimate.allocInit(21, 206);call #Ultimate.allocInit(34, 207);call #Ultimate.allocInit(24, 208);call #Ultimate.allocInit(24, 209);call #Ultimate.allocInit(6, 210);call write~init~int(51, 210, 0, 1);call write~init~int(99, 210, 1, 1);call write~init~int(53, 210, 2, 1);call write~init~int(57, 210, 3, 1);call write~init~int(120, 210, 4, 1);call write~init~int(0, 210, 5, 1);call #Ultimate.allocInit(21, 211);call #Ultimate.allocInit(34, 212);call #Ultimate.allocInit(43, 213);call #Ultimate.allocInit(43, 214);call #Ultimate.allocInit(50, 215);call #Ultimate.allocInit(6, 216);call write~init~int(51, 216, 0, 1);call write~init~int(99, 216, 1, 1);call write~init~int(53, 216, 2, 1);call write~init~int(57, 216, 3, 1);call write~init~int(120, 216, 4, 1);call write~init~int(0, 216, 5, 1);call #Ultimate.allocInit(17, 217);call #Ultimate.allocInit(34, 218);call #Ultimate.allocInit(34, 219);call #Ultimate.allocInit(34, 220);call #Ultimate.allocInit(6, 221);call write~init~int(51, 221, 0, 1);call write~init~int(99, 221, 1, 1);call write~init~int(53, 221, 2, 1);call write~init~int(57, 221, 3, 1);call write~init~int(120, 221, 4, 1);call write~init~int(0, 221, 5, 1);call #Ultimate.allocInit(17, 222);call #Ultimate.allocInit(34, 223);call #Ultimate.allocInit(48, 224);call #Ultimate.allocInit(48, 225);call #Ultimate.allocInit(6, 226);call write~init~int(51, 226, 0, 1);call write~init~int(99, 226, 1, 1);call write~init~int(53, 226, 2, 1);call write~init~int(57, 226, 3, 1);call write~init~int(120, 226, 4, 1);call write~init~int(0, 226, 5, 1);call #Ultimate.allocInit(17, 227);call #Ultimate.allocInit(34, 228);call #Ultimate.allocInit(38, 229);call #Ultimate.allocInit(38, 230);call #Ultimate.allocInit(6, 231);call write~init~int(51, 231, 0, 1);call write~init~int(99, 231, 1, 1);call write~init~int(53, 231, 2, 1);call write~init~int(57, 231, 3, 1);call write~init~int(120, 231, 4, 1);call write~init~int(0, 231, 5, 1);call #Ultimate.allocInit(17, 232);call #Ultimate.allocInit(34, 233);call #Ultimate.allocInit(27, 234);call #Ultimate.allocInit(27, 235);call #Ultimate.allocInit(48, 236);call #Ultimate.allocInit(6, 237);call write~init~int(51, 237, 0, 1);call write~init~int(99, 237, 1, 1);call write~init~int(53, 237, 2, 1);call write~init~int(57, 237, 3, 1);call write~init~int(120, 237, 4, 1);call write~init~int(0, 237, 5, 1);call #Ultimate.allocInit(17, 238);call #Ultimate.allocInit(34, 239);call #Ultimate.allocInit(38, 240);call #Ultimate.allocInit(38, 241);call #Ultimate.allocInit(6, 242);call write~init~int(51, 242, 0, 1);call write~init~int(99, 242, 1, 1);call write~init~int(53, 242, 2, 1);call write~init~int(57, 242, 3, 1);call write~init~int(120, 242, 4, 1);call write~init~int(0, 242, 5, 1);call #Ultimate.allocInit(20, 243);call #Ultimate.allocInit(34, 244);call #Ultimate.allocInit(35, 245);call #Ultimate.allocInit(35, 246);call #Ultimate.allocInit(6, 247);call write~init~int(51, 247, 0, 1);call write~init~int(99, 247, 1, 1);call write~init~int(53, 247, 2, 1);call write~init~int(57, 247, 3, 1);call write~init~int(120, 247, 4, 1);call write~init~int(0, 247, 5, 1);call #Ultimate.allocInit(20, 248);call #Ultimate.allocInit(34, 249);call #Ultimate.allocInit(41, 250);call #Ultimate.allocInit(41, 251);call #Ultimate.allocInit(6, 252);call write~init~int(51, 252, 0, 1);call write~init~int(99, 252, 1, 1);call write~init~int(53, 252, 2, 1);call write~init~int(57, 252, 3, 1);call write~init~int(120, 252, 4, 1);call write~init~int(0, 252, 5, 1);call #Ultimate.allocInit(20, 253);call #Ultimate.allocInit(34, 254);call #Ultimate.allocInit(48, 255);call #Ultimate.allocInit(48, 256);call #Ultimate.allocInit(6, 257);call write~init~int(51, 257, 0, 1);call write~init~int(99, 257, 1, 1);call write~init~int(53, 257, 2, 1);call write~init~int(57, 257, 3, 1);call write~init~int(120, 257, 4, 1);call write~init~int(0, 257, 5, 1);call #Ultimate.allocInit(20, 258);call #Ultimate.allocInit(34, 259);call #Ultimate.allocInit(38, 260);call #Ultimate.allocInit(38, 261);call #Ultimate.allocInit(6, 262);call write~init~int(51, 262, 0, 1);call write~init~int(99, 262, 1, 1);call write~init~int(53, 262, 2, 1);call write~init~int(57, 262, 3, 1);call write~init~int(120, 262, 4, 1);call write~init~int(0, 262, 5, 1);call #Ultimate.allocInit(20, 263);call #Ultimate.allocInit(34, 264);call #Ultimate.allocInit(35, 265);call #Ultimate.allocInit(35, 266);call #Ultimate.allocInit(6, 267);call write~init~int(51, 267, 0, 1);call write~init~int(99, 267, 1, 1);call write~init~int(53, 267, 2, 1);call write~init~int(57, 267, 3, 1);call write~init~int(120, 267, 4, 1);call write~init~int(0, 267, 5, 1);call #Ultimate.allocInit(20, 268);call #Ultimate.allocInit(34, 269);call #Ultimate.allocInit(30, 270);call #Ultimate.allocInit(30, 271);call #Ultimate.allocInit(6, 272);call write~init~int(51, 272, 0, 1);call write~init~int(99, 272, 1, 1);call write~init~int(53, 272, 2, 1);call write~init~int(57, 272, 3, 1);call write~init~int(120, 272, 4, 1);call write~init~int(0, 272, 5, 1);call #Ultimate.allocInit(20, 273);call #Ultimate.allocInit(34, 274);call #Ultimate.allocInit(33, 275);call #Ultimate.allocInit(33, 276);call #Ultimate.allocInit(48, 277);call #Ultimate.allocInit(6, 278);call write~init~int(51, 278, 0, 1);call write~init~int(99, 278, 1, 1);call write~init~int(53, 278, 2, 1);call write~init~int(57, 278, 3, 1);call write~init~int(120, 278, 4, 1);call write~init~int(0, 278, 5, 1);call #Ultimate.allocInit(20, 279);call #Ultimate.allocInit(34, 280);call #Ultimate.allocInit(38, 281);call #Ultimate.allocInit(38, 282);call #Ultimate.allocInit(6, 283);call write~init~int(51, 283, 0, 1);call write~init~int(99, 283, 1, 1);call write~init~int(53, 283, 2, 1);call write~init~int(57, 283, 3, 1);call write~init~int(120, 283, 4, 1);call write~init~int(0, 283, 5, 1);call #Ultimate.allocInit(10, 284);call #Ultimate.allocInit(34, 285);call #Ultimate.allocInit(45, 286);call #Ultimate.allocInit(45, 287);call #Ultimate.allocInit(6, 288);call write~init~int(51, 288, 0, 1);call write~init~int(99, 288, 1, 1);call write~init~int(53, 288, 2, 1);call write~init~int(57, 288, 3, 1);call write~init~int(120, 288, 4, 1);call write~init~int(0, 288, 5, 1);call #Ultimate.allocInit(10, 289);call #Ultimate.allocInit(34, 290);call #Ultimate.allocInit(26, 291);call #Ultimate.allocInit(26, 292);call #Ultimate.allocInit(6, 293);call write~init~int(51, 293, 0, 1);call write~init~int(99, 293, 1, 1);call write~init~int(53, 293, 2, 1);call write~init~int(57, 293, 3, 1);call write~init~int(120, 293, 4, 1);call write~init~int(0, 293, 5, 1);call #Ultimate.allocInit(10, 294);call #Ultimate.allocInit(34, 295);call #Ultimate.allocInit(40, 296);call #Ultimate.allocInit(40, 297);call #Ultimate.allocInit(50, 298);call #Ultimate.allocInit(6, 299);call write~init~int(51, 299, 0, 1);call write~init~int(99, 299, 1, 1);call write~init~int(53, 299, 2, 1);call write~init~int(57, 299, 3, 1);call write~init~int(120, 299, 4, 1);call write~init~int(0, 299, 5, 1);call #Ultimate.allocInit(13, 300);call #Ultimate.allocInit(34, 301);call #Ultimate.allocInit(30, 302);call #Ultimate.allocInit(30, 303);call #Ultimate.allocInit(6, 304);call write~init~int(51, 304, 0, 1);call write~init~int(99, 304, 1, 1);call write~init~int(53, 304, 2, 1);call write~init~int(57, 304, 3, 1);call write~init~int(120, 304, 4, 1);call write~init~int(0, 304, 5, 1);call #Ultimate.allocInit(13, 305);call #Ultimate.allocInit(34, 306);call #Ultimate.allocInit(26, 307);call #Ultimate.allocInit(26, 308);call #Ultimate.allocInit(6, 309);call write~init~int(51, 309, 0, 1);call write~init~int(99, 309, 1, 1);call write~init~int(53, 309, 2, 1);call write~init~int(57, 309, 3, 1);call write~init~int(120, 309, 4, 1);call write~init~int(0, 309, 5, 1);call #Ultimate.allocInit(13, 310);call #Ultimate.allocInit(34, 311);call #Ultimate.allocInit(40, 312);call #Ultimate.allocInit(40, 313);call #Ultimate.allocInit(22, 314);call #Ultimate.allocInit(6, 315);call write~init~int(51, 315, 0, 1);call write~init~int(99, 315, 1, 1);call write~init~int(53, 315, 2, 1);call write~init~int(57, 315, 3, 1);call write~init~int(120, 315, 4, 1);call write~init~int(0, 315, 5, 1);call #Ultimate.allocInit(13, 316);call #Ultimate.allocInit(34, 317);call #Ultimate.allocInit(21, 318);call #Ultimate.allocInit(21, 319);call #Ultimate.allocInit(10, 320);call #Ultimate.allocInit(9, 321);call #Ultimate.allocInit(6, 322);call write~init~int(51, 322, 0, 1);call write~init~int(99, 322, 1, 1);call write~init~int(53, 322, 2, 1);call write~init~int(57, 322, 3, 1);call write~init~int(120, 322, 4, 1);call write~init~int(0, 322, 5, 1);call #Ultimate.allocInit(13, 323);call #Ultimate.allocInit(34, 324);call #Ultimate.allocInit(51, 325);call #Ultimate.allocInit(51, 326);call #Ultimate.allocInit(6, 327);call write~init~int(51, 327, 0, 1);call write~init~int(99, 327, 1, 1);call write~init~int(53, 327, 2, 1);call write~init~int(57, 327, 3, 1);call write~init~int(120, 327, 4, 1);call write~init~int(0, 327, 5, 1);call #Ultimate.allocInit(13, 328);call #Ultimate.allocInit(34, 329);call #Ultimate.allocInit(85, 330);call #Ultimate.allocInit(85, 331);call #Ultimate.allocInit(60, 332);call #Ultimate.allocInit(54, 333);call #Ultimate.allocInit(32, 334);call #Ultimate.allocInit(39, 335);call #Ultimate.allocInit(34, 336);call #Ultimate.allocInit(6, 337);call write~init~int(51, 337, 0, 1);call write~init~int(99, 337, 1, 1);call write~init~int(53, 337, 2, 1);call write~init~int(57, 337, 3, 1);call write~init~int(120, 337, 4, 1);call write~init~int(0, 337, 5, 1);call #Ultimate.allocInit(14, 338);call #Ultimate.allocInit(14, 339);call #Ultimate.allocInit(14, 340);call #Ultimate.allocInit(32, 341);call #Ultimate.allocInit(25, 342);call #Ultimate.allocInit(46, 343);call #Ultimate.allocInit(6, 344);call write~init~int(51, 344, 0, 1);call write~init~int(99, 344, 1, 1);call write~init~int(53, 344, 2, 1);call write~init~int(57, 344, 3, 1);call write~init~int(120, 344, 4, 1);call write~init~int(0, 344, 5, 1);call #Ultimate.allocInit(6, 345);call write~init~int(51, 345, 0, 1);call write~init~int(99, 345, 1, 1);call write~init~int(53, 345, 2, 1);call write~init~int(57, 345, 3, 1);call write~init~int(120, 345, 4, 1);call write~init~int(0, 345, 5, 1);call #Ultimate.allocInit(1, 346);call write~init~int(0, 346, 0, 1);call #Ultimate.allocInit(54, 347);call #Ultimate.allocInit(56, 348);call #Ultimate.allocInit(58, 349);call #Ultimate.allocInit(58, 350);call #Ultimate.allocInit(58, 351);call #Ultimate.allocInit(54, 352);call #Ultimate.allocInit(56, 353);call #Ultimate.allocInit(58, 354);call #Ultimate.allocInit(58, 355);call #Ultimate.allocInit(58, 356);call #Ultimate.allocInit(54, 357);call #Ultimate.allocInit(56, 358);call #Ultimate.allocInit(58, 359);call #Ultimate.allocInit(58, 360);call #Ultimate.allocInit(58, 361);call #Ultimate.allocInit(54, 362);call #Ultimate.allocInit(56, 363);call #Ultimate.allocInit(58, 364);call #Ultimate.allocInit(58, 365);call #Ultimate.allocInit(58, 366);call #Ultimate.allocInit(54, 367);call #Ultimate.allocInit(56, 368);call #Ultimate.allocInit(58, 369);call #Ultimate.allocInit(58, 370);call #Ultimate.allocInit(58, 371);call #Ultimate.allocInit(54, 372);call #Ultimate.allocInit(56, 373);call #Ultimate.allocInit(58, 374);call #Ultimate.allocInit(58, 375);call #Ultimate.allocInit(58, 376);call #Ultimate.allocInit(54, 377);call #Ultimate.allocInit(56, 378);call #Ultimate.allocInit(58, 379);call #Ultimate.allocInit(58, 380);call #Ultimate.allocInit(58, 381);call #Ultimate.allocInit(54, 382);call #Ultimate.allocInit(56, 383);call #Ultimate.allocInit(58, 384);call #Ultimate.allocInit(58, 385);call #Ultimate.allocInit(58, 386);call #Ultimate.allocInit(54, 387);call #Ultimate.allocInit(56, 388);call #Ultimate.allocInit(58, 389);call #Ultimate.allocInit(58, 390);call #Ultimate.allocInit(58, 391);call #Ultimate.allocInit(54, 392);call #Ultimate.allocInit(56, 393);call #Ultimate.allocInit(58, 394);call #Ultimate.allocInit(58, 395);call #Ultimate.allocInit(58, 396);call #Ultimate.allocInit(54, 397);call #Ultimate.allocInit(56, 398);call #Ultimate.allocInit(58, 399);call #Ultimate.allocInit(58, 400);call #Ultimate.allocInit(58, 401);call #Ultimate.allocInit(54, 402);call #Ultimate.allocInit(56, 403);call #Ultimate.allocInit(58, 404);call #Ultimate.allocInit(58, 405);call #Ultimate.allocInit(58, 406);call #Ultimate.allocInit(54, 407);call #Ultimate.allocInit(56, 408);call #Ultimate.allocInit(58, 409);call #Ultimate.allocInit(58, 410);call #Ultimate.allocInit(58, 411);call #Ultimate.allocInit(54, 412);call #Ultimate.allocInit(56, 413);call #Ultimate.allocInit(58, 414);call #Ultimate.allocInit(58, 415);call #Ultimate.allocInit(58, 416);call #Ultimate.allocInit(57, 417);call #Ultimate.allocInit(57, 418);call #Ultimate.allocInit(57, 419);call #Ultimate.allocInit(57, 420);call #Ultimate.allocInit(57, 421);call #Ultimate.allocInit(57, 422);call #Ultimate.allocInit(57, 423);call #Ultimate.allocInit(57, 424);call #Ultimate.allocInit(57, 425);call #Ultimate.allocInit(57, 426);call #Ultimate.allocInit(57, 427);call #Ultimate.allocInit(57, 428);call #Ultimate.allocInit(57, 429);call #Ultimate.allocInit(57, 430);call #Ultimate.allocInit(2, 431);call write~init~int(48, 431, 0, 1);call write~init~int(0, 431, 1, 1);call #Ultimate.allocInit(70, 432);~rx_copybreak~0 := 200;~mtu~0 := 1500;~max_interrupt_work~0 := 32;~watchdog~0 := 5000;~debug~0 := 1;~#version~0.base, ~#version~0.offset := 433, 0;call #Ultimate.allocInit(34, 433);call write~init~int(51, ~#version~0.base, ~#version~0.offset, 1);call write~init~int(99, ~#version~0.base, 1 + ~#version~0.offset, 1);call write~init~int(53, ~#version~0.base, 2 + ~#version~0.offset, 1);call write~init~int(57, ~#version~0.base, 3 + ~#version~0.offset, 1);call write~init~int(120, ~#version~0.base, 4 + ~#version~0.offset, 1);call write~init~int(58, ~#version~0.base, 5 + ~#version~0.offset, 1);call write~init~int(32, ~#version~0.base, 6 + ~#version~0.offset, 1);call write~init~int(68, ~#version~0.base, 7 + ~#version~0.offset, 1);call write~init~int(111, ~#version~0.base, 8 + ~#version~0.offset, 1);call write~init~int(110, ~#version~0.base, 9 + ~#version~0.offset, 1);call write~init~int(97, ~#version~0.base, 10 + ~#version~0.offset, 1);call write~init~int(108, ~#version~0.base, 11 + ~#version~0.offset, 1);call write~init~int(100, ~#version~0.base, 12 + ~#version~0.offset, 1);call write~init~int(32, ~#version~0.base, 13 + ~#version~0.offset, 1);call write~init~int(66, ~#version~0.base, 14 + ~#version~0.offset, 1);call write~init~int(101, ~#version~0.base, 15 + ~#version~0.offset, 1);call write~init~int(99, ~#version~0.base, 16 + ~#version~0.offset, 1);call write~init~int(107, ~#version~0.base, 17 + ~#version~0.offset, 1);call write~init~int(101, ~#version~0.base, 18 + ~#version~0.offset, 1);call write~init~int(114, ~#version~0.base, 19 + ~#version~0.offset, 1);call write~init~int(32, ~#version~0.base, 20 + ~#version~0.offset, 1);call write~init~int(97, ~#version~0.base, 21 + ~#version~0.offset, 1);call write~init~int(110, ~#version~0.base, 22 + ~#version~0.offset, 1);call write~init~int(100, ~#version~0.base, 23 + ~#version~0.offset, 1);call write~init~int(32, ~#version~0.base, 24 + ~#version~0.offset, 1);call write~init~int(111, ~#version~0.base, 25 + ~#version~0.offset, 1);call write~init~int(116, ~#version~0.base, 26 + ~#version~0.offset, 1);call write~init~int(104, ~#version~0.base, 27 + ~#version~0.offset, 1);call write~init~int(101, ~#version~0.base, 28 + ~#version~0.offset, 1);call write~init~int(114, ~#version~0.base, 29 + ~#version~0.offset, 1);call write~init~int(115, ~#version~0.base, 30 + ~#version~0.offset, 1);call write~init~int(46, ~#version~0.base, 31 + ~#version~0.offset, 1);call write~init~int(10, ~#version~0.base, 32 + ~#version~0.offset, 1);call write~init~int(0, ~#version~0.base, 33 + ~#version~0.offset, 1);~mii_preamble_required~0 := 0;~#vortex_info_tbl~0.base, ~#vortex_info_tbl~0.offset := 434, 0;call #Ultimate.allocInit(800, 434);call write~init~$Pointer$(4, 0, ~#vortex_info_tbl~0.base, ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 8 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 12 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 16 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(5, 0, ~#vortex_info_tbl~0.base, 20 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 28 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 32 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 36 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(6, 0, ~#vortex_info_tbl~0.base, 40 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 48 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 52 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 56 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(7, 0, ~#vortex_info_tbl~0.base, 60 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 68 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 72 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 76 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(8, 0, ~#vortex_info_tbl~0.base, 80 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 88 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 92 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 96 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(9, 0, ~#vortex_info_tbl~0.base, 100 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 108 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(1, ~#vortex_info_tbl~0.base, 112 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(32, ~#vortex_info_tbl~0.base, 116 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(10, 0, ~#vortex_info_tbl~0.base, 120 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 128 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(65538, ~#vortex_info_tbl~0.base, 132 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(64, ~#vortex_info_tbl~0.base, 136 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(11, 0, ~#vortex_info_tbl~0.base, 140 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 148 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(65538, ~#vortex_info_tbl~0.base, 152 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(64, ~#vortex_info_tbl~0.base, 156 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(12, 0, ~#vortex_info_tbl~0.base, 160 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 168 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 172 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 176 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(13, 0, ~#vortex_info_tbl~0.base, 180 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 188 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 192 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 196 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(14, 0, ~#vortex_info_tbl~0.base, 200 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 208 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 212 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 216 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(15, 0, ~#vortex_info_tbl~0.base, 220 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 228 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 232 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 236 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(16, 0, ~#vortex_info_tbl~0.base, 240 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 248 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(65602, ~#vortex_info_tbl~0.base, 252 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(64, ~#vortex_info_tbl~0.base, 256 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(17, 0, ~#vortex_info_tbl~0.base, 260 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 268 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(65602, ~#vortex_info_tbl~0.base, 272 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(64, ~#vortex_info_tbl~0.base, 276 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(18, 0, ~#vortex_info_tbl~0.base, 280 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 288 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41092, ~#vortex_info_tbl~0.base, 292 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 296 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(19, 0, ~#vortex_info_tbl~0.base, 300 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 308 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41092, ~#vortex_info_tbl~0.base, 312 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 316 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(20, 0, ~#vortex_info_tbl~0.base, 320 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 328 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8324, ~#vortex_info_tbl~0.base, 332 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 336 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(21, 0, ~#vortex_info_tbl~0.base, 340 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 348 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8196, ~#vortex_info_tbl~0.base, 352 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 356 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(22, 0, ~#vortex_info_tbl~0.base, 360 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 368 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41096, ~#vortex_info_tbl~0.base, 372 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 376 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(23, 0, ~#vortex_info_tbl~0.base, 380 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 388 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8264, ~#vortex_info_tbl~0.base, 392 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 396 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(24, 0, ~#vortex_info_tbl~0.base, 400 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 408 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(40964, ~#vortex_info_tbl~0.base, 412 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 416 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(25, 0, ~#vortex_info_tbl~0.base, 420 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 428 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8324, ~#vortex_info_tbl~0.base, 432 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 436 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(26, 0, ~#vortex_info_tbl~0.base, 440 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 448 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41092, ~#vortex_info_tbl~0.base, 452 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 456 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(27, 0, ~#vortex_info_tbl~0.base, 460 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 468 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8212, ~#vortex_info_tbl~0.base, 472 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 476 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(28, 0, ~#vortex_info_tbl~0.base, 480 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 488 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(9112, ~#vortex_info_tbl~0.base, 492 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 496 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(29, 0, ~#vortex_info_tbl~0.base, 500 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 508 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(29576, ~#vortex_info_tbl~0.base, 512 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 516 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(30, 0, ~#vortex_info_tbl~0.base, 520 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 528 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(82, ~#vortex_info_tbl~0.base, 532 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 536 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(31, 0, ~#vortex_info_tbl~0.base, 540 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 548 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(82, ~#vortex_info_tbl~0.base, 552 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 556 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(32, 0, ~#vortex_info_tbl~0.base, 560 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 568 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(9620, ~#vortex_info_tbl~0.base, 572 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 576 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(33, 0, ~#vortex_info_tbl~0.base, 580 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 588 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(11160, ~#vortex_info_tbl~0.base, 592 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 596 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(34, 0, ~#vortex_info_tbl~0.base, 600 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 608 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(10132, ~#vortex_info_tbl~0.base, 612 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 616 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(35, 0, ~#vortex_info_tbl~0.base, 620 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 628 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(10132, ~#vortex_info_tbl~0.base, 632 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 636 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(36, 0, ~#vortex_info_tbl~0.base, 640 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 648 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(11160, ~#vortex_info_tbl~0.base, 652 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 656 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(37, 0, ~#vortex_info_tbl~0.base, 660 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 668 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 672 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 676 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(38, 0, ~#vortex_info_tbl~0.base, 680 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 688 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 692 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 696 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(39, 0, ~#vortex_info_tbl~0.base, 700 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 708 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 712 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 716 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(40, 0, ~#vortex_info_tbl~0.base, 720 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 728 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 732 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 736 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(41, 0, ~#vortex_info_tbl~0.base, 740 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 748 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(41092, ~#vortex_info_tbl~0.base, 752 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 756 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(42, 0, ~#vortex_info_tbl~0.base, 760 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(4, ~#vortex_info_tbl~0.base, 768 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(8328, ~#vortex_info_tbl~0.base, 772 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(128, ~#vortex_info_tbl~0.base, 776 + ~#vortex_info_tbl~0.offset, 4);call write~init~$Pointer$(0, 0, ~#vortex_info_tbl~0.base, 780 + ~#vortex_info_tbl~0.offset, 8);call write~init~int(0, ~#vortex_info_tbl~0.base, 788 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(0, ~#vortex_info_tbl~0.base, 792 + ~#vortex_info_tbl~0.offset, 4);call write~init~int(0, ~#vortex_info_tbl~0.base, 796 + ~#vortex_info_tbl~0.offset, 4);~#vortex_pci_tbl~0.base, ~#vortex_pci_tbl~0.offset := 435, 0;call #Ultimate.allocInit(1280, 435);call write~init~int(4279, ~#vortex_pci_tbl~0.base, ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22784, ~#vortex_pci_tbl~0.base, 4 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 8 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 12 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 16 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 20 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 24 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 32 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22816, ~#vortex_pci_tbl~0.base, 36 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 40 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 44 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 48 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 52 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(1, ~#vortex_pci_tbl~0.base, 56 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 64 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22896, ~#vortex_pci_tbl~0.base, 68 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 72 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 76 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 80 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 84 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(2, ~#vortex_pci_tbl~0.base, 88 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 96 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22864, ~#vortex_pci_tbl~0.base, 100 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 104 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 108 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 112 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 116 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(3, ~#vortex_pci_tbl~0.base, 120 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 128 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22865, ~#vortex_pci_tbl~0.base, 132 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 136 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 140 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 144 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 148 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4, ~#vortex_pci_tbl~0.base, 152 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 160 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22866, ~#vortex_pci_tbl~0.base, 164 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 168 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 172 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 176 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 180 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(5, ~#vortex_pci_tbl~0.base, 184 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 192 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36864, ~#vortex_pci_tbl~0.base, 196 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 200 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 204 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 208 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 212 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(6, ~#vortex_pci_tbl~0.base, 216 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 224 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36865, ~#vortex_pci_tbl~0.base, 228 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 232 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 236 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 240 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 244 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(7, ~#vortex_pci_tbl~0.base, 248 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 256 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36868, ~#vortex_pci_tbl~0.base, 260 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 264 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 268 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 272 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 276 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(8, ~#vortex_pci_tbl~0.base, 280 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 288 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36869, ~#vortex_pci_tbl~0.base, 292 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 296 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 300 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 304 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 308 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(9, ~#vortex_pci_tbl~0.base, 312 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 320 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36870, ~#vortex_pci_tbl~0.base, 324 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 328 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 332 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 336 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 340 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(10, ~#vortex_pci_tbl~0.base, 344 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 352 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36874, ~#vortex_pci_tbl~0.base, 356 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 360 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 364 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 368 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 372 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(11, ~#vortex_pci_tbl~0.base, 376 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 384 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36944, ~#vortex_pci_tbl~0.base, 388 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 392 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 396 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 400 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 404 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(12, ~#vortex_pci_tbl~0.base, 408 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 416 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36945, ~#vortex_pci_tbl~0.base, 420 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 424 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 428 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 432 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 436 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(13, ~#vortex_pci_tbl~0.base, 440 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 448 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36948, ~#vortex_pci_tbl~0.base, 452 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 456 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 460 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 464 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 468 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(14, ~#vortex_pci_tbl~0.base, 472 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 480 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36949, ~#vortex_pci_tbl~0.base, 484 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 488 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 492 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 496 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 500 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(15, ~#vortex_pci_tbl~0.base, 504 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 512 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36952, ~#vortex_pci_tbl~0.base, 516 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 520 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 524 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 528 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 532 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(16, ~#vortex_pci_tbl~0.base, 536 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 544 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36954, ~#vortex_pci_tbl~0.base, 548 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 552 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 556 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 560 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 564 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(17, ~#vortex_pci_tbl~0.base, 568 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 576 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37376, ~#vortex_pci_tbl~0.base, 580 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 584 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 588 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 592 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 596 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(18, ~#vortex_pci_tbl~0.base, 600 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 608 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37378, ~#vortex_pci_tbl~0.base, 612 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 616 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 620 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 624 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 628 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(19, ~#vortex_pci_tbl~0.base, 632 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 640 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(38912, ~#vortex_pci_tbl~0.base, 644 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 648 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 652 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 656 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 660 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(20, ~#vortex_pci_tbl~0.base, 664 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 672 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(38917, ~#vortex_pci_tbl~0.base, 676 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 680 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 684 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 688 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 692 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(21, ~#vortex_pci_tbl~0.base, 696 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 704 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(30278, ~#vortex_pci_tbl~0.base, 708 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 712 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 716 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 720 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 724 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(22, ~#vortex_pci_tbl~0.base, 728 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 736 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(20565, ~#vortex_pci_tbl~0.base, 740 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 744 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 748 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 752 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 756 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(23, ~#vortex_pci_tbl~0.base, 760 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 768 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(24661, ~#vortex_pci_tbl~0.base, 772 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 776 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 780 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 784 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 788 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(24, ~#vortex_pci_tbl~0.base, 792 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 800 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(24662, ~#vortex_pci_tbl~0.base, 804 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 808 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 812 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 816 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 820 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(25, ~#vortex_pci_tbl~0.base, 824 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 832 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(23383, ~#vortex_pci_tbl~0.base, 836 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 840 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 844 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 848 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 852 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(26, ~#vortex_pci_tbl~0.base, 856 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 864 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(20567, ~#vortex_pci_tbl~0.base, 868 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 872 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 876 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 880 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 884 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(27, ~#vortex_pci_tbl~0.base, 888 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 896 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(20823, ~#vortex_pci_tbl~0.base, 900 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 904 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 908 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 912 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 916 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(28, ~#vortex_pci_tbl~0.base, 920 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 928 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(21079, ~#vortex_pci_tbl~0.base, 932 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 936 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 940 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 944 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 948 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(29, ~#vortex_pci_tbl~0.base, 952 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 960 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(25952, ~#vortex_pci_tbl~0.base, 964 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 968 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 972 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 976 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 980 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(30, ~#vortex_pci_tbl~0.base, 984 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 992 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(25954, ~#vortex_pci_tbl~0.base, 996 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1000 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1004 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1008 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1012 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(31, ~#vortex_pci_tbl~0.base, 1016 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1024 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(25956, ~#vortex_pci_tbl~0.base, 1028 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1032 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1036 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1040 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1044 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(32, ~#vortex_pci_tbl~0.base, 1048 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1056 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(17664, ~#vortex_pci_tbl~0.base, 1060 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1064 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1068 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1072 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1076 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(33, ~#vortex_pci_tbl~0.base, 1080 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1088 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37377, ~#vortex_pci_tbl~0.base, 1092 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1096 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1100 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1104 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1108 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(34, ~#vortex_pci_tbl~0.base, 1112 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1120 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4609, ~#vortex_pci_tbl~0.base, 1124 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1128 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1132 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1136 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1140 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(35, ~#vortex_pci_tbl~0.base, 1144 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1152 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4610, ~#vortex_pci_tbl~0.base, 1156 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1160 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1164 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1168 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1172 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36, ~#vortex_pci_tbl~0.base, 1176 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1184 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(36950, ~#vortex_pci_tbl~0.base, 1188 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1192 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1196 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1200 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1204 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37, ~#vortex_pci_tbl~0.base, 1208 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(4279, ~#vortex_pci_tbl~0.base, 1216 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(37392, ~#vortex_pci_tbl~0.base, 1220 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1224 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#vortex_pci_tbl~0.base, 1228 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1232 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1236 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(38, ~#vortex_pci_tbl~0.base, 1240 + ~#vortex_pci_tbl~0.offset, 8);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1248 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1252 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1256 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1260 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1264 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1268 + ~#vortex_pci_tbl~0.offset, 4);call write~init~int(0, ~#vortex_pci_tbl~0.base, 1272 + ~#vortex_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#media_tbl~0.base, ~#media_tbl~0.offset := 436, 0;call #Ultimate.allocInit(264, 436);call write~init~$Pointer$(43, 0, ~#media_tbl~0.base, ~#media_tbl~0.offset, 8);call write~init~int(192, ~#media_tbl~0.base, 8 + ~#media_tbl~0.offset, 4);call write~init~int(8, ~#media_tbl~0.base, 12 + ~#media_tbl~0.offset, 4);call write~init~int(3, ~#media_tbl~0.base, 16 + ~#media_tbl~0.offset, 4);call write~init~int(350, ~#media_tbl~0.base, 20 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(44, 0, ~#media_tbl~0.base, 24 + ~#media_tbl~0.offset, 8);call write~init~int(8, ~#media_tbl~0.base, 32 + ~#media_tbl~0.offset, 4);call write~init~int(32, ~#media_tbl~0.base, 36 + ~#media_tbl~0.offset, 4);call write~init~int(10, ~#media_tbl~0.base, 40 + ~#media_tbl~0.offset, 4);call write~init~int(25, ~#media_tbl~0.base, 44 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(45, 0, ~#media_tbl~0.base, 48 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 56 + ~#media_tbl~0.offset, 4);call write~init~int(128, ~#media_tbl~0.base, 60 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 64 + ~#media_tbl~0.offset, 4);call write~init~int(10000, ~#media_tbl~0.base, 68 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(46, 0, ~#media_tbl~0.base, 72 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 80 + ~#media_tbl~0.offset, 4);call write~init~int(16, ~#media_tbl~0.base, 84 + ~#media_tbl~0.offset, 4);call write~init~int(1, ~#media_tbl~0.base, 88 + ~#media_tbl~0.offset, 4);call write~init~int(25, ~#media_tbl~0.base, 92 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(47, 0, ~#media_tbl~0.base, 96 + ~#media_tbl~0.offset, 8);call write~init~int(128, ~#media_tbl~0.base, 104 + ~#media_tbl~0.offset, 4);call write~init~int(2, ~#media_tbl~0.base, 108 + ~#media_tbl~0.offset, 4);call write~init~int(5, ~#media_tbl~0.base, 112 + ~#media_tbl~0.offset, 4);call write~init~int(350, ~#media_tbl~0.base, 116 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(48, 0, ~#media_tbl~0.base, 120 + ~#media_tbl~0.offset, 8);call write~init~int(128, ~#media_tbl~0.base, 128 + ~#media_tbl~0.offset, 4);call write~init~int(4, ~#media_tbl~0.base, 132 + ~#media_tbl~0.offset, 4);call write~init~int(6, ~#media_tbl~0.base, 136 + ~#media_tbl~0.offset, 4);call write~init~int(350, ~#media_tbl~0.base, 140 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(49, 0, ~#media_tbl~0.base, 144 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 152 + ~#media_tbl~0.offset, 4);call write~init~int(65, ~#media_tbl~0.base, 156 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 160 + ~#media_tbl~0.offset, 4);call write~init~int(750, ~#media_tbl~0.base, 164 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(50, 0, ~#media_tbl~0.base, 168 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 176 + ~#media_tbl~0.offset, 4);call write~init~int(1, ~#media_tbl~0.base, 180 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 184 + ~#media_tbl~0.offset, 4);call write~init~int(10000, ~#media_tbl~0.base, 188 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(51, 0, ~#media_tbl~0.base, 192 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 200 + ~#media_tbl~0.offset, 4);call write~init~int(65, ~#media_tbl~0.base, 204 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 208 + ~#media_tbl~0.offset, 4);call write~init~int(750, ~#media_tbl~0.base, 212 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(52, 0, ~#media_tbl~0.base, 216 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 224 + ~#media_tbl~0.offset, 4);call write~init~int(65, ~#media_tbl~0.base, 228 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 232 + ~#media_tbl~0.offset, 4);call write~init~int(750, ~#media_tbl~0.base, 236 + ~#media_tbl~0.offset, 4);call write~init~$Pointer$(53, 0, ~#media_tbl~0.base, 240 + ~#media_tbl~0.offset, 8);call write~init~int(0, ~#media_tbl~0.base, 248 + ~#media_tbl~0.offset, 4);call write~init~int(255, ~#media_tbl~0.base, 252 + ~#media_tbl~0.offset, 4);call write~init~int(0, ~#media_tbl~0.base, 256 + ~#media_tbl~0.offset, 4);call write~init~int(10000, ~#media_tbl~0.base, 260 + ~#media_tbl~0.offset, 4);~#ethtool_stats_keys~0.base, ~#ethtool_stats_keys~0.offset := 437, 0;call #Ultimate.allocInit(160, 437);call write~init~int(116, ~#ethtool_stats_keys~0.base, ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 1 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 2 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(100, ~#ethtool_stats_keys~0.base, 3 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 4 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(102, ~#ethtool_stats_keys~0.base, 5 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 6 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(114, ~#ethtool_stats_keys~0.base, 7 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(114, ~#ethtool_stats_keys~0.base, 8 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 9 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(100, ~#ethtool_stats_keys~0.base, 10 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 11 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 12 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 13 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 14 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 15 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 16 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 17 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 18 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 19 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 20 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 21 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 22 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 23 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 24 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 25 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 26 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 27 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 28 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 29 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 30 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 31 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(116, ~#ethtool_stats_keys~0.base, 32 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 33 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 34 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(109, ~#ethtool_stats_keys~0.base, 35 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(97, ~#ethtool_stats_keys~0.base, 36 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 37 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 38 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(99, ~#ethtool_stats_keys~0.base, 39 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 40 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 41 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 42 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 43 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 44 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 45 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 46 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(110, ~#ethtool_stats_keys~0.base, 47 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 48 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 49 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 50 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 51 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 52 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 53 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 54 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 55 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 56 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 57 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 58 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 59 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 60 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 61 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 62 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 63 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(116, ~#ethtool_stats_keys~0.base, 64 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 65 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 66 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(109, ~#ethtool_stats_keys~0.base, 67 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(117, ~#ethtool_stats_keys~0.base, 68 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 69 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(116, ~#ethtool_stats_keys~0.base, 70 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 71 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(112, ~#ethtool_stats_keys~0.base, 72 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 73 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 74 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 75 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(99, ~#ethtool_stats_keys~0.base, 76 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 77 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 78 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 79 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 80 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 81 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 82 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 83 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(110, ~#ethtool_stats_keys~0.base, 84 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 85 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 86 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 87 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 88 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 89 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 90 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 91 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 92 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 93 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 94 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 95 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(116, ~#ethtool_stats_keys~0.base, 96 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 97 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 98 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 99 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 100 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(110, ~#ethtool_stats_keys~0.base, 101 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(103, ~#ethtool_stats_keys~0.base, 102 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 103 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(101, ~#ethtool_stats_keys~0.base, 104 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 105 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(99, ~#ethtool_stats_keys~0.base, 106 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 107 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 108 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(108, ~#ethtool_stats_keys~0.base, 109 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 110 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 111 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(105, ~#ethtool_stats_keys~0.base, 112 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(111, ~#ethtool_stats_keys~0.base, 113 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(110, ~#ethtool_stats_keys~0.base, 114 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 115 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 116 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 117 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 118 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 119 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 120 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 121 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 122 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 123 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 124 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 125 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 126 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 127 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(114, ~#ethtool_stats_keys~0.base, 128 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(120, ~#ethtool_stats_keys~0.base, 129 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 130 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(98, ~#ethtool_stats_keys~0.base, 131 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(97, ~#ethtool_stats_keys~0.base, 132 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(100, ~#ethtool_stats_keys~0.base, 133 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(95, ~#ethtool_stats_keys~0.base, 134 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 135 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(115, ~#ethtool_stats_keys~0.base, 136 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(100, ~#ethtool_stats_keys~0.base, 137 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 138 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 139 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 140 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 141 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 142 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 143 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 144 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 145 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 146 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 147 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 148 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 149 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 150 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 151 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 152 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 153 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 154 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 155 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 156 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 157 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 158 + ~#ethtool_stats_keys~0.offset, 1);call write~init~int(0, ~#ethtool_stats_keys~0.base, 159 + ~#ethtool_stats_keys~0.offset, 1);~#options~0.base, ~#options~0.offset := 438, 0;call #Ultimate.allocInit(32, 438);call write~init~int(-1, ~#options~0.base, ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 4 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 8 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 12 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 16 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 20 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 24 + ~#options~0.offset, 4);call write~init~int(-1, ~#options~0.base, 28 + ~#options~0.offset, 4);~#full_duplex~0.base, ~#full_duplex~0.offset := 439, 0;call #Ultimate.allocInit(32, 439);call write~init~int(-1, ~#full_duplex~0.base, ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 4 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 8 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 12 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 16 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 20 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 24 + ~#full_duplex~0.offset, 4);call write~init~int(-1, ~#full_duplex~0.base, 28 + ~#full_duplex~0.offset, 4);~#hw_checksums~0.base, ~#hw_checksums~0.offset := 440, 0;call #Ultimate.allocInit(32, 440);call write~init~int(-1, ~#hw_checksums~0.base, ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 4 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 8 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 12 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 16 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 20 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 24 + ~#hw_checksums~0.offset, 4);call write~init~int(-1, ~#hw_checksums~0.base, 28 + ~#hw_checksums~0.offset, 4);~#flow_ctrl~0.base, ~#flow_ctrl~0.offset := 441, 0;call #Ultimate.allocInit(32, 441);call write~init~int(-1, ~#flow_ctrl~0.base, ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 4 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 8 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 12 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 16 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 20 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 24 + ~#flow_ctrl~0.offset, 4);call write~init~int(-1, ~#flow_ctrl~0.base, 28 + ~#flow_ctrl~0.offset, 4);~#enable_wol~0.base, ~#enable_wol~0.offset := 442, 0;call #Ultimate.allocInit(32, 442);call write~init~int(-1, ~#enable_wol~0.base, ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 4 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 8 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 12 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 16 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 20 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 24 + ~#enable_wol~0.offset, 4);call write~init~int(-1, ~#enable_wol~0.base, 28 + ~#enable_wol~0.offset, 4);~#use_mmio~0.base, ~#use_mmio~0.offset := 443, 0;call #Ultimate.allocInit(32, 443);call write~init~int(-1, ~#use_mmio~0.base, ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 4 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 8 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 12 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 16 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 20 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 24 + ~#use_mmio~0.offset, 4);call write~init~int(-1, ~#use_mmio~0.base, 28 + ~#use_mmio~0.offset, 4);~global_options~0 := -1;~global_full_duplex~0 := -1;~global_enable_wol~0 := -1;~global_use_mmio~0 := -1;~compaq_ioaddr~0 := 0;~compaq_irq~0 := 0;~compaq_device_id~0 := 22784;~compaq_net_device~0.base, ~compaq_net_device~0.offset := 0, 0;~vortex_cards_found~0 := 0;~#vortex_pm_ops~0.base, ~#vortex_pm_ops~0.offset := 444, 0;call #Ultimate.allocInit(184, 444);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 8 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_suspend.base, #funAddr~vortex_suspend.offset, ~#vortex_pm_ops~0.base, 16 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_resume.base, #funAddr~vortex_resume.offset, ~#vortex_pm_ops~0.base, 24 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_suspend.base, #funAddr~vortex_suspend.offset, ~#vortex_pm_ops~0.base, 32 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_resume.base, #funAddr~vortex_resume.offset, ~#vortex_pm_ops~0.base, 40 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_suspend.base, #funAddr~vortex_suspend.offset, ~#vortex_pm_ops~0.base, 48 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_resume.base, #funAddr~vortex_resume.offset, ~#vortex_pm_ops~0.base, 56 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 64 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 72 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 80 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 88 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 96 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 104 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 112 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 120 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 128 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 136 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 144 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 152 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 160 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 168 + ~#vortex_pm_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_pm_ops~0.base, 176 + ~#vortex_pm_ops~0.offset, 8);~#boomrang_netdev_ops~0.base, ~#boomrang_netdev_ops~0.offset := 445, 0;call #Ultimate.allocInit(472, 445);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 8 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_open.base, #funAddr~vortex_open.offset, ~#boomrang_netdev_ops~0.base, 16 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_close.base, #funAddr~vortex_close.offset, ~#boomrang_netdev_ops~0.base, 24 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~boomerang_start_xmit.base, #funAddr~boomerang_start_xmit.offset, ~#boomrang_netdev_ops~0.base, 32 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 40 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 48 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~set_rx_mode.base, #funAddr~set_rx_mode.offset, ~#boomrang_netdev_ops~0.base, 56 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset, ~#boomrang_netdev_ops~0.base, 64 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset, ~#boomrang_netdev_ops~0.base, 72 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_ioctl.base, #funAddr~vortex_ioctl.offset, ~#boomrang_netdev_ops~0.base, 80 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 88 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset, ~#boomrang_netdev_ops~0.base, 96 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 104 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_tx_timeout.base, #funAddr~vortex_tx_timeout.offset, ~#boomrang_netdev_ops~0.base, 112 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 120 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_stats.base, #funAddr~vortex_get_stats.offset, ~#boomrang_netdev_ops~0.base, 128 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 136 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 144 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~poll_vortex.base, #funAddr~poll_vortex.offset, ~#boomrang_netdev_ops~0.base, 152 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 160 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 168 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 176 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 184 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 192 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 200 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 208 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 216 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 224 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 232 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 240 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 248 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 256 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 264 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 272 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 280 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 288 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 296 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 304 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 312 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 320 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 328 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 336 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 344 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 352 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 360 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 368 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 376 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 384 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 392 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 400 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 408 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 416 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 424 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 432 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 440 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 448 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 456 + ~#boomrang_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#boomrang_netdev_ops~0.base, 464 + ~#boomrang_netdev_ops~0.offset, 8);~#vortex_netdev_ops~0.base, ~#vortex_netdev_ops~0.offset := 446, 0;call #Ultimate.allocInit(472, 446);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 8 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_open.base, #funAddr~vortex_open.offset, ~#vortex_netdev_ops~0.base, 16 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_close.base, #funAddr~vortex_close.offset, ~#vortex_netdev_ops~0.base, 24 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_start_xmit.base, #funAddr~vortex_start_xmit.offset, ~#vortex_netdev_ops~0.base, 32 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 40 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 48 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~set_rx_mode.base, #funAddr~set_rx_mode.offset, ~#vortex_netdev_ops~0.base, 56 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_mac_addr.base, #funAddr~eth_mac_addr.offset, ~#vortex_netdev_ops~0.base, 64 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_validate_addr.base, #funAddr~eth_validate_addr.offset, ~#vortex_netdev_ops~0.base, 72 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_ioctl.base, #funAddr~vortex_ioctl.offset, ~#vortex_netdev_ops~0.base, 80 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 88 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~eth_change_mtu.base, #funAddr~eth_change_mtu.offset, ~#vortex_netdev_ops~0.base, 96 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 104 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_tx_timeout.base, #funAddr~vortex_tx_timeout.offset, ~#vortex_netdev_ops~0.base, 112 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 120 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_stats.base, #funAddr~vortex_get_stats.offset, ~#vortex_netdev_ops~0.base, 128 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 136 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 144 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~poll_vortex.base, #funAddr~poll_vortex.offset, ~#vortex_netdev_ops~0.base, 152 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 160 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 168 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 176 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 184 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 192 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 200 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 208 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 216 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 224 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 232 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 240 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 248 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 256 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 264 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 272 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 280 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 288 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 296 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 304 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 312 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 320 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 328 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 336 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 344 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 352 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 360 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 368 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 376 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 384 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 392 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 400 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 408 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 416 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 424 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 432 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 440 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 448 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 456 + ~#vortex_netdev_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_netdev_ops~0.base, 464 + ~#vortex_netdev_ops~0.offset, 8);~#vortex_ethtool_ops~0.base, ~#vortex_ethtool_ops~0.offset := 447, 0;call #Ultimate.allocInit(368, 447);call write~init~$Pointer$(#funAddr~vortex_get_settings.base, #funAddr~vortex_get_settings.offset, ~#vortex_ethtool_ops~0.base, ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_set_settings.base, #funAddr~vortex_set_settings.offset, ~#vortex_ethtool_ops~0.base, 8 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_drvinfo.base, #funAddr~vortex_get_drvinfo.offset, ~#vortex_ethtool_ops~0.base, 16 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 24 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 32 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_wol.base, #funAddr~vortex_get_wol.offset, ~#vortex_ethtool_ops~0.base, 40 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_set_wol.base, #funAddr~vortex_set_wol.offset, ~#vortex_ethtool_ops~0.base, 48 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_msglevel.base, #funAddr~vortex_get_msglevel.offset, ~#vortex_ethtool_ops~0.base, 56 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_set_msglevel.base, #funAddr~vortex_set_msglevel.offset, ~#vortex_ethtool_ops~0.base, 64 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_nway_reset.base, #funAddr~vortex_nway_reset.offset, ~#vortex_ethtool_ops~0.base, 72 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~ethtool_op_get_link.base, #funAddr~ethtool_op_get_link.offset, ~#vortex_ethtool_ops~0.base, 80 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 88 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 96 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 104 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 112 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 120 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 128 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 136 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 144 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 152 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 160 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_strings.base, #funAddr~vortex_get_strings.offset, ~#vortex_ethtool_ops~0.base, 168 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 176 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_ethtool_stats.base, #funAddr~vortex_get_ethtool_stats.offset, ~#vortex_ethtool_ops~0.base, 184 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 192 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 200 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 208 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 216 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_get_sset_count.base, #funAddr~vortex_get_sset_count.offset, ~#vortex_ethtool_ops~0.base, 224 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 232 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 240 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 248 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 256 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 264 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 272 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 280 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 288 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 296 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 304 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 312 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 320 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~ethtool_op_get_ts_info.base, #funAddr~ethtool_op_get_ts_info.offset, ~#vortex_ethtool_ops~0.base, 328 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 336 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 344 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 352 + ~#vortex_ethtool_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_ethtool_ops~0.base, 360 + ~#vortex_ethtool_ops~0.offset, 8);~#vortex_driver~0.base, ~#vortex_driver~0.offset := 448, 0;call #Ultimate.allocInit(301, 448);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 8 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(344, 0, ~#vortex_driver~0.base, 16 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(~#vortex_pci_tbl~0.base, ~#vortex_pci_tbl~0.offset, ~#vortex_driver~0.base, 24 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_init_one.base, #funAddr~vortex_init_one.offset, ~#vortex_driver~0.base, 32 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~vortex_remove_one.base, #funAddr~vortex_remove_one.offset, ~#vortex_driver~0.base, 40 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 48 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 56 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 64 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 72 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 80 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 88 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 96 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 104 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 112 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 120 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 128 + ~#vortex_driver~0.offset, 8);call write~init~int(0, ~#vortex_driver~0.base, 136 + ~#vortex_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 137 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 145 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 153 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 161 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 169 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 177 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 185 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 193 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(~#vortex_pm_ops~0.base, ~#vortex_pm_ops~0.offset, ~#vortex_driver~0.base, 201 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 209 + ~#vortex_driver~0.offset, 8);call write~init~int(0, ~#vortex_driver~0.base, 217 + ~#vortex_driver~0.offset, 4);call write~init~int(0, ~#vortex_driver~0.base, 221 + ~#vortex_driver~0.offset, 4);call write~init~int(0, ~#vortex_driver~0.base, 225 + ~#vortex_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 229 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 237 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 245 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 253 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 261 + ~#vortex_driver~0.offset, 8);call write~init~int(0, ~#vortex_driver~0.base, 269 + ~#vortex_driver~0.offset, 4);call write~init~int(0, ~#vortex_driver~0.base, 273 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 285 + ~#vortex_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#vortex_driver~0.base, 293 + ~#vortex_driver~0.offset, 8);~vortex_have_pci~0 := 0;~vortex_have_eisa~0 := 0;~ldv_thread_0~0.identifier := 0;~ldv_thread_0~0.function.base, ~ldv_thread_0~0.function.offset := 0, 0;~ldv_thread_1~0.identifier := 0;~ldv_thread_1~0.function.base, ~ldv_thread_1~0.function.offset := 0, 0;~ldv_thread_16~0.identifier := 0;~ldv_thread_16~0.function.base, ~ldv_thread_16~0.function.offset := 0, 0;~ldv_thread_2~0.identifier := 0;~ldv_thread_2~0.function.base, ~ldv_thread_2~0.function.offset := 0, 0;~ldv_thread_3~0.identifier := 0;~ldv_thread_3~0.function.base, ~ldv_thread_3~0.function.offset := 0, 0;~ldv_thread_4~0.identifier := 0;~ldv_thread_4~0.function.base, ~ldv_thread_4~0.function.offset := 0, 0;~ldv_thread_5~0.identifier := 0;~ldv_thread_5~0.function.base, ~ldv_thread_5~0.function.offset := 0, 0;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_vortex_private~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_mii_lock_of_vortex_private~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1;~ldv_spin_window_lock_of_vortex_private~0 := 1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,330 INFO L290 TraceCheckUtils]: 1: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_ldv_initialize } true; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,330 INFO L290 TraceCheckUtils]: 2: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_entry_EMGentry_16 } true;ldv_entry_EMGentry_16_#in~arg0#1.base, ldv_entry_EMGentry_16_#in~arg0#1.offset := 0, 0;havoc ldv_entry_EMGentry_16_#t~ret1441#1, ldv_entry_EMGentry_16_#t~ret1442#1, ldv_entry_EMGentry_16_#t~ret1443#1, ldv_entry_EMGentry_16_#t~ret1444#1, ldv_entry_EMGentry_16_~arg0#1.base, ldv_entry_EMGentry_16_~arg0#1.offset, ldv_entry_EMGentry_16_~ldv_16_exit_vortex_cleanup_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_exit_vortex_cleanup_default~0#1.offset, ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.offset, ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1, ldv_entry_EMGentry_16_~tmp~85#1, ldv_entry_EMGentry_16_~tmp___0~45#1;ldv_entry_EMGentry_16_~arg0#1.base, ldv_entry_EMGentry_16_~arg0#1.offset := ldv_entry_EMGentry_16_#in~arg0#1.base, ldv_entry_EMGentry_16_#in~arg0#1.offset;havoc ldv_entry_EMGentry_16_~ldv_16_exit_vortex_cleanup_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_exit_vortex_cleanup_default~0#1.offset;havoc ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.offset;havoc ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1;havoc ldv_entry_EMGentry_16_~tmp~85#1;havoc ldv_entry_EMGentry_16_~tmp___0~45#1;assume { :begin_inline_ldv_EMGentry_init_vortex_init_16_9 } true;ldv_EMGentry_init_vortex_init_16_9_#in~arg0#1.base, ldv_EMGentry_init_vortex_init_16_9_#in~arg0#1.offset := ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.base, ldv_entry_EMGentry_16_~ldv_16_init_vortex_init_default~0#1.offset;havoc ldv_EMGentry_init_vortex_init_16_9_#res#1;havoc ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1, ldv_EMGentry_init_vortex_init_16_9_~arg0#1.base, ldv_EMGentry_init_vortex_init_16_9_~arg0#1.offset, ldv_EMGentry_init_vortex_init_16_9_~tmp~76#1;ldv_EMGentry_init_vortex_init_16_9_~arg0#1.base, ldv_EMGentry_init_vortex_init_16_9_~arg0#1.offset := ldv_EMGentry_init_vortex_init_16_9_#in~arg0#1.base, ldv_EMGentry_init_vortex_init_16_9_#in~arg0#1.offset;havoc ldv_EMGentry_init_vortex_init_16_9_~tmp~76#1;assume { :begin_inline_vortex_init } true;havoc vortex_init_#res#1;havoc vortex_init_#t~ret1411#1, vortex_init_#t~ret1412#1, vortex_init_#t~ite1413#1, vortex_init_~pci_rc~0#1, vortex_init_~eisa_rc~0#1;havoc vortex_init_~pci_rc~0#1;havoc vortex_init_~eisa_rc~0#1;assume { :begin_inline_ldv___pci_register_driver_138 } true;ldv___pci_register_driver_138_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg1#1.offset, ldv___pci_register_driver_138_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg2#1.offset, ldv___pci_register_driver_138_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg3#1.offset := ~#vortex_driver~0.base, ~#vortex_driver~0.offset, ~#__this_module~0.base, ~#__this_module~0.offset, 345, 0;havoc ldv___pci_register_driver_138_#res#1;havoc ldv___pci_register_driver_138_#t~ret1641#1, ldv___pci_register_driver_138_#t~ret1642#1, ldv___pci_register_driver_138_~ldv_func_arg1#1.base, ldv___pci_register_driver_138_~ldv_func_arg1#1.offset, ldv___pci_register_driver_138_~ldv_func_arg2#1.base, ldv___pci_register_driver_138_~ldv_func_arg2#1.offset, ldv___pci_register_driver_138_~ldv_func_arg3#1.base, ldv___pci_register_driver_138_~ldv_func_arg3#1.offset, ldv___pci_register_driver_138_~ldv_func_res~9#1, ldv___pci_register_driver_138_~tmp~115#1, ldv___pci_register_driver_138_~tmp___0~60#1;ldv___pci_register_driver_138_~ldv_func_arg1#1.base, ldv___pci_register_driver_138_~ldv_func_arg1#1.offset := ldv___pci_register_driver_138_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg1#1.offset;ldv___pci_register_driver_138_~ldv_func_arg2#1.base, ldv___pci_register_driver_138_~ldv_func_arg2#1.offset := ldv___pci_register_driver_138_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg2#1.offset;ldv___pci_register_driver_138_~ldv_func_arg3#1.base, ldv___pci_register_driver_138_~ldv_func_arg3#1.offset := ldv___pci_register_driver_138_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_138_#in~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_138_~ldv_func_res~9#1;havoc ldv___pci_register_driver_138_~tmp~115#1;havoc ldv___pci_register_driver_138_~tmp___0~60#1;assume { :begin_inline___pci_register_driver } true;__pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset, __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset, __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset := ldv___pci_register_driver_138_~ldv_func_arg1#1.base, ldv___pci_register_driver_138_~ldv_func_arg1#1.offset, ldv___pci_register_driver_138_~ldv_func_arg2#1.base, ldv___pci_register_driver_138_~ldv_func_arg2#1.offset, ldv___pci_register_driver_138_~ldv_func_arg3#1.base, ldv___pci_register_driver_138_~ldv_func_arg3#1.offset;havoc __pci_register_driver_#res#1;havoc __pci_register_driver_#t~nondet1759#1, __pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset, __pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset, __pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset;__pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset := __pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset;__pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset := __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset;__pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset := __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset;assume -2147483648 <= __pci_register_driver_#t~nondet1759#1 && __pci_register_driver_#t~nondet1759#1 <= 2147483647;__pci_register_driver_#res#1 := __pci_register_driver_#t~nondet1759#1;havoc __pci_register_driver_#t~nondet1759#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,331 INFO L290 TraceCheckUtils]: 3: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv___pci_register_driver_138_#t~ret1641#1 := __pci_register_driver_#res#1;assume { :end_inline___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_138_#t~ret1641#1 && ldv___pci_register_driver_138_#t~ret1641#1 <= 2147483647;ldv___pci_register_driver_138_~tmp~115#1 := ldv___pci_register_driver_138_#t~ret1641#1;havoc ldv___pci_register_driver_138_#t~ret1641#1;ldv___pci_register_driver_138_~ldv_func_res~9#1 := ldv___pci_register_driver_138_~tmp~115#1;assume { :begin_inline_ldv___pci_register_driver } true;ldv___pci_register_driver_#in~arg0#1, ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset, ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset, ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset := ldv___pci_register_driver_138_~ldv_func_res~9#1, ldv___pci_register_driver_138_~ldv_func_arg1#1.base, ldv___pci_register_driver_138_~ldv_func_arg1#1.offset, ldv___pci_register_driver_138_~ldv_func_arg2#1.base, ldv___pci_register_driver_138_~ldv_func_arg2#1.offset, ldv___pci_register_driver_138_~ldv_func_arg3#1.base, ldv___pci_register_driver_138_~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_#res#1;havoc ldv___pci_register_driver_#t~ret1418#1, ldv___pci_register_driver_~arg0#1, ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset, ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset, ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset, ldv___pci_register_driver_~ldv_15_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_15_pci_driver_pci_driver~0#1.offset, ldv___pci_register_driver_~tmp~77#1;ldv___pci_register_driver_~arg0#1 := ldv___pci_register_driver_#in~arg0#1;ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset := ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset;ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset := ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset;ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset := ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset;havoc ldv___pci_register_driver_~ldv_15_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_15_pci_driver_pci_driver~0#1.offset;havoc ldv___pci_register_driver_~tmp~77#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,331 INFO L272 TraceCheckUtils]: 4: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv___pci_register_driver_#t~ret1418#1 := ldv_undef_int(); {21501#true} is VALID [2022-02-20 23:13:10,332 INFO L290 TraceCheckUtils]: 5: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,332 INFO L290 TraceCheckUtils]: 6: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,333 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7987#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,334 INFO L290 TraceCheckUtils]: 8: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume -2147483648 <= ldv___pci_register_driver_#t~ret1418#1 && ldv___pci_register_driver_#t~ret1418#1 <= 2147483647;ldv___pci_register_driver_~tmp~77#1 := ldv___pci_register_driver_#t~ret1418#1;havoc ldv___pci_register_driver_#t~ret1418#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,337 INFO L290 TraceCheckUtils]: 9: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume !(0 != ldv___pci_register_driver_~tmp~77#1); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,337 INFO L272 TraceCheckUtils]: 10: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_assume((if 0 != ldv___pci_register_driver_~arg0#1 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,337 INFO L290 TraceCheckUtils]: 11: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,337 INFO L290 TraceCheckUtils]: 12: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,338 INFO L290 TraceCheckUtils]: 13: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,338 INFO L284 TraceCheckUtils]: 14: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8049#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,339 INFO L290 TraceCheckUtils]: 15: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv___pci_register_driver_#res#1 := ldv___pci_register_driver_~arg0#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,339 INFO L290 TraceCheckUtils]: 16: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv___pci_register_driver_138_#t~ret1642#1 := ldv___pci_register_driver_#res#1;assume { :end_inline_ldv___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_138_#t~ret1642#1 && ldv___pci_register_driver_138_#t~ret1642#1 <= 2147483647;ldv___pci_register_driver_138_~tmp___0~60#1 := ldv___pci_register_driver_138_#t~ret1642#1;havoc ldv___pci_register_driver_138_#t~ret1642#1;ldv___pci_register_driver_138_#res#1 := ldv___pci_register_driver_138_~tmp___0~60#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,339 INFO L290 TraceCheckUtils]: 17: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} vortex_init_#t~ret1411#1 := ldv___pci_register_driver_138_#res#1;assume { :end_inline_ldv___pci_register_driver_138 } true;assume -2147483648 <= vortex_init_#t~ret1411#1 && vortex_init_#t~ret1411#1 <= 2147483647;vortex_init_~pci_rc~0#1 := vortex_init_#t~ret1411#1;havoc vortex_init_#t~ret1411#1;assume { :begin_inline_vortex_eisa_init } true;havoc vortex_eisa_init_#res#1;havoc vortex_eisa_init_#t~ret345#1.base, vortex_eisa_init_#t~ret345#1.offset, vortex_eisa_init_#t~ret346#1, vortex_eisa_init_~eisa_found~0#1, vortex_eisa_init_~orig_cards_found~0#1, vortex_eisa_init_~tmp~39#1, vortex_eisa_init_~tmp___0~14#1.base, vortex_eisa_init_~tmp___0~14#1.offset;havoc vortex_eisa_init_~eisa_found~0#1;havoc vortex_eisa_init_~orig_cards_found~0#1;havoc vortex_eisa_init_~tmp~39#1;havoc vortex_eisa_init_~tmp___0~14#1.base, vortex_eisa_init_~tmp___0~14#1.offset;vortex_eisa_init_~eisa_found~0#1 := 0;vortex_eisa_init_~orig_cards_found~0#1 := ~vortex_cards_found~0; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,340 INFO L290 TraceCheckUtils]: 18: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume !(0 != ~compaq_ioaddr~0); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,340 INFO L290 TraceCheckUtils]: 19: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} vortex_eisa_init_#res#1 := ~vortex_cards_found~0 - vortex_eisa_init_~orig_cards_found~0#1 + vortex_eisa_init_~eisa_found~0#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,341 INFO L290 TraceCheckUtils]: 20: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} vortex_init_#t~ret1412#1 := vortex_eisa_init_#res#1;assume { :end_inline_vortex_eisa_init } true;assume -2147483648 <= vortex_init_#t~ret1412#1 && vortex_init_#t~ret1412#1 <= 2147483647;vortex_init_~eisa_rc~0#1 := vortex_init_#t~ret1412#1;havoc vortex_init_#t~ret1412#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,341 INFO L290 TraceCheckUtils]: 21: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume 0 == vortex_init_~pci_rc~0#1;~vortex_have_pci~0 := 1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,342 INFO L290 TraceCheckUtils]: 22: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume vortex_init_~eisa_rc~0#1 > 0;~vortex_have_eisa~0 := 1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,342 INFO L290 TraceCheckUtils]: 23: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume 0 != ~vortex_have_pci~0 + ~vortex_have_eisa~0;vortex_init_#t~ite1413#1 := 0; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,342 INFO L290 TraceCheckUtils]: 24: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} vortex_init_#res#1 := vortex_init_#t~ite1413#1;havoc vortex_init_#t~ite1413#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,343 INFO L290 TraceCheckUtils]: 25: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1 := vortex_init_#res#1;assume { :end_inline_vortex_init } true;assume -2147483648 <= ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1 && ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1 <= 2147483647;ldv_EMGentry_init_vortex_init_16_9_~tmp~76#1 := ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1;havoc ldv_EMGentry_init_vortex_init_16_9_#t~ret1417#1;ldv_EMGentry_init_vortex_init_16_9_#res#1 := ldv_EMGentry_init_vortex_init_16_9_~tmp~76#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,343 INFO L290 TraceCheckUtils]: 26: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv_entry_EMGentry_16_#t~ret1441#1 := ldv_EMGentry_init_vortex_init_16_9_#res#1;assume { :end_inline_ldv_EMGentry_init_vortex_init_16_9 } true;assume -2147483648 <= ldv_entry_EMGentry_16_#t~ret1441#1 && ldv_entry_EMGentry_16_#t~ret1441#1 <= 2147483647;ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1 := ldv_entry_EMGentry_16_#t~ret1441#1;havoc ldv_entry_EMGentry_16_#t~ret1441#1;assume { :begin_inline_ldv_post_init } true;ldv_post_init_#in~init_ret_val#1 := ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1;havoc ldv_post_init_#res#1;havoc ldv_post_init_#t~ret1654#1, ldv_post_init_~init_ret_val#1, ldv_post_init_~tmp~121#1;ldv_post_init_~init_ret_val#1 := ldv_post_init_#in~init_ret_val#1;havoc ldv_post_init_~tmp~121#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,343 INFO L272 TraceCheckUtils]: 27: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_post_init_#t~ret1654#1 := ldv_filter_positive_int(ldv_post_init_~init_ret_val#1); {21501#true} is VALID [2022-02-20 23:13:10,343 INFO L290 TraceCheckUtils]: 28: Hoare triple {21501#true} ~val := #in~val; {21501#true} is VALID [2022-02-20 23:13:10,344 INFO L272 TraceCheckUtils]: 29: Hoare triple {21501#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,344 INFO L290 TraceCheckUtils]: 30: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,344 INFO L290 TraceCheckUtils]: 31: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,344 INFO L290 TraceCheckUtils]: 32: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,344 INFO L284 TraceCheckUtils]: 33: Hoare quadruple {21501#true} {21501#true} #7811#return; {21501#true} is VALID [2022-02-20 23:13:10,344 INFO L290 TraceCheckUtils]: 34: Hoare triple {21501#true} #res := ~val; {21501#true} is VALID [2022-02-20 23:13:10,344 INFO L290 TraceCheckUtils]: 35: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,345 INFO L284 TraceCheckUtils]: 36: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8055#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,345 INFO L290 TraceCheckUtils]: 37: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume -2147483648 <= ldv_post_init_#t~ret1654#1 && ldv_post_init_#t~ret1654#1 <= 2147483647;ldv_post_init_~tmp~121#1 := ldv_post_init_#t~ret1654#1;havoc ldv_post_init_#t~ret1654#1;ldv_post_init_#res#1 := ldv_post_init_~tmp~121#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,346 INFO L290 TraceCheckUtils]: 38: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv_entry_EMGentry_16_#t~ret1442#1 := ldv_post_init_#res#1;assume { :end_inline_ldv_post_init } true;assume -2147483648 <= ldv_entry_EMGentry_16_#t~ret1442#1 && ldv_entry_EMGentry_16_#t~ret1442#1 <= 2147483647;ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1 := ldv_entry_EMGentry_16_#t~ret1442#1;havoc ldv_entry_EMGentry_16_#t~ret1442#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,346 INFO L272 TraceCheckUtils]: 39: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_entry_EMGentry_16_#t~ret1443#1 := ldv_undef_int(); {21501#true} is VALID [2022-02-20 23:13:10,346 INFO L290 TraceCheckUtils]: 40: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,346 INFO L290 TraceCheckUtils]: 41: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,347 INFO L284 TraceCheckUtils]: 42: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8057#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,347 INFO L290 TraceCheckUtils]: 43: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume -2147483648 <= ldv_entry_EMGentry_16_#t~ret1443#1 && ldv_entry_EMGentry_16_#t~ret1443#1 <= 2147483647;ldv_entry_EMGentry_16_~tmp___0~45#1 := ldv_entry_EMGentry_16_#t~ret1443#1;havoc ldv_entry_EMGentry_16_#t~ret1443#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,348 INFO L290 TraceCheckUtils]: 44: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume !(0 != ldv_entry_EMGentry_16_~tmp___0~45#1); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,348 INFO L272 TraceCheckUtils]: 45: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_assume((if 0 == ldv_entry_EMGentry_16_~ldv_16_ret_default~0#1 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,348 INFO L290 TraceCheckUtils]: 46: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,348 INFO L290 TraceCheckUtils]: 47: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,348 INFO L290 TraceCheckUtils]: 48: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,349 INFO L284 TraceCheckUtils]: 49: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8065#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,349 INFO L272 TraceCheckUtils]: 50: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_entry_EMGentry_16_#t~ret1444#1 := ldv_undef_int(); {21501#true} is VALID [2022-02-20 23:13:10,349 INFO L290 TraceCheckUtils]: 51: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,349 INFO L290 TraceCheckUtils]: 52: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,349 INFO L284 TraceCheckUtils]: 53: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8067#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,350 INFO L290 TraceCheckUtils]: 54: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume -2147483648 <= ldv_entry_EMGentry_16_#t~ret1444#1 && ldv_entry_EMGentry_16_#t~ret1444#1 <= 2147483647;ldv_entry_EMGentry_16_~tmp~85#1 := ldv_entry_EMGentry_16_#t~ret1444#1;havoc ldv_entry_EMGentry_16_#t~ret1444#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,350 INFO L290 TraceCheckUtils]: 55: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume 0 != ldv_entry_EMGentry_16_~tmp~85#1;assume { :begin_inline_ldv_dispatch_register_platform_instance_15_16_5 } true;havoc ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.base, ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.offset, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.base, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.offset, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.base, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.offset;havoc ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.base, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.offset;havoc ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.base, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.offset; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,351 INFO L272 TraceCheckUtils]: 56: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.base, ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.offset := ldv_xmalloc(4); {21591#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 23:13:10,351 INFO L290 TraceCheckUtils]: 57: Hoare triple {21591#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~127.base, ~tmp~127.offset;havoc ~tmp___0~64;call #t~malloc1675.base, #t~malloc1675.offset := #Ultimate.allocOnHeap(~size);~tmp~127.base, ~tmp~127.offset := #t~malloc1675.base, #t~malloc1675.offset;havoc #t~malloc1675.base, #t~malloc1675.offset;~res~3.base, ~res~3.offset := ~tmp~127.base, ~tmp~127.offset; {21501#true} is VALID [2022-02-20 23:13:10,351 INFO L272 TraceCheckUtils]: 58: Hoare triple {21501#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,351 INFO L290 TraceCheckUtils]: 59: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,351 INFO L290 TraceCheckUtils]: 60: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,352 INFO L290 TraceCheckUtils]: 61: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,352 INFO L284 TraceCheckUtils]: 62: Hoare quadruple {21501#true} {21501#true} #7545#return; {21501#true} is VALID [2022-02-20 23:13:10,352 INFO L272 TraceCheckUtils]: 63: Hoare triple {21501#true} call #t~ret1676 := ldv_is_err(~res~3.base, ~res~3.offset); {21501#true} is VALID [2022-02-20 23:13:10,352 INFO L290 TraceCheckUtils]: 64: Hoare triple {21501#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {21501#true} is VALID [2022-02-20 23:13:10,352 INFO L290 TraceCheckUtils]: 65: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,352 INFO L284 TraceCheckUtils]: 66: Hoare quadruple {21501#true} {21501#true} #7547#return; {21501#true} is VALID [2022-02-20 23:13:10,352 INFO L290 TraceCheckUtils]: 67: Hoare triple {21501#true} assume -9223372036854775808 <= #t~ret1676 && #t~ret1676 <= 9223372036854775807;~tmp___0~64 := #t~ret1676;havoc #t~ret1676; {21501#true} is VALID [2022-02-20 23:13:10,353 INFO L272 TraceCheckUtils]: 68: Hoare triple {21501#true} call ldv_assume((if 0 == ~tmp___0~64 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,353 INFO L290 TraceCheckUtils]: 69: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,353 INFO L290 TraceCheckUtils]: 70: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,353 INFO L290 TraceCheckUtils]: 71: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,353 INFO L284 TraceCheckUtils]: 72: Hoare quadruple {21501#true} {21501#true} #7549#return; {21501#true} is VALID [2022-02-20 23:13:10,353 INFO L290 TraceCheckUtils]: 73: Hoare triple {21501#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {21501#true} is VALID [2022-02-20 23:13:10,353 INFO L290 TraceCheckUtils]: 74: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,354 INFO L284 TraceCheckUtils]: 75: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8069#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,354 INFO L290 TraceCheckUtils]: 76: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.base, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.offset := ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.base, ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.offset;havoc ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.base, ldv_dispatch_register_platform_instance_15_16_5_#t~ret1426#1.offset;ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.base, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.offset := ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.base, ldv_dispatch_register_platform_instance_15_16_5_~tmp~84#1.offset;assume { :begin_inline_ldv_pm_platform_instance_4 } true;ldv_pm_platform_instance_4_#in~arg0#1.base, ldv_pm_platform_instance_4_#in~arg0#1.offset := ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.base, ldv_dispatch_register_platform_instance_15_16_5_~cf_arg_4~0#1.offset;havoc ldv_pm_platform_instance_4_#t~ret1545#1, ldv_pm_platform_instance_4_#t~ret1546#1.base, ldv_pm_platform_instance_4_#t~ret1546#1.offset, ldv_pm_platform_instance_4_#t~mem1547#1.base, ldv_pm_platform_instance_4_#t~mem1547#1.offset, ldv_pm_platform_instance_4_#t~mem1548#1.base, ldv_pm_platform_instance_4_#t~mem1548#1.offset, ldv_pm_platform_instance_4_#t~ret1549#1, ldv_pm_platform_instance_4_#t~ret1550#1, ldv_pm_platform_instance_4_#t~ret1551#1, ldv_pm_platform_instance_4_#t~ret1552#1, ldv_pm_platform_instance_4_#t~ret1553#1.base, ldv_pm_platform_instance_4_#t~ret1553#1.offset, ldv_pm_platform_instance_4_#t~mem1554#1.base, ldv_pm_platform_instance_4_#t~mem1554#1.offset, ldv_pm_platform_instance_4_#t~mem1555#1.base, ldv_pm_platform_instance_4_#t~mem1555#1.offset, ldv_pm_platform_instance_4_~arg0#1.base, ldv_pm_platform_instance_4_~arg0#1.offset, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.base, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.offset, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.offset, ldv_pm_platform_instance_4_~ldv_4_ldv_param_3_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_3_0_default~0#1.offset, ldv_pm_platform_instance_4_~ldv_4_probed_default~0#1, ldv_pm_platform_instance_4_~tmp~95#1.base, ldv_pm_platform_instance_4_~tmp~95#1.offset, ldv_pm_platform_instance_4_~tmp___0~48#1, ldv_pm_platform_instance_4_~tmp___1~31#1, ldv_pm_platform_instance_4_~tmp___2~21#1, ldv_pm_platform_instance_4_~tmp___3~19#1.base, ldv_pm_platform_instance_4_~tmp___3~19#1.offset;ldv_pm_platform_instance_4_~arg0#1.base, ldv_pm_platform_instance_4_~arg0#1.offset := ldv_pm_platform_instance_4_#in~arg0#1.base, ldv_pm_platform_instance_4_#in~arg0#1.offset;havoc ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.base, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.offset;havoc ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.offset;havoc ldv_pm_platform_instance_4_~ldv_4_ldv_param_3_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_3_0_default~0#1.offset;havoc ldv_pm_platform_instance_4_~ldv_4_probed_default~0#1;havoc ldv_pm_platform_instance_4_~tmp~95#1.base, ldv_pm_platform_instance_4_~tmp~95#1.offset;havoc ldv_pm_platform_instance_4_~tmp___0~48#1;havoc ldv_pm_platform_instance_4_~tmp___1~31#1;havoc ldv_pm_platform_instance_4_~tmp___2~21#1;havoc ldv_pm_platform_instance_4_~tmp___3~19#1.base, ldv_pm_platform_instance_4_~tmp___3~19#1.offset;ldv_pm_platform_instance_4_~ldv_4_probed_default~0#1 := 1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,355 INFO L272 TraceCheckUtils]: 77: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_pm_platform_instance_4_#t~ret1545#1 := ldv_undef_int(); {21501#true} is VALID [2022-02-20 23:13:10,355 INFO L290 TraceCheckUtils]: 78: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,355 INFO L290 TraceCheckUtils]: 79: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,355 INFO L284 TraceCheckUtils]: 80: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8071#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,356 INFO L290 TraceCheckUtils]: 81: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume -2147483648 <= ldv_pm_platform_instance_4_#t~ret1545#1 && ldv_pm_platform_instance_4_#t~ret1545#1 <= 2147483647;ldv_pm_platform_instance_4_~tmp___1~31#1 := ldv_pm_platform_instance_4_#t~ret1545#1;havoc ldv_pm_platform_instance_4_#t~ret1545#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,356 INFO L290 TraceCheckUtils]: 82: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume 0 != ldv_pm_platform_instance_4_~tmp___1~31#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,357 INFO L272 TraceCheckUtils]: 83: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_pm_platform_instance_4_#t~ret1546#1.base, ldv_pm_platform_instance_4_#t~ret1546#1.offset := ldv_xmalloc(1432); {21591#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 23:13:10,357 INFO L290 TraceCheckUtils]: 84: Hoare triple {21591#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~127.base, ~tmp~127.offset;havoc ~tmp___0~64;call #t~malloc1675.base, #t~malloc1675.offset := #Ultimate.allocOnHeap(~size);~tmp~127.base, ~tmp~127.offset := #t~malloc1675.base, #t~malloc1675.offset;havoc #t~malloc1675.base, #t~malloc1675.offset;~res~3.base, ~res~3.offset := ~tmp~127.base, ~tmp~127.offset; {21501#true} is VALID [2022-02-20 23:13:10,357 INFO L272 TraceCheckUtils]: 85: Hoare triple {21501#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,357 INFO L290 TraceCheckUtils]: 86: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,357 INFO L290 TraceCheckUtils]: 87: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,358 INFO L290 TraceCheckUtils]: 88: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,358 INFO L284 TraceCheckUtils]: 89: Hoare quadruple {21501#true} {21501#true} #7545#return; {21501#true} is VALID [2022-02-20 23:13:10,358 INFO L272 TraceCheckUtils]: 90: Hoare triple {21501#true} call #t~ret1676 := ldv_is_err(~res~3.base, ~res~3.offset); {21501#true} is VALID [2022-02-20 23:13:10,358 INFO L290 TraceCheckUtils]: 91: Hoare triple {21501#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {21501#true} is VALID [2022-02-20 23:13:10,358 INFO L290 TraceCheckUtils]: 92: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,358 INFO L284 TraceCheckUtils]: 93: Hoare quadruple {21501#true} {21501#true} #7547#return; {21501#true} is VALID [2022-02-20 23:13:10,358 INFO L290 TraceCheckUtils]: 94: Hoare triple {21501#true} assume -9223372036854775808 <= #t~ret1676 && #t~ret1676 <= 9223372036854775807;~tmp___0~64 := #t~ret1676;havoc #t~ret1676; {21501#true} is VALID [2022-02-20 23:13:10,358 INFO L272 TraceCheckUtils]: 95: Hoare triple {21501#true} call ldv_assume((if 0 == ~tmp___0~64 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,359 INFO L290 TraceCheckUtils]: 96: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,359 INFO L290 TraceCheckUtils]: 97: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,359 INFO L290 TraceCheckUtils]: 98: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,359 INFO L284 TraceCheckUtils]: 99: Hoare quadruple {21501#true} {21501#true} #7549#return; {21501#true} is VALID [2022-02-20 23:13:10,359 INFO L290 TraceCheckUtils]: 100: Hoare triple {21501#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {21501#true} is VALID [2022-02-20 23:13:10,359 INFO L290 TraceCheckUtils]: 101: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,360 INFO L284 TraceCheckUtils]: 102: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8073#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,360 INFO L290 TraceCheckUtils]: 103: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv_pm_platform_instance_4_~tmp~95#1.base, ldv_pm_platform_instance_4_~tmp~95#1.offset := ldv_pm_platform_instance_4_#t~ret1546#1.base, ldv_pm_platform_instance_4_#t~ret1546#1.offset;havoc ldv_pm_platform_instance_4_#t~ret1546#1.base, ldv_pm_platform_instance_4_#t~ret1546#1.offset;ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.offset := ldv_pm_platform_instance_4_~tmp~95#1.base, ldv_pm_platform_instance_4_~tmp~95#1.offset; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,360 INFO L272 TraceCheckUtils]: 104: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_pre_probe(); {21501#true} is VALID [2022-02-20 23:13:10,361 INFO L290 TraceCheckUtils]: 105: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,361 INFO L284 TraceCheckUtils]: 106: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #8075#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,361 INFO L290 TraceCheckUtils]: 107: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_pm_platform_instance_4_#t~mem1547#1.base, ldv_pm_platform_instance_4_#t~mem1547#1.offset := read~$Pointer$(ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.base, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.offset, 8); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,362 INFO L290 TraceCheckUtils]: 108: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume 0 != (ldv_pm_platform_instance_4_#t~mem1547#1.base + ldv_pm_platform_instance_4_#t~mem1547#1.offset) % 18446744073709551616;havoc ldv_pm_platform_instance_4_#t~mem1547#1.base, ldv_pm_platform_instance_4_#t~mem1547#1.offset;call ldv_pm_platform_instance_4_#t~mem1548#1.base, ldv_pm_platform_instance_4_#t~mem1548#1.offset := read~$Pointer$(ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.base, ldv_pm_platform_instance_4_~ldv_4_container_platform_driver~0#1.offset, 8);assume { :begin_inline_ldv_platform_instance_probe_4_14 } true;ldv_platform_instance_probe_4_14_#in~arg0#1.base, ldv_platform_instance_probe_4_14_#in~arg0#1.offset, ldv_platform_instance_probe_4_14_#in~arg1#1.base, ldv_platform_instance_probe_4_14_#in~arg1#1.offset := ldv_pm_platform_instance_4_#t~mem1548#1.base, ldv_pm_platform_instance_4_#t~mem1548#1.offset, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.base, ldv_pm_platform_instance_4_~ldv_4_ldv_param_14_0_default~0#1.offset;havoc ldv_platform_instance_probe_4_14_#res#1;havoc ldv_platform_instance_probe_4_14_#t~ret1503#1, ldv_platform_instance_probe_4_14_~arg0#1.base, ldv_platform_instance_probe_4_14_~arg0#1.offset, ldv_platform_instance_probe_4_14_~arg1#1.base, ldv_platform_instance_probe_4_14_~arg1#1.offset, ldv_platform_instance_probe_4_14_~tmp~94#1;ldv_platform_instance_probe_4_14_~arg0#1.base, ldv_platform_instance_probe_4_14_~arg0#1.offset := ldv_platform_instance_probe_4_14_#in~arg0#1.base, ldv_platform_instance_probe_4_14_#in~arg0#1.offset;ldv_platform_instance_probe_4_14_~arg1#1.base, ldv_platform_instance_probe_4_14_~arg1#1.offset := ldv_platform_instance_probe_4_14_#in~arg1#1.base, ldv_platform_instance_probe_4_14_#in~arg1#1.offset;havoc ldv_platform_instance_probe_4_14_~tmp~94#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,363 INFO L272 TraceCheckUtils]: 109: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_platform_instance_probe_4_14_#t~ret1503#1 := ##fun~$Pointer$~TO~int(ldv_platform_instance_probe_4_14_~arg1#1.base, ldv_platform_instance_probe_4_14_~arg1#1.offset, ldv_platform_instance_probe_4_14_~arg0#1.base, ldv_platform_instance_probe_4_14_~arg0#1.offset); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,363 INFO L290 TraceCheckUtils]: 110: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #~1543.base, #~1543.offset := #in~1543.base, #in~1543.offset; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,364 INFO L290 TraceCheckUtils]: 111: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume !(#in~#fp.base == #funAddr~vortex_nway_reset.base && #in~#fp.offset == #funAddr~vortex_nway_reset.offset); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,364 INFO L290 TraceCheckUtils]: 112: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume !(#in~#fp.base == #funAddr~eth_validate_addr.base && #in~#fp.offset == #funAddr~eth_validate_addr.offset); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,364 INFO L290 TraceCheckUtils]: 113: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume !(#in~#fp.base == #funAddr~vortex_close.base && #in~#fp.offset == #funAddr~vortex_close.offset); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,365 INFO L290 TraceCheckUtils]: 114: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume #in~#fp.base == #funAddr~vortex_open.base && #in~#fp.offset == #funAddr~vortex_open.offset; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,365 INFO L272 TraceCheckUtils]: 115: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call #t~ret1805 := vortex_open(#~1543.base, #~1543.offset); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,366 INFO L290 TraceCheckUtils]: 116: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~vp~6#1.base, ~vp~6#1.offset;havoc ~tmp~45#1.base, ~tmp~45#1.offset;havoc ~i~3#1;havoc ~retval~1#1;call ~#descriptor~2#1.base, ~#descriptor~2#1.offset := #Ultimate.allocOnStack(40);havoc ~tmp___0~19#1;havoc ~skb~1#1.base, ~skb~1#1.offset;havoc ~__mptr~4#1.base, ~__mptr~4#1.offset;havoc ~tmp___1~12#1.base, ~tmp___1~12#1.offset;havoc ~tmp___2~5#1.base, ~tmp___2~5#1.offset;havoc ~tmp___3~4#1;havoc ~j~0#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,366 INFO L272 TraceCheckUtils]: 117: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call #t~ret654#1.base, #t~ret654#1.offset := netdev_priv(~dev#1.base, ~dev#1.offset); {21501#true} is VALID [2022-02-20 23:13:10,366 INFO L290 TraceCheckUtils]: 118: Hoare triple {21501#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {21501#true} is VALID [2022-02-20 23:13:10,366 INFO L290 TraceCheckUtils]: 119: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,367 INFO L284 TraceCheckUtils]: 120: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7851#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,367 INFO L290 TraceCheckUtils]: 121: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ~tmp~45#1.base, ~tmp~45#1.offset := #t~ret654#1.base, #t~ret654#1.offset;havoc #t~ret654#1.base, #t~ret654#1.offset;~vp~6#1.base, ~vp~6#1.offset := ~tmp~45#1.base, ~tmp~45#1.offset;call #t~mem655#1 := read~int(~dev#1.base, 64 + ~dev#1.offset, 4);call #t~mem656#1 := read~int(~vp~6#1.base, 797 + ~vp~6#1.offset, 1); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,368 INFO L290 TraceCheckUtils]: 122: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume 0 != #t~mem656#1 % 256 % 4294967296;#t~ite657#1.base, #t~ite657#1.offset := #funAddr~boomerang_interrupt.base, #funAddr~boomerang_interrupt.offset; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,369 INFO L290 TraceCheckUtils]: 123: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume { :begin_inline_ldv_request_irq_102 } true;ldv_request_irq_102_#in~irq#1, ldv_request_irq_102_#in~handler#1.base, ldv_request_irq_102_#in~handler#1.offset, ldv_request_irq_102_#in~flags#1, ldv_request_irq_102_#in~name#1.base, ldv_request_irq_102_#in~name#1.offset, ldv_request_irq_102_#in~dev#1.base, ldv_request_irq_102_#in~dev#1.offset := #t~mem655#1, #t~ite657#1.base, #t~ite657#1.offset, 128, ~dev#1.base, ~dev#1.offset, ~dev#1.base, ~dev#1.offset;havoc ldv_request_irq_102_#res#1;havoc ldv_request_irq_102_#t~ret1626#1, ldv_request_irq_102_#t~ret1627#1, ldv_request_irq_102_~irq#1, ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset, ldv_request_irq_102_~flags#1, ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset, ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset, ldv_request_irq_102_~ldv_func_res~2#1, ldv_request_irq_102_~tmp~107#1, ldv_request_irq_102_~tmp___0~53#1;ldv_request_irq_102_~irq#1 := ldv_request_irq_102_#in~irq#1;ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset := ldv_request_irq_102_#in~handler#1.base, ldv_request_irq_102_#in~handler#1.offset;ldv_request_irq_102_~flags#1 := ldv_request_irq_102_#in~flags#1;ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset := ldv_request_irq_102_#in~name#1.base, ldv_request_irq_102_#in~name#1.offset;ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset := ldv_request_irq_102_#in~dev#1.base, ldv_request_irq_102_#in~dev#1.offset;havoc ldv_request_irq_102_~ldv_func_res~2#1;havoc ldv_request_irq_102_~tmp~107#1;havoc ldv_request_irq_102_~tmp___0~53#1;assume { :begin_inline_request_irq } true;request_irq_#in~irq#1, request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset, request_irq_#in~flags#1, request_irq_#in~name#1.base, request_irq_#in~name#1.offset, request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset := ldv_request_irq_102_~irq#1, ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset, ldv_request_irq_102_~flags#1, ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset, ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset;havoc request_irq_#res#1;havoc request_irq_#t~ret289#1, request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset, request_irq_~tmp~32#1;request_irq_~irq#1 := request_irq_#in~irq#1;request_irq_~handler#1.base, request_irq_~handler#1.offset := request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset;request_irq_~flags#1 := request_irq_#in~flags#1;request_irq_~name#1.base, request_irq_~name#1.offset := request_irq_#in~name#1.base, request_irq_#in~name#1.offset;request_irq_~dev#1.base, request_irq_~dev#1.offset := request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset;havoc request_irq_~tmp~32#1;assume { :begin_inline_request_threaded_irq } true;request_threaded_irq_#in~arg0#1, request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset, request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset, request_threaded_irq_#in~arg3#1, request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset, request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset := request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, 0, 0, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset;havoc request_threaded_irq_#res#1;havoc request_threaded_irq_#t~nondet1792#1, request_threaded_irq_~arg0#1, request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset, request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset, request_threaded_irq_~arg3#1, request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset, request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset;request_threaded_irq_~arg0#1 := request_threaded_irq_#in~arg0#1;request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset := request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset;request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset := request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset;request_threaded_irq_~arg3#1 := request_threaded_irq_#in~arg3#1;request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset := request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset;request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset := request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset;assume -2147483648 <= request_threaded_irq_#t~nondet1792#1 && request_threaded_irq_#t~nondet1792#1 <= 2147483647;request_threaded_irq_#res#1 := request_threaded_irq_#t~nondet1792#1;havoc request_threaded_irq_#t~nondet1792#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,369 INFO L290 TraceCheckUtils]: 124: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} request_irq_#t~ret289#1 := request_threaded_irq_#res#1;assume { :end_inline_request_threaded_irq } true;assume -2147483648 <= request_irq_#t~ret289#1 && request_irq_#t~ret289#1 <= 2147483647;request_irq_~tmp~32#1 := request_irq_#t~ret289#1;havoc request_irq_#t~ret289#1;request_irq_#res#1 := request_irq_~tmp~32#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,370 INFO L290 TraceCheckUtils]: 125: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv_request_irq_102_#t~ret1626#1 := request_irq_#res#1;assume { :end_inline_request_irq } true;assume -2147483648 <= ldv_request_irq_102_#t~ret1626#1 && ldv_request_irq_102_#t~ret1626#1 <= 2147483647;ldv_request_irq_102_~tmp~107#1 := ldv_request_irq_102_#t~ret1626#1;havoc ldv_request_irq_102_#t~ret1626#1;ldv_request_irq_102_~ldv_func_res~2#1 := ldv_request_irq_102_~tmp~107#1;assume { :begin_inline_ldv_request_irq } true;ldv_request_irq_#in~arg0#1, ldv_request_irq_#in~arg1#1, ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset, ldv_request_irq_#in~arg3#1, ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset, ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset := ldv_request_irq_102_~ldv_func_res~2#1, ldv_request_irq_102_~irq#1, ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset, ldv_request_irq_102_~flags#1, ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset, ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset;havoc ldv_request_irq_#res#1;havoc ldv_request_irq_#t~ret1608#1, ldv_request_irq_~arg0#1, ldv_request_irq_~arg1#1, ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset, ldv_request_irq_~arg3#1, ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset, ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset, ldv_request_irq_~ldv_12_callback_handler~0#1.base, ldv_request_irq_~ldv_12_callback_handler~0#1.offset, ldv_request_irq_~ldv_12_data_data~0#1.base, ldv_request_irq_~ldv_12_data_data~0#1.offset, ldv_request_irq_~ldv_12_line_line~0#1, ldv_request_irq_~ldv_12_thread_thread~0#1.base, ldv_request_irq_~ldv_12_thread_thread~0#1.offset, ldv_request_irq_~tmp~99#1;ldv_request_irq_~arg0#1 := ldv_request_irq_#in~arg0#1;ldv_request_irq_~arg1#1 := ldv_request_irq_#in~arg1#1;ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset := ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset;ldv_request_irq_~arg3#1 := ldv_request_irq_#in~arg3#1;ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset := ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset;ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset := ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset;havoc ldv_request_irq_~ldv_12_callback_handler~0#1.base, ldv_request_irq_~ldv_12_callback_handler~0#1.offset;havoc ldv_request_irq_~ldv_12_data_data~0#1.base, ldv_request_irq_~ldv_12_data_data~0#1.offset;havoc ldv_request_irq_~ldv_12_line_line~0#1;havoc ldv_request_irq_~ldv_12_thread_thread~0#1.base, ldv_request_irq_~ldv_12_thread_thread~0#1.offset;havoc ldv_request_irq_~tmp~99#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,370 INFO L272 TraceCheckUtils]: 126: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_request_irq_#t~ret1608#1 := ldv_undef_int(); {21501#true} is VALID [2022-02-20 23:13:10,370 INFO L290 TraceCheckUtils]: 127: Hoare triple {21501#true} havoc ~tmp~129;assume -2147483648 <= #t~nondet1679 && #t~nondet1679 <= 2147483647;~tmp~129 := #t~nondet1679;havoc #t~nondet1679;#res := ~tmp~129; {21501#true} is VALID [2022-02-20 23:13:10,370 INFO L290 TraceCheckUtils]: 128: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,370 INFO L284 TraceCheckUtils]: 129: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7853#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,371 INFO L290 TraceCheckUtils]: 130: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume -2147483648 <= ldv_request_irq_#t~ret1608#1 && ldv_request_irq_#t~ret1608#1 <= 2147483647;ldv_request_irq_~tmp~99#1 := ldv_request_irq_#t~ret1608#1;havoc ldv_request_irq_#t~ret1608#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,373 INFO L290 TraceCheckUtils]: 131: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume !(0 != ldv_request_irq_~tmp~99#1); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,373 INFO L272 TraceCheckUtils]: 132: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_assume((if 0 != ldv_request_irq_~arg0#1 then 1 else 0)); {21501#true} is VALID [2022-02-20 23:13:10,373 INFO L290 TraceCheckUtils]: 133: Hoare triple {21501#true} ~expression := #in~expression; {21501#true} is VALID [2022-02-20 23:13:10,373 INFO L290 TraceCheckUtils]: 134: Hoare triple {21501#true} assume !(0 == ~expression); {21501#true} is VALID [2022-02-20 23:13:10,373 INFO L290 TraceCheckUtils]: 135: Hoare triple {21501#true} assume true; {21501#true} is VALID [2022-02-20 23:13:10,379 INFO L284 TraceCheckUtils]: 136: Hoare quadruple {21501#true} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7875#return; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,379 INFO L290 TraceCheckUtils]: 137: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv_request_irq_#res#1 := ldv_request_irq_~arg0#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,379 INFO L290 TraceCheckUtils]: 138: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ldv_request_irq_102_#t~ret1627#1 := ldv_request_irq_#res#1;assume { :end_inline_ldv_request_irq } true;assume -2147483648 <= ldv_request_irq_102_#t~ret1627#1 && ldv_request_irq_102_#t~ret1627#1 <= 2147483647;ldv_request_irq_102_~tmp___0~53#1 := ldv_request_irq_102_#t~ret1627#1;havoc ldv_request_irq_102_#t~ret1627#1;ldv_request_irq_102_#res#1 := ldv_request_irq_102_~tmp___0~53#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,380 INFO L290 TraceCheckUtils]: 139: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #t~ret658#1 := ldv_request_irq_102_#res#1;assume { :end_inline_ldv_request_irq_102 } true;assume -2147483648 <= #t~ret658#1 && #t~ret658#1 <= 2147483647;~retval~1#1 := #t~ret658#1;havoc #t~mem655#1;havoc #t~mem656#1;havoc #t~ite657#1.base, #t~ite657#1.offset;havoc #t~ret658#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,380 INFO L290 TraceCheckUtils]: 140: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume !(0 != ~retval~1#1);call #t~mem661#1 := read~int(~vp~6#1.base, 797 + ~vp~6#1.offset, 1); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,380 INFO L290 TraceCheckUtils]: 141: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume 0 != #t~mem661#1 % 256 % 4294967296;havoc #t~mem661#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,381 INFO L290 TraceCheckUtils]: 142: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume !(~debug~0 > 2); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,381 INFO L290 TraceCheckUtils]: 143: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ~i~3#1 := 0; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,382 INFO L290 TraceCheckUtils]: 144: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume ~i~3#1 <= 31; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,383 INFO L290 TraceCheckUtils]: 145: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call #t~mem665#1.base, #t~mem665#1.offset := read~$Pointer$(~vp~6#1.base, ~vp~6#1.offset, 8);call #t~mem666#1 := read~int(~vp~6#1.base, 16 + ~vp~6#1.offset, 8);call write~int(#t~mem666#1 + 16 * (1 + ~i~3#1), #t~mem665#1.base, #t~mem665#1.offset + 16 * (if ~i~3#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then ~i~3#1 % 18446744073709551616 % 18446744073709551616 else ~i~3#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616), 4);havoc #t~mem665#1.base, #t~mem665#1.offset;havoc #t~mem666#1;call #t~mem667#1.base, #t~mem667#1.offset := read~$Pointer$(~vp~6#1.base, ~vp~6#1.offset, 8);call write~int(0, #t~mem667#1.base, 4 + (#t~mem667#1.offset + 16 * (if ~i~3#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then ~i~3#1 % 18446744073709551616 % 18446744073709551616 else ~i~3#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616)), 4);havoc #t~mem667#1.base, #t~mem667#1.offset;call #t~mem668#1.base, #t~mem668#1.offset := read~$Pointer$(~vp~6#1.base, ~vp~6#1.offset, 8);call write~int(2147485184, #t~mem668#1.base, 12 + (#t~mem668#1.offset + 16 * (if ~i~3#1 % 18446744073709551616 % 18446744073709551616 <= 9223372036854775807 then ~i~3#1 % 18446744073709551616 % 18446744073709551616 else ~i~3#1 % 18446744073709551616 % 18446744073709551616 - 18446744073709551616)), 4);havoc #t~mem668#1.base, #t~mem668#1.offset;assume { :begin_inline_ldv___netdev_alloc_skb_103 } true;ldv___netdev_alloc_skb_103_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_103_#in~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_103_#in~ldv_func_arg2#1, ldv___netdev_alloc_skb_103_#in~flags#1 := ~dev#1.base, ~dev#1.offset, 1536, 208;havoc ldv___netdev_alloc_skb_103_#res#1.base, ldv___netdev_alloc_skb_103_#res#1.offset;havoc ldv___netdev_alloc_skb_103_#t~ret1628#1.base, ldv___netdev_alloc_skb_103_#t~ret1628#1.offset, ldv___netdev_alloc_skb_103_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_103_~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_103_~ldv_func_arg2#1, ldv___netdev_alloc_skb_103_~flags#1, ldv___netdev_alloc_skb_103_~tmp~108#1.base, ldv___netdev_alloc_skb_103_~tmp~108#1.offset;ldv___netdev_alloc_skb_103_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_103_~ldv_func_arg1#1.offset := ldv___netdev_alloc_skb_103_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_103_#in~ldv_func_arg1#1.offset;ldv___netdev_alloc_skb_103_~ldv_func_arg2#1 := ldv___netdev_alloc_skb_103_#in~ldv_func_arg2#1;ldv___netdev_alloc_skb_103_~flags#1 := ldv___netdev_alloc_skb_103_#in~flags#1;havoc ldv___netdev_alloc_skb_103_~tmp~108#1.base, ldv___netdev_alloc_skb_103_~tmp~108#1.offset; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,383 INFO L272 TraceCheckUtils]: 146: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call ldv_check_alloc_flags(ldv___netdev_alloc_skb_103_~flags#1); {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,384 INFO L290 TraceCheckUtils]: 147: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} ~flags#1 := #in~flags#1;havoc ~tmp~116#1; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,384 INFO L290 TraceCheckUtils]: 148: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} assume 32 != ~flags#1 % 4294967296 && 0 != ~flags#1 % 4294967296; {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} is VALID [2022-02-20 23:13:10,384 INFO L272 TraceCheckUtils]: 149: Hoare triple {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} call #t~ret1643#1 := ldv_exclusive_spin_is_locked(); {21501#true} is VALID [2022-02-20 23:13:10,385 INFO L290 TraceCheckUtils]: 150: Hoare triple {21501#true} assume !(2 == ~ldv_spin__xmit_lock_of_netdev_queue~0); {21614#(or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)))} is VALID [2022-02-20 23:13:10,385 INFO L290 TraceCheckUtils]: 151: Hoare triple {21614#(or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)))} assume 2 == ~ldv_spin_addr_list_lock_of_net_device~0;#res := 1; {21615#(and (or (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)) (<= 2 ~ldv_spin_addr_list_lock_of_net_device~0)) (or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (and (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)) (<= ~ldv_spin_addr_list_lock_of_net_device~0 2))))} is VALID [2022-02-20 23:13:10,386 INFO L290 TraceCheckUtils]: 152: Hoare triple {21615#(and (or (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)) (<= 2 ~ldv_spin_addr_list_lock_of_net_device~0)) (or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (and (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)) (<= ~ldv_spin_addr_list_lock_of_net_device~0 2))))} assume true; {21615#(and (or (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)) (<= 2 ~ldv_spin_addr_list_lock_of_net_device~0)) (or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (and (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)) (<= ~ldv_spin_addr_list_lock_of_net_device~0 2))))} is VALID [2022-02-20 23:13:10,386 INFO L284 TraceCheckUtils]: 153: Hoare quadruple {21615#(and (or (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)) (<= 2 ~ldv_spin_addr_list_lock_of_net_device~0)) (or (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 1) (and (not (<= ~ldv_spin__xmit_lock_of_netdev_queue~0 2)) (<= ~ldv_spin_addr_list_lock_of_net_device~0 2))))} {21503#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 ~ldv_spin_addr_list_lock_of_net_device~0)} #7101#return; {21502#false} is VALID [2022-02-20 23:13:10,386 INFO L290 TraceCheckUtils]: 154: Hoare triple {21502#false} assume -2147483648 <= #t~ret1643#1 && #t~ret1643#1 <= 2147483647;~tmp~116#1 := #t~ret1643#1;havoc #t~ret1643#1;assume { :begin_inline_ldv_assert_linux_alloc_spinlock__wrong_flags } true;ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1 := (if 0 == ~tmp~116#1 then 1 else 0);havoc ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1;ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1 := ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1; {21502#false} is VALID [2022-02-20 23:13:10,386 INFO L290 TraceCheckUtils]: 155: Hoare triple {21502#false} assume 0 == ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1; {21502#false} is VALID [2022-02-20 23:13:10,387 INFO L290 TraceCheckUtils]: 156: Hoare triple {21502#false} assume !false; {21502#false} is VALID [2022-02-20 23:13:10,387 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2022-02-20 23:13:10,387 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 23:13:10,387 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387672438] [2022-02-20 23:13:10,388 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1387672438] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 23:13:10,388 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 23:13:10,388 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-02-20 23:13:10,388 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988128574] [2022-02-20 23:13:10,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 23:13:10,389 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 5 states have internal predecessors, (77), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) Word has length 157 [2022-02-20 23:13:10,390 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 23:13:10,390 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 5 states have internal predecessors, (77), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18) [2022-02-20 23:13:10,533 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 116 edges. 116 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 23:13:10,533 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-02-20 23:13:10,533 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 23:13:10,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-02-20 23:13:10,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-02-20 23:13:10,534 INFO L87 Difference]: Start difference. First operand 2907 states and 4158 transitions. Second operand has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 5 states have internal predecessors, (77), 2 states have call successors, (21), 3 states have call predecessors, (21), 2 states have return successors, (18), 3 states have call predecessors, (18), 2 states have call successors, (18)