./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 11d3d0800a0e0d53b4d0190c9a443eccbd843952940cf36579a7110b5d32d86b --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 22:54:34,154 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 22:54:34,156 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 22:54:34,174 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 22:54:34,175 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 22:54:34,175 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 22:54:34,176 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 22:54:34,178 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 22:54:34,179 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 22:54:34,180 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 22:54:34,180 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 22:54:34,181 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 22:54:34,182 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 22:54:34,182 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 22:54:34,183 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 22:54:34,184 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 22:54:34,185 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 22:54:34,185 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 22:54:34,187 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 22:54:34,188 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 22:54:34,189 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 22:54:34,190 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 22:54:34,191 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 22:54:34,192 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 22:54:34,194 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 22:54:34,194 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 22:54:34,194 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 22:54:34,195 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 22:54:34,195 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 22:54:34,196 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 22:54:34,196 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 22:54:34,196 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 22:54:34,197 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 22:54:34,197 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 22:54:34,198 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 22:54:34,198 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 22:54:34,199 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 22:54:34,199 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 22:54:34,199 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 22:54:34,200 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 22:54:34,200 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 22:54:34,201 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 22:54:34,214 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 22:54:34,215 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 22:54:34,215 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 22:54:34,215 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 22:54:34,216 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 22:54:34,216 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 22:54:34,216 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 22:54:34,216 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 22:54:34,217 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 22:54:34,217 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 22:54:34,217 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 22:54:34,217 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 22:54:34,217 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 22:54:34,218 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 22:54:34,218 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 22:54:34,218 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 22:54:34,218 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 22:54:34,218 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 22:54:34,218 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 22:54:34,219 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 22:54:34,219 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 22:54:34,219 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:54:34,219 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 22:54:34,219 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 22:54:34,219 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 22:54:34,220 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 22:54:34,220 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 22:54:34,220 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 22:54:34,220 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 22:54:34,220 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 22:54:34,220 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 11d3d0800a0e0d53b4d0190c9a443eccbd843952940cf36579a7110b5d32d86b [2022-02-20 22:54:34,369 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 22:54:34,385 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 22:54:34,387 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 22:54:34,387 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 22:54:34,388 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 22:54:34,389 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i [2022-02-20 22:54:34,423 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3175718a/21b0d690adfb49f49e311fafb9049d14/FLAG959228cab [2022-02-20 22:54:35,032 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 22:54:35,032 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i [2022-02-20 22:54:35,073 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3175718a/21b0d690adfb49f49e311fafb9049d14/FLAG959228cab [2022-02-20 22:54:35,461 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3175718a/21b0d690adfb49f49e311fafb9049d14 [2022-02-20 22:54:35,463 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 22:54:35,465 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 22:54:35,469 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 22:54:35,469 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 22:54:35,473 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 22:54:35,474 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:54:35" (1/1) ... [2022-02-20 22:54:35,475 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@caed5ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:35, skipping insertion in model container [2022-02-20 22:54:35,475 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:54:35" (1/1) ... [2022-02-20 22:54:35,479 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 22:54:35,553 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 22:54:36,981 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i[323389,323402] [2022-02-20 22:54:36,983 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i[323534,323547] [2022-02-20 22:54:37,006 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:54:37,035 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 22:54:37,294 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i[323389,323402] [2022-02-20 22:54:37,295 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i[323534,323547] [2022-02-20 22:54:37,299 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:54:37,382 INFO L208 MainTranslator]: Completed translation [2022-02-20 22:54:37,382 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37 WrapperNode [2022-02-20 22:54:37,383 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 22:54:37,383 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 22:54:37,384 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 22:54:37,384 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 22:54:37,389 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,487 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,632 INFO L137 Inliner]: procedures = 379, calls = 2098, calls flagged for inlining = 146, calls inlined = 127, statements flattened = 4220 [2022-02-20 22:54:37,633 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 22:54:37,633 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 22:54:37,634 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 22:54:37,634 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 22:54:37,640 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,640 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,663 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,663 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,751 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,771 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,791 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,815 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 22:54:37,816 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 22:54:37,817 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 22:54:37,817 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 22:54:37,818 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (1/1) ... [2022-02-20 22:54:37,825 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:54:37,832 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:54:37,856 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 22:54:37,871 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 22:54:37,896 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_97 [2022-02-20 22:54:37,896 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_97 [2022-02-20 22:54:37,896 INFO L130 BoogieDeclarations]: Found specification of procedure ResetChip [2022-02-20 22:54:37,896 INFO L138 BoogieDeclarations]: Found implementation of procedure ResetChip [2022-02-20 22:54:37,896 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2022-02-20 22:54:37,896 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2022-02-20 22:54:37,896 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 22:54:37,897 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 22:54:37,897 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2022-02-20 22:54:37,897 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2022-02-20 22:54:37,897 INFO L130 BoogieDeclarations]: Found specification of procedure RxCurCount [2022-02-20 22:54:37,897 INFO L138 BoogieDeclarations]: Found implementation of procedure RxCurCount [2022-02-20 22:54:37,898 INFO L130 BoogieDeclarations]: Found specification of procedure irda_device_txqueue_empty [2022-02-20 22:54:37,898 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_device_txqueue_empty [2022-02-20 22:54:37,898 INFO L130 BoogieDeclarations]: Found specification of procedure irda_setup_dma [2022-02-20 22:54:37,898 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_setup_dma [2022-02-20 22:54:37,898 INFO L130 BoogieDeclarations]: Found specification of procedure netif_wake_queue [2022-02-20 22:54:37,898 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_wake_queue [2022-02-20 22:54:37,898 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 22:54:37,898 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 22:54:37,898 INFO L130 BoogieDeclarations]: Found specification of procedure pci_read_config_byte [2022-02-20 22:54:37,899 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_read_config_byte [2022-02-20 22:54:37,899 INFO L130 BoogieDeclarations]: Found specification of procedure Sdelay [2022-02-20 22:54:37,899 INFO L138 BoogieDeclarations]: Found implementation of procedure Sdelay [2022-02-20 22:54:37,899 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2022-02-20 22:54:37,899 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2022-02-20 22:54:37,899 INFO L130 BoogieDeclarations]: Found specification of procedure CheckRegBit [2022-02-20 22:54:37,899 INFO L138 BoogieDeclarations]: Found implementation of procedure CheckRegBit [2022-02-20 22:54:37,899 INFO L130 BoogieDeclarations]: Found specification of procedure via_remove_one [2022-02-20 22:54:37,900 INFO L138 BoogieDeclarations]: Found implementation of procedure via_remove_one [2022-02-20 22:54:37,900 INFO L130 BoogieDeclarations]: Found specification of procedure SetSIR [2022-02-20 22:54:37,900 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSIR [2022-02-20 22:54:37,900 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_speed [2022-02-20 22:54:37,900 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_speed [2022-02-20 22:54:37,900 INFO L130 BoogieDeclarations]: Found specification of procedure netif_stop_queue [2022-02-20 22:54:37,900 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_stop_queue [2022-02-20 22:54:37,901 INFO L130 BoogieDeclarations]: Found specification of procedure SetMaxRxPacketSize [2022-02-20 22:54:37,901 INFO L138 BoogieDeclarations]: Found implementation of procedure SetMaxRxPacketSize [2022-02-20 22:54:37,901 INFO L130 BoogieDeclarations]: Found specification of procedure dma_zalloc_coherent [2022-02-20 22:54:37,901 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_zalloc_coherent [2022-02-20 22:54:37,901 INFO L130 BoogieDeclarations]: Found specification of procedure GetRecvByte [2022-02-20 22:54:37,901 INFO L138 BoogieDeclarations]: Found implementation of procedure GetRecvByte [2022-02-20 22:54:37,901 INFO L130 BoogieDeclarations]: Found specification of procedure consume_skb [2022-02-20 22:54:37,902 INFO L138 BoogieDeclarations]: Found implementation of procedure consume_skb [2022-02-20 22:54:37,902 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 22:54:37,902 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 22:54:37,902 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_xmalloc [2022-02-20 22:54:37,902 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_xmalloc [2022-02-20 22:54:37,902 INFO L130 BoogieDeclarations]: Found specification of procedure SetPulseWidth [2022-02-20 22:54:37,902 INFO L138 BoogieDeclarations]: Found implementation of procedure SetPulseWidth [2022-02-20 22:54:37,903 INFO L130 BoogieDeclarations]: Found specification of procedure Tdelay [2022-02-20 22:54:37,903 INFO L138 BoogieDeclarations]: Found implementation of procedure Tdelay [2022-02-20 22:54:37,903 INFO L130 BoogieDeclarations]: Found specification of procedure netif_rx [2022-02-20 22:54:37,903 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_rx [2022-02-20 22:54:37,903 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_is_err [2022-02-20 22:54:37,904 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_is_err [2022-02-20 22:54:37,904 INFO L130 BoogieDeclarations]: Found specification of procedure hwreset [2022-02-20 22:54:37,904 INFO L138 BoogieDeclarations]: Found implementation of procedure hwreset [2022-02-20 22:54:37,905 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 22:54:37,905 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 22:54:37,905 INFO L130 BoogieDeclarations]: Found specification of procedure ClkTx [2022-02-20 22:54:37,905 INFO L138 BoogieDeclarations]: Found implementation of procedure ClkTx [2022-02-20 22:54:37,905 INFO L130 BoogieDeclarations]: Found specification of procedure WriteLPCReg [2022-02-20 22:54:37,905 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteLPCReg [2022-02-20 22:54:37,906 INFO L130 BoogieDeclarations]: Found specification of procedure capable [2022-02-20 22:54:37,906 INFO L138 BoogieDeclarations]: Found implementation of procedure capable [2022-02-20 22:54:37,906 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 22:54:37,906 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 22:54:37,906 INFO L130 BoogieDeclarations]: Found specification of procedure pci_write_config_byte [2022-02-20 22:54:37,906 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_write_config_byte [2022-02-20 22:54:37,906 INFO L130 BoogieDeclarations]: Found specification of procedure CommonInit [2022-02-20 22:54:37,906 INFO L138 BoogieDeclarations]: Found implementation of procedure CommonInit [2022-02-20 22:54:37,906 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_priv [2022-02-20 22:54:37,907 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_priv [2022-02-20 22:54:37,907 INFO L130 BoogieDeclarations]: Found specification of procedure outb [2022-02-20 22:54:37,907 INFO L138 BoogieDeclarations]: Found implementation of procedure outb [2022-02-20 22:54:37,907 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_get_tx_queue [2022-02-20 22:54:37,907 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_get_tx_queue [2022-02-20 22:54:37,908 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_positive_int [2022-02-20 22:54:37,908 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_positive_int [2022-02-20 22:54:37,908 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq [2022-02-20 22:54:37,908 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq [2022-02-20 22:54:37,908 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_dongle_speed [2022-02-20 22:54:37,908 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_dongle_speed [2022-02-20 22:54:37,908 INFO L130 BoogieDeclarations]: Found specification of procedure ReadLPCReg [2022-02-20 22:54:37,908 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadLPCReg [2022-02-20 22:54:37,908 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2022-02-20 22:54:37,909 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2022-02-20 22:54:37,909 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2022-02-20 22:54:37,909 INFO L130 BoogieDeclarations]: Found specification of procedure free_dma [2022-02-20 22:54:37,909 INFO L138 BoogieDeclarations]: Found implementation of procedure free_dma [2022-02-20 22:54:37,909 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_lock_of_via_ircc_cb [2022-02-20 22:54:37,909 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_lock_of_via_ircc_cb [2022-02-20 22:54:37,910 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_receive [2022-02-20 22:54:37,910 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_receive [2022-02-20 22:54:37,910 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2022-02-20 22:54:37,910 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assume [2022-02-20 22:54:37,910 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assume [2022-02-20 22:54:37,911 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_xmit [2022-02-20 22:54:37,911 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_xmit [2022-02-20 22:54:37,911 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reserve [2022-02-20 22:54:37,911 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reserve [2022-02-20 22:54:37,911 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_close [2022-02-20 22:54:37,911 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_close [2022-02-20 22:54:37,911 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 22:54:37,911 INFO L130 BoogieDeclarations]: Found specification of procedure dma_free_attrs [2022-02-20 22:54:37,911 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_free_attrs [2022-02-20 22:54:37,912 INFO L130 BoogieDeclarations]: Found specification of procedure netif_tx_start_queue [2022-02-20 22:54:37,912 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_tx_start_queue [2022-02-20 22:54:37,912 INFO L130 BoogieDeclarations]: Found specification of procedure free_netdev [2022-02-20 22:54:37,912 INFO L138 BoogieDeclarations]: Found implementation of procedure free_netdev [2022-02-20 22:54:37,912 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2022-02-20 22:54:37,912 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2022-02-20 22:54:37,912 INFO L130 BoogieDeclarations]: Found specification of procedure CkRxRecv [2022-02-20 22:54:37,913 INFO L138 BoogieDeclarations]: Found implementation of procedure CkRxRecv [2022-02-20 22:54:37,913 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2022-02-20 22:54:37,913 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2022-02-20 22:54:37,914 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_err_code [2022-02-20 22:54:37,915 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_err_code [2022-02-20 22:54:37,915 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_alloc_flags [2022-02-20 22:54:37,915 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_alloc_flags [2022-02-20 22:54:37,916 INFO L130 BoogieDeclarations]: Found specification of procedure irda_get_next_speed [2022-02-20 22:54:37,917 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_get_next_speed [2022-02-20 22:54:37,917 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2022-02-20 22:54:37,917 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2022-02-20 22:54:37,917 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 22:54:37,917 INFO L130 BoogieDeclarations]: Found specification of procedure net_ratelimit [2022-02-20 22:54:37,921 INFO L138 BoogieDeclarations]: Found implementation of procedure net_ratelimit [2022-02-20 22:54:37,922 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendByte [2022-02-20 22:54:37,922 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendByte [2022-02-20 22:54:37,922 INFO L130 BoogieDeclarations]: Found specification of procedure dev_alloc_skb [2022-02-20 22:54:37,922 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_alloc_skb [2022-02-20 22:54:37,922 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2022-02-20 22:54:37,922 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2022-02-20 22:54:37,922 INFO L130 BoogieDeclarations]: Found specification of procedure ReadReg [2022-02-20 22:54:37,922 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadReg [2022-02-20 22:54:37,922 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_open [2022-02-20 22:54:37,923 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_open [2022-02-20 22:54:37,923 INFO L130 BoogieDeclarations]: Found specification of procedure WriteRegBit [2022-02-20 22:54:37,923 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteRegBit [2022-02-20 22:54:37,923 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 22:54:37,923 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Indx [2022-02-20 22:54:37,923 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Indx [2022-02-20 22:54:37,923 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_lock_of_via_ircc_cb [2022-02-20 22:54:37,923 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_lock_of_via_ircc_cb [2022-02-20 22:54:37,923 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 22:54:37,923 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_int [2022-02-20 22:54:37,924 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_int [2022-02-20 22:54:37,924 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2022-02-20 22:54:37,924 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2022-02-20 22:54:37,924 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-02-20 22:54:37,924 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 22:54:37,924 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 22:54:37,924 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~int [2022-02-20 22:54:37,924 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~int [2022-02-20 22:54:37,924 INFO L130 BoogieDeclarations]: Found specification of procedure WriteReg [2022-02-20 22:54:37,924 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteReg [2022-02-20 22:54:37,925 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendPreambleCount [2022-02-20 22:54:37,925 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendPreambleCount [2022-02-20 22:54:37,925 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_exclusive_spin_is_locked [2022-02-20 22:54:37,925 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_exclusive_spin_is_locked [2022-02-20 22:54:37,925 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assert [2022-02-20 22:54:37,925 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assert [2022-02-20 22:54:37,925 INFO L130 BoogieDeclarations]: Found specification of procedure InitCard [2022-02-20 22:54:37,925 INFO L138 BoogieDeclarations]: Found implementation of procedure InitCard [2022-02-20 22:54:37,925 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free [2022-02-20 22:54:37,925 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free [2022-02-20 22:54:37,925 INFO L130 BoogieDeclarations]: Found specification of procedure SetTimer [2022-02-20 22:54:37,926 INFO L138 BoogieDeclarations]: Found implementation of procedure SetTimer [2022-02-20 22:54:37,926 INFO L130 BoogieDeclarations]: Found specification of procedure ActClk [2022-02-20 22:54:37,926 INFO L138 BoogieDeclarations]: Found implementation of procedure ActClk [2022-02-20 22:54:37,926 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_spin_lock [2022-02-20 22:54:37,926 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_spin_lock [2022-02-20 22:54:37,926 INFO L130 BoogieDeclarations]: Found specification of procedure warn_slowpath_null [2022-02-20 22:54:37,926 INFO L138 BoogieDeclarations]: Found implementation of procedure warn_slowpath_null [2022-02-20 22:54:37,926 INFO L130 BoogieDeclarations]: Found specification of procedure SetBaudRate [2022-02-20 22:54:37,926 INFO L138 BoogieDeclarations]: Found implementation of procedure SetBaudRate [2022-02-20 22:54:37,926 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Byte [2022-02-20 22:54:37,927 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Byte [2022-02-20 22:54:37,927 INFO L130 BoogieDeclarations]: Found specification of procedure skb_put [2022-02-20 22:54:37,927 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_put [2022-02-20 22:54:37,927 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_netdev [2022-02-20 22:54:37,927 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_netdev [2022-02-20 22:54:37,927 INFO L130 BoogieDeclarations]: Found specification of procedure request_dma [2022-02-20 22:54:37,927 INFO L138 BoogieDeclarations]: Found implementation of procedure request_dma [2022-02-20 22:54:37,927 INFO L130 BoogieDeclarations]: Found specification of procedure inb [2022-02-20 22:54:37,927 INFO L138 BoogieDeclarations]: Found implementation of procedure inb [2022-02-20 22:54:37,927 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 22:54:37,928 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reset_mac_header [2022-02-20 22:54:37,928 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reset_mac_header [2022-02-20 22:54:37,928 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_open [2022-02-20 22:54:37,929 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_open [2022-02-20 22:54:37,929 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2022-02-20 22:54:37,929 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2022-02-20 22:54:37,929 INFO L130 BoogieDeclarations]: Found specification of procedure skb_copy_to_linear_data [2022-02-20 22:54:37,929 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_copy_to_linear_data [2022-02-20 22:54:37,929 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 22:54:37,930 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 22:54:38,493 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 22:54:38,495 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 22:54:38,661 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 22:54:41,788 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 22:54:41,802 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 22:54:41,803 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-02-20 22:54:41,805 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:54:41 BoogieIcfgContainer [2022-02-20 22:54:41,805 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 22:54:41,806 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 22:54:41,807 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 22:54:41,809 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 22:54:41,809 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 10:54:35" (1/3) ... [2022-02-20 22:54:41,809 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4104bfa9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:54:41, skipping insertion in model container [2022-02-20 22:54:41,810 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:54:37" (2/3) ... [2022-02-20 22:54:41,810 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4104bfa9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:54:41, skipping insertion in model container [2022-02-20 22:54:41,810 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:54:41" (3/3) ... [2022-02-20 22:54:41,811 INFO L111 eAbstractionObserver]: Analyzing ICFG linux-3.14_linux-alloc-spinlock_drivers-net-irda-via-ircc.cil.i [2022-02-20 22:54:41,814 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 22:54:41,814 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-02-20 22:54:41,848 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 22:54:41,852 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 22:54:41,852 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-02-20 22:54:41,932 INFO L276 IsEmpty]: Start isEmpty. Operand has 1890 states, 1157 states have (on average 1.2947277441659464) internal successors, (1498), 1188 states have internal predecessors, (1498), 641 states have call successors, (641), 91 states have call predecessors, (641), 90 states have return successors, (638), 626 states have call predecessors, (638), 638 states have call successors, (638) [2022-02-20 22:54:41,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 302 [2022-02-20 22:54:41,955 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:54:41,956 INFO L514 BasicCegarLoop]: trace histogram [15, 15, 15, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:54:41,956 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_check_alloc_flagsErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:54:41,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:54:41,961 INFO L85 PathProgramCache]: Analyzing trace with hash 792279208, now seen corresponding path program 1 times [2022-02-20 22:54:41,967 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:54:41,967 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [821299881] [2022-02-20 22:54:41,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:54:41,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:54:42,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,469 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:54:42,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,483 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,483 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,484 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4637#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,485 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 12 [2022-02-20 22:54:42,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,493 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,494 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,494 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,494 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4639#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,499 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 18 [2022-02-20 22:54:42,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,513 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,519 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,519 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,519 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,519 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,520 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:54:42,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,525 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,525 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,525 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,526 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 22:54:42,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,531 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,531 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,531 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,531 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,532 INFO L290 TraceCheckUtils]: 0: Hoare triple {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~25;call #t~malloc909.base, #t~malloc909.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc909.base, #t~malloc909.offset;havoc #t~malloc909.base, #t~malloc909.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {1893#true} is VALID [2022-02-20 22:54:42,532 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,532 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,532 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,532 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,533 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,533 INFO L272 TraceCheckUtils]: 6: Hoare triple {1893#true} call #t~ret910 := ldv_is_err(~res~3.base, ~res~3.offset); {1893#true} is VALID [2022-02-20 22:54:42,533 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,533 INFO L290 TraceCheckUtils]: 8: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,533 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,534 INFO L290 TraceCheckUtils]: 10: Hoare triple {1893#true} assume -9223372036854775808 <= #t~ret910 && #t~ret910 <= 9223372036854775807;~tmp___0~25 := #t~ret910;havoc #t~ret910; {1893#true} is VALID [2022-02-20 22:54:42,534 INFO L272 TraceCheckUtils]: 11: Hoare triple {1893#true} call ldv_assume((if 0 == ~tmp___0~25 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,534 INFO L290 TraceCheckUtils]: 12: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,534 INFO L290 TraceCheckUtils]: 13: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,534 INFO L290 TraceCheckUtils]: 14: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,534 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,535 INFO L290 TraceCheckUtils]: 16: Hoare triple {1893#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {1893#true} is VALID [2022-02-20 22:54:42,535 INFO L290 TraceCheckUtils]: 17: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,536 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4641#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,536 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 40 [2022-02-20 22:54:42,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,549 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,554 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,554 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,554 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,554 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,554 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:54:42,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,559 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,559 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,560 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,560 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 22:54:42,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,564 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,564 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,564 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,564 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,565 INFO L290 TraceCheckUtils]: 0: Hoare triple {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~25;call #t~malloc909.base, #t~malloc909.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc909.base, #t~malloc909.offset;havoc #t~malloc909.base, #t~malloc909.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {1893#true} is VALID [2022-02-20 22:54:42,565 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,565 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,565 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,565 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,566 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,566 INFO L272 TraceCheckUtils]: 6: Hoare triple {1893#true} call #t~ret910 := ldv_is_err(~res~3.base, ~res~3.offset); {1893#true} is VALID [2022-02-20 22:54:42,566 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,566 INFO L290 TraceCheckUtils]: 8: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,566 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,566 INFO L290 TraceCheckUtils]: 10: Hoare triple {1893#true} assume -9223372036854775808 <= #t~ret910 && #t~ret910 <= 9223372036854775807;~tmp___0~25 := #t~ret910;havoc #t~ret910; {1893#true} is VALID [2022-02-20 22:54:42,567 INFO L272 TraceCheckUtils]: 11: Hoare triple {1893#true} call ldv_assume((if 0 == ~tmp___0~25 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,567 INFO L290 TraceCheckUtils]: 12: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,567 INFO L290 TraceCheckUtils]: 13: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,567 INFO L290 TraceCheckUtils]: 14: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,567 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,568 INFO L290 TraceCheckUtils]: 16: Hoare triple {1893#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {1893#true} is VALID [2022-02-20 22:54:42,568 INFO L290 TraceCheckUtils]: 17: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,568 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4645#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,569 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 61 [2022-02-20 22:54:42,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,582 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,587 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,588 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,588 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,588 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,588 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:54:42,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,593 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,594 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,594 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,594 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 22:54:42,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,599 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,599 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,599 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,599 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,600 INFO L290 TraceCheckUtils]: 0: Hoare triple {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~25;call #t~malloc909.base, #t~malloc909.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc909.base, #t~malloc909.offset;havoc #t~malloc909.base, #t~malloc909.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {1893#true} is VALID [2022-02-20 22:54:42,600 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,600 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,600 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,600 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,601 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,601 INFO L272 TraceCheckUtils]: 6: Hoare triple {1893#true} call #t~ret910 := ldv_is_err(~res~3.base, ~res~3.offset); {1893#true} is VALID [2022-02-20 22:54:42,601 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,601 INFO L290 TraceCheckUtils]: 8: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,601 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,602 INFO L290 TraceCheckUtils]: 10: Hoare triple {1893#true} assume -9223372036854775808 <= #t~ret910 && #t~ret910 <= 9223372036854775807;~tmp___0~25 := #t~ret910;havoc #t~ret910; {1893#true} is VALID [2022-02-20 22:54:42,602 INFO L272 TraceCheckUtils]: 11: Hoare triple {1893#true} call ldv_assume((if 0 == ~tmp___0~25 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,602 INFO L290 TraceCheckUtils]: 12: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,602 INFO L290 TraceCheckUtils]: 13: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,602 INFO L290 TraceCheckUtils]: 14: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,602 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,603 INFO L290 TraceCheckUtils]: 16: Hoare triple {1893#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {1893#true} is VALID [2022-02-20 22:54:42,603 INFO L290 TraceCheckUtils]: 17: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,604 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4647#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,604 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 82 [2022-02-20 22:54:42,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,612 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,612 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,613 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4649#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,613 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 95 [2022-02-20 22:54:42,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,620 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,625 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,625 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,626 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,626 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,626 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~val := #in~val; {1893#true} is VALID [2022-02-20 22:54:42,626 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,626 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,626 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,627 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,627 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,627 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} #res := ~val; {1893#true} is VALID [2022-02-20 22:54:42,627 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,628 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4717#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,628 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 107 [2022-02-20 22:54:42,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,638 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,639 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,639 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4719#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,639 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 113 [2022-02-20 22:54:42,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,646 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,646 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,647 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,647 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4721#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,648 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 118 [2022-02-20 22:54:42,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,655 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,655 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,656 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4729#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,656 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 127 [2022-02-20 22:54:42,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,664 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,670 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,674 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,674 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,674 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,675 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,675 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~val := #in~val; {1893#true} is VALID [2022-02-20 22:54:42,675 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,675 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,675 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,675 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,676 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,676 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} #res := ~val; {1893#true} is VALID [2022-02-20 22:54:42,676 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,676 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1893#true} {1893#true} #3627#return; {1893#true} is VALID [2022-02-20 22:54:42,676 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~ret_val := #in~ret_val;havoc ~tmp~74; {1893#true} is VALID [2022-02-20 22:54:42,677 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call #t~ret890 := ldv_filter_positive_int(~ret_val); {1893#true} is VALID [2022-02-20 22:54:42,677 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~val := #in~val; {1893#true} is VALID [2022-02-20 22:54:42,677 INFO L272 TraceCheckUtils]: 3: Hoare triple {1893#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,677 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,677 INFO L290 TraceCheckUtils]: 5: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,677 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,677 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,678 INFO L290 TraceCheckUtils]: 8: Hoare triple {1893#true} #res := ~val; {1893#true} is VALID [2022-02-20 22:54:42,678 INFO L290 TraceCheckUtils]: 9: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,678 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1893#true} {1893#true} #3627#return; {1893#true} is VALID [2022-02-20 22:54:42,678 INFO L290 TraceCheckUtils]: 11: Hoare triple {1893#true} assume -2147483648 <= #t~ret890 && #t~ret890 <= 2147483647;~tmp~74 := #t~ret890;havoc #t~ret890;#res := ~tmp~74; {1893#true} is VALID [2022-02-20 22:54:42,678 INFO L290 TraceCheckUtils]: 12: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,679 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4733#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,679 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 144 [2022-02-20 22:54:42,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,688 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,693 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,697 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,698 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,698 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,698 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,698 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~val := #in~val; {1893#true} is VALID [2022-02-20 22:54:42,699 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,699 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,699 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,699 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,699 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,699 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} #res := ~val; {1893#true} is VALID [2022-02-20 22:54:42,699 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,700 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1893#true} {1893#true} #3627#return; {1893#true} is VALID [2022-02-20 22:54:42,700 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~ret_val := #in~ret_val;havoc ~tmp~74; {1893#true} is VALID [2022-02-20 22:54:42,700 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call #t~ret890 := ldv_filter_positive_int(~ret_val); {1893#true} is VALID [2022-02-20 22:54:42,700 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~val := #in~val; {1893#true} is VALID [2022-02-20 22:54:42,700 INFO L272 TraceCheckUtils]: 3: Hoare triple {1893#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,700 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,701 INFO L290 TraceCheckUtils]: 5: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,701 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,701 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,701 INFO L290 TraceCheckUtils]: 8: Hoare triple {1893#true} #res := ~val; {1893#true} is VALID [2022-02-20 22:54:42,701 INFO L290 TraceCheckUtils]: 9: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,701 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1893#true} {1893#true} #3627#return; {1893#true} is VALID [2022-02-20 22:54:42,702 INFO L290 TraceCheckUtils]: 11: Hoare triple {1893#true} assume -2147483648 <= #t~ret890 && #t~ret890 <= 2147483647;~tmp~74 := #t~ret890;havoc #t~ret890;#res := ~tmp~74; {1893#true} is VALID [2022-02-20 22:54:42,702 INFO L290 TraceCheckUtils]: 12: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,702 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4737#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,703 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 168 [2022-02-20 22:54:42,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,711 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1893#true} is VALID [2022-02-20 22:54:42,711 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,711 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1894#false} #4165#return; {1894#false} is VALID [2022-02-20 22:54:42,712 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 176 [2022-02-20 22:54:42,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,717 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,717 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,718 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1894#false} #4167#return; {1894#false} is VALID [2022-02-20 22:54:42,718 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 182 [2022-02-20 22:54:42,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,724 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,725 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,725 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,725 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1894#false} #4169#return; {1894#false} is VALID [2022-02-20 22:54:42,725 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 188 [2022-02-20 22:54:42,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,737 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,742 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,742 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,742 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,743 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,743 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:54:42,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,747 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,747 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,747 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,747 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 22:54:42,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,751 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,752 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,752 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,752 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,752 INFO L290 TraceCheckUtils]: 0: Hoare triple {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~25;call #t~malloc909.base, #t~malloc909.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc909.base, #t~malloc909.offset;havoc #t~malloc909.base, #t~malloc909.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {1893#true} is VALID [2022-02-20 22:54:42,752 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,752 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,753 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,753 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,753 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,753 INFO L272 TraceCheckUtils]: 6: Hoare triple {1893#true} call #t~ret910 := ldv_is_err(~res~3.base, ~res~3.offset); {1893#true} is VALID [2022-02-20 22:54:42,753 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,753 INFO L290 TraceCheckUtils]: 8: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,753 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,754 INFO L290 TraceCheckUtils]: 10: Hoare triple {1893#true} assume -9223372036854775808 <= #t~ret910 && #t~ret910 <= 9223372036854775807;~tmp___0~25 := #t~ret910;havoc #t~ret910; {1893#true} is VALID [2022-02-20 22:54:42,754 INFO L272 TraceCheckUtils]: 11: Hoare triple {1893#true} call ldv_assume((if 0 == ~tmp___0~25 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,754 INFO L290 TraceCheckUtils]: 12: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,754 INFO L290 TraceCheckUtils]: 13: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,754 INFO L290 TraceCheckUtils]: 14: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,754 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,755 INFO L290 TraceCheckUtils]: 16: Hoare triple {1893#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {1893#true} is VALID [2022-02-20 22:54:42,755 INFO L290 TraceCheckUtils]: 17: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,755 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {1893#true} {1894#false} #4171#return; {1894#false} is VALID [2022-02-20 22:54:42,755 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 212 [2022-02-20 22:54:42,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,760 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1893#true} is VALID [2022-02-20 22:54:42,760 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,760 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1894#false} #4175#return; {1894#false} is VALID [2022-02-20 22:54:42,763 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 217 [2022-02-20 22:54:42,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,768 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-02-20 22:54:42,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,772 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {1893#true} is VALID [2022-02-20 22:54:42,772 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,772 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {2173#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} #4633#return; {1893#true} is VALID [2022-02-20 22:54:42,772 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 4 [2022-02-20 22:54:42,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,776 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,776 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,776 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,777 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {1893#true} #4635#return; {1893#true} is VALID [2022-02-20 22:54:42,777 INFO L272 TraceCheckUtils]: 0: Hoare triple {2173#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} call ldv_assert(191, 0, (if 1 == ~ldv_spin_lock_of_via_ircc_cb~0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,777 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {1893#true} is VALID [2022-02-20 22:54:42,777 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,777 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1893#true} {2173#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} #4633#return; {1893#true} is VALID [2022-02-20 22:54:42,777 INFO L272 TraceCheckUtils]: 4: Hoare triple {1893#true} call ldv_assume((if 1 == ~ldv_spin_lock_of_via_ircc_cb~0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,778 INFO L290 TraceCheckUtils]: 5: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,778 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,778 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,778 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1893#true} {1893#true} #4635#return; {1893#true} is VALID [2022-02-20 22:54:42,778 INFO L290 TraceCheckUtils]: 9: Hoare triple {1893#true} ~ldv_spin_lock_of_via_ircc_cb~0 := 2; {1893#true} is VALID [2022-02-20 22:54:42,778 INFO L290 TraceCheckUtils]: 10: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,779 INFO L284 TraceCheckUtils]: 11: Hoare quadruple {1893#true} {1894#false} #4177#return; {1894#false} is VALID [2022-02-20 22:54:42,779 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 234 [2022-02-20 22:54:42,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,784 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,845 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,846 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,846 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,846 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,846 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,847 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,847 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,847 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,847 INFO L290 TraceCheckUtils]: 5: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,847 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,847 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1893#true} {1894#false} #4179#return; {1894#false} is VALID [2022-02-20 22:54:42,848 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 248 [2022-02-20 22:54:42,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,854 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,857 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,858 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,858 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,858 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,858 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,858 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,858 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,859 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,859 INFO L290 TraceCheckUtils]: 5: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,859 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,859 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1893#true} {1894#false} #4263#return; {1894#false} is VALID [2022-02-20 22:54:42,865 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 262 [2022-02-20 22:54:42,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,878 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,883 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,887 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,887 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,888 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,888 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,888 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,888 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,888 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,888 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,889 INFO L290 TraceCheckUtils]: 5: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,889 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,889 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1893#true} {1893#true} #3987#return; {1893#true} is VALID [2022-02-20 22:54:42,889 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 22:54:42,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,894 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:54:42,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,898 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,898 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,898 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,898 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,899 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,899 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,899 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,899 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,899 INFO L290 TraceCheckUtils]: 5: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,899 INFO L290 TraceCheckUtils]: 6: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,900 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1893#true} {1893#true} #3989#return; {1893#true} is VALID [2022-02-20 22:54:42,900 INFO L290 TraceCheckUtils]: 0: Hoare triple {2187#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~iobase := #in~iobase;~self.base, ~self.offset := #in~self.base, #in~self.offset;havoc ~low~4;havoc ~high~4;havoc ~wTmp~2;havoc ~wTmp1~2;havoc ~ret~0; {1893#true} is VALID [2022-02-20 22:54:42,900 INFO L272 TraceCheckUtils]: 1: Hoare triple {1893#true} call #t~ret159 := ReadReg(~iobase % 65536, 44); {1893#true} is VALID [2022-02-20 22:54:42,900 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,900 INFO L272 TraceCheckUtils]: 3: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,900 INFO L290 TraceCheckUtils]: 4: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,901 INFO L290 TraceCheckUtils]: 5: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,901 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,901 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,901 INFO L290 TraceCheckUtils]: 8: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,901 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1893#true} {1893#true} #3987#return; {1893#true} is VALID [2022-02-20 22:54:42,901 INFO L290 TraceCheckUtils]: 10: Hoare triple {1893#true} ~low~4 := #t~ret159;havoc #t~ret159; {1893#true} is VALID [2022-02-20 22:54:42,901 INFO L272 TraceCheckUtils]: 11: Hoare triple {1893#true} call #t~ret160 := ReadReg(~iobase % 65536, 45); {1893#true} is VALID [2022-02-20 22:54:42,902 INFO L290 TraceCheckUtils]: 12: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,902 INFO L272 TraceCheckUtils]: 13: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,902 INFO L290 TraceCheckUtils]: 14: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,902 INFO L290 TraceCheckUtils]: 15: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,902 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,902 INFO L290 TraceCheckUtils]: 17: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,902 INFO L290 TraceCheckUtils]: 18: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,903 INFO L284 TraceCheckUtils]: 19: Hoare quadruple {1893#true} {1893#true} #3989#return; {1893#true} is VALID [2022-02-20 22:54:42,903 INFO L290 TraceCheckUtils]: 20: Hoare triple {1893#true} ~high~4 := #t~ret160;havoc #t~ret160;~wTmp1~2 := ~high~4 % 256;~wTmp~2 := (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 0 == ~low~4 % 256 then (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) else (if 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256) then ~low~4 % 256 else (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256)) || ((1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 1 == ~low~4 % 256) then 1 else ~bitwiseOr((if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536), ~low~4 % 256))));call #t~mem161 := read~int(~self.base, 596 + ~self.offset, 4); {1893#true} is VALID [2022-02-20 22:54:42,903 INFO L290 TraceCheckUtils]: 21: Hoare triple {1893#true} assume ~wTmp~2 % 65536 % 4294967296 >= #t~mem161 % 4294967296;havoc #t~mem161;call #t~mem162 := read~int(~self.base, 596 + ~self.offset, 4);~ret~0 := ~wTmp~2 % 65536 - #t~mem162 % 65536;havoc #t~mem162; {1893#true} is VALID [2022-02-20 22:54:42,903 INFO L290 TraceCheckUtils]: 22: Hoare triple {1893#true} call write~int(~wTmp~2 % 65536, ~self.base, 596 + ~self.offset, 4);#res := ~ret~0; {1893#true} is VALID [2022-02-20 22:54:42,903 INFO L290 TraceCheckUtils]: 23: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,904 INFO L284 TraceCheckUtils]: 24: Hoare quadruple {1893#true} {1894#false} #4265#return; {1894#false} is VALID [2022-02-20 22:54:42,904 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 294 [2022-02-20 22:54:42,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:54:42,908 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} assume 2 == ~ldv_spin_NOT_ARG_SIGN~0;#res := 1; {1893#true} is VALID [2022-02-20 22:54:42,908 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,908 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1893#true} {1894#false} #3629#return; {1894#false} is VALID [2022-02-20 22:54:42,910 INFO L290 TraceCheckUtils]: 0: Hoare triple {1893#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(190, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(9, 4);call #Ultimate.allocInit(9, 5);call #Ultimate.allocInit(7, 6);call write~init~int(15, 6, 0, 1);call write~init~int(37, 6, 1, 1);call write~init~int(115, 6, 2, 1);call write~init~int(40, 6, 3, 1);call write~init~int(41, 6, 4, 1);call write~init~int(10, 6, 5, 1);call write~init~int(0, 6, 6, 1);call #Ultimate.allocInit(14, 7);call #Ultimate.allocInit(9, 8);call #Ultimate.allocInit(45, 9);call #Ultimate.allocInit(14, 10);call #Ultimate.allocInit(25, 11);call #Ultimate.allocInit(13, 12);call #Ultimate.allocInit(22, 13);call #Ultimate.allocInit(13, 14);call #Ultimate.allocInit(23, 15);call #Ultimate.allocInit(13, 16);call #Ultimate.allocInit(23, 17);call #Ultimate.allocInit(13, 18);call #Ultimate.allocInit(22, 19);call #Ultimate.allocInit(13, 20);call #Ultimate.allocInit(7, 21);call write~init~int(15, 21, 0, 1);call write~init~int(37, 21, 1, 1);call write~init~int(115, 21, 2, 1);call write~init~int(40, 21, 3, 1);call write~init~int(41, 21, 4, 1);call write~init~int(10, 21, 5, 1);call write~init~int(0, 21, 6, 1);call #Ultimate.allocInit(17, 22);call #Ultimate.allocInit(7, 23);call write~init~int(15, 23, 0, 1);call write~init~int(37, 23, 1, 1);call write~init~int(115, 23, 2, 1);call write~init~int(40, 23, 3, 1);call write~init~int(41, 23, 4, 1);call write~init~int(10, 23, 5, 1);call write~init~int(0, 23, 6, 1);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(22, 25);call #Ultimate.allocInit(35, 26);call #Ultimate.allocInit(14, 27);call #Ultimate.allocInit(40, 28);call #Ultimate.allocInit(7, 29);call write~init~int(15, 29, 0, 1);call write~init~int(37, 29, 1, 1);call write~init~int(115, 29, 2, 1);call write~init~int(40, 29, 3, 1);call write~init~int(41, 29, 4, 1);call write~init~int(10, 29, 5, 1);call write~init~int(0, 29, 6, 1);call #Ultimate.allocInit(15, 30);call #Ultimate.allocInit(30, 31);call #Ultimate.allocInit(15, 32);call #Ultimate.allocInit(7, 33);call write~init~int(15, 33, 0, 1);call write~init~int(37, 33, 1, 1);call write~init~int(115, 33, 2, 1);call write~init~int(40, 33, 3, 1);call write~init~int(41, 33, 4, 1);call write~init~int(10, 33, 5, 1);call write~init~int(0, 33, 6, 1);call #Ultimate.allocInit(12, 34);call #Ultimate.allocInit(85, 35);call #Ultimate.allocInit(47, 36);call #Ultimate.allocInit(29, 37);call #Ultimate.allocInit(58, 38);call #Ultimate.allocInit(29, 39);call #Ultimate.allocInit(50, 40);call #Ultimate.allocInit(29, 41);call #Ultimate.allocInit(40, 42);call #Ultimate.allocInit(29, 43);call #Ultimate.allocInit(30, 44);call #Ultimate.allocInit(22, 45);call #Ultimate.allocInit(31, 46);call #Ultimate.allocInit(28, 47);call #Ultimate.allocInit(23, 48);call #Ultimate.allocInit(13, 49);call #Ultimate.allocInit(45, 50);call #Ultimate.allocInit(18, 51);call #Ultimate.allocInit(7, 52);call write~init~int(15, 52, 0, 1);call write~init~int(37, 52, 1, 1);call write~init~int(115, 52, 2, 1);call write~init~int(40, 52, 3, 1);call write~init~int(41, 52, 4, 1);call write~init~int(10, 52, 5, 1);call write~init~int(0, 52, 6, 1);call #Ultimate.allocInit(27, 53);call #Ultimate.allocInit(56, 54);call #Ultimate.allocInit(27, 55);call #Ultimate.allocInit(7, 56);call write~init~int(15, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(40, 56, 3, 1);call write~init~int(41, 56, 4, 1);call write~init~int(10, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(21, 57);call #Ultimate.allocInit(50, 58);call #Ultimate.allocInit(30, 59);call #Ultimate.allocInit(41, 60);call #Ultimate.allocInit(30, 61);call #Ultimate.allocInit(26, 62);call #Ultimate.allocInit(30, 63);call #Ultimate.allocInit(15, 64);call #Ultimate.allocInit(14, 65);call #Ultimate.allocInit(23, 66);call #Ultimate.allocInit(15, 67);call #Ultimate.allocInit(48, 68);call #Ultimate.allocInit(15, 69);call #Ultimate.allocInit(43, 70);call #Ultimate.allocInit(19, 71);call #Ultimate.allocInit(6, 72);call write~init~int(84, 72, 0, 1);call write~init~int(105, 72, 1, 1);call write~init~int(109, 72, 2, 1);call write~init~int(101, 72, 3, 1);call write~init~int(114, 72, 4, 1);call write~init~int(0, 72, 5, 1);call #Ultimate.allocInit(1, 73);call write~init~int(0, 73, 0, 1);call #Ultimate.allocInit(3, 74);call write~init~int(84, 74, 0, 1);call write~init~int(120, 74, 1, 1);call write~init~int(0, 74, 2, 1);call #Ultimate.allocInit(1, 75);call write~init~int(0, 75, 0, 1);call #Ultimate.allocInit(3, 76);call write~init~int(82, 76, 0, 1);call write~init~int(120, 76, 1, 1);call write~init~int(0, 76, 2, 1);call #Ultimate.allocInit(1, 77);call write~init~int(0, 77, 0, 1);call #Ultimate.allocInit(38, 78);call #Ultimate.allocInit(19, 79);call #Ultimate.allocInit(13, 80);call #Ultimate.allocInit(1, 81);call write~init~int(0, 81, 0, 1);call #Ultimate.allocInit(4, 82);call write~init~int(69, 82, 0, 1);call write~init~int(79, 82, 1, 1);call write~init~int(77, 82, 2, 1);call write~init~int(0, 82, 3, 1);call #Ultimate.allocInit(1, 83);call write~init~int(0, 83, 0, 1);call #Ultimate.allocInit(11, 84);call #Ultimate.allocInit(1, 85);call write~init~int(0, 85, 0, 1);call #Ultimate.allocInit(10, 86);call #Ultimate.allocInit(1, 87);call write~init~int(0, 87, 0, 1);call #Ultimate.allocInit(47, 88);call #Ultimate.allocInit(19, 89);call #Ultimate.allocInit(9, 90);call #Ultimate.allocInit(1, 91);call write~init~int(0, 91, 0, 1);call #Ultimate.allocInit(8, 92);call #Ultimate.allocInit(1, 93);call write~init~int(0, 93, 0, 1);call #Ultimate.allocInit(12, 94);call #Ultimate.allocInit(1, 95);call write~init~int(0, 95, 0, 1);call #Ultimate.allocInit(4, 96);call write~init~int(69, 96, 0, 1);call write~init~int(79, 96, 1, 1);call write~init~int(70, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(1, 97);call write~init~int(0, 97, 0, 1);call #Ultimate.allocInit(7, 98);call write~init~int(82, 98, 0, 1);call write~init~int(120, 98, 1, 1);call write~init~int(68, 98, 2, 1);call write~init~int(97, 98, 3, 1);call write~init~int(116, 98, 4, 1);call write~init~int(97, 98, 5, 1);call write~init~int(0, 98, 6, 1);call #Ultimate.allocInit(1, 99);call write~init~int(0, 99, 0, 1);call #Ultimate.allocInit(9, 100);call #Ultimate.allocInit(1, 101);call write~init~int(0, 101, 0, 1);call #Ultimate.allocInit(8, 102);call #Ultimate.allocInit(1, 103);call write~init~int(0, 103, 0, 1);call #Ultimate.allocInit(17, 104);call #Ultimate.allocInit(19, 105);call #Ultimate.allocInit(79, 106);call #Ultimate.allocInit(19, 107);call #Ultimate.allocInit(7, 108);call write~init~int(15, 108, 0, 1);call write~init~int(37, 108, 1, 1);call write~init~int(115, 108, 2, 1);call write~init~int(40, 108, 3, 1);call write~init~int(41, 108, 4, 1);call write~init~int(10, 108, 5, 1);call write~init~int(0, 108, 6, 1);call #Ultimate.allocInit(8, 109);call #Ultimate.allocInit(31, 110);call #Ultimate.allocInit(28, 111);call #Ultimate.allocInit(22, 112);call #Ultimate.allocInit(13, 113);call #Ultimate.allocInit(22, 114);call #Ultimate.allocInit(22, 115);call #Ultimate.allocInit(7, 116);call write~init~int(15, 116, 0, 1);call write~init~int(37, 116, 1, 1);call write~init~int(115, 116, 2, 1);call write~init~int(40, 116, 3, 1);call write~init~int(41, 116, 4, 1);call write~init~int(10, 116, 5, 1);call write~init~int(0, 116, 6, 1);call #Ultimate.allocInit(18, 117);call #Ultimate.allocInit(31, 118);call #Ultimate.allocInit(28, 119);call #Ultimate.allocInit(18, 120);call #Ultimate.allocInit(12, 121);call #Ultimate.allocInit(31, 122);call #Ultimate.allocInit(28, 123);call #Ultimate.allocInit(18, 124);call #Ultimate.allocInit(13, 125);call #Ultimate.allocInit(32, 126);call #Ultimate.allocInit(32, 127);call #Ultimate.allocInit(33, 128);call #Ultimate.allocInit(11, 129);call #Ultimate.allocInit(7, 130);call write~init~int(15, 130, 0, 1);call write~init~int(37, 130, 1, 1);call write~init~int(115, 130, 2, 1);call write~init~int(40, 130, 3, 1);call write~init~int(41, 130, 4, 1);call write~init~int(10, 130, 5, 1);call write~init~int(0, 130, 6, 1);call #Ultimate.allocInit(19, 131);call #Ultimate.allocInit(31, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(19, 134);call #Ultimate.allocInit(12, 135);call #Ultimate.allocInit(31, 136);call #Ultimate.allocInit(28, 137);call #Ultimate.allocInit(19, 138);call #Ultimate.allocInit(13, 139);call #Ultimate.allocInit(31, 140);call #Ultimate.allocInit(28, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(12, 143);call #Ultimate.allocInit(31, 144);call #Ultimate.allocInit(28, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(13, 147);call #Ultimate.allocInit(23, 148);call #Ultimate.allocInit(19, 149);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(54, 151);call #Ultimate.allocInit(56, 152);call #Ultimate.allocInit(58, 153);call #Ultimate.allocInit(58, 154);call #Ultimate.allocInit(58, 155);call #Ultimate.allocInit(54, 156);call #Ultimate.allocInit(56, 157);call #Ultimate.allocInit(58, 158);call #Ultimate.allocInit(58, 159);call #Ultimate.allocInit(58, 160);call #Ultimate.allocInit(54, 161);call #Ultimate.allocInit(56, 162);call #Ultimate.allocInit(58, 163);call #Ultimate.allocInit(58, 164);call #Ultimate.allocInit(58, 165);call #Ultimate.allocInit(54, 166);call #Ultimate.allocInit(56, 167);call #Ultimate.allocInit(58, 168);call #Ultimate.allocInit(58, 169);call #Ultimate.allocInit(58, 170);call #Ultimate.allocInit(54, 171);call #Ultimate.allocInit(56, 172);call #Ultimate.allocInit(58, 173);call #Ultimate.allocInit(58, 174);call #Ultimate.allocInit(58, 175);call #Ultimate.allocInit(54, 176);call #Ultimate.allocInit(56, 177);call #Ultimate.allocInit(58, 178);call #Ultimate.allocInit(58, 179);call #Ultimate.allocInit(58, 180);call #Ultimate.allocInit(54, 181);call #Ultimate.allocInit(56, 182);call #Ultimate.allocInit(58, 183);call #Ultimate.allocInit(58, 184);call #Ultimate.allocInit(58, 185);call #Ultimate.allocInit(54, 186);call #Ultimate.allocInit(56, 187);call #Ultimate.allocInit(58, 188);call #Ultimate.allocInit(58, 189);call #Ultimate.allocInit(58, 190);call #Ultimate.allocInit(54, 191);call #Ultimate.allocInit(56, 192);call #Ultimate.allocInit(58, 193);call #Ultimate.allocInit(58, 194);call #Ultimate.allocInit(58, 195);call #Ultimate.allocInit(54, 196);call #Ultimate.allocInit(56, 197);call #Ultimate.allocInit(58, 198);call #Ultimate.allocInit(58, 199);call #Ultimate.allocInit(58, 200);call #Ultimate.allocInit(54, 201);call #Ultimate.allocInit(56, 202);call #Ultimate.allocInit(58, 203);call #Ultimate.allocInit(58, 204);call #Ultimate.allocInit(58, 205);call #Ultimate.allocInit(54, 206);call #Ultimate.allocInit(56, 207);call #Ultimate.allocInit(58, 208);call #Ultimate.allocInit(58, 209);call #Ultimate.allocInit(58, 210);call #Ultimate.allocInit(54, 211);call #Ultimate.allocInit(56, 212);call #Ultimate.allocInit(58, 213);call #Ultimate.allocInit(58, 214);call #Ultimate.allocInit(58, 215);call #Ultimate.allocInit(54, 216);call #Ultimate.allocInit(56, 217);call #Ultimate.allocInit(58, 218);call #Ultimate.allocInit(58, 219);call #Ultimate.allocInit(58, 220);call #Ultimate.allocInit(57, 221);call #Ultimate.allocInit(57, 222);call #Ultimate.allocInit(57, 223);call #Ultimate.allocInit(57, 224);call #Ultimate.allocInit(57, 225);call #Ultimate.allocInit(57, 226);call #Ultimate.allocInit(57, 227);call #Ultimate.allocInit(57, 228);call #Ultimate.allocInit(57, 229);call #Ultimate.allocInit(57, 230);call #Ultimate.allocInit(57, 231);call #Ultimate.allocInit(57, 232);call #Ultimate.allocInit(57, 233);call #Ultimate.allocInit(57, 234);call #Ultimate.allocInit(2, 235);call write~init~int(48, 235, 0, 1);call write~init~int(0, 235, 1, 1);call #Ultimate.allocInit(64, 236);~driver_name~0.base, ~driver_name~0.offset := 4, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 237, 0;call #Ultimate.allocInit(192, 237);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#via_driver~0.base, ~#via_driver~0.offset := 238, 0;call #Ultimate.allocInit(301, 238);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(5, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 145 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 153 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 161 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 169 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 177 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 185 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 193 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 201 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 209 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 217 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 237 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 245 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 253 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 261 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 269 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 285 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 293 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 239, 0;call #Ultimate.allocInit(472, 239);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 240, 0;call #Ultimate.allocInit(472, 240);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_thread_0~0.identifier := 0;~ldv_thread_0~0.function.base, ~ldv_thread_0~0.function.offset := 0, 0;~ldv_thread_1~0.identifier := 0;~ldv_thread_1~0.function.base, ~ldv_thread_1~0.function.offset := 0, 0;~ldv_thread_10~0.identifier := 0;~ldv_thread_10~0.function.base, ~ldv_thread_10~0.function.offset := 0, 0;~ldv_thread_2~0.identifier := 0;~ldv_thread_2~0.function.base, ~ldv_thread_2~0.function.offset := 0, 0;~ldv_spin_NOT_ARG_SIGN~0 := 1;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_dma_spin_lock~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_via_ircc_cb~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1; {1893#true} is VALID [2022-02-20 22:54:42,910 INFO L290 TraceCheckUtils]: 1: Hoare triple {1893#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_ldv_initialize } true; {1893#true} is VALID [2022-02-20 22:54:42,910 INFO L290 TraceCheckUtils]: 2: Hoare triple {1893#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_entry_EMGentry_10 } true;ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset := 0, 0;havoc ldv_entry_EMGentry_10_#t~ret800#1, ldv_entry_EMGentry_10_#t~ret801#1, ldv_entry_EMGentry_10_#t~ret802#1, ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1, ldv_entry_EMGentry_10_~tmp~49#1;ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset := ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_entry_EMGentry_10_~tmp~49#1;assume { :begin_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset := ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_#res#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret793#1, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset, ldv_EMGentry_init_via_ircc_init_10_7_~tmp~44#1;ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset := ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_~tmp~44#1;assume { :begin_inline_via_ircc_init } true;havoc via_ircc_init_#res#1;havoc via_ircc_init_#t~nondet213#1, via_ircc_init_#t~ret214#1, via_ircc_init_#t~nondet215#1, via_ircc_init_~rc~0#1;havoc via_ircc_init_~rc~0#1; {1893#true} is VALID [2022-02-20 22:54:42,911 INFO L290 TraceCheckUtils]: 3: Hoare triple {1893#true} assume ~irda_debug~0 % 4294967296 > 2;havoc via_ircc_init_#t~nondet213#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,912 INFO L290 TraceCheckUtils]: 4: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume { :begin_inline_ldv___pci_register_driver_90 } true;ldv___pci_register_driver_90_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_90_#in~ldv_func_arg1#1.offset, ldv___pci_register_driver_90_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_90_#in~ldv_func_arg2#1.offset, ldv___pci_register_driver_90_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_90_#in~ldv_func_arg3#1.offset := ~#via_driver~0.base, ~#via_driver~0.offset, ~#__this_module~0.base, ~#__this_module~0.offset, 8, 0;havoc ldv___pci_register_driver_90_#res#1;havoc ldv___pci_register_driver_90_#t~ret871#1, ldv___pci_register_driver_90_#t~ret872#1, ldv___pci_register_driver_90_~ldv_func_arg1#1.base, ldv___pci_register_driver_90_~ldv_func_arg1#1.offset, ldv___pci_register_driver_90_~ldv_func_arg2#1.base, ldv___pci_register_driver_90_~ldv_func_arg2#1.offset, ldv___pci_register_driver_90_~ldv_func_arg3#1.base, ldv___pci_register_driver_90_~ldv_func_arg3#1.offset, ldv___pci_register_driver_90_~ldv_func_res~0#1, ldv___pci_register_driver_90_~tmp~64#1, ldv___pci_register_driver_90_~tmp___0~19#1;ldv___pci_register_driver_90_~ldv_func_arg1#1.base, ldv___pci_register_driver_90_~ldv_func_arg1#1.offset := ldv___pci_register_driver_90_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_90_#in~ldv_func_arg1#1.offset;ldv___pci_register_driver_90_~ldv_func_arg2#1.base, ldv___pci_register_driver_90_~ldv_func_arg2#1.offset := ldv___pci_register_driver_90_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_90_#in~ldv_func_arg2#1.offset;ldv___pci_register_driver_90_~ldv_func_arg3#1.base, ldv___pci_register_driver_90_~ldv_func_arg3#1.offset := ldv___pci_register_driver_90_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_90_#in~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_90_~ldv_func_res~0#1;havoc ldv___pci_register_driver_90_~tmp~64#1;havoc ldv___pci_register_driver_90_~tmp___0~19#1;assume { :begin_inline___pci_register_driver } true;__pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset, __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset, __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset := ldv___pci_register_driver_90_~ldv_func_arg1#1.base, ldv___pci_register_driver_90_~ldv_func_arg1#1.offset, ldv___pci_register_driver_90_~ldv_func_arg2#1.base, ldv___pci_register_driver_90_~ldv_func_arg2#1.offset, ldv___pci_register_driver_90_~ldv_func_arg3#1.base, ldv___pci_register_driver_90_~ldv_func_arg3#1.offset;havoc __pci_register_driver_#res#1;havoc __pci_register_driver_#t~nondet991#1, __pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset, __pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset, __pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset;__pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset := __pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset;__pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset := __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset;__pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset := __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset;assume -2147483648 <= __pci_register_driver_#t~nondet991#1 && __pci_register_driver_#t~nondet991#1 <= 2147483647;__pci_register_driver_#res#1 := __pci_register_driver_#t~nondet991#1;havoc __pci_register_driver_#t~nondet991#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,913 INFO L290 TraceCheckUtils]: 5: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} ldv___pci_register_driver_90_#t~ret871#1 := __pci_register_driver_#res#1;assume { :end_inline___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_90_#t~ret871#1 && ldv___pci_register_driver_90_#t~ret871#1 <= 2147483647;ldv___pci_register_driver_90_~tmp~64#1 := ldv___pci_register_driver_90_#t~ret871#1;havoc ldv___pci_register_driver_90_#t~ret871#1;ldv___pci_register_driver_90_~ldv_func_res~0#1 := ldv___pci_register_driver_90_~tmp~64#1;assume { :begin_inline_ldv___pci_register_driver } true;ldv___pci_register_driver_#in~arg0#1, ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset, ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset, ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset := ldv___pci_register_driver_90_~ldv_func_res~0#1, ldv___pci_register_driver_90_~ldv_func_arg1#1.base, ldv___pci_register_driver_90_~ldv_func_arg1#1.offset, ldv___pci_register_driver_90_~ldv_func_arg2#1.base, ldv___pci_register_driver_90_~ldv_func_arg2#1.offset, ldv___pci_register_driver_90_~ldv_func_arg3#1.base, ldv___pci_register_driver_90_~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_#res#1;havoc ldv___pci_register_driver_#t~ret794#1, ldv___pci_register_driver_~arg0#1, ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset, ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset, ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset, ldv___pci_register_driver_~tmp~45#1;ldv___pci_register_driver_~arg0#1 := ldv___pci_register_driver_#in~arg0#1;ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset := ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset;ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset := ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset;ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset := ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset;havoc ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset;havoc ldv___pci_register_driver_~tmp~45#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,913 INFO L272 TraceCheckUtils]: 6: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv___pci_register_driver_#t~ret794#1 := ldv_undef_int(); {1893#true} is VALID [2022-02-20 22:54:42,913 INFO L290 TraceCheckUtils]: 7: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,913 INFO L290 TraceCheckUtils]: 8: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,914 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4637#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,914 INFO L290 TraceCheckUtils]: 10: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume -2147483648 <= ldv___pci_register_driver_#t~ret794#1 && ldv___pci_register_driver_#t~ret794#1 <= 2147483647;ldv___pci_register_driver_~tmp~45#1 := ldv___pci_register_driver_#t~ret794#1;havoc ldv___pci_register_driver_#t~ret794#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,915 INFO L290 TraceCheckUtils]: 11: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume 0 != ldv___pci_register_driver_~tmp~45#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,915 INFO L272 TraceCheckUtils]: 12: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_assume((if 0 == ldv___pci_register_driver_~arg0#1 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,915 INFO L290 TraceCheckUtils]: 13: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,915 INFO L290 TraceCheckUtils]: 14: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,915 INFO L290 TraceCheckUtils]: 15: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,916 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4639#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,916 INFO L290 TraceCheckUtils]: 17: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset := ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset;assume { :begin_inline_ldv_dispatch_register_9_2 } true;ldv_dispatch_register_9_2_#in~arg0#1.base, ldv_dispatch_register_9_2_#in~arg0#1.offset := ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset;havoc ldv_dispatch_register_9_2_#t~ret797#1.base, ldv_dispatch_register_9_2_#t~ret797#1.offset, ldv_dispatch_register_9_2_~arg0#1.base, ldv_dispatch_register_9_2_~arg0#1.offset, ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset, ldv_dispatch_register_9_2_~tmp~48#1.base, ldv_dispatch_register_9_2_~tmp~48#1.offset;ldv_dispatch_register_9_2_~arg0#1.base, ldv_dispatch_register_9_2_~arg0#1.offset := ldv_dispatch_register_9_2_#in~arg0#1.base, ldv_dispatch_register_9_2_#in~arg0#1.offset;havoc ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset;havoc ldv_dispatch_register_9_2_~tmp~48#1.base, ldv_dispatch_register_9_2_~tmp~48#1.offset; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,917 INFO L272 TraceCheckUtils]: 18: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_dispatch_register_9_2_#t~ret797#1.base, ldv_dispatch_register_9_2_#t~ret797#1.offset := ldv_xmalloc(16); {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:54:42,917 INFO L290 TraceCheckUtils]: 19: Hoare triple {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~25;call #t~malloc909.base, #t~malloc909.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc909.base, #t~malloc909.offset;havoc #t~malloc909.base, #t~malloc909.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {1893#true} is VALID [2022-02-20 22:54:42,917 INFO L272 TraceCheckUtils]: 20: Hoare triple {1893#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,917 INFO L290 TraceCheckUtils]: 21: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,917 INFO L290 TraceCheckUtils]: 22: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,918 INFO L290 TraceCheckUtils]: 23: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,918 INFO L284 TraceCheckUtils]: 24: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,918 INFO L272 TraceCheckUtils]: 25: Hoare triple {1893#true} call #t~ret910 := ldv_is_err(~res~3.base, ~res~3.offset); {1893#true} is VALID [2022-02-20 22:54:42,918 INFO L290 TraceCheckUtils]: 26: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,918 INFO L290 TraceCheckUtils]: 27: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,918 INFO L284 TraceCheckUtils]: 28: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,918 INFO L290 TraceCheckUtils]: 29: Hoare triple {1893#true} assume -9223372036854775808 <= #t~ret910 && #t~ret910 <= 9223372036854775807;~tmp___0~25 := #t~ret910;havoc #t~ret910; {1893#true} is VALID [2022-02-20 22:54:42,919 INFO L272 TraceCheckUtils]: 30: Hoare triple {1893#true} call ldv_assume((if 0 == ~tmp___0~25 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,919 INFO L290 TraceCheckUtils]: 31: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,919 INFO L290 TraceCheckUtils]: 32: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,919 INFO L290 TraceCheckUtils]: 33: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,919 INFO L284 TraceCheckUtils]: 34: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,919 INFO L290 TraceCheckUtils]: 35: Hoare triple {1893#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {1893#true} is VALID [2022-02-20 22:54:42,919 INFO L290 TraceCheckUtils]: 36: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,920 INFO L284 TraceCheckUtils]: 37: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4641#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,921 INFO L290 TraceCheckUtils]: 38: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} ldv_dispatch_register_9_2_~tmp~48#1.base, ldv_dispatch_register_9_2_~tmp~48#1.offset := ldv_dispatch_register_9_2_#t~ret797#1.base, ldv_dispatch_register_9_2_#t~ret797#1.offset;havoc ldv_dispatch_register_9_2_#t~ret797#1.base, ldv_dispatch_register_9_2_#t~ret797#1.offset;ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset := ldv_dispatch_register_9_2_~tmp~48#1.base, ldv_dispatch_register_9_2_~tmp~48#1.offset;call write~$Pointer$(ldv_dispatch_register_9_2_~arg0#1.base, ldv_dispatch_register_9_2_~arg0#1.offset, ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset, 8);assume { :begin_inline_ldv_pci_pci_instance_2 } true;ldv_pci_pci_instance_2_#in~arg0#1.base, ldv_pci_pci_instance_2_#in~arg0#1.offset := ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset;havoc ldv_pci_pci_instance_2_#t~mem830#1.base, ldv_pci_pci_instance_2_#t~mem830#1.offset, ldv_pci_pci_instance_2_#t~ret831#1.base, ldv_pci_pci_instance_2_#t~ret831#1.offset, ldv_pci_pci_instance_2_#t~ret832#1.base, ldv_pci_pci_instance_2_#t~ret832#1.offset, ldv_pci_pci_instance_2_#t~ret833#1, ldv_pci_pci_instance_2_#t~mem834#1.base, ldv_pci_pci_instance_2_#t~mem834#1.offset, ldv_pci_pci_instance_2_#t~ret835#1, ldv_pci_pci_instance_2_#t~ret836#1, ldv_pci_pci_instance_2_#t~ret837#1, ldv_pci_pci_instance_2_#t~ret838#1, ldv_pci_pci_instance_2_#t~mem839#1.base, ldv_pci_pci_instance_2_#t~mem839#1.offset, ldv_pci_pci_instance_2_#t~mem840#1.base, ldv_pci_pci_instance_2_#t~mem840#1.offset, ldv_pci_pci_instance_2_#t~mem841#1, ldv_pci_pci_instance_2_#t~ret842#1, ldv_pci_pci_instance_2_#t~ret843#1, ldv_pci_pci_instance_2_#t~mem844#1.base, ldv_pci_pci_instance_2_#t~mem844#1.offset, ldv_pci_pci_instance_2_#t~mem845#1.base, ldv_pci_pci_instance_2_#t~mem845#1.offset, ldv_pci_pci_instance_2_#t~mem846#1, ldv_pci_pci_instance_2_#t~ret847#1, ldv_pci_pci_instance_2_#t~ret848#1, ldv_pci_pci_instance_2_#t~mem849#1.base, ldv_pci_pci_instance_2_#t~mem849#1.offset, ldv_pci_pci_instance_2_#t~mem850#1.base, ldv_pci_pci_instance_2_#t~mem850#1.offset, ldv_pci_pci_instance_2_#t~mem851#1.base, ldv_pci_pci_instance_2_#t~mem851#1.offset, ldv_pci_pci_instance_2_#t~mem852#1.base, ldv_pci_pci_instance_2_#t~mem852#1.offset, ldv_pci_pci_instance_2_#t~mem853#1.base, ldv_pci_pci_instance_2_#t~mem853#1.offset, ldv_pci_pci_instance_2_#t~mem854#1.base, ldv_pci_pci_instance_2_#t~mem854#1.offset, ldv_pci_pci_instance_2_#t~mem855#1.base, ldv_pci_pci_instance_2_#t~mem855#1.offset, ldv_pci_pci_instance_2_~arg0#1.base, ldv_pci_pci_instance_2_~arg0#1.offset, ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.offset, ldv_pci_pci_instance_2_~#ldv_2_resource_pm_message~0#1.base, ldv_pci_pci_instance_2_~#ldv_2_resource_pm_message~0#1.offset, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.offset, ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1, ldv_pci_pci_instance_2_~data~4#1.base, ldv_pci_pci_instance_2_~data~4#1.offset, ldv_pci_pci_instance_2_~tmp~56#1.base, ldv_pci_pci_instance_2_~tmp~56#1.offset, ldv_pci_pci_instance_2_~tmp___0~17#1.base, ldv_pci_pci_instance_2_~tmp___0~17#1.offset, ldv_pci_pci_instance_2_~tmp___1~12#1, ldv_pci_pci_instance_2_~tmp___2~10#1, ldv_pci_pci_instance_2_~tmp___3~7#1;ldv_pci_pci_instance_2_~arg0#1.base, ldv_pci_pci_instance_2_~arg0#1.offset := ldv_pci_pci_instance_2_#in~arg0#1.base, ldv_pci_pci_instance_2_#in~arg0#1.offset;havoc ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset;havoc ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.offset;call ldv_pci_pci_instance_2_~#ldv_2_resource_pm_message~0#1.base, ldv_pci_pci_instance_2_~#ldv_2_resource_pm_message~0#1.offset := #Ultimate.allocOnStack(4);havoc ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.offset;havoc ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1;havoc ldv_pci_pci_instance_2_~data~4#1.base, ldv_pci_pci_instance_2_~data~4#1.offset;havoc ldv_pci_pci_instance_2_~tmp~56#1.base, ldv_pci_pci_instance_2_~tmp~56#1.offset;havoc ldv_pci_pci_instance_2_~tmp___0~17#1.base, ldv_pci_pci_instance_2_~tmp___0~17#1.offset;havoc ldv_pci_pci_instance_2_~tmp___1~12#1;havoc ldv_pci_pci_instance_2_~tmp___2~10#1;havoc ldv_pci_pci_instance_2_~tmp___3~7#1;ldv_pci_pci_instance_2_~data~4#1.base, ldv_pci_pci_instance_2_~data~4#1.offset := ldv_pci_pci_instance_2_~arg0#1.base, ldv_pci_pci_instance_2_~arg0#1.offset;ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1 := 1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,921 INFO L290 TraceCheckUtils]: 39: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume !(0 != (ldv_pci_pci_instance_2_~data~4#1.base + ldv_pci_pci_instance_2_~data~4#1.offset) % 18446744073709551616); {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,922 INFO L272 TraceCheckUtils]: 40: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_pci_pci_instance_2_#t~ret831#1.base, ldv_pci_pci_instance_2_#t~ret831#1.offset := ldv_xmalloc(2936); {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:54:42,922 INFO L290 TraceCheckUtils]: 41: Hoare triple {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~25;call #t~malloc909.base, #t~malloc909.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc909.base, #t~malloc909.offset;havoc #t~malloc909.base, #t~malloc909.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {1893#true} is VALID [2022-02-20 22:54:42,922 INFO L272 TraceCheckUtils]: 42: Hoare triple {1893#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,922 INFO L290 TraceCheckUtils]: 43: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,922 INFO L290 TraceCheckUtils]: 44: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,923 INFO L290 TraceCheckUtils]: 45: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,923 INFO L284 TraceCheckUtils]: 46: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,923 INFO L272 TraceCheckUtils]: 47: Hoare triple {1893#true} call #t~ret910 := ldv_is_err(~res~3.base, ~res~3.offset); {1893#true} is VALID [2022-02-20 22:54:42,923 INFO L290 TraceCheckUtils]: 48: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,923 INFO L290 TraceCheckUtils]: 49: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,923 INFO L284 TraceCheckUtils]: 50: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,923 INFO L290 TraceCheckUtils]: 51: Hoare triple {1893#true} assume -9223372036854775808 <= #t~ret910 && #t~ret910 <= 9223372036854775807;~tmp___0~25 := #t~ret910;havoc #t~ret910; {1893#true} is VALID [2022-02-20 22:54:42,923 INFO L272 TraceCheckUtils]: 52: Hoare triple {1893#true} call ldv_assume((if 0 == ~tmp___0~25 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,924 INFO L290 TraceCheckUtils]: 53: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,924 INFO L290 TraceCheckUtils]: 54: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,924 INFO L290 TraceCheckUtils]: 55: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,924 INFO L284 TraceCheckUtils]: 56: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,924 INFO L290 TraceCheckUtils]: 57: Hoare triple {1893#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {1893#true} is VALID [2022-02-20 22:54:42,924 INFO L290 TraceCheckUtils]: 58: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,925 INFO L284 TraceCheckUtils]: 59: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4645#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,925 INFO L290 TraceCheckUtils]: 60: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} ldv_pci_pci_instance_2_~tmp~56#1.base, ldv_pci_pci_instance_2_~tmp~56#1.offset := ldv_pci_pci_instance_2_#t~ret831#1.base, ldv_pci_pci_instance_2_#t~ret831#1.offset;havoc ldv_pci_pci_instance_2_#t~ret831#1.base, ldv_pci_pci_instance_2_#t~ret831#1.offset;ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.offset := ldv_pci_pci_instance_2_~tmp~56#1.base, ldv_pci_pci_instance_2_~tmp~56#1.offset; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,926 INFO L272 TraceCheckUtils]: 61: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_pci_pci_instance_2_#t~ret832#1.base, ldv_pci_pci_instance_2_#t~ret832#1.offset := ldv_xmalloc(32); {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:54:42,926 INFO L290 TraceCheckUtils]: 62: Hoare triple {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~25;call #t~malloc909.base, #t~malloc909.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc909.base, #t~malloc909.offset;havoc #t~malloc909.base, #t~malloc909.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {1893#true} is VALID [2022-02-20 22:54:42,926 INFO L272 TraceCheckUtils]: 63: Hoare triple {1893#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,926 INFO L290 TraceCheckUtils]: 64: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,926 INFO L290 TraceCheckUtils]: 65: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,927 INFO L290 TraceCheckUtils]: 66: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,927 INFO L284 TraceCheckUtils]: 67: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,927 INFO L272 TraceCheckUtils]: 68: Hoare triple {1893#true} call #t~ret910 := ldv_is_err(~res~3.base, ~res~3.offset); {1893#true} is VALID [2022-02-20 22:54:42,927 INFO L290 TraceCheckUtils]: 69: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,927 INFO L290 TraceCheckUtils]: 70: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,927 INFO L284 TraceCheckUtils]: 71: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,927 INFO L290 TraceCheckUtils]: 72: Hoare triple {1893#true} assume -9223372036854775808 <= #t~ret910 && #t~ret910 <= 9223372036854775807;~tmp___0~25 := #t~ret910;havoc #t~ret910; {1893#true} is VALID [2022-02-20 22:54:42,928 INFO L272 TraceCheckUtils]: 73: Hoare triple {1893#true} call ldv_assume((if 0 == ~tmp___0~25 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,928 INFO L290 TraceCheckUtils]: 74: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,928 INFO L290 TraceCheckUtils]: 75: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,928 INFO L290 TraceCheckUtils]: 76: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,928 INFO L284 TraceCheckUtils]: 77: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,928 INFO L290 TraceCheckUtils]: 78: Hoare triple {1893#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {1893#true} is VALID [2022-02-20 22:54:42,928 INFO L290 TraceCheckUtils]: 79: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,929 INFO L284 TraceCheckUtils]: 80: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4647#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,929 INFO L290 TraceCheckUtils]: 81: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} ldv_pci_pci_instance_2_~tmp___0~17#1.base, ldv_pci_pci_instance_2_~tmp___0~17#1.offset := ldv_pci_pci_instance_2_#t~ret832#1.base, ldv_pci_pci_instance_2_#t~ret832#1.offset;havoc ldv_pci_pci_instance_2_#t~ret832#1.base, ldv_pci_pci_instance_2_#t~ret832#1.offset;ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.offset := ldv_pci_pci_instance_2_~tmp___0~17#1.base, ldv_pci_pci_instance_2_~tmp___0~17#1.offset; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,930 INFO L272 TraceCheckUtils]: 82: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_pci_pci_instance_2_#t~ret833#1 := ldv_undef_int(); {1893#true} is VALID [2022-02-20 22:54:42,930 INFO L290 TraceCheckUtils]: 83: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,930 INFO L290 TraceCheckUtils]: 84: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,930 INFO L284 TraceCheckUtils]: 85: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4649#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,931 INFO L290 TraceCheckUtils]: 86: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume -2147483648 <= ldv_pci_pci_instance_2_#t~ret833#1 && ldv_pci_pci_instance_2_#t~ret833#1 <= 2147483647;ldv_pci_pci_instance_2_~tmp___2~10#1 := ldv_pci_pci_instance_2_#t~ret833#1;havoc ldv_pci_pci_instance_2_#t~ret833#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,931 INFO L290 TraceCheckUtils]: 87: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume 0 != ldv_pci_pci_instance_2_~tmp___2~10#1;assume { :begin_inline_ldv_pre_probe } true; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,932 INFO L290 TraceCheckUtils]: 88: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume { :end_inline_ldv_pre_probe } true;call ldv_pci_pci_instance_2_#t~mem834#1.base, ldv_pci_pci_instance_2_#t~mem834#1.offset := read~$Pointer$(ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, 32 + ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset, 8);assume { :begin_inline_ldv_pci_instance_probe_2_17 } true;ldv_pci_instance_probe_2_17_#in~arg0#1.base, ldv_pci_instance_probe_2_17_#in~arg0#1.offset, ldv_pci_instance_probe_2_17_#in~arg1#1.base, ldv_pci_instance_probe_2_17_#in~arg1#1.offset, ldv_pci_instance_probe_2_17_#in~arg2#1.base, ldv_pci_instance_probe_2_17_#in~arg2#1.offset := ldv_pci_pci_instance_2_#t~mem834#1.base, ldv_pci_pci_instance_2_#t~mem834#1.offset, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.offset, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.offset;havoc ldv_pci_instance_probe_2_17_#res#1;havoc ldv_pci_instance_probe_2_17_#t~ret816#1, ldv_pci_instance_probe_2_17_~arg0#1.base, ldv_pci_instance_probe_2_17_~arg0#1.offset, ldv_pci_instance_probe_2_17_~arg1#1.base, ldv_pci_instance_probe_2_17_~arg1#1.offset, ldv_pci_instance_probe_2_17_~arg2#1.base, ldv_pci_instance_probe_2_17_~arg2#1.offset, ldv_pci_instance_probe_2_17_~tmp~53#1;ldv_pci_instance_probe_2_17_~arg0#1.base, ldv_pci_instance_probe_2_17_~arg0#1.offset := ldv_pci_instance_probe_2_17_#in~arg0#1.base, ldv_pci_instance_probe_2_17_#in~arg0#1.offset;ldv_pci_instance_probe_2_17_~arg1#1.base, ldv_pci_instance_probe_2_17_~arg1#1.offset := ldv_pci_instance_probe_2_17_#in~arg1#1.base, ldv_pci_instance_probe_2_17_#in~arg1#1.offset;ldv_pci_instance_probe_2_17_~arg2#1.base, ldv_pci_instance_probe_2_17_~arg2#1.offset := ldv_pci_instance_probe_2_17_#in~arg2#1.base, ldv_pci_instance_probe_2_17_#in~arg2#1.offset;havoc ldv_pci_instance_probe_2_17_~tmp~53#1;assume { :begin_inline_via_init_one } true;via_init_one_#in~pcidev#1.base, via_init_one_#in~pcidev#1.offset, via_init_one_#in~id#1.base, via_init_one_#in~id#1.offset := ldv_pci_instance_probe_2_17_~arg1#1.base, ldv_pci_instance_probe_2_17_~arg1#1.offset, ldv_pci_instance_probe_2_17_~arg2#1.base, ldv_pci_instance_probe_2_17_~arg2#1.offset;havoc via_init_one_#res#1;havoc via_init_one_#t~nondet216#1, via_init_one_#t~mem217#1, via_init_one_#t~ret218#1, via_init_one_#t~nondet219#1, via_init_one_#t~ret220#1, via_init_one_#t~nondet221#1, via_init_one_#t~ret222#1, via_init_one_#t~ret223#1, via_init_one_#t~ret224#1, via_init_one_#t~ret226#1, via_init_one_#t~nondet225#1, via_init_one_#t~ret227#1, via_init_one_#t~ret228#1, via_init_one_#t~ret230#1, via_init_one_#t~ret231#1, via_init_one_#t~ret233#1, via_init_one_#t~mem234#1, via_init_one_#t~ret235#1, via_init_one_#t~ret236#1, via_init_one_#t~mem237#1, via_init_one_#t~ret238#1, via_init_one_#t~ret239#1, via_init_one_#t~ret240#1, via_init_one_#t~nondet229#1, via_init_one_#t~nondet232#1, via_init_one_#t~nondet241#1, via_init_one_#t~ret242#1, via_init_one_#t~mem243#1, via_init_one_#t~ret244#1, via_init_one_#t~mem245#1, via_init_one_#t~ret246#1, via_init_one_#t~ret247#1, via_init_one_#t~mem248#1, via_init_one_#t~ret249#1, via_init_one_#t~ret250#1, via_init_one_#t~ret251#1, via_init_one_#t~mem252#1, via_init_one_#t~ret253#1, via_init_one_#t~mem254#1, via_init_one_#t~ret255#1, via_init_one_#t~mem256#1, via_init_one_#t~ret257#1, via_init_one_#t~mem258#1, via_init_one_#t~ret259#1, via_init_one_#t~mem261#1, via_init_one_#t~ret263#1, via_init_one_#t~mem264#1, via_init_one_#t~ret265#1, via_init_one_#t~mem267#1, via_init_one_#t~ret269#1, via_init_one_#t~nondet262#1, via_init_one_#t~nondet268#1, via_init_one_#t~nondet270#1, via_init_one_~pcidev#1.base, via_init_one_~pcidev#1.offset, via_init_one_~id#1.base, via_init_one_~id#1.offset, via_init_one_~rc~1#1, via_init_one_~temp~4#1, via_init_one_~#oldPCI_40~0#1.base, via_init_one_~#oldPCI_40~0#1.offset, via_init_one_~#oldPCI_44~0#1.base, via_init_one_~#oldPCI_44~0#1.offset, via_init_one_~#bTmp~8#1.base, via_init_one_~#bTmp~8#1.offset, via_init_one_~#bTmp1~0#1.base, via_init_one_~#bTmp1~0#1.offset, via_init_one_~Chipset~0#1, via_init_one_~FirDRQ1~0#1, via_init_one_~FirDRQ0~0#1, via_init_one_~FirIRQ~0#1, via_init_one_~FirIOBase~0#1, via_init_one_~#info~0#1.base, via_init_one_~#info~0#1.offset, via_init_one_~tmp~25#1, via_init_one_~tmp___0~5#1, via_init_one_~tmp___1~2#1, via_init_one_~tmp___2~1#1, via_init_one_~tmp___3~0#1, via_init_one_~tmp___4~0#1, via_init_one_~tmp___5~0#1;via_init_one_~pcidev#1.base, via_init_one_~pcidev#1.offset := via_init_one_#in~pcidev#1.base, via_init_one_#in~pcidev#1.offset;via_init_one_~id#1.base, via_init_one_~id#1.offset := via_init_one_#in~id#1.base, via_init_one_#in~id#1.offset;havoc via_init_one_~rc~1#1;havoc via_init_one_~temp~4#1;call via_init_one_~#oldPCI_40~0#1.base, via_init_one_~#oldPCI_40~0#1.offset := #Ultimate.allocOnStack(1);call via_init_one_~#oldPCI_44~0#1.base, via_init_one_~#oldPCI_44~0#1.offset := #Ultimate.allocOnStack(1);call via_init_one_~#bTmp~8#1.base, via_init_one_~#bTmp~8#1.offset := #Ultimate.allocOnStack(1);call via_init_one_~#bTmp1~0#1.base, via_init_one_~#bTmp1~0#1.offset := #Ultimate.allocOnStack(1);havoc via_init_one_~Chipset~0#1;havoc via_init_one_~FirDRQ1~0#1;havoc via_init_one_~FirDRQ0~0#1;havoc via_init_one_~FirIRQ~0#1;havoc via_init_one_~FirIOBase~0#1;call via_init_one_~#info~0#1.base, via_init_one_~#info~0#1.offset := #Ultimate.allocOnStack(72);havoc via_init_one_~tmp~25#1;havoc via_init_one_~tmp___0~5#1;havoc via_init_one_~tmp___1~2#1;havoc via_init_one_~tmp___2~1#1;havoc via_init_one_~tmp___3~0#1;havoc via_init_one_~tmp___4~0#1;havoc via_init_one_~tmp___5~0#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,933 INFO L290 TraceCheckUtils]: 89: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume ~irda_debug~0 % 4294967296 > 1;havoc via_init_one_#t~nondet216#1;call via_init_one_#t~mem217#1 := read~int(via_init_one_~id#1.base, 4 + via_init_one_~id#1.offset, 4);havoc via_init_one_#t~mem217#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,933 INFO L290 TraceCheckUtils]: 90: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume { :begin_inline_pci_enable_device } true;pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset := via_init_one_~pcidev#1.base, via_init_one_~pcidev#1.offset;havoc pci_enable_device_#res#1;havoc pci_enable_device_#t~nondet1003#1, pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset;pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset := pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset;assume -2147483648 <= pci_enable_device_#t~nondet1003#1 && pci_enable_device_#t~nondet1003#1 <= 2147483647;pci_enable_device_#res#1 := pci_enable_device_#t~nondet1003#1;havoc pci_enable_device_#t~nondet1003#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,934 INFO L290 TraceCheckUtils]: 91: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} via_init_one_#t~ret218#1 := pci_enable_device_#res#1;assume { :end_inline_pci_enable_device } true;assume -2147483648 <= via_init_one_#t~ret218#1 && via_init_one_#t~ret218#1 <= 2147483647;via_init_one_~rc~1#1 := via_init_one_#t~ret218#1;havoc via_init_one_#t~ret218#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,934 INFO L290 TraceCheckUtils]: 92: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume 0 != via_init_one_~rc~1#1;havoc via_init_one_#t~nondet219#1;via_init_one_#res#1 := -19;call ULTIMATE.dealloc(via_init_one_~#oldPCI_40~0#1.base, via_init_one_~#oldPCI_40~0#1.offset);havoc via_init_one_~#oldPCI_40~0#1.base, via_init_one_~#oldPCI_40~0#1.offset;call ULTIMATE.dealloc(via_init_one_~#oldPCI_44~0#1.base, via_init_one_~#oldPCI_44~0#1.offset);havoc via_init_one_~#oldPCI_44~0#1.base, via_init_one_~#oldPCI_44~0#1.offset;call ULTIMATE.dealloc(via_init_one_~#bTmp~8#1.base, via_init_one_~#bTmp~8#1.offset);havoc via_init_one_~#bTmp~8#1.base, via_init_one_~#bTmp~8#1.offset;call ULTIMATE.dealloc(via_init_one_~#bTmp1~0#1.base, via_init_one_~#bTmp1~0#1.offset);havoc via_init_one_~#bTmp1~0#1.base, via_init_one_~#bTmp1~0#1.offset;call ULTIMATE.dealloc(via_init_one_~#info~0#1.base, via_init_one_~#info~0#1.offset);havoc via_init_one_~#info~0#1.base, via_init_one_~#info~0#1.offset; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,935 INFO L290 TraceCheckUtils]: 93: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} ldv_pci_instance_probe_2_17_#t~ret816#1 := via_init_one_#res#1;assume { :end_inline_via_init_one } true;assume -2147483648 <= ldv_pci_instance_probe_2_17_#t~ret816#1 && ldv_pci_instance_probe_2_17_#t~ret816#1 <= 2147483647;ldv_pci_instance_probe_2_17_~tmp~53#1 := ldv_pci_instance_probe_2_17_#t~ret816#1;havoc ldv_pci_instance_probe_2_17_#t~ret816#1;ldv_pci_instance_probe_2_17_#res#1 := ldv_pci_instance_probe_2_17_~tmp~53#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,935 INFO L290 TraceCheckUtils]: 94: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} ldv_pci_pci_instance_2_#t~ret835#1 := ldv_pci_instance_probe_2_17_#res#1;assume { :end_inline_ldv_pci_instance_probe_2_17 } true;assume -2147483648 <= ldv_pci_pci_instance_2_#t~ret835#1 && ldv_pci_pci_instance_2_#t~ret835#1 <= 2147483647;ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1 := ldv_pci_pci_instance_2_#t~ret835#1;havoc ldv_pci_pci_instance_2_#t~mem834#1.base, ldv_pci_pci_instance_2_#t~mem834#1.offset;havoc ldv_pci_pci_instance_2_#t~ret835#1;assume { :begin_inline_ldv_post_probe } true;ldv_post_probe_#in~probe_ret_val#1 := ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1;havoc ldv_post_probe_#res#1;havoc ldv_post_probe_#t~ret889#1, ldv_post_probe_~probe_ret_val#1, ldv_post_probe_~tmp~73#1;ldv_post_probe_~probe_ret_val#1 := ldv_post_probe_#in~probe_ret_val#1;havoc ldv_post_probe_~tmp~73#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,935 INFO L272 TraceCheckUtils]: 95: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_post_probe_#t~ret889#1 := ldv_filter_positive_int(ldv_post_probe_~probe_ret_val#1); {1893#true} is VALID [2022-02-20 22:54:42,935 INFO L290 TraceCheckUtils]: 96: Hoare triple {1893#true} ~val := #in~val; {1893#true} is VALID [2022-02-20 22:54:42,935 INFO L272 TraceCheckUtils]: 97: Hoare triple {1893#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,936 INFO L290 TraceCheckUtils]: 98: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,936 INFO L290 TraceCheckUtils]: 99: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,936 INFO L290 TraceCheckUtils]: 100: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,936 INFO L284 TraceCheckUtils]: 101: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,936 INFO L290 TraceCheckUtils]: 102: Hoare triple {1893#true} #res := ~val; {1893#true} is VALID [2022-02-20 22:54:42,936 INFO L290 TraceCheckUtils]: 103: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,937 INFO L284 TraceCheckUtils]: 104: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4717#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,937 INFO L290 TraceCheckUtils]: 105: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume -2147483648 <= ldv_post_probe_#t~ret889#1 && ldv_post_probe_#t~ret889#1 <= 2147483647;ldv_post_probe_~tmp~73#1 := ldv_post_probe_#t~ret889#1;havoc ldv_post_probe_#t~ret889#1;ldv_post_probe_#res#1 := ldv_post_probe_~tmp~73#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,938 INFO L290 TraceCheckUtils]: 106: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} ldv_pci_pci_instance_2_#t~ret836#1 := ldv_post_probe_#res#1;assume { :end_inline_ldv_post_probe } true;assume -2147483648 <= ldv_pci_pci_instance_2_#t~ret836#1 && ldv_pci_pci_instance_2_#t~ret836#1 <= 2147483647;ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1 := ldv_pci_pci_instance_2_#t~ret836#1;havoc ldv_pci_pci_instance_2_#t~ret836#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,938 INFO L272 TraceCheckUtils]: 107: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_pci_pci_instance_2_#t~ret837#1 := ldv_undef_int(); {1893#true} is VALID [2022-02-20 22:54:42,938 INFO L290 TraceCheckUtils]: 108: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,938 INFO L290 TraceCheckUtils]: 109: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,939 INFO L284 TraceCheckUtils]: 110: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4719#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,939 INFO L290 TraceCheckUtils]: 111: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume -2147483648 <= ldv_pci_pci_instance_2_#t~ret837#1 && ldv_pci_pci_instance_2_#t~ret837#1 <= 2147483647;ldv_pci_pci_instance_2_~tmp___1~12#1 := ldv_pci_pci_instance_2_#t~ret837#1;havoc ldv_pci_pci_instance_2_#t~ret837#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,939 INFO L290 TraceCheckUtils]: 112: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume 0 != ldv_pci_pci_instance_2_~tmp___1~12#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,940 INFO L272 TraceCheckUtils]: 113: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_assume((if 0 == ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,940 INFO L290 TraceCheckUtils]: 114: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,940 INFO L290 TraceCheckUtils]: 115: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,940 INFO L290 TraceCheckUtils]: 116: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,940 INFO L284 TraceCheckUtils]: 117: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4721#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,941 INFO L272 TraceCheckUtils]: 118: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_pci_pci_instance_2_#t~ret838#1 := ldv_undef_int(); {1893#true} is VALID [2022-02-20 22:54:42,941 INFO L290 TraceCheckUtils]: 119: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,941 INFO L290 TraceCheckUtils]: 120: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,941 INFO L284 TraceCheckUtils]: 121: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4729#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,942 INFO L290 TraceCheckUtils]: 122: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume -2147483648 <= ldv_pci_pci_instance_2_#t~ret838#1 && ldv_pci_pci_instance_2_#t~ret838#1 <= 2147483647;ldv_pci_pci_instance_2_~tmp___3~7#1 := ldv_pci_pci_instance_2_#t~ret838#1;havoc ldv_pci_pci_instance_2_#t~ret838#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,942 INFO L290 TraceCheckUtils]: 123: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume !(1 == ldv_pci_pci_instance_2_~tmp___3~7#1); {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,943 INFO L290 TraceCheckUtils]: 124: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume 2 == ldv_pci_pci_instance_2_~tmp___3~7#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,943 INFO L290 TraceCheckUtils]: 125: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_pci_pci_instance_2_#t~mem839#1.base, ldv_pci_pci_instance_2_#t~mem839#1.offset := read~$Pointer$(ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, 48 + ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset, 8); {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,943 INFO L290 TraceCheckUtils]: 126: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume !(0 != (ldv_pci_pci_instance_2_#t~mem839#1.base + ldv_pci_pci_instance_2_#t~mem839#1.offset) % 18446744073709551616);havoc ldv_pci_pci_instance_2_#t~mem839#1.base, ldv_pci_pci_instance_2_#t~mem839#1.offset; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,944 INFO L272 TraceCheckUtils]: 127: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_pci_pci_instance_2_#t~ret843#1 := ldv_filter_err_code(ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1); {1893#true} is VALID [2022-02-20 22:54:42,944 INFO L290 TraceCheckUtils]: 128: Hoare triple {1893#true} ~ret_val := #in~ret_val;havoc ~tmp~74; {1893#true} is VALID [2022-02-20 22:54:42,944 INFO L272 TraceCheckUtils]: 129: Hoare triple {1893#true} call #t~ret890 := ldv_filter_positive_int(~ret_val); {1893#true} is VALID [2022-02-20 22:54:42,944 INFO L290 TraceCheckUtils]: 130: Hoare triple {1893#true} ~val := #in~val; {1893#true} is VALID [2022-02-20 22:54:42,944 INFO L272 TraceCheckUtils]: 131: Hoare triple {1893#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,944 INFO L290 TraceCheckUtils]: 132: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,944 INFO L290 TraceCheckUtils]: 133: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,944 INFO L290 TraceCheckUtils]: 134: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,945 INFO L284 TraceCheckUtils]: 135: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,945 INFO L290 TraceCheckUtils]: 136: Hoare triple {1893#true} #res := ~val; {1893#true} is VALID [2022-02-20 22:54:42,945 INFO L290 TraceCheckUtils]: 137: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,945 INFO L284 TraceCheckUtils]: 138: Hoare quadruple {1893#true} {1893#true} #3627#return; {1893#true} is VALID [2022-02-20 22:54:42,945 INFO L290 TraceCheckUtils]: 139: Hoare triple {1893#true} assume -2147483648 <= #t~ret890 && #t~ret890 <= 2147483647;~tmp~74 := #t~ret890;havoc #t~ret890;#res := ~tmp~74; {1893#true} is VALID [2022-02-20 22:54:42,945 INFO L290 TraceCheckUtils]: 140: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,946 INFO L284 TraceCheckUtils]: 141: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4733#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,946 INFO L290 TraceCheckUtils]: 142: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume -2147483648 <= ldv_pci_pci_instance_2_#t~ret843#1 && ldv_pci_pci_instance_2_#t~ret843#1 <= 2147483647;ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1 := ldv_pci_pci_instance_2_#t~ret843#1;havoc ldv_pci_pci_instance_2_#t~ret843#1;call ldv_pci_pci_instance_2_#t~mem844#1.base, ldv_pci_pci_instance_2_#t~mem844#1.offset := read~$Pointer$(ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, 56 + ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset, 8); {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,947 INFO L290 TraceCheckUtils]: 143: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume !(0 != (ldv_pci_pci_instance_2_#t~mem844#1.base + ldv_pci_pci_instance_2_#t~mem844#1.offset) % 18446744073709551616);havoc ldv_pci_pci_instance_2_#t~mem844#1.base, ldv_pci_pci_instance_2_#t~mem844#1.offset; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,947 INFO L272 TraceCheckUtils]: 144: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_pci_pci_instance_2_#t~ret848#1 := ldv_filter_err_code(ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1); {1893#true} is VALID [2022-02-20 22:54:42,947 INFO L290 TraceCheckUtils]: 145: Hoare triple {1893#true} ~ret_val := #in~ret_val;havoc ~tmp~74; {1893#true} is VALID [2022-02-20 22:54:42,947 INFO L272 TraceCheckUtils]: 146: Hoare triple {1893#true} call #t~ret890 := ldv_filter_positive_int(~ret_val); {1893#true} is VALID [2022-02-20 22:54:42,947 INFO L290 TraceCheckUtils]: 147: Hoare triple {1893#true} ~val := #in~val; {1893#true} is VALID [2022-02-20 22:54:42,947 INFO L272 TraceCheckUtils]: 148: Hoare triple {1893#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,948 INFO L290 TraceCheckUtils]: 149: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,948 INFO L290 TraceCheckUtils]: 150: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,948 INFO L290 TraceCheckUtils]: 151: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,948 INFO L284 TraceCheckUtils]: 152: Hoare quadruple {1893#true} {1893#true} #4163#return; {1893#true} is VALID [2022-02-20 22:54:42,948 INFO L290 TraceCheckUtils]: 153: Hoare triple {1893#true} #res := ~val; {1893#true} is VALID [2022-02-20 22:54:42,948 INFO L290 TraceCheckUtils]: 154: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,948 INFO L284 TraceCheckUtils]: 155: Hoare quadruple {1893#true} {1893#true} #3627#return; {1893#true} is VALID [2022-02-20 22:54:42,948 INFO L290 TraceCheckUtils]: 156: Hoare triple {1893#true} assume -2147483648 <= #t~ret890 && #t~ret890 <= 2147483647;~tmp~74 := #t~ret890;havoc #t~ret890;#res := ~tmp~74; {1893#true} is VALID [2022-02-20 22:54:42,949 INFO L290 TraceCheckUtils]: 157: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,949 INFO L284 TraceCheckUtils]: 158: Hoare quadruple {1893#true} {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #4737#return; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,950 INFO L290 TraceCheckUtils]: 159: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume -2147483648 <= ldv_pci_pci_instance_2_#t~ret848#1 && ldv_pci_pci_instance_2_#t~ret848#1 <= 2147483647;ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1 := ldv_pci_pci_instance_2_#t~ret848#1;havoc ldv_pci_pci_instance_2_#t~ret848#1;call ldv_pci_pci_instance_2_#t~mem849#1.base, ldv_pci_pci_instance_2_#t~mem849#1.offset := read~$Pointer$(ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, 64 + ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset, 8); {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,950 INFO L290 TraceCheckUtils]: 160: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume 0 != (ldv_pci_pci_instance_2_#t~mem849#1.base + ldv_pci_pci_instance_2_#t~mem849#1.offset) % 18446744073709551616;havoc ldv_pci_pci_instance_2_#t~mem849#1.base, ldv_pci_pci_instance_2_#t~mem849#1.offset;call ldv_pci_pci_instance_2_#t~mem850#1.base, ldv_pci_pci_instance_2_#t~mem850#1.offset := read~$Pointer$(ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, 64 + ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset, 8);assume { :begin_inline_ldv_pci_instance_resume_early_2_6 } true;ldv_pci_instance_resume_early_2_6_#in~arg0#1.base, ldv_pci_instance_resume_early_2_6_#in~arg0#1.offset, ldv_pci_instance_resume_early_2_6_#in~arg1#1.base, ldv_pci_instance_resume_early_2_6_#in~arg1#1.offset := ldv_pci_pci_instance_2_#t~mem850#1.base, ldv_pci_pci_instance_2_#t~mem850#1.offset, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.offset;havoc ldv_pci_instance_resume_early_2_6_#t~ret820#1, ldv_pci_instance_resume_early_2_6_~arg0#1.base, ldv_pci_instance_resume_early_2_6_~arg0#1.offset, ldv_pci_instance_resume_early_2_6_~arg1#1.base, ldv_pci_instance_resume_early_2_6_~arg1#1.offset;ldv_pci_instance_resume_early_2_6_~arg0#1.base, ldv_pci_instance_resume_early_2_6_~arg0#1.offset := ldv_pci_instance_resume_early_2_6_#in~arg0#1.base, ldv_pci_instance_resume_early_2_6_#in~arg0#1.offset;ldv_pci_instance_resume_early_2_6_~arg1#1.base, ldv_pci_instance_resume_early_2_6_~arg1#1.offset := ldv_pci_instance_resume_early_2_6_#in~arg1#1.base, ldv_pci_instance_resume_early_2_6_#in~arg1#1.offset; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,951 INFO L272 TraceCheckUtils]: 161: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call ldv_pci_instance_resume_early_2_6_#t~ret820#1 := ##fun~$Pointer$~TO~int(ldv_pci_instance_resume_early_2_6_~arg1#1.base, ldv_pci_instance_resume_early_2_6_~arg1#1.offset, ldv_pci_instance_resume_early_2_6_~arg0#1.base, ldv_pci_instance_resume_early_2_6_~arg0#1.offset); {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,951 INFO L290 TraceCheckUtils]: 162: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} #~819.base, #~819.offset := #in~819.base, #in~819.offset; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,952 INFO L290 TraceCheckUtils]: 163: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume !(#in~#fp.base == #funAddr~via_ircc_net_close.base && #in~#fp.offset == #funAddr~via_ircc_net_close.offset); {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,952 INFO L272 TraceCheckUtils]: 164: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} call #t~ret1014 := via_ircc_net_open(#~819.base, #~819.offset); {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,953 INFO L290 TraceCheckUtils]: 165: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~self~5#1.base, ~self~5#1.offset;havoc ~iobase~10#1;call ~#hwname~0#1.base, ~#hwname~0#1.offset := #Ultimate.allocOnStack(32);havoc ~tmp~41#1.base, ~tmp~41#1.offset;havoc ~tmp___0~14#1;havoc ~tmp___1~10#1;havoc ~tmp___2~8#1;havoc ~tmp___3~5#1;havoc ~tmp___4~5#1;havoc ~tmp___5~3#1; {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} is VALID [2022-02-20 22:54:42,953 INFO L290 TraceCheckUtils]: 166: Hoare triple {1895#(not (<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296)))))} assume !(~irda_debug~0 % 4294967296 > 2); {1894#false} is VALID [2022-02-20 22:54:42,954 INFO L290 TraceCheckUtils]: 167: Hoare triple {1894#false} assume !(0 == (~dev#1.base + ~dev#1.offset) % 18446744073709551616); {1894#false} is VALID [2022-02-20 22:54:42,954 INFO L272 TraceCheckUtils]: 168: Hoare triple {1894#false} call #t~ret739#1.base, #t~ret739#1.offset := netdev_priv(~dev#1.base, ~dev#1.offset); {1893#true} is VALID [2022-02-20 22:54:42,954 INFO L290 TraceCheckUtils]: 169: Hoare triple {1893#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1893#true} is VALID [2022-02-20 22:54:42,954 INFO L290 TraceCheckUtils]: 170: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,954 INFO L284 TraceCheckUtils]: 171: Hoare quadruple {1893#true} {1894#false} #4165#return; {1894#false} is VALID [2022-02-20 22:54:42,954 INFO L290 TraceCheckUtils]: 172: Hoare triple {1894#false} ~tmp~41#1.base, ~tmp~41#1.offset := #t~ret739#1.base, #t~ret739#1.offset;havoc #t~ret739#1.base, #t~ret739#1.offset;~self~5#1.base, ~self~5#1.offset := ~tmp~41#1.base, ~tmp~41#1.offset;call write~int(0, ~dev#1.base, 260 + ~dev#1.offset, 8); {1894#false} is VALID [2022-02-20 22:54:42,954 INFO L290 TraceCheckUtils]: 173: Hoare triple {1894#false} assume !(0 == (~self~5#1.base + ~self~5#1.offset) % 18446744073709551616);call #t~mem741#1 := read~int(~self~5#1.base, 292 + ~self~5#1.offset, 4);~iobase~10#1 := #t~mem741#1;havoc #t~mem741#1;call #t~mem742#1 := read~int(~self~5#1.base, 308 + ~self~5#1.offset, 4);assume { :begin_inline_ldv_request_irq_102 } true;ldv_request_irq_102_#in~irq#1, ldv_request_irq_102_#in~handler#1.base, ldv_request_irq_102_#in~handler#1.offset, ldv_request_irq_102_#in~flags#1, ldv_request_irq_102_#in~name#1.base, ldv_request_irq_102_#in~name#1.offset, ldv_request_irq_102_#in~dev#1.base, ldv_request_irq_102_#in~dev#1.offset := #t~mem742#1, #funAddr~via_ircc_interrupt.base, #funAddr~via_ircc_interrupt.offset, 0, ~dev#1.base, ~dev#1.offset, ~dev#1.base, ~dev#1.offset;havoc ldv_request_irq_102_#res#1;havoc ldv_request_irq_102_#t~ret875#1, ldv_request_irq_102_#t~ret876#1, ldv_request_irq_102_~irq#1, ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset, ldv_request_irq_102_~flags#1, ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset, ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset, ldv_request_irq_102_~ldv_func_res~2#1, ldv_request_irq_102_~tmp~66#1, ldv_request_irq_102_~tmp___0~21#1;ldv_request_irq_102_~irq#1 := ldv_request_irq_102_#in~irq#1;ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset := ldv_request_irq_102_#in~handler#1.base, ldv_request_irq_102_#in~handler#1.offset;ldv_request_irq_102_~flags#1 := ldv_request_irq_102_#in~flags#1;ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset := ldv_request_irq_102_#in~name#1.base, ldv_request_irq_102_#in~name#1.offset;ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset := ldv_request_irq_102_#in~dev#1.base, ldv_request_irq_102_#in~dev#1.offset;havoc ldv_request_irq_102_~ldv_func_res~2#1;havoc ldv_request_irq_102_~tmp~66#1;havoc ldv_request_irq_102_~tmp___0~21#1;assume { :begin_inline_request_irq } true;request_irq_#in~irq#1, request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset, request_irq_#in~flags#1, request_irq_#in~name#1.base, request_irq_#in~name#1.offset, request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset := ldv_request_irq_102_~irq#1, ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset, ldv_request_irq_102_~flags#1, ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset, ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset;havoc request_irq_#res#1;havoc request_irq_#t~ret106#1, request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset, request_irq_~tmp~13#1;request_irq_~irq#1 := request_irq_#in~irq#1;request_irq_~handler#1.base, request_irq_~handler#1.offset := request_irq_#in~handler#1.base, request_irq_#in~handler#1.offset;request_irq_~flags#1 := request_irq_#in~flags#1;request_irq_~name#1.base, request_irq_~name#1.offset := request_irq_#in~name#1.base, request_irq_#in~name#1.offset;request_irq_~dev#1.base, request_irq_~dev#1.offset := request_irq_#in~dev#1.base, request_irq_#in~dev#1.offset;havoc request_irq_~tmp~13#1;assume { :begin_inline_request_threaded_irq } true;request_threaded_irq_#in~arg0#1, request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset, request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset, request_threaded_irq_#in~arg3#1, request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset, request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset := request_irq_~irq#1, request_irq_~handler#1.base, request_irq_~handler#1.offset, 0, 0, request_irq_~flags#1, request_irq_~name#1.base, request_irq_~name#1.offset, request_irq_~dev#1.base, request_irq_~dev#1.offset;havoc request_threaded_irq_#res#1;havoc request_threaded_irq_#t~nondet1007#1, request_threaded_irq_~arg0#1, request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset, request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset, request_threaded_irq_~arg3#1, request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset, request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset;request_threaded_irq_~arg0#1 := request_threaded_irq_#in~arg0#1;request_threaded_irq_~arg1#1.base, request_threaded_irq_~arg1#1.offset := request_threaded_irq_#in~arg1#1.base, request_threaded_irq_#in~arg1#1.offset;request_threaded_irq_~arg2#1.base, request_threaded_irq_~arg2#1.offset := request_threaded_irq_#in~arg2#1.base, request_threaded_irq_#in~arg2#1.offset;request_threaded_irq_~arg3#1 := request_threaded_irq_#in~arg3#1;request_threaded_irq_~arg4#1.base, request_threaded_irq_~arg4#1.offset := request_threaded_irq_#in~arg4#1.base, request_threaded_irq_#in~arg4#1.offset;request_threaded_irq_~arg5#1.base, request_threaded_irq_~arg5#1.offset := request_threaded_irq_#in~arg5#1.base, request_threaded_irq_#in~arg5#1.offset;assume -2147483648 <= request_threaded_irq_#t~nondet1007#1 && request_threaded_irq_#t~nondet1007#1 <= 2147483647;request_threaded_irq_#res#1 := request_threaded_irq_#t~nondet1007#1;havoc request_threaded_irq_#t~nondet1007#1; {1894#false} is VALID [2022-02-20 22:54:42,955 INFO L290 TraceCheckUtils]: 174: Hoare triple {1894#false} request_irq_#t~ret106#1 := request_threaded_irq_#res#1;assume { :end_inline_request_threaded_irq } true;assume -2147483648 <= request_irq_#t~ret106#1 && request_irq_#t~ret106#1 <= 2147483647;request_irq_~tmp~13#1 := request_irq_#t~ret106#1;havoc request_irq_#t~ret106#1;request_irq_#res#1 := request_irq_~tmp~13#1; {1894#false} is VALID [2022-02-20 22:54:42,955 INFO L290 TraceCheckUtils]: 175: Hoare triple {1894#false} ldv_request_irq_102_#t~ret875#1 := request_irq_#res#1;assume { :end_inline_request_irq } true;assume -2147483648 <= ldv_request_irq_102_#t~ret875#1 && ldv_request_irq_102_#t~ret875#1 <= 2147483647;ldv_request_irq_102_~tmp~66#1 := ldv_request_irq_102_#t~ret875#1;havoc ldv_request_irq_102_#t~ret875#1;ldv_request_irq_102_~ldv_func_res~2#1 := ldv_request_irq_102_~tmp~66#1;assume { :begin_inline_ldv_request_irq } true;ldv_request_irq_#in~arg0#1, ldv_request_irq_#in~arg1#1, ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset, ldv_request_irq_#in~arg3#1, ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset, ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset := ldv_request_irq_102_~ldv_func_res~2#1, ldv_request_irq_102_~irq#1, ldv_request_irq_102_~handler#1.base, ldv_request_irq_102_~handler#1.offset, ldv_request_irq_102_~flags#1, ldv_request_irq_102_~name#1.base, ldv_request_irq_102_~name#1.offset, ldv_request_irq_102_~dev#1.base, ldv_request_irq_102_~dev#1.offset;havoc ldv_request_irq_#res#1;havoc ldv_request_irq_#t~ret863#1, ldv_request_irq_~arg0#1, ldv_request_irq_~arg1#1, ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset, ldv_request_irq_~arg3#1, ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset, ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset, ldv_request_irq_~ldv_6_callback_handler~0#1.base, ldv_request_irq_~ldv_6_callback_handler~0#1.offset, ldv_request_irq_~ldv_6_data_data~0#1.base, ldv_request_irq_~ldv_6_data_data~0#1.offset, ldv_request_irq_~ldv_6_line_line~0#1, ldv_request_irq_~ldv_6_thread_thread~0#1.base, ldv_request_irq_~ldv_6_thread_thread~0#1.offset, ldv_request_irq_~tmp~59#1;ldv_request_irq_~arg0#1 := ldv_request_irq_#in~arg0#1;ldv_request_irq_~arg1#1 := ldv_request_irq_#in~arg1#1;ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset := ldv_request_irq_#in~arg2#1.base, ldv_request_irq_#in~arg2#1.offset;ldv_request_irq_~arg3#1 := ldv_request_irq_#in~arg3#1;ldv_request_irq_~arg4#1.base, ldv_request_irq_~arg4#1.offset := ldv_request_irq_#in~arg4#1.base, ldv_request_irq_#in~arg4#1.offset;ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset := ldv_request_irq_#in~arg5#1.base, ldv_request_irq_#in~arg5#1.offset;havoc ldv_request_irq_~ldv_6_callback_handler~0#1.base, ldv_request_irq_~ldv_6_callback_handler~0#1.offset;havoc ldv_request_irq_~ldv_6_data_data~0#1.base, ldv_request_irq_~ldv_6_data_data~0#1.offset;havoc ldv_request_irq_~ldv_6_line_line~0#1;havoc ldv_request_irq_~ldv_6_thread_thread~0#1.base, ldv_request_irq_~ldv_6_thread_thread~0#1.offset;havoc ldv_request_irq_~tmp~59#1; {1894#false} is VALID [2022-02-20 22:54:42,955 INFO L272 TraceCheckUtils]: 176: Hoare triple {1894#false} call ldv_request_irq_#t~ret863#1 := ldv_undef_int(); {1893#true} is VALID [2022-02-20 22:54:42,955 INFO L290 TraceCheckUtils]: 177: Hoare triple {1893#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet913 && #t~nondet913 <= 2147483647;~tmp~80 := #t~nondet913;havoc #t~nondet913;#res := ~tmp~80; {1893#true} is VALID [2022-02-20 22:54:42,955 INFO L290 TraceCheckUtils]: 178: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,955 INFO L284 TraceCheckUtils]: 179: Hoare quadruple {1893#true} {1894#false} #4167#return; {1894#false} is VALID [2022-02-20 22:54:42,956 INFO L290 TraceCheckUtils]: 180: Hoare triple {1894#false} assume -2147483648 <= ldv_request_irq_#t~ret863#1 && ldv_request_irq_#t~ret863#1 <= 2147483647;ldv_request_irq_~tmp~59#1 := ldv_request_irq_#t~ret863#1;havoc ldv_request_irq_#t~ret863#1; {1894#false} is VALID [2022-02-20 22:54:42,956 INFO L290 TraceCheckUtils]: 181: Hoare triple {1894#false} assume 0 != ldv_request_irq_~tmp~59#1; {1894#false} is VALID [2022-02-20 22:54:42,956 INFO L272 TraceCheckUtils]: 182: Hoare triple {1894#false} call ldv_assume((if 0 == ldv_request_irq_~arg0#1 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,956 INFO L290 TraceCheckUtils]: 183: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,956 INFO L290 TraceCheckUtils]: 184: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,956 INFO L290 TraceCheckUtils]: 185: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,956 INFO L284 TraceCheckUtils]: 186: Hoare quadruple {1893#true} {1894#false} #4169#return; {1894#false} is VALID [2022-02-20 22:54:42,956 INFO L290 TraceCheckUtils]: 187: Hoare triple {1894#false} ldv_request_irq_~ldv_6_line_line~0#1 := (if ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 <= 2147483647 then ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 else ldv_request_irq_~arg1#1 % 4294967296 % 4294967296 - 4294967296);ldv_request_irq_~ldv_6_callback_handler~0#1.base, ldv_request_irq_~ldv_6_callback_handler~0#1.offset := ldv_request_irq_~arg2#1.base, ldv_request_irq_~arg2#1.offset;ldv_request_irq_~ldv_6_thread_thread~0#1.base, ldv_request_irq_~ldv_6_thread_thread~0#1.offset := 0, 0;ldv_request_irq_~ldv_6_data_data~0#1.base, ldv_request_irq_~ldv_6_data_data~0#1.offset := ldv_request_irq_~arg5#1.base, ldv_request_irq_~arg5#1.offset;assume { :begin_inline_ldv_dispatch_irq_register_6_2 } true;ldv_dispatch_irq_register_6_2_#in~arg0#1, ldv_dispatch_irq_register_6_2_#in~arg1#1.base, ldv_dispatch_irq_register_6_2_#in~arg1#1.offset, ldv_dispatch_irq_register_6_2_#in~arg2#1.base, ldv_dispatch_irq_register_6_2_#in~arg2#1.offset, ldv_dispatch_irq_register_6_2_#in~arg3#1.base, ldv_dispatch_irq_register_6_2_#in~arg3#1.offset := ldv_request_irq_~ldv_6_line_line~0#1, ldv_request_irq_~ldv_6_callback_handler~0#1.base, ldv_request_irq_~ldv_6_callback_handler~0#1.offset, ldv_request_irq_~ldv_6_thread_thread~0#1.base, ldv_request_irq_~ldv_6_thread_thread~0#1.offset, ldv_request_irq_~ldv_6_data_data~0#1.base, ldv_request_irq_~ldv_6_data_data~0#1.offset;havoc ldv_dispatch_irq_register_6_2_#t~ret795#1.base, ldv_dispatch_irq_register_6_2_#t~ret795#1.offset, ldv_dispatch_irq_register_6_2_~arg0#1, ldv_dispatch_irq_register_6_2_~arg1#1.base, ldv_dispatch_irq_register_6_2_~arg1#1.offset, ldv_dispatch_irq_register_6_2_~arg2#1.base, ldv_dispatch_irq_register_6_2_~arg2#1.offset, ldv_dispatch_irq_register_6_2_~arg3#1.base, ldv_dispatch_irq_register_6_2_~arg3#1.offset, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.base, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.offset, ldv_dispatch_irq_register_6_2_~tmp~46#1.base, ldv_dispatch_irq_register_6_2_~tmp~46#1.offset;ldv_dispatch_irq_register_6_2_~arg0#1 := ldv_dispatch_irq_register_6_2_#in~arg0#1;ldv_dispatch_irq_register_6_2_~arg1#1.base, ldv_dispatch_irq_register_6_2_~arg1#1.offset := ldv_dispatch_irq_register_6_2_#in~arg1#1.base, ldv_dispatch_irq_register_6_2_#in~arg1#1.offset;ldv_dispatch_irq_register_6_2_~arg2#1.base, ldv_dispatch_irq_register_6_2_~arg2#1.offset := ldv_dispatch_irq_register_6_2_#in~arg2#1.base, ldv_dispatch_irq_register_6_2_#in~arg2#1.offset;ldv_dispatch_irq_register_6_2_~arg3#1.base, ldv_dispatch_irq_register_6_2_~arg3#1.offset := ldv_dispatch_irq_register_6_2_#in~arg3#1.base, ldv_dispatch_irq_register_6_2_#in~arg3#1.offset;havoc ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.base, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.offset;havoc ldv_dispatch_irq_register_6_2_~tmp~46#1.base, ldv_dispatch_irq_register_6_2_~tmp~46#1.offset; {1894#false} is VALID [2022-02-20 22:54:42,957 INFO L272 TraceCheckUtils]: 188: Hoare triple {1894#false} call ldv_dispatch_irq_register_6_2_#t~ret795#1.base, ldv_dispatch_irq_register_6_2_#t~ret795#1.offset := ldv_xmalloc(40); {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:54:42,957 INFO L290 TraceCheckUtils]: 189: Hoare triple {2098#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~25;call #t~malloc909.base, #t~malloc909.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc909.base, #t~malloc909.offset;havoc #t~malloc909.base, #t~malloc909.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {1893#true} is VALID [2022-02-20 22:54:42,957 INFO L272 TraceCheckUtils]: 190: Hoare triple {1893#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,957 INFO L290 TraceCheckUtils]: 191: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,957 INFO L290 TraceCheckUtils]: 192: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,957 INFO L290 TraceCheckUtils]: 193: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,957 INFO L284 TraceCheckUtils]: 194: Hoare quadruple {1893#true} {1893#true} #4003#return; {1893#true} is VALID [2022-02-20 22:54:42,958 INFO L272 TraceCheckUtils]: 195: Hoare triple {1893#true} call #t~ret910 := ldv_is_err(~res~3.base, ~res~3.offset); {1893#true} is VALID [2022-02-20 22:54:42,958 INFO L290 TraceCheckUtils]: 196: Hoare triple {1893#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {1893#true} is VALID [2022-02-20 22:54:42,958 INFO L290 TraceCheckUtils]: 197: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,958 INFO L284 TraceCheckUtils]: 198: Hoare quadruple {1893#true} {1893#true} #4005#return; {1893#true} is VALID [2022-02-20 22:54:42,958 INFO L290 TraceCheckUtils]: 199: Hoare triple {1893#true} assume -9223372036854775808 <= #t~ret910 && #t~ret910 <= 9223372036854775807;~tmp___0~25 := #t~ret910;havoc #t~ret910; {1893#true} is VALID [2022-02-20 22:54:42,958 INFO L272 TraceCheckUtils]: 200: Hoare triple {1893#true} call ldv_assume((if 0 == ~tmp___0~25 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,958 INFO L290 TraceCheckUtils]: 201: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,959 INFO L290 TraceCheckUtils]: 202: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,959 INFO L290 TraceCheckUtils]: 203: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,959 INFO L284 TraceCheckUtils]: 204: Hoare quadruple {1893#true} {1893#true} #4007#return; {1893#true} is VALID [2022-02-20 22:54:42,959 INFO L290 TraceCheckUtils]: 205: Hoare triple {1893#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {1893#true} is VALID [2022-02-20 22:54:42,959 INFO L290 TraceCheckUtils]: 206: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,959 INFO L284 TraceCheckUtils]: 207: Hoare quadruple {1893#true} {1894#false} #4171#return; {1894#false} is VALID [2022-02-20 22:54:42,959 INFO L290 TraceCheckUtils]: 208: Hoare triple {1894#false} ldv_dispatch_irq_register_6_2_~tmp~46#1.base, ldv_dispatch_irq_register_6_2_~tmp~46#1.offset := ldv_dispatch_irq_register_6_2_#t~ret795#1.base, ldv_dispatch_irq_register_6_2_#t~ret795#1.offset;havoc ldv_dispatch_irq_register_6_2_#t~ret795#1.base, ldv_dispatch_irq_register_6_2_#t~ret795#1.offset;ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.base, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.offset := ldv_dispatch_irq_register_6_2_~tmp~46#1.base, ldv_dispatch_irq_register_6_2_~tmp~46#1.offset;call write~int(ldv_dispatch_irq_register_6_2_~arg0#1, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.base, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.offset, 4);call write~$Pointer$(ldv_dispatch_irq_register_6_2_~arg1#1.base, ldv_dispatch_irq_register_6_2_~arg1#1.offset, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.base, 4 + ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.offset, 8);call write~$Pointer$(ldv_dispatch_irq_register_6_2_~arg2#1.base, ldv_dispatch_irq_register_6_2_~arg2#1.offset, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.base, 12 + ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.offset, 8);call write~$Pointer$(ldv_dispatch_irq_register_6_2_~arg3#1.base, ldv_dispatch_irq_register_6_2_~arg3#1.offset, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.base, 20 + ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.offset, 8);assume { :begin_inline_ldv_interrupt_interrupt_instance_0 } true;ldv_interrupt_interrupt_instance_0_#in~arg0#1.base, ldv_interrupt_interrupt_instance_0_#in~arg0#1.offset := ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.base, ldv_dispatch_irq_register_6_2_~cf_arg_0~0#1.offset;havoc ldv_interrupt_interrupt_instance_0_#t~mem807#1, ldv_interrupt_interrupt_instance_0_#t~mem808#1.base, ldv_interrupt_interrupt_instance_0_#t~mem808#1.offset, ldv_interrupt_interrupt_instance_0_#t~mem809#1.base, ldv_interrupt_interrupt_instance_0_#t~mem809#1.offset, ldv_interrupt_interrupt_instance_0_#t~mem810#1.base, ldv_interrupt_interrupt_instance_0_#t~mem810#1.offset, ldv_interrupt_interrupt_instance_0_#t~ret811#1, ldv_interrupt_interrupt_instance_0_#t~ret812#1, ldv_interrupt_interrupt_instance_0_~arg0#1.base, ldv_interrupt_interrupt_instance_0_~arg0#1.offset, ldv_interrupt_interrupt_instance_0_~ldv_0_callback_handler~0#1.base, ldv_interrupt_interrupt_instance_0_~ldv_0_callback_handler~0#1.offset, ldv_interrupt_interrupt_instance_0_~ldv_0_data_data~0#1.base, ldv_interrupt_interrupt_instance_0_~ldv_0_data_data~0#1.offset, ldv_interrupt_interrupt_instance_0_~ldv_0_line_line~0#1, ldv_interrupt_interrupt_instance_0_~ldv_0_ret_val_default~0#1, ldv_interrupt_interrupt_instance_0_~ldv_0_thread_thread~0#1.base, ldv_interrupt_interrupt_instance_0_~ldv_0_thread_thread~0#1.offset, ldv_interrupt_interrupt_instance_0_~data~2#1.base, ldv_interrupt_interrupt_instance_0_~data~2#1.offset, ldv_interrupt_interrupt_instance_0_~tmp~51#1;ldv_interrupt_interrupt_instance_0_~arg0#1.base, ldv_interrupt_interrupt_instance_0_~arg0#1.offset := ldv_interrupt_interrupt_instance_0_#in~arg0#1.base, ldv_interrupt_interrupt_instance_0_#in~arg0#1.offset;havoc ldv_interrupt_interrupt_instance_0_~ldv_0_callback_handler~0#1.base, ldv_interrupt_interrupt_instance_0_~ldv_0_callback_handler~0#1.offset;havoc ldv_interrupt_interrupt_instance_0_~ldv_0_data_data~0#1.base, ldv_interrupt_interrupt_instance_0_~ldv_0_data_data~0#1.offset;havoc ldv_interrupt_interrupt_instance_0_~ldv_0_line_line~0#1;havoc ldv_interrupt_interrupt_instance_0_~ldv_0_ret_val_default~0#1;havoc ldv_interrupt_interrupt_instance_0_~ldv_0_thread_thread~0#1.base, ldv_interrupt_interrupt_instance_0_~ldv_0_thread_thread~0#1.offset;havoc ldv_interrupt_interrupt_instance_0_~data~2#1.base, ldv_interrupt_interrupt_instance_0_~data~2#1.offset;havoc ldv_interrupt_interrupt_instance_0_~tmp~51#1;ldv_interrupt_interrupt_instance_0_~data~2#1.base, ldv_interrupt_interrupt_instance_0_~data~2#1.offset := ldv_interrupt_interrupt_instance_0_~arg0#1.base, ldv_interrupt_interrupt_instance_0_~arg0#1.offset; {1894#false} is VALID [2022-02-20 22:54:42,960 INFO L290 TraceCheckUtils]: 209: Hoare triple {1894#false} assume !(0 != (ldv_interrupt_interrupt_instance_0_~data~2#1.base + ldv_interrupt_interrupt_instance_0_~data~2#1.offset) % 18446744073709551616); {1894#false} is VALID [2022-02-20 22:54:42,960 INFO L290 TraceCheckUtils]: 210: Hoare triple {1894#false} assume { :begin_inline_ldv_switch_to_interrupt_context } true; {1894#false} is VALID [2022-02-20 22:54:42,960 INFO L290 TraceCheckUtils]: 211: Hoare triple {1894#false} assume { :end_inline_ldv_switch_to_interrupt_context } true;assume { :begin_inline_ldv_interrupt_instance_handler_0_5 } true;ldv_interrupt_instance_handler_0_5_#in~arg0#1.base, ldv_interrupt_instance_handler_0_5_#in~arg0#1.offset, ldv_interrupt_instance_handler_0_5_#in~arg1#1, ldv_interrupt_instance_handler_0_5_#in~arg2#1.base, ldv_interrupt_instance_handler_0_5_#in~arg2#1.offset := ldv_interrupt_interrupt_instance_0_~ldv_0_callback_handler~0#1.base, ldv_interrupt_interrupt_instance_0_~ldv_0_callback_handler~0#1.offset, ldv_interrupt_interrupt_instance_0_~ldv_0_line_line~0#1, ldv_interrupt_interrupt_instance_0_~ldv_0_data_data~0#1.base, ldv_interrupt_interrupt_instance_0_~ldv_0_data_data~0#1.offset;havoc ldv_interrupt_instance_handler_0_5_#res#1;havoc ldv_interrupt_instance_handler_0_5_#t~ret803#1, ldv_interrupt_instance_handler_0_5_~arg0#1.base, ldv_interrupt_instance_handler_0_5_~arg0#1.offset, ldv_interrupt_instance_handler_0_5_~arg1#1, ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset, ldv_interrupt_instance_handler_0_5_~tmp~50#1;ldv_interrupt_instance_handler_0_5_~arg0#1.base, ldv_interrupt_instance_handler_0_5_~arg0#1.offset := ldv_interrupt_instance_handler_0_5_#in~arg0#1.base, ldv_interrupt_instance_handler_0_5_#in~arg0#1.offset;ldv_interrupt_instance_handler_0_5_~arg1#1 := ldv_interrupt_instance_handler_0_5_#in~arg1#1;ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset := ldv_interrupt_instance_handler_0_5_#in~arg2#1.base, ldv_interrupt_instance_handler_0_5_#in~arg2#1.offset;havoc ldv_interrupt_instance_handler_0_5_~tmp~50#1;assume { :begin_inline_via_ircc_interrupt } true;via_ircc_interrupt_#in~dummy#1, via_ircc_interrupt_#in~dev_id#1.base, via_ircc_interrupt_#in~dev_id#1.offset := ldv_interrupt_instance_handler_0_5_~arg1#1, ldv_interrupt_instance_handler_0_5_~arg2#1.base, ldv_interrupt_instance_handler_0_5_~arg2#1.offset;havoc via_ircc_interrupt_#res#1;havoc via_ircc_interrupt_#t~ret675#1.base, via_ircc_interrupt_#t~ret675#1.offset, via_ircc_interrupt_#t~mem676#1, via_ircc_interrupt_#t~ret677#1, via_ircc_interrupt_#t~nondet678#1, via_ircc_interrupt_#t~ite679#1.base, via_ircc_interrupt_#t~ite679#1.offset, via_ircc_interrupt_#t~ite680#1.base, via_ircc_interrupt_#t~ite680#1.offset, via_ircc_interrupt_#t~ite681#1.base, via_ircc_interrupt_#t~ite681#1.offset, via_ircc_interrupt_#t~mem682#1, via_ircc_interrupt_#t~ret683#1, via_ircc_interrupt_#t~mem684#1, via_ircc_interrupt_#t~ret685#1, via_ircc_interrupt_#t~mem686#1, via_ircc_interrupt_#t~mem687#1, via_ircc_interrupt_#t~mem688#1.base, via_ircc_interrupt_#t~mem688#1.offset, via_ircc_interrupt_#t~ret689#1, via_ircc_interrupt_#t~ret690#1, via_ircc_interrupt_#t~ret691#1, via_ircc_interrupt_#t~ret692#1, via_ircc_interrupt_#t~nondet693#1, via_ircc_interrupt_#t~ite694#1.base, via_ircc_interrupt_#t~ite694#1.offset, via_ircc_interrupt_#t~ite695#1.base, via_ircc_interrupt_#t~ite695#1.offset, via_ircc_interrupt_#t~ite696#1.base, via_ircc_interrupt_#t~ite696#1.offset, via_ircc_interrupt_#t~ite697#1.base, via_ircc_interrupt_#t~ite697#1.offset, via_ircc_interrupt_#t~mem698#1, via_ircc_interrupt_#t~ret699#1, via_ircc_interrupt_#t~mem700#1.base, via_ircc_interrupt_#t~mem700#1.offset, via_ircc_interrupt_#t~ret701#1, via_ircc_interrupt_#t~ret702#1, via_ircc_interrupt_#t~mem703#1, via_ircc_interrupt_#t~ret704#1, via_ircc_interrupt_#t~nondet705#1, via_ircc_interrupt_#t~ite706#1.base, via_ircc_interrupt_#t~ite706#1.offset, via_ircc_interrupt_#t~ite707#1.base, via_ircc_interrupt_#t~ite707#1.offset, via_ircc_interrupt_#t~ite708#1.base, via_ircc_interrupt_#t~ite708#1.offset, via_ircc_interrupt_#t~ite709#1.base, via_ircc_interrupt_#t~ite709#1.offset, via_ircc_interrupt_#t~ite710#1.base, via_ircc_interrupt_#t~ite710#1.offset, via_ircc_interrupt_#t~ite711#1.base, via_ircc_interrupt_#t~ite711#1.offset, via_ircc_interrupt_#t~ite712#1.base, via_ircc_interrupt_#t~ite712#1.offset, via_ircc_interrupt_#t~nondet713#1, via_ircc_interrupt_#t~ret714#1, via_ircc_interrupt_#t~ret715#1, via_ircc_interrupt_#t~ret716#1, via_ircc_interrupt_#t~nondet717#1, via_ircc_interrupt_#t~mem718#1, via_ircc_interrupt_#t~ret719#1, via_ircc_interrupt_~dummy#1, via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset, via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset, via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset, via_ircc_interrupt_~tmp~39#1.base, via_ircc_interrupt_~tmp~39#1.offset, via_ircc_interrupt_~iobase~7#1, via_ircc_interrupt_~iHostIntType~0#1, via_ircc_interrupt_~iRxIntType~0#1, via_ircc_interrupt_~iTxIntType~0#1, via_ircc_interrupt_~tmp___0~13#1, via_ircc_interrupt_~tmp___1~9#1, via_ircc_interrupt_~tmp___2~7#1, via_ircc_interrupt_~tmp___3~4#1, via_ircc_interrupt_~tmp___4~4#1;via_ircc_interrupt_~dummy#1 := via_ircc_interrupt_#in~dummy#1;via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset := via_ircc_interrupt_#in~dev_id#1.base, via_ircc_interrupt_#in~dev_id#1.offset;havoc via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset;havoc via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset;havoc via_ircc_interrupt_~tmp~39#1.base, via_ircc_interrupt_~tmp~39#1.offset;havoc via_ircc_interrupt_~iobase~7#1;havoc via_ircc_interrupt_~iHostIntType~0#1;havoc via_ircc_interrupt_~iRxIntType~0#1;havoc via_ircc_interrupt_~iTxIntType~0#1;havoc via_ircc_interrupt_~tmp___0~13#1;havoc via_ircc_interrupt_~tmp___1~9#1;havoc via_ircc_interrupt_~tmp___2~7#1;havoc via_ircc_interrupt_~tmp___3~4#1;havoc via_ircc_interrupt_~tmp___4~4#1;via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset := via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset; {1894#false} is VALID [2022-02-20 22:54:42,960 INFO L272 TraceCheckUtils]: 212: Hoare triple {1894#false} call via_ircc_interrupt_#t~ret675#1.base, via_ircc_interrupt_#t~ret675#1.offset := netdev_priv(via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset); {1893#true} is VALID [2022-02-20 22:54:42,960 INFO L290 TraceCheckUtils]: 213: Hoare triple {1893#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3200 + ~dev.offset; {1893#true} is VALID [2022-02-20 22:54:42,960 INFO L290 TraceCheckUtils]: 214: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,960 INFO L284 TraceCheckUtils]: 215: Hoare quadruple {1893#true} {1894#false} #4175#return; {1894#false} is VALID [2022-02-20 22:54:42,961 INFO L290 TraceCheckUtils]: 216: Hoare triple {1894#false} via_ircc_interrupt_~tmp~39#1.base, via_ircc_interrupt_~tmp~39#1.offset := via_ircc_interrupt_#t~ret675#1.base, via_ircc_interrupt_#t~ret675#1.offset;havoc via_ircc_interrupt_#t~ret675#1.base, via_ircc_interrupt_#t~ret675#1.offset;via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset := via_ircc_interrupt_~tmp~39#1.base, via_ircc_interrupt_~tmp~39#1.offset;call via_ircc_interrupt_#t~mem676#1 := read~int(via_ircc_interrupt_~self~4#1.base, 292 + via_ircc_interrupt_~self~4#1.offset, 4);via_ircc_interrupt_~iobase~7#1 := via_ircc_interrupt_#t~mem676#1;havoc via_ircc_interrupt_#t~mem676#1;assume { :begin_inline_ldv_spin_lock_100 } true;ldv_spin_lock_100_#in~lock#1.base, ldv_spin_lock_100_#in~lock#1.offset := via_ircc_interrupt_~self~4#1.base, 489 + via_ircc_interrupt_~self~4#1.offset;havoc ldv_spin_lock_100_~lock#1.base, ldv_spin_lock_100_~lock#1.offset;ldv_spin_lock_100_~lock#1.base, ldv_spin_lock_100_~lock#1.offset := ldv_spin_lock_100_#in~lock#1.base, ldv_spin_lock_100_#in~lock#1.offset; {1894#false} is VALID [2022-02-20 22:54:42,961 INFO L272 TraceCheckUtils]: 217: Hoare triple {1894#false} call ldv_spin_lock_lock_of_via_ircc_cb(); {2173#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} is VALID [2022-02-20 22:54:42,961 INFO L272 TraceCheckUtils]: 218: Hoare triple {2173#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} call ldv_assert(191, 0, (if 1 == ~ldv_spin_lock_of_via_ircc_cb~0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,961 INFO L290 TraceCheckUtils]: 219: Hoare triple {1893#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset;~arg1 := #in~arg1; {1893#true} is VALID [2022-02-20 22:54:42,961 INFO L290 TraceCheckUtils]: 220: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,961 INFO L284 TraceCheckUtils]: 221: Hoare quadruple {1893#true} {2173#(= |old(~ldv_spin_lock_of_via_ircc_cb~0)| ~ldv_spin_lock_of_via_ircc_cb~0)} #4633#return; {1893#true} is VALID [2022-02-20 22:54:42,961 INFO L272 TraceCheckUtils]: 222: Hoare triple {1893#true} call ldv_assume((if 1 == ~ldv_spin_lock_of_via_ircc_cb~0 then 1 else 0)); {1893#true} is VALID [2022-02-20 22:54:42,962 INFO L290 TraceCheckUtils]: 223: Hoare triple {1893#true} ~expression := #in~expression; {1893#true} is VALID [2022-02-20 22:54:42,962 INFO L290 TraceCheckUtils]: 224: Hoare triple {1893#true} assume !(0 == ~expression); {1893#true} is VALID [2022-02-20 22:54:42,962 INFO L290 TraceCheckUtils]: 225: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,962 INFO L284 TraceCheckUtils]: 226: Hoare quadruple {1893#true} {1893#true} #4635#return; {1893#true} is VALID [2022-02-20 22:54:42,962 INFO L290 TraceCheckUtils]: 227: Hoare triple {1893#true} ~ldv_spin_lock_of_via_ircc_cb~0 := 2; {1893#true} is VALID [2022-02-20 22:54:42,962 INFO L290 TraceCheckUtils]: 228: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,962 INFO L284 TraceCheckUtils]: 229: Hoare quadruple {1893#true} {1894#false} #4177#return; {1894#false} is VALID [2022-02-20 22:54:42,962 INFO L290 TraceCheckUtils]: 230: Hoare triple {1894#false} assume { :begin_inline_spin_lock } true;spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset := ldv_spin_lock_100_~lock#1.base, ldv_spin_lock_100_~lock#1.offset;havoc spin_lock_~lock#1.base, spin_lock_~lock#1.offset;spin_lock_~lock#1.base, spin_lock_~lock#1.offset := spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset;assume { :begin_inline__raw_spin_lock } true;_raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset := spin_lock_~lock#1.base, spin_lock_~lock#1.offset;havoc _raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset;_raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset := _raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset; {1894#false} is VALID [2022-02-20 22:54:42,963 INFO L290 TraceCheckUtils]: 231: Hoare triple {1894#false} assume { :end_inline__raw_spin_lock } true; {1894#false} is VALID [2022-02-20 22:54:42,963 INFO L290 TraceCheckUtils]: 232: Hoare triple {1894#false} assume { :end_inline_spin_lock } true; {1894#false} is VALID [2022-02-20 22:54:42,963 INFO L290 TraceCheckUtils]: 233: Hoare triple {1894#false} assume { :end_inline_ldv_spin_lock_100 } true; {1894#false} is VALID [2022-02-20 22:54:42,963 INFO L272 TraceCheckUtils]: 234: Hoare triple {1894#false} call via_ircc_interrupt_#t~ret677#1 := ReadReg(via_ircc_interrupt_~iobase~7#1, 33); {1893#true} is VALID [2022-02-20 22:54:42,963 INFO L290 TraceCheckUtils]: 235: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,963 INFO L272 TraceCheckUtils]: 236: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,963 INFO L290 TraceCheckUtils]: 237: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,963 INFO L290 TraceCheckUtils]: 238: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,964 INFO L284 TraceCheckUtils]: 239: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,964 INFO L290 TraceCheckUtils]: 240: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,964 INFO L290 TraceCheckUtils]: 241: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,964 INFO L284 TraceCheckUtils]: 242: Hoare quadruple {1893#true} {1894#false} #4179#return; {1894#false} is VALID [2022-02-20 22:54:42,964 INFO L290 TraceCheckUtils]: 243: Hoare triple {1894#false} via_ircc_interrupt_~iHostIntType~0#1 := via_ircc_interrupt_#t~ret677#1;havoc via_ircc_interrupt_#t~ret677#1; {1894#false} is VALID [2022-02-20 22:54:42,964 INFO L290 TraceCheckUtils]: 244: Hoare triple {1894#false} assume !(~irda_debug~0 % 4294967296 > 3); {1894#false} is VALID [2022-02-20 22:54:42,964 INFO L290 TraceCheckUtils]: 245: Hoare triple {1894#false} assume !(0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 64)))); {1894#false} is VALID [2022-02-20 22:54:42,965 INFO L290 TraceCheckUtils]: 246: Hoare triple {1894#false} assume !(0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 32)))); {1894#false} is VALID [2022-02-20 22:54:42,965 INFO L290 TraceCheckUtils]: 247: Hoare triple {1894#false} assume 0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 16))); {1894#false} is VALID [2022-02-20 22:54:42,965 INFO L272 TraceCheckUtils]: 248: Hoare triple {1894#false} call via_ircc_interrupt_#t~ret704#1 := ReadReg(via_ircc_interrupt_~iobase~7#1, 39); {1893#true} is VALID [2022-02-20 22:54:42,965 INFO L290 TraceCheckUtils]: 249: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,965 INFO L272 TraceCheckUtils]: 250: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,965 INFO L290 TraceCheckUtils]: 251: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,965 INFO L290 TraceCheckUtils]: 252: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,966 INFO L284 TraceCheckUtils]: 253: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,966 INFO L290 TraceCheckUtils]: 254: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,966 INFO L290 TraceCheckUtils]: 255: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,966 INFO L284 TraceCheckUtils]: 256: Hoare quadruple {1893#true} {1894#false} #4263#return; {1894#false} is VALID [2022-02-20 22:54:42,966 INFO L290 TraceCheckUtils]: 257: Hoare triple {1894#false} via_ircc_interrupt_~iRxIntType~0#1 := via_ircc_interrupt_#t~ret704#1;havoc via_ircc_interrupt_#t~ret704#1; {1894#false} is VALID [2022-02-20 22:54:42,966 INFO L290 TraceCheckUtils]: 258: Hoare triple {1894#false} assume !(~irda_debug~0 % 4294967296 > 3); {1894#false} is VALID [2022-02-20 22:54:42,966 INFO L290 TraceCheckUtils]: 259: Hoare triple {1894#false} assume !(0 == via_ircc_interrupt_~iRxIntType~0#1 % 256 % 4294967296); {1894#false} is VALID [2022-02-20 22:54:42,966 INFO L290 TraceCheckUtils]: 260: Hoare triple {1894#false} assume 0 != (if 0 == via_ircc_interrupt_~iRxIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iRxIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iRxIntType~0#1 % 256, 16)));assume { :begin_inline_via_ircc_dma_receive_complete } true;via_ircc_dma_receive_complete_#in~self#1.base, via_ircc_dma_receive_complete_#in~self#1.offset, via_ircc_dma_receive_complete_#in~iobase#1 := via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset, via_ircc_interrupt_~iobase~7#1;havoc via_ircc_dma_receive_complete_#res#1;havoc via_ircc_dma_receive_complete_#t~mem533#1, via_ircc_dma_receive_complete_#t~mem534#1, via_ircc_dma_receive_complete_#t~ret535#1, via_ircc_dma_receive_complete_#t~ret536#1.base, via_ircc_dma_receive_complete_#t~ret536#1.offset, via_ircc_dma_receive_complete_#t~ret537#1.base, via_ircc_dma_receive_complete_#t~ret537#1.offset, via_ircc_dma_receive_complete_#t~mem538#1, via_ircc_dma_receive_complete_#t~mem539#1.base, via_ircc_dma_receive_complete_#t~mem539#1.offset, via_ircc_dma_receive_complete_#t~mem540#1.base, via_ircc_dma_receive_complete_#t~mem540#1.offset, via_ircc_dma_receive_complete_#t~mem541#1, via_ircc_dma_receive_complete_#t~mem542#1, via_ircc_dma_receive_complete_#t~mem543#1.base, via_ircc_dma_receive_complete_#t~mem543#1.offset, via_ircc_dma_receive_complete_#t~mem544#1.base, via_ircc_dma_receive_complete_#t~mem544#1.offset, via_ircc_dma_receive_complete_#t~mem545#1, via_ircc_dma_receive_complete_#t~mem546#1.base, via_ircc_dma_receive_complete_#t~mem546#1.offset, via_ircc_dma_receive_complete_#t~mem547#1.base, via_ircc_dma_receive_complete_#t~mem547#1.offset, via_ircc_dma_receive_complete_#t~mem548#1.base, via_ircc_dma_receive_complete_#t~mem548#1.offset, via_ircc_dma_receive_complete_#t~mem549#1, via_ircc_dma_receive_complete_#t~mem550#1.base, via_ircc_dma_receive_complete_#t~mem550#1.offset, via_ircc_dma_receive_complete_#t~mem551#1.base, via_ircc_dma_receive_complete_#t~mem551#1.offset, via_ircc_dma_receive_complete_#t~mem552#1, via_ircc_dma_receive_complete_#t~mem553#1.base, via_ircc_dma_receive_complete_#t~mem553#1.offset, via_ircc_dma_receive_complete_#t~ret554#1, via_ircc_dma_receive_complete_#t~ret555#1, via_ircc_dma_receive_complete_#t~ret556#1, via_ircc_dma_receive_complete_#t~nondet557#1, via_ircc_dma_receive_complete_#t~mem558#1, via_ircc_dma_receive_complete_#t~ret559#1, via_ircc_dma_receive_complete_#t~nondet560#1, via_ircc_dma_receive_complete_#t~mem561#1, via_ircc_dma_receive_complete_#t~mem562#1, via_ircc_dma_receive_complete_#t~mem563#1, via_ircc_dma_receive_complete_#t~mem564#1, via_ircc_dma_receive_complete_#t~mem565#1, via_ircc_dma_receive_complete_#t~mem566#1, via_ircc_dma_receive_complete_#t~mem567#1, via_ircc_dma_receive_complete_#t~ret568#1, via_ircc_dma_receive_complete_#t~ret569#1, via_ircc_dma_receive_complete_#t~ret570#1, via_ircc_dma_receive_complete_#t~mem571#1, via_ircc_dma_receive_complete_#t~mem572#1, via_ircc_dma_receive_complete_#t~mem573#1, via_ircc_dma_receive_complete_#t~mem574#1, via_ircc_dma_receive_complete_#t~mem575#1, via_ircc_dma_receive_complete_#t~mem576#1, via_ircc_dma_receive_complete_#t~mem577#1, via_ircc_dma_receive_complete_#t~ret578#1.base, via_ircc_dma_receive_complete_#t~ret578#1.offset, via_ircc_dma_receive_complete_#t~mem579#1.base, via_ircc_dma_receive_complete_#t~mem579#1.offset, via_ircc_dma_receive_complete_#t~short580#1, via_ircc_dma_receive_complete_#t~mem581#1.base, via_ircc_dma_receive_complete_#t~mem581#1.offset, via_ircc_dma_receive_complete_#t~short582#1, via_ircc_dma_receive_complete_#t~mem583#1.base, via_ircc_dma_receive_complete_#t~mem583#1.offset, via_ircc_dma_receive_complete_#t~mem584#1.base, via_ircc_dma_receive_complete_#t~mem584#1.offset, via_ircc_dma_receive_complete_#t~mem585#1, via_ircc_dma_receive_complete_#t~ret586#1.base, via_ircc_dma_receive_complete_#t~ret586#1.offset, via_ircc_dma_receive_complete_#t~mem587#1.base, via_ircc_dma_receive_complete_#t~mem587#1.offset, via_ircc_dma_receive_complete_#t~nondet588#1, via_ircc_dma_receive_complete_#t~mem589#1.base, via_ircc_dma_receive_complete_#t~mem589#1.offset, via_ircc_dma_receive_complete_#t~mem590#1.base, via_ircc_dma_receive_complete_#t~mem590#1.offset, via_ircc_dma_receive_complete_#t~mem591#1.base, via_ircc_dma_receive_complete_#t~mem591#1.offset, via_ircc_dma_receive_complete_#t~mem592#1.base, via_ircc_dma_receive_complete_#t~mem592#1.offset, via_ircc_dma_receive_complete_#t~mem593#1, via_ircc_dma_receive_complete_#t~mem594#1.base, via_ircc_dma_receive_complete_#t~mem594#1.offset, via_ircc_dma_receive_complete_#t~mem595#1.base, via_ircc_dma_receive_complete_#t~mem595#1.offset, via_ircc_dma_receive_complete_#t~mem596#1, via_ircc_dma_receive_complete_#t~mem597#1.base, via_ircc_dma_receive_complete_#t~mem597#1.offset, via_ircc_dma_receive_complete_#t~ret598#1, via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset, via_ircc_dma_receive_complete_~iobase#1, via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset, via_ircc_dma_receive_complete_~skb~0#1.base, via_ircc_dma_receive_complete_~skb~0#1.offset, via_ircc_dma_receive_complete_~len~0#1, via_ircc_dma_receive_complete_~i~8#1, via_ircc_dma_receive_complete_~status~0#1, via_ircc_dma_receive_complete_~tmp~36#1, via_ircc_dma_receive_complete_~tmp___0~11#1, via_ircc_dma_receive_complete_~tmp___1~7#1, via_ircc_dma_receive_complete_~tmp___2~5#1;via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset := via_ircc_dma_receive_complete_#in~self#1.base, via_ircc_dma_receive_complete_#in~self#1.offset;via_ircc_dma_receive_complete_~iobase#1 := via_ircc_dma_receive_complete_#in~iobase#1;havoc via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset;havoc via_ircc_dma_receive_complete_~skb~0#1.base, via_ircc_dma_receive_complete_~skb~0#1.offset;havoc via_ircc_dma_receive_complete_~len~0#1;havoc via_ircc_dma_receive_complete_~i~8#1;havoc via_ircc_dma_receive_complete_~status~0#1;havoc via_ircc_dma_receive_complete_~tmp~36#1;havoc via_ircc_dma_receive_complete_~tmp___0~11#1;havoc via_ircc_dma_receive_complete_~tmp___1~7#1;havoc via_ircc_dma_receive_complete_~tmp___2~5#1;via_ircc_dma_receive_complete_~status~0#1 := 0;call via_ircc_dma_receive_complete_#t~mem533#1 := read~int(via_ircc_dma_receive_complete_~self#1.base, 292 + via_ircc_dma_receive_complete_~self#1.offset, 4);via_ircc_dma_receive_complete_~iobase#1 := via_ircc_dma_receive_complete_#t~mem533#1;havoc via_ircc_dma_receive_complete_#t~mem533#1;via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset := via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset;call via_ircc_dma_receive_complete_#t~mem534#1 := read~int(via_ircc_dma_receive_complete_~self#1.base, 344 + via_ircc_dma_receive_complete_~self#1.offset, 4); {1894#false} is VALID [2022-02-20 22:54:42,967 INFO L290 TraceCheckUtils]: 261: Hoare triple {1894#false} assume via_ircc_dma_receive_complete_#t~mem534#1 % 4294967296 <= 3999999;havoc via_ircc_dma_receive_complete_#t~mem534#1; {1894#false} is VALID [2022-02-20 22:54:42,967 INFO L272 TraceCheckUtils]: 262: Hoare triple {1894#false} call via_ircc_dma_receive_complete_#t~ret535#1 := GetRecvByte(via_ircc_dma_receive_complete_~iobase#1 % 65536, via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset); {2187#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:54:42,967 INFO L290 TraceCheckUtils]: 263: Hoare triple {2187#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~iobase := #in~iobase;~self.base, ~self.offset := #in~self.base, #in~self.offset;havoc ~low~4;havoc ~high~4;havoc ~wTmp~2;havoc ~wTmp1~2;havoc ~ret~0; {1893#true} is VALID [2022-02-20 22:54:42,967 INFO L272 TraceCheckUtils]: 264: Hoare triple {1893#true} call #t~ret159 := ReadReg(~iobase % 65536, 44); {1893#true} is VALID [2022-02-20 22:54:42,967 INFO L290 TraceCheckUtils]: 265: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,967 INFO L272 TraceCheckUtils]: 266: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,967 INFO L290 TraceCheckUtils]: 267: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,968 INFO L290 TraceCheckUtils]: 268: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,968 INFO L284 TraceCheckUtils]: 269: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,968 INFO L290 TraceCheckUtils]: 270: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,968 INFO L290 TraceCheckUtils]: 271: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,968 INFO L284 TraceCheckUtils]: 272: Hoare quadruple {1893#true} {1893#true} #3987#return; {1893#true} is VALID [2022-02-20 22:54:42,968 INFO L290 TraceCheckUtils]: 273: Hoare triple {1893#true} ~low~4 := #t~ret159;havoc #t~ret159; {1893#true} is VALID [2022-02-20 22:54:42,968 INFO L272 TraceCheckUtils]: 274: Hoare triple {1893#true} call #t~ret160 := ReadReg(~iobase % 65536, 45); {1893#true} is VALID [2022-02-20 22:54:42,968 INFO L290 TraceCheckUtils]: 275: Hoare triple {1893#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,969 INFO L272 TraceCheckUtils]: 276: Hoare triple {1893#true} call #t~ret137 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1893#true} is VALID [2022-02-20 22:54:42,969 INFO L290 TraceCheckUtils]: 277: Hoare triple {1893#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1893#true} is VALID [2022-02-20 22:54:42,969 INFO L290 TraceCheckUtils]: 278: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,969 INFO L284 TraceCheckUtils]: 279: Hoare quadruple {1893#true} {1893#true} #3667#return; {1893#true} is VALID [2022-02-20 22:54:42,969 INFO L290 TraceCheckUtils]: 280: Hoare triple {1893#true} ~tmp~16 := #t~ret137;havoc #t~ret137;#res := ~tmp~16; {1893#true} is VALID [2022-02-20 22:54:42,969 INFO L290 TraceCheckUtils]: 281: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,969 INFO L284 TraceCheckUtils]: 282: Hoare quadruple {1893#true} {1893#true} #3989#return; {1893#true} is VALID [2022-02-20 22:54:42,969 INFO L290 TraceCheckUtils]: 283: Hoare triple {1893#true} ~high~4 := #t~ret160;havoc #t~ret160;~wTmp1~2 := ~high~4 % 256;~wTmp~2 := (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 0 == ~low~4 % 256 then (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) else (if 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256) then ~low~4 % 256 else (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256)) || ((1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 1 == ~low~4 % 256) then 1 else ~bitwiseOr((if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536), ~low~4 % 256))));call #t~mem161 := read~int(~self.base, 596 + ~self.offset, 4); {1893#true} is VALID [2022-02-20 22:54:42,970 INFO L290 TraceCheckUtils]: 284: Hoare triple {1893#true} assume ~wTmp~2 % 65536 % 4294967296 >= #t~mem161 % 4294967296;havoc #t~mem161;call #t~mem162 := read~int(~self.base, 596 + ~self.offset, 4);~ret~0 := ~wTmp~2 % 65536 - #t~mem162 % 65536;havoc #t~mem162; {1893#true} is VALID [2022-02-20 22:54:42,970 INFO L290 TraceCheckUtils]: 285: Hoare triple {1893#true} call write~int(~wTmp~2 % 65536, ~self.base, 596 + ~self.offset, 4);#res := ~ret~0; {1893#true} is VALID [2022-02-20 22:54:42,970 INFO L290 TraceCheckUtils]: 286: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,970 INFO L284 TraceCheckUtils]: 287: Hoare quadruple {1893#true} {1894#false} #4265#return; {1894#false} is VALID [2022-02-20 22:54:42,970 INFO L290 TraceCheckUtils]: 288: Hoare triple {1894#false} via_ircc_dma_receive_complete_~tmp~36#1 := via_ircc_dma_receive_complete_#t~ret535#1;havoc via_ircc_dma_receive_complete_#t~ret535#1;via_ircc_dma_receive_complete_~len~0#1 := via_ircc_dma_receive_complete_~tmp~36#1 % 65536; {1894#false} is VALID [2022-02-20 22:54:42,970 INFO L272 TraceCheckUtils]: 289: Hoare triple {1894#false} call via_ircc_dma_receive_complete_#t~ret536#1.base, via_ircc_dma_receive_complete_#t~ret536#1.offset := dev_alloc_skb(1 + via_ircc_dma_receive_complete_~len~0#1); {1894#false} is VALID [2022-02-20 22:54:42,970 INFO L290 TraceCheckUtils]: 290: Hoare triple {1894#false} ~length#1 := #in~length#1;havoc ~tmp~4#1.base, ~tmp~4#1.offset;assume { :begin_inline_netdev_alloc_skb } true;netdev_alloc_skb_#in~dev#1.base, netdev_alloc_skb_#in~dev#1.offset, netdev_alloc_skb_#in~length#1 := 0, 0, ~length#1;havoc netdev_alloc_skb_#res#1.base, netdev_alloc_skb_#res#1.offset;havoc netdev_alloc_skb_#t~ret57#1.base, netdev_alloc_skb_#t~ret57#1.offset, netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset, netdev_alloc_skb_~length#1, netdev_alloc_skb_~tmp~3#1.base, netdev_alloc_skb_~tmp~3#1.offset;netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset := netdev_alloc_skb_#in~dev#1.base, netdev_alloc_skb_#in~dev#1.offset;netdev_alloc_skb_~length#1 := netdev_alloc_skb_#in~length#1;havoc netdev_alloc_skb_~tmp~3#1.base, netdev_alloc_skb_~tmp~3#1.offset;assume { :begin_inline_ldv___netdev_alloc_skb_57 } true;ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_57_#in~ldv_func_arg2#1, ldv___netdev_alloc_skb_57_#in~flags#1 := netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset, netdev_alloc_skb_~length#1, 32;havoc ldv___netdev_alloc_skb_57_#res#1.base, ldv___netdev_alloc_skb_57_#res#1.offset;havoc ldv___netdev_alloc_skb_57_#t~ret868#1.base, ldv___netdev_alloc_skb_57_#t~ret868#1.offset, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_57_~ldv_func_arg2#1, ldv___netdev_alloc_skb_57_~flags#1, ldv___netdev_alloc_skb_57_~tmp~61#1.base, ldv___netdev_alloc_skb_57_~tmp~61#1.offset;ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_~ldv_func_arg1#1.offset := ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_57_#in~ldv_func_arg1#1.offset;ldv___netdev_alloc_skb_57_~ldv_func_arg2#1 := ldv___netdev_alloc_skb_57_#in~ldv_func_arg2#1;ldv___netdev_alloc_skb_57_~flags#1 := ldv___netdev_alloc_skb_57_#in~flags#1;havoc ldv___netdev_alloc_skb_57_~tmp~61#1.base, ldv___netdev_alloc_skb_57_~tmp~61#1.offset; {1894#false} is VALID [2022-02-20 22:54:42,971 INFO L272 TraceCheckUtils]: 291: Hoare triple {1894#false} call ldv_check_alloc_flags(ldv___netdev_alloc_skb_57_~flags#1); {1894#false} is VALID [2022-02-20 22:54:42,971 INFO L290 TraceCheckUtils]: 292: Hoare triple {1894#false} ~flags#1 := #in~flags#1;havoc ~tmp~67#1; {1894#false} is VALID [2022-02-20 22:54:42,971 INFO L290 TraceCheckUtils]: 293: Hoare triple {1894#false} assume 32 != ~flags#1 % 4294967296 && 0 != ~flags#1 % 4294967296; {1894#false} is VALID [2022-02-20 22:54:42,971 INFO L272 TraceCheckUtils]: 294: Hoare triple {1894#false} call #t~ret877#1 := ldv_exclusive_spin_is_locked(); {1893#true} is VALID [2022-02-20 22:54:42,971 INFO L290 TraceCheckUtils]: 295: Hoare triple {1893#true} assume 2 == ~ldv_spin_NOT_ARG_SIGN~0;#res := 1; {1893#true} is VALID [2022-02-20 22:54:42,971 INFO L290 TraceCheckUtils]: 296: Hoare triple {1893#true} assume true; {1893#true} is VALID [2022-02-20 22:54:42,971 INFO L284 TraceCheckUtils]: 297: Hoare quadruple {1893#true} {1894#false} #3629#return; {1894#false} is VALID [2022-02-20 22:54:42,971 INFO L290 TraceCheckUtils]: 298: Hoare triple {1894#false} assume -2147483648 <= #t~ret877#1 && #t~ret877#1 <= 2147483647;~tmp~67#1 := #t~ret877#1;havoc #t~ret877#1;assume { :begin_inline_ldv_assert_linux_alloc_spinlock__wrong_flags } true;ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1 := (if 0 == ~tmp~67#1 then 1 else 0);havoc ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1;ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1 := ldv_assert_linux_alloc_spinlock__wrong_flags_#in~expr#1; {1894#false} is VALID [2022-02-20 22:54:42,972 INFO L290 TraceCheckUtils]: 299: Hoare triple {1894#false} assume 0 == ldv_assert_linux_alloc_spinlock__wrong_flags_~expr#1; {1894#false} is VALID [2022-02-20 22:54:42,972 INFO L290 TraceCheckUtils]: 300: Hoare triple {1894#false} assume !false; {1894#false} is VALID [2022-02-20 22:54:42,973 INFO L134 CoverageAnalysis]: Checked inductivity of 587 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 587 trivial. 0 not checked. [2022-02-20 22:54:42,973 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:54:42,973 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [821299881] [2022-02-20 22:54:42,974 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [821299881] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:54:42,974 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:54:42,974 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-02-20 22:54:42,975 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148221017] [2022-02-20 22:54:42,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:54:42,980 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 21.8) internal successors, (109), 3 states have internal predecessors, (109), 4 states have call successors, (36), 6 states have call predecessors, (36), 1 states have return successors, (32), 3 states have call predecessors, (32), 4 states have call successors, (32) Word has length 301 [2022-02-20 22:54:42,982 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:54:42,985 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 6 states, 5 states have (on average 21.8) internal successors, (109), 3 states have internal predecessors, (109), 4 states have call successors, (36), 6 states have call predecessors, (36), 1 states have return successors, (32), 3 states have call predecessors, (32), 4 states have call successors, (32) [2022-02-20 22:54:43,146 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 177 edges. 177 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:54:43,146 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-02-20 22:54:43,146 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:54:43,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-02-20 22:54:43,160 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-02-20 22:54:43,168 INFO L87 Difference]: Start difference. First operand has 1890 states, 1157 states have (on average 1.2947277441659464) internal successors, (1498), 1188 states have internal predecessors, (1498), 641 states have call successors, (641), 91 states have call predecessors, (641), 90 states have return successors, (638), 626 states have call predecessors, (638), 638 states have call successors, (638) Second operand has 6 states, 5 states have (on average 21.8) internal successors, (109), 3 states have internal predecessors, (109), 4 states have call successors, (36), 6 states have call predecessors, (36), 1 states have return successors, (32), 3 states have call predecessors, (32), 4 states have call successors, (32) [2022-02-20 22:55:40,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:55:40,815 INFO L93 Difference]: Finished difference Result 6103 states and 9246 transitions. [2022-02-20 22:55:40,815 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-02-20 22:55:40,816 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 21.8) internal successors, (109), 3 states have internal predecessors, (109), 4 states have call successors, (36), 6 states have call predecessors, (36), 1 states have return successors, (32), 3 states have call predecessors, (32), 4 states have call successors, (32) Word has length 301 [2022-02-20 22:55:40,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:55:40,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 5 states have (on average 21.8) internal successors, (109), 3 states have internal predecessors, (109), 4 states have call successors, (36), 6 states have call predecessors, (36), 1 states have return successors, (32), 3 states have call predecessors, (32), 4 states have call successors, (32) [2022-02-20 22:55:41,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 9246 transitions. [2022-02-20 22:55:41,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 5 states have (on average 21.8) internal successors, (109), 3 states have internal predecessors, (109), 4 states have call successors, (36), 6 states have call predecessors, (36), 1 states have return successors, (32), 3 states have call predecessors, (32), 4 states have call successors, (32) [2022-02-20 22:55:42,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 9246 transitions. [2022-02-20 22:55:42,043 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 13 states and 9246 transitions.