./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 6c1be66de5de44f99e184f931232a9d8bcb0b8fd4712efbcede070913355a2c0 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 22:58:37,482 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 22:58:37,484 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 22:58:37,506 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 22:58:37,507 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 22:58:37,508 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 22:58:37,508 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 22:58:37,510 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 22:58:37,511 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 22:58:37,511 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 22:58:37,512 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 22:58:37,513 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 22:58:37,513 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 22:58:37,514 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 22:58:37,515 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 22:58:37,515 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 22:58:37,516 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 22:58:37,516 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 22:58:37,517 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 22:58:37,519 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 22:58:37,519 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 22:58:37,524 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 22:58:37,525 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 22:58:37,526 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 22:58:37,528 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 22:58:37,531 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 22:58:37,532 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 22:58:37,532 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 22:58:37,533 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 22:58:37,534 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 22:58:37,534 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 22:58:37,535 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 22:58:37,536 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 22:58:37,537 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 22:58:37,538 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 22:58:37,538 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 22:58:37,539 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 22:58:37,539 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 22:58:37,539 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 22:58:37,540 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 22:58:37,540 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 22:58:37,541 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 22:58:37,556 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 22:58:37,556 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 22:58:37,557 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 22:58:37,557 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 22:58:37,557 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 22:58:37,557 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 22:58:37,558 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 22:58:37,558 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 22:58:37,558 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 22:58:37,558 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 22:58:37,559 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 22:58:37,559 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 22:58:37,559 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 22:58:37,559 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 22:58:37,559 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 22:58:37,559 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 22:58:37,559 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 22:58:37,559 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 22:58:37,560 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 22:58:37,560 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 22:58:37,560 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 22:58:37,560 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:58:37,560 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 22:58:37,560 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 22:58:37,561 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 22:58:37,561 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 22:58:37,561 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 22:58:37,561 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 22:58:37,561 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 22:58:37,561 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 22:58:37,561 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6c1be66de5de44f99e184f931232a9d8bcb0b8fd4712efbcede070913355a2c0 [2022-02-20 22:58:37,757 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 22:58:37,774 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 22:58:37,776 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 22:58:37,778 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 22:58:37,778 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 22:58:37,779 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i [2022-02-20 22:58:37,826 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ca0bc0404/59b36ab4d4d54b488e68f5a8f58e51ca/FLAGff08789ac [2022-02-20 22:58:38,463 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 22:58:38,464 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i [2022-02-20 22:58:38,508 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ca0bc0404/59b36ab4d4d54b488e68f5a8f58e51ca/FLAGff08789ac [2022-02-20 22:58:38,852 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ca0bc0404/59b36ab4d4d54b488e68f5a8f58e51ca [2022-02-20 22:58:38,855 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 22:58:38,855 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 22:58:38,857 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 22:58:38,857 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 22:58:38,859 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 22:58:38,860 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:58:38" (1/1) ... [2022-02-20 22:58:38,861 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@50c4253d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:38, skipping insertion in model container [2022-02-20 22:58:38,862 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:58:38" (1/1) ... [2022-02-20 22:58:38,866 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 22:58:38,953 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 22:58:40,549 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i[324559,324572] [2022-02-20 22:58:40,551 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i[324728,324741] [2022-02-20 22:58:40,552 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i[324895,324908] [2022-02-20 22:58:40,552 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i[325063,325076] [2022-02-20 22:58:40,567 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:58:40,599 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 22:58:40,874 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i[324559,324572] [2022-02-20 22:58:40,875 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i[324728,324741] [2022-02-20 22:58:40,875 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i[324895,324908] [2022-02-20 22:58:40,876 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i[325063,325076] [2022-02-20 22:58:40,882 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:58:40,973 INFO L208 MainTranslator]: Completed translation [2022-02-20 22:58:40,973 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40 WrapperNode [2022-02-20 22:58:40,973 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 22:58:40,974 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 22:58:40,974 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 22:58:40,974 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 22:58:40,979 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,051 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,212 INFO L137 Inliner]: procedures = 386, calls = 2027, calls flagged for inlining = 151, calls inlined = 130, statements flattened = 4217 [2022-02-20 22:58:41,212 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 22:58:41,213 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 22:58:41,213 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 22:58:41,213 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 22:58:41,219 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,219 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,251 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,252 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,324 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,342 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,361 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,421 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 22:58:41,422 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 22:58:41,423 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 22:58:41,423 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 22:58:41,425 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (1/1) ... [2022-02-20 22:58:41,430 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:58:41,437 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:58:41,447 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 22:58:41,450 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 22:58:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2022-02-20 22:58:41,476 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2022-02-20 22:58:41,476 INFO L130 BoogieDeclarations]: Found specification of procedure RxCurCount [2022-02-20 22:58:41,476 INFO L138 BoogieDeclarations]: Found implementation of procedure RxCurCount [2022-02-20 22:58:41,476 INFO L130 BoogieDeclarations]: Found specification of procedure irda_setup_dma [2022-02-20 22:58:41,476 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_setup_dma [2022-02-20 22:58:41,483 INFO L130 BoogieDeclarations]: Found specification of procedure netif_wake_queue [2022-02-20 22:58:41,483 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_wake_queue [2022-02-20 22:58:41,483 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 22:58:41,483 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 22:58:41,484 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_73 [2022-02-20 22:58:41,484 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_73 [2022-02-20 22:58:41,484 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2022-02-20 22:58:41,484 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2022-02-20 22:58:41,484 INFO L130 BoogieDeclarations]: Found specification of procedure CheckRegBit [2022-02-20 22:58:41,484 INFO L138 BoogieDeclarations]: Found implementation of procedure CheckRegBit [2022-02-20 22:58:41,485 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assert_linux_kernel_locking_spinlock__one_thread_double_lock [2022-02-20 22:58:41,485 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assert_linux_kernel_locking_spinlock__one_thread_double_lock [2022-02-20 22:58:41,485 INFO L130 BoogieDeclarations]: Found specification of procedure via_remove_one [2022-02-20 22:58:41,485 INFO L138 BoogieDeclarations]: Found implementation of procedure via_remove_one [2022-02-20 22:58:41,485 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_speed [2022-02-20 22:58:41,485 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_speed [2022-02-20 22:58:41,485 INFO L130 BoogieDeclarations]: Found specification of procedure dma_zalloc_coherent [2022-02-20 22:58:41,485 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_zalloc_coherent [2022-02-20 22:58:41,485 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_xmalloc [2022-02-20 22:58:41,486 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_xmalloc [2022-02-20 22:58:41,486 INFO L130 BoogieDeclarations]: Found specification of procedure SetPulseWidth [2022-02-20 22:58:41,486 INFO L138 BoogieDeclarations]: Found implementation of procedure SetPulseWidth [2022-02-20 22:58:41,486 INFO L130 BoogieDeclarations]: Found specification of procedure Tdelay [2022-02-20 22:58:41,486 INFO L138 BoogieDeclarations]: Found implementation of procedure Tdelay [2022-02-20 22:58:41,486 INFO L130 BoogieDeclarations]: Found specification of procedure netif_rx [2022-02-20 22:58:41,486 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_rx [2022-02-20 22:58:41,487 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_is_err [2022-02-20 22:58:41,487 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_is_err [2022-02-20 22:58:41,487 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 22:58:41,487 INFO L130 BoogieDeclarations]: Found specification of procedure ClkTx [2022-02-20 22:58:41,487 INFO L138 BoogieDeclarations]: Found implementation of procedure ClkTx [2022-02-20 22:58:41,487 INFO L130 BoogieDeclarations]: Found specification of procedure WriteLPCReg [2022-02-20 22:58:41,487 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteLPCReg [2022-02-20 22:58:41,487 INFO L130 BoogieDeclarations]: Found specification of procedure capable [2022-02-20 22:58:41,488 INFO L138 BoogieDeclarations]: Found implementation of procedure capable [2022-02-20 22:58:41,488 INFO L130 BoogieDeclarations]: Found specification of procedure CommonInit [2022-02-20 22:58:41,488 INFO L138 BoogieDeclarations]: Found implementation of procedure CommonInit [2022-02-20 22:58:41,488 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_get_tx_queue [2022-02-20 22:58:41,488 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_get_tx_queue [2022-02-20 22:58:41,488 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_dongle_speed [2022-02-20 22:58:41,489 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_dongle_speed [2022-02-20 22:58:41,489 INFO L130 BoogieDeclarations]: Found specification of procedure ReadLPCReg [2022-02-20 22:58:41,489 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadLPCReg [2022-02-20 22:58:41,489 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2022-02-20 22:58:41,489 INFO L130 BoogieDeclarations]: Found specification of procedure free_dma [2022-02-20 22:58:41,490 INFO L138 BoogieDeclarations]: Found implementation of procedure free_dma [2022-02-20 22:58:41,490 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_lock_of_via_ircc_cb [2022-02-20 22:58:41,490 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_lock_of_via_ircc_cb [2022-02-20 22:58:41,491 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_receive [2022-02-20 22:58:41,491 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_receive [2022-02-20 22:58:41,491 INFO L130 BoogieDeclarations]: Found specification of procedure get_dma_ops [2022-02-20 22:58:41,491 INFO L138 BoogieDeclarations]: Found implementation of procedure get_dma_ops [2022-02-20 22:58:41,491 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2022-02-20 22:58:41,492 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assume [2022-02-20 22:58:41,492 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assume [2022-02-20 22:58:41,492 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_close [2022-02-20 22:58:41,492 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_close [2022-02-20 22:58:41,492 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 22:58:41,492 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2022-02-20 22:58:41,492 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2022-02-20 22:58:41,493 INFO L130 BoogieDeclarations]: Found specification of procedure CkRxRecv [2022-02-20 22:58:41,493 INFO L138 BoogieDeclarations]: Found implementation of procedure CkRxRecv [2022-02-20 22:58:41,493 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2022-02-20 22:58:41,493 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2022-02-20 22:58:41,493 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_err_code [2022-02-20 22:58:41,493 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_err_code [2022-02-20 22:58:41,493 INFO L130 BoogieDeclarations]: Found specification of procedure irda_get_next_speed [2022-02-20 22:58:41,494 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_get_next_speed [2022-02-20 22:58:41,494 INFO L130 BoogieDeclarations]: Found specification of procedure ReadReg [2022-02-20 22:58:41,494 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadReg [2022-02-20 22:58:41,494 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_open [2022-02-20 22:58:41,494 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_open [2022-02-20 22:58:41,494 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit [2022-02-20 22:58:41,494 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit [2022-02-20 22:58:41,494 INFO L130 BoogieDeclarations]: Found specification of procedure WriteRegBit [2022-02-20 22:58:41,494 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteRegBit [2022-02-20 22:58:41,495 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 22:58:41,495 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Indx [2022-02-20 22:58:41,495 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Indx [2022-02-20 22:58:41,495 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 22:58:41,495 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_int [2022-02-20 22:58:41,496 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_int [2022-02-20 22:58:41,496 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2022-02-20 22:58:41,496 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2022-02-20 22:58:41,496 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-02-20 22:58:41,496 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 22:58:41,497 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 22:58:41,497 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~int [2022-02-20 22:58:41,497 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~int [2022-02-20 22:58:41,497 INFO L130 BoogieDeclarations]: Found specification of procedure WriteReg [2022-02-20 22:58:41,497 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteReg [2022-02-20 22:58:41,497 INFO L130 BoogieDeclarations]: Found specification of procedure __ldv_spin_lock [2022-02-20 22:58:41,497 INFO L138 BoogieDeclarations]: Found implementation of procedure __ldv_spin_lock [2022-02-20 22:58:41,497 INFO L130 BoogieDeclarations]: Found specification of procedure warn_slowpath_null [2022-02-20 22:58:41,498 INFO L138 BoogieDeclarations]: Found implementation of procedure warn_slowpath_null [2022-02-20 22:58:41,498 INFO L130 BoogieDeclarations]: Found specification of procedure SetBaudRate [2022-02-20 22:58:41,498 INFO L138 BoogieDeclarations]: Found implementation of procedure SetBaudRate [2022-02-20 22:58:41,498 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Byte [2022-02-20 22:58:41,498 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Byte [2022-02-20 22:58:41,499 INFO L130 BoogieDeclarations]: Found specification of procedure skb_put [2022-02-20 22:58:41,499 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_put [2022-02-20 22:58:41,499 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_netdev [2022-02-20 22:58:41,499 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_netdev [2022-02-20 22:58:41,499 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_open [2022-02-20 22:58:41,499 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_open [2022-02-20 22:58:41,499 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 22:58:41,500 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 22:58:41,500 INFO L130 BoogieDeclarations]: Found specification of procedure ResetChip [2022-02-20 22:58:41,502 INFO L138 BoogieDeclarations]: Found implementation of procedure ResetChip [2022-02-20 22:58:41,502 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2022-02-20 22:58:41,503 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2022-02-20 22:58:41,503 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 22:58:41,504 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 22:58:41,504 INFO L130 BoogieDeclarations]: Found specification of procedure irda_device_txqueue_empty [2022-02-20 22:58:41,504 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_device_txqueue_empty [2022-02-20 22:58:41,504 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assert_linux_kernel_locking_spinlock__one_thread_double_unlock [2022-02-20 22:58:41,505 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assert_linux_kernel_locking_spinlock__one_thread_double_unlock [2022-02-20 22:58:41,510 INFO L130 BoogieDeclarations]: Found specification of procedure pci_read_config_byte [2022-02-20 22:58:41,510 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_read_config_byte [2022-02-20 22:58:41,510 INFO L130 BoogieDeclarations]: Found specification of procedure Sdelay [2022-02-20 22:58:41,510 INFO L138 BoogieDeclarations]: Found implementation of procedure Sdelay [2022-02-20 22:58:41,510 INFO L130 BoogieDeclarations]: Found specification of procedure SetSIR [2022-02-20 22:58:41,510 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSIR [2022-02-20 22:58:41,510 INFO L130 BoogieDeclarations]: Found specification of procedure netif_stop_queue [2022-02-20 22:58:41,511 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_stop_queue [2022-02-20 22:58:41,511 INFO L130 BoogieDeclarations]: Found specification of procedure SetMaxRxPacketSize [2022-02-20 22:58:41,511 INFO L138 BoogieDeclarations]: Found implementation of procedure SetMaxRxPacketSize [2022-02-20 22:58:41,511 INFO L130 BoogieDeclarations]: Found specification of procedure GetRecvByte [2022-02-20 22:58:41,511 INFO L138 BoogieDeclarations]: Found implementation of procedure GetRecvByte [2022-02-20 22:58:41,511 INFO L130 BoogieDeclarations]: Found specification of procedure consume_skb [2022-02-20 22:58:41,511 INFO L138 BoogieDeclarations]: Found implementation of procedure consume_skb [2022-02-20 22:58:41,511 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 22:58:41,511 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 22:58:41,511 INFO L130 BoogieDeclarations]: Found specification of procedure hwreset [2022-02-20 22:58:41,511 INFO L138 BoogieDeclarations]: Found implementation of procedure hwreset [2022-02-20 22:58:41,512 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 22:58:41,512 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 22:58:41,512 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 22:58:41,512 INFO L130 BoogieDeclarations]: Found specification of procedure pci_write_config_byte [2022-02-20 22:58:41,512 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_write_config_byte [2022-02-20 22:58:41,512 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_priv [2022-02-20 22:58:41,512 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_priv [2022-02-20 22:58:41,512 INFO L130 BoogieDeclarations]: Found specification of procedure outb [2022-02-20 22:58:41,512 INFO L138 BoogieDeclarations]: Found implementation of procedure outb [2022-02-20 22:58:41,512 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_positive_int [2022-02-20 22:58:41,512 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_positive_int [2022-02-20 22:58:41,512 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq [2022-02-20 22:58:41,513 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq [2022-02-20 22:58:41,513 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_xmit [2022-02-20 22:58:41,513 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_xmit [2022-02-20 22:58:41,513 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reserve [2022-02-20 22:58:41,513 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reserve [2022-02-20 22:58:41,513 INFO L130 BoogieDeclarations]: Found specification of procedure dma_free_attrs [2022-02-20 22:58:41,513 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_free_attrs [2022-02-20 22:58:41,513 INFO L130 BoogieDeclarations]: Found specification of procedure netif_tx_start_queue [2022-02-20 22:58:41,513 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_tx_start_queue [2022-02-20 22:58:41,513 INFO L130 BoogieDeclarations]: Found specification of procedure free_netdev [2022-02-20 22:58:41,513 INFO L138 BoogieDeclarations]: Found implementation of procedure free_netdev [2022-02-20 22:58:41,514 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2022-02-20 22:58:41,514 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2022-02-20 22:58:41,514 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 22:58:41,514 INFO L130 BoogieDeclarations]: Found specification of procedure net_ratelimit [2022-02-20 22:58:41,514 INFO L138 BoogieDeclarations]: Found implementation of procedure net_ratelimit [2022-02-20 22:58:41,514 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendByte [2022-02-20 22:58:41,514 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendByte [2022-02-20 22:58:41,514 INFO L130 BoogieDeclarations]: Found specification of procedure dev_alloc_skb [2022-02-20 22:58:41,514 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_alloc_skb [2022-02-20 22:58:41,514 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2022-02-20 22:58:41,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2022-02-20 22:58:41,515 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_lock_of_via_ircc_cb [2022-02-20 22:58:41,515 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_lock_of_via_ircc_cb [2022-02-20 22:58:41,515 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendPreambleCount [2022-02-20 22:58:41,515 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendPreambleCount [2022-02-20 22:58:41,515 INFO L130 BoogieDeclarations]: Found specification of procedure InitCard [2022-02-20 22:58:41,515 INFO L138 BoogieDeclarations]: Found implementation of procedure InitCard [2022-02-20 22:58:41,516 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free [2022-02-20 22:58:41,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free [2022-02-20 22:58:41,516 INFO L130 BoogieDeclarations]: Found specification of procedure SetTimer [2022-02-20 22:58:41,516 INFO L138 BoogieDeclarations]: Found implementation of procedure SetTimer [2022-02-20 22:58:41,516 INFO L130 BoogieDeclarations]: Found specification of procedure ActClk [2022-02-20 22:58:41,516 INFO L138 BoogieDeclarations]: Found implementation of procedure ActClk [2022-02-20 22:58:41,516 INFO L130 BoogieDeclarations]: Found specification of procedure request_dma [2022-02-20 22:58:41,516 INFO L138 BoogieDeclarations]: Found implementation of procedure request_dma [2022-02-20 22:58:41,516 INFO L130 BoogieDeclarations]: Found specification of procedure inb [2022-02-20 22:58:41,516 INFO L138 BoogieDeclarations]: Found implementation of procedure inb [2022-02-20 22:58:41,517 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 22:58:41,517 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reset_mac_header [2022-02-20 22:58:41,517 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reset_mac_header [2022-02-20 22:58:41,517 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2022-02-20 22:58:41,517 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2022-02-20 22:58:41,517 INFO L130 BoogieDeclarations]: Found specification of procedure skb_copy_to_linear_data [2022-02-20 22:58:41,517 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_copy_to_linear_data [2022-02-20 22:58:42,006 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 22:58:42,010 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 22:58:42,284 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 22:58:46,509 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 22:58:46,540 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 22:58:46,540 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-02-20 22:58:46,544 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:58:46 BoogieIcfgContainer [2022-02-20 22:58:46,545 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 22:58:46,546 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 22:58:46,546 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 22:58:46,548 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 22:58:46,549 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 10:58:38" (1/3) ... [2022-02-20 22:58:46,549 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@54139f12 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:58:46, skipping insertion in model container [2022-02-20 22:58:46,549 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:58:40" (2/3) ... [2022-02-20 22:58:46,550 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@54139f12 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:58:46, skipping insertion in model container [2022-02-20 22:58:46,550 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:58:46" (3/3) ... [2022-02-20 22:58:46,551 INFO L111 eAbstractionObserver]: Analyzing ICFG linux-3.14_linux-kernel-locking-spinlock_drivers-net-irda-via-ircc.cil.i [2022-02-20 22:58:46,555 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 22:58:46,555 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 3 error locations. [2022-02-20 22:58:46,612 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 22:58:46,619 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 22:58:46,619 INFO L340 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2022-02-20 22:58:46,690 INFO L276 IsEmpty]: Start isEmpty. Operand has 1902 states, 1173 states have (on average 1.298380221653879) internal successors, (1523), 1206 states have internal predecessors, (1523), 635 states have call successors, (635), 91 states have call predecessors, (635), 90 states have return successors, (632), 620 states have call predecessors, (632), 632 states have call successors, (632) [2022-02-20 22:58:46,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2022-02-20 22:58:46,697 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:58:46,697 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:58:46,698 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exitErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_assert_linux_kernel_locking_spinlock__one_thread_double_unlockErr0ASSERT_VIOLATIONERROR_FUNCTION, ldv_assert_linux_kernel_locking_spinlock__one_thread_double_lockErr0ASSERT_VIOLATIONERROR_FUNCTION (and 1 more)] === [2022-02-20 22:58:46,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:58:46,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1136157762, now seen corresponding path program 1 times [2022-02-20 22:58:46,711 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:58:46,712 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985346245] [2022-02-20 22:58:46,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:58:46,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:58:46,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:58:47,205 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:58:47,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:58:47,237 INFO L290 TraceCheckUtils]: 0: Hoare triple {1905#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {1905#true} is VALID [2022-02-20 22:58:47,238 INFO L290 TraceCheckUtils]: 1: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,239 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4692#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,240 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 12 [2022-02-20 22:58:47,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:58:47,256 INFO L290 TraceCheckUtils]: 0: Hoare triple {1905#true} ~expression := #in~expression; {1905#true} is VALID [2022-02-20 22:58:47,257 INFO L290 TraceCheckUtils]: 1: Hoare triple {1905#true} assume !(0 == ~expression); {1905#true} is VALID [2022-02-20 22:58:47,259 INFO L290 TraceCheckUtils]: 2: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,260 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4804#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,260 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2022-02-20 22:58:47,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:58:47,276 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:58:47,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:58:47,287 INFO L290 TraceCheckUtils]: 0: Hoare triple {1905#true} ~expression := #in~expression; {1905#true} is VALID [2022-02-20 22:58:47,288 INFO L290 TraceCheckUtils]: 1: Hoare triple {1905#true} assume !(0 == ~expression); {1905#true} is VALID [2022-02-20 22:58:47,288 INFO L290 TraceCheckUtils]: 2: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,289 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1905#true} {1905#true} #4228#return; {1905#true} is VALID [2022-02-20 22:58:47,289 INFO L290 TraceCheckUtils]: 0: Hoare triple {1905#true} ~val := #in~val; {1905#true} is VALID [2022-02-20 22:58:47,289 INFO L272 TraceCheckUtils]: 1: Hoare triple {1905#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1905#true} is VALID [2022-02-20 22:58:47,290 INFO L290 TraceCheckUtils]: 2: Hoare triple {1905#true} ~expression := #in~expression; {1905#true} is VALID [2022-02-20 22:58:47,290 INFO L290 TraceCheckUtils]: 3: Hoare triple {1905#true} assume !(0 == ~expression); {1905#true} is VALID [2022-02-20 22:58:47,290 INFO L290 TraceCheckUtils]: 4: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,290 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {1905#true} {1905#true} #4228#return; {1905#true} is VALID [2022-02-20 22:58:47,290 INFO L290 TraceCheckUtils]: 6: Hoare triple {1905#true} #res := ~val; {1905#true} is VALID [2022-02-20 22:58:47,291 INFO L290 TraceCheckUtils]: 7: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,292 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4806#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,292 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2022-02-20 22:58:47,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:58:47,303 INFO L290 TraceCheckUtils]: 0: Hoare triple {1905#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {1905#true} is VALID [2022-02-20 22:58:47,304 INFO L290 TraceCheckUtils]: 1: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,304 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4808#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,304 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 41 [2022-02-20 22:58:47,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:58:47,313 INFO L290 TraceCheckUtils]: 0: Hoare triple {1905#true} ~expression := #in~expression; {1905#true} is VALID [2022-02-20 22:58:47,313 INFO L290 TraceCheckUtils]: 1: Hoare triple {1905#true} assume !(0 == ~expression); {1905#true} is VALID [2022-02-20 22:58:47,313 INFO L290 TraceCheckUtils]: 2: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,314 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4810#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,330 INFO L290 TraceCheckUtils]: 0: Hoare triple {1905#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(199, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(9, 4);call #Ultimate.allocInit(9, 5);call #Ultimate.allocInit(7, 6);call write~init~int(15, 6, 0, 1);call write~init~int(37, 6, 1, 1);call write~init~int(115, 6, 2, 1);call write~init~int(40, 6, 3, 1);call write~init~int(41, 6, 4, 1);call write~init~int(10, 6, 5, 1);call write~init~int(0, 6, 6, 1);call #Ultimate.allocInit(14, 7);call #Ultimate.allocInit(9, 8);call #Ultimate.allocInit(45, 9);call #Ultimate.allocInit(14, 10);call #Ultimate.allocInit(25, 11);call #Ultimate.allocInit(13, 12);call #Ultimate.allocInit(22, 13);call #Ultimate.allocInit(13, 14);call #Ultimate.allocInit(23, 15);call #Ultimate.allocInit(13, 16);call #Ultimate.allocInit(23, 17);call #Ultimate.allocInit(13, 18);call #Ultimate.allocInit(22, 19);call #Ultimate.allocInit(13, 20);call #Ultimate.allocInit(7, 21);call write~init~int(15, 21, 0, 1);call write~init~int(37, 21, 1, 1);call write~init~int(115, 21, 2, 1);call write~init~int(40, 21, 3, 1);call write~init~int(41, 21, 4, 1);call write~init~int(10, 21, 5, 1);call write~init~int(0, 21, 6, 1);call #Ultimate.allocInit(17, 22);call #Ultimate.allocInit(7, 23);call write~init~int(15, 23, 0, 1);call write~init~int(37, 23, 1, 1);call write~init~int(115, 23, 2, 1);call write~init~int(40, 23, 3, 1);call write~init~int(41, 23, 4, 1);call write~init~int(10, 23, 5, 1);call write~init~int(0, 23, 6, 1);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(22, 25);call #Ultimate.allocInit(35, 26);call #Ultimate.allocInit(14, 27);call #Ultimate.allocInit(40, 28);call #Ultimate.allocInit(7, 29);call write~init~int(15, 29, 0, 1);call write~init~int(37, 29, 1, 1);call write~init~int(115, 29, 2, 1);call write~init~int(40, 29, 3, 1);call write~init~int(41, 29, 4, 1);call write~init~int(10, 29, 5, 1);call write~init~int(0, 29, 6, 1);call #Ultimate.allocInit(15, 30);call #Ultimate.allocInit(30, 31);call #Ultimate.allocInit(15, 32);call #Ultimate.allocInit(7, 33);call write~init~int(15, 33, 0, 1);call write~init~int(37, 33, 1, 1);call write~init~int(115, 33, 2, 1);call write~init~int(40, 33, 3, 1);call write~init~int(41, 33, 4, 1);call write~init~int(10, 33, 5, 1);call write~init~int(0, 33, 6, 1);call #Ultimate.allocInit(12, 34);call #Ultimate.allocInit(85, 35);call #Ultimate.allocInit(47, 36);call #Ultimate.allocInit(29, 37);call #Ultimate.allocInit(58, 38);call #Ultimate.allocInit(29, 39);call #Ultimate.allocInit(50, 40);call #Ultimate.allocInit(29, 41);call #Ultimate.allocInit(40, 42);call #Ultimate.allocInit(29, 43);call #Ultimate.allocInit(30, 44);call #Ultimate.allocInit(22, 45);call #Ultimate.allocInit(31, 46);call #Ultimate.allocInit(28, 47);call #Ultimate.allocInit(23, 48);call #Ultimate.allocInit(13, 49);call #Ultimate.allocInit(45, 50);call #Ultimate.allocInit(18, 51);call #Ultimate.allocInit(7, 52);call write~init~int(15, 52, 0, 1);call write~init~int(37, 52, 1, 1);call write~init~int(115, 52, 2, 1);call write~init~int(40, 52, 3, 1);call write~init~int(41, 52, 4, 1);call write~init~int(10, 52, 5, 1);call write~init~int(0, 52, 6, 1);call #Ultimate.allocInit(27, 53);call #Ultimate.allocInit(56, 54);call #Ultimate.allocInit(27, 55);call #Ultimate.allocInit(7, 56);call write~init~int(15, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(40, 56, 3, 1);call write~init~int(41, 56, 4, 1);call write~init~int(10, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(21, 57);call #Ultimate.allocInit(50, 58);call #Ultimate.allocInit(30, 59);call #Ultimate.allocInit(41, 60);call #Ultimate.allocInit(30, 61);call #Ultimate.allocInit(26, 62);call #Ultimate.allocInit(30, 63);call #Ultimate.allocInit(15, 64);call #Ultimate.allocInit(14, 65);call #Ultimate.allocInit(23, 66);call #Ultimate.allocInit(15, 67);call #Ultimate.allocInit(48, 68);call #Ultimate.allocInit(15, 69);call #Ultimate.allocInit(43, 70);call #Ultimate.allocInit(19, 71);call #Ultimate.allocInit(6, 72);call write~init~int(84, 72, 0, 1);call write~init~int(105, 72, 1, 1);call write~init~int(109, 72, 2, 1);call write~init~int(101, 72, 3, 1);call write~init~int(114, 72, 4, 1);call write~init~int(0, 72, 5, 1);call #Ultimate.allocInit(1, 73);call write~init~int(0, 73, 0, 1);call #Ultimate.allocInit(3, 74);call write~init~int(84, 74, 0, 1);call write~init~int(120, 74, 1, 1);call write~init~int(0, 74, 2, 1);call #Ultimate.allocInit(1, 75);call write~init~int(0, 75, 0, 1);call #Ultimate.allocInit(3, 76);call write~init~int(82, 76, 0, 1);call write~init~int(120, 76, 1, 1);call write~init~int(0, 76, 2, 1);call #Ultimate.allocInit(1, 77);call write~init~int(0, 77, 0, 1);call #Ultimate.allocInit(38, 78);call #Ultimate.allocInit(19, 79);call #Ultimate.allocInit(13, 80);call #Ultimate.allocInit(1, 81);call write~init~int(0, 81, 0, 1);call #Ultimate.allocInit(4, 82);call write~init~int(69, 82, 0, 1);call write~init~int(79, 82, 1, 1);call write~init~int(77, 82, 2, 1);call write~init~int(0, 82, 3, 1);call #Ultimate.allocInit(1, 83);call write~init~int(0, 83, 0, 1);call #Ultimate.allocInit(11, 84);call #Ultimate.allocInit(1, 85);call write~init~int(0, 85, 0, 1);call #Ultimate.allocInit(10, 86);call #Ultimate.allocInit(1, 87);call write~init~int(0, 87, 0, 1);call #Ultimate.allocInit(47, 88);call #Ultimate.allocInit(19, 89);call #Ultimate.allocInit(9, 90);call #Ultimate.allocInit(1, 91);call write~init~int(0, 91, 0, 1);call #Ultimate.allocInit(8, 92);call #Ultimate.allocInit(1, 93);call write~init~int(0, 93, 0, 1);call #Ultimate.allocInit(12, 94);call #Ultimate.allocInit(1, 95);call write~init~int(0, 95, 0, 1);call #Ultimate.allocInit(4, 96);call write~init~int(69, 96, 0, 1);call write~init~int(79, 96, 1, 1);call write~init~int(70, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(1, 97);call write~init~int(0, 97, 0, 1);call #Ultimate.allocInit(7, 98);call write~init~int(82, 98, 0, 1);call write~init~int(120, 98, 1, 1);call write~init~int(68, 98, 2, 1);call write~init~int(97, 98, 3, 1);call write~init~int(116, 98, 4, 1);call write~init~int(97, 98, 5, 1);call write~init~int(0, 98, 6, 1);call #Ultimate.allocInit(1, 99);call write~init~int(0, 99, 0, 1);call #Ultimate.allocInit(9, 100);call #Ultimate.allocInit(1, 101);call write~init~int(0, 101, 0, 1);call #Ultimate.allocInit(8, 102);call #Ultimate.allocInit(1, 103);call write~init~int(0, 103, 0, 1);call #Ultimate.allocInit(17, 104);call #Ultimate.allocInit(19, 105);call #Ultimate.allocInit(79, 106);call #Ultimate.allocInit(19, 107);call #Ultimate.allocInit(7, 108);call write~init~int(15, 108, 0, 1);call write~init~int(37, 108, 1, 1);call write~init~int(115, 108, 2, 1);call write~init~int(40, 108, 3, 1);call write~init~int(41, 108, 4, 1);call write~init~int(10, 108, 5, 1);call write~init~int(0, 108, 6, 1);call #Ultimate.allocInit(8, 109);call #Ultimate.allocInit(31, 110);call #Ultimate.allocInit(28, 111);call #Ultimate.allocInit(22, 112);call #Ultimate.allocInit(13, 113);call #Ultimate.allocInit(22, 114);call #Ultimate.allocInit(22, 115);call #Ultimate.allocInit(7, 116);call write~init~int(15, 116, 0, 1);call write~init~int(37, 116, 1, 1);call write~init~int(115, 116, 2, 1);call write~init~int(40, 116, 3, 1);call write~init~int(41, 116, 4, 1);call write~init~int(10, 116, 5, 1);call write~init~int(0, 116, 6, 1);call #Ultimate.allocInit(18, 117);call #Ultimate.allocInit(31, 118);call #Ultimate.allocInit(28, 119);call #Ultimate.allocInit(18, 120);call #Ultimate.allocInit(12, 121);call #Ultimate.allocInit(31, 122);call #Ultimate.allocInit(28, 123);call #Ultimate.allocInit(18, 124);call #Ultimate.allocInit(13, 125);call #Ultimate.allocInit(32, 126);call #Ultimate.allocInit(32, 127);call #Ultimate.allocInit(33, 128);call #Ultimate.allocInit(11, 129);call #Ultimate.allocInit(7, 130);call write~init~int(15, 130, 0, 1);call write~init~int(37, 130, 1, 1);call write~init~int(115, 130, 2, 1);call write~init~int(40, 130, 3, 1);call write~init~int(41, 130, 4, 1);call write~init~int(10, 130, 5, 1);call write~init~int(0, 130, 6, 1);call #Ultimate.allocInit(19, 131);call #Ultimate.allocInit(31, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(19, 134);call #Ultimate.allocInit(12, 135);call #Ultimate.allocInit(31, 136);call #Ultimate.allocInit(28, 137);call #Ultimate.allocInit(19, 138);call #Ultimate.allocInit(13, 139);call #Ultimate.allocInit(31, 140);call #Ultimate.allocInit(28, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(12, 143);call #Ultimate.allocInit(31, 144);call #Ultimate.allocInit(28, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(13, 147);call #Ultimate.allocInit(23, 148);call #Ultimate.allocInit(19, 149);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(2, 151);call write~init~int(48, 151, 0, 1);call write~init~int(0, 151, 1, 1);call #Ultimate.allocInit(73, 152);~driver_name~0.base, ~driver_name~0.offset := 4, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 153, 0;call #Ultimate.allocInit(192, 153);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#via_driver~0.base, ~#via_driver~0.offset := 154, 0;call #Ultimate.allocInit(301, 154);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(5, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 145 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 153 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 161 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 169 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 177 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 185 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 193 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 201 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 209 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 217 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 237 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 245 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 253 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 261 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 269 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 285 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 293 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 155, 0;call #Ultimate.allocInit(472, 155);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 156, 0;call #Ultimate.allocInit(472, 156);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_thread_0~0.identifier := 0;~ldv_thread_0~0.function.base, ~ldv_thread_0~0.function.offset := 0, 0;~ldv_thread_1~0.identifier := 0;~ldv_thread_1~0.function.base, ~ldv_thread_1~0.function.offset := 0, 0;~ldv_thread_10~0.identifier := 0;~ldv_thread_10~0.function.base, ~ldv_thread_10~0.function.offset := 0, 0;~ldv_thread_2~0.identifier := 0;~ldv_thread_2~0.function.base, ~ldv_thread_2~0.function.offset := 0, 0;~ldv_spin_NOT_ARG_SIGN~0 := 1;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_dma_spin_lock~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_via_ircc_cb~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,331 INFO L290 TraceCheckUtils]: 1: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_ldv_initialize } true; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,332 INFO L290 TraceCheckUtils]: 2: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_entry_EMGentry_10 } true;ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset := 0, 0;havoc ldv_entry_EMGentry_10_#t~ret831#1, ldv_entry_EMGentry_10_#t~ret832#1, ldv_entry_EMGentry_10_#t~ret833#1, ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1, ldv_entry_EMGentry_10_~tmp~52#1;ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset := ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_entry_EMGentry_10_~tmp~52#1;assume { :begin_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset := ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_#res#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset, ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset := ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;assume { :begin_inline_via_ircc_init } true;havoc via_ircc_init_#res#1;havoc via_ircc_init_#t~nondet244#1, via_ircc_init_#t~ret245#1, via_ircc_init_#t~nondet246#1, via_ircc_init_~rc~0#1;havoc via_ircc_init_~rc~0#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,332 INFO L290 TraceCheckUtils]: 3: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume !(~irda_debug~0 % 4294967296 > 2); {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,332 INFO L290 TraceCheckUtils]: 4: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume { :begin_inline_ldv___pci_register_driver_66 } true;ldv___pci_register_driver_66_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.offset := ~#via_driver~0.base, ~#via_driver~0.offset, ~#__this_module~0.base, ~#__this_module~0.offset, 8, 0;havoc ldv___pci_register_driver_66_#res#1;havoc ldv___pci_register_driver_66_#t~ret900#1, ldv___pci_register_driver_66_#t~ret901#1, ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset, ldv___pci_register_driver_66_~ldv_func_res~0#1, ldv___pci_register_driver_66_~tmp~65#1, ldv___pci_register_driver_66_~tmp___0~20#1;ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg1#1.offset;ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.offset;ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_66_~ldv_func_res~0#1;havoc ldv___pci_register_driver_66_~tmp~65#1;havoc ldv___pci_register_driver_66_~tmp___0~20#1;assume { :begin_inline___pci_register_driver } true;__pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset, __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset, __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset := ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset;havoc __pci_register_driver_#res#1;havoc __pci_register_driver_#t~nondet1022#1, __pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset, __pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset, __pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset;__pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset := __pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset;__pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset := __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset;__pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset := __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset;assume -2147483648 <= __pci_register_driver_#t~nondet1022#1 && __pci_register_driver_#t~nondet1022#1 <= 2147483647;__pci_register_driver_#res#1 := __pci_register_driver_#t~nondet1022#1;havoc __pci_register_driver_#t~nondet1022#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,333 INFO L290 TraceCheckUtils]: 5: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} ldv___pci_register_driver_66_#t~ret900#1 := __pci_register_driver_#res#1;assume { :end_inline___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_66_#t~ret900#1 && ldv___pci_register_driver_66_#t~ret900#1 <= 2147483647;ldv___pci_register_driver_66_~tmp~65#1 := ldv___pci_register_driver_66_#t~ret900#1;havoc ldv___pci_register_driver_66_#t~ret900#1;ldv___pci_register_driver_66_~ldv_func_res~0#1 := ldv___pci_register_driver_66_~tmp~65#1;assume { :begin_inline_ldv___pci_register_driver } true;ldv___pci_register_driver_#in~arg0#1, ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset, ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset, ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset := ldv___pci_register_driver_66_~ldv_func_res~0#1, ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_#res#1;havoc ldv___pci_register_driver_#t~ret825#1, ldv___pci_register_driver_~arg0#1, ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset, ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset, ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset, ldv___pci_register_driver_~tmp~48#1;ldv___pci_register_driver_~arg0#1 := ldv___pci_register_driver_#in~arg0#1;ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset := ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset;ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset := ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset;ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset := ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset;havoc ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset;havoc ldv___pci_register_driver_~tmp~48#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,333 INFO L272 TraceCheckUtils]: 6: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} call ldv___pci_register_driver_#t~ret825#1 := ldv_undef_int(); {1905#true} is VALID [2022-02-20 22:58:47,333 INFO L290 TraceCheckUtils]: 7: Hoare triple {1905#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {1905#true} is VALID [2022-02-20 22:58:47,333 INFO L290 TraceCheckUtils]: 8: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,334 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4692#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,335 INFO L290 TraceCheckUtils]: 10: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume -2147483648 <= ldv___pci_register_driver_#t~ret825#1 && ldv___pci_register_driver_#t~ret825#1 <= 2147483647;ldv___pci_register_driver_~tmp~48#1 := ldv___pci_register_driver_#t~ret825#1;havoc ldv___pci_register_driver_#t~ret825#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,335 INFO L290 TraceCheckUtils]: 11: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume !(0 != ldv___pci_register_driver_~tmp~48#1); {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,335 INFO L272 TraceCheckUtils]: 12: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} call ldv_assume((if 0 != ldv___pci_register_driver_~arg0#1 then 1 else 0)); {1905#true} is VALID [2022-02-20 22:58:47,335 INFO L290 TraceCheckUtils]: 13: Hoare triple {1905#true} ~expression := #in~expression; {1905#true} is VALID [2022-02-20 22:58:47,336 INFO L290 TraceCheckUtils]: 14: Hoare triple {1905#true} assume !(0 == ~expression); {1905#true} is VALID [2022-02-20 22:58:47,336 INFO L290 TraceCheckUtils]: 15: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,336 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4804#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,337 INFO L290 TraceCheckUtils]: 17: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} ldv___pci_register_driver_#res#1 := ldv___pci_register_driver_~arg0#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,337 INFO L290 TraceCheckUtils]: 18: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} ldv___pci_register_driver_66_#t~ret901#1 := ldv___pci_register_driver_#res#1;assume { :end_inline_ldv___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_66_#t~ret901#1 && ldv___pci_register_driver_66_#t~ret901#1 <= 2147483647;ldv___pci_register_driver_66_~tmp___0~20#1 := ldv___pci_register_driver_66_#t~ret901#1;havoc ldv___pci_register_driver_66_#t~ret901#1;ldv___pci_register_driver_66_#res#1 := ldv___pci_register_driver_66_~tmp___0~20#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,337 INFO L290 TraceCheckUtils]: 19: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} via_ircc_init_#t~ret245#1 := ldv___pci_register_driver_66_#res#1;assume { :end_inline_ldv___pci_register_driver_66 } true;assume -2147483648 <= via_ircc_init_#t~ret245#1 && via_ircc_init_#t~ret245#1 <= 2147483647;via_ircc_init_~rc~0#1 := via_ircc_init_#t~ret245#1;havoc via_ircc_init_#t~ret245#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,341 INFO L290 TraceCheckUtils]: 20: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume via_ircc_init_~rc~0#1 < 0;havoc via_ircc_init_#t~nondet246#1;via_ircc_init_#res#1 := -19; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,342 INFO L290 TraceCheckUtils]: 21: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 := via_ircc_init_#res#1;assume { :end_inline_via_ircc_init } true;assume -2147483648 <= ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 && ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 <= 2147483647;ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1 := ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1;ldv_EMGentry_init_via_ircc_init_10_7_#res#1 := ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,342 INFO L290 TraceCheckUtils]: 22: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} ldv_entry_EMGentry_10_#t~ret831#1 := ldv_EMGentry_init_via_ircc_init_10_7_#res#1;assume { :end_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret831#1 && ldv_entry_EMGentry_10_#t~ret831#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret831#1;havoc ldv_entry_EMGentry_10_#t~ret831#1;assume { :begin_inline_ldv_post_init } true;ldv_post_init_#in~init_ret_val#1 := ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_post_init_#res#1;havoc ldv_post_init_#t~ret915#1, ldv_post_init_~init_ret_val#1, ldv_post_init_~tmp~71#1;ldv_post_init_~init_ret_val#1 := ldv_post_init_#in~init_ret_val#1;havoc ldv_post_init_~tmp~71#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,347 INFO L272 TraceCheckUtils]: 23: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} call ldv_post_init_#t~ret915#1 := ldv_filter_positive_int(ldv_post_init_~init_ret_val#1); {1905#true} is VALID [2022-02-20 22:58:47,348 INFO L290 TraceCheckUtils]: 24: Hoare triple {1905#true} ~val := #in~val; {1905#true} is VALID [2022-02-20 22:58:47,348 INFO L272 TraceCheckUtils]: 25: Hoare triple {1905#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1905#true} is VALID [2022-02-20 22:58:47,348 INFO L290 TraceCheckUtils]: 26: Hoare triple {1905#true} ~expression := #in~expression; {1905#true} is VALID [2022-02-20 22:58:47,348 INFO L290 TraceCheckUtils]: 27: Hoare triple {1905#true} assume !(0 == ~expression); {1905#true} is VALID [2022-02-20 22:58:47,348 INFO L290 TraceCheckUtils]: 28: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,349 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {1905#true} {1905#true} #4228#return; {1905#true} is VALID [2022-02-20 22:58:47,349 INFO L290 TraceCheckUtils]: 30: Hoare triple {1905#true} #res := ~val; {1905#true} is VALID [2022-02-20 22:58:47,349 INFO L290 TraceCheckUtils]: 31: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,350 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4806#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,351 INFO L290 TraceCheckUtils]: 33: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume -2147483648 <= ldv_post_init_#t~ret915#1 && ldv_post_init_#t~ret915#1 <= 2147483647;ldv_post_init_~tmp~71#1 := ldv_post_init_#t~ret915#1;havoc ldv_post_init_#t~ret915#1;ldv_post_init_#res#1 := ldv_post_init_~tmp~71#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,352 INFO L290 TraceCheckUtils]: 34: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} ldv_entry_EMGentry_10_#t~ret832#1 := ldv_post_init_#res#1;assume { :end_inline_ldv_post_init } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret832#1 && ldv_entry_EMGentry_10_#t~ret832#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret832#1;havoc ldv_entry_EMGentry_10_#t~ret832#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,352 INFO L272 TraceCheckUtils]: 35: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} call ldv_entry_EMGentry_10_#t~ret833#1 := ldv_undef_int(); {1905#true} is VALID [2022-02-20 22:58:47,352 INFO L290 TraceCheckUtils]: 36: Hoare triple {1905#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {1905#true} is VALID [2022-02-20 22:58:47,352 INFO L290 TraceCheckUtils]: 37: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,353 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4808#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,353 INFO L290 TraceCheckUtils]: 39: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret833#1 && ldv_entry_EMGentry_10_#t~ret833#1 <= 2147483647;ldv_entry_EMGentry_10_~tmp~52#1 := ldv_entry_EMGentry_10_#t~ret833#1;havoc ldv_entry_EMGentry_10_#t~ret833#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,354 INFO L290 TraceCheckUtils]: 40: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} assume 0 != ldv_entry_EMGentry_10_~tmp~52#1; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,354 INFO L272 TraceCheckUtils]: 41: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} call ldv_assume((if 0 != ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 then 1 else 0)); {1905#true} is VALID [2022-02-20 22:58:47,354 INFO L290 TraceCheckUtils]: 42: Hoare triple {1905#true} ~expression := #in~expression; {1905#true} is VALID [2022-02-20 22:58:47,354 INFO L290 TraceCheckUtils]: 43: Hoare triple {1905#true} assume !(0 == ~expression); {1905#true} is VALID [2022-02-20 22:58:47,354 INFO L290 TraceCheckUtils]: 44: Hoare triple {1905#true} assume true; {1905#true} is VALID [2022-02-20 22:58:47,355 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {1905#true} {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} #4810#return; {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,355 INFO L272 TraceCheckUtils]: 46: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} call ldv_check_final_state(); {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} is VALID [2022-02-20 22:58:47,356 INFO L272 TraceCheckUtils]: 47: Hoare triple {1907#(= ~ldv_spin_NOT_ARG_SIGN~0 1)} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin_NOT_ARG_SIGN~0 then 1 else 0)); {1931#(not (= |ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_#in~expr| 0))} is VALID [2022-02-20 22:58:47,356 INFO L290 TraceCheckUtils]: 48: Hoare triple {1931#(not (= |ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_#in~expr| 0))} ~expr := #in~expr; {1932#(not (= ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_~expr 0))} is VALID [2022-02-20 22:58:47,357 INFO L290 TraceCheckUtils]: 49: Hoare triple {1932#(not (= ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_~expr 0))} assume 0 == ~expr; {1906#false} is VALID [2022-02-20 22:58:47,357 INFO L290 TraceCheckUtils]: 50: Hoare triple {1906#false} assume !false; {1906#false} is VALID [2022-02-20 22:58:47,358 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2022-02-20 22:58:47,359 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:58:47,359 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985346245] [2022-02-20 22:58:47,360 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985346245] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:58:47,360 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:58:47,360 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-20 22:58:47,363 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481286615] [2022-02-20 22:58:47,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:58:47,367 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 5.8) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 51 [2022-02-20 22:58:47,369 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:58:47,372 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 5.8) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:58:47,430 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:58:47,430 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-02-20 22:58:47,431 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:58:47,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-20 22:58:47,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-20 22:58:47,456 INFO L87 Difference]: Start difference. First operand has 1902 states, 1173 states have (on average 1.298380221653879) internal successors, (1523), 1206 states have internal predecessors, (1523), 635 states have call successors, (635), 91 states have call predecessors, (635), 90 states have return successors, (632), 620 states have call predecessors, (632), 632 states have call successors, (632) Second operand has 5 states, 5 states have (on average 5.8) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:58:57,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:58:57,550 INFO L93 Difference]: Finished difference Result 3777 states and 5648 transitions. [2022-02-20 22:58:57,550 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-20 22:58:57,550 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 5.8) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 51 [2022-02-20 22:58:57,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:58:57,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 5.8) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:58:58,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 5648 transitions. [2022-02-20 22:58:58,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 5.8) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:58:58,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 5648 transitions. [2022-02-20 22:58:58,313 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 5648 transitions. [2022-02-20 22:59:02,518 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 5648 edges. 5648 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:59:03,025 INFO L225 Difference]: With dead ends: 3777 [2022-02-20 22:59:03,026 INFO L226 Difference]: Without dead ends: 1894 [2022-02-20 22:59:03,047 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-02-20 22:59:03,052 INFO L933 BasicCegarLoop]: 2732 mSDtfsCounter, 2706 mSDsluCounter, 5449 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2720 SdHoareTripleChecker+Valid, 8181 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-02-20 22:59:03,053 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [2720 Valid, 8181 Invalid, 22 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-02-20 22:59:03,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1894 states. [2022-02-20 22:59:03,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1894 to 1894. [2022-02-20 22:59:03,212 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:59:03,228 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1894 states. Second operand has 1894 states, 1169 states have (on average 1.2540633019674936) internal successors, (1466), 1202 states have internal predecessors, (1466), 632 states have call successors, (632), 91 states have call predecessors, (632), 90 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:03,234 INFO L74 IsIncluded]: Start isIncluded. First operand 1894 states. Second operand has 1894 states, 1169 states have (on average 1.2540633019674936) internal successors, (1466), 1202 states have internal predecessors, (1466), 632 states have call successors, (632), 91 states have call predecessors, (632), 90 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:03,240 INFO L87 Difference]: Start difference. First operand 1894 states. Second operand has 1894 states, 1169 states have (on average 1.2540633019674936) internal successors, (1466), 1202 states have internal predecessors, (1466), 632 states have call successors, (632), 91 states have call predecessors, (632), 90 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:03,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:59:03,387 INFO L93 Difference]: Finished difference Result 1894 states and 2727 transitions. [2022-02-20 22:59:03,387 INFO L276 IsEmpty]: Start isEmpty. Operand 1894 states and 2727 transitions. [2022-02-20 22:59:03,405 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:59:03,406 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:59:03,411 INFO L74 IsIncluded]: Start isIncluded. First operand has 1894 states, 1169 states have (on average 1.2540633019674936) internal successors, (1466), 1202 states have internal predecessors, (1466), 632 states have call successors, (632), 91 states have call predecessors, (632), 90 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) Second operand 1894 states. [2022-02-20 22:59:03,416 INFO L87 Difference]: Start difference. First operand has 1894 states, 1169 states have (on average 1.2540633019674936) internal successors, (1466), 1202 states have internal predecessors, (1466), 632 states have call successors, (632), 91 states have call predecessors, (632), 90 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) Second operand 1894 states. [2022-02-20 22:59:03,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:59:03,559 INFO L93 Difference]: Finished difference Result 1894 states and 2727 transitions. [2022-02-20 22:59:03,559 INFO L276 IsEmpty]: Start isEmpty. Operand 1894 states and 2727 transitions. [2022-02-20 22:59:03,571 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:59:03,571 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:59:03,572 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:59:03,572 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:59:03,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1894 states, 1169 states have (on average 1.2540633019674936) internal successors, (1466), 1202 states have internal predecessors, (1466), 632 states have call successors, (632), 91 states have call predecessors, (632), 90 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:03,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1894 states to 1894 states and 2727 transitions. [2022-02-20 22:59:03,780 INFO L78 Accepts]: Start accepts. Automaton has 1894 states and 2727 transitions. Word has length 51 [2022-02-20 22:59:03,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:59:03,781 INFO L470 AbstractCegarLoop]: Abstraction has 1894 states and 2727 transitions. [2022-02-20 22:59:03,781 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 5.8) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:59:03,781 INFO L276 IsEmpty]: Start isEmpty. Operand 1894 states and 2727 transitions. [2022-02-20 22:59:03,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2022-02-20 22:59:03,783 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:59:03,783 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:59:03,783 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-02-20 22:59:03,784 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exitErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_assert_linux_kernel_locking_spinlock__one_thread_double_unlockErr0ASSERT_VIOLATIONERROR_FUNCTION, ldv_assert_linux_kernel_locking_spinlock__one_thread_double_lockErr0ASSERT_VIOLATIONERROR_FUNCTION (and 1 more)] === [2022-02-20 22:59:03,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:59:03,784 INFO L85 PathProgramCache]: Analyzing trace with hash 1221928255, now seen corresponding path program 1 times [2022-02-20 22:59:03,785 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:59:03,785 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144253848] [2022-02-20 22:59:03,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:59:03,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:59:03,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:03,946 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:59:03,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:03,956 INFO L290 TraceCheckUtils]: 0: Hoare triple {14086#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {14086#true} is VALID [2022-02-20 22:59:03,957 INFO L290 TraceCheckUtils]: 1: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:03,957 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4692#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:03,957 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 12 [2022-02-20 22:59:03,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:03,964 INFO L290 TraceCheckUtils]: 0: Hoare triple {14086#true} ~expression := #in~expression; {14086#true} is VALID [2022-02-20 22:59:03,965 INFO L290 TraceCheckUtils]: 1: Hoare triple {14086#true} assume !(0 == ~expression); {14086#true} is VALID [2022-02-20 22:59:03,965 INFO L290 TraceCheckUtils]: 2: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:03,965 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4804#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:03,965 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2022-02-20 22:59:03,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:03,980 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:59:03,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:03,988 INFO L290 TraceCheckUtils]: 0: Hoare triple {14086#true} ~expression := #in~expression; {14086#true} is VALID [2022-02-20 22:59:03,988 INFO L290 TraceCheckUtils]: 1: Hoare triple {14086#true} assume !(0 == ~expression); {14086#true} is VALID [2022-02-20 22:59:03,988 INFO L290 TraceCheckUtils]: 2: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:03,988 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14086#true} {14086#true} #4228#return; {14086#true} is VALID [2022-02-20 22:59:03,989 INFO L290 TraceCheckUtils]: 0: Hoare triple {14086#true} ~val := #in~val; {14086#true} is VALID [2022-02-20 22:59:03,990 INFO L272 TraceCheckUtils]: 1: Hoare triple {14086#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {14086#true} is VALID [2022-02-20 22:59:03,990 INFO L290 TraceCheckUtils]: 2: Hoare triple {14086#true} ~expression := #in~expression; {14086#true} is VALID [2022-02-20 22:59:03,990 INFO L290 TraceCheckUtils]: 3: Hoare triple {14086#true} assume !(0 == ~expression); {14086#true} is VALID [2022-02-20 22:59:03,990 INFO L290 TraceCheckUtils]: 4: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:03,990 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {14086#true} {14086#true} #4228#return; {14086#true} is VALID [2022-02-20 22:59:03,990 INFO L290 TraceCheckUtils]: 6: Hoare triple {14086#true} #res := ~val; {14086#true} is VALID [2022-02-20 22:59:03,991 INFO L290 TraceCheckUtils]: 7: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:03,991 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4806#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:03,991 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2022-02-20 22:59:03,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:03,999 INFO L290 TraceCheckUtils]: 0: Hoare triple {14086#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {14086#true} is VALID [2022-02-20 22:59:04,002 INFO L290 TraceCheckUtils]: 1: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,004 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4808#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,004 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 41 [2022-02-20 22:59:04,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:04,013 INFO L290 TraceCheckUtils]: 0: Hoare triple {14086#true} ~expression := #in~expression; {14086#true} is VALID [2022-02-20 22:59:04,013 INFO L290 TraceCheckUtils]: 1: Hoare triple {14086#true} assume !(0 == ~expression); {14086#true} is VALID [2022-02-20 22:59:04,013 INFO L290 TraceCheckUtils]: 2: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,014 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4810#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,014 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 47 [2022-02-20 22:59:04,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:04,022 INFO L290 TraceCheckUtils]: 0: Hoare triple {14086#true} ~expr := #in~expr; {14086#true} is VALID [2022-02-20 22:59:04,022 INFO L290 TraceCheckUtils]: 1: Hoare triple {14086#true} assume !(0 == ~expr); {14086#true} is VALID [2022-02-20 22:59:04,023 INFO L290 TraceCheckUtils]: 2: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,024 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4648#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,025 INFO L290 TraceCheckUtils]: 0: Hoare triple {14086#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(199, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(9, 4);call #Ultimate.allocInit(9, 5);call #Ultimate.allocInit(7, 6);call write~init~int(15, 6, 0, 1);call write~init~int(37, 6, 1, 1);call write~init~int(115, 6, 2, 1);call write~init~int(40, 6, 3, 1);call write~init~int(41, 6, 4, 1);call write~init~int(10, 6, 5, 1);call write~init~int(0, 6, 6, 1);call #Ultimate.allocInit(14, 7);call #Ultimate.allocInit(9, 8);call #Ultimate.allocInit(45, 9);call #Ultimate.allocInit(14, 10);call #Ultimate.allocInit(25, 11);call #Ultimate.allocInit(13, 12);call #Ultimate.allocInit(22, 13);call #Ultimate.allocInit(13, 14);call #Ultimate.allocInit(23, 15);call #Ultimate.allocInit(13, 16);call #Ultimate.allocInit(23, 17);call #Ultimate.allocInit(13, 18);call #Ultimate.allocInit(22, 19);call #Ultimate.allocInit(13, 20);call #Ultimate.allocInit(7, 21);call write~init~int(15, 21, 0, 1);call write~init~int(37, 21, 1, 1);call write~init~int(115, 21, 2, 1);call write~init~int(40, 21, 3, 1);call write~init~int(41, 21, 4, 1);call write~init~int(10, 21, 5, 1);call write~init~int(0, 21, 6, 1);call #Ultimate.allocInit(17, 22);call #Ultimate.allocInit(7, 23);call write~init~int(15, 23, 0, 1);call write~init~int(37, 23, 1, 1);call write~init~int(115, 23, 2, 1);call write~init~int(40, 23, 3, 1);call write~init~int(41, 23, 4, 1);call write~init~int(10, 23, 5, 1);call write~init~int(0, 23, 6, 1);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(22, 25);call #Ultimate.allocInit(35, 26);call #Ultimate.allocInit(14, 27);call #Ultimate.allocInit(40, 28);call #Ultimate.allocInit(7, 29);call write~init~int(15, 29, 0, 1);call write~init~int(37, 29, 1, 1);call write~init~int(115, 29, 2, 1);call write~init~int(40, 29, 3, 1);call write~init~int(41, 29, 4, 1);call write~init~int(10, 29, 5, 1);call write~init~int(0, 29, 6, 1);call #Ultimate.allocInit(15, 30);call #Ultimate.allocInit(30, 31);call #Ultimate.allocInit(15, 32);call #Ultimate.allocInit(7, 33);call write~init~int(15, 33, 0, 1);call write~init~int(37, 33, 1, 1);call write~init~int(115, 33, 2, 1);call write~init~int(40, 33, 3, 1);call write~init~int(41, 33, 4, 1);call write~init~int(10, 33, 5, 1);call write~init~int(0, 33, 6, 1);call #Ultimate.allocInit(12, 34);call #Ultimate.allocInit(85, 35);call #Ultimate.allocInit(47, 36);call #Ultimate.allocInit(29, 37);call #Ultimate.allocInit(58, 38);call #Ultimate.allocInit(29, 39);call #Ultimate.allocInit(50, 40);call #Ultimate.allocInit(29, 41);call #Ultimate.allocInit(40, 42);call #Ultimate.allocInit(29, 43);call #Ultimate.allocInit(30, 44);call #Ultimate.allocInit(22, 45);call #Ultimate.allocInit(31, 46);call #Ultimate.allocInit(28, 47);call #Ultimate.allocInit(23, 48);call #Ultimate.allocInit(13, 49);call #Ultimate.allocInit(45, 50);call #Ultimate.allocInit(18, 51);call #Ultimate.allocInit(7, 52);call write~init~int(15, 52, 0, 1);call write~init~int(37, 52, 1, 1);call write~init~int(115, 52, 2, 1);call write~init~int(40, 52, 3, 1);call write~init~int(41, 52, 4, 1);call write~init~int(10, 52, 5, 1);call write~init~int(0, 52, 6, 1);call #Ultimate.allocInit(27, 53);call #Ultimate.allocInit(56, 54);call #Ultimate.allocInit(27, 55);call #Ultimate.allocInit(7, 56);call write~init~int(15, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(40, 56, 3, 1);call write~init~int(41, 56, 4, 1);call write~init~int(10, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(21, 57);call #Ultimate.allocInit(50, 58);call #Ultimate.allocInit(30, 59);call #Ultimate.allocInit(41, 60);call #Ultimate.allocInit(30, 61);call #Ultimate.allocInit(26, 62);call #Ultimate.allocInit(30, 63);call #Ultimate.allocInit(15, 64);call #Ultimate.allocInit(14, 65);call #Ultimate.allocInit(23, 66);call #Ultimate.allocInit(15, 67);call #Ultimate.allocInit(48, 68);call #Ultimate.allocInit(15, 69);call #Ultimate.allocInit(43, 70);call #Ultimate.allocInit(19, 71);call #Ultimate.allocInit(6, 72);call write~init~int(84, 72, 0, 1);call write~init~int(105, 72, 1, 1);call write~init~int(109, 72, 2, 1);call write~init~int(101, 72, 3, 1);call write~init~int(114, 72, 4, 1);call write~init~int(0, 72, 5, 1);call #Ultimate.allocInit(1, 73);call write~init~int(0, 73, 0, 1);call #Ultimate.allocInit(3, 74);call write~init~int(84, 74, 0, 1);call write~init~int(120, 74, 1, 1);call write~init~int(0, 74, 2, 1);call #Ultimate.allocInit(1, 75);call write~init~int(0, 75, 0, 1);call #Ultimate.allocInit(3, 76);call write~init~int(82, 76, 0, 1);call write~init~int(120, 76, 1, 1);call write~init~int(0, 76, 2, 1);call #Ultimate.allocInit(1, 77);call write~init~int(0, 77, 0, 1);call #Ultimate.allocInit(38, 78);call #Ultimate.allocInit(19, 79);call #Ultimate.allocInit(13, 80);call #Ultimate.allocInit(1, 81);call write~init~int(0, 81, 0, 1);call #Ultimate.allocInit(4, 82);call write~init~int(69, 82, 0, 1);call write~init~int(79, 82, 1, 1);call write~init~int(77, 82, 2, 1);call write~init~int(0, 82, 3, 1);call #Ultimate.allocInit(1, 83);call write~init~int(0, 83, 0, 1);call #Ultimate.allocInit(11, 84);call #Ultimate.allocInit(1, 85);call write~init~int(0, 85, 0, 1);call #Ultimate.allocInit(10, 86);call #Ultimate.allocInit(1, 87);call write~init~int(0, 87, 0, 1);call #Ultimate.allocInit(47, 88);call #Ultimate.allocInit(19, 89);call #Ultimate.allocInit(9, 90);call #Ultimate.allocInit(1, 91);call write~init~int(0, 91, 0, 1);call #Ultimate.allocInit(8, 92);call #Ultimate.allocInit(1, 93);call write~init~int(0, 93, 0, 1);call #Ultimate.allocInit(12, 94);call #Ultimate.allocInit(1, 95);call write~init~int(0, 95, 0, 1);call #Ultimate.allocInit(4, 96);call write~init~int(69, 96, 0, 1);call write~init~int(79, 96, 1, 1);call write~init~int(70, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(1, 97);call write~init~int(0, 97, 0, 1);call #Ultimate.allocInit(7, 98);call write~init~int(82, 98, 0, 1);call write~init~int(120, 98, 1, 1);call write~init~int(68, 98, 2, 1);call write~init~int(97, 98, 3, 1);call write~init~int(116, 98, 4, 1);call write~init~int(97, 98, 5, 1);call write~init~int(0, 98, 6, 1);call #Ultimate.allocInit(1, 99);call write~init~int(0, 99, 0, 1);call #Ultimate.allocInit(9, 100);call #Ultimate.allocInit(1, 101);call write~init~int(0, 101, 0, 1);call #Ultimate.allocInit(8, 102);call #Ultimate.allocInit(1, 103);call write~init~int(0, 103, 0, 1);call #Ultimate.allocInit(17, 104);call #Ultimate.allocInit(19, 105);call #Ultimate.allocInit(79, 106);call #Ultimate.allocInit(19, 107);call #Ultimate.allocInit(7, 108);call write~init~int(15, 108, 0, 1);call write~init~int(37, 108, 1, 1);call write~init~int(115, 108, 2, 1);call write~init~int(40, 108, 3, 1);call write~init~int(41, 108, 4, 1);call write~init~int(10, 108, 5, 1);call write~init~int(0, 108, 6, 1);call #Ultimate.allocInit(8, 109);call #Ultimate.allocInit(31, 110);call #Ultimate.allocInit(28, 111);call #Ultimate.allocInit(22, 112);call #Ultimate.allocInit(13, 113);call #Ultimate.allocInit(22, 114);call #Ultimate.allocInit(22, 115);call #Ultimate.allocInit(7, 116);call write~init~int(15, 116, 0, 1);call write~init~int(37, 116, 1, 1);call write~init~int(115, 116, 2, 1);call write~init~int(40, 116, 3, 1);call write~init~int(41, 116, 4, 1);call write~init~int(10, 116, 5, 1);call write~init~int(0, 116, 6, 1);call #Ultimate.allocInit(18, 117);call #Ultimate.allocInit(31, 118);call #Ultimate.allocInit(28, 119);call #Ultimate.allocInit(18, 120);call #Ultimate.allocInit(12, 121);call #Ultimate.allocInit(31, 122);call #Ultimate.allocInit(28, 123);call #Ultimate.allocInit(18, 124);call #Ultimate.allocInit(13, 125);call #Ultimate.allocInit(32, 126);call #Ultimate.allocInit(32, 127);call #Ultimate.allocInit(33, 128);call #Ultimate.allocInit(11, 129);call #Ultimate.allocInit(7, 130);call write~init~int(15, 130, 0, 1);call write~init~int(37, 130, 1, 1);call write~init~int(115, 130, 2, 1);call write~init~int(40, 130, 3, 1);call write~init~int(41, 130, 4, 1);call write~init~int(10, 130, 5, 1);call write~init~int(0, 130, 6, 1);call #Ultimate.allocInit(19, 131);call #Ultimate.allocInit(31, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(19, 134);call #Ultimate.allocInit(12, 135);call #Ultimate.allocInit(31, 136);call #Ultimate.allocInit(28, 137);call #Ultimate.allocInit(19, 138);call #Ultimate.allocInit(13, 139);call #Ultimate.allocInit(31, 140);call #Ultimate.allocInit(28, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(12, 143);call #Ultimate.allocInit(31, 144);call #Ultimate.allocInit(28, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(13, 147);call #Ultimate.allocInit(23, 148);call #Ultimate.allocInit(19, 149);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(2, 151);call write~init~int(48, 151, 0, 1);call write~init~int(0, 151, 1, 1);call #Ultimate.allocInit(73, 152);~driver_name~0.base, ~driver_name~0.offset := 4, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 153, 0;call #Ultimate.allocInit(192, 153);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#via_driver~0.base, ~#via_driver~0.offset := 154, 0;call #Ultimate.allocInit(301, 154);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(5, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 145 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 153 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 161 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 169 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 177 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 185 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 193 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 201 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 209 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 217 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 237 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 245 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 253 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 261 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 269 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 285 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 293 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 155, 0;call #Ultimate.allocInit(472, 155);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 156, 0;call #Ultimate.allocInit(472, 156);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_thread_0~0.identifier := 0;~ldv_thread_0~0.function.base, ~ldv_thread_0~0.function.offset := 0, 0;~ldv_thread_1~0.identifier := 0;~ldv_thread_1~0.function.base, ~ldv_thread_1~0.function.offset := 0, 0;~ldv_thread_10~0.identifier := 0;~ldv_thread_10~0.function.base, ~ldv_thread_10~0.function.offset := 0, 0;~ldv_thread_2~0.identifier := 0;~ldv_thread_2~0.function.base, ~ldv_thread_2~0.function.offset := 0, 0;~ldv_spin_NOT_ARG_SIGN~0 := 1;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_dma_spin_lock~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_via_ircc_cb~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,026 INFO L290 TraceCheckUtils]: 1: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_ldv_initialize } true; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,027 INFO L290 TraceCheckUtils]: 2: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_entry_EMGentry_10 } true;ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset := 0, 0;havoc ldv_entry_EMGentry_10_#t~ret831#1, ldv_entry_EMGentry_10_#t~ret832#1, ldv_entry_EMGentry_10_#t~ret833#1, ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1, ldv_entry_EMGentry_10_~tmp~52#1;ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset := ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_entry_EMGentry_10_~tmp~52#1;assume { :begin_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset := ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_#res#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset, ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset := ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;assume { :begin_inline_via_ircc_init } true;havoc via_ircc_init_#res#1;havoc via_ircc_init_#t~nondet244#1, via_ircc_init_#t~ret245#1, via_ircc_init_#t~nondet246#1, via_ircc_init_~rc~0#1;havoc via_ircc_init_~rc~0#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,027 INFO L290 TraceCheckUtils]: 3: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(~irda_debug~0 % 4294967296 > 2); {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,034 INFO L290 TraceCheckUtils]: 4: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume { :begin_inline_ldv___pci_register_driver_66 } true;ldv___pci_register_driver_66_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.offset := ~#via_driver~0.base, ~#via_driver~0.offset, ~#__this_module~0.base, ~#__this_module~0.offset, 8, 0;havoc ldv___pci_register_driver_66_#res#1;havoc ldv___pci_register_driver_66_#t~ret900#1, ldv___pci_register_driver_66_#t~ret901#1, ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset, ldv___pci_register_driver_66_~ldv_func_res~0#1, ldv___pci_register_driver_66_~tmp~65#1, ldv___pci_register_driver_66_~tmp___0~20#1;ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg1#1.offset;ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.offset;ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_66_~ldv_func_res~0#1;havoc ldv___pci_register_driver_66_~tmp~65#1;havoc ldv___pci_register_driver_66_~tmp___0~20#1;assume { :begin_inline___pci_register_driver } true;__pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset, __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset, __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset := ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset;havoc __pci_register_driver_#res#1;havoc __pci_register_driver_#t~nondet1022#1, __pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset, __pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset, __pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset;__pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset := __pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset;__pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset := __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset;__pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset := __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset;assume -2147483648 <= __pci_register_driver_#t~nondet1022#1 && __pci_register_driver_#t~nondet1022#1 <= 2147483647;__pci_register_driver_#res#1 := __pci_register_driver_#t~nondet1022#1;havoc __pci_register_driver_#t~nondet1022#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,036 INFO L290 TraceCheckUtils]: 5: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv___pci_register_driver_66_#t~ret900#1 := __pci_register_driver_#res#1;assume { :end_inline___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_66_#t~ret900#1 && ldv___pci_register_driver_66_#t~ret900#1 <= 2147483647;ldv___pci_register_driver_66_~tmp~65#1 := ldv___pci_register_driver_66_#t~ret900#1;havoc ldv___pci_register_driver_66_#t~ret900#1;ldv___pci_register_driver_66_~ldv_func_res~0#1 := ldv___pci_register_driver_66_~tmp~65#1;assume { :begin_inline_ldv___pci_register_driver } true;ldv___pci_register_driver_#in~arg0#1, ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset, ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset, ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset := ldv___pci_register_driver_66_~ldv_func_res~0#1, ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_#res#1;havoc ldv___pci_register_driver_#t~ret825#1, ldv___pci_register_driver_~arg0#1, ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset, ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset, ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset, ldv___pci_register_driver_~tmp~48#1;ldv___pci_register_driver_~arg0#1 := ldv___pci_register_driver_#in~arg0#1;ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset := ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset;ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset := ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset;ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset := ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset;havoc ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset;havoc ldv___pci_register_driver_~tmp~48#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,037 INFO L272 TraceCheckUtils]: 6: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv___pci_register_driver_#t~ret825#1 := ldv_undef_int(); {14086#true} is VALID [2022-02-20 22:59:04,037 INFO L290 TraceCheckUtils]: 7: Hoare triple {14086#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {14086#true} is VALID [2022-02-20 22:59:04,038 INFO L290 TraceCheckUtils]: 8: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,038 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4692#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,039 INFO L290 TraceCheckUtils]: 10: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume -2147483648 <= ldv___pci_register_driver_#t~ret825#1 && ldv___pci_register_driver_#t~ret825#1 <= 2147483647;ldv___pci_register_driver_~tmp~48#1 := ldv___pci_register_driver_#t~ret825#1;havoc ldv___pci_register_driver_#t~ret825#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,039 INFO L290 TraceCheckUtils]: 11: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume !(0 != ldv___pci_register_driver_~tmp~48#1); {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,039 INFO L272 TraceCheckUtils]: 12: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_assume((if 0 != ldv___pci_register_driver_~arg0#1 then 1 else 0)); {14086#true} is VALID [2022-02-20 22:59:04,039 INFO L290 TraceCheckUtils]: 13: Hoare triple {14086#true} ~expression := #in~expression; {14086#true} is VALID [2022-02-20 22:59:04,040 INFO L290 TraceCheckUtils]: 14: Hoare triple {14086#true} assume !(0 == ~expression); {14086#true} is VALID [2022-02-20 22:59:04,040 INFO L290 TraceCheckUtils]: 15: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,040 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4804#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,040 INFO L290 TraceCheckUtils]: 17: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv___pci_register_driver_#res#1 := ldv___pci_register_driver_~arg0#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,041 INFO L290 TraceCheckUtils]: 18: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv___pci_register_driver_66_#t~ret901#1 := ldv___pci_register_driver_#res#1;assume { :end_inline_ldv___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_66_#t~ret901#1 && ldv___pci_register_driver_66_#t~ret901#1 <= 2147483647;ldv___pci_register_driver_66_~tmp___0~20#1 := ldv___pci_register_driver_66_#t~ret901#1;havoc ldv___pci_register_driver_66_#t~ret901#1;ldv___pci_register_driver_66_#res#1 := ldv___pci_register_driver_66_~tmp___0~20#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,041 INFO L290 TraceCheckUtils]: 19: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} via_ircc_init_#t~ret245#1 := ldv___pci_register_driver_66_#res#1;assume { :end_inline_ldv___pci_register_driver_66 } true;assume -2147483648 <= via_ircc_init_#t~ret245#1 && via_ircc_init_#t~ret245#1 <= 2147483647;via_ircc_init_~rc~0#1 := via_ircc_init_#t~ret245#1;havoc via_ircc_init_#t~ret245#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,041 INFO L290 TraceCheckUtils]: 20: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume via_ircc_init_~rc~0#1 < 0;havoc via_ircc_init_#t~nondet246#1;via_ircc_init_#res#1 := -19; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,042 INFO L290 TraceCheckUtils]: 21: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 := via_ircc_init_#res#1;assume { :end_inline_via_ircc_init } true;assume -2147483648 <= ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 && ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 <= 2147483647;ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1 := ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1;ldv_EMGentry_init_via_ircc_init_10_7_#res#1 := ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,042 INFO L290 TraceCheckUtils]: 22: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_entry_EMGentry_10_#t~ret831#1 := ldv_EMGentry_init_via_ircc_init_10_7_#res#1;assume { :end_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret831#1 && ldv_entry_EMGentry_10_#t~ret831#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret831#1;havoc ldv_entry_EMGentry_10_#t~ret831#1;assume { :begin_inline_ldv_post_init } true;ldv_post_init_#in~init_ret_val#1 := ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_post_init_#res#1;havoc ldv_post_init_#t~ret915#1, ldv_post_init_~init_ret_val#1, ldv_post_init_~tmp~71#1;ldv_post_init_~init_ret_val#1 := ldv_post_init_#in~init_ret_val#1;havoc ldv_post_init_~tmp~71#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,042 INFO L272 TraceCheckUtils]: 23: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_post_init_#t~ret915#1 := ldv_filter_positive_int(ldv_post_init_~init_ret_val#1); {14086#true} is VALID [2022-02-20 22:59:04,042 INFO L290 TraceCheckUtils]: 24: Hoare triple {14086#true} ~val := #in~val; {14086#true} is VALID [2022-02-20 22:59:04,042 INFO L272 TraceCheckUtils]: 25: Hoare triple {14086#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {14086#true} is VALID [2022-02-20 22:59:04,043 INFO L290 TraceCheckUtils]: 26: Hoare triple {14086#true} ~expression := #in~expression; {14086#true} is VALID [2022-02-20 22:59:04,043 INFO L290 TraceCheckUtils]: 27: Hoare triple {14086#true} assume !(0 == ~expression); {14086#true} is VALID [2022-02-20 22:59:04,043 INFO L290 TraceCheckUtils]: 28: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,043 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {14086#true} {14086#true} #4228#return; {14086#true} is VALID [2022-02-20 22:59:04,043 INFO L290 TraceCheckUtils]: 30: Hoare triple {14086#true} #res := ~val; {14086#true} is VALID [2022-02-20 22:59:04,043 INFO L290 TraceCheckUtils]: 31: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,044 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4806#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,044 INFO L290 TraceCheckUtils]: 33: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume -2147483648 <= ldv_post_init_#t~ret915#1 && ldv_post_init_#t~ret915#1 <= 2147483647;ldv_post_init_~tmp~71#1 := ldv_post_init_#t~ret915#1;havoc ldv_post_init_#t~ret915#1;ldv_post_init_#res#1 := ldv_post_init_~tmp~71#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,044 INFO L290 TraceCheckUtils]: 34: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} ldv_entry_EMGentry_10_#t~ret832#1 := ldv_post_init_#res#1;assume { :end_inline_ldv_post_init } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret832#1 && ldv_entry_EMGentry_10_#t~ret832#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret832#1;havoc ldv_entry_EMGentry_10_#t~ret832#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,044 INFO L272 TraceCheckUtils]: 35: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_entry_EMGentry_10_#t~ret833#1 := ldv_undef_int(); {14086#true} is VALID [2022-02-20 22:59:04,045 INFO L290 TraceCheckUtils]: 36: Hoare triple {14086#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {14086#true} is VALID [2022-02-20 22:59:04,045 INFO L290 TraceCheckUtils]: 37: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,045 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4808#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,045 INFO L290 TraceCheckUtils]: 39: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret833#1 && ldv_entry_EMGentry_10_#t~ret833#1 <= 2147483647;ldv_entry_EMGentry_10_~tmp~52#1 := ldv_entry_EMGentry_10_#t~ret833#1;havoc ldv_entry_EMGentry_10_#t~ret833#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,046 INFO L290 TraceCheckUtils]: 40: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} assume 0 != ldv_entry_EMGentry_10_~tmp~52#1; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,046 INFO L272 TraceCheckUtils]: 41: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_assume((if 0 != ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 then 1 else 0)); {14086#true} is VALID [2022-02-20 22:59:04,046 INFO L290 TraceCheckUtils]: 42: Hoare triple {14086#true} ~expression := #in~expression; {14086#true} is VALID [2022-02-20 22:59:04,046 INFO L290 TraceCheckUtils]: 43: Hoare triple {14086#true} assume !(0 == ~expression); {14086#true} is VALID [2022-02-20 22:59:04,046 INFO L290 TraceCheckUtils]: 44: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,047 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4810#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,047 INFO L272 TraceCheckUtils]: 46: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_check_final_state(); {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,047 INFO L272 TraceCheckUtils]: 47: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin_NOT_ARG_SIGN~0 then 1 else 0)); {14086#true} is VALID [2022-02-20 22:59:04,047 INFO L290 TraceCheckUtils]: 48: Hoare triple {14086#true} ~expr := #in~expr; {14086#true} is VALID [2022-02-20 22:59:04,048 INFO L290 TraceCheckUtils]: 49: Hoare triple {14086#true} assume !(0 == ~expr); {14086#true} is VALID [2022-02-20 22:59:04,048 INFO L290 TraceCheckUtils]: 50: Hoare triple {14086#true} assume true; {14086#true} is VALID [2022-02-20 22:59:04,048 INFO L284 TraceCheckUtils]: 51: Hoare quadruple {14086#true} {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} #4648#return; {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} is VALID [2022-02-20 22:59:04,049 INFO L272 TraceCheckUtils]: 52: Hoare triple {14088#(= ~ldv_spin__xmit_lock_of_netdev_queue~0 1)} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin__xmit_lock_of_netdev_queue~0 then 1 else 0)); {14116#(not (= |ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_#in~expr| 0))} is VALID [2022-02-20 22:59:04,049 INFO L290 TraceCheckUtils]: 53: Hoare triple {14116#(not (= |ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_#in~expr| 0))} ~expr := #in~expr; {14117#(not (= ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_~expr 0))} is VALID [2022-02-20 22:59:04,049 INFO L290 TraceCheckUtils]: 54: Hoare triple {14117#(not (= ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_~expr 0))} assume 0 == ~expr; {14087#false} is VALID [2022-02-20 22:59:04,049 INFO L290 TraceCheckUtils]: 55: Hoare triple {14087#false} assume !false; {14087#false} is VALID [2022-02-20 22:59:04,050 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2022-02-20 22:59:04,050 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:59:04,050 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144253848] [2022-02-20 22:59:04,051 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144253848] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:59:04,051 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:59:04,051 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-20 22:59:04,051 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569153000] [2022-02-20 22:59:04,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:59:04,052 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) Word has length 56 [2022-02-20 22:59:04,052 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:59:04,052 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2022-02-20 22:59:04,107 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 48 edges. 48 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:59:04,107 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-02-20 22:59:04,107 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:59:04,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-20 22:59:04,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-20 22:59:04,108 INFO L87 Difference]: Start difference. First operand 1894 states and 2727 transitions. Second operand has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2022-02-20 22:59:15,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:59:15,095 INFO L93 Difference]: Finished difference Result 1900 states and 2732 transitions. [2022-02-20 22:59:15,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-20 22:59:15,095 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) Word has length 56 [2022-02-20 22:59:15,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:59:15,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2022-02-20 22:59:15,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 2729 transitions. [2022-02-20 22:59:15,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2022-02-20 22:59:15,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 2729 transitions. [2022-02-20 22:59:15,377 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 2729 transitions. [2022-02-20 22:59:17,578 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 2729 edges. 2729 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:59:17,786 INFO L225 Difference]: With dead ends: 1900 [2022-02-20 22:59:17,786 INFO L226 Difference]: Without dead ends: 1898 [2022-02-20 22:59:17,787 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-02-20 22:59:17,788 INFO L933 BasicCegarLoop]: 2724 mSDtfsCounter, 2691 mSDsluCounter, 5427 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2703 SdHoareTripleChecker+Valid, 8151 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-02-20 22:59:17,788 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [2703 Valid, 8151 Invalid, 22 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-02-20 22:59:17,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1898 states. [2022-02-20 22:59:17,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1898 to 1898. [2022-02-20 22:59:17,849 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:59:17,854 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1898 states. Second operand has 1898 states, 1172 states have (on average 1.2534129692832765) internal successors, (1469), 1205 states have internal predecessors, (1469), 632 states have call successors, (632), 92 states have call predecessors, (632), 91 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:17,859 INFO L74 IsIncluded]: Start isIncluded. First operand 1898 states. Second operand has 1898 states, 1172 states have (on average 1.2534129692832765) internal successors, (1469), 1205 states have internal predecessors, (1469), 632 states have call successors, (632), 92 states have call predecessors, (632), 91 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:17,864 INFO L87 Difference]: Start difference. First operand 1898 states. Second operand has 1898 states, 1172 states have (on average 1.2534129692832765) internal successors, (1469), 1205 states have internal predecessors, (1469), 632 states have call successors, (632), 92 states have call predecessors, (632), 91 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:17,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:59:18,000 INFO L93 Difference]: Finished difference Result 1898 states and 2730 transitions. [2022-02-20 22:59:18,000 INFO L276 IsEmpty]: Start isEmpty. Operand 1898 states and 2730 transitions. [2022-02-20 22:59:18,012 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:59:18,012 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:59:18,028 INFO L74 IsIncluded]: Start isIncluded. First operand has 1898 states, 1172 states have (on average 1.2534129692832765) internal successors, (1469), 1205 states have internal predecessors, (1469), 632 states have call successors, (632), 92 states have call predecessors, (632), 91 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) Second operand 1898 states. [2022-02-20 22:59:18,035 INFO L87 Difference]: Start difference. First operand has 1898 states, 1172 states have (on average 1.2534129692832765) internal successors, (1469), 1205 states have internal predecessors, (1469), 632 states have call successors, (632), 92 states have call predecessors, (632), 91 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) Second operand 1898 states. [2022-02-20 22:59:18,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:59:18,168 INFO L93 Difference]: Finished difference Result 1898 states and 2730 transitions. [2022-02-20 22:59:18,169 INFO L276 IsEmpty]: Start isEmpty. Operand 1898 states and 2730 transitions. [2022-02-20 22:59:18,178 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:59:18,178 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:59:18,178 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:59:18,178 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:59:18,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1898 states, 1172 states have (on average 1.2534129692832765) internal successors, (1469), 1205 states have internal predecessors, (1469), 632 states have call successors, (632), 92 states have call predecessors, (632), 91 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:18,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1898 states to 1898 states and 2730 transitions. [2022-02-20 22:59:18,382 INFO L78 Accepts]: Start accepts. Automaton has 1898 states and 2730 transitions. Word has length 56 [2022-02-20 22:59:18,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:59:18,383 INFO L470 AbstractCegarLoop]: Abstraction has 1898 states and 2730 transitions. [2022-02-20 22:59:18,383 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 2 states have call predecessors, (7), 2 states have call successors, (7) [2022-02-20 22:59:18,383 INFO L276 IsEmpty]: Start isEmpty. Operand 1898 states and 2730 transitions. [2022-02-20 22:59:18,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2022-02-20 22:59:18,384 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:59:18,384 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:59:18,384 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-02-20 22:59:18,384 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exitErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_assert_linux_kernel_locking_spinlock__one_thread_double_unlockErr0ASSERT_VIOLATIONERROR_FUNCTION, ldv_assert_linux_kernel_locking_spinlock__one_thread_double_lockErr0ASSERT_VIOLATIONERROR_FUNCTION (and 1 more)] === [2022-02-20 22:59:18,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:59:18,385 INFO L85 PathProgramCache]: Analyzing trace with hash 1736938018, now seen corresponding path program 1 times [2022-02-20 22:59:18,385 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:59:18,385 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286766201] [2022-02-20 22:59:18,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:59:18,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:59:18,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:18,502 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:59:18,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:18,516 INFO L290 TraceCheckUtils]: 0: Hoare triple {23514#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {23514#true} is VALID [2022-02-20 22:59:18,516 INFO L290 TraceCheckUtils]: 1: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,517 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4692#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,517 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 12 [2022-02-20 22:59:18,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:18,522 INFO L290 TraceCheckUtils]: 0: Hoare triple {23514#true} ~expression := #in~expression; {23514#true} is VALID [2022-02-20 22:59:18,522 INFO L290 TraceCheckUtils]: 1: Hoare triple {23514#true} assume !(0 == ~expression); {23514#true} is VALID [2022-02-20 22:59:18,522 INFO L290 TraceCheckUtils]: 2: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,523 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4804#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,523 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2022-02-20 22:59:18,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:18,531 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:59:18,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:18,536 INFO L290 TraceCheckUtils]: 0: Hoare triple {23514#true} ~expression := #in~expression; {23514#true} is VALID [2022-02-20 22:59:18,537 INFO L290 TraceCheckUtils]: 1: Hoare triple {23514#true} assume !(0 == ~expression); {23514#true} is VALID [2022-02-20 22:59:18,537 INFO L290 TraceCheckUtils]: 2: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,537 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {23514#true} {23514#true} #4228#return; {23514#true} is VALID [2022-02-20 22:59:18,537 INFO L290 TraceCheckUtils]: 0: Hoare triple {23514#true} ~val := #in~val; {23514#true} is VALID [2022-02-20 22:59:18,537 INFO L272 TraceCheckUtils]: 1: Hoare triple {23514#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {23514#true} is VALID [2022-02-20 22:59:18,537 INFO L290 TraceCheckUtils]: 2: Hoare triple {23514#true} ~expression := #in~expression; {23514#true} is VALID [2022-02-20 22:59:18,537 INFO L290 TraceCheckUtils]: 3: Hoare triple {23514#true} assume !(0 == ~expression); {23514#true} is VALID [2022-02-20 22:59:18,538 INFO L290 TraceCheckUtils]: 4: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,538 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {23514#true} {23514#true} #4228#return; {23514#true} is VALID [2022-02-20 22:59:18,538 INFO L290 TraceCheckUtils]: 6: Hoare triple {23514#true} #res := ~val; {23514#true} is VALID [2022-02-20 22:59:18,538 INFO L290 TraceCheckUtils]: 7: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,538 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4806#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,539 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2022-02-20 22:59:18,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:18,547 INFO L290 TraceCheckUtils]: 0: Hoare triple {23514#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {23514#true} is VALID [2022-02-20 22:59:18,547 INFO L290 TraceCheckUtils]: 1: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,548 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4808#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,548 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 41 [2022-02-20 22:59:18,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:18,560 INFO L290 TraceCheckUtils]: 0: Hoare triple {23514#true} ~expression := #in~expression; {23514#true} is VALID [2022-02-20 22:59:18,560 INFO L290 TraceCheckUtils]: 1: Hoare triple {23514#true} assume !(0 == ~expression); {23514#true} is VALID [2022-02-20 22:59:18,560 INFO L290 TraceCheckUtils]: 2: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,561 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4810#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,561 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 47 [2022-02-20 22:59:18,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:18,569 INFO L290 TraceCheckUtils]: 0: Hoare triple {23514#true} ~expr := #in~expr; {23514#true} is VALID [2022-02-20 22:59:18,570 INFO L290 TraceCheckUtils]: 1: Hoare triple {23514#true} assume !(0 == ~expr); {23514#true} is VALID [2022-02-20 22:59:18,570 INFO L290 TraceCheckUtils]: 2: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,570 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4648#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,570 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 52 [2022-02-20 22:59:18,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:18,575 INFO L290 TraceCheckUtils]: 0: Hoare triple {23514#true} ~expr := #in~expr; {23514#true} is VALID [2022-02-20 22:59:18,575 INFO L290 TraceCheckUtils]: 1: Hoare triple {23514#true} assume !(0 == ~expr); {23514#true} is VALID [2022-02-20 22:59:18,575 INFO L290 TraceCheckUtils]: 2: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,575 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4650#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,576 INFO L290 TraceCheckUtils]: 0: Hoare triple {23514#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(199, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(9, 4);call #Ultimate.allocInit(9, 5);call #Ultimate.allocInit(7, 6);call write~init~int(15, 6, 0, 1);call write~init~int(37, 6, 1, 1);call write~init~int(115, 6, 2, 1);call write~init~int(40, 6, 3, 1);call write~init~int(41, 6, 4, 1);call write~init~int(10, 6, 5, 1);call write~init~int(0, 6, 6, 1);call #Ultimate.allocInit(14, 7);call #Ultimate.allocInit(9, 8);call #Ultimate.allocInit(45, 9);call #Ultimate.allocInit(14, 10);call #Ultimate.allocInit(25, 11);call #Ultimate.allocInit(13, 12);call #Ultimate.allocInit(22, 13);call #Ultimate.allocInit(13, 14);call #Ultimate.allocInit(23, 15);call #Ultimate.allocInit(13, 16);call #Ultimate.allocInit(23, 17);call #Ultimate.allocInit(13, 18);call #Ultimate.allocInit(22, 19);call #Ultimate.allocInit(13, 20);call #Ultimate.allocInit(7, 21);call write~init~int(15, 21, 0, 1);call write~init~int(37, 21, 1, 1);call write~init~int(115, 21, 2, 1);call write~init~int(40, 21, 3, 1);call write~init~int(41, 21, 4, 1);call write~init~int(10, 21, 5, 1);call write~init~int(0, 21, 6, 1);call #Ultimate.allocInit(17, 22);call #Ultimate.allocInit(7, 23);call write~init~int(15, 23, 0, 1);call write~init~int(37, 23, 1, 1);call write~init~int(115, 23, 2, 1);call write~init~int(40, 23, 3, 1);call write~init~int(41, 23, 4, 1);call write~init~int(10, 23, 5, 1);call write~init~int(0, 23, 6, 1);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(22, 25);call #Ultimate.allocInit(35, 26);call #Ultimate.allocInit(14, 27);call #Ultimate.allocInit(40, 28);call #Ultimate.allocInit(7, 29);call write~init~int(15, 29, 0, 1);call write~init~int(37, 29, 1, 1);call write~init~int(115, 29, 2, 1);call write~init~int(40, 29, 3, 1);call write~init~int(41, 29, 4, 1);call write~init~int(10, 29, 5, 1);call write~init~int(0, 29, 6, 1);call #Ultimate.allocInit(15, 30);call #Ultimate.allocInit(30, 31);call #Ultimate.allocInit(15, 32);call #Ultimate.allocInit(7, 33);call write~init~int(15, 33, 0, 1);call write~init~int(37, 33, 1, 1);call write~init~int(115, 33, 2, 1);call write~init~int(40, 33, 3, 1);call write~init~int(41, 33, 4, 1);call write~init~int(10, 33, 5, 1);call write~init~int(0, 33, 6, 1);call #Ultimate.allocInit(12, 34);call #Ultimate.allocInit(85, 35);call #Ultimate.allocInit(47, 36);call #Ultimate.allocInit(29, 37);call #Ultimate.allocInit(58, 38);call #Ultimate.allocInit(29, 39);call #Ultimate.allocInit(50, 40);call #Ultimate.allocInit(29, 41);call #Ultimate.allocInit(40, 42);call #Ultimate.allocInit(29, 43);call #Ultimate.allocInit(30, 44);call #Ultimate.allocInit(22, 45);call #Ultimate.allocInit(31, 46);call #Ultimate.allocInit(28, 47);call #Ultimate.allocInit(23, 48);call #Ultimate.allocInit(13, 49);call #Ultimate.allocInit(45, 50);call #Ultimate.allocInit(18, 51);call #Ultimate.allocInit(7, 52);call write~init~int(15, 52, 0, 1);call write~init~int(37, 52, 1, 1);call write~init~int(115, 52, 2, 1);call write~init~int(40, 52, 3, 1);call write~init~int(41, 52, 4, 1);call write~init~int(10, 52, 5, 1);call write~init~int(0, 52, 6, 1);call #Ultimate.allocInit(27, 53);call #Ultimate.allocInit(56, 54);call #Ultimate.allocInit(27, 55);call #Ultimate.allocInit(7, 56);call write~init~int(15, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(40, 56, 3, 1);call write~init~int(41, 56, 4, 1);call write~init~int(10, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(21, 57);call #Ultimate.allocInit(50, 58);call #Ultimate.allocInit(30, 59);call #Ultimate.allocInit(41, 60);call #Ultimate.allocInit(30, 61);call #Ultimate.allocInit(26, 62);call #Ultimate.allocInit(30, 63);call #Ultimate.allocInit(15, 64);call #Ultimate.allocInit(14, 65);call #Ultimate.allocInit(23, 66);call #Ultimate.allocInit(15, 67);call #Ultimate.allocInit(48, 68);call #Ultimate.allocInit(15, 69);call #Ultimate.allocInit(43, 70);call #Ultimate.allocInit(19, 71);call #Ultimate.allocInit(6, 72);call write~init~int(84, 72, 0, 1);call write~init~int(105, 72, 1, 1);call write~init~int(109, 72, 2, 1);call write~init~int(101, 72, 3, 1);call write~init~int(114, 72, 4, 1);call write~init~int(0, 72, 5, 1);call #Ultimate.allocInit(1, 73);call write~init~int(0, 73, 0, 1);call #Ultimate.allocInit(3, 74);call write~init~int(84, 74, 0, 1);call write~init~int(120, 74, 1, 1);call write~init~int(0, 74, 2, 1);call #Ultimate.allocInit(1, 75);call write~init~int(0, 75, 0, 1);call #Ultimate.allocInit(3, 76);call write~init~int(82, 76, 0, 1);call write~init~int(120, 76, 1, 1);call write~init~int(0, 76, 2, 1);call #Ultimate.allocInit(1, 77);call write~init~int(0, 77, 0, 1);call #Ultimate.allocInit(38, 78);call #Ultimate.allocInit(19, 79);call #Ultimate.allocInit(13, 80);call #Ultimate.allocInit(1, 81);call write~init~int(0, 81, 0, 1);call #Ultimate.allocInit(4, 82);call write~init~int(69, 82, 0, 1);call write~init~int(79, 82, 1, 1);call write~init~int(77, 82, 2, 1);call write~init~int(0, 82, 3, 1);call #Ultimate.allocInit(1, 83);call write~init~int(0, 83, 0, 1);call #Ultimate.allocInit(11, 84);call #Ultimate.allocInit(1, 85);call write~init~int(0, 85, 0, 1);call #Ultimate.allocInit(10, 86);call #Ultimate.allocInit(1, 87);call write~init~int(0, 87, 0, 1);call #Ultimate.allocInit(47, 88);call #Ultimate.allocInit(19, 89);call #Ultimate.allocInit(9, 90);call #Ultimate.allocInit(1, 91);call write~init~int(0, 91, 0, 1);call #Ultimate.allocInit(8, 92);call #Ultimate.allocInit(1, 93);call write~init~int(0, 93, 0, 1);call #Ultimate.allocInit(12, 94);call #Ultimate.allocInit(1, 95);call write~init~int(0, 95, 0, 1);call #Ultimate.allocInit(4, 96);call write~init~int(69, 96, 0, 1);call write~init~int(79, 96, 1, 1);call write~init~int(70, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(1, 97);call write~init~int(0, 97, 0, 1);call #Ultimate.allocInit(7, 98);call write~init~int(82, 98, 0, 1);call write~init~int(120, 98, 1, 1);call write~init~int(68, 98, 2, 1);call write~init~int(97, 98, 3, 1);call write~init~int(116, 98, 4, 1);call write~init~int(97, 98, 5, 1);call write~init~int(0, 98, 6, 1);call #Ultimate.allocInit(1, 99);call write~init~int(0, 99, 0, 1);call #Ultimate.allocInit(9, 100);call #Ultimate.allocInit(1, 101);call write~init~int(0, 101, 0, 1);call #Ultimate.allocInit(8, 102);call #Ultimate.allocInit(1, 103);call write~init~int(0, 103, 0, 1);call #Ultimate.allocInit(17, 104);call #Ultimate.allocInit(19, 105);call #Ultimate.allocInit(79, 106);call #Ultimate.allocInit(19, 107);call #Ultimate.allocInit(7, 108);call write~init~int(15, 108, 0, 1);call write~init~int(37, 108, 1, 1);call write~init~int(115, 108, 2, 1);call write~init~int(40, 108, 3, 1);call write~init~int(41, 108, 4, 1);call write~init~int(10, 108, 5, 1);call write~init~int(0, 108, 6, 1);call #Ultimate.allocInit(8, 109);call #Ultimate.allocInit(31, 110);call #Ultimate.allocInit(28, 111);call #Ultimate.allocInit(22, 112);call #Ultimate.allocInit(13, 113);call #Ultimate.allocInit(22, 114);call #Ultimate.allocInit(22, 115);call #Ultimate.allocInit(7, 116);call write~init~int(15, 116, 0, 1);call write~init~int(37, 116, 1, 1);call write~init~int(115, 116, 2, 1);call write~init~int(40, 116, 3, 1);call write~init~int(41, 116, 4, 1);call write~init~int(10, 116, 5, 1);call write~init~int(0, 116, 6, 1);call #Ultimate.allocInit(18, 117);call #Ultimate.allocInit(31, 118);call #Ultimate.allocInit(28, 119);call #Ultimate.allocInit(18, 120);call #Ultimate.allocInit(12, 121);call #Ultimate.allocInit(31, 122);call #Ultimate.allocInit(28, 123);call #Ultimate.allocInit(18, 124);call #Ultimate.allocInit(13, 125);call #Ultimate.allocInit(32, 126);call #Ultimate.allocInit(32, 127);call #Ultimate.allocInit(33, 128);call #Ultimate.allocInit(11, 129);call #Ultimate.allocInit(7, 130);call write~init~int(15, 130, 0, 1);call write~init~int(37, 130, 1, 1);call write~init~int(115, 130, 2, 1);call write~init~int(40, 130, 3, 1);call write~init~int(41, 130, 4, 1);call write~init~int(10, 130, 5, 1);call write~init~int(0, 130, 6, 1);call #Ultimate.allocInit(19, 131);call #Ultimate.allocInit(31, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(19, 134);call #Ultimate.allocInit(12, 135);call #Ultimate.allocInit(31, 136);call #Ultimate.allocInit(28, 137);call #Ultimate.allocInit(19, 138);call #Ultimate.allocInit(13, 139);call #Ultimate.allocInit(31, 140);call #Ultimate.allocInit(28, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(12, 143);call #Ultimate.allocInit(31, 144);call #Ultimate.allocInit(28, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(13, 147);call #Ultimate.allocInit(23, 148);call #Ultimate.allocInit(19, 149);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(2, 151);call write~init~int(48, 151, 0, 1);call write~init~int(0, 151, 1, 1);call #Ultimate.allocInit(73, 152);~driver_name~0.base, ~driver_name~0.offset := 4, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 153, 0;call #Ultimate.allocInit(192, 153);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#via_driver~0.base, ~#via_driver~0.offset := 154, 0;call #Ultimate.allocInit(301, 154);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(5, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 145 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 153 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 161 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 169 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 177 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 185 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 193 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 201 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 209 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 217 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 237 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 245 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 253 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 261 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 269 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 285 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 293 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 155, 0;call #Ultimate.allocInit(472, 155);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 156, 0;call #Ultimate.allocInit(472, 156);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_thread_0~0.identifier := 0;~ldv_thread_0~0.function.base, ~ldv_thread_0~0.function.offset := 0, 0;~ldv_thread_1~0.identifier := 0;~ldv_thread_1~0.function.base, ~ldv_thread_1~0.function.offset := 0, 0;~ldv_thread_10~0.identifier := 0;~ldv_thread_10~0.function.base, ~ldv_thread_10~0.function.offset := 0, 0;~ldv_thread_2~0.identifier := 0;~ldv_thread_2~0.function.base, ~ldv_thread_2~0.function.offset := 0, 0;~ldv_spin_NOT_ARG_SIGN~0 := 1;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_dma_spin_lock~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_via_ircc_cb~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,576 INFO L290 TraceCheckUtils]: 1: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_ldv_initialize } true; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,577 INFO L290 TraceCheckUtils]: 2: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_entry_EMGentry_10 } true;ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset := 0, 0;havoc ldv_entry_EMGentry_10_#t~ret831#1, ldv_entry_EMGentry_10_#t~ret832#1, ldv_entry_EMGentry_10_#t~ret833#1, ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1, ldv_entry_EMGentry_10_~tmp~52#1;ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset := ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_entry_EMGentry_10_~tmp~52#1;assume { :begin_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset := ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_#res#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset, ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset := ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;assume { :begin_inline_via_ircc_init } true;havoc via_ircc_init_#res#1;havoc via_ircc_init_#t~nondet244#1, via_ircc_init_#t~ret245#1, via_ircc_init_#t~nondet246#1, via_ircc_init_~rc~0#1;havoc via_ircc_init_~rc~0#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,577 INFO L290 TraceCheckUtils]: 3: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume !(~irda_debug~0 % 4294967296 > 2); {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,577 INFO L290 TraceCheckUtils]: 4: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume { :begin_inline_ldv___pci_register_driver_66 } true;ldv___pci_register_driver_66_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.offset := ~#via_driver~0.base, ~#via_driver~0.offset, ~#__this_module~0.base, ~#__this_module~0.offset, 8, 0;havoc ldv___pci_register_driver_66_#res#1;havoc ldv___pci_register_driver_66_#t~ret900#1, ldv___pci_register_driver_66_#t~ret901#1, ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset, ldv___pci_register_driver_66_~ldv_func_res~0#1, ldv___pci_register_driver_66_~tmp~65#1, ldv___pci_register_driver_66_~tmp___0~20#1;ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg1#1.offset;ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.offset;ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_66_~ldv_func_res~0#1;havoc ldv___pci_register_driver_66_~tmp~65#1;havoc ldv___pci_register_driver_66_~tmp___0~20#1;assume { :begin_inline___pci_register_driver } true;__pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset, __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset, __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset := ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset;havoc __pci_register_driver_#res#1;havoc __pci_register_driver_#t~nondet1022#1, __pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset, __pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset, __pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset;__pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset := __pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset;__pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset := __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset;__pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset := __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset;assume -2147483648 <= __pci_register_driver_#t~nondet1022#1 && __pci_register_driver_#t~nondet1022#1 <= 2147483647;__pci_register_driver_#res#1 := __pci_register_driver_#t~nondet1022#1;havoc __pci_register_driver_#t~nondet1022#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,578 INFO L290 TraceCheckUtils]: 5: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} ldv___pci_register_driver_66_#t~ret900#1 := __pci_register_driver_#res#1;assume { :end_inline___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_66_#t~ret900#1 && ldv___pci_register_driver_66_#t~ret900#1 <= 2147483647;ldv___pci_register_driver_66_~tmp~65#1 := ldv___pci_register_driver_66_#t~ret900#1;havoc ldv___pci_register_driver_66_#t~ret900#1;ldv___pci_register_driver_66_~ldv_func_res~0#1 := ldv___pci_register_driver_66_~tmp~65#1;assume { :begin_inline_ldv___pci_register_driver } true;ldv___pci_register_driver_#in~arg0#1, ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset, ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset, ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset := ldv___pci_register_driver_66_~ldv_func_res~0#1, ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_#res#1;havoc ldv___pci_register_driver_#t~ret825#1, ldv___pci_register_driver_~arg0#1, ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset, ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset, ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset, ldv___pci_register_driver_~tmp~48#1;ldv___pci_register_driver_~arg0#1 := ldv___pci_register_driver_#in~arg0#1;ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset := ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset;ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset := ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset;ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset := ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset;havoc ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset;havoc ldv___pci_register_driver_~tmp~48#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,578 INFO L272 TraceCheckUtils]: 6: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} call ldv___pci_register_driver_#t~ret825#1 := ldv_undef_int(); {23514#true} is VALID [2022-02-20 22:59:18,578 INFO L290 TraceCheckUtils]: 7: Hoare triple {23514#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {23514#true} is VALID [2022-02-20 22:59:18,578 INFO L290 TraceCheckUtils]: 8: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,579 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4692#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,579 INFO L290 TraceCheckUtils]: 10: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume -2147483648 <= ldv___pci_register_driver_#t~ret825#1 && ldv___pci_register_driver_#t~ret825#1 <= 2147483647;ldv___pci_register_driver_~tmp~48#1 := ldv___pci_register_driver_#t~ret825#1;havoc ldv___pci_register_driver_#t~ret825#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,579 INFO L290 TraceCheckUtils]: 11: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume !(0 != ldv___pci_register_driver_~tmp~48#1); {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,579 INFO L272 TraceCheckUtils]: 12: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} call ldv_assume((if 0 != ldv___pci_register_driver_~arg0#1 then 1 else 0)); {23514#true} is VALID [2022-02-20 22:59:18,579 INFO L290 TraceCheckUtils]: 13: Hoare triple {23514#true} ~expression := #in~expression; {23514#true} is VALID [2022-02-20 22:59:18,580 INFO L290 TraceCheckUtils]: 14: Hoare triple {23514#true} assume !(0 == ~expression); {23514#true} is VALID [2022-02-20 22:59:18,580 INFO L290 TraceCheckUtils]: 15: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,580 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4804#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,580 INFO L290 TraceCheckUtils]: 17: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} ldv___pci_register_driver_#res#1 := ldv___pci_register_driver_~arg0#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,581 INFO L290 TraceCheckUtils]: 18: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} ldv___pci_register_driver_66_#t~ret901#1 := ldv___pci_register_driver_#res#1;assume { :end_inline_ldv___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_66_#t~ret901#1 && ldv___pci_register_driver_66_#t~ret901#1 <= 2147483647;ldv___pci_register_driver_66_~tmp___0~20#1 := ldv___pci_register_driver_66_#t~ret901#1;havoc ldv___pci_register_driver_66_#t~ret901#1;ldv___pci_register_driver_66_#res#1 := ldv___pci_register_driver_66_~tmp___0~20#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,581 INFO L290 TraceCheckUtils]: 19: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} via_ircc_init_#t~ret245#1 := ldv___pci_register_driver_66_#res#1;assume { :end_inline_ldv___pci_register_driver_66 } true;assume -2147483648 <= via_ircc_init_#t~ret245#1 && via_ircc_init_#t~ret245#1 <= 2147483647;via_ircc_init_~rc~0#1 := via_ircc_init_#t~ret245#1;havoc via_ircc_init_#t~ret245#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,581 INFO L290 TraceCheckUtils]: 20: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume via_ircc_init_~rc~0#1 < 0;havoc via_ircc_init_#t~nondet246#1;via_ircc_init_#res#1 := -19; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,582 INFO L290 TraceCheckUtils]: 21: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 := via_ircc_init_#res#1;assume { :end_inline_via_ircc_init } true;assume -2147483648 <= ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 && ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 <= 2147483647;ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1 := ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1;ldv_EMGentry_init_via_ircc_init_10_7_#res#1 := ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,582 INFO L290 TraceCheckUtils]: 22: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} ldv_entry_EMGentry_10_#t~ret831#1 := ldv_EMGentry_init_via_ircc_init_10_7_#res#1;assume { :end_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret831#1 && ldv_entry_EMGentry_10_#t~ret831#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret831#1;havoc ldv_entry_EMGentry_10_#t~ret831#1;assume { :begin_inline_ldv_post_init } true;ldv_post_init_#in~init_ret_val#1 := ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_post_init_#res#1;havoc ldv_post_init_#t~ret915#1, ldv_post_init_~init_ret_val#1, ldv_post_init_~tmp~71#1;ldv_post_init_~init_ret_val#1 := ldv_post_init_#in~init_ret_val#1;havoc ldv_post_init_~tmp~71#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,582 INFO L272 TraceCheckUtils]: 23: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} call ldv_post_init_#t~ret915#1 := ldv_filter_positive_int(ldv_post_init_~init_ret_val#1); {23514#true} is VALID [2022-02-20 22:59:18,582 INFO L290 TraceCheckUtils]: 24: Hoare triple {23514#true} ~val := #in~val; {23514#true} is VALID [2022-02-20 22:59:18,583 INFO L272 TraceCheckUtils]: 25: Hoare triple {23514#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {23514#true} is VALID [2022-02-20 22:59:18,583 INFO L290 TraceCheckUtils]: 26: Hoare triple {23514#true} ~expression := #in~expression; {23514#true} is VALID [2022-02-20 22:59:18,583 INFO L290 TraceCheckUtils]: 27: Hoare triple {23514#true} assume !(0 == ~expression); {23514#true} is VALID [2022-02-20 22:59:18,583 INFO L290 TraceCheckUtils]: 28: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,583 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {23514#true} {23514#true} #4228#return; {23514#true} is VALID [2022-02-20 22:59:18,583 INFO L290 TraceCheckUtils]: 30: Hoare triple {23514#true} #res := ~val; {23514#true} is VALID [2022-02-20 22:59:18,583 INFO L290 TraceCheckUtils]: 31: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,584 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4806#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,584 INFO L290 TraceCheckUtils]: 33: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume -2147483648 <= ldv_post_init_#t~ret915#1 && ldv_post_init_#t~ret915#1 <= 2147483647;ldv_post_init_~tmp~71#1 := ldv_post_init_#t~ret915#1;havoc ldv_post_init_#t~ret915#1;ldv_post_init_#res#1 := ldv_post_init_~tmp~71#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,584 INFO L290 TraceCheckUtils]: 34: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} ldv_entry_EMGentry_10_#t~ret832#1 := ldv_post_init_#res#1;assume { :end_inline_ldv_post_init } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret832#1 && ldv_entry_EMGentry_10_#t~ret832#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret832#1;havoc ldv_entry_EMGentry_10_#t~ret832#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,585 INFO L272 TraceCheckUtils]: 35: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} call ldv_entry_EMGentry_10_#t~ret833#1 := ldv_undef_int(); {23514#true} is VALID [2022-02-20 22:59:18,591 INFO L290 TraceCheckUtils]: 36: Hoare triple {23514#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {23514#true} is VALID [2022-02-20 22:59:18,591 INFO L290 TraceCheckUtils]: 37: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,592 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4808#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,593 INFO L290 TraceCheckUtils]: 39: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret833#1 && ldv_entry_EMGentry_10_#t~ret833#1 <= 2147483647;ldv_entry_EMGentry_10_~tmp~52#1 := ldv_entry_EMGentry_10_#t~ret833#1;havoc ldv_entry_EMGentry_10_#t~ret833#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,596 INFO L290 TraceCheckUtils]: 40: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} assume 0 != ldv_entry_EMGentry_10_~tmp~52#1; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,597 INFO L272 TraceCheckUtils]: 41: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} call ldv_assume((if 0 != ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 then 1 else 0)); {23514#true} is VALID [2022-02-20 22:59:18,597 INFO L290 TraceCheckUtils]: 42: Hoare triple {23514#true} ~expression := #in~expression; {23514#true} is VALID [2022-02-20 22:59:18,597 INFO L290 TraceCheckUtils]: 43: Hoare triple {23514#true} assume !(0 == ~expression); {23514#true} is VALID [2022-02-20 22:59:18,598 INFO L290 TraceCheckUtils]: 44: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,598 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4810#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,599 INFO L272 TraceCheckUtils]: 46: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} call ldv_check_final_state(); {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,599 INFO L272 TraceCheckUtils]: 47: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin_NOT_ARG_SIGN~0 then 1 else 0)); {23514#true} is VALID [2022-02-20 22:59:18,599 INFO L290 TraceCheckUtils]: 48: Hoare triple {23514#true} ~expr := #in~expr; {23514#true} is VALID [2022-02-20 22:59:18,599 INFO L290 TraceCheckUtils]: 49: Hoare triple {23514#true} assume !(0 == ~expr); {23514#true} is VALID [2022-02-20 22:59:18,600 INFO L290 TraceCheckUtils]: 50: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,600 INFO L284 TraceCheckUtils]: 51: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4648#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,602 INFO L272 TraceCheckUtils]: 52: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin__xmit_lock_of_netdev_queue~0 then 1 else 0)); {23514#true} is VALID [2022-02-20 22:59:18,603 INFO L290 TraceCheckUtils]: 53: Hoare triple {23514#true} ~expr := #in~expr; {23514#true} is VALID [2022-02-20 22:59:18,603 INFO L290 TraceCheckUtils]: 54: Hoare triple {23514#true} assume !(0 == ~expr); {23514#true} is VALID [2022-02-20 22:59:18,604 INFO L290 TraceCheckUtils]: 55: Hoare triple {23514#true} assume true; {23514#true} is VALID [2022-02-20 22:59:18,606 INFO L284 TraceCheckUtils]: 56: Hoare quadruple {23514#true} {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} #4650#return; {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} is VALID [2022-02-20 22:59:18,606 INFO L272 TraceCheckUtils]: 57: Hoare triple {23516#(= ~ldv_spin_addr_list_lock_of_net_device~0 1)} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin_addr_list_lock_of_net_device~0 then 1 else 0)); {23548#(not (= |ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_#in~expr| 0))} is VALID [2022-02-20 22:59:18,606 INFO L290 TraceCheckUtils]: 58: Hoare triple {23548#(not (= |ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_#in~expr| 0))} ~expr := #in~expr; {23549#(not (= ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_~expr 0))} is VALID [2022-02-20 22:59:18,607 INFO L290 TraceCheckUtils]: 59: Hoare triple {23549#(not (= ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit_~expr 0))} assume 0 == ~expr; {23515#false} is VALID [2022-02-20 22:59:18,607 INFO L290 TraceCheckUtils]: 60: Hoare triple {23515#false} assume !false; {23515#false} is VALID [2022-02-20 22:59:18,607 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2022-02-20 22:59:18,607 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:59:18,607 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286766201] [2022-02-20 22:59:18,608 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286766201] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:59:18,608 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:59:18,608 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-20 22:59:18,608 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644879727] [2022-02-20 22:59:18,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:59:18,609 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 61 [2022-02-20 22:59:18,609 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:59:18,609 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2022-02-20 22:59:18,658 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:59:18,658 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-02-20 22:59:18,658 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:59:18,659 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-20 22:59:18,659 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-20 22:59:18,659 INFO L87 Difference]: Start difference. First operand 1898 states and 2730 transitions. Second operand has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2022-02-20 22:59:30,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:59:30,289 INFO L93 Difference]: Finished difference Result 1904 states and 2735 transitions. [2022-02-20 22:59:30,289 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-20 22:59:30,289 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 61 [2022-02-20 22:59:30,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:59:30,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2022-02-20 22:59:30,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 2729 transitions. [2022-02-20 22:59:30,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2022-02-20 22:59:30,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 2729 transitions. [2022-02-20 22:59:30,560 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 2729 transitions. [2022-02-20 22:59:32,744 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 2729 edges. 2729 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:59:32,915 INFO L225 Difference]: With dead ends: 1904 [2022-02-20 22:59:32,916 INFO L226 Difference]: Without dead ends: 1902 [2022-02-20 22:59:32,916 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-02-20 22:59:32,917 INFO L933 BasicCegarLoop]: 2724 mSDtfsCounter, 2691 mSDsluCounter, 5427 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2702 SdHoareTripleChecker+Valid, 8151 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-02-20 22:59:32,921 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [2702 Valid, 8151 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-02-20 22:59:32,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1902 states. [2022-02-20 22:59:32,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1902 to 1902. [2022-02-20 22:59:32,971 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:59:32,975 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1902 states. Second operand has 1902 states, 1175 states have (on average 1.2527659574468084) internal successors, (1472), 1208 states have internal predecessors, (1472), 632 states have call successors, (632), 93 states have call predecessors, (632), 92 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:32,978 INFO L74 IsIncluded]: Start isIncluded. First operand 1902 states. Second operand has 1902 states, 1175 states have (on average 1.2527659574468084) internal successors, (1472), 1208 states have internal predecessors, (1472), 632 states have call successors, (632), 93 states have call predecessors, (632), 92 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:32,981 INFO L87 Difference]: Start difference. First operand 1902 states. Second operand has 1902 states, 1175 states have (on average 1.2527659574468084) internal successors, (1472), 1208 states have internal predecessors, (1472), 632 states have call successors, (632), 93 states have call predecessors, (632), 92 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:33,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:59:33,108 INFO L93 Difference]: Finished difference Result 1902 states and 2733 transitions. [2022-02-20 22:59:33,108 INFO L276 IsEmpty]: Start isEmpty. Operand 1902 states and 2733 transitions. [2022-02-20 22:59:33,136 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:59:33,136 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:59:33,140 INFO L74 IsIncluded]: Start isIncluded. First operand has 1902 states, 1175 states have (on average 1.2527659574468084) internal successors, (1472), 1208 states have internal predecessors, (1472), 632 states have call successors, (632), 93 states have call predecessors, (632), 92 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) Second operand 1902 states. [2022-02-20 22:59:33,143 INFO L87 Difference]: Start difference. First operand has 1902 states, 1175 states have (on average 1.2527659574468084) internal successors, (1472), 1208 states have internal predecessors, (1472), 632 states have call successors, (632), 93 states have call predecessors, (632), 92 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) Second operand 1902 states. [2022-02-20 22:59:33,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:59:33,268 INFO L93 Difference]: Finished difference Result 1902 states and 2733 transitions. [2022-02-20 22:59:33,268 INFO L276 IsEmpty]: Start isEmpty. Operand 1902 states and 2733 transitions. [2022-02-20 22:59:33,276 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:59:33,277 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:59:33,277 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:59:33,277 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:59:33,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1902 states, 1175 states have (on average 1.2527659574468084) internal successors, (1472), 1208 states have internal predecessors, (1472), 632 states have call successors, (632), 93 states have call predecessors, (632), 92 states have return successors, (629), 617 states have call predecessors, (629), 629 states have call successors, (629) [2022-02-20 22:59:33,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1902 states to 1902 states and 2733 transitions. [2022-02-20 22:59:33,479 INFO L78 Accepts]: Start accepts. Automaton has 1902 states and 2733 transitions. Word has length 61 [2022-02-20 22:59:33,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:59:33,479 INFO L470 AbstractCegarLoop]: Abstraction has 1902 states and 2733 transitions. [2022-02-20 22:59:33,480 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 6.4) internal successors, (32), 4 states have internal predecessors, (32), 2 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2022-02-20 22:59:33,480 INFO L276 IsEmpty]: Start isEmpty. Operand 1902 states and 2733 transitions. [2022-02-20 22:59:33,480 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2022-02-20 22:59:33,481 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:59:33,481 INFO L514 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:59:33,481 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-02-20 22:59:33,481 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exitErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_assert_linux_kernel_locking_spinlock__one_thread_double_unlockErr0ASSERT_VIOLATIONERROR_FUNCTION, ldv_assert_linux_kernel_locking_spinlock__one_thread_double_lockErr0ASSERT_VIOLATIONERROR_FUNCTION (and 1 more)] === [2022-02-20 22:59:33,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:59:33,482 INFO L85 PathProgramCache]: Analyzing trace with hash 2129791922, now seen corresponding path program 1 times [2022-02-20 22:59:33,482 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:59:33,482 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577030249] [2022-02-20 22:59:33,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:59:33,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:59:33,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,590 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:59:33,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,597 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {32964#true} is VALID [2022-02-20 22:59:33,597 INFO L290 TraceCheckUtils]: 1: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,598 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4692#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,598 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 12 [2022-02-20 22:59:33,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,606 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} ~expression := #in~expression; {32964#true} is VALID [2022-02-20 22:59:33,606 INFO L290 TraceCheckUtils]: 1: Hoare triple {32964#true} assume !(0 == ~expression); {32964#true} is VALID [2022-02-20 22:59:33,607 INFO L290 TraceCheckUtils]: 2: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,607 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4804#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,607 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2022-02-20 22:59:33,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,615 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:59:33,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,622 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} ~expression := #in~expression; {32964#true} is VALID [2022-02-20 22:59:33,622 INFO L290 TraceCheckUtils]: 1: Hoare triple {32964#true} assume !(0 == ~expression); {32964#true} is VALID [2022-02-20 22:59:33,623 INFO L290 TraceCheckUtils]: 2: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,623 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {32964#true} {32964#true} #4228#return; {32964#true} is VALID [2022-02-20 22:59:33,623 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} ~val := #in~val; {32964#true} is VALID [2022-02-20 22:59:33,624 INFO L272 TraceCheckUtils]: 1: Hoare triple {32964#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {32964#true} is VALID [2022-02-20 22:59:33,624 INFO L290 TraceCheckUtils]: 2: Hoare triple {32964#true} ~expression := #in~expression; {32964#true} is VALID [2022-02-20 22:59:33,624 INFO L290 TraceCheckUtils]: 3: Hoare triple {32964#true} assume !(0 == ~expression); {32964#true} is VALID [2022-02-20 22:59:33,624 INFO L290 TraceCheckUtils]: 4: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,624 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {32964#true} {32964#true} #4228#return; {32964#true} is VALID [2022-02-20 22:59:33,624 INFO L290 TraceCheckUtils]: 6: Hoare triple {32964#true} #res := ~val; {32964#true} is VALID [2022-02-20 22:59:33,624 INFO L290 TraceCheckUtils]: 7: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,625 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4806#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,625 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2022-02-20 22:59:33,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,637 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {32964#true} is VALID [2022-02-20 22:59:33,637 INFO L290 TraceCheckUtils]: 1: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,637 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4808#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,638 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 41 [2022-02-20 22:59:33,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,644 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} ~expression := #in~expression; {32964#true} is VALID [2022-02-20 22:59:33,644 INFO L290 TraceCheckUtils]: 1: Hoare triple {32964#true} assume !(0 == ~expression); {32964#true} is VALID [2022-02-20 22:59:33,644 INFO L290 TraceCheckUtils]: 2: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,644 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4816#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,646 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 56 [2022-02-20 22:59:33,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,655 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} ~expr := #in~expr; {32964#true} is VALID [2022-02-20 22:59:33,656 INFO L290 TraceCheckUtils]: 1: Hoare triple {32964#true} assume !(0 == ~expr); {32964#true} is VALID [2022-02-20 22:59:33,656 INFO L290 TraceCheckUtils]: 2: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,656 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {32964#true} {32965#false} #4648#return; {32965#false} is VALID [2022-02-20 22:59:33,656 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 61 [2022-02-20 22:59:33,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,663 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} ~expr := #in~expr; {32964#true} is VALID [2022-02-20 22:59:33,663 INFO L290 TraceCheckUtils]: 1: Hoare triple {32964#true} assume !(0 == ~expr); {32964#true} is VALID [2022-02-20 22:59:33,663 INFO L290 TraceCheckUtils]: 2: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,663 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {32964#true} {32965#false} #4650#return; {32965#false} is VALID [2022-02-20 22:59:33,664 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 66 [2022-02-20 22:59:33,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:59:33,670 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} ~expr := #in~expr; {32964#true} is VALID [2022-02-20 22:59:33,670 INFO L290 TraceCheckUtils]: 1: Hoare triple {32964#true} assume !(0 == ~expr); {32964#true} is VALID [2022-02-20 22:59:33,670 INFO L290 TraceCheckUtils]: 2: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,671 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {32964#true} {32965#false} #4652#return; {32965#false} is VALID [2022-02-20 22:59:33,671 INFO L290 TraceCheckUtils]: 0: Hoare triple {32964#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(199, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(9, 4);call #Ultimate.allocInit(9, 5);call #Ultimate.allocInit(7, 6);call write~init~int(15, 6, 0, 1);call write~init~int(37, 6, 1, 1);call write~init~int(115, 6, 2, 1);call write~init~int(40, 6, 3, 1);call write~init~int(41, 6, 4, 1);call write~init~int(10, 6, 5, 1);call write~init~int(0, 6, 6, 1);call #Ultimate.allocInit(14, 7);call #Ultimate.allocInit(9, 8);call #Ultimate.allocInit(45, 9);call #Ultimate.allocInit(14, 10);call #Ultimate.allocInit(25, 11);call #Ultimate.allocInit(13, 12);call #Ultimate.allocInit(22, 13);call #Ultimate.allocInit(13, 14);call #Ultimate.allocInit(23, 15);call #Ultimate.allocInit(13, 16);call #Ultimate.allocInit(23, 17);call #Ultimate.allocInit(13, 18);call #Ultimate.allocInit(22, 19);call #Ultimate.allocInit(13, 20);call #Ultimate.allocInit(7, 21);call write~init~int(15, 21, 0, 1);call write~init~int(37, 21, 1, 1);call write~init~int(115, 21, 2, 1);call write~init~int(40, 21, 3, 1);call write~init~int(41, 21, 4, 1);call write~init~int(10, 21, 5, 1);call write~init~int(0, 21, 6, 1);call #Ultimate.allocInit(17, 22);call #Ultimate.allocInit(7, 23);call write~init~int(15, 23, 0, 1);call write~init~int(37, 23, 1, 1);call write~init~int(115, 23, 2, 1);call write~init~int(40, 23, 3, 1);call write~init~int(41, 23, 4, 1);call write~init~int(10, 23, 5, 1);call write~init~int(0, 23, 6, 1);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(22, 25);call #Ultimate.allocInit(35, 26);call #Ultimate.allocInit(14, 27);call #Ultimate.allocInit(40, 28);call #Ultimate.allocInit(7, 29);call write~init~int(15, 29, 0, 1);call write~init~int(37, 29, 1, 1);call write~init~int(115, 29, 2, 1);call write~init~int(40, 29, 3, 1);call write~init~int(41, 29, 4, 1);call write~init~int(10, 29, 5, 1);call write~init~int(0, 29, 6, 1);call #Ultimate.allocInit(15, 30);call #Ultimate.allocInit(30, 31);call #Ultimate.allocInit(15, 32);call #Ultimate.allocInit(7, 33);call write~init~int(15, 33, 0, 1);call write~init~int(37, 33, 1, 1);call write~init~int(115, 33, 2, 1);call write~init~int(40, 33, 3, 1);call write~init~int(41, 33, 4, 1);call write~init~int(10, 33, 5, 1);call write~init~int(0, 33, 6, 1);call #Ultimate.allocInit(12, 34);call #Ultimate.allocInit(85, 35);call #Ultimate.allocInit(47, 36);call #Ultimate.allocInit(29, 37);call #Ultimate.allocInit(58, 38);call #Ultimate.allocInit(29, 39);call #Ultimate.allocInit(50, 40);call #Ultimate.allocInit(29, 41);call #Ultimate.allocInit(40, 42);call #Ultimate.allocInit(29, 43);call #Ultimate.allocInit(30, 44);call #Ultimate.allocInit(22, 45);call #Ultimate.allocInit(31, 46);call #Ultimate.allocInit(28, 47);call #Ultimate.allocInit(23, 48);call #Ultimate.allocInit(13, 49);call #Ultimate.allocInit(45, 50);call #Ultimate.allocInit(18, 51);call #Ultimate.allocInit(7, 52);call write~init~int(15, 52, 0, 1);call write~init~int(37, 52, 1, 1);call write~init~int(115, 52, 2, 1);call write~init~int(40, 52, 3, 1);call write~init~int(41, 52, 4, 1);call write~init~int(10, 52, 5, 1);call write~init~int(0, 52, 6, 1);call #Ultimate.allocInit(27, 53);call #Ultimate.allocInit(56, 54);call #Ultimate.allocInit(27, 55);call #Ultimate.allocInit(7, 56);call write~init~int(15, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(40, 56, 3, 1);call write~init~int(41, 56, 4, 1);call write~init~int(10, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(21, 57);call #Ultimate.allocInit(50, 58);call #Ultimate.allocInit(30, 59);call #Ultimate.allocInit(41, 60);call #Ultimate.allocInit(30, 61);call #Ultimate.allocInit(26, 62);call #Ultimate.allocInit(30, 63);call #Ultimate.allocInit(15, 64);call #Ultimate.allocInit(14, 65);call #Ultimate.allocInit(23, 66);call #Ultimate.allocInit(15, 67);call #Ultimate.allocInit(48, 68);call #Ultimate.allocInit(15, 69);call #Ultimate.allocInit(43, 70);call #Ultimate.allocInit(19, 71);call #Ultimate.allocInit(6, 72);call write~init~int(84, 72, 0, 1);call write~init~int(105, 72, 1, 1);call write~init~int(109, 72, 2, 1);call write~init~int(101, 72, 3, 1);call write~init~int(114, 72, 4, 1);call write~init~int(0, 72, 5, 1);call #Ultimate.allocInit(1, 73);call write~init~int(0, 73, 0, 1);call #Ultimate.allocInit(3, 74);call write~init~int(84, 74, 0, 1);call write~init~int(120, 74, 1, 1);call write~init~int(0, 74, 2, 1);call #Ultimate.allocInit(1, 75);call write~init~int(0, 75, 0, 1);call #Ultimate.allocInit(3, 76);call write~init~int(82, 76, 0, 1);call write~init~int(120, 76, 1, 1);call write~init~int(0, 76, 2, 1);call #Ultimate.allocInit(1, 77);call write~init~int(0, 77, 0, 1);call #Ultimate.allocInit(38, 78);call #Ultimate.allocInit(19, 79);call #Ultimate.allocInit(13, 80);call #Ultimate.allocInit(1, 81);call write~init~int(0, 81, 0, 1);call #Ultimate.allocInit(4, 82);call write~init~int(69, 82, 0, 1);call write~init~int(79, 82, 1, 1);call write~init~int(77, 82, 2, 1);call write~init~int(0, 82, 3, 1);call #Ultimate.allocInit(1, 83);call write~init~int(0, 83, 0, 1);call #Ultimate.allocInit(11, 84);call #Ultimate.allocInit(1, 85);call write~init~int(0, 85, 0, 1);call #Ultimate.allocInit(10, 86);call #Ultimate.allocInit(1, 87);call write~init~int(0, 87, 0, 1);call #Ultimate.allocInit(47, 88);call #Ultimate.allocInit(19, 89);call #Ultimate.allocInit(9, 90);call #Ultimate.allocInit(1, 91);call write~init~int(0, 91, 0, 1);call #Ultimate.allocInit(8, 92);call #Ultimate.allocInit(1, 93);call write~init~int(0, 93, 0, 1);call #Ultimate.allocInit(12, 94);call #Ultimate.allocInit(1, 95);call write~init~int(0, 95, 0, 1);call #Ultimate.allocInit(4, 96);call write~init~int(69, 96, 0, 1);call write~init~int(79, 96, 1, 1);call write~init~int(70, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(1, 97);call write~init~int(0, 97, 0, 1);call #Ultimate.allocInit(7, 98);call write~init~int(82, 98, 0, 1);call write~init~int(120, 98, 1, 1);call write~init~int(68, 98, 2, 1);call write~init~int(97, 98, 3, 1);call write~init~int(116, 98, 4, 1);call write~init~int(97, 98, 5, 1);call write~init~int(0, 98, 6, 1);call #Ultimate.allocInit(1, 99);call write~init~int(0, 99, 0, 1);call #Ultimate.allocInit(9, 100);call #Ultimate.allocInit(1, 101);call write~init~int(0, 101, 0, 1);call #Ultimate.allocInit(8, 102);call #Ultimate.allocInit(1, 103);call write~init~int(0, 103, 0, 1);call #Ultimate.allocInit(17, 104);call #Ultimate.allocInit(19, 105);call #Ultimate.allocInit(79, 106);call #Ultimate.allocInit(19, 107);call #Ultimate.allocInit(7, 108);call write~init~int(15, 108, 0, 1);call write~init~int(37, 108, 1, 1);call write~init~int(115, 108, 2, 1);call write~init~int(40, 108, 3, 1);call write~init~int(41, 108, 4, 1);call write~init~int(10, 108, 5, 1);call write~init~int(0, 108, 6, 1);call #Ultimate.allocInit(8, 109);call #Ultimate.allocInit(31, 110);call #Ultimate.allocInit(28, 111);call #Ultimate.allocInit(22, 112);call #Ultimate.allocInit(13, 113);call #Ultimate.allocInit(22, 114);call #Ultimate.allocInit(22, 115);call #Ultimate.allocInit(7, 116);call write~init~int(15, 116, 0, 1);call write~init~int(37, 116, 1, 1);call write~init~int(115, 116, 2, 1);call write~init~int(40, 116, 3, 1);call write~init~int(41, 116, 4, 1);call write~init~int(10, 116, 5, 1);call write~init~int(0, 116, 6, 1);call #Ultimate.allocInit(18, 117);call #Ultimate.allocInit(31, 118);call #Ultimate.allocInit(28, 119);call #Ultimate.allocInit(18, 120);call #Ultimate.allocInit(12, 121);call #Ultimate.allocInit(31, 122);call #Ultimate.allocInit(28, 123);call #Ultimate.allocInit(18, 124);call #Ultimate.allocInit(13, 125);call #Ultimate.allocInit(32, 126);call #Ultimate.allocInit(32, 127);call #Ultimate.allocInit(33, 128);call #Ultimate.allocInit(11, 129);call #Ultimate.allocInit(7, 130);call write~init~int(15, 130, 0, 1);call write~init~int(37, 130, 1, 1);call write~init~int(115, 130, 2, 1);call write~init~int(40, 130, 3, 1);call write~init~int(41, 130, 4, 1);call write~init~int(10, 130, 5, 1);call write~init~int(0, 130, 6, 1);call #Ultimate.allocInit(19, 131);call #Ultimate.allocInit(31, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(19, 134);call #Ultimate.allocInit(12, 135);call #Ultimate.allocInit(31, 136);call #Ultimate.allocInit(28, 137);call #Ultimate.allocInit(19, 138);call #Ultimate.allocInit(13, 139);call #Ultimate.allocInit(31, 140);call #Ultimate.allocInit(28, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(12, 143);call #Ultimate.allocInit(31, 144);call #Ultimate.allocInit(28, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(13, 147);call #Ultimate.allocInit(23, 148);call #Ultimate.allocInit(19, 149);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(2, 151);call write~init~int(48, 151, 0, 1);call write~init~int(0, 151, 1, 1);call #Ultimate.allocInit(73, 152);~driver_name~0.base, ~driver_name~0.offset := 4, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 153, 0;call #Ultimate.allocInit(192, 153);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#via_driver~0.base, ~#via_driver~0.offset := 154, 0;call #Ultimate.allocInit(301, 154);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(5, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 145 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 153 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 161 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 169 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 177 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 185 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 193 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 201 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 209 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 217 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 237 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 245 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 253 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 261 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 269 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 285 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 293 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 155, 0;call #Ultimate.allocInit(472, 155);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 156, 0;call #Ultimate.allocInit(472, 156);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_thread_0~0.identifier := 0;~ldv_thread_0~0.function.base, ~ldv_thread_0~0.function.offset := 0, 0;~ldv_thread_1~0.identifier := 0;~ldv_thread_1~0.function.base, ~ldv_thread_1~0.function.offset := 0, 0;~ldv_thread_10~0.identifier := 0;~ldv_thread_10~0.function.base, ~ldv_thread_10~0.function.offset := 0, 0;~ldv_thread_2~0.identifier := 0;~ldv_thread_2~0.function.base, ~ldv_thread_2~0.function.offset := 0, 0;~ldv_spin_NOT_ARG_SIGN~0 := 1;~ldv_spin__xmit_lock_of_netdev_queue~0 := 1;~ldv_spin_addr_list_lock_of_net_device~0 := 1;~ldv_spin_alloc_lock_of_task_struct~0 := 1;~ldv_spin_dma_spin_lock~0 := 1;~ldv_spin_i_lock_of_inode~0 := 1;~ldv_spin_lock~0 := 1;~ldv_spin_lock_of_NOT_ARG_SIGN~0 := 1;~ldv_spin_lock_of_via_ircc_cb~0 := 1;~ldv_spin_lru_lock_of_netns_frags~0 := 1;~ldv_spin_node_size_lock_of_pglist_data~0 := 1;~ldv_spin_ptl~0 := 1;~ldv_spin_siglock_of_sighand_struct~0 := 1;~ldv_spin_tx_global_lock_of_net_device~0 := 1; {32964#true} is VALID [2022-02-20 22:59:33,671 INFO L290 TraceCheckUtils]: 1: Hoare triple {32964#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_ldv_initialize } true; {32964#true} is VALID [2022-02-20 22:59:33,672 INFO L290 TraceCheckUtils]: 2: Hoare triple {32964#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_entry_EMGentry_10 } true;ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset := 0, 0;havoc ldv_entry_EMGentry_10_#t~ret831#1, ldv_entry_EMGentry_10_#t~ret832#1, ldv_entry_EMGentry_10_#t~ret833#1, ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1, ldv_entry_EMGentry_10_~tmp~52#1;ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset := ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_entry_EMGentry_10_~tmp~52#1;assume { :begin_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset := ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_#res#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset, ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset := ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;assume { :begin_inline_via_ircc_init } true;havoc via_ircc_init_#res#1;havoc via_ircc_init_#t~nondet244#1, via_ircc_init_#t~ret245#1, via_ircc_init_#t~nondet246#1, via_ircc_init_~rc~0#1;havoc via_ircc_init_~rc~0#1; {32964#true} is VALID [2022-02-20 22:59:33,673 INFO L290 TraceCheckUtils]: 3: Hoare triple {32964#true} assume !(~irda_debug~0 % 4294967296 > 2); {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,673 INFO L290 TraceCheckUtils]: 4: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} assume { :begin_inline_ldv___pci_register_driver_66 } true;ldv___pci_register_driver_66_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.offset := ~#via_driver~0.base, ~#via_driver~0.offset, ~#__this_module~0.base, ~#__this_module~0.offset, 8, 0;havoc ldv___pci_register_driver_66_#res#1;havoc ldv___pci_register_driver_66_#t~ret900#1, ldv___pci_register_driver_66_#t~ret901#1, ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset, ldv___pci_register_driver_66_~ldv_func_res~0#1, ldv___pci_register_driver_66_~tmp~65#1, ldv___pci_register_driver_66_~tmp___0~20#1;ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg1#1.offset;ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg2#1.offset;ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset := ldv___pci_register_driver_66_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_66_#in~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_66_~ldv_func_res~0#1;havoc ldv___pci_register_driver_66_~tmp~65#1;havoc ldv___pci_register_driver_66_~tmp___0~20#1;assume { :begin_inline___pci_register_driver } true;__pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset, __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset, __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset := ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset;havoc __pci_register_driver_#res#1;havoc __pci_register_driver_#t~nondet1022#1, __pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset, __pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset, __pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset;__pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset := __pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset;__pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset := __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset;__pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset := __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset;assume -2147483648 <= __pci_register_driver_#t~nondet1022#1 && __pci_register_driver_#t~nondet1022#1 <= 2147483647;__pci_register_driver_#res#1 := __pci_register_driver_#t~nondet1022#1;havoc __pci_register_driver_#t~nondet1022#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,674 INFO L290 TraceCheckUtils]: 5: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} ldv___pci_register_driver_66_#t~ret900#1 := __pci_register_driver_#res#1;assume { :end_inline___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_66_#t~ret900#1 && ldv___pci_register_driver_66_#t~ret900#1 <= 2147483647;ldv___pci_register_driver_66_~tmp~65#1 := ldv___pci_register_driver_66_#t~ret900#1;havoc ldv___pci_register_driver_66_#t~ret900#1;ldv___pci_register_driver_66_~ldv_func_res~0#1 := ldv___pci_register_driver_66_~tmp~65#1;assume { :begin_inline_ldv___pci_register_driver } true;ldv___pci_register_driver_#in~arg0#1, ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset, ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset, ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset := ldv___pci_register_driver_66_~ldv_func_res~0#1, ldv___pci_register_driver_66_~ldv_func_arg1#1.base, ldv___pci_register_driver_66_~ldv_func_arg1#1.offset, ldv___pci_register_driver_66_~ldv_func_arg2#1.base, ldv___pci_register_driver_66_~ldv_func_arg2#1.offset, ldv___pci_register_driver_66_~ldv_func_arg3#1.base, ldv___pci_register_driver_66_~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_#res#1;havoc ldv___pci_register_driver_#t~ret825#1, ldv___pci_register_driver_~arg0#1, ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset, ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset, ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset, ldv___pci_register_driver_~tmp~48#1;ldv___pci_register_driver_~arg0#1 := ldv___pci_register_driver_#in~arg0#1;ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset := ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset;ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset := ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset;ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset := ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset;havoc ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset;havoc ldv___pci_register_driver_~tmp~48#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,674 INFO L272 TraceCheckUtils]: 6: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} call ldv___pci_register_driver_#t~ret825#1 := ldv_undef_int(); {32964#true} is VALID [2022-02-20 22:59:33,674 INFO L290 TraceCheckUtils]: 7: Hoare triple {32964#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {32964#true} is VALID [2022-02-20 22:59:33,675 INFO L290 TraceCheckUtils]: 8: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,675 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4692#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,675 INFO L290 TraceCheckUtils]: 10: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} assume -2147483648 <= ldv___pci_register_driver_#t~ret825#1 && ldv___pci_register_driver_#t~ret825#1 <= 2147483647;ldv___pci_register_driver_~tmp~48#1 := ldv___pci_register_driver_#t~ret825#1;havoc ldv___pci_register_driver_#t~ret825#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,676 INFO L290 TraceCheckUtils]: 11: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} assume !(0 != ldv___pci_register_driver_~tmp~48#1); {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,676 INFO L272 TraceCheckUtils]: 12: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} call ldv_assume((if 0 != ldv___pci_register_driver_~arg0#1 then 1 else 0)); {32964#true} is VALID [2022-02-20 22:59:33,676 INFO L290 TraceCheckUtils]: 13: Hoare triple {32964#true} ~expression := #in~expression; {32964#true} is VALID [2022-02-20 22:59:33,676 INFO L290 TraceCheckUtils]: 14: Hoare triple {32964#true} assume !(0 == ~expression); {32964#true} is VALID [2022-02-20 22:59:33,676 INFO L290 TraceCheckUtils]: 15: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,677 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4804#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,677 INFO L290 TraceCheckUtils]: 17: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} ldv___pci_register_driver_#res#1 := ldv___pci_register_driver_~arg0#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,677 INFO L290 TraceCheckUtils]: 18: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} ldv___pci_register_driver_66_#t~ret901#1 := ldv___pci_register_driver_#res#1;assume { :end_inline_ldv___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_66_#t~ret901#1 && ldv___pci_register_driver_66_#t~ret901#1 <= 2147483647;ldv___pci_register_driver_66_~tmp___0~20#1 := ldv___pci_register_driver_66_#t~ret901#1;havoc ldv___pci_register_driver_66_#t~ret901#1;ldv___pci_register_driver_66_#res#1 := ldv___pci_register_driver_66_~tmp___0~20#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,678 INFO L290 TraceCheckUtils]: 19: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} via_ircc_init_#t~ret245#1 := ldv___pci_register_driver_66_#res#1;assume { :end_inline_ldv___pci_register_driver_66 } true;assume -2147483648 <= via_ircc_init_#t~ret245#1 && via_ircc_init_#t~ret245#1 <= 2147483647;via_ircc_init_~rc~0#1 := via_ircc_init_#t~ret245#1;havoc via_ircc_init_#t~ret245#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,678 INFO L290 TraceCheckUtils]: 20: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} assume via_ircc_init_~rc~0#1 < 0;havoc via_ircc_init_#t~nondet246#1;via_ircc_init_#res#1 := -19; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,679 INFO L290 TraceCheckUtils]: 21: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 := via_ircc_init_#res#1;assume { :end_inline_via_ircc_init } true;assume -2147483648 <= ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 && ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1 <= 2147483647;ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1 := ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret824#1;ldv_EMGentry_init_via_ircc_init_10_7_#res#1 := ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,679 INFO L290 TraceCheckUtils]: 22: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} ldv_entry_EMGentry_10_#t~ret831#1 := ldv_EMGentry_init_via_ircc_init_10_7_#res#1;assume { :end_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret831#1 && ldv_entry_EMGentry_10_#t~ret831#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret831#1;havoc ldv_entry_EMGentry_10_#t~ret831#1;assume { :begin_inline_ldv_post_init } true;ldv_post_init_#in~init_ret_val#1 := ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_post_init_#res#1;havoc ldv_post_init_#t~ret915#1, ldv_post_init_~init_ret_val#1, ldv_post_init_~tmp~71#1;ldv_post_init_~init_ret_val#1 := ldv_post_init_#in~init_ret_val#1;havoc ldv_post_init_~tmp~71#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,679 INFO L272 TraceCheckUtils]: 23: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} call ldv_post_init_#t~ret915#1 := ldv_filter_positive_int(ldv_post_init_~init_ret_val#1); {32964#true} is VALID [2022-02-20 22:59:33,679 INFO L290 TraceCheckUtils]: 24: Hoare triple {32964#true} ~val := #in~val; {32964#true} is VALID [2022-02-20 22:59:33,684 INFO L272 TraceCheckUtils]: 25: Hoare triple {32964#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {32964#true} is VALID [2022-02-20 22:59:33,684 INFO L290 TraceCheckUtils]: 26: Hoare triple {32964#true} ~expression := #in~expression; {32964#true} is VALID [2022-02-20 22:59:33,684 INFO L290 TraceCheckUtils]: 27: Hoare triple {32964#true} assume !(0 == ~expression); {32964#true} is VALID [2022-02-20 22:59:33,684 INFO L290 TraceCheckUtils]: 28: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,684 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {32964#true} {32964#true} #4228#return; {32964#true} is VALID [2022-02-20 22:59:33,684 INFO L290 TraceCheckUtils]: 30: Hoare triple {32964#true} #res := ~val; {32964#true} is VALID [2022-02-20 22:59:33,685 INFO L290 TraceCheckUtils]: 31: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,685 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4806#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,685 INFO L290 TraceCheckUtils]: 33: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} assume -2147483648 <= ldv_post_init_#t~ret915#1 && ldv_post_init_#t~ret915#1 <= 2147483647;ldv_post_init_~tmp~71#1 := ldv_post_init_#t~ret915#1;havoc ldv_post_init_#t~ret915#1;ldv_post_init_#res#1 := ldv_post_init_~tmp~71#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,686 INFO L290 TraceCheckUtils]: 34: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} ldv_entry_EMGentry_10_#t~ret832#1 := ldv_post_init_#res#1;assume { :end_inline_ldv_post_init } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret832#1 && ldv_entry_EMGentry_10_#t~ret832#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret832#1;havoc ldv_entry_EMGentry_10_#t~ret832#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,686 INFO L272 TraceCheckUtils]: 35: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} call ldv_entry_EMGentry_10_#t~ret833#1 := ldv_undef_int(); {32964#true} is VALID [2022-02-20 22:59:33,686 INFO L290 TraceCheckUtils]: 36: Hoare triple {32964#true} havoc ~tmp~79;assume -2147483648 <= #t~nondet941 && #t~nondet941 <= 2147483647;~tmp~79 := #t~nondet941;havoc #t~nondet941;#res := ~tmp~79; {32964#true} is VALID [2022-02-20 22:59:33,686 INFO L290 TraceCheckUtils]: 37: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,687 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4808#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,687 INFO L290 TraceCheckUtils]: 39: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret833#1 && ldv_entry_EMGentry_10_#t~ret833#1 <= 2147483647;ldv_entry_EMGentry_10_~tmp~52#1 := ldv_entry_EMGentry_10_#t~ret833#1;havoc ldv_entry_EMGentry_10_#t~ret833#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,687 INFO L290 TraceCheckUtils]: 40: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} assume !(0 != ldv_entry_EMGentry_10_~tmp~52#1); {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,688 INFO L272 TraceCheckUtils]: 41: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} call ldv_assume((if 0 == ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 then 1 else 0)); {32964#true} is VALID [2022-02-20 22:59:33,688 INFO L290 TraceCheckUtils]: 42: Hoare triple {32964#true} ~expression := #in~expression; {32964#true} is VALID [2022-02-20 22:59:33,688 INFO L290 TraceCheckUtils]: 43: Hoare triple {32964#true} assume !(0 == ~expression); {32964#true} is VALID [2022-02-20 22:59:33,688 INFO L290 TraceCheckUtils]: 44: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,688 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {32964#true} {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} #4816#return; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,689 INFO L290 TraceCheckUtils]: 46: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} assume { :begin_inline_ldv_EMGentry_exit_via_ircc_cleanup_10_2 } true;ldv_EMGentry_exit_via_ircc_cleanup_10_2_#in~arg0#1.base, ldv_EMGentry_exit_via_ircc_cleanup_10_2_#in~arg0#1.offset := ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset;havoc ldv_EMGentry_exit_via_ircc_cleanup_10_2_~arg0#1.base, ldv_EMGentry_exit_via_ircc_cleanup_10_2_~arg0#1.offset;ldv_EMGentry_exit_via_ircc_cleanup_10_2_~arg0#1.base, ldv_EMGentry_exit_via_ircc_cleanup_10_2_~arg0#1.offset := ldv_EMGentry_exit_via_ircc_cleanup_10_2_#in~arg0#1.base, ldv_EMGentry_exit_via_ircc_cleanup_10_2_#in~arg0#1.offset;assume { :begin_inline_via_ircc_cleanup } true;havoc via_ircc_cleanup_#t~nondet302#1; {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} is VALID [2022-02-20 22:59:33,690 INFO L290 TraceCheckUtils]: 47: Hoare triple {32966#(<= ~irda_debug~0 (+ 2 (* 4294967296 (div ~irda_debug~0 4294967296))))} assume ~irda_debug~0 % 4294967296 > 2;havoc via_ircc_cleanup_#t~nondet302#1; {32965#false} is VALID [2022-02-20 22:59:33,690 INFO L290 TraceCheckUtils]: 48: Hoare triple {32965#false} assume { :begin_inline_ldv_pci_unregister_driver_67 } true;ldv_pci_unregister_driver_67_#in~ldv_func_arg1#1.base, ldv_pci_unregister_driver_67_#in~ldv_func_arg1#1.offset := ~#via_driver~0.base, ~#via_driver~0.offset;havoc ldv_pci_unregister_driver_67_~ldv_func_arg1#1.base, ldv_pci_unregister_driver_67_~ldv_func_arg1#1.offset;ldv_pci_unregister_driver_67_~ldv_func_arg1#1.base, ldv_pci_unregister_driver_67_~ldv_func_arg1#1.offset := ldv_pci_unregister_driver_67_#in~ldv_func_arg1#1.base, ldv_pci_unregister_driver_67_#in~ldv_func_arg1#1.offset;assume { :begin_inline_pci_unregister_driver } true;pci_unregister_driver_#in~arg0#1.base, pci_unregister_driver_#in~arg0#1.offset := ldv_pci_unregister_driver_67_~ldv_func_arg1#1.base, ldv_pci_unregister_driver_67_~ldv_func_arg1#1.offset;havoc pci_unregister_driver_~arg0#1.base, pci_unregister_driver_~arg0#1.offset;pci_unregister_driver_~arg0#1.base, pci_unregister_driver_~arg0#1.offset := pci_unregister_driver_#in~arg0#1.base, pci_unregister_driver_#in~arg0#1.offset; {32965#false} is VALID [2022-02-20 22:59:33,690 INFO L290 TraceCheckUtils]: 49: Hoare triple {32965#false} assume { :end_inline_pci_unregister_driver } true;assume { :begin_inline_ldv_pci_unregister_driver } true;ldv_pci_unregister_driver_#in~arg0#1.base, ldv_pci_unregister_driver_#in~arg0#1.offset, ldv_pci_unregister_driver_#in~arg1#1.base, ldv_pci_unregister_driver_#in~arg1#1.offset := 0, 0, ldv_pci_unregister_driver_67_~ldv_func_arg1#1.base, ldv_pci_unregister_driver_67_~ldv_func_arg1#1.offset;havoc ldv_pci_unregister_driver_~arg0#1.base, ldv_pci_unregister_driver_~arg0#1.offset, ldv_pci_unregister_driver_~arg1#1.base, ldv_pci_unregister_driver_~arg1#1.offset, ldv_pci_unregister_driver_~ldv_8_pci_driver_pci_driver~0#1.base, ldv_pci_unregister_driver_~ldv_8_pci_driver_pci_driver~0#1.offset;ldv_pci_unregister_driver_~arg0#1.base, ldv_pci_unregister_driver_~arg0#1.offset := ldv_pci_unregister_driver_#in~arg0#1.base, ldv_pci_unregister_driver_#in~arg0#1.offset;ldv_pci_unregister_driver_~arg1#1.base, ldv_pci_unregister_driver_~arg1#1.offset := ldv_pci_unregister_driver_#in~arg1#1.base, ldv_pci_unregister_driver_#in~arg1#1.offset;havoc ldv_pci_unregister_driver_~ldv_8_pci_driver_pci_driver~0#1.base, ldv_pci_unregister_driver_~ldv_8_pci_driver_pci_driver~0#1.offset;ldv_pci_unregister_driver_~ldv_8_pci_driver_pci_driver~0#1.base, ldv_pci_unregister_driver_~ldv_8_pci_driver_pci_driver~0#1.offset := ldv_pci_unregister_driver_~arg1#1.base, ldv_pci_unregister_driver_~arg1#1.offset;assume { :begin_inline_ldv_dispatch_deregister_8_1 } true;ldv_dispatch_deregister_8_1_#in~arg0#1.base, ldv_dispatch_deregister_8_1_#in~arg0#1.offset := ldv_pci_unregister_driver_~ldv_8_pci_driver_pci_driver~0#1.base, ldv_pci_unregister_driver_~ldv_8_pci_driver_pci_driver~0#1.offset;havoc ldv_dispatch_deregister_8_1_~arg0#1.base, ldv_dispatch_deregister_8_1_~arg0#1.offset;ldv_dispatch_deregister_8_1_~arg0#1.base, ldv_dispatch_deregister_8_1_~arg0#1.offset := ldv_dispatch_deregister_8_1_#in~arg0#1.base, ldv_dispatch_deregister_8_1_#in~arg0#1.offset; {32965#false} is VALID [2022-02-20 22:59:33,690 INFO L290 TraceCheckUtils]: 50: Hoare triple {32965#false} assume { :end_inline_ldv_dispatch_deregister_8_1 } true; {32965#false} is VALID [2022-02-20 22:59:33,690 INFO L290 TraceCheckUtils]: 51: Hoare triple {32965#false} assume { :end_inline_ldv_pci_unregister_driver } true; {32965#false} is VALID [2022-02-20 22:59:33,691 INFO L290 TraceCheckUtils]: 52: Hoare triple {32965#false} assume { :end_inline_ldv_pci_unregister_driver_67 } true; {32965#false} is VALID [2022-02-20 22:59:33,691 INFO L290 TraceCheckUtils]: 53: Hoare triple {32965#false} assume { :end_inline_via_ircc_cleanup } true; {32965#false} is VALID [2022-02-20 22:59:33,691 INFO L290 TraceCheckUtils]: 54: Hoare triple {32965#false} assume { :end_inline_ldv_EMGentry_exit_via_ircc_cleanup_10_2 } true; {32965#false} is VALID [2022-02-20 22:59:33,691 INFO L272 TraceCheckUtils]: 55: Hoare triple {32965#false} call ldv_check_final_state(); {32965#false} is VALID [2022-02-20 22:59:33,691 INFO L272 TraceCheckUtils]: 56: Hoare triple {32965#false} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin_NOT_ARG_SIGN~0 then 1 else 0)); {32964#true} is VALID [2022-02-20 22:59:33,691 INFO L290 TraceCheckUtils]: 57: Hoare triple {32964#true} ~expr := #in~expr; {32964#true} is VALID [2022-02-20 22:59:33,692 INFO L290 TraceCheckUtils]: 58: Hoare triple {32964#true} assume !(0 == ~expr); {32964#true} is VALID [2022-02-20 22:59:33,692 INFO L290 TraceCheckUtils]: 59: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,692 INFO L284 TraceCheckUtils]: 60: Hoare quadruple {32964#true} {32965#false} #4648#return; {32965#false} is VALID [2022-02-20 22:59:33,692 INFO L272 TraceCheckUtils]: 61: Hoare triple {32965#false} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin__xmit_lock_of_netdev_queue~0 then 1 else 0)); {32964#true} is VALID [2022-02-20 22:59:33,692 INFO L290 TraceCheckUtils]: 62: Hoare triple {32964#true} ~expr := #in~expr; {32964#true} is VALID [2022-02-20 22:59:33,693 INFO L290 TraceCheckUtils]: 63: Hoare triple {32964#true} assume !(0 == ~expr); {32964#true} is VALID [2022-02-20 22:59:33,693 INFO L290 TraceCheckUtils]: 64: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,694 INFO L284 TraceCheckUtils]: 65: Hoare quadruple {32964#true} {32965#false} #4650#return; {32965#false} is VALID [2022-02-20 22:59:33,694 INFO L272 TraceCheckUtils]: 66: Hoare triple {32965#false} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin_addr_list_lock_of_net_device~0 then 1 else 0)); {32964#true} is VALID [2022-02-20 22:59:33,695 INFO L290 TraceCheckUtils]: 67: Hoare triple {32964#true} ~expr := #in~expr; {32964#true} is VALID [2022-02-20 22:59:33,696 INFO L290 TraceCheckUtils]: 68: Hoare triple {32964#true} assume !(0 == ~expr); {32964#true} is VALID [2022-02-20 22:59:33,696 INFO L290 TraceCheckUtils]: 69: Hoare triple {32964#true} assume true; {32964#true} is VALID [2022-02-20 22:59:33,696 INFO L284 TraceCheckUtils]: 70: Hoare quadruple {32964#true} {32965#false} #4652#return; {32965#false} is VALID [2022-02-20 22:59:33,696 INFO L272 TraceCheckUtils]: 71: Hoare triple {32965#false} call ldv_assert_linux_kernel_locking_spinlock__one_thread_locked_at_exit((if 1 == ~ldv_spin_alloc_lock_of_task_struct~0 then 1 else 0)); {32965#false} is VALID [2022-02-20 22:59:33,697 INFO L290 TraceCheckUtils]: 72: Hoare triple {32965#false} ~expr := #in~expr; {32965#false} is VALID [2022-02-20 22:59:33,697 INFO L290 TraceCheckUtils]: 73: Hoare triple {32965#false} assume 0 == ~expr; {32965#false} is VALID [2022-02-20 22:59:33,697 INFO L290 TraceCheckUtils]: 74: Hoare triple {32965#false} assume !false; {32965#false} is VALID [2022-02-20 22:59:33,697 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2022-02-20 22:59:33,697 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:59:33,698 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577030249] [2022-02-20 22:59:33,698 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577030249] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:59:33,698 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:59:33,698 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-20 22:59:33,698 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853975336] [2022-02-20 22:59:33,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:59:33,699 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 3 states have call successors, (11), 2 states have call predecessors, (11), 1 states have return successors, (9), 3 states have call predecessors, (9), 3 states have call successors, (9) Word has length 75 [2022-02-20 22:59:33,699 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:59:33,699 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 3 states have call successors, (11), 2 states have call predecessors, (11), 1 states have return successors, (9), 3 states have call predecessors, (9), 3 states have call successors, (9) [2022-02-20 22:59:33,762 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:59:33,762 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-02-20 22:59:33,762 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:59:33,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-20 22:59:33,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-20 22:59:33,763 INFO L87 Difference]: Start difference. First operand 1902 states and 2733 transitions. Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 3 states have call successors, (11), 2 states have call predecessors, (11), 1 states have return successors, (9), 3 states have call predecessors, (9), 3 states have call successors, (9)