./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash b690325b7d1e58e38bff17a4189057cbc4b34bf32c3567c06d7db1b90b9742db --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 23:00:39,661 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 23:00:39,663 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 23:00:39,681 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 23:00:39,682 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 23:00:39,683 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 23:00:39,684 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 23:00:39,685 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 23:00:39,686 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 23:00:39,686 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 23:00:39,687 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 23:00:39,689 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 23:00:39,690 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 23:00:39,692 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 23:00:39,693 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 23:00:39,694 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 23:00:39,695 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 23:00:39,698 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 23:00:39,699 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 23:00:39,703 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 23:00:39,704 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 23:00:39,705 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 23:00:39,706 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 23:00:39,706 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 23:00:39,710 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 23:00:39,710 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 23:00:39,711 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 23:00:39,712 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 23:00:39,712 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 23:00:39,713 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 23:00:39,716 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 23:00:39,716 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 23:00:39,717 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 23:00:39,717 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 23:00:39,718 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 23:00:39,718 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 23:00:39,718 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 23:00:39,719 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 23:00:39,719 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 23:00:39,720 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 23:00:39,721 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 23:00:39,721 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 23:00:39,734 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 23:00:39,738 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 23:00:39,739 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 23:00:39,739 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 23:00:39,740 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 23:00:39,740 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 23:00:39,740 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 23:00:39,741 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 23:00:39,741 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 23:00:39,741 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 23:00:39,741 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 23:00:39,742 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 23:00:39,742 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 23:00:39,742 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 23:00:39,742 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 23:00:39,742 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 23:00:39,742 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 23:00:39,742 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 23:00:39,743 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 23:00:39,743 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 23:00:39,743 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 23:00:39,743 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 23:00:39,743 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 23:00:39,743 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 23:00:39,743 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 23:00:39,744 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 23:00:39,744 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 23:00:39,744 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 23:00:39,744 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 23:00:39,744 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 23:00:39,744 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b690325b7d1e58e38bff17a4189057cbc4b34bf32c3567c06d7db1b90b9742db [2022-02-20 23:00:39,908 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 23:00:39,921 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 23:00:39,923 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 23:00:39,924 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 23:00:39,926 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 23:00:39,927 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i [2022-02-20 23:00:39,985 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0e66440ac/b43212eb23e34c27bc1e439b30a1f887/FLAGc82196d38 [2022-02-20 23:00:40,563 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 23:00:40,564 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i [2022-02-20 23:00:40,603 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0e66440ac/b43212eb23e34c27bc1e439b30a1f887/FLAGc82196d38 [2022-02-20 23:00:40,785 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0e66440ac/b43212eb23e34c27bc1e439b30a1f887 [2022-02-20 23:00:40,788 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 23:00:40,790 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 23:00:40,792 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 23:00:40,793 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 23:00:40,795 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 23:00:40,796 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 11:00:40" (1/1) ... [2022-02-20 23:00:40,798 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@464de400 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:40, skipping insertion in model container [2022-02-20 23:00:40,798 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 11:00:40" (1/1) ... [2022-02-20 23:00:40,816 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 23:00:40,892 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 23:00:42,483 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i[290402,290415] [2022-02-20 23:00:42,485 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i[290549,290562] [2022-02-20 23:00:42,492 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i[290688,290701] [2022-02-20 23:00:42,493 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i[290846,290859] [2022-02-20 23:00:42,506 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 23:00:42,557 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 23:00:42,798 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i[290402,290415] [2022-02-20 23:00:42,799 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i[290549,290562] [2022-02-20 23:00:42,800 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i[290688,290701] [2022-02-20 23:00:42,800 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-3.14/linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i[290846,290859] [2022-02-20 23:00:42,806 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 23:00:42,894 INFO L208 MainTranslator]: Completed translation [2022-02-20 23:00:42,895 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42 WrapperNode [2022-02-20 23:00:42,895 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 23:00:42,896 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 23:00:42,896 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 23:00:42,896 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 23:00:42,902 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:42,977 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:43,121 INFO L137 Inliner]: procedures = 281, calls = 1828, calls flagged for inlining = 136, calls inlined = 128, statements flattened = 4216 [2022-02-20 23:00:43,122 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 23:00:43,123 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 23:00:43,123 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 23:00:43,123 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 23:00:43,129 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:43,130 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:43,147 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:43,148 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:43,265 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:43,283 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:43,303 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:43,330 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 23:00:43,331 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 23:00:43,331 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 23:00:43,331 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 23:00:43,333 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (1/1) ... [2022-02-20 23:00:43,338 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 23:00:43,345 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 23:00:43,356 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 23:00:43,365 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 23:00:43,392 INFO L130 BoogieDeclarations]: Found specification of procedure ResetChip [2022-02-20 23:00:43,392 INFO L138 BoogieDeclarations]: Found implementation of procedure ResetChip [2022-02-20 23:00:43,392 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2022-02-20 23:00:43,392 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2022-02-20 23:00:43,392 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 23:00:43,392 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 23:00:43,393 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2022-02-20 23:00:43,393 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2022-02-20 23:00:43,393 INFO L130 BoogieDeclarations]: Found specification of procedure RxCurCount [2022-02-20 23:00:43,393 INFO L138 BoogieDeclarations]: Found implementation of procedure RxCurCount [2022-02-20 23:00:43,393 INFO L130 BoogieDeclarations]: Found specification of procedure irda_device_txqueue_empty [2022-02-20 23:00:43,393 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_device_txqueue_empty [2022-02-20 23:00:43,393 INFO L130 BoogieDeclarations]: Found specification of procedure irda_setup_dma [2022-02-20 23:00:43,393 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_setup_dma [2022-02-20 23:00:43,394 INFO L130 BoogieDeclarations]: Found specification of procedure netif_wake_queue [2022-02-20 23:00:43,394 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_wake_queue [2022-02-20 23:00:43,394 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 23:00:43,394 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 23:00:43,394 INFO L130 BoogieDeclarations]: Found specification of procedure pci_read_config_byte [2022-02-20 23:00:43,394 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_read_config_byte [2022-02-20 23:00:43,394 INFO L130 BoogieDeclarations]: Found specification of procedure Sdelay [2022-02-20 23:00:43,394 INFO L138 BoogieDeclarations]: Found implementation of procedure Sdelay [2022-02-20 23:00:43,394 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2022-02-20 23:00:43,395 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2022-02-20 23:00:43,395 INFO L130 BoogieDeclarations]: Found specification of procedure CheckRegBit [2022-02-20 23:00:43,395 INFO L138 BoogieDeclarations]: Found implementation of procedure CheckRegBit [2022-02-20 23:00:43,395 INFO L130 BoogieDeclarations]: Found specification of procedure via_remove_one [2022-02-20 23:00:43,395 INFO L138 BoogieDeclarations]: Found implementation of procedure via_remove_one [2022-02-20 23:00:43,395 INFO L130 BoogieDeclarations]: Found specification of procedure SetSIR [2022-02-20 23:00:43,395 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSIR [2022-02-20 23:00:43,395 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_speed [2022-02-20 23:00:43,395 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_speed [2022-02-20 23:00:43,396 INFO L130 BoogieDeclarations]: Found specification of procedure netif_stop_queue [2022-02-20 23:00:43,396 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_stop_queue [2022-02-20 23:00:43,396 INFO L130 BoogieDeclarations]: Found specification of procedure SetMaxRxPacketSize [2022-02-20 23:00:43,396 INFO L138 BoogieDeclarations]: Found implementation of procedure SetMaxRxPacketSize [2022-02-20 23:00:43,396 INFO L130 BoogieDeclarations]: Found specification of procedure spinlock_check [2022-02-20 23:00:43,396 INFO L138 BoogieDeclarations]: Found implementation of procedure spinlock_check [2022-02-20 23:00:43,396 INFO L130 BoogieDeclarations]: Found specification of procedure GetRecvByte [2022-02-20 23:00:43,397 INFO L138 BoogieDeclarations]: Found implementation of procedure GetRecvByte [2022-02-20 23:00:43,397 INFO L130 BoogieDeclarations]: Found specification of procedure dma_zalloc_coherent [2022-02-20 23:00:43,397 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_zalloc_coherent [2022-02-20 23:00:43,397 INFO L130 BoogieDeclarations]: Found specification of procedure consume_skb [2022-02-20 23:00:43,397 INFO L138 BoogieDeclarations]: Found implementation of procedure consume_skb [2022-02-20 23:00:43,397 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 23:00:43,397 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 23:00:43,398 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_xmalloc [2022-02-20 23:00:43,398 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_xmalloc [2022-02-20 23:00:43,398 INFO L130 BoogieDeclarations]: Found specification of procedure SetPulseWidth [2022-02-20 23:00:43,398 INFO L138 BoogieDeclarations]: Found implementation of procedure SetPulseWidth [2022-02-20 23:00:43,398 INFO L130 BoogieDeclarations]: Found specification of procedure Tdelay [2022-02-20 23:00:43,399 INFO L138 BoogieDeclarations]: Found implementation of procedure Tdelay [2022-02-20 23:00:43,399 INFO L130 BoogieDeclarations]: Found specification of procedure netif_rx [2022-02-20 23:00:43,399 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_rx [2022-02-20 23:00:43,400 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_is_err [2022-02-20 23:00:43,400 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_is_err [2022-02-20 23:00:43,400 INFO L130 BoogieDeclarations]: Found specification of procedure hwreset [2022-02-20 23:00:43,400 INFO L138 BoogieDeclarations]: Found implementation of procedure hwreset [2022-02-20 23:00:43,400 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2022-02-20 23:00:43,400 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2022-02-20 23:00:43,401 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 23:00:43,401 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 23:00:43,401 INFO L130 BoogieDeclarations]: Found specification of procedure ClkTx [2022-02-20 23:00:43,401 INFO L138 BoogieDeclarations]: Found implementation of procedure ClkTx [2022-02-20 23:00:43,401 INFO L130 BoogieDeclarations]: Found specification of procedure WriteLPCReg [2022-02-20 23:00:43,401 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteLPCReg [2022-02-20 23:00:43,402 INFO L130 BoogieDeclarations]: Found specification of procedure capable [2022-02-20 23:00:43,402 INFO L138 BoogieDeclarations]: Found implementation of procedure capable [2022-02-20 23:00:43,402 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 23:00:43,402 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~~structbegin~int~structend~~TO~int [2022-02-20 23:00:43,402 INFO L130 BoogieDeclarations]: Found specification of procedure pci_write_config_byte [2022-02-20 23:00:43,402 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_write_config_byte [2022-02-20 23:00:43,402 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_lock_irqsave [2022-02-20 23:00:43,402 INFO L138 BoogieDeclarations]: Found implementation of procedure _raw_spin_lock_irqsave [2022-02-20 23:00:43,402 INFO L130 BoogieDeclarations]: Found specification of procedure CommonInit [2022-02-20 23:00:43,403 INFO L138 BoogieDeclarations]: Found implementation of procedure CommonInit [2022-02-20 23:00:43,403 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_priv [2022-02-20 23:00:43,403 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_priv [2022-02-20 23:00:43,403 INFO L130 BoogieDeclarations]: Found specification of procedure outb [2022-02-20 23:00:43,403 INFO L138 BoogieDeclarations]: Found implementation of procedure outb [2022-02-20 23:00:43,403 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_get_tx_queue [2022-02-20 23:00:43,403 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_get_tx_queue [2022-02-20 23:00:43,403 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_positive_int [2022-02-20 23:00:43,403 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_positive_int [2022-02-20 23:00:43,404 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq [2022-02-20 23:00:43,404 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq [2022-02-20 23:00:43,404 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_dongle_speed [2022-02-20 23:00:43,404 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_dongle_speed [2022-02-20 23:00:43,404 INFO L130 BoogieDeclarations]: Found specification of procedure ReadLPCReg [2022-02-20 23:00:43,405 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadLPCReg [2022-02-20 23:00:43,405 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2022-02-20 23:00:43,405 INFO L130 BoogieDeclarations]: Found specification of procedure free_dma [2022-02-20 23:00:43,405 INFO L138 BoogieDeclarations]: Found implementation of procedure free_dma [2022-02-20 23:00:43,405 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_receive [2022-02-20 23:00:43,405 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_receive [2022-02-20 23:00:43,406 INFO L130 BoogieDeclarations]: Found specification of procedure get_dma_ops [2022-02-20 23:00:43,406 INFO L138 BoogieDeclarations]: Found implementation of procedure get_dma_ops [2022-02-20 23:00:43,406 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2022-02-20 23:00:43,406 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_assume [2022-02-20 23:00:43,406 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_assume [2022-02-20 23:00:43,406 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_xmit [2022-02-20 23:00:43,406 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_xmit [2022-02-20 23:00:43,406 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reserve [2022-02-20 23:00:43,406 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reserve [2022-02-20 23:00:43,407 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_close [2022-02-20 23:00:43,407 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_close [2022-02-20 23:00:43,407 INFO L130 BoogieDeclarations]: Found specification of procedure dma_free_attrs [2022-02-20 23:00:43,407 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_free_attrs [2022-02-20 23:00:43,407 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 23:00:43,407 INFO L130 BoogieDeclarations]: Found specification of procedure netif_tx_start_queue [2022-02-20 23:00:43,407 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_tx_start_queue [2022-02-20 23:00:43,408 INFO L130 BoogieDeclarations]: Found specification of procedure free_netdev [2022-02-20 23:00:43,408 INFO L138 BoogieDeclarations]: Found implementation of procedure free_netdev [2022-02-20 23:00:43,408 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2022-02-20 23:00:43,410 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2022-02-20 23:00:43,410 INFO L130 BoogieDeclarations]: Found specification of procedure CkRxRecv [2022-02-20 23:00:43,411 INFO L138 BoogieDeclarations]: Found implementation of procedure CkRxRecv [2022-02-20 23:00:43,411 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2022-02-20 23:00:43,411 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2022-02-20 23:00:43,412 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_filter_err_code [2022-02-20 23:00:43,412 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_filter_err_code [2022-02-20 23:00:43,412 INFO L130 BoogieDeclarations]: Found specification of procedure irda_get_next_speed [2022-02-20 23:00:43,412 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_get_next_speed [2022-02-20 23:00:43,417 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2022-02-20 23:00:43,417 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2022-02-20 23:00:43,417 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 23:00:43,417 INFO L130 BoogieDeclarations]: Found specification of procedure net_ratelimit [2022-02-20 23:00:43,417 INFO L138 BoogieDeclarations]: Found implementation of procedure net_ratelimit [2022-02-20 23:00:43,418 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendByte [2022-02-20 23:00:43,418 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendByte [2022-02-20 23:00:43,418 INFO L130 BoogieDeclarations]: Found specification of procedure dev_alloc_skb [2022-02-20 23:00:43,418 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_alloc_skb [2022-02-20 23:00:43,418 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2022-02-20 23:00:43,418 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2022-02-20 23:00:43,418 INFO L130 BoogieDeclarations]: Found specification of procedure ReadReg [2022-02-20 23:00:43,418 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadReg [2022-02-20 23:00:43,418 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_open [2022-02-20 23:00:43,418 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_open [2022-02-20 23:00:43,419 INFO L130 BoogieDeclarations]: Found specification of procedure WriteRegBit [2022-02-20 23:00:43,419 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteRegBit [2022-02-20 23:00:43,419 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 23:00:43,419 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Indx [2022-02-20 23:00:43,419 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Indx [2022-02-20 23:00:43,419 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 23:00:43,419 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_int [2022-02-20 23:00:43,419 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_int [2022-02-20 23:00:43,419 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2022-02-20 23:00:43,420 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2022-02-20 23:00:43,420 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-02-20 23:00:43,420 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 23:00:43,420 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2022-02-20 23:00:43,420 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~int [2022-02-20 23:00:43,420 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~int [2022-02-20 23:00:43,420 INFO L130 BoogieDeclarations]: Found specification of procedure WriteReg [2022-02-20 23:00:43,420 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteReg [2022-02-20 23:00:43,420 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendPreambleCount [2022-02-20 23:00:43,420 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendPreambleCount [2022-02-20 23:00:43,421 INFO L130 BoogieDeclarations]: Found specification of procedure InitCard [2022-02-20 23:00:43,421 INFO L138 BoogieDeclarations]: Found implementation of procedure InitCard [2022-02-20 23:00:43,421 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free [2022-02-20 23:00:43,421 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free [2022-02-20 23:00:43,421 INFO L130 BoogieDeclarations]: Found specification of procedure SetTimer [2022-02-20 23:00:43,421 INFO L138 BoogieDeclarations]: Found implementation of procedure SetTimer [2022-02-20 23:00:43,421 INFO L130 BoogieDeclarations]: Found specification of procedure ActClk [2022-02-20 23:00:43,421 INFO L138 BoogieDeclarations]: Found implementation of procedure ActClk [2022-02-20 23:00:43,421 INFO L130 BoogieDeclarations]: Found specification of procedure warn_slowpath_null [2022-02-20 23:00:43,421 INFO L138 BoogieDeclarations]: Found implementation of procedure warn_slowpath_null [2022-02-20 23:00:43,422 INFO L130 BoogieDeclarations]: Found specification of procedure SetBaudRate [2022-02-20 23:00:43,422 INFO L138 BoogieDeclarations]: Found implementation of procedure SetBaudRate [2022-02-20 23:00:43,422 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Byte [2022-02-20 23:00:43,422 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Byte [2022-02-20 23:00:43,422 INFO L130 BoogieDeclarations]: Found specification of procedure skb_put [2022-02-20 23:00:43,422 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_put [2022-02-20 23:00:43,422 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_netdev [2022-02-20 23:00:43,422 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_netdev [2022-02-20 23:00:43,422 INFO L130 BoogieDeclarations]: Found specification of procedure request_dma [2022-02-20 23:00:43,422 INFO L138 BoogieDeclarations]: Found implementation of procedure request_dma [2022-02-20 23:00:43,423 INFO L130 BoogieDeclarations]: Found specification of procedure inb [2022-02-20 23:00:43,423 INFO L138 BoogieDeclarations]: Found implementation of procedure inb [2022-02-20 23:00:43,423 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 23:00:43,423 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reset_mac_header [2022-02-20 23:00:43,423 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reset_mac_header [2022-02-20 23:00:43,423 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_open [2022-02-20 23:00:43,423 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_open [2022-02-20 23:00:43,423 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2022-02-20 23:00:43,423 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_final_state [2022-02-20 23:00:43,424 INFO L130 BoogieDeclarations]: Found specification of procedure skb_copy_to_linear_data [2022-02-20 23:00:43,424 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_copy_to_linear_data [2022-02-20 23:00:43,424 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 23:00:43,424 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 23:00:43,988 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 23:00:43,990 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 23:00:44,244 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 23:00:47,652 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 23:00:47,687 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 23:00:47,687 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-02-20 23:00:47,691 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 11:00:47 BoogieIcfgContainer [2022-02-20 23:00:47,691 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 23:00:47,693 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 23:00:47,693 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 23:00:47,698 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 23:00:47,699 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 11:00:40" (1/3) ... [2022-02-20 23:00:47,699 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7ae9f619 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 11:00:47, skipping insertion in model container [2022-02-20 23:00:47,700 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 11:00:42" (2/3) ... [2022-02-20 23:00:47,700 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7ae9f619 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 11:00:47, skipping insertion in model container [2022-02-20 23:00:47,700 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 11:00:47" (3/3) ... [2022-02-20 23:00:47,701 INFO L111 eAbstractionObserver]: Analyzing ICFG linux-3.14_linux-usb-dev_drivers-net-irda-via-ircc.cil.i [2022-02-20 23:00:47,708 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 23:00:47,709 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 2 error locations. [2022-02-20 23:00:47,746 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 23:00:47,750 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 23:00:47,750 INFO L340 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2022-02-20 23:00:47,835 INFO L276 IsEmpty]: Start isEmpty. Operand has 1867 states, 1163 states have (on average 1.300085984522786) internal successors, (1512), 1195 states have internal predecessors, (1512), 615 states have call successors, (615), 87 states have call predecessors, (615), 86 states have return successors, (612), 600 states have call predecessors, (612), 612 states have call successors, (612) [2022-02-20 23:00:47,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2022-02-20 23:00:47,842 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 23:00:47,843 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 23:00:47,843 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_check_final_stateErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_check_final_stateErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 23:00:47,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 23:00:47,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1721609146, now seen corresponding path program 1 times [2022-02-20 23:00:47,856 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 23:00:47,857 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004235479] [2022-02-20 23:00:47,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 23:00:47,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 23:00:48,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:00:48,368 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 23:00:48,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:00:48,395 INFO L290 TraceCheckUtils]: 0: Hoare triple {1870#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet965 && #t~nondet965 <= 2147483647;~tmp~80 := #t~nondet965;havoc #t~nondet965;#res := ~tmp~80; {1870#true} is VALID [2022-02-20 23:00:48,395 INFO L290 TraceCheckUtils]: 1: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,396 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4619#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,397 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 12 [2022-02-20 23:00:48,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:00:48,405 INFO L290 TraceCheckUtils]: 0: Hoare triple {1870#true} ~expression := #in~expression; {1870#true} is VALID [2022-02-20 23:00:48,405 INFO L290 TraceCheckUtils]: 1: Hoare triple {1870#true} assume !(0 == ~expression); {1870#true} is VALID [2022-02-20 23:00:48,406 INFO L290 TraceCheckUtils]: 2: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,406 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4731#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,406 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2022-02-20 23:00:48,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:00:48,415 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:00:48,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:00:48,421 INFO L290 TraceCheckUtils]: 0: Hoare triple {1870#true} ~expression := #in~expression; {1870#true} is VALID [2022-02-20 23:00:48,421 INFO L290 TraceCheckUtils]: 1: Hoare triple {1870#true} assume !(0 == ~expression); {1870#true} is VALID [2022-02-20 23:00:48,421 INFO L290 TraceCheckUtils]: 2: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,422 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1870#true} {1870#true} #4191#return; {1870#true} is VALID [2022-02-20 23:00:48,422 INFO L290 TraceCheckUtils]: 0: Hoare triple {1870#true} ~val := #in~val; {1870#true} is VALID [2022-02-20 23:00:48,422 INFO L272 TraceCheckUtils]: 1: Hoare triple {1870#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1870#true} is VALID [2022-02-20 23:00:48,422 INFO L290 TraceCheckUtils]: 2: Hoare triple {1870#true} ~expression := #in~expression; {1870#true} is VALID [2022-02-20 23:00:48,422 INFO L290 TraceCheckUtils]: 3: Hoare triple {1870#true} assume !(0 == ~expression); {1870#true} is VALID [2022-02-20 23:00:48,423 INFO L290 TraceCheckUtils]: 4: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,423 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {1870#true} {1870#true} #4191#return; {1870#true} is VALID [2022-02-20 23:00:48,423 INFO L290 TraceCheckUtils]: 6: Hoare triple {1870#true} #res := ~val; {1870#true} is VALID [2022-02-20 23:00:48,423 INFO L290 TraceCheckUtils]: 7: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,424 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4733#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,424 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2022-02-20 23:00:48,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:00:48,432 INFO L290 TraceCheckUtils]: 0: Hoare triple {1870#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet965 && #t~nondet965 <= 2147483647;~tmp~80 := #t~nondet965;havoc #t~nondet965;#res := ~tmp~80; {1870#true} is VALID [2022-02-20 23:00:48,432 INFO L290 TraceCheckUtils]: 1: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,433 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4735#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,433 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 41 [2022-02-20 23:00:48,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:00:48,444 INFO L290 TraceCheckUtils]: 0: Hoare triple {1870#true} ~expression := #in~expression; {1870#true} is VALID [2022-02-20 23:00:48,445 INFO L290 TraceCheckUtils]: 1: Hoare triple {1870#true} assume !(0 == ~expression); {1870#true} is VALID [2022-02-20 23:00:48,445 INFO L290 TraceCheckUtils]: 2: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,446 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4737#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,448 INFO L290 TraceCheckUtils]: 0: Hoare triple {1870#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(183, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(9, 4);call #Ultimate.allocInit(9, 5);call #Ultimate.allocInit(7, 6);call write~init~int(15, 6, 0, 1);call write~init~int(37, 6, 1, 1);call write~init~int(115, 6, 2, 1);call write~init~int(40, 6, 3, 1);call write~init~int(41, 6, 4, 1);call write~init~int(10, 6, 5, 1);call write~init~int(0, 6, 6, 1);call #Ultimate.allocInit(14, 7);call #Ultimate.allocInit(9, 8);call #Ultimate.allocInit(45, 9);call #Ultimate.allocInit(14, 10);call #Ultimate.allocInit(25, 11);call #Ultimate.allocInit(13, 12);call #Ultimate.allocInit(22, 13);call #Ultimate.allocInit(13, 14);call #Ultimate.allocInit(23, 15);call #Ultimate.allocInit(13, 16);call #Ultimate.allocInit(23, 17);call #Ultimate.allocInit(13, 18);call #Ultimate.allocInit(22, 19);call #Ultimate.allocInit(13, 20);call #Ultimate.allocInit(7, 21);call write~init~int(15, 21, 0, 1);call write~init~int(37, 21, 1, 1);call write~init~int(115, 21, 2, 1);call write~init~int(40, 21, 3, 1);call write~init~int(41, 21, 4, 1);call write~init~int(10, 21, 5, 1);call write~init~int(0, 21, 6, 1);call #Ultimate.allocInit(17, 22);call #Ultimate.allocInit(7, 23);call write~init~int(15, 23, 0, 1);call write~init~int(37, 23, 1, 1);call write~init~int(115, 23, 2, 1);call write~init~int(40, 23, 3, 1);call write~init~int(41, 23, 4, 1);call write~init~int(10, 23, 5, 1);call write~init~int(0, 23, 6, 1);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(22, 25);call #Ultimate.allocInit(35, 26);call #Ultimate.allocInit(14, 27);call #Ultimate.allocInit(40, 28);call #Ultimate.allocInit(7, 29);call write~init~int(15, 29, 0, 1);call write~init~int(37, 29, 1, 1);call write~init~int(115, 29, 2, 1);call write~init~int(40, 29, 3, 1);call write~init~int(41, 29, 4, 1);call write~init~int(10, 29, 5, 1);call write~init~int(0, 29, 6, 1);call #Ultimate.allocInit(15, 30);call #Ultimate.allocInit(30, 31);call #Ultimate.allocInit(15, 32);call #Ultimate.allocInit(7, 33);call write~init~int(15, 33, 0, 1);call write~init~int(37, 33, 1, 1);call write~init~int(115, 33, 2, 1);call write~init~int(40, 33, 3, 1);call write~init~int(41, 33, 4, 1);call write~init~int(10, 33, 5, 1);call write~init~int(0, 33, 6, 1);call #Ultimate.allocInit(12, 34);call #Ultimate.allocInit(85, 35);call #Ultimate.allocInit(47, 36);call #Ultimate.allocInit(29, 37);call #Ultimate.allocInit(58, 38);call #Ultimate.allocInit(29, 39);call #Ultimate.allocInit(50, 40);call #Ultimate.allocInit(29, 41);call #Ultimate.allocInit(40, 42);call #Ultimate.allocInit(29, 43);call #Ultimate.allocInit(30, 44);call #Ultimate.allocInit(22, 45);call #Ultimate.allocInit(31, 46);call #Ultimate.allocInit(28, 47);call #Ultimate.allocInit(23, 48);call #Ultimate.allocInit(13, 49);call #Ultimate.allocInit(45, 50);call #Ultimate.allocInit(18, 51);call #Ultimate.allocInit(7, 52);call write~init~int(15, 52, 0, 1);call write~init~int(37, 52, 1, 1);call write~init~int(115, 52, 2, 1);call write~init~int(40, 52, 3, 1);call write~init~int(41, 52, 4, 1);call write~init~int(10, 52, 5, 1);call write~init~int(0, 52, 6, 1);call #Ultimate.allocInit(27, 53);call #Ultimate.allocInit(56, 54);call #Ultimate.allocInit(27, 55);call #Ultimate.allocInit(7, 56);call write~init~int(15, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(40, 56, 3, 1);call write~init~int(41, 56, 4, 1);call write~init~int(10, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(21, 57);call #Ultimate.allocInit(50, 58);call #Ultimate.allocInit(30, 59);call #Ultimate.allocInit(41, 60);call #Ultimate.allocInit(30, 61);call #Ultimate.allocInit(26, 62);call #Ultimate.allocInit(30, 63);call #Ultimate.allocInit(15, 64);call #Ultimate.allocInit(14, 65);call #Ultimate.allocInit(23, 66);call #Ultimate.allocInit(15, 67);call #Ultimate.allocInit(48, 68);call #Ultimate.allocInit(15, 69);call #Ultimate.allocInit(43, 70);call #Ultimate.allocInit(19, 71);call #Ultimate.allocInit(6, 72);call write~init~int(84, 72, 0, 1);call write~init~int(105, 72, 1, 1);call write~init~int(109, 72, 2, 1);call write~init~int(101, 72, 3, 1);call write~init~int(114, 72, 4, 1);call write~init~int(0, 72, 5, 1);call #Ultimate.allocInit(1, 73);call write~init~int(0, 73, 0, 1);call #Ultimate.allocInit(3, 74);call write~init~int(84, 74, 0, 1);call write~init~int(120, 74, 1, 1);call write~init~int(0, 74, 2, 1);call #Ultimate.allocInit(1, 75);call write~init~int(0, 75, 0, 1);call #Ultimate.allocInit(3, 76);call write~init~int(82, 76, 0, 1);call write~init~int(120, 76, 1, 1);call write~init~int(0, 76, 2, 1);call #Ultimate.allocInit(1, 77);call write~init~int(0, 77, 0, 1);call #Ultimate.allocInit(38, 78);call #Ultimate.allocInit(19, 79);call #Ultimate.allocInit(13, 80);call #Ultimate.allocInit(1, 81);call write~init~int(0, 81, 0, 1);call #Ultimate.allocInit(4, 82);call write~init~int(69, 82, 0, 1);call write~init~int(79, 82, 1, 1);call write~init~int(77, 82, 2, 1);call write~init~int(0, 82, 3, 1);call #Ultimate.allocInit(1, 83);call write~init~int(0, 83, 0, 1);call #Ultimate.allocInit(11, 84);call #Ultimate.allocInit(1, 85);call write~init~int(0, 85, 0, 1);call #Ultimate.allocInit(10, 86);call #Ultimate.allocInit(1, 87);call write~init~int(0, 87, 0, 1);call #Ultimate.allocInit(47, 88);call #Ultimate.allocInit(19, 89);call #Ultimate.allocInit(9, 90);call #Ultimate.allocInit(1, 91);call write~init~int(0, 91, 0, 1);call #Ultimate.allocInit(8, 92);call #Ultimate.allocInit(1, 93);call write~init~int(0, 93, 0, 1);call #Ultimate.allocInit(12, 94);call #Ultimate.allocInit(1, 95);call write~init~int(0, 95, 0, 1);call #Ultimate.allocInit(4, 96);call write~init~int(69, 96, 0, 1);call write~init~int(79, 96, 1, 1);call write~init~int(70, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(1, 97);call write~init~int(0, 97, 0, 1);call #Ultimate.allocInit(7, 98);call write~init~int(82, 98, 0, 1);call write~init~int(120, 98, 1, 1);call write~init~int(68, 98, 2, 1);call write~init~int(97, 98, 3, 1);call write~init~int(116, 98, 4, 1);call write~init~int(97, 98, 5, 1);call write~init~int(0, 98, 6, 1);call #Ultimate.allocInit(1, 99);call write~init~int(0, 99, 0, 1);call #Ultimate.allocInit(9, 100);call #Ultimate.allocInit(1, 101);call write~init~int(0, 101, 0, 1);call #Ultimate.allocInit(8, 102);call #Ultimate.allocInit(1, 103);call write~init~int(0, 103, 0, 1);call #Ultimate.allocInit(17, 104);call #Ultimate.allocInit(19, 105);call #Ultimate.allocInit(79, 106);call #Ultimate.allocInit(19, 107);call #Ultimate.allocInit(7, 108);call write~init~int(15, 108, 0, 1);call write~init~int(37, 108, 1, 1);call write~init~int(115, 108, 2, 1);call write~init~int(40, 108, 3, 1);call write~init~int(41, 108, 4, 1);call write~init~int(10, 108, 5, 1);call write~init~int(0, 108, 6, 1);call #Ultimate.allocInit(8, 109);call #Ultimate.allocInit(31, 110);call #Ultimate.allocInit(28, 111);call #Ultimate.allocInit(22, 112);call #Ultimate.allocInit(13, 113);call #Ultimate.allocInit(22, 114);call #Ultimate.allocInit(22, 115);call #Ultimate.allocInit(7, 116);call write~init~int(15, 116, 0, 1);call write~init~int(37, 116, 1, 1);call write~init~int(115, 116, 2, 1);call write~init~int(40, 116, 3, 1);call write~init~int(41, 116, 4, 1);call write~init~int(10, 116, 5, 1);call write~init~int(0, 116, 6, 1);call #Ultimate.allocInit(18, 117);call #Ultimate.allocInit(31, 118);call #Ultimate.allocInit(28, 119);call #Ultimate.allocInit(18, 120);call #Ultimate.allocInit(12, 121);call #Ultimate.allocInit(31, 122);call #Ultimate.allocInit(28, 123);call #Ultimate.allocInit(18, 124);call #Ultimate.allocInit(13, 125);call #Ultimate.allocInit(32, 126);call #Ultimate.allocInit(32, 127);call #Ultimate.allocInit(33, 128);call #Ultimate.allocInit(11, 129);call #Ultimate.allocInit(7, 130);call write~init~int(15, 130, 0, 1);call write~init~int(37, 130, 1, 1);call write~init~int(115, 130, 2, 1);call write~init~int(40, 130, 3, 1);call write~init~int(41, 130, 4, 1);call write~init~int(10, 130, 5, 1);call write~init~int(0, 130, 6, 1);call #Ultimate.allocInit(19, 131);call #Ultimate.allocInit(31, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(19, 134);call #Ultimate.allocInit(12, 135);call #Ultimate.allocInit(31, 136);call #Ultimate.allocInit(28, 137);call #Ultimate.allocInit(19, 138);call #Ultimate.allocInit(13, 139);call #Ultimate.allocInit(31, 140);call #Ultimate.allocInit(28, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(12, 143);call #Ultimate.allocInit(31, 144);call #Ultimate.allocInit(28, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(13, 147);call #Ultimate.allocInit(23, 148);call #Ultimate.allocInit(19, 149);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(2, 151);call write~init~int(48, 151, 0, 1);call write~init~int(0, 151, 1, 1);call #Ultimate.allocInit(57, 152);~driver_name~0.base, ~driver_name~0.offset := 4, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 153, 0;call #Ultimate.allocInit(192, 153);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#via_driver~0.base, ~#via_driver~0.offset := 154, 0;call #Ultimate.allocInit(301, 154);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(5, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 145 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 153 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 161 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 169 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 177 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 185 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 193 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 201 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 209 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 217 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 237 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 245 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 253 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 261 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 269 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 285 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 293 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 155, 0;call #Ultimate.allocInit(472, 155);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 156, 0;call #Ultimate.allocInit(472, 156);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_thread_0~0.identifier := 0;~ldv_thread_0~0.function.base, ~ldv_thread_0~0.function.offset := 0, 0;~ldv_thread_1~0.identifier := 0;~ldv_thread_1~0.function.base, ~ldv_thread_1~0.function.offset := 0, 0;~ldv_thread_10~0.identifier := 0;~ldv_thread_10~0.function.base, ~ldv_thread_10~0.function.offset := 0, 0;~ldv_thread_2~0.identifier := 0;~ldv_thread_2~0.function.base, ~ldv_thread_2~0.function.offset := 0, 0;~LDV_USB_DEV_REF_COUNTS~0 := 0; {1870#true} is VALID [2022-02-20 23:00:48,449 INFO L290 TraceCheckUtils]: 1: Hoare triple {1870#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_ldv_initialize } true;~LDV_USB_DEV_REF_COUNTS~0 := 0; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,449 INFO L290 TraceCheckUtils]: 2: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_entry_EMGentry_10 } true;ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset := 0, 0;havoc ldv_entry_EMGentry_10_#t~ret837#1, ldv_entry_EMGentry_10_#t~ret838#1, ldv_entry_EMGentry_10_#t~ret839#1, ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1, ldv_entry_EMGentry_10_~tmp~52#1;ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset := ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_entry_EMGentry_10_~tmp~52#1;assume { :begin_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset := ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_#res#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret830#1, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset, ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset := ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;assume { :begin_inline_via_ircc_init } true;havoc via_ircc_init_#res#1;havoc via_ircc_init_#t~nondet244#1, via_ircc_init_#t~ret245#1, via_ircc_init_#t~nondet246#1, via_ircc_init_~rc~0#1;havoc via_ircc_init_~rc~0#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,450 INFO L290 TraceCheckUtils]: 3: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume ~irda_debug~0 % 4294967296 > 2;havoc via_ircc_init_#t~nondet244#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,450 INFO L290 TraceCheckUtils]: 4: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume { :begin_inline_ldv___pci_register_driver_18 } true;ldv___pci_register_driver_18_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg1#1.offset, ldv___pci_register_driver_18_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg2#1.offset, ldv___pci_register_driver_18_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg3#1.offset := ~#via_driver~0.base, ~#via_driver~0.offset, ~#__this_module~0.base, ~#__this_module~0.offset, 8, 0;havoc ldv___pci_register_driver_18_#res#1;havoc ldv___pci_register_driver_18_#t~ret906#1, ldv___pci_register_driver_18_#t~ret907#1, ldv___pci_register_driver_18_~ldv_func_arg1#1.base, ldv___pci_register_driver_18_~ldv_func_arg1#1.offset, ldv___pci_register_driver_18_~ldv_func_arg2#1.base, ldv___pci_register_driver_18_~ldv_func_arg2#1.offset, ldv___pci_register_driver_18_~ldv_func_arg3#1.base, ldv___pci_register_driver_18_~ldv_func_arg3#1.offset, ldv___pci_register_driver_18_~ldv_func_res~0#1, ldv___pci_register_driver_18_~tmp~65#1, ldv___pci_register_driver_18_~tmp___0~22#1;ldv___pci_register_driver_18_~ldv_func_arg1#1.base, ldv___pci_register_driver_18_~ldv_func_arg1#1.offset := ldv___pci_register_driver_18_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg1#1.offset;ldv___pci_register_driver_18_~ldv_func_arg2#1.base, ldv___pci_register_driver_18_~ldv_func_arg2#1.offset := ldv___pci_register_driver_18_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg2#1.offset;ldv___pci_register_driver_18_~ldv_func_arg3#1.base, ldv___pci_register_driver_18_~ldv_func_arg3#1.offset := ldv___pci_register_driver_18_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_18_~ldv_func_res~0#1;havoc ldv___pci_register_driver_18_~tmp~65#1;havoc ldv___pci_register_driver_18_~tmp___0~22#1;assume { :begin_inline___pci_register_driver } true;__pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset, __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset, __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset := ldv___pci_register_driver_18_~ldv_func_arg1#1.base, ldv___pci_register_driver_18_~ldv_func_arg1#1.offset, ldv___pci_register_driver_18_~ldv_func_arg2#1.base, ldv___pci_register_driver_18_~ldv_func_arg2#1.offset, ldv___pci_register_driver_18_~ldv_func_arg3#1.base, ldv___pci_register_driver_18_~ldv_func_arg3#1.offset;havoc __pci_register_driver_#res#1;havoc __pci_register_driver_#t~nondet976#1, __pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset, __pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset, __pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset;__pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset := __pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset;__pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset := __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset;__pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset := __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset;assume -2147483648 <= __pci_register_driver_#t~nondet976#1 && __pci_register_driver_#t~nondet976#1 <= 2147483647;__pci_register_driver_#res#1 := __pci_register_driver_#t~nondet976#1;havoc __pci_register_driver_#t~nondet976#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,451 INFO L290 TraceCheckUtils]: 5: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} ldv___pci_register_driver_18_#t~ret906#1 := __pci_register_driver_#res#1;assume { :end_inline___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_18_#t~ret906#1 && ldv___pci_register_driver_18_#t~ret906#1 <= 2147483647;ldv___pci_register_driver_18_~tmp~65#1 := ldv___pci_register_driver_18_#t~ret906#1;havoc ldv___pci_register_driver_18_#t~ret906#1;ldv___pci_register_driver_18_~ldv_func_res~0#1 := ldv___pci_register_driver_18_~tmp~65#1;assume { :begin_inline_ldv___pci_register_driver } true;ldv___pci_register_driver_#in~arg0#1, ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset, ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset, ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset := ldv___pci_register_driver_18_~ldv_func_res~0#1, ldv___pci_register_driver_18_~ldv_func_arg1#1.base, ldv___pci_register_driver_18_~ldv_func_arg1#1.offset, ldv___pci_register_driver_18_~ldv_func_arg2#1.base, ldv___pci_register_driver_18_~ldv_func_arg2#1.offset, ldv___pci_register_driver_18_~ldv_func_arg3#1.base, ldv___pci_register_driver_18_~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_#res#1;havoc ldv___pci_register_driver_#t~ret831#1, ldv___pci_register_driver_~arg0#1, ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset, ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset, ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset, ldv___pci_register_driver_~tmp~48#1;ldv___pci_register_driver_~arg0#1 := ldv___pci_register_driver_#in~arg0#1;ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset := ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset;ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset := ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset;ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset := ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset;havoc ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset;havoc ldv___pci_register_driver_~tmp~48#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,451 INFO L272 TraceCheckUtils]: 6: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} call ldv___pci_register_driver_#t~ret831#1 := ldv_undef_int(); {1870#true} is VALID [2022-02-20 23:00:48,451 INFO L290 TraceCheckUtils]: 7: Hoare triple {1870#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet965 && #t~nondet965 <= 2147483647;~tmp~80 := #t~nondet965;havoc #t~nondet965;#res := ~tmp~80; {1870#true} is VALID [2022-02-20 23:00:48,451 INFO L290 TraceCheckUtils]: 8: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,452 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4619#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,452 INFO L290 TraceCheckUtils]: 10: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume -2147483648 <= ldv___pci_register_driver_#t~ret831#1 && ldv___pci_register_driver_#t~ret831#1 <= 2147483647;ldv___pci_register_driver_~tmp~48#1 := ldv___pci_register_driver_#t~ret831#1;havoc ldv___pci_register_driver_#t~ret831#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,453 INFO L290 TraceCheckUtils]: 11: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume !(0 != ldv___pci_register_driver_~tmp~48#1); {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,453 INFO L272 TraceCheckUtils]: 12: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} call ldv_assume((if 0 != ldv___pci_register_driver_~arg0#1 then 1 else 0)); {1870#true} is VALID [2022-02-20 23:00:48,453 INFO L290 TraceCheckUtils]: 13: Hoare triple {1870#true} ~expression := #in~expression; {1870#true} is VALID [2022-02-20 23:00:48,453 INFO L290 TraceCheckUtils]: 14: Hoare triple {1870#true} assume !(0 == ~expression); {1870#true} is VALID [2022-02-20 23:00:48,454 INFO L290 TraceCheckUtils]: 15: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,454 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4731#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,455 INFO L290 TraceCheckUtils]: 17: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} ldv___pci_register_driver_#res#1 := ldv___pci_register_driver_~arg0#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,455 INFO L290 TraceCheckUtils]: 18: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} ldv___pci_register_driver_18_#t~ret907#1 := ldv___pci_register_driver_#res#1;assume { :end_inline_ldv___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_18_#t~ret907#1 && ldv___pci_register_driver_18_#t~ret907#1 <= 2147483647;ldv___pci_register_driver_18_~tmp___0~22#1 := ldv___pci_register_driver_18_#t~ret907#1;havoc ldv___pci_register_driver_18_#t~ret907#1;ldv___pci_register_driver_18_#res#1 := ldv___pci_register_driver_18_~tmp___0~22#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,455 INFO L290 TraceCheckUtils]: 19: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} via_ircc_init_#t~ret245#1 := ldv___pci_register_driver_18_#res#1;assume { :end_inline_ldv___pci_register_driver_18 } true;assume -2147483648 <= via_ircc_init_#t~ret245#1 && via_ircc_init_#t~ret245#1 <= 2147483647;via_ircc_init_~rc~0#1 := via_ircc_init_#t~ret245#1;havoc via_ircc_init_#t~ret245#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,456 INFO L290 TraceCheckUtils]: 20: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume via_ircc_init_~rc~0#1 < 0;havoc via_ircc_init_#t~nondet246#1;via_ircc_init_#res#1 := -19; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,456 INFO L290 TraceCheckUtils]: 21: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} ldv_EMGentry_init_via_ircc_init_10_7_#t~ret830#1 := via_ircc_init_#res#1;assume { :end_inline_via_ircc_init } true;assume -2147483648 <= ldv_EMGentry_init_via_ircc_init_10_7_#t~ret830#1 && ldv_EMGentry_init_via_ircc_init_10_7_#t~ret830#1 <= 2147483647;ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1 := ldv_EMGentry_init_via_ircc_init_10_7_#t~ret830#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret830#1;ldv_EMGentry_init_via_ircc_init_10_7_#res#1 := ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,457 INFO L290 TraceCheckUtils]: 22: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} ldv_entry_EMGentry_10_#t~ret837#1 := ldv_EMGentry_init_via_ircc_init_10_7_#res#1;assume { :end_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret837#1 && ldv_entry_EMGentry_10_#t~ret837#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret837#1;havoc ldv_entry_EMGentry_10_#t~ret837#1;assume { :begin_inline_ldv_post_init } true;ldv_post_init_#in~init_ret_val#1 := ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_post_init_#res#1;havoc ldv_post_init_#t~ret938#1, ldv_post_init_~init_ret_val#1, ldv_post_init_~tmp~72#1;ldv_post_init_~init_ret_val#1 := ldv_post_init_#in~init_ret_val#1;havoc ldv_post_init_~tmp~72#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,457 INFO L272 TraceCheckUtils]: 23: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} call ldv_post_init_#t~ret938#1 := ldv_filter_positive_int(ldv_post_init_~init_ret_val#1); {1870#true} is VALID [2022-02-20 23:00:48,457 INFO L290 TraceCheckUtils]: 24: Hoare triple {1870#true} ~val := #in~val; {1870#true} is VALID [2022-02-20 23:00:48,457 INFO L272 TraceCheckUtils]: 25: Hoare triple {1870#true} call ldv_assume((if ~val <= 0 then 1 else 0)); {1870#true} is VALID [2022-02-20 23:00:48,458 INFO L290 TraceCheckUtils]: 26: Hoare triple {1870#true} ~expression := #in~expression; {1870#true} is VALID [2022-02-20 23:00:48,458 INFO L290 TraceCheckUtils]: 27: Hoare triple {1870#true} assume !(0 == ~expression); {1870#true} is VALID [2022-02-20 23:00:48,458 INFO L290 TraceCheckUtils]: 28: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,458 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {1870#true} {1870#true} #4191#return; {1870#true} is VALID [2022-02-20 23:00:48,458 INFO L290 TraceCheckUtils]: 30: Hoare triple {1870#true} #res := ~val; {1870#true} is VALID [2022-02-20 23:00:48,459 INFO L290 TraceCheckUtils]: 31: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,459 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4733#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,460 INFO L290 TraceCheckUtils]: 33: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume -2147483648 <= ldv_post_init_#t~ret938#1 && ldv_post_init_#t~ret938#1 <= 2147483647;ldv_post_init_~tmp~72#1 := ldv_post_init_#t~ret938#1;havoc ldv_post_init_#t~ret938#1;ldv_post_init_#res#1 := ldv_post_init_~tmp~72#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,460 INFO L290 TraceCheckUtils]: 34: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} ldv_entry_EMGentry_10_#t~ret838#1 := ldv_post_init_#res#1;assume { :end_inline_ldv_post_init } true;assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret838#1 && ldv_entry_EMGentry_10_#t~ret838#1 <= 2147483647;ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 := ldv_entry_EMGentry_10_#t~ret838#1;havoc ldv_entry_EMGentry_10_#t~ret838#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,460 INFO L272 TraceCheckUtils]: 35: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} call ldv_entry_EMGentry_10_#t~ret839#1 := ldv_undef_int(); {1870#true} is VALID [2022-02-20 23:00:48,461 INFO L290 TraceCheckUtils]: 36: Hoare triple {1870#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet965 && #t~nondet965 <= 2147483647;~tmp~80 := #t~nondet965;havoc #t~nondet965;#res := ~tmp~80; {1870#true} is VALID [2022-02-20 23:00:48,461 INFO L290 TraceCheckUtils]: 37: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,461 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4735#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,462 INFO L290 TraceCheckUtils]: 39: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume -2147483648 <= ldv_entry_EMGentry_10_#t~ret839#1 && ldv_entry_EMGentry_10_#t~ret839#1 <= 2147483647;ldv_entry_EMGentry_10_~tmp~52#1 := ldv_entry_EMGentry_10_#t~ret839#1;havoc ldv_entry_EMGentry_10_#t~ret839#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,462 INFO L290 TraceCheckUtils]: 40: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume 0 != ldv_entry_EMGentry_10_~tmp~52#1; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,462 INFO L272 TraceCheckUtils]: 41: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} call ldv_assume((if 0 != ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1 then 1 else 0)); {1870#true} is VALID [2022-02-20 23:00:48,462 INFO L290 TraceCheckUtils]: 42: Hoare triple {1870#true} ~expression := #in~expression; {1870#true} is VALID [2022-02-20 23:00:48,463 INFO L290 TraceCheckUtils]: 43: Hoare triple {1870#true} assume !(0 == ~expression); {1870#true} is VALID [2022-02-20 23:00:48,463 INFO L290 TraceCheckUtils]: 44: Hoare triple {1870#true} assume true; {1870#true} is VALID [2022-02-20 23:00:48,463 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {1870#true} {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} #4737#return; {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,464 INFO L272 TraceCheckUtils]: 46: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} call ldv_check_final_state(); {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} is VALID [2022-02-20 23:00:48,464 INFO L290 TraceCheckUtils]: 47: Hoare triple {1872#(= ~LDV_USB_DEV_REF_COUNTS~0 0)} assume { :begin_inline_ldv_assert_linux_usb_dev__more_initial_at_exit } true;ldv_assert_linux_usb_dev__more_initial_at_exit_#in~expr#1 := (if 0 == ~LDV_USB_DEV_REF_COUNTS~0 then 1 else 0);havoc ldv_assert_linux_usb_dev__more_initial_at_exit_~expr#1;ldv_assert_linux_usb_dev__more_initial_at_exit_~expr#1 := ldv_assert_linux_usb_dev__more_initial_at_exit_#in~expr#1; {1896#(not (= 0 |ldv_check_final_state_ldv_assert_linux_usb_dev__more_initial_at_exit_~expr#1|))} is VALID [2022-02-20 23:00:48,465 INFO L290 TraceCheckUtils]: 48: Hoare triple {1896#(not (= 0 |ldv_check_final_state_ldv_assert_linux_usb_dev__more_initial_at_exit_~expr#1|))} assume 0 == ldv_assert_linux_usb_dev__more_initial_at_exit_~expr#1; {1871#false} is VALID [2022-02-20 23:00:48,465 INFO L290 TraceCheckUtils]: 49: Hoare triple {1871#false} assume !false; {1871#false} is VALID [2022-02-20 23:00:48,466 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2022-02-20 23:00:48,466 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 23:00:48,466 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2004235479] [2022-02-20 23:00:48,467 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2004235479] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 23:00:48,467 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 23:00:48,467 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-20 23:00:48,468 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669951795] [2022-02-20 23:00:48,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 23:00:48,473 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 7.25) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (7), 2 states have call predecessors, (7), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 50 [2022-02-20 23:00:48,474 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 23:00:48,476 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 7.25) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (7), 2 states have call predecessors, (7), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 23:00:48,534 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 42 edges. 42 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 23:00:48,534 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-02-20 23:00:48,534 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 23:00:48,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-20 23:00:48,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-20 23:00:48,557 INFO L87 Difference]: Start difference. First operand has 1867 states, 1163 states have (on average 1.300085984522786) internal successors, (1512), 1195 states have internal predecessors, (1512), 615 states have call successors, (615), 87 states have call predecessors, (615), 86 states have return successors, (612), 600 states have call predecessors, (612), 612 states have call successors, (612) Second operand has 4 states, 4 states have (on average 7.25) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (7), 2 states have call predecessors, (7), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 23:00:56,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 23:00:56,431 INFO L93 Difference]: Finished difference Result 3701 states and 5517 transitions. [2022-02-20 23:00:56,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-20 23:00:56,432 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 7.25) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (7), 2 states have call predecessors, (7), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 50 [2022-02-20 23:00:56,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 23:00:56,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 7.25) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (7), 2 states have call predecessors, (7), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 23:00:56,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 5517 transitions. [2022-02-20 23:00:56,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 7.25) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (7), 2 states have call predecessors, (7), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 23:00:57,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 5517 transitions. [2022-02-20 23:00:57,128 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 4 states and 5517 transitions. [2022-02-20 23:01:01,260 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 5517 edges. 5517 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 23:01:01,646 INFO L225 Difference]: With dead ends: 3701 [2022-02-20 23:01:01,647 INFO L226 Difference]: Without dead ends: 1819 [2022-02-20 23:01:01,663 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-02-20 23:01:01,666 INFO L933 BasicCegarLoop]: 2680 mSDtfsCounter, 2660 mSDsluCounter, 2678 mSDsCounter, 0 mSdLazyCounter, 4 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2662 SdHoareTripleChecker+Valid, 5358 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 4 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-02-20 23:01:01,667 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [2662 Valid, 5358 Invalid, 5 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [1 Valid, 4 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-02-20 23:01:01,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1819 states. [2022-02-20 23:01:01,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1819 to 1819. [2022-02-20 23:01:01,800 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 23:01:01,814 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1819 states. Second operand has 1819 states, 1130 states have (on average 1.2575221238938052) internal successors, (1421), 1159 states have internal predecessors, (1421), 603 states have call successors, (603), 85 states have call predecessors, (603), 85 states have return successors, (603), 591 states have call predecessors, (603), 603 states have call successors, (603) [2022-02-20 23:01:01,820 INFO L74 IsIncluded]: Start isIncluded. First operand 1819 states. Second operand has 1819 states, 1130 states have (on average 1.2575221238938052) internal successors, (1421), 1159 states have internal predecessors, (1421), 603 states have call successors, (603), 85 states have call predecessors, (603), 85 states have return successors, (603), 591 states have call predecessors, (603), 603 states have call successors, (603) [2022-02-20 23:01:01,825 INFO L87 Difference]: Start difference. First operand 1819 states. Second operand has 1819 states, 1130 states have (on average 1.2575221238938052) internal successors, (1421), 1159 states have internal predecessors, (1421), 603 states have call successors, (603), 85 states have call predecessors, (603), 85 states have return successors, (603), 591 states have call predecessors, (603), 603 states have call successors, (603) [2022-02-20 23:01:02,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 23:01:02,006 INFO L93 Difference]: Finished difference Result 1819 states and 2627 transitions. [2022-02-20 23:01:02,007 INFO L276 IsEmpty]: Start isEmpty. Operand 1819 states and 2627 transitions. [2022-02-20 23:01:02,021 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 23:01:02,021 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 23:01:02,026 INFO L74 IsIncluded]: Start isIncluded. First operand has 1819 states, 1130 states have (on average 1.2575221238938052) internal successors, (1421), 1159 states have internal predecessors, (1421), 603 states have call successors, (603), 85 states have call predecessors, (603), 85 states have return successors, (603), 591 states have call predecessors, (603), 603 states have call successors, (603) Second operand 1819 states. [2022-02-20 23:01:02,030 INFO L87 Difference]: Start difference. First operand has 1819 states, 1130 states have (on average 1.2575221238938052) internal successors, (1421), 1159 states have internal predecessors, (1421), 603 states have call successors, (603), 85 states have call predecessors, (603), 85 states have return successors, (603), 591 states have call predecessors, (603), 603 states have call successors, (603) Second operand 1819 states. [2022-02-20 23:01:02,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 23:01:02,175 INFO L93 Difference]: Finished difference Result 1819 states and 2627 transitions. [2022-02-20 23:01:02,176 INFO L276 IsEmpty]: Start isEmpty. Operand 1819 states and 2627 transitions. [2022-02-20 23:01:02,188 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 23:01:02,188 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 23:01:02,188 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 23:01:02,188 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 23:01:02,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1819 states, 1130 states have (on average 1.2575221238938052) internal successors, (1421), 1159 states have internal predecessors, (1421), 603 states have call successors, (603), 85 states have call predecessors, (603), 85 states have return successors, (603), 591 states have call predecessors, (603), 603 states have call successors, (603) [2022-02-20 23:01:02,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1819 states to 1819 states and 2627 transitions. [2022-02-20 23:01:02,387 INFO L78 Accepts]: Start accepts. Automaton has 1819 states and 2627 transitions. Word has length 50 [2022-02-20 23:01:02,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 23:01:02,388 INFO L470 AbstractCegarLoop]: Abstraction has 1819 states and 2627 transitions. [2022-02-20 23:01:02,389 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 7.25) internal successors, (29), 4 states have internal predecessors, (29), 2 states have call successors, (7), 2 states have call predecessors, (7), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 23:01:02,389 INFO L276 IsEmpty]: Start isEmpty. Operand 1819 states and 2627 transitions. [2022-02-20 23:01:02,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2022-02-20 23:01:02,391 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 23:01:02,392 INFO L514 BasicCegarLoop]: trace histogram [7, 7, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 23:01:02,392 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-02-20 23:01:02,392 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_check_final_stateErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 23:01:02,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 23:01:02,395 INFO L85 PathProgramCache]: Analyzing trace with hash -107056878, now seen corresponding path program 1 times [2022-02-20 23:01:02,395 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 23:01:02,395 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005873961] [2022-02-20 23:01:02,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 23:01:02,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 23:01:02,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,585 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 23:01:02,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,592 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet965 && #t~nondet965 <= 2147483647;~tmp~80 := #t~nondet965;havoc #t~nondet965;#res := ~tmp~80; {13650#true} is VALID [2022-02-20 23:01:02,592 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,592 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4619#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,593 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 12 [2022-02-20 23:01:02,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,599 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,599 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,600 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,600 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4621#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,604 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 18 [2022-02-20 23:01:02,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,616 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:01:02,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,620 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,621 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,621 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,621 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13650#true} {13650#true} #4031#return; {13650#true} is VALID [2022-02-20 23:01:02,621 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 23:01:02,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,626 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {13650#true} is VALID [2022-02-20 23:01:02,626 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,626 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {13650#true} {13650#true} #4033#return; {13650#true} is VALID [2022-02-20 23:01:02,626 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 23:01:02,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,630 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,631 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,631 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,631 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13650#true} {13650#true} #4035#return; {13650#true} is VALID [2022-02-20 23:01:02,633 INFO L290 TraceCheckUtils]: 0: Hoare triple {13720#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~28;call #t~malloc961.base, #t~malloc961.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc961.base, #t~malloc961.offset;havoc #t~malloc961.base, #t~malloc961.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {13650#true} is VALID [2022-02-20 23:01:02,634 INFO L272 TraceCheckUtils]: 1: Hoare triple {13650#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,634 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,634 INFO L290 TraceCheckUtils]: 3: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,634 INFO L290 TraceCheckUtils]: 4: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,634 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {13650#true} {13650#true} #4031#return; {13650#true} is VALID [2022-02-20 23:01:02,635 INFO L272 TraceCheckUtils]: 6: Hoare triple {13650#true} call #t~ret962 := ldv_is_err(~res~3.base, ~res~3.offset); {13650#true} is VALID [2022-02-20 23:01:02,635 INFO L290 TraceCheckUtils]: 7: Hoare triple {13650#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {13650#true} is VALID [2022-02-20 23:01:02,635 INFO L290 TraceCheckUtils]: 8: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,636 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {13650#true} {13650#true} #4033#return; {13650#true} is VALID [2022-02-20 23:01:02,636 INFO L290 TraceCheckUtils]: 10: Hoare triple {13650#true} assume -9223372036854775808 <= #t~ret962 && #t~ret962 <= 9223372036854775807;~tmp___0~28 := #t~ret962;havoc #t~ret962; {13650#true} is VALID [2022-02-20 23:01:02,636 INFO L272 TraceCheckUtils]: 11: Hoare triple {13650#true} call ldv_assume((if 0 == ~tmp___0~28 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,636 INFO L290 TraceCheckUtils]: 12: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,636 INFO L290 TraceCheckUtils]: 13: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,637 INFO L290 TraceCheckUtils]: 14: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,637 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {13650#true} {13650#true} #4035#return; {13650#true} is VALID [2022-02-20 23:01:02,637 INFO L290 TraceCheckUtils]: 16: Hoare triple {13650#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {13650#true} is VALID [2022-02-20 23:01:02,637 INFO L290 TraceCheckUtils]: 17: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,638 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4623#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,638 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 40 [2022-02-20 23:01:02,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,651 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:01:02,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,662 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,663 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,663 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,666 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13650#true} {13650#true} #4031#return; {13650#true} is VALID [2022-02-20 23:01:02,667 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 23:01:02,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,677 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {13650#true} is VALID [2022-02-20 23:01:02,678 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,678 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {13650#true} {13650#true} #4033#return; {13650#true} is VALID [2022-02-20 23:01:02,678 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 23:01:02,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,687 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,687 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,687 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,688 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13650#true} {13650#true} #4035#return; {13650#true} is VALID [2022-02-20 23:01:02,688 INFO L290 TraceCheckUtils]: 0: Hoare triple {13720#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~28;call #t~malloc961.base, #t~malloc961.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc961.base, #t~malloc961.offset;havoc #t~malloc961.base, #t~malloc961.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {13650#true} is VALID [2022-02-20 23:01:02,688 INFO L272 TraceCheckUtils]: 1: Hoare triple {13650#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,688 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,688 INFO L290 TraceCheckUtils]: 3: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,689 INFO L290 TraceCheckUtils]: 4: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,689 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {13650#true} {13650#true} #4031#return; {13650#true} is VALID [2022-02-20 23:01:02,689 INFO L272 TraceCheckUtils]: 6: Hoare triple {13650#true} call #t~ret962 := ldv_is_err(~res~3.base, ~res~3.offset); {13650#true} is VALID [2022-02-20 23:01:02,689 INFO L290 TraceCheckUtils]: 7: Hoare triple {13650#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {13650#true} is VALID [2022-02-20 23:01:02,690 INFO L290 TraceCheckUtils]: 8: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,690 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {13650#true} {13650#true} #4033#return; {13650#true} is VALID [2022-02-20 23:01:02,690 INFO L290 TraceCheckUtils]: 10: Hoare triple {13650#true} assume -9223372036854775808 <= #t~ret962 && #t~ret962 <= 9223372036854775807;~tmp___0~28 := #t~ret962;havoc #t~ret962; {13650#true} is VALID [2022-02-20 23:01:02,690 INFO L272 TraceCheckUtils]: 11: Hoare triple {13650#true} call ldv_assume((if 0 == ~tmp___0~28 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,690 INFO L290 TraceCheckUtils]: 12: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,690 INFO L290 TraceCheckUtils]: 13: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,690 INFO L290 TraceCheckUtils]: 14: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,691 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {13650#true} {13650#true} #4035#return; {13650#true} is VALID [2022-02-20 23:01:02,691 INFO L290 TraceCheckUtils]: 16: Hoare triple {13650#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {13650#true} is VALID [2022-02-20 23:01:02,691 INFO L290 TraceCheckUtils]: 17: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,692 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4627#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,692 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 61 [2022-02-20 23:01:02,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,704 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 23:01:02,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,709 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,709 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,709 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,709 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13650#true} {13650#true} #4031#return; {13650#true} is VALID [2022-02-20 23:01:02,710 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 23:01:02,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,714 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {13650#true} is VALID [2022-02-20 23:01:02,715 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,715 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {13650#true} {13650#true} #4033#return; {13650#true} is VALID [2022-02-20 23:01:02,715 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 23:01:02,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,719 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,719 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,719 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,719 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13650#true} {13650#true} #4035#return; {13650#true} is VALID [2022-02-20 23:01:02,720 INFO L290 TraceCheckUtils]: 0: Hoare triple {13720#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~28;call #t~malloc961.base, #t~malloc961.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc961.base, #t~malloc961.offset;havoc #t~malloc961.base, #t~malloc961.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {13650#true} is VALID [2022-02-20 23:01:02,720 INFO L272 TraceCheckUtils]: 1: Hoare triple {13650#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,720 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,720 INFO L290 TraceCheckUtils]: 3: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,720 INFO L290 TraceCheckUtils]: 4: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,720 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {13650#true} {13650#true} #4031#return; {13650#true} is VALID [2022-02-20 23:01:02,721 INFO L272 TraceCheckUtils]: 6: Hoare triple {13650#true} call #t~ret962 := ldv_is_err(~res~3.base, ~res~3.offset); {13650#true} is VALID [2022-02-20 23:01:02,721 INFO L290 TraceCheckUtils]: 7: Hoare triple {13650#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {13650#true} is VALID [2022-02-20 23:01:02,721 INFO L290 TraceCheckUtils]: 8: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,721 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {13650#true} {13650#true} #4033#return; {13650#true} is VALID [2022-02-20 23:01:02,721 INFO L290 TraceCheckUtils]: 10: Hoare triple {13650#true} assume -9223372036854775808 <= #t~ret962 && #t~ret962 <= 9223372036854775807;~tmp___0~28 := #t~ret962;havoc #t~ret962; {13650#true} is VALID [2022-02-20 23:01:02,721 INFO L272 TraceCheckUtils]: 11: Hoare triple {13650#true} call ldv_assume((if 0 == ~tmp___0~28 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,721 INFO L290 TraceCheckUtils]: 12: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,722 INFO L290 TraceCheckUtils]: 13: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,722 INFO L290 TraceCheckUtils]: 14: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,722 INFO L284 TraceCheckUtils]: 15: Hoare quadruple {13650#true} {13650#true} #4035#return; {13650#true} is VALID [2022-02-20 23:01:02,722 INFO L290 TraceCheckUtils]: 16: Hoare triple {13650#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {13650#true} is VALID [2022-02-20 23:01:02,722 INFO L290 TraceCheckUtils]: 17: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,723 INFO L284 TraceCheckUtils]: 18: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4629#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,723 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 82 [2022-02-20 23:01:02,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 23:01:02,730 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet965 && #t~nondet965 <= 2147483647;~tmp~80 := #t~nondet965;havoc #t~nondet965;#res := ~tmp~80; {13650#true} is VALID [2022-02-20 23:01:02,730 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,730 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4631#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,731 INFO L290 TraceCheckUtils]: 0: Hoare triple {13650#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(183, 1);call #Ultimate.allocInit(26, 2);call #Ultimate.allocInit(63, 3);call #Ultimate.allocInit(9, 4);call #Ultimate.allocInit(9, 5);call #Ultimate.allocInit(7, 6);call write~init~int(15, 6, 0, 1);call write~init~int(37, 6, 1, 1);call write~init~int(115, 6, 2, 1);call write~init~int(40, 6, 3, 1);call write~init~int(41, 6, 4, 1);call write~init~int(10, 6, 5, 1);call write~init~int(0, 6, 6, 1);call #Ultimate.allocInit(14, 7);call #Ultimate.allocInit(9, 8);call #Ultimate.allocInit(45, 9);call #Ultimate.allocInit(14, 10);call #Ultimate.allocInit(25, 11);call #Ultimate.allocInit(13, 12);call #Ultimate.allocInit(22, 13);call #Ultimate.allocInit(13, 14);call #Ultimate.allocInit(23, 15);call #Ultimate.allocInit(13, 16);call #Ultimate.allocInit(23, 17);call #Ultimate.allocInit(13, 18);call #Ultimate.allocInit(22, 19);call #Ultimate.allocInit(13, 20);call #Ultimate.allocInit(7, 21);call write~init~int(15, 21, 0, 1);call write~init~int(37, 21, 1, 1);call write~init~int(115, 21, 2, 1);call write~init~int(40, 21, 3, 1);call write~init~int(41, 21, 4, 1);call write~init~int(10, 21, 5, 1);call write~init~int(0, 21, 6, 1);call #Ultimate.allocInit(17, 22);call #Ultimate.allocInit(7, 23);call write~init~int(15, 23, 0, 1);call write~init~int(37, 23, 1, 1);call write~init~int(115, 23, 2, 1);call write~init~int(40, 23, 3, 1);call write~init~int(41, 23, 4, 1);call write~init~int(10, 23, 5, 1);call write~init~int(0, 23, 6, 1);call #Ultimate.allocInit(14, 24);call #Ultimate.allocInit(22, 25);call #Ultimate.allocInit(35, 26);call #Ultimate.allocInit(14, 27);call #Ultimate.allocInit(40, 28);call #Ultimate.allocInit(7, 29);call write~init~int(15, 29, 0, 1);call write~init~int(37, 29, 1, 1);call write~init~int(115, 29, 2, 1);call write~init~int(40, 29, 3, 1);call write~init~int(41, 29, 4, 1);call write~init~int(10, 29, 5, 1);call write~init~int(0, 29, 6, 1);call #Ultimate.allocInit(15, 30);call #Ultimate.allocInit(30, 31);call #Ultimate.allocInit(15, 32);call #Ultimate.allocInit(7, 33);call write~init~int(15, 33, 0, 1);call write~init~int(37, 33, 1, 1);call write~init~int(115, 33, 2, 1);call write~init~int(40, 33, 3, 1);call write~init~int(41, 33, 4, 1);call write~init~int(10, 33, 5, 1);call write~init~int(0, 33, 6, 1);call #Ultimate.allocInit(12, 34);call #Ultimate.allocInit(85, 35);call #Ultimate.allocInit(47, 36);call #Ultimate.allocInit(29, 37);call #Ultimate.allocInit(58, 38);call #Ultimate.allocInit(29, 39);call #Ultimate.allocInit(50, 40);call #Ultimate.allocInit(29, 41);call #Ultimate.allocInit(40, 42);call #Ultimate.allocInit(29, 43);call #Ultimate.allocInit(30, 44);call #Ultimate.allocInit(22, 45);call #Ultimate.allocInit(31, 46);call #Ultimate.allocInit(28, 47);call #Ultimate.allocInit(23, 48);call #Ultimate.allocInit(13, 49);call #Ultimate.allocInit(45, 50);call #Ultimate.allocInit(18, 51);call #Ultimate.allocInit(7, 52);call write~init~int(15, 52, 0, 1);call write~init~int(37, 52, 1, 1);call write~init~int(115, 52, 2, 1);call write~init~int(40, 52, 3, 1);call write~init~int(41, 52, 4, 1);call write~init~int(10, 52, 5, 1);call write~init~int(0, 52, 6, 1);call #Ultimate.allocInit(27, 53);call #Ultimate.allocInit(56, 54);call #Ultimate.allocInit(27, 55);call #Ultimate.allocInit(7, 56);call write~init~int(15, 56, 0, 1);call write~init~int(37, 56, 1, 1);call write~init~int(115, 56, 2, 1);call write~init~int(40, 56, 3, 1);call write~init~int(41, 56, 4, 1);call write~init~int(10, 56, 5, 1);call write~init~int(0, 56, 6, 1);call #Ultimate.allocInit(21, 57);call #Ultimate.allocInit(50, 58);call #Ultimate.allocInit(30, 59);call #Ultimate.allocInit(41, 60);call #Ultimate.allocInit(30, 61);call #Ultimate.allocInit(26, 62);call #Ultimate.allocInit(30, 63);call #Ultimate.allocInit(15, 64);call #Ultimate.allocInit(14, 65);call #Ultimate.allocInit(23, 66);call #Ultimate.allocInit(15, 67);call #Ultimate.allocInit(48, 68);call #Ultimate.allocInit(15, 69);call #Ultimate.allocInit(43, 70);call #Ultimate.allocInit(19, 71);call #Ultimate.allocInit(6, 72);call write~init~int(84, 72, 0, 1);call write~init~int(105, 72, 1, 1);call write~init~int(109, 72, 2, 1);call write~init~int(101, 72, 3, 1);call write~init~int(114, 72, 4, 1);call write~init~int(0, 72, 5, 1);call #Ultimate.allocInit(1, 73);call write~init~int(0, 73, 0, 1);call #Ultimate.allocInit(3, 74);call write~init~int(84, 74, 0, 1);call write~init~int(120, 74, 1, 1);call write~init~int(0, 74, 2, 1);call #Ultimate.allocInit(1, 75);call write~init~int(0, 75, 0, 1);call #Ultimate.allocInit(3, 76);call write~init~int(82, 76, 0, 1);call write~init~int(120, 76, 1, 1);call write~init~int(0, 76, 2, 1);call #Ultimate.allocInit(1, 77);call write~init~int(0, 77, 0, 1);call #Ultimate.allocInit(38, 78);call #Ultimate.allocInit(19, 79);call #Ultimate.allocInit(13, 80);call #Ultimate.allocInit(1, 81);call write~init~int(0, 81, 0, 1);call #Ultimate.allocInit(4, 82);call write~init~int(69, 82, 0, 1);call write~init~int(79, 82, 1, 1);call write~init~int(77, 82, 2, 1);call write~init~int(0, 82, 3, 1);call #Ultimate.allocInit(1, 83);call write~init~int(0, 83, 0, 1);call #Ultimate.allocInit(11, 84);call #Ultimate.allocInit(1, 85);call write~init~int(0, 85, 0, 1);call #Ultimate.allocInit(10, 86);call #Ultimate.allocInit(1, 87);call write~init~int(0, 87, 0, 1);call #Ultimate.allocInit(47, 88);call #Ultimate.allocInit(19, 89);call #Ultimate.allocInit(9, 90);call #Ultimate.allocInit(1, 91);call write~init~int(0, 91, 0, 1);call #Ultimate.allocInit(8, 92);call #Ultimate.allocInit(1, 93);call write~init~int(0, 93, 0, 1);call #Ultimate.allocInit(12, 94);call #Ultimate.allocInit(1, 95);call write~init~int(0, 95, 0, 1);call #Ultimate.allocInit(4, 96);call write~init~int(69, 96, 0, 1);call write~init~int(79, 96, 1, 1);call write~init~int(70, 96, 2, 1);call write~init~int(0, 96, 3, 1);call #Ultimate.allocInit(1, 97);call write~init~int(0, 97, 0, 1);call #Ultimate.allocInit(7, 98);call write~init~int(82, 98, 0, 1);call write~init~int(120, 98, 1, 1);call write~init~int(68, 98, 2, 1);call write~init~int(97, 98, 3, 1);call write~init~int(116, 98, 4, 1);call write~init~int(97, 98, 5, 1);call write~init~int(0, 98, 6, 1);call #Ultimate.allocInit(1, 99);call write~init~int(0, 99, 0, 1);call #Ultimate.allocInit(9, 100);call #Ultimate.allocInit(1, 101);call write~init~int(0, 101, 0, 1);call #Ultimate.allocInit(8, 102);call #Ultimate.allocInit(1, 103);call write~init~int(0, 103, 0, 1);call #Ultimate.allocInit(17, 104);call #Ultimate.allocInit(19, 105);call #Ultimate.allocInit(79, 106);call #Ultimate.allocInit(19, 107);call #Ultimate.allocInit(7, 108);call write~init~int(15, 108, 0, 1);call write~init~int(37, 108, 1, 1);call write~init~int(115, 108, 2, 1);call write~init~int(40, 108, 3, 1);call write~init~int(41, 108, 4, 1);call write~init~int(10, 108, 5, 1);call write~init~int(0, 108, 6, 1);call #Ultimate.allocInit(8, 109);call #Ultimate.allocInit(31, 110);call #Ultimate.allocInit(28, 111);call #Ultimate.allocInit(22, 112);call #Ultimate.allocInit(13, 113);call #Ultimate.allocInit(22, 114);call #Ultimate.allocInit(22, 115);call #Ultimate.allocInit(7, 116);call write~init~int(15, 116, 0, 1);call write~init~int(37, 116, 1, 1);call write~init~int(115, 116, 2, 1);call write~init~int(40, 116, 3, 1);call write~init~int(41, 116, 4, 1);call write~init~int(10, 116, 5, 1);call write~init~int(0, 116, 6, 1);call #Ultimate.allocInit(18, 117);call #Ultimate.allocInit(31, 118);call #Ultimate.allocInit(28, 119);call #Ultimate.allocInit(18, 120);call #Ultimate.allocInit(12, 121);call #Ultimate.allocInit(31, 122);call #Ultimate.allocInit(28, 123);call #Ultimate.allocInit(18, 124);call #Ultimate.allocInit(13, 125);call #Ultimate.allocInit(32, 126);call #Ultimate.allocInit(32, 127);call #Ultimate.allocInit(33, 128);call #Ultimate.allocInit(11, 129);call #Ultimate.allocInit(7, 130);call write~init~int(15, 130, 0, 1);call write~init~int(37, 130, 1, 1);call write~init~int(115, 130, 2, 1);call write~init~int(40, 130, 3, 1);call write~init~int(41, 130, 4, 1);call write~init~int(10, 130, 5, 1);call write~init~int(0, 130, 6, 1);call #Ultimate.allocInit(19, 131);call #Ultimate.allocInit(31, 132);call #Ultimate.allocInit(28, 133);call #Ultimate.allocInit(19, 134);call #Ultimate.allocInit(12, 135);call #Ultimate.allocInit(31, 136);call #Ultimate.allocInit(28, 137);call #Ultimate.allocInit(19, 138);call #Ultimate.allocInit(13, 139);call #Ultimate.allocInit(31, 140);call #Ultimate.allocInit(28, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(12, 143);call #Ultimate.allocInit(31, 144);call #Ultimate.allocInit(28, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(13, 147);call #Ultimate.allocInit(23, 148);call #Ultimate.allocInit(19, 149);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(2, 151);call write~init~int(48, 151, 0, 1);call write~init~int(0, 151, 1, 1);call #Ultimate.allocInit(57, 152);~driver_name~0.base, ~driver_name~0.offset := 4, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 153, 0;call #Ultimate.allocInit(192, 153);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci_device_table~0.vendor := 0;~__mod_pci_device_table~0.device := 0;~__mod_pci_device_table~0.subvendor := 0;~__mod_pci_device_table~0.subdevice := 0;~__mod_pci_device_table~0.class := 0;~__mod_pci_device_table~0.class_mask := 0;~__mod_pci_device_table~0.driver_data := 0;~#via_driver~0.base, ~#via_driver~0.offset := 154, 0;call #Ultimate.allocInit(301, 154);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(5, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 145 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 153 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 161 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 169 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 177 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 185 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 193 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 201 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 209 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 217 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 237 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 245 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 253 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 261 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 269 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 285 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 293 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 155, 0;call #Ultimate.allocInit(472, 155);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 156, 0;call #Ultimate.allocInit(472, 156);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_thread_0~0.identifier := 0;~ldv_thread_0~0.function.base, ~ldv_thread_0~0.function.offset := 0, 0;~ldv_thread_1~0.identifier := 0;~ldv_thread_1~0.function.base, ~ldv_thread_1~0.function.offset := 0, 0;~ldv_thread_10~0.identifier := 0;~ldv_thread_10~0.function.base, ~ldv_thread_10~0.function.offset := 0, 0;~ldv_thread_2~0.identifier := 0;~ldv_thread_2~0.function.base, ~ldv_thread_2~0.function.offset := 0, 0;~LDV_USB_DEV_REF_COUNTS~0 := 0; {13650#true} is VALID [2022-02-20 23:01:02,731 INFO L290 TraceCheckUtils]: 1: Hoare triple {13650#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_ldv_initialize } true;~LDV_USB_DEV_REF_COUNTS~0 := 0; {13650#true} is VALID [2022-02-20 23:01:02,731 INFO L290 TraceCheckUtils]: 2: Hoare triple {13650#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_entry_EMGentry_10 } true;ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset := 0, 0;havoc ldv_entry_EMGentry_10_#t~ret837#1, ldv_entry_EMGentry_10_#t~ret838#1, ldv_entry_EMGentry_10_#t~ret839#1, ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset, ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1, ldv_entry_EMGentry_10_~tmp~52#1;ldv_entry_EMGentry_10_~arg0#1.base, ldv_entry_EMGentry_10_~arg0#1.offset := ldv_entry_EMGentry_10_#in~arg0#1.base, ldv_entry_EMGentry_10_#in~arg0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_exit_via_ircc_cleanup_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_entry_EMGentry_10_~ldv_10_ret_default~0#1;havoc ldv_entry_EMGentry_10_~tmp~52#1;assume { :begin_inline_ldv_EMGentry_init_via_ircc_init_10_7 } true;ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset := ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.base, ldv_entry_EMGentry_10_~ldv_10_init_via_ircc_init_default~0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_#res#1;havoc ldv_EMGentry_init_via_ircc_init_10_7_#t~ret830#1, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset, ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_~arg0#1.offset := ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.base, ldv_EMGentry_init_via_ircc_init_10_7_#in~arg0#1.offset;havoc ldv_EMGentry_init_via_ircc_init_10_7_~tmp~47#1;assume { :begin_inline_via_ircc_init } true;havoc via_ircc_init_#res#1;havoc via_ircc_init_#t~nondet244#1, via_ircc_init_#t~ret245#1, via_ircc_init_#t~nondet246#1, via_ircc_init_~rc~0#1;havoc via_ircc_init_~rc~0#1; {13650#true} is VALID [2022-02-20 23:01:02,732 INFO L290 TraceCheckUtils]: 3: Hoare triple {13650#true} assume ~irda_debug~0 % 4294967296 > 2;havoc via_ircc_init_#t~nondet244#1; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,733 INFO L290 TraceCheckUtils]: 4: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} assume { :begin_inline_ldv___pci_register_driver_18 } true;ldv___pci_register_driver_18_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg1#1.offset, ldv___pci_register_driver_18_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg2#1.offset, ldv___pci_register_driver_18_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg3#1.offset := ~#via_driver~0.base, ~#via_driver~0.offset, ~#__this_module~0.base, ~#__this_module~0.offset, 8, 0;havoc ldv___pci_register_driver_18_#res#1;havoc ldv___pci_register_driver_18_#t~ret906#1, ldv___pci_register_driver_18_#t~ret907#1, ldv___pci_register_driver_18_~ldv_func_arg1#1.base, ldv___pci_register_driver_18_~ldv_func_arg1#1.offset, ldv___pci_register_driver_18_~ldv_func_arg2#1.base, ldv___pci_register_driver_18_~ldv_func_arg2#1.offset, ldv___pci_register_driver_18_~ldv_func_arg3#1.base, ldv___pci_register_driver_18_~ldv_func_arg3#1.offset, ldv___pci_register_driver_18_~ldv_func_res~0#1, ldv___pci_register_driver_18_~tmp~65#1, ldv___pci_register_driver_18_~tmp___0~22#1;ldv___pci_register_driver_18_~ldv_func_arg1#1.base, ldv___pci_register_driver_18_~ldv_func_arg1#1.offset := ldv___pci_register_driver_18_#in~ldv_func_arg1#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg1#1.offset;ldv___pci_register_driver_18_~ldv_func_arg2#1.base, ldv___pci_register_driver_18_~ldv_func_arg2#1.offset := ldv___pci_register_driver_18_#in~ldv_func_arg2#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg2#1.offset;ldv___pci_register_driver_18_~ldv_func_arg3#1.base, ldv___pci_register_driver_18_~ldv_func_arg3#1.offset := ldv___pci_register_driver_18_#in~ldv_func_arg3#1.base, ldv___pci_register_driver_18_#in~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_18_~ldv_func_res~0#1;havoc ldv___pci_register_driver_18_~tmp~65#1;havoc ldv___pci_register_driver_18_~tmp___0~22#1;assume { :begin_inline___pci_register_driver } true;__pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset, __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset, __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset := ldv___pci_register_driver_18_~ldv_func_arg1#1.base, ldv___pci_register_driver_18_~ldv_func_arg1#1.offset, ldv___pci_register_driver_18_~ldv_func_arg2#1.base, ldv___pci_register_driver_18_~ldv_func_arg2#1.offset, ldv___pci_register_driver_18_~ldv_func_arg3#1.base, ldv___pci_register_driver_18_~ldv_func_arg3#1.offset;havoc __pci_register_driver_#res#1;havoc __pci_register_driver_#t~nondet976#1, __pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset, __pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset, __pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset;__pci_register_driver_~arg0#1.base, __pci_register_driver_~arg0#1.offset := __pci_register_driver_#in~arg0#1.base, __pci_register_driver_#in~arg0#1.offset;__pci_register_driver_~arg1#1.base, __pci_register_driver_~arg1#1.offset := __pci_register_driver_#in~arg1#1.base, __pci_register_driver_#in~arg1#1.offset;__pci_register_driver_~arg2#1.base, __pci_register_driver_~arg2#1.offset := __pci_register_driver_#in~arg2#1.base, __pci_register_driver_#in~arg2#1.offset;assume -2147483648 <= __pci_register_driver_#t~nondet976#1 && __pci_register_driver_#t~nondet976#1 <= 2147483647;__pci_register_driver_#res#1 := __pci_register_driver_#t~nondet976#1;havoc __pci_register_driver_#t~nondet976#1; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,733 INFO L290 TraceCheckUtils]: 5: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} ldv___pci_register_driver_18_#t~ret906#1 := __pci_register_driver_#res#1;assume { :end_inline___pci_register_driver } true;assume -2147483648 <= ldv___pci_register_driver_18_#t~ret906#1 && ldv___pci_register_driver_18_#t~ret906#1 <= 2147483647;ldv___pci_register_driver_18_~tmp~65#1 := ldv___pci_register_driver_18_#t~ret906#1;havoc ldv___pci_register_driver_18_#t~ret906#1;ldv___pci_register_driver_18_~ldv_func_res~0#1 := ldv___pci_register_driver_18_~tmp~65#1;assume { :begin_inline_ldv___pci_register_driver } true;ldv___pci_register_driver_#in~arg0#1, ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset, ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset, ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset := ldv___pci_register_driver_18_~ldv_func_res~0#1, ldv___pci_register_driver_18_~ldv_func_arg1#1.base, ldv___pci_register_driver_18_~ldv_func_arg1#1.offset, ldv___pci_register_driver_18_~ldv_func_arg2#1.base, ldv___pci_register_driver_18_~ldv_func_arg2#1.offset, ldv___pci_register_driver_18_~ldv_func_arg3#1.base, ldv___pci_register_driver_18_~ldv_func_arg3#1.offset;havoc ldv___pci_register_driver_#res#1;havoc ldv___pci_register_driver_#t~ret831#1, ldv___pci_register_driver_~arg0#1, ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset, ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset, ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset, ldv___pci_register_driver_~tmp~48#1;ldv___pci_register_driver_~arg0#1 := ldv___pci_register_driver_#in~arg0#1;ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset := ldv___pci_register_driver_#in~arg1#1.base, ldv___pci_register_driver_#in~arg1#1.offset;ldv___pci_register_driver_~arg2#1.base, ldv___pci_register_driver_~arg2#1.offset := ldv___pci_register_driver_#in~arg2#1.base, ldv___pci_register_driver_#in~arg2#1.offset;ldv___pci_register_driver_~arg3#1.base, ldv___pci_register_driver_~arg3#1.offset := ldv___pci_register_driver_#in~arg3#1.base, ldv___pci_register_driver_#in~arg3#1.offset;havoc ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset;havoc ldv___pci_register_driver_~tmp~48#1; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,734 INFO L272 TraceCheckUtils]: 6: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} call ldv___pci_register_driver_#t~ret831#1 := ldv_undef_int(); {13650#true} is VALID [2022-02-20 23:01:02,734 INFO L290 TraceCheckUtils]: 7: Hoare triple {13650#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet965 && #t~nondet965 <= 2147483647;~tmp~80 := #t~nondet965;havoc #t~nondet965;#res := ~tmp~80; {13650#true} is VALID [2022-02-20 23:01:02,734 INFO L290 TraceCheckUtils]: 8: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,734 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4619#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,735 INFO L290 TraceCheckUtils]: 10: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} assume -2147483648 <= ldv___pci_register_driver_#t~ret831#1 && ldv___pci_register_driver_#t~ret831#1 <= 2147483647;ldv___pci_register_driver_~tmp~48#1 := ldv___pci_register_driver_#t~ret831#1;havoc ldv___pci_register_driver_#t~ret831#1; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,735 INFO L290 TraceCheckUtils]: 11: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} assume 0 != ldv___pci_register_driver_~tmp~48#1; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,735 INFO L272 TraceCheckUtils]: 12: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} call ldv_assume((if 0 == ldv___pci_register_driver_~arg0#1 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,735 INFO L290 TraceCheckUtils]: 13: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,736 INFO L290 TraceCheckUtils]: 14: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,736 INFO L290 TraceCheckUtils]: 15: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,736 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4621#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,737 INFO L290 TraceCheckUtils]: 17: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset := ldv___pci_register_driver_~arg1#1.base, ldv___pci_register_driver_~arg1#1.offset;assume { :begin_inline_ldv_dispatch_register_9_2 } true;ldv_dispatch_register_9_2_#in~arg0#1.base, ldv_dispatch_register_9_2_#in~arg0#1.offset := ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.base, ldv___pci_register_driver_~ldv_9_pci_driver_pci_driver~0#1.offset;havoc ldv_dispatch_register_9_2_#t~ret834#1.base, ldv_dispatch_register_9_2_#t~ret834#1.offset, ldv_dispatch_register_9_2_~arg0#1.base, ldv_dispatch_register_9_2_~arg0#1.offset, ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset, ldv_dispatch_register_9_2_~tmp~51#1.base, ldv_dispatch_register_9_2_~tmp~51#1.offset;ldv_dispatch_register_9_2_~arg0#1.base, ldv_dispatch_register_9_2_~arg0#1.offset := ldv_dispatch_register_9_2_#in~arg0#1.base, ldv_dispatch_register_9_2_#in~arg0#1.offset;havoc ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset;havoc ldv_dispatch_register_9_2_~tmp~51#1.base, ldv_dispatch_register_9_2_~tmp~51#1.offset; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,737 INFO L272 TraceCheckUtils]: 18: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} call ldv_dispatch_register_9_2_#t~ret834#1.base, ldv_dispatch_register_9_2_#t~ret834#1.offset := ldv_xmalloc(16); {13720#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 23:01:02,738 INFO L290 TraceCheckUtils]: 19: Hoare triple {13720#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~28;call #t~malloc961.base, #t~malloc961.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc961.base, #t~malloc961.offset;havoc #t~malloc961.base, #t~malloc961.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {13650#true} is VALID [2022-02-20 23:01:02,738 INFO L272 TraceCheckUtils]: 20: Hoare triple {13650#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,738 INFO L290 TraceCheckUtils]: 21: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,738 INFO L290 TraceCheckUtils]: 22: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,738 INFO L290 TraceCheckUtils]: 23: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,738 INFO L284 TraceCheckUtils]: 24: Hoare quadruple {13650#true} {13650#true} #4031#return; {13650#true} is VALID [2022-02-20 23:01:02,738 INFO L272 TraceCheckUtils]: 25: Hoare triple {13650#true} call #t~ret962 := ldv_is_err(~res~3.base, ~res~3.offset); {13650#true} is VALID [2022-02-20 23:01:02,739 INFO L290 TraceCheckUtils]: 26: Hoare triple {13650#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {13650#true} is VALID [2022-02-20 23:01:02,739 INFO L290 TraceCheckUtils]: 27: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,739 INFO L284 TraceCheckUtils]: 28: Hoare quadruple {13650#true} {13650#true} #4033#return; {13650#true} is VALID [2022-02-20 23:01:02,739 INFO L290 TraceCheckUtils]: 29: Hoare triple {13650#true} assume -9223372036854775808 <= #t~ret962 && #t~ret962 <= 9223372036854775807;~tmp___0~28 := #t~ret962;havoc #t~ret962; {13650#true} is VALID [2022-02-20 23:01:02,739 INFO L272 TraceCheckUtils]: 30: Hoare triple {13650#true} call ldv_assume((if 0 == ~tmp___0~28 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,739 INFO L290 TraceCheckUtils]: 31: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,739 INFO L290 TraceCheckUtils]: 32: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,740 INFO L290 TraceCheckUtils]: 33: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,740 INFO L284 TraceCheckUtils]: 34: Hoare quadruple {13650#true} {13650#true} #4035#return; {13650#true} is VALID [2022-02-20 23:01:02,740 INFO L290 TraceCheckUtils]: 35: Hoare triple {13650#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {13650#true} is VALID [2022-02-20 23:01:02,740 INFO L290 TraceCheckUtils]: 36: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,741 INFO L284 TraceCheckUtils]: 37: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4623#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,741 INFO L290 TraceCheckUtils]: 38: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} ldv_dispatch_register_9_2_~tmp~51#1.base, ldv_dispatch_register_9_2_~tmp~51#1.offset := ldv_dispatch_register_9_2_#t~ret834#1.base, ldv_dispatch_register_9_2_#t~ret834#1.offset;havoc ldv_dispatch_register_9_2_#t~ret834#1.base, ldv_dispatch_register_9_2_#t~ret834#1.offset;ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset := ldv_dispatch_register_9_2_~tmp~51#1.base, ldv_dispatch_register_9_2_~tmp~51#1.offset;call write~$Pointer$(ldv_dispatch_register_9_2_~arg0#1.base, ldv_dispatch_register_9_2_~arg0#1.offset, ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset, 8);assume { :begin_inline_ldv_pci_pci_instance_2 } true;ldv_pci_pci_instance_2_#in~arg0#1.base, ldv_pci_pci_instance_2_#in~arg0#1.offset := ldv_dispatch_register_9_2_~cf_arg_2~0#1.base, ldv_dispatch_register_9_2_~cf_arg_2~0#1.offset;havoc ldv_pci_pci_instance_2_#t~mem867#1.base, ldv_pci_pci_instance_2_#t~mem867#1.offset, ldv_pci_pci_instance_2_#t~ret868#1.base, ldv_pci_pci_instance_2_#t~ret868#1.offset, ldv_pci_pci_instance_2_#t~ret869#1.base, ldv_pci_pci_instance_2_#t~ret869#1.offset, ldv_pci_pci_instance_2_#t~ret870#1, ldv_pci_pci_instance_2_#t~mem871#1.base, ldv_pci_pci_instance_2_#t~mem871#1.offset, ldv_pci_pci_instance_2_#t~ret872#1, ldv_pci_pci_instance_2_#t~ret873#1, ldv_pci_pci_instance_2_#t~ret874#1, ldv_pci_pci_instance_2_#t~ret875#1, ldv_pci_pci_instance_2_#t~mem876#1.base, ldv_pci_pci_instance_2_#t~mem876#1.offset, ldv_pci_pci_instance_2_#t~mem877#1.base, ldv_pci_pci_instance_2_#t~mem877#1.offset, ldv_pci_pci_instance_2_#t~mem878#1, ldv_pci_pci_instance_2_#t~ret879#1, ldv_pci_pci_instance_2_#t~ret880#1, ldv_pci_pci_instance_2_#t~mem881#1.base, ldv_pci_pci_instance_2_#t~mem881#1.offset, ldv_pci_pci_instance_2_#t~mem882#1.base, ldv_pci_pci_instance_2_#t~mem882#1.offset, ldv_pci_pci_instance_2_#t~mem883#1, ldv_pci_pci_instance_2_#t~ret884#1, ldv_pci_pci_instance_2_#t~ret885#1, ldv_pci_pci_instance_2_#t~mem886#1.base, ldv_pci_pci_instance_2_#t~mem886#1.offset, ldv_pci_pci_instance_2_#t~mem887#1.base, ldv_pci_pci_instance_2_#t~mem887#1.offset, ldv_pci_pci_instance_2_#t~mem888#1.base, ldv_pci_pci_instance_2_#t~mem888#1.offset, ldv_pci_pci_instance_2_#t~mem889#1.base, ldv_pci_pci_instance_2_#t~mem889#1.offset, ldv_pci_pci_instance_2_#t~mem890#1.base, ldv_pci_pci_instance_2_#t~mem890#1.offset, ldv_pci_pci_instance_2_#t~mem891#1.base, ldv_pci_pci_instance_2_#t~mem891#1.offset, ldv_pci_pci_instance_2_#t~mem892#1.base, ldv_pci_pci_instance_2_#t~mem892#1.offset, ldv_pci_pci_instance_2_~arg0#1.base, ldv_pci_pci_instance_2_~arg0#1.offset, ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.offset, ldv_pci_pci_instance_2_~#ldv_2_resource_pm_message~0#1.base, ldv_pci_pci_instance_2_~#ldv_2_resource_pm_message~0#1.offset, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.offset, ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1, ldv_pci_pci_instance_2_~data~4#1.base, ldv_pci_pci_instance_2_~data~4#1.offset, ldv_pci_pci_instance_2_~tmp~59#1.base, ldv_pci_pci_instance_2_~tmp~59#1.offset, ldv_pci_pci_instance_2_~tmp___0~20#1.base, ldv_pci_pci_instance_2_~tmp___0~20#1.offset, ldv_pci_pci_instance_2_~tmp___1~13#1, ldv_pci_pci_instance_2_~tmp___2~10#1, ldv_pci_pci_instance_2_~tmp___3~7#1;ldv_pci_pci_instance_2_~arg0#1.base, ldv_pci_pci_instance_2_~arg0#1.offset := ldv_pci_pci_instance_2_#in~arg0#1.base, ldv_pci_pci_instance_2_#in~arg0#1.offset;havoc ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset;havoc ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.offset;call ldv_pci_pci_instance_2_~#ldv_2_resource_pm_message~0#1.base, ldv_pci_pci_instance_2_~#ldv_2_resource_pm_message~0#1.offset := #Ultimate.allocOnStack(4);havoc ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.offset;havoc ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1;havoc ldv_pci_pci_instance_2_~data~4#1.base, ldv_pci_pci_instance_2_~data~4#1.offset;havoc ldv_pci_pci_instance_2_~tmp~59#1.base, ldv_pci_pci_instance_2_~tmp~59#1.offset;havoc ldv_pci_pci_instance_2_~tmp___0~20#1.base, ldv_pci_pci_instance_2_~tmp___0~20#1.offset;havoc ldv_pci_pci_instance_2_~tmp___1~13#1;havoc ldv_pci_pci_instance_2_~tmp___2~10#1;havoc ldv_pci_pci_instance_2_~tmp___3~7#1;ldv_pci_pci_instance_2_~data~4#1.base, ldv_pci_pci_instance_2_~data~4#1.offset := ldv_pci_pci_instance_2_~arg0#1.base, ldv_pci_pci_instance_2_~arg0#1.offset;ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1 := 1; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,742 INFO L290 TraceCheckUtils]: 39: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} assume !(0 != (ldv_pci_pci_instance_2_~data~4#1.base + ldv_pci_pci_instance_2_~data~4#1.offset) % 18446744073709551616); {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,743 INFO L272 TraceCheckUtils]: 40: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} call ldv_pci_pci_instance_2_#t~ret868#1.base, ldv_pci_pci_instance_2_#t~ret868#1.offset := ldv_xmalloc(2936); {13720#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 23:01:02,743 INFO L290 TraceCheckUtils]: 41: Hoare triple {13720#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~28;call #t~malloc961.base, #t~malloc961.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc961.base, #t~malloc961.offset;havoc #t~malloc961.base, #t~malloc961.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {13650#true} is VALID [2022-02-20 23:01:02,743 INFO L272 TraceCheckUtils]: 42: Hoare triple {13650#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,743 INFO L290 TraceCheckUtils]: 43: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,743 INFO L290 TraceCheckUtils]: 44: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,743 INFO L290 TraceCheckUtils]: 45: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,743 INFO L284 TraceCheckUtils]: 46: Hoare quadruple {13650#true} {13650#true} #4031#return; {13650#true} is VALID [2022-02-20 23:01:02,744 INFO L272 TraceCheckUtils]: 47: Hoare triple {13650#true} call #t~ret962 := ldv_is_err(~res~3.base, ~res~3.offset); {13650#true} is VALID [2022-02-20 23:01:02,744 INFO L290 TraceCheckUtils]: 48: Hoare triple {13650#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {13650#true} is VALID [2022-02-20 23:01:02,744 INFO L290 TraceCheckUtils]: 49: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,744 INFO L284 TraceCheckUtils]: 50: Hoare quadruple {13650#true} {13650#true} #4033#return; {13650#true} is VALID [2022-02-20 23:01:02,744 INFO L290 TraceCheckUtils]: 51: Hoare triple {13650#true} assume -9223372036854775808 <= #t~ret962 && #t~ret962 <= 9223372036854775807;~tmp___0~28 := #t~ret962;havoc #t~ret962; {13650#true} is VALID [2022-02-20 23:01:02,744 INFO L272 TraceCheckUtils]: 52: Hoare triple {13650#true} call ldv_assume((if 0 == ~tmp___0~28 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,744 INFO L290 TraceCheckUtils]: 53: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,745 INFO L290 TraceCheckUtils]: 54: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,745 INFO L290 TraceCheckUtils]: 55: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,745 INFO L284 TraceCheckUtils]: 56: Hoare quadruple {13650#true} {13650#true} #4035#return; {13650#true} is VALID [2022-02-20 23:01:02,745 INFO L290 TraceCheckUtils]: 57: Hoare triple {13650#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {13650#true} is VALID [2022-02-20 23:01:02,745 INFO L290 TraceCheckUtils]: 58: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,746 INFO L284 TraceCheckUtils]: 59: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4627#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,746 INFO L290 TraceCheckUtils]: 60: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} ldv_pci_pci_instance_2_~tmp~59#1.base, ldv_pci_pci_instance_2_~tmp~59#1.offset := ldv_pci_pci_instance_2_#t~ret868#1.base, ldv_pci_pci_instance_2_#t~ret868#1.offset;havoc ldv_pci_pci_instance_2_#t~ret868#1.base, ldv_pci_pci_instance_2_#t~ret868#1.offset;ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.offset := ldv_pci_pci_instance_2_~tmp~59#1.base, ldv_pci_pci_instance_2_~tmp~59#1.offset; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,747 INFO L272 TraceCheckUtils]: 61: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} call ldv_pci_pci_instance_2_#t~ret869#1.base, ldv_pci_pci_instance_2_#t~ret869#1.offset := ldv_xmalloc(32); {13720#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 23:01:02,747 INFO L290 TraceCheckUtils]: 62: Hoare triple {13720#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~res~3.base, ~res~3.offset;havoc ~tmp~78.base, ~tmp~78.offset;havoc ~tmp___0~28;call #t~malloc961.base, #t~malloc961.offset := #Ultimate.allocOnHeap(~size);~tmp~78.base, ~tmp~78.offset := #t~malloc961.base, #t~malloc961.offset;havoc #t~malloc961.base, #t~malloc961.offset;~res~3.base, ~res~3.offset := ~tmp~78.base, ~tmp~78.offset; {13650#true} is VALID [2022-02-20 23:01:02,747 INFO L272 TraceCheckUtils]: 63: Hoare triple {13650#true} call ldv_assume((if 0 != (~res~3.base + ~res~3.offset) % 18446744073709551616 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,747 INFO L290 TraceCheckUtils]: 64: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,747 INFO L290 TraceCheckUtils]: 65: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,748 INFO L290 TraceCheckUtils]: 66: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,748 INFO L284 TraceCheckUtils]: 67: Hoare quadruple {13650#true} {13650#true} #4031#return; {13650#true} is VALID [2022-02-20 23:01:02,748 INFO L272 TraceCheckUtils]: 68: Hoare triple {13650#true} call #t~ret962 := ldv_is_err(~res~3.base, ~res~3.offset); {13650#true} is VALID [2022-02-20 23:01:02,748 INFO L290 TraceCheckUtils]: 69: Hoare triple {13650#true} ~ptr.base, ~ptr.offset := #in~ptr.base, #in~ptr.offset;#res := (if (~ptr.base + ~ptr.offset) % 18446744073709551616 > 4294967295 then 1 else 0); {13650#true} is VALID [2022-02-20 23:01:02,748 INFO L290 TraceCheckUtils]: 70: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,748 INFO L284 TraceCheckUtils]: 71: Hoare quadruple {13650#true} {13650#true} #4033#return; {13650#true} is VALID [2022-02-20 23:01:02,748 INFO L290 TraceCheckUtils]: 72: Hoare triple {13650#true} assume -9223372036854775808 <= #t~ret962 && #t~ret962 <= 9223372036854775807;~tmp___0~28 := #t~ret962;havoc #t~ret962; {13650#true} is VALID [2022-02-20 23:01:02,749 INFO L272 TraceCheckUtils]: 73: Hoare triple {13650#true} call ldv_assume((if 0 == ~tmp___0~28 then 1 else 0)); {13650#true} is VALID [2022-02-20 23:01:02,749 INFO L290 TraceCheckUtils]: 74: Hoare triple {13650#true} ~expression := #in~expression; {13650#true} is VALID [2022-02-20 23:01:02,749 INFO L290 TraceCheckUtils]: 75: Hoare triple {13650#true} assume !(0 == ~expression); {13650#true} is VALID [2022-02-20 23:01:02,749 INFO L290 TraceCheckUtils]: 76: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,749 INFO L284 TraceCheckUtils]: 77: Hoare quadruple {13650#true} {13650#true} #4035#return; {13650#true} is VALID [2022-02-20 23:01:02,749 INFO L290 TraceCheckUtils]: 78: Hoare triple {13650#true} #res.base, #res.offset := ~res~3.base, ~res~3.offset; {13650#true} is VALID [2022-02-20 23:01:02,749 INFO L290 TraceCheckUtils]: 79: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,750 INFO L284 TraceCheckUtils]: 80: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4629#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,751 INFO L290 TraceCheckUtils]: 81: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} ldv_pci_pci_instance_2_~tmp___0~20#1.base, ldv_pci_pci_instance_2_~tmp___0~20#1.offset := ldv_pci_pci_instance_2_#t~ret869#1.base, ldv_pci_pci_instance_2_#t~ret869#1.offset;havoc ldv_pci_pci_instance_2_#t~ret869#1.base, ldv_pci_pci_instance_2_#t~ret869#1.offset;ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.offset := ldv_pci_pci_instance_2_~tmp___0~20#1.base, ldv_pci_pci_instance_2_~tmp___0~20#1.offset; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,751 INFO L272 TraceCheckUtils]: 82: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} call ldv_pci_pci_instance_2_#t~ret870#1 := ldv_undef_int(); {13650#true} is VALID [2022-02-20 23:01:02,751 INFO L290 TraceCheckUtils]: 83: Hoare triple {13650#true} havoc ~tmp~80;assume -2147483648 <= #t~nondet965 && #t~nondet965 <= 2147483647;~tmp~80 := #t~nondet965;havoc #t~nondet965;#res := ~tmp~80; {13650#true} is VALID [2022-02-20 23:01:02,751 INFO L290 TraceCheckUtils]: 84: Hoare triple {13650#true} assume true; {13650#true} is VALID [2022-02-20 23:01:02,751 INFO L284 TraceCheckUtils]: 85: Hoare quadruple {13650#true} {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} #4631#return; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,752 INFO L290 TraceCheckUtils]: 86: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} assume -2147483648 <= ldv_pci_pci_instance_2_#t~ret870#1 && ldv_pci_pci_instance_2_#t~ret870#1 <= 2147483647;ldv_pci_pci_instance_2_~tmp___2~10#1 := ldv_pci_pci_instance_2_#t~ret870#1;havoc ldv_pci_pci_instance_2_#t~ret870#1; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,752 INFO L290 TraceCheckUtils]: 87: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} assume 0 != ldv_pci_pci_instance_2_~tmp___2~10#1;assume { :begin_inline_ldv_pre_probe } true; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,753 INFO L290 TraceCheckUtils]: 88: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} assume { :end_inline_ldv_pre_probe } true;call ldv_pci_pci_instance_2_#t~mem871#1.base, ldv_pci_pci_instance_2_#t~mem871#1.offset := read~$Pointer$(ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.base, 32 + ldv_pci_pci_instance_2_~ldv_2_container_pci_driver~0#1.offset, 8);assume { :begin_inline_ldv_pci_instance_probe_2_17 } true;ldv_pci_instance_probe_2_17_#in~arg0#1.base, ldv_pci_instance_probe_2_17_#in~arg0#1.offset, ldv_pci_instance_probe_2_17_#in~arg1#1.base, ldv_pci_instance_probe_2_17_#in~arg1#1.offset, ldv_pci_instance_probe_2_17_#in~arg2#1.base, ldv_pci_instance_probe_2_17_#in~arg2#1.offset := ldv_pci_pci_instance_2_#t~mem871#1.base, ldv_pci_pci_instance_2_#t~mem871#1.offset, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_dev~0#1.offset, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.base, ldv_pci_pci_instance_2_~ldv_2_resource_struct_pci_device_id_ptr~0#1.offset;havoc ldv_pci_instance_probe_2_17_#res#1;havoc ldv_pci_instance_probe_2_17_#t~ret853#1, ldv_pci_instance_probe_2_17_~arg0#1.base, ldv_pci_instance_probe_2_17_~arg0#1.offset, ldv_pci_instance_probe_2_17_~arg1#1.base, ldv_pci_instance_probe_2_17_~arg1#1.offset, ldv_pci_instance_probe_2_17_~arg2#1.base, ldv_pci_instance_probe_2_17_~arg2#1.offset, ldv_pci_instance_probe_2_17_~tmp~56#1;ldv_pci_instance_probe_2_17_~arg0#1.base, ldv_pci_instance_probe_2_17_~arg0#1.offset := ldv_pci_instance_probe_2_17_#in~arg0#1.base, ldv_pci_instance_probe_2_17_#in~arg0#1.offset;ldv_pci_instance_probe_2_17_~arg1#1.base, ldv_pci_instance_probe_2_17_~arg1#1.offset := ldv_pci_instance_probe_2_17_#in~arg1#1.base, ldv_pci_instance_probe_2_17_#in~arg1#1.offset;ldv_pci_instance_probe_2_17_~arg2#1.base, ldv_pci_instance_probe_2_17_~arg2#1.offset := ldv_pci_instance_probe_2_17_#in~arg2#1.base, ldv_pci_instance_probe_2_17_#in~arg2#1.offset;havoc ldv_pci_instance_probe_2_17_~tmp~56#1;assume { :begin_inline_via_init_one } true;via_init_one_#in~pcidev#1.base, via_init_one_#in~pcidev#1.offset, via_init_one_#in~id#1.base, via_init_one_#in~id#1.offset := ldv_pci_instance_probe_2_17_~arg1#1.base, ldv_pci_instance_probe_2_17_~arg1#1.offset, ldv_pci_instance_probe_2_17_~arg2#1.base, ldv_pci_instance_probe_2_17_~arg2#1.offset;havoc via_init_one_#res#1;havoc via_init_one_#t~nondet247#1, via_init_one_#t~mem248#1, via_init_one_#t~ret249#1, via_init_one_#t~nondet250#1, via_init_one_#t~ret251#1, via_init_one_#t~nondet252#1, via_init_one_#t~ret253#1, via_init_one_#t~ret254#1, via_init_one_#t~ret255#1, via_init_one_#t~ret257#1, via_init_one_#t~nondet256#1, via_init_one_#t~ret258#1, via_init_one_#t~ret259#1, via_init_one_#t~ret261#1, via_init_one_#t~ret262#1, via_init_one_#t~ret264#1, via_init_one_#t~mem265#1, via_init_one_#t~ret266#1, via_init_one_#t~ret267#1, via_init_one_#t~mem268#1, via_init_one_#t~ret269#1, via_init_one_#t~ret270#1, via_init_one_#t~ret271#1, via_init_one_#t~nondet260#1, via_init_one_#t~nondet263#1, via_init_one_#t~nondet272#1, via_init_one_#t~ret273#1, via_init_one_#t~mem274#1, via_init_one_#t~ret275#1, via_init_one_#t~mem276#1, via_init_one_#t~ret277#1, via_init_one_#t~ret278#1, via_init_one_#t~mem279#1, via_init_one_#t~ret280#1, via_init_one_#t~ret281#1, via_init_one_#t~ret282#1, via_init_one_#t~mem283#1, via_init_one_#t~ret284#1, via_init_one_#t~mem285#1, via_init_one_#t~ret286#1, via_init_one_#t~mem287#1, via_init_one_#t~ret288#1, via_init_one_#t~mem289#1, via_init_one_#t~ret290#1, via_init_one_#t~mem292#1, via_init_one_#t~ret294#1, via_init_one_#t~mem295#1, via_init_one_#t~ret296#1, via_init_one_#t~mem298#1, via_init_one_#t~ret300#1, via_init_one_#t~nondet293#1, via_init_one_#t~nondet299#1, via_init_one_#t~nondet301#1, via_init_one_~pcidev#1.base, via_init_one_~pcidev#1.offset, via_init_one_~id#1.base, via_init_one_~id#1.offset, via_init_one_~rc~1#1, via_init_one_~temp~4#1, via_init_one_~#oldPCI_40~0#1.base, via_init_one_~#oldPCI_40~0#1.offset, via_init_one_~#oldPCI_44~0#1.base, via_init_one_~#oldPCI_44~0#1.offset, via_init_one_~#bTmp~8#1.base, via_init_one_~#bTmp~8#1.offset, via_init_one_~#bTmp1~0#1.base, via_init_one_~#bTmp1~0#1.offset, via_init_one_~Chipset~0#1, via_init_one_~FirDRQ1~0#1, via_init_one_~FirDRQ0~0#1, via_init_one_~FirIRQ~0#1, via_init_one_~FirIOBase~0#1, via_init_one_~#info~0#1.base, via_init_one_~#info~0#1.offset, via_init_one_~tmp~28#1, via_init_one_~tmp___0~6#1, via_init_one_~tmp___1~3#1, via_init_one_~tmp___2~1#1, via_init_one_~tmp___3~0#1, via_init_one_~tmp___4~0#1, via_init_one_~tmp___5~0#1;via_init_one_~pcidev#1.base, via_init_one_~pcidev#1.offset := via_init_one_#in~pcidev#1.base, via_init_one_#in~pcidev#1.offset;via_init_one_~id#1.base, via_init_one_~id#1.offset := via_init_one_#in~id#1.base, via_init_one_#in~id#1.offset;havoc via_init_one_~rc~1#1;havoc via_init_one_~temp~4#1;call via_init_one_~#oldPCI_40~0#1.base, via_init_one_~#oldPCI_40~0#1.offset := #Ultimate.allocOnStack(1);call via_init_one_~#oldPCI_44~0#1.base, via_init_one_~#oldPCI_44~0#1.offset := #Ultimate.allocOnStack(1);call via_init_one_~#bTmp~8#1.base, via_init_one_~#bTmp~8#1.offset := #Ultimate.allocOnStack(1);call via_init_one_~#bTmp1~0#1.base, via_init_one_~#bTmp1~0#1.offset := #Ultimate.allocOnStack(1);havoc via_init_one_~Chipset~0#1;havoc via_init_one_~FirDRQ1~0#1;havoc via_init_one_~FirDRQ0~0#1;havoc via_init_one_~FirIRQ~0#1;havoc via_init_one_~FirIOBase~0#1;call via_init_one_~#info~0#1.base, via_init_one_~#info~0#1.offset := #Ultimate.allocOnStack(72);havoc via_init_one_~tmp~28#1;havoc via_init_one_~tmp___0~6#1;havoc via_init_one_~tmp___1~3#1;havoc via_init_one_~tmp___2~1#1;havoc via_init_one_~tmp___3~0#1;havoc via_init_one_~tmp___4~0#1;havoc via_init_one_~tmp___5~0#1; {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} is VALID [2022-02-20 23:01:02,754 INFO L290 TraceCheckUtils]: 89: Hoare triple {13652#(<= (+ 3 (* 4294967296 (div ~irda_debug~0 4294967296))) ~irda_debug~0)} assume !(~irda_debug~0 % 4294967296 > 1); {13651#false} is VALID [2022-02-20 23:01:02,754 INFO L290 TraceCheckUtils]: 90: Hoare triple {13651#false} assume { :begin_inline_pci_enable_device } true;pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset := via_init_one_~pcidev#1.base, via_init_one_~pcidev#1.offset;havoc pci_enable_device_#res#1;havoc pci_enable_device_#t~nondet989#1, pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset;pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset := pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset;assume -2147483648 <= pci_enable_device_#t~nondet989#1 && pci_enable_device_#t~nondet989#1 <= 2147483647;pci_enable_device_#res#1 := pci_enable_device_#t~nondet989#1;havoc pci_enable_device_#t~nondet989#1; {13651#false} is VALID [2022-02-20 23:01:02,754 INFO L290 TraceCheckUtils]: 91: Hoare triple {13651#false} via_init_one_#t~ret249#1 := pci_enable_device_#res#1;assume { :end_inline_pci_enable_device } true;assume -2147483648 <= via_init_one_#t~ret249#1 && via_init_one_#t~ret249#1 <= 2147483647;via_init_one_~rc~1#1 := via_init_one_#t~ret249#1;havoc via_init_one_#t~ret249#1; {13651#false} is VALID [2022-02-20 23:01:02,755 INFO L290 TraceCheckUtils]: 92: Hoare triple {13651#false} assume 0 != via_init_one_~rc~1#1;havoc via_init_one_#t~nondet250#1;via_init_one_#res#1 := -19;call ULTIMATE.dealloc(via_init_one_~#oldPCI_40~0#1.base, via_init_one_~#oldPCI_40~0#1.offset);havoc via_init_one_~#oldPCI_40~0#1.base, via_init_one_~#oldPCI_40~0#1.offset;call ULTIMATE.dealloc(via_init_one_~#oldPCI_44~0#1.base, via_init_one_~#oldPCI_44~0#1.offset);havoc via_init_one_~#oldPCI_44~0#1.base, via_init_one_~#oldPCI_44~0#1.offset;call ULTIMATE.dealloc(via_init_one_~#bTmp~8#1.base, via_init_one_~#bTmp~8#1.offset);havoc via_init_one_~#bTmp~8#1.base, via_init_one_~#bTmp~8#1.offset;call ULTIMATE.dealloc(via_init_one_~#bTmp1~0#1.base, via_init_one_~#bTmp1~0#1.offset);havoc via_init_one_~#bTmp1~0#1.base, via_init_one_~#bTmp1~0#1.offset;call ULTIMATE.dealloc(via_init_one_~#info~0#1.base, via_init_one_~#info~0#1.offset);havoc via_init_one_~#info~0#1.base, via_init_one_~#info~0#1.offset; {13651#false} is VALID [2022-02-20 23:01:02,755 INFO L290 TraceCheckUtils]: 93: Hoare triple {13651#false} ldv_pci_instance_probe_2_17_#t~ret853#1 := via_init_one_#res#1;assume { :end_inline_via_init_one } true;assume -2147483648 <= ldv_pci_instance_probe_2_17_#t~ret853#1 && ldv_pci_instance_probe_2_17_#t~ret853#1 <= 2147483647;ldv_pci_instance_probe_2_17_~tmp~56#1 := ldv_pci_instance_probe_2_17_#t~ret853#1;havoc ldv_pci_instance_probe_2_17_#t~ret853#1;ldv_pci_instance_probe_2_17_#res#1 := ldv_pci_instance_probe_2_17_~tmp~56#1; {13651#false} is VALID [2022-02-20 23:01:02,755 INFO L290 TraceCheckUtils]: 94: Hoare triple {13651#false} ldv_pci_pci_instance_2_#t~ret872#1 := ldv_pci_instance_probe_2_17_#res#1;assume { :end_inline_ldv_pci_instance_probe_2_17 } true;assume -2147483648 <= ldv_pci_pci_instance_2_#t~ret872#1 && ldv_pci_pci_instance_2_#t~ret872#1 <= 2147483647;ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1 := ldv_pci_pci_instance_2_#t~ret872#1;havoc ldv_pci_pci_instance_2_#t~mem871#1.base, ldv_pci_pci_instance_2_#t~mem871#1.offset;havoc ldv_pci_pci_instance_2_#t~ret872#1;assume { :begin_inline_ldv_ldv_post_probe_28 } true;ldv_ldv_post_probe_28_#in~ldv_func_arg1#1 := ldv_pci_pci_instance_2_~ldv_2_ret_default~0#1;havoc ldv_ldv_post_probe_28_#res#1;havoc ldv_ldv_post_probe_28_#t~ret912#1, ldv_ldv_post_probe_28_~ldv_func_arg1#1, ldv_ldv_post_probe_28_~tmp~68#1;ldv_ldv_post_probe_28_~ldv_func_arg1#1 := ldv_ldv_post_probe_28_#in~ldv_func_arg1#1;havoc ldv_ldv_post_probe_28_~tmp~68#1;assume { :begin_inline_ldv_check_return_value_probe } true;ldv_check_return_value_probe_#in~retval#1 := ldv_ldv_post_probe_28_~ldv_func_arg1#1;havoc ldv_check_return_value_probe_~retval#1;ldv_check_return_value_probe_~retval#1 := ldv_check_return_value_probe_#in~retval#1; {13651#false} is VALID [2022-02-20 23:01:02,755 INFO L290 TraceCheckUtils]: 95: Hoare triple {13651#false} assume 0 != ldv_check_return_value_probe_~retval#1;assume { :begin_inline_ldv_assert_linux_usb_dev__probe_failed } true;ldv_assert_linux_usb_dev__probe_failed_#in~expr#1 := (if 0 == ~LDV_USB_DEV_REF_COUNTS~0 then 1 else 0);havoc ldv_assert_linux_usb_dev__probe_failed_~expr#1;ldv_assert_linux_usb_dev__probe_failed_~expr#1 := ldv_assert_linux_usb_dev__probe_failed_#in~expr#1; {13651#false} is VALID [2022-02-20 23:01:02,755 INFO L290 TraceCheckUtils]: 96: Hoare triple {13651#false} assume 0 == ldv_assert_linux_usb_dev__probe_failed_~expr#1; {13651#false} is VALID [2022-02-20 23:01:02,755 INFO L290 TraceCheckUtils]: 97: Hoare triple {13651#false} assume !false; {13651#false} is VALID [2022-02-20 23:01:02,756 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 120 trivial. 0 not checked. [2022-02-20 23:01:02,756 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 23:01:02,756 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2005873961] [2022-02-20 23:01:02,756 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2005873961] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 23:01:02,757 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 23:01:02,757 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-20 23:01:02,757 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498826766] [2022-02-20 23:01:02,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 23:01:02,758 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) Word has length 98 [2022-02-20 23:01:02,759 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 23:01:02,759 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2022-02-20 23:01:02,820 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 23:01:02,820 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-02-20 23:01:02,820 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 23:01:02,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-20 23:01:02,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-20 23:01:02,821 INFO L87 Difference]: Start difference. First operand 1819 states and 2627 transitions. Second operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2022-02-20 23:01:35,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 23:01:35,565 INFO L93 Difference]: Finished difference Result 5443 states and 7935 transitions. [2022-02-20 23:01:35,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-02-20 23:01:35,567 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) Word has length 98 [2022-02-20 23:01:35,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 23:01:35,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2022-02-20 23:01:36,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 7935 transitions. [2022-02-20 23:01:36,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 9.0) internal successors, (36), 3 states have internal predecessors, (36), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2022-02-20 23:01:36,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 7935 transitions. [2022-02-20 23:01:36,609 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 7935 transitions.