./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--net--irda--via-ircc.ko-entry_point.cil.out.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--net--irda--via-ircc.ko-entry_point.cil.out.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash f665efa4a665554cf7543e013a29ff4c6ab086907b4fe7628b89c7f514f54a81 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 22:29:56,801 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 22:29:56,803 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 22:29:56,826 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 22:29:56,826 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 22:29:56,828 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 22:29:56,830 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 22:29:56,832 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 22:29:56,833 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 22:29:56,836 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 22:29:56,837 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 22:29:56,838 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 22:29:56,838 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 22:29:56,840 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 22:29:56,841 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 22:29:56,842 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 22:29:56,843 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 22:29:56,843 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 22:29:56,846 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 22:29:56,850 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 22:29:56,850 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 22:29:56,851 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 22:29:56,852 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 22:29:56,853 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 22:29:56,857 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 22:29:56,857 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 22:29:56,857 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 22:29:56,858 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 22:29:56,858 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 22:29:56,859 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 22:29:56,859 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 22:29:56,860 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 22:29:56,861 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 22:29:56,862 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 22:29:56,862 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 22:29:56,862 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 22:29:56,863 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 22:29:56,863 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 22:29:56,863 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 22:29:56,864 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 22:29:56,865 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 22:29:56,865 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 22:29:56,890 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 22:29:56,891 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 22:29:56,898 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 22:29:56,898 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 22:29:56,898 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 22:29:56,898 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 22:29:56,899 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 22:29:56,899 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 22:29:56,899 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 22:29:56,899 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 22:29:56,899 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 22:29:56,900 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 22:29:56,900 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 22:29:56,900 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 22:29:56,900 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 22:29:56,901 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 22:29:56,901 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 22:29:56,901 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 22:29:56,901 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 22:29:56,901 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 22:29:56,901 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 22:29:56,902 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:29:56,902 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 22:29:56,902 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 22:29:56,902 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 22:29:56,902 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 22:29:56,903 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 22:29:56,903 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 22:29:56,903 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 22:29:56,903 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 22:29:56,904 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> f665efa4a665554cf7543e013a29ff4c6ab086907b4fe7628b89c7f514f54a81 [2022-02-20 22:29:57,079 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 22:29:57,091 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 22:29:57,093 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 22:29:57,094 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 22:29:57,094 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 22:29:57,095 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--net--irda--via-ircc.ko-entry_point.cil.out.i [2022-02-20 22:29:57,133 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/36bb85140/e92a89eaf9bd4a0da8be841b0aa8a1ef/FLAG744da8976 [2022-02-20 22:29:57,778 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 22:29:57,779 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--net--irda--via-ircc.ko-entry_point.cil.out.i [2022-02-20 22:29:57,811 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/36bb85140/e92a89eaf9bd4a0da8be841b0aa8a1ef/FLAG744da8976 [2022-02-20 22:29:58,198 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/36bb85140/e92a89eaf9bd4a0da8be841b0aa8a1ef [2022-02-20 22:29:58,199 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 22:29:58,200 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 22:29:58,201 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 22:29:58,201 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 22:29:58,204 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 22:29:58,205 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:29:58" (1/1) ... [2022-02-20 22:29:58,206 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6362fb73 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:58, skipping insertion in model container [2022-02-20 22:29:58,206 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:29:58" (1/1) ... [2022-02-20 22:29:58,210 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 22:29:58,280 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 22:29:59,366 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--net--irda--via-ircc.ko-entry_point.cil.out.i[298813,298826] [2022-02-20 22:29:59,396 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:29:59,421 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 22:29:59,648 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--net--irda--via-ircc.ko-entry_point.cil.out.i[298813,298826] [2022-02-20 22:29:59,653 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:29:59,709 INFO L208 MainTranslator]: Completed translation [2022-02-20 22:29:59,710 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59 WrapperNode [2022-02-20 22:29:59,711 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 22:29:59,712 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 22:29:59,712 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 22:29:59,712 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 22:29:59,717 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:29:59,774 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:29:59,907 INFO L137 Inliner]: procedures = 237, calls = 2052, calls flagged for inlining = 107, calls inlined = 104, statements flattened = 4644 [2022-02-20 22:29:59,908 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 22:29:59,908 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 22:29:59,908 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 22:29:59,909 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 22:29:59,915 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:29:59,916 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:29:59,959 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:29:59,960 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:30:00,074 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:30:00,095 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:30:00,110 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:30:00,146 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 22:30:00,156 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 22:30:00,156 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 22:30:00,156 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 22:30:00,157 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (1/1) ... [2022-02-20 22:30:00,167 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:30:00,177 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:30:00,189 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 22:30:00,195 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 22:30:00,212 INFO L130 BoogieDeclarations]: Found specification of procedure ResetChip [2022-02-20 22:30:00,213 INFO L138 BoogieDeclarations]: Found implementation of procedure ResetChip [2022-02-20 22:30:00,213 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_ioctl [2022-02-20 22:30:00,213 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_ioctl [2022-02-20 22:30:00,213 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2022-02-20 22:30:00,213 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2022-02-20 22:30:00,213 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 22:30:00,214 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 22:30:00,214 INFO L130 BoogieDeclarations]: Found specification of procedure RxCurCount [2022-02-20 22:30:00,214 INFO L138 BoogieDeclarations]: Found implementation of procedure RxCurCount [2022-02-20 22:30:00,214 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2022-02-20 22:30:00,216 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2022-02-20 22:30:00,217 INFO L130 BoogieDeclarations]: Found specification of procedure irda_device_txqueue_empty [2022-02-20 22:30:00,217 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_device_txqueue_empty [2022-02-20 22:30:00,217 INFO L130 BoogieDeclarations]: Found specification of procedure irda_setup_dma [2022-02-20 22:30:00,217 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_setup_dma [2022-02-20 22:30:00,217 INFO L130 BoogieDeclarations]: Found specification of procedure netif_wake_queue [2022-02-20 22:30:00,217 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_wake_queue [2022-02-20 22:30:00,217 INFO L130 BoogieDeclarations]: Found specification of procedure debug_lockdep_rcu_enabled [2022-02-20 22:30:00,217 INFO L138 BoogieDeclarations]: Found implementation of procedure debug_lockdep_rcu_enabled [2022-02-20 22:30:00,217 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock [2022-02-20 22:30:00,218 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock [2022-02-20 22:30:00,218 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 22:30:00,218 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 22:30:00,218 INFO L130 BoogieDeclarations]: Found specification of procedure pci_read_config_byte [2022-02-20 22:30:00,218 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_read_config_byte [2022-02-20 22:30:00,218 INFO L130 BoogieDeclarations]: Found specification of procedure Sdelay [2022-02-20 22:30:00,218 INFO L138 BoogieDeclarations]: Found implementation of procedure Sdelay [2022-02-20 22:30:00,218 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2022-02-20 22:30:00,219 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2022-02-20 22:30:00,219 INFO L130 BoogieDeclarations]: Found specification of procedure CheckRegBit [2022-02-20 22:30:00,219 INFO L138 BoogieDeclarations]: Found implementation of procedure CheckRegBit [2022-02-20 22:30:00,219 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2022-02-20 22:30:00,219 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2022-02-20 22:30:00,219 INFO L130 BoogieDeclarations]: Found specification of procedure SetSIR [2022-02-20 22:30:00,219 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSIR [2022-02-20 22:30:00,219 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_speed [2022-02-20 22:30:00,219 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_speed [2022-02-20 22:30:00,220 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2022-02-20 22:30:00,220 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2022-02-20 22:30:00,220 INFO L130 BoogieDeclarations]: Found specification of procedure netif_stop_queue [2022-02-20 22:30:00,220 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_stop_queue [2022-02-20 22:30:00,220 INFO L130 BoogieDeclarations]: Found specification of procedure SetMaxRxPacketSize [2022-02-20 22:30:00,220 INFO L138 BoogieDeclarations]: Found implementation of procedure SetMaxRxPacketSize [2022-02-20 22:30:00,220 INFO L130 BoogieDeclarations]: Found specification of procedure dma_zalloc_coherent [2022-02-20 22:30:00,220 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_zalloc_coherent [2022-02-20 22:30:00,220 INFO L130 BoogieDeclarations]: Found specification of procedure GetRecvByte [2022-02-20 22:30:00,221 INFO L138 BoogieDeclarations]: Found implementation of procedure GetRecvByte [2022-02-20 22:30:00,221 INFO L130 BoogieDeclarations]: Found specification of procedure consume_skb [2022-02-20 22:30:00,221 INFO L138 BoogieDeclarations]: Found implementation of procedure consume_skb [2022-02-20 22:30:00,221 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 22:30:00,221 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 22:30:00,221 INFO L130 BoogieDeclarations]: Found specification of procedure SetPulseWidth [2022-02-20 22:30:00,221 INFO L138 BoogieDeclarations]: Found implementation of procedure SetPulseWidth [2022-02-20 22:30:00,222 INFO L130 BoogieDeclarations]: Found specification of procedure Tdelay [2022-02-20 22:30:00,222 INFO L138 BoogieDeclarations]: Found implementation of procedure Tdelay [2022-02-20 22:30:00,222 INFO L130 BoogieDeclarations]: Found specification of procedure netif_rx [2022-02-20 22:30:00,223 INFO L138 BoogieDeclarations]: Found implementation of procedure netif_rx [2022-02-20 22:30:00,223 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock [2022-02-20 22:30:00,223 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock [2022-02-20 22:30:00,224 INFO L130 BoogieDeclarations]: Found specification of procedure hwreset [2022-02-20 22:30:00,224 INFO L138 BoogieDeclarations]: Found implementation of procedure hwreset [2022-02-20 22:30:00,225 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2022-02-20 22:30:00,225 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2022-02-20 22:30:00,225 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 22:30:00,225 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 22:30:00,225 INFO L130 BoogieDeclarations]: Found specification of procedure ClkTx [2022-02-20 22:30:00,225 INFO L138 BoogieDeclarations]: Found implementation of procedure ClkTx [2022-02-20 22:30:00,225 INFO L130 BoogieDeclarations]: Found specification of procedure WriteLPCReg [2022-02-20 22:30:00,226 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteLPCReg [2022-02-20 22:30:00,226 INFO L130 BoogieDeclarations]: Found specification of procedure capable [2022-02-20 22:30:00,226 INFO L138 BoogieDeclarations]: Found implementation of procedure capable [2022-02-20 22:30:00,226 INFO L130 BoogieDeclarations]: Found specification of procedure pci_write_config_byte [2022-02-20 22:30:00,226 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_write_config_byte [2022-02-20 22:30:00,226 INFO L130 BoogieDeclarations]: Found specification of procedure CommonInit [2022-02-20 22:30:00,226 INFO L138 BoogieDeclarations]: Found implementation of procedure CommonInit [2022-02-20 22:30:00,226 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_priv [2022-02-20 22:30:00,227 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_priv [2022-02-20 22:30:00,227 INFO L130 BoogieDeclarations]: Found specification of procedure outb [2022-02-20 22:30:00,227 INFO L138 BoogieDeclarations]: Found implementation of procedure outb [2022-02-20 22:30:00,227 INFO L130 BoogieDeclarations]: Found specification of procedure netdev_get_tx_queue [2022-02-20 22:30:00,227 INFO L138 BoogieDeclarations]: Found implementation of procedure netdev_get_tx_queue [2022-02-20 22:30:00,228 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_change_dongle_speed [2022-02-20 22:30:00,228 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_change_dongle_speed [2022-02-20 22:30:00,228 INFO L130 BoogieDeclarations]: Found specification of procedure ReadLPCReg [2022-02-20 22:30:00,228 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadLPCReg [2022-02-20 22:30:00,228 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2022-02-20 22:30:00,228 INFO L130 BoogieDeclarations]: Found specification of procedure free_dma [2022-02-20 22:30:00,228 INFO L138 BoogieDeclarations]: Found implementation of procedure free_dma [2022-02-20 22:30:00,228 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_receive [2022-02-20 22:30:00,229 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_receive [2022-02-20 22:30:00,229 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2022-02-20 22:30:00,229 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_dma_xmit [2022-02-20 22:30:00,229 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_dma_xmit [2022-02-20 22:30:00,229 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reserve [2022-02-20 22:30:00,229 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reserve [2022-02-20 22:30:00,230 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_close [2022-02-20 22:30:00,230 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_close [2022-02-20 22:30:00,230 INFO L130 BoogieDeclarations]: Found specification of procedure dma_free_attrs [2022-02-20 22:30:00,230 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_free_attrs [2022-02-20 22:30:00,231 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 22:30:00,231 INFO L130 BoogieDeclarations]: Found specification of procedure free_netdev [2022-02-20 22:30:00,231 INFO L138 BoogieDeclarations]: Found implementation of procedure free_netdev [2022-02-20 22:30:00,231 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2022-02-20 22:30:00,231 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2022-02-20 22:30:00,231 INFO L130 BoogieDeclarations]: Found specification of procedure CkRxRecv [2022-02-20 22:30:00,231 INFO L138 BoogieDeclarations]: Found implementation of procedure CkRxRecv [2022-02-20 22:30:00,232 INFO L130 BoogieDeclarations]: Found specification of procedure rcu_is_watching [2022-02-20 22:30:00,232 INFO L138 BoogieDeclarations]: Found implementation of procedure rcu_is_watching [2022-02-20 22:30:00,232 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_alloc_flags [2022-02-20 22:30:00,232 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_alloc_flags [2022-02-20 22:30:00,232 INFO L130 BoogieDeclarations]: Found specification of procedure irda_get_next_speed [2022-02-20 22:30:00,232 INFO L138 BoogieDeclarations]: Found implementation of procedure irda_get_next_speed [2022-02-20 22:30:00,232 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2022-02-20 22:30:00,233 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2022-02-20 22:30:00,233 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 22:30:00,233 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2022-02-20 22:30:00,233 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2022-02-20 22:30:00,233 INFO L130 BoogieDeclarations]: Found specification of procedure net_ratelimit [2022-02-20 22:30:00,234 INFO L138 BoogieDeclarations]: Found implementation of procedure net_ratelimit [2022-02-20 22:30:00,235 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendByte [2022-02-20 22:30:00,236 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendByte [2022-02-20 22:30:00,236 INFO L130 BoogieDeclarations]: Found specification of procedure dev_alloc_skb [2022-02-20 22:30:00,236 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_alloc_skb [2022-02-20 22:30:00,236 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2022-02-20 22:30:00,237 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2022-02-20 22:30:00,237 INFO L130 BoogieDeclarations]: Found specification of procedure ReadReg [2022-02-20 22:30:00,237 INFO L138 BoogieDeclarations]: Found implementation of procedure ReadReg [2022-02-20 22:30:00,237 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_open [2022-02-20 22:30:00,241 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_open [2022-02-20 22:30:00,241 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_init_zalloc [2022-02-20 22:30:00,241 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_init_zalloc [2022-02-20 22:30:00,242 INFO L130 BoogieDeclarations]: Found specification of procedure WriteRegBit [2022-02-20 22:30:00,242 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteRegBit [2022-02-20 22:30:00,242 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 22:30:00,242 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Indx [2022-02-20 22:30:00,242 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Indx [2022-02-20 22:30:00,242 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_memset [2022-02-20 22:30:00,242 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_memset [2022-02-20 22:30:00,242 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 22:30:00,242 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2022-02-20 22:30:00,242 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2022-02-20 22:30:00,242 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-02-20 22:30:00,243 INFO L130 BoogieDeclarations]: Found specification of procedure lockdep_rcu_suspicious [2022-02-20 22:30:00,243 INFO L138 BoogieDeclarations]: Found implementation of procedure lockdep_rcu_suspicious [2022-02-20 22:30:00,243 INFO L130 BoogieDeclarations]: Found specification of procedure __bad_percpu_size [2022-02-20 22:30:00,243 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2022-02-20 22:30:00,243 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2022-02-20 22:30:00,243 INFO L130 BoogieDeclarations]: Found specification of procedure WriteReg [2022-02-20 22:30:00,243 INFO L138 BoogieDeclarations]: Found implementation of procedure WriteReg [2022-02-20 22:30:00,243 INFO L130 BoogieDeclarations]: Found specification of procedure SetSendPreambleCount [2022-02-20 22:30:00,243 INFO L138 BoogieDeclarations]: Found implementation of procedure SetSendPreambleCount [2022-02-20 22:30:00,243 INFO L130 BoogieDeclarations]: Found specification of procedure InitCard [2022-02-20 22:30:00,243 INFO L138 BoogieDeclarations]: Found implementation of procedure InitCard [2022-02-20 22:30:00,244 INFO L130 BoogieDeclarations]: Found specification of procedure SetTimer [2022-02-20 22:30:00,244 INFO L138 BoogieDeclarations]: Found implementation of procedure SetTimer [2022-02-20 22:30:00,244 INFO L130 BoogieDeclarations]: Found specification of procedure ActClk [2022-02-20 22:30:00,244 INFO L138 BoogieDeclarations]: Found implementation of procedure ActClk [2022-02-20 22:30:00,244 INFO L130 BoogieDeclarations]: Found specification of procedure SetBaudRate [2022-02-20 22:30:00,244 INFO L138 BoogieDeclarations]: Found implementation of procedure SetBaudRate [2022-02-20 22:30:00,244 INFO L130 BoogieDeclarations]: Found specification of procedure Wr_Byte [2022-02-20 22:30:00,244 INFO L138 BoogieDeclarations]: Found implementation of procedure Wr_Byte [2022-02-20 22:30:00,244 INFO L130 BoogieDeclarations]: Found specification of procedure skb_put [2022-02-20 22:30:00,244 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_put [2022-02-20 22:30:00,244 INFO L130 BoogieDeclarations]: Found specification of procedure request_dma [2022-02-20 22:30:00,245 INFO L138 BoogieDeclarations]: Found implementation of procedure request_dma [2022-02-20 22:30:00,245 INFO L130 BoogieDeclarations]: Found specification of procedure inb [2022-02-20 22:30:00,245 INFO L138 BoogieDeclarations]: Found implementation of procedure inb [2022-02-20 22:30:00,245 INFO L130 BoogieDeclarations]: Found specification of procedure rcu_read_unlock [2022-02-20 22:30:00,245 INFO L138 BoogieDeclarations]: Found implementation of procedure rcu_read_unlock [2022-02-20 22:30:00,245 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 22:30:00,245 INFO L130 BoogieDeclarations]: Found specification of procedure skb_reset_mac_header [2022-02-20 22:30:00,245 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_reset_mac_header [2022-02-20 22:30:00,245 INFO L130 BoogieDeclarations]: Found specification of procedure via_ircc_net_open [2022-02-20 22:30:00,245 INFO L138 BoogieDeclarations]: Found implementation of procedure via_ircc_net_open [2022-02-20 22:30:00,246 INFO L130 BoogieDeclarations]: Found specification of procedure skb_copy_to_linear_data [2022-02-20 22:30:00,246 INFO L138 BoogieDeclarations]: Found implementation of procedure skb_copy_to_linear_data [2022-02-20 22:30:00,246 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 22:30:00,246 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 22:30:00,691 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 22:30:00,693 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 22:30:01,050 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 22:30:05,227 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 22:30:05,255 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 22:30:05,258 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-02-20 22:30:05,261 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:30:05 BoogieIcfgContainer [2022-02-20 22:30:05,261 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 22:30:05,262 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 22:30:05,262 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 22:30:05,265 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 22:30:05,265 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 10:29:58" (1/3) ... [2022-02-20 22:30:05,265 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@44d687f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:30:05, skipping insertion in model container [2022-02-20 22:30:05,265 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:29:59" (2/3) ... [2022-02-20 22:30:05,266 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@44d687f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:30:05, skipping insertion in model container [2022-02-20 22:30:05,266 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:30:05" (3/3) ... [2022-02-20 22:30:05,267 INFO L111 eAbstractionObserver]: Analyzing ICFG linux-4.2-rc1.tar.xz-43_2a-drivers--net--irda--via-ircc.ko-entry_point.cil.out.i [2022-02-20 22:30:05,270 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 22:30:05,270 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-02-20 22:30:05,310 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 22:30:05,313 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 22:30:05,314 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-02-20 22:30:05,365 INFO L276 IsEmpty]: Start isEmpty. Operand has 1913 states, 1213 states have (on average 1.3437757625721352) internal successors, (1630), 1244 states have internal predecessors, (1630), 618 states have call successors, (618), 81 states have call predecessors, (618), 80 states have return successors, (611), 600 states have call predecessors, (611), 611 states have call successors, (611) [2022-02-20 22:30:05,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-02-20 22:30:05,424 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:30:05,425 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:30:05,425 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:30:05,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:30:05,429 INFO L85 PathProgramCache]: Analyzing trace with hash 2066397638, now seen corresponding path program 1 times [2022-02-20 22:30:05,435 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:30:05,436 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264868256] [2022-02-20 22:30:05,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:30:05,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:30:05,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:05,940 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:30:05,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:05,963 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:05,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:05,976 INFO L290 TraceCheckUtils]: 0: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:05,976 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:05,977 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:05,978 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:05,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:05,987 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:05,988 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:05,989 INFO L290 TraceCheckUtils]: 2: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:05,989 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:05,989 INFO L290 TraceCheckUtils]: 0: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:05,990 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:05,990 INFO L290 TraceCheckUtils]: 2: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:05,990 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:05,991 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:05,991 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:05,991 INFO L272 TraceCheckUtils]: 6: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:05,991 INFO L290 TraceCheckUtils]: 7: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:05,992 INFO L290 TraceCheckUtils]: 8: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:05,992 INFO L290 TraceCheckUtils]: 9: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:05,992 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:05,992 INFO L290 TraceCheckUtils]: 11: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:05,992 INFO L290 TraceCheckUtils]: 12: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:05,992 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1917#false} {1916#true} #4821#return; {1917#false} is VALID [2022-02-20 22:30:05,993 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 18 [2022-02-20 22:30:05,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,017 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:06,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,028 INFO L290 TraceCheckUtils]: 0: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,029 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,030 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,043 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:06,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,050 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,051 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,051 INFO L290 TraceCheckUtils]: 2: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,051 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,051 INFO L290 TraceCheckUtils]: 0: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:06,052 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:06,052 INFO L290 TraceCheckUtils]: 2: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,054 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,054 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,054 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:06,054 INFO L272 TraceCheckUtils]: 6: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:06,054 INFO L290 TraceCheckUtils]: 7: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,055 INFO L290 TraceCheckUtils]: 8: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,055 INFO L290 TraceCheckUtils]: 9: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,055 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,055 INFO L290 TraceCheckUtils]: 11: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:06,055 INFO L290 TraceCheckUtils]: 12: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,056 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1917#false} {1917#false} #4823#return; {1917#false} is VALID [2022-02-20 22:30:06,056 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 34 [2022-02-20 22:30:06,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,072 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:06,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,084 INFO L290 TraceCheckUtils]: 0: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,084 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,085 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,085 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:06,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,095 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,096 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,098 INFO L290 TraceCheckUtils]: 2: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,099 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,099 INFO L290 TraceCheckUtils]: 0: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:06,100 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:06,100 INFO L290 TraceCheckUtils]: 2: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,102 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,102 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,102 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:06,102 INFO L272 TraceCheckUtils]: 6: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:06,102 INFO L290 TraceCheckUtils]: 7: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,107 INFO L290 TraceCheckUtils]: 8: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,107 INFO L290 TraceCheckUtils]: 9: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,108 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,108 INFO L290 TraceCheckUtils]: 11: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:06,108 INFO L290 TraceCheckUtils]: 12: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,108 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1917#false} {1917#false} #4825#return; {1917#false} is VALID [2022-02-20 22:30:06,109 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 50 [2022-02-20 22:30:06,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,125 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:06,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,131 INFO L290 TraceCheckUtils]: 0: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,131 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,131 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,132 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:06,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,141 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,141 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,142 INFO L290 TraceCheckUtils]: 2: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,142 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,142 INFO L290 TraceCheckUtils]: 0: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:06,143 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:06,143 INFO L290 TraceCheckUtils]: 2: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,143 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,143 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,144 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:06,144 INFO L272 TraceCheckUtils]: 6: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:06,144 INFO L290 TraceCheckUtils]: 7: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,144 INFO L290 TraceCheckUtils]: 8: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,144 INFO L290 TraceCheckUtils]: 9: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,144 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,145 INFO L290 TraceCheckUtils]: 11: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:06,145 INFO L290 TraceCheckUtils]: 12: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,145 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1917#false} {1917#false} #4827#return; {1917#false} is VALID [2022-02-20 22:30:06,146 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 66 [2022-02-20 22:30:06,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,162 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:06,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,171 INFO L290 TraceCheckUtils]: 0: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,171 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,171 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,172 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:06,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,180 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,181 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,181 INFO L290 TraceCheckUtils]: 2: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,181 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,182 INFO L290 TraceCheckUtils]: 0: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:06,183 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:06,183 INFO L290 TraceCheckUtils]: 2: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,183 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,183 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,183 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:06,183 INFO L272 TraceCheckUtils]: 6: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:06,184 INFO L290 TraceCheckUtils]: 7: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,185 INFO L290 TraceCheckUtils]: 8: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,186 INFO L290 TraceCheckUtils]: 9: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,186 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,186 INFO L290 TraceCheckUtils]: 11: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:06,186 INFO L290 TraceCheckUtils]: 12: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,186 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1917#false} {1917#false} #4829#return; {1917#false} is VALID [2022-02-20 22:30:06,192 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 83 [2022-02-20 22:30:06,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,204 INFO L290 TraceCheckUtils]: 0: Hoare triple {2088#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~s#1.base, ~s#1.offset := #in~s#1.base, #in~s#1.offset;~c#1 := #in~c#1;~n#1 := #in~n#1;havoc ~tmp~3#1.base, ~tmp~3#1.offset;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := ~s#1.base, ~s#1.offset, ~c#1, ~n#1;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr938#1;#Ultimate.C_memset_#t~loopctr938#1 := 0; {1916#true} is VALID [2022-02-20 22:30:06,205 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume !(#Ultimate.C_memset_#t~loopctr938#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {1916#true} is VALID [2022-02-20 22:30:06,205 INFO L290 TraceCheckUtils]: 2: Hoare triple {1916#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;#t~memset~res23#1.base, #t~memset~res23#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;~tmp~3#1.base, ~tmp~3#1.offset := ~s#1.base, ~s#1.offset;havoc #t~memset~res23#1.base, #t~memset~res23#1.offset;#res#1.base, #res#1.offset := ~tmp~3#1.base, ~tmp~3#1.offset; {1916#true} is VALID [2022-02-20 22:30:06,205 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,205 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1917#false} #4831#return; {1917#false} is VALID [2022-02-20 22:30:06,206 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 90 [2022-02-20 22:30:06,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,215 INFO L290 TraceCheckUtils]: 0: Hoare triple {2088#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~s#1.base, ~s#1.offset := #in~s#1.base, #in~s#1.offset;~c#1 := #in~c#1;~n#1 := #in~n#1;havoc ~tmp~3#1.base, ~tmp~3#1.offset;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := ~s#1.base, ~s#1.offset, ~c#1, ~n#1;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr938#1;#Ultimate.C_memset_#t~loopctr938#1 := 0; {1916#true} is VALID [2022-02-20 22:30:06,216 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume !(#Ultimate.C_memset_#t~loopctr938#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {1916#true} is VALID [2022-02-20 22:30:06,217 INFO L290 TraceCheckUtils]: 2: Hoare triple {1916#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;#t~memset~res23#1.base, #t~memset~res23#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;~tmp~3#1.base, ~tmp~3#1.offset := ~s#1.base, ~s#1.offset;havoc #t~memset~res23#1.base, #t~memset~res23#1.offset;#res#1.base, #res#1.offset := ~tmp~3#1.base, ~tmp~3#1.offset; {1916#true} is VALID [2022-02-20 22:30:06,217 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,218 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1917#false} #4833#return; {1917#false} is VALID [2022-02-20 22:30:06,219 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 110 [2022-02-20 22:30:06,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,226 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3008 + ~dev.offset; {1916#true} is VALID [2022-02-20 22:30:06,233 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,235 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1917#false} #4211#return; {1917#false} is VALID [2022-02-20 22:30:06,238 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 115 [2022-02-20 22:30:06,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,244 INFO L290 TraceCheckUtils]: 0: Hoare triple {2089#(= ~ldv_spin~0 |old(~ldv_spin~0)|)} ~ldv_spin~0 := 1; {1916#true} is VALID [2022-02-20 22:30:06,244 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,244 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1917#false} #4213#return; {1917#false} is VALID [2022-02-20 22:30:06,245 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 123 [2022-02-20 22:30:06,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,254 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:06,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,260 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,261 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,261 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,261 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,261 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,261 INFO L290 TraceCheckUtils]: 2: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,262 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,262 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,262 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,262 INFO L290 TraceCheckUtils]: 6: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,262 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1916#true} {1917#false} #4215#return; {1917#false} is VALID [2022-02-20 22:30:06,262 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 133 [2022-02-20 22:30:06,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,268 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {1916#true} is VALID [2022-02-20 22:30:06,268 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,268 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1917#false} #4217#return; {1917#false} is VALID [2022-02-20 22:30:06,269 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 142 [2022-02-20 22:30:06,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,276 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:06,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,282 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,282 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,282 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,283 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,283 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,283 INFO L290 TraceCheckUtils]: 2: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,283 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,283 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,283 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,283 INFO L290 TraceCheckUtils]: 6: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,284 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1916#true} {1917#false} #4311#return; {1917#false} is VALID [2022-02-20 22:30:06,284 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 152 [2022-02-20 22:30:06,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,289 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {1916#true} is VALID [2022-02-20 22:30:06,290 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,290 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1917#false} #4313#return; {1917#false} is VALID [2022-02-20 22:30:06,290 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 161 [2022-02-20 22:30:06,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,307 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:06,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,313 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:06,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,319 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,319 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,319 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,320 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,320 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,320 INFO L290 TraceCheckUtils]: 2: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,320 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,320 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,320 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,320 INFO L290 TraceCheckUtils]: 6: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,321 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1916#true} {1916#true} #4207#return; {1916#true} is VALID [2022-02-20 22:30:06,321 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 22:30:06,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,327 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:06,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:06,333 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,333 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,333 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,333 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,333 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,334 INFO L290 TraceCheckUtils]: 2: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,334 INFO L290 TraceCheckUtils]: 3: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,334 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,334 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,334 INFO L290 TraceCheckUtils]: 6: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,334 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1916#true} {1916#true} #4209#return; {1916#true} is VALID [2022-02-20 22:30:06,335 INFO L290 TraceCheckUtils]: 0: Hoare triple {2088#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~iobase := #in~iobase;~self.base, ~self.offset := #in~self.base, #in~self.offset;havoc ~low~4;havoc ~high~4;havoc ~wTmp~2;havoc ~wTmp1~2;havoc ~ret~0; {1916#true} is VALID [2022-02-20 22:30:06,335 INFO L272 TraceCheckUtils]: 1: Hoare triple {1916#true} call #t~ret178 := ReadReg(~iobase % 65536, 44); {1916#true} is VALID [2022-02-20 22:30:06,335 INFO L290 TraceCheckUtils]: 2: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,335 INFO L272 TraceCheckUtils]: 3: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,335 INFO L290 TraceCheckUtils]: 4: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,335 INFO L290 TraceCheckUtils]: 5: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,335 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,336 INFO L290 TraceCheckUtils]: 7: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,336 INFO L290 TraceCheckUtils]: 8: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,336 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {1916#true} {1916#true} #4207#return; {1916#true} is VALID [2022-02-20 22:30:06,336 INFO L290 TraceCheckUtils]: 10: Hoare triple {1916#true} ~low~4 := #t~ret178;havoc #t~ret178; {1916#true} is VALID [2022-02-20 22:30:06,336 INFO L272 TraceCheckUtils]: 11: Hoare triple {1916#true} call #t~ret179 := ReadReg(~iobase % 65536, 45); {1916#true} is VALID [2022-02-20 22:30:06,336 INFO L290 TraceCheckUtils]: 12: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,336 INFO L272 TraceCheckUtils]: 13: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,337 INFO L290 TraceCheckUtils]: 14: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,337 INFO L290 TraceCheckUtils]: 15: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,337 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,337 INFO L290 TraceCheckUtils]: 17: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,337 INFO L290 TraceCheckUtils]: 18: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,337 INFO L284 TraceCheckUtils]: 19: Hoare quadruple {1916#true} {1916#true} #4209#return; {1916#true} is VALID [2022-02-20 22:30:06,337 INFO L290 TraceCheckUtils]: 20: Hoare triple {1916#true} ~high~4 := #t~ret179;havoc #t~ret179;~wTmp1~2 := ~high~4 % 256;~wTmp~2 := (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 0 == ~low~4 % 256 then (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) else (if 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256) then ~low~4 % 256 else (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256)) || ((1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 1 == ~low~4 % 256) then 1 else ~bitwiseOr((if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536), ~low~4 % 256))));call #t~mem180 := read~int(~self.base, 564 + ~self.offset, 4); {1916#true} is VALID [2022-02-20 22:30:06,338 INFO L290 TraceCheckUtils]: 21: Hoare triple {1916#true} assume ~wTmp~2 % 65536 % 4294967296 >= #t~mem180 % 4294967296;havoc #t~mem180;call #t~mem181 := read~int(~self.base, 564 + ~self.offset, 4);~ret~0 := ~wTmp~2 % 65536 - #t~mem181 % 65536;havoc #t~mem181; {1916#true} is VALID [2022-02-20 22:30:06,338 INFO L290 TraceCheckUtils]: 22: Hoare triple {1916#true} call write~int(~wTmp~2 % 65536, ~self.base, 564 + ~self.offset, 4);#res := ~ret~0; {1916#true} is VALID [2022-02-20 22:30:06,338 INFO L290 TraceCheckUtils]: 23: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,338 INFO L284 TraceCheckUtils]: 24: Hoare quadruple {1916#true} {1917#false} #4317#return; {1917#false} is VALID [2022-02-20 22:30:06,341 INFO L290 TraceCheckUtils]: 0: Hoare triple {1916#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(81, 2);call #Ultimate.allocInit(25, 3);call #Ultimate.allocInit(42, 4);call #Ultimate.allocInit(25, 5);call #Ultimate.allocInit(44, 6);call #Ultimate.allocInit(26, 7);call #Ultimate.allocInit(41, 8);call #Ultimate.allocInit(9, 9);call #Ultimate.allocInit(9, 10);call #Ultimate.allocInit(9, 11);call #Ultimate.allocInit(9, 12);call #Ultimate.allocInit(14, 13);call #Ultimate.allocInit(207, 14);call #Ultimate.allocInit(44, 15);call #Ultimate.allocInit(44, 16);call #Ultimate.allocInit(14, 17);call #Ultimate.allocInit(9, 18);call #Ultimate.allocInit(13, 19);call #Ultimate.allocInit(207, 20);call #Ultimate.allocInit(24, 21);call #Ultimate.allocInit(24, 22);call #Ultimate.allocInit(13, 23);call #Ultimate.allocInit(9, 24);call #Ultimate.allocInit(13, 25);call #Ultimate.allocInit(207, 26);call #Ultimate.allocInit(21, 27);call #Ultimate.allocInit(21, 28);call #Ultimate.allocInit(13, 29);call #Ultimate.allocInit(9, 30);call #Ultimate.allocInit(13, 31);call #Ultimate.allocInit(207, 32);call #Ultimate.allocInit(22, 33);call #Ultimate.allocInit(22, 34);call #Ultimate.allocInit(13, 35);call #Ultimate.allocInit(9, 36);call #Ultimate.allocInit(13, 37);call #Ultimate.allocInit(207, 38);call #Ultimate.allocInit(22, 39);call #Ultimate.allocInit(22, 40);call #Ultimate.allocInit(13, 41);call #Ultimate.allocInit(9, 42);call #Ultimate.allocInit(13, 43);call #Ultimate.allocInit(207, 44);call #Ultimate.allocInit(21, 45);call #Ultimate.allocInit(21, 46);call #Ultimate.allocInit(13, 47);call #Ultimate.allocInit(22, 48);call #Ultimate.allocInit(9, 49);call #Ultimate.allocInit(14, 50);call #Ultimate.allocInit(207, 51);call #Ultimate.allocInit(34, 52);call #Ultimate.allocInit(34, 53);call #Ultimate.allocInit(14, 54);call #Ultimate.allocInit(40, 55);call #Ultimate.allocInit(9, 56);call #Ultimate.allocInit(15, 57);call #Ultimate.allocInit(207, 58);call #Ultimate.allocInit(29, 59);call #Ultimate.allocInit(29, 60);call #Ultimate.allocInit(15, 61);call #Ultimate.allocInit(84, 62);call #Ultimate.allocInit(9, 63);call #Ultimate.allocInit(29, 64);call #Ultimate.allocInit(207, 65);call #Ultimate.allocInit(46, 66);call #Ultimate.allocInit(46, 67);call #Ultimate.allocInit(29, 68);call #Ultimate.allocInit(9, 69);call #Ultimate.allocInit(29, 70);call #Ultimate.allocInit(207, 71);call #Ultimate.allocInit(56, 72);call #Ultimate.allocInit(56, 73);call #Ultimate.allocInit(29, 74);call #Ultimate.allocInit(9, 75);call #Ultimate.allocInit(29, 76);call #Ultimate.allocInit(207, 77);call #Ultimate.allocInit(49, 78);call #Ultimate.allocInit(49, 79);call #Ultimate.allocInit(29, 80);call #Ultimate.allocInit(40, 81);call #Ultimate.allocInit(29, 82);call #Ultimate.allocInit(9, 83);call #Ultimate.allocInit(22, 84);call #Ultimate.allocInit(207, 85);call #Ultimate.allocInit(29, 86);call #Ultimate.allocInit(29, 87);call #Ultimate.allocInit(22, 88);call #Ultimate.allocInit(31, 89);call #Ultimate.allocInit(207, 90);call #Ultimate.allocInit(23, 91);call #Ultimate.allocInit(13, 92);call #Ultimate.allocInit(9, 93);call #Ultimate.allocInit(18, 94);call #Ultimate.allocInit(207, 95);call #Ultimate.allocInit(44, 96);call #Ultimate.allocInit(44, 97);call #Ultimate.allocInit(18, 98);call #Ultimate.allocInit(9, 99);call #Ultimate.allocInit(27, 100);call #Ultimate.allocInit(207, 101);call #Ultimate.allocInit(55, 102);call #Ultimate.allocInit(55, 103);call #Ultimate.allocInit(27, 104);call #Ultimate.allocInit(9, 105);call #Ultimate.allocInit(30, 106);call #Ultimate.allocInit(207, 107);call #Ultimate.allocInit(47, 108);call #Ultimate.allocInit(47, 109);call #Ultimate.allocInit(30, 110);call #Ultimate.allocInit(9, 111);call #Ultimate.allocInit(30, 112);call #Ultimate.allocInit(207, 113);call #Ultimate.allocInit(40, 114);call #Ultimate.allocInit(40, 115);call #Ultimate.allocInit(30, 116);call #Ultimate.allocInit(9, 117);call #Ultimate.allocInit(30, 118);call #Ultimate.allocInit(207, 119);call #Ultimate.allocInit(25, 120);call #Ultimate.allocInit(25, 121);call #Ultimate.allocInit(30, 122);call #Ultimate.allocInit(9, 123);call #Ultimate.allocInit(14, 124);call #Ultimate.allocInit(207, 125);call #Ultimate.allocInit(14, 126);call #Ultimate.allocInit(14, 127);call #Ultimate.allocInit(14, 128);call #Ultimate.allocInit(9, 129);call #Ultimate.allocInit(15, 130);call #Ultimate.allocInit(207, 131);call #Ultimate.allocInit(22, 132);call #Ultimate.allocInit(22, 133);call #Ultimate.allocInit(15, 134);call #Ultimate.allocInit(9, 135);call #Ultimate.allocInit(15, 136);call #Ultimate.allocInit(207, 137);call #Ultimate.allocInit(47, 138);call #Ultimate.allocInit(47, 139);call #Ultimate.allocInit(15, 140);call #Ultimate.allocInit(9, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(207, 143);call #Ultimate.allocInit(42, 144);call #Ultimate.allocInit(42, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(6, 147);call write~init~int(84, 147, 0, 1);call write~init~int(105, 147, 1, 1);call write~init~int(109, 147, 2, 1);call write~init~int(101, 147, 3, 1);call write~init~int(114, 147, 4, 1);call write~init~int(0, 147, 5, 1);call #Ultimate.allocInit(1, 148);call write~init~int(0, 148, 0, 1);call #Ultimate.allocInit(3, 149);call write~init~int(84, 149, 0, 1);call write~init~int(120, 149, 1, 1);call write~init~int(0, 149, 2, 1);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(3, 151);call write~init~int(82, 151, 0, 1);call write~init~int(120, 151, 1, 1);call write~init~int(0, 151, 2, 1);call #Ultimate.allocInit(1, 152);call write~init~int(0, 152, 0, 1);call #Ultimate.allocInit(9, 153);call #Ultimate.allocInit(19, 154);call #Ultimate.allocInit(207, 155);call #Ultimate.allocInit(37, 156);call #Ultimate.allocInit(37, 157);call #Ultimate.allocInit(19, 158);call #Ultimate.allocInit(13, 159);call #Ultimate.allocInit(1, 160);call write~init~int(0, 160, 0, 1);call #Ultimate.allocInit(4, 161);call write~init~int(69, 161, 0, 1);call write~init~int(79, 161, 1, 1);call write~init~int(77, 161, 2, 1);call write~init~int(0, 161, 3, 1);call #Ultimate.allocInit(1, 162);call write~init~int(0, 162, 0, 1);call #Ultimate.allocInit(11, 163);call #Ultimate.allocInit(1, 164);call write~init~int(0, 164, 0, 1);call #Ultimate.allocInit(10, 165);call #Ultimate.allocInit(1, 166);call write~init~int(0, 166, 0, 1);call #Ultimate.allocInit(9, 167);call #Ultimate.allocInit(19, 168);call #Ultimate.allocInit(207, 169);call #Ultimate.allocInit(46, 170);call #Ultimate.allocInit(46, 171);call #Ultimate.allocInit(19, 172);call #Ultimate.allocInit(9, 173);call #Ultimate.allocInit(1, 174);call write~init~int(0, 174, 0, 1);call #Ultimate.allocInit(8, 175);call #Ultimate.allocInit(1, 176);call write~init~int(0, 176, 0, 1);call #Ultimate.allocInit(12, 177);call #Ultimate.allocInit(1, 178);call write~init~int(0, 178, 0, 1);call #Ultimate.allocInit(4, 179);call write~init~int(69, 179, 0, 1);call write~init~int(79, 179, 1, 1);call write~init~int(70, 179, 2, 1);call write~init~int(0, 179, 3, 1);call #Ultimate.allocInit(1, 180);call write~init~int(0, 180, 0, 1);call #Ultimate.allocInit(7, 181);call write~init~int(82, 181, 0, 1);call write~init~int(120, 181, 1, 1);call write~init~int(68, 181, 2, 1);call write~init~int(97, 181, 3, 1);call write~init~int(116, 181, 4, 1);call write~init~int(97, 181, 5, 1);call write~init~int(0, 181, 6, 1);call #Ultimate.allocInit(1, 182);call write~init~int(0, 182, 0, 1);call #Ultimate.allocInit(9, 183);call #Ultimate.allocInit(1, 184);call write~init~int(0, 184, 0, 1);call #Ultimate.allocInit(8, 185);call #Ultimate.allocInit(1, 186);call write~init~int(0, 186, 0, 1);call #Ultimate.allocInit(9, 187);call #Ultimate.allocInit(19, 188);call #Ultimate.allocInit(207, 189);call #Ultimate.allocInit(16, 190);call #Ultimate.allocInit(16, 191);call #Ultimate.allocInit(19, 192);call #Ultimate.allocInit(9, 193);call #Ultimate.allocInit(19, 194);call #Ultimate.allocInit(207, 195);call #Ultimate.allocInit(78, 196);call #Ultimate.allocInit(78, 197);call #Ultimate.allocInit(19, 198);call #Ultimate.allocInit(31, 199);call #Ultimate.allocInit(207, 200);call #Ultimate.allocInit(22, 201);call #Ultimate.allocInit(13, 202);call #Ultimate.allocInit(9, 203);call #Ultimate.allocInit(22, 204);call #Ultimate.allocInit(207, 205);call #Ultimate.allocInit(21, 206);call #Ultimate.allocInit(21, 207);call #Ultimate.allocInit(22, 208);call #Ultimate.allocInit(31, 209);call #Ultimate.allocInit(207, 210);call #Ultimate.allocInit(18, 211);call #Ultimate.allocInit(12, 212);call #Ultimate.allocInit(31, 213);call #Ultimate.allocInit(207, 214);call #Ultimate.allocInit(18, 215);call #Ultimate.allocInit(13, 216);call #Ultimate.allocInit(32, 217);call #Ultimate.allocInit(32, 218);call #Ultimate.allocInit(33, 219);call #Ultimate.allocInit(11, 220);call #Ultimate.allocInit(31, 221);call #Ultimate.allocInit(207, 222);call #Ultimate.allocInit(19, 223);call #Ultimate.allocInit(12, 224);call #Ultimate.allocInit(31, 225);call #Ultimate.allocInit(207, 226);call #Ultimate.allocInit(19, 227);call #Ultimate.allocInit(13, 228);call #Ultimate.allocInit(31, 229);call #Ultimate.allocInit(207, 230);call #Ultimate.allocInit(19, 231);call #Ultimate.allocInit(12, 232);call #Ultimate.allocInit(31, 233);call #Ultimate.allocInit(207, 234);call #Ultimate.allocInit(19, 235);call #Ultimate.allocInit(13, 236);call #Ultimate.allocInit(9, 237);call #Ultimate.allocInit(19, 238);call #Ultimate.allocInit(207, 239);call #Ultimate.allocInit(22, 240);call #Ultimate.allocInit(22, 241);call #Ultimate.allocInit(19, 242);~ldv_irq_1_3~0 := 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~pci_counter~0 := 0;~ldv_irq_1_0~0 := 0;~via_ircc_fir_ops_group1~0.base, ~via_ircc_fir_ops_group1~0.offset := 0, 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_1~0 := 0;~ldv_irq_line_1_3~0 := 0;~via_driver_group1~0.base, ~via_driver_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~ldv_state_variable_4~0 := 0;~via_ircc_sir_ops_group1~0.base, ~via_ircc_sir_ops_group1~0.offset := 0, 0;~driver_name~0.base, ~driver_name~0.offset := 9, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 243, 0;call #Ultimate.allocInit(192, 243);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[5 := 0];~#via_driver~0.base, ~#via_driver~0.offset := 244, 0;call #Ultimate.allocInit(305, 244);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(10, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~int(0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 141 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 149 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 157 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 165 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 173 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 181 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 189 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 197 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 205 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 213 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 233 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 241 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 249 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 257 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 265 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 277 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 289 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 297 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 245, 0;call #Ultimate.allocInit(528, 245);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 472 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 480 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 488 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 496 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 504 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 512 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 520 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 246, 0;call #Ultimate.allocInit(528, 246);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 472 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 480 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 488 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 496 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 504 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 512 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 520 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_5~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_4~0 := 0;~ldv_retval_1~0 := 0;~ldv_retval_3~0 := 0;~ldv_spin~0 := 0; {1916#true} is VALID [2022-02-20 22:30:06,341 INFO L290 TraceCheckUtils]: 1: Hoare triple {1916#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret847#1.base, main_#t~ret847#1.offset, main_#t~ret848#1.base, main_#t~ret848#1.offset, main_#t~ret849#1.base, main_#t~ret849#1.offset, main_#t~ret850#1.base, main_#t~ret850#1.offset, main_#t~ret851#1.base, main_#t~ret851#1.offset, main_#t~ret852#1.base, main_#t~ret852#1.offset, main_#t~ret853#1.base, main_#t~ret853#1.offset, main_#t~nondet854#1, main_#t~switch855#1, main_#t~nondet856#1, main_#t~switch857#1, main_#t~ret858#1, main_#t~ret859#1, main_#t~nondet860#1, main_#t~switch861#1, main_#t~ret862#1, main_#t~nondet863#1, main_#t~switch864#1, main_#t~ret865#1, main_#t~mem866#1, main_#t~ret867#1, main_#t~mem868#1, main_#t~ret869#1, main_#t~mem870#1, main_#t~ret871#1, main_#t~ret872#1, main_#t~ret873#1, main_#t~ret874#1, main_#t~ret875#1, main_#t~nondet876#1, main_#t~switch877#1, main_#t~ret878#1, main_#t~mem879#1, main_#t~ret880#1, main_#t~mem881#1, main_#t~ret882#1, main_#t~mem883#1, main_#t~ret884#1, main_#t~ret885#1, main_#t~ret886#1, main_#t~ret887#1, main_#t~ret888#1, main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset, main_~tmp~54#1.base, main_~tmp~54#1.offset, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp___0~22#1.base, main_~tmp___0~22#1.offset, main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset, main_~tmp___1~15#1.base, main_~tmp___1~15#1.offset, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset, main_~tmp___2~11#1.base, main_~tmp___2~11#1.offset, main_~#ldvarg5~0#1.base, main_~#ldvarg5~0#1.offset, main_~ldvarg6~0#1.base, main_~ldvarg6~0#1.offset, main_~tmp___3~8#1.base, main_~tmp___3~8#1.offset, main_~tmp___4~8#1, main_~tmp___5~8#1, main_~tmp___6~5#1, main_~tmp___7~3#1, main_~tmp___8~3#1;havoc main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset;havoc main_~tmp~54#1.base, main_~tmp~54#1.offset;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp___0~22#1.base, main_~tmp___0~22#1.offset;havoc main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset;havoc main_~tmp___1~15#1.base, main_~tmp___1~15#1.offset;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset;havoc main_~tmp___2~11#1.base, main_~tmp___2~11#1.offset;call main_~#ldvarg5~0#1.base, main_~#ldvarg5~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~ldvarg6~0#1.base, main_~ldvarg6~0#1.offset;havoc main_~tmp___3~8#1.base, main_~tmp___3~8#1.offset;havoc main_~tmp___4~8#1;havoc main_~tmp___5~8#1;havoc main_~tmp___6~5#1;havoc main_~tmp___7~3#1;havoc main_~tmp___8~3#1; {1916#true} is VALID [2022-02-20 22:30:06,342 INFO L272 TraceCheckUtils]: 2: Hoare triple {1916#true} call main_#t~ret847#1.base, main_#t~ret847#1.offset := ldv_init_zalloc(32); {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:06,342 INFO L290 TraceCheckUtils]: 3: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:06,343 INFO L272 TraceCheckUtils]: 4: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:06,343 INFO L290 TraceCheckUtils]: 5: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,344 INFO L290 TraceCheckUtils]: 6: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,344 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,344 INFO L290 TraceCheckUtils]: 8: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:06,344 INFO L272 TraceCheckUtils]: 9: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:06,344 INFO L290 TraceCheckUtils]: 10: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,344 INFO L290 TraceCheckUtils]: 11: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,345 INFO L290 TraceCheckUtils]: 12: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,345 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,345 INFO L290 TraceCheckUtils]: 14: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:06,345 INFO L290 TraceCheckUtils]: 15: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,345 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1917#false} {1916#true} #4821#return; {1917#false} is VALID [2022-02-20 22:30:06,345 INFO L290 TraceCheckUtils]: 17: Hoare triple {1917#false} main_~tmp~54#1.base, main_~tmp~54#1.offset := main_#t~ret847#1.base, main_#t~ret847#1.offset;havoc main_#t~ret847#1.base, main_#t~ret847#1.offset;main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset := main_~tmp~54#1.base, main_~tmp~54#1.offset; {1917#false} is VALID [2022-02-20 22:30:06,345 INFO L272 TraceCheckUtils]: 18: Hoare triple {1917#false} call main_#t~ret848#1.base, main_#t~ret848#1.offset := ldv_init_zalloc(232); {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:06,346 INFO L290 TraceCheckUtils]: 19: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:06,346 INFO L272 TraceCheckUtils]: 20: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:06,347 INFO L290 TraceCheckUtils]: 21: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,347 INFO L290 TraceCheckUtils]: 22: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,347 INFO L284 TraceCheckUtils]: 23: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,347 INFO L290 TraceCheckUtils]: 24: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:06,347 INFO L272 TraceCheckUtils]: 25: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:06,347 INFO L290 TraceCheckUtils]: 26: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,348 INFO L290 TraceCheckUtils]: 27: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,348 INFO L290 TraceCheckUtils]: 28: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,348 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,348 INFO L290 TraceCheckUtils]: 30: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:06,348 INFO L290 TraceCheckUtils]: 31: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,348 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {1917#false} {1917#false} #4823#return; {1917#false} is VALID [2022-02-20 22:30:06,348 INFO L290 TraceCheckUtils]: 33: Hoare triple {1917#false} main_~tmp___0~22#1.base, main_~tmp___0~22#1.offset := main_#t~ret848#1.base, main_#t~ret848#1.offset;havoc main_#t~ret848#1.base, main_#t~ret848#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp___0~22#1.base, main_~tmp___0~22#1.offset; {1917#false} is VALID [2022-02-20 22:30:06,349 INFO L272 TraceCheckUtils]: 34: Hoare triple {1917#false} call main_#t~ret849#1.base, main_#t~ret849#1.offset := ldv_init_zalloc(40); {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:06,349 INFO L290 TraceCheckUtils]: 35: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:06,349 INFO L272 TraceCheckUtils]: 36: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:06,350 INFO L290 TraceCheckUtils]: 37: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,350 INFO L290 TraceCheckUtils]: 38: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,350 INFO L284 TraceCheckUtils]: 39: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,350 INFO L290 TraceCheckUtils]: 40: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:06,350 INFO L272 TraceCheckUtils]: 41: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:06,350 INFO L290 TraceCheckUtils]: 42: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,351 INFO L290 TraceCheckUtils]: 43: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,351 INFO L290 TraceCheckUtils]: 44: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,351 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,351 INFO L290 TraceCheckUtils]: 46: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:06,351 INFO L290 TraceCheckUtils]: 47: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,351 INFO L284 TraceCheckUtils]: 48: Hoare quadruple {1917#false} {1917#false} #4825#return; {1917#false} is VALID [2022-02-20 22:30:06,351 INFO L290 TraceCheckUtils]: 49: Hoare triple {1917#false} main_~tmp___1~15#1.base, main_~tmp___1~15#1.offset := main_#t~ret849#1.base, main_#t~ret849#1.offset;havoc main_#t~ret849#1.base, main_#t~ret849#1.offset;main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset := main_~tmp___1~15#1.base, main_~tmp___1~15#1.offset; {1917#false} is VALID [2022-02-20 22:30:06,352 INFO L272 TraceCheckUtils]: 50: Hoare triple {1917#false} call main_#t~ret850#1.base, main_#t~ret850#1.offset := ldv_init_zalloc(232); {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:06,352 INFO L290 TraceCheckUtils]: 51: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:06,352 INFO L272 TraceCheckUtils]: 52: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:06,353 INFO L290 TraceCheckUtils]: 53: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,353 INFO L290 TraceCheckUtils]: 54: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,353 INFO L284 TraceCheckUtils]: 55: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,353 INFO L290 TraceCheckUtils]: 56: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:06,353 INFO L272 TraceCheckUtils]: 57: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:06,353 INFO L290 TraceCheckUtils]: 58: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,353 INFO L290 TraceCheckUtils]: 59: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,354 INFO L290 TraceCheckUtils]: 60: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,354 INFO L284 TraceCheckUtils]: 61: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,354 INFO L290 TraceCheckUtils]: 62: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:06,354 INFO L290 TraceCheckUtils]: 63: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,354 INFO L284 TraceCheckUtils]: 64: Hoare quadruple {1917#false} {1917#false} #4827#return; {1917#false} is VALID [2022-02-20 22:30:06,354 INFO L290 TraceCheckUtils]: 65: Hoare triple {1917#false} main_~tmp___2~11#1.base, main_~tmp___2~11#1.offset := main_#t~ret850#1.base, main_#t~ret850#1.offset;havoc main_#t~ret850#1.base, main_#t~ret850#1.offset;main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset := main_~tmp___2~11#1.base, main_~tmp___2~11#1.offset; {1917#false} is VALID [2022-02-20 22:30:06,354 INFO L272 TraceCheckUtils]: 66: Hoare triple {1917#false} call main_#t~ret851#1.base, main_#t~ret851#1.offset := ldv_init_zalloc(40); {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:06,355 INFO L290 TraceCheckUtils]: 67: Hoare triple {2051#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {1916#true} is VALID [2022-02-20 22:30:06,355 INFO L272 TraceCheckUtils]: 68: Hoare triple {1916#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {2059#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:06,355 INFO L290 TraceCheckUtils]: 69: Hoare triple {2059#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1916#true} is VALID [2022-02-20 22:30:06,356 INFO L290 TraceCheckUtils]: 70: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,356 INFO L284 TraceCheckUtils]: 71: Hoare quadruple {1916#true} {1916#true} #4165#return; {1916#true} is VALID [2022-02-20 22:30:06,356 INFO L290 TraceCheckUtils]: 72: Hoare triple {1916#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1916#true} is VALID [2022-02-20 22:30:06,356 INFO L272 TraceCheckUtils]: 73: Hoare triple {1916#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1916#true} is VALID [2022-02-20 22:30:06,356 INFO L290 TraceCheckUtils]: 74: Hoare triple {1916#true} ~cond := #in~cond; {1916#true} is VALID [2022-02-20 22:30:06,356 INFO L290 TraceCheckUtils]: 75: Hoare triple {1916#true} assume 0 == ~cond;assume false; {1917#false} is VALID [2022-02-20 22:30:06,357 INFO L290 TraceCheckUtils]: 76: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,357 INFO L284 TraceCheckUtils]: 77: Hoare quadruple {1917#false} {1916#true} #4167#return; {1917#false} is VALID [2022-02-20 22:30:06,357 INFO L290 TraceCheckUtils]: 78: Hoare triple {1917#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1917#false} is VALID [2022-02-20 22:30:06,357 INFO L290 TraceCheckUtils]: 79: Hoare triple {1917#false} assume true; {1917#false} is VALID [2022-02-20 22:30:06,357 INFO L284 TraceCheckUtils]: 80: Hoare quadruple {1917#false} {1917#false} #4829#return; {1917#false} is VALID [2022-02-20 22:30:06,357 INFO L290 TraceCheckUtils]: 81: Hoare triple {1917#false} main_~tmp___3~8#1.base, main_~tmp___3~8#1.offset := main_#t~ret851#1.base, main_#t~ret851#1.offset;havoc main_#t~ret851#1.base, main_#t~ret851#1.offset;main_~ldvarg6~0#1.base, main_~ldvarg6~0#1.offset := main_~tmp___3~8#1.base, main_~tmp___3~8#1.offset;assume { :begin_inline_ldv_initialize } true; {1917#false} is VALID [2022-02-20 22:30:06,357 INFO L290 TraceCheckUtils]: 82: Hoare triple {1917#false} assume { :end_inline_ldv_initialize } true; {1917#false} is VALID [2022-02-20 22:30:06,357 INFO L272 TraceCheckUtils]: 83: Hoare triple {1917#false} call main_#t~ret852#1.base, main_#t~ret852#1.offset := ldv_memset(main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4); {2088#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:30:06,358 INFO L290 TraceCheckUtils]: 84: Hoare triple {2088#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~s#1.base, ~s#1.offset := #in~s#1.base, #in~s#1.offset;~c#1 := #in~c#1;~n#1 := #in~n#1;havoc ~tmp~3#1.base, ~tmp~3#1.offset;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := ~s#1.base, ~s#1.offset, ~c#1, ~n#1;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr938#1;#Ultimate.C_memset_#t~loopctr938#1 := 0; {1916#true} is VALID [2022-02-20 22:30:06,358 INFO L290 TraceCheckUtils]: 85: Hoare triple {1916#true} assume !(#Ultimate.C_memset_#t~loopctr938#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {1916#true} is VALID [2022-02-20 22:30:06,358 INFO L290 TraceCheckUtils]: 86: Hoare triple {1916#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;#t~memset~res23#1.base, #t~memset~res23#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;~tmp~3#1.base, ~tmp~3#1.offset := ~s#1.base, ~s#1.offset;havoc #t~memset~res23#1.base, #t~memset~res23#1.offset;#res#1.base, #res#1.offset := ~tmp~3#1.base, ~tmp~3#1.offset; {1916#true} is VALID [2022-02-20 22:30:06,358 INFO L290 TraceCheckUtils]: 87: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,358 INFO L284 TraceCheckUtils]: 88: Hoare quadruple {1916#true} {1917#false} #4831#return; {1917#false} is VALID [2022-02-20 22:30:06,358 INFO L290 TraceCheckUtils]: 89: Hoare triple {1917#false} havoc main_#t~ret852#1.base, main_#t~ret852#1.offset; {1917#false} is VALID [2022-02-20 22:30:06,358 INFO L272 TraceCheckUtils]: 90: Hoare triple {1917#false} call main_#t~ret853#1.base, main_#t~ret853#1.offset := ldv_memset(main_~#ldvarg5~0#1.base, main_~#ldvarg5~0#1.offset, 0, 4); {2088#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:30:06,359 INFO L290 TraceCheckUtils]: 91: Hoare triple {2088#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~s#1.base, ~s#1.offset := #in~s#1.base, #in~s#1.offset;~c#1 := #in~c#1;~n#1 := #in~n#1;havoc ~tmp~3#1.base, ~tmp~3#1.offset;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := ~s#1.base, ~s#1.offset, ~c#1, ~n#1;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr938#1;#Ultimate.C_memset_#t~loopctr938#1 := 0; {1916#true} is VALID [2022-02-20 22:30:06,359 INFO L290 TraceCheckUtils]: 92: Hoare triple {1916#true} assume !(#Ultimate.C_memset_#t~loopctr938#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {1916#true} is VALID [2022-02-20 22:30:06,359 INFO L290 TraceCheckUtils]: 93: Hoare triple {1916#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;#t~memset~res23#1.base, #t~memset~res23#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;~tmp~3#1.base, ~tmp~3#1.offset := ~s#1.base, ~s#1.offset;havoc #t~memset~res23#1.base, #t~memset~res23#1.offset;#res#1.base, #res#1.offset := ~tmp~3#1.base, ~tmp~3#1.offset; {1916#true} is VALID [2022-02-20 22:30:06,359 INFO L290 TraceCheckUtils]: 94: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,359 INFO L284 TraceCheckUtils]: 95: Hoare quadruple {1916#true} {1917#false} #4833#return; {1917#false} is VALID [2022-02-20 22:30:06,359 INFO L290 TraceCheckUtils]: 96: Hoare triple {1917#false} havoc main_#t~ret853#1.base, main_#t~ret853#1.offset;~ldv_state_variable_4~0 := 0;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {1917#false} is VALID [2022-02-20 22:30:06,359 INFO L290 TraceCheckUtils]: 97: Hoare triple {1917#false} assume -2147483648 <= main_#t~nondet854#1 && main_#t~nondet854#1 <= 2147483647;main_~tmp___4~8#1 := main_#t~nondet854#1;havoc main_#t~nondet854#1;main_#t~switch855#1 := 0 == main_~tmp___4~8#1; {1917#false} is VALID [2022-02-20 22:30:06,359 INFO L290 TraceCheckUtils]: 98: Hoare triple {1917#false} assume !main_#t~switch855#1;main_#t~switch855#1 := main_#t~switch855#1 || 1 == main_~tmp___4~8#1; {1917#false} is VALID [2022-02-20 22:30:06,360 INFO L290 TraceCheckUtils]: 99: Hoare triple {1917#false} assume main_#t~switch855#1; {1917#false} is VALID [2022-02-20 22:30:06,360 INFO L290 TraceCheckUtils]: 100: Hoare triple {1917#false} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet840#1, choose_interrupt_1_#t~switch841#1, choose_interrupt_1_#t~ret842#1, choose_interrupt_1_#t~ret843#1, choose_interrupt_1_#t~ret844#1, choose_interrupt_1_#t~ret845#1, choose_interrupt_1_~tmp~52#1;havoc choose_interrupt_1_~tmp~52#1;assume -2147483648 <= choose_interrupt_1_#t~nondet840#1 && choose_interrupt_1_#t~nondet840#1 <= 2147483647;choose_interrupt_1_~tmp~52#1 := choose_interrupt_1_#t~nondet840#1;havoc choose_interrupt_1_#t~nondet840#1;choose_interrupt_1_#t~switch841#1 := 0 == choose_interrupt_1_~tmp~52#1; {1917#false} is VALID [2022-02-20 22:30:06,360 INFO L290 TraceCheckUtils]: 101: Hoare triple {1917#false} assume !choose_interrupt_1_#t~switch841#1;choose_interrupt_1_#t~switch841#1 := choose_interrupt_1_#t~switch841#1 || 1 == choose_interrupt_1_~tmp~52#1; {1917#false} is VALID [2022-02-20 22:30:06,360 INFO L290 TraceCheckUtils]: 102: Hoare triple {1917#false} assume !choose_interrupt_1_#t~switch841#1;choose_interrupt_1_#t~switch841#1 := choose_interrupt_1_#t~switch841#1 || 2 == choose_interrupt_1_~tmp~52#1; {1917#false} is VALID [2022-02-20 22:30:06,360 INFO L290 TraceCheckUtils]: 103: Hoare triple {1917#false} assume !choose_interrupt_1_#t~switch841#1;choose_interrupt_1_#t~switch841#1 := choose_interrupt_1_#t~switch841#1 || 3 == choose_interrupt_1_~tmp~52#1; {1917#false} is VALID [2022-02-20 22:30:06,360 INFO L290 TraceCheckUtils]: 104: Hoare triple {1917#false} assume choose_interrupt_1_#t~switch841#1; {1917#false} is VALID [2022-02-20 22:30:06,360 INFO L272 TraceCheckUtils]: 105: Hoare triple {1917#false} call choose_interrupt_1_#t~ret845#1 := ldv_irq_1(~ldv_irq_1_3~0, ~ldv_irq_line_1_3~0, ~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset); {1917#false} is VALID [2022-02-20 22:30:06,361 INFO L290 TraceCheckUtils]: 106: Hoare triple {1917#false} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~49#1;havoc ~tmp___0~21#1;assume -2147483648 <= #t~nondet834#1 && #t~nondet834#1 <= 2147483647;~tmp~49#1 := #t~nondet834#1;havoc #t~nondet834#1;~irq_retval~0#1 := ~tmp~49#1; {1917#false} is VALID [2022-02-20 22:30:06,361 INFO L290 TraceCheckUtils]: 107: Hoare triple {1917#false} assume 0 != ~state#1;assume -2147483648 <= #t~nondet835#1 && #t~nondet835#1 <= 2147483647;~tmp___0~21#1 := #t~nondet835#1;havoc #t~nondet835#1;#t~switch836#1 := 0 == ~tmp___0~21#1; {1917#false} is VALID [2022-02-20 22:30:06,361 INFO L290 TraceCheckUtils]: 108: Hoare triple {1917#false} assume #t~switch836#1; {1917#false} is VALID [2022-02-20 22:30:06,361 INFO L290 TraceCheckUtils]: 109: Hoare triple {1917#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_via_ircc_interrupt } true;via_ircc_interrupt_#in~dummy#1, via_ircc_interrupt_#in~dev_id#1.base, via_ircc_interrupt_#in~dev_id#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc via_ircc_interrupt_#res#1;havoc via_ircc_interrupt_#t~ret711#1.base, via_ircc_interrupt_#t~ret711#1.offset, via_ircc_interrupt_#t~mem712#1, via_ircc_interrupt_#t~ret713#1, via_ircc_interrupt_#t~mem714#1, via_ircc_interrupt_#t~ret715#1, via_ircc_interrupt_#t~ite716#1.base, via_ircc_interrupt_#t~ite716#1.offset, via_ircc_interrupt_#t~ite717#1.base, via_ircc_interrupt_#t~ite717#1.offset, via_ircc_interrupt_#t~ite718#1.base, via_ircc_interrupt_#t~ite718#1.offset, via_ircc_interrupt_#t~mem719#1, via_ircc_interrupt_#t~ret720#1, via_ircc_interrupt_#t~mem721#1, via_ircc_interrupt_#t~ret722#1, via_ircc_interrupt_#t~mem723#1, via_ircc_interrupt_#t~mem724#1, via_ircc_interrupt_#t~mem725#1.base, via_ircc_interrupt_#t~mem725#1.offset, via_ircc_interrupt_#t~ret726#1, via_ircc_interrupt_#t~ret727#1, via_ircc_interrupt_#t~ret728#1, via_ircc_interrupt_#t~ret729#1, via_ircc_interrupt_#t~mem730#1, via_ircc_interrupt_#t~ret731#1, via_ircc_interrupt_#t~ite732#1.base, via_ircc_interrupt_#t~ite732#1.offset, via_ircc_interrupt_#t~ite733#1.base, via_ircc_interrupt_#t~ite733#1.offset, via_ircc_interrupt_#t~ite734#1.base, via_ircc_interrupt_#t~ite734#1.offset, via_ircc_interrupt_#t~ite735#1.base, via_ircc_interrupt_#t~ite735#1.offset, via_ircc_interrupt_#t~mem736#1, via_ircc_interrupt_#t~ret737#1, via_ircc_interrupt_#t~mem738#1.base, via_ircc_interrupt_#t~mem738#1.offset, via_ircc_interrupt_#t~ret739#1, via_ircc_interrupt_#t~ret740#1, via_ircc_interrupt_#t~mem741#1, via_ircc_interrupt_#t~ret742#1, via_ircc_interrupt_#t~mem743#1, via_ircc_interrupt_#t~ret744#1, via_ircc_interrupt_#t~ite745#1.base, via_ircc_interrupt_#t~ite745#1.offset, via_ircc_interrupt_#t~ite746#1.base, via_ircc_interrupt_#t~ite746#1.offset, via_ircc_interrupt_#t~ite747#1.base, via_ircc_interrupt_#t~ite747#1.offset, via_ircc_interrupt_#t~ite748#1.base, via_ircc_interrupt_#t~ite748#1.offset, via_ircc_interrupt_#t~ite749#1.base, via_ircc_interrupt_#t~ite749#1.offset, via_ircc_interrupt_#t~ite750#1.base, via_ircc_interrupt_#t~ite750#1.offset, via_ircc_interrupt_#t~ite751#1.base, via_ircc_interrupt_#t~ite751#1.offset, via_ircc_interrupt_#t~mem752#1, via_ircc_interrupt_#t~ret753#1, via_ircc_interrupt_#t~ret754#1, via_ircc_interrupt_#t~ret755#1, via_ircc_interrupt_#t~mem756#1, via_ircc_interrupt_#t~ret757#1, via_ircc_interrupt_#t~ret758#1, via_ircc_interrupt_#t~mem759#1, via_ircc_interrupt_#t~ret760#1, via_ircc_interrupt_~dummy#1, via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset, via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset, via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset, via_ircc_interrupt_~tmp~44#1.base, via_ircc_interrupt_~tmp~44#1.offset, via_ircc_interrupt_~iobase~7#1, via_ircc_interrupt_~iHostIntType~0#1, via_ircc_interrupt_~iRxIntType~0#1, via_ircc_interrupt_~iTxIntType~0#1, via_ircc_interrupt_~#descriptor~11#1.base, via_ircc_interrupt_~#descriptor~11#1.offset, via_ircc_interrupt_~tmp___0~17#1, via_ircc_interrupt_~tmp___1~12#1, via_ircc_interrupt_~#descriptor___0~4#1.base, via_ircc_interrupt_~#descriptor___0~4#1.offset, via_ircc_interrupt_~tmp___2~8#1, via_ircc_interrupt_~tmp___3~5#1, via_ircc_interrupt_~tmp___4~5#1, via_ircc_interrupt_~#descriptor___1~3#1.base, via_ircc_interrupt_~#descriptor___1~3#1.offset, via_ircc_interrupt_~tmp___5~5#1, via_ircc_interrupt_~#descriptor___2~1#1.base, via_ircc_interrupt_~#descriptor___2~1#1.offset, via_ircc_interrupt_~tmp___6~4#1, via_ircc_interrupt_~tmp___7~2#1, via_ircc_interrupt_~#descriptor___3~1#1.base, via_ircc_interrupt_~#descriptor___3~1#1.offset, via_ircc_interrupt_~tmp___8~2#1, via_ircc_interrupt_~tmp___9~2#1;via_ircc_interrupt_~dummy#1 := via_ircc_interrupt_#in~dummy#1;via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset := via_ircc_interrupt_#in~dev_id#1.base, via_ircc_interrupt_#in~dev_id#1.offset;havoc via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset;havoc via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset;havoc via_ircc_interrupt_~tmp~44#1.base, via_ircc_interrupt_~tmp~44#1.offset;havoc via_ircc_interrupt_~iobase~7#1;havoc via_ircc_interrupt_~iHostIntType~0#1;havoc via_ircc_interrupt_~iRxIntType~0#1;havoc via_ircc_interrupt_~iTxIntType~0#1;call via_ircc_interrupt_~#descriptor~11#1.base, via_ircc_interrupt_~#descriptor~11#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___0~17#1;havoc via_ircc_interrupt_~tmp___1~12#1;call via_ircc_interrupt_~#descriptor___0~4#1.base, via_ircc_interrupt_~#descriptor___0~4#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___2~8#1;havoc via_ircc_interrupt_~tmp___3~5#1;havoc via_ircc_interrupt_~tmp___4~5#1;call via_ircc_interrupt_~#descriptor___1~3#1.base, via_ircc_interrupt_~#descriptor___1~3#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___5~5#1;call via_ircc_interrupt_~#descriptor___2~1#1.base, via_ircc_interrupt_~#descriptor___2~1#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___6~4#1;havoc via_ircc_interrupt_~tmp___7~2#1;call via_ircc_interrupt_~#descriptor___3~1#1.base, via_ircc_interrupt_~#descriptor___3~1#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___8~2#1;havoc via_ircc_interrupt_~tmp___9~2#1;via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset := via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset; {1917#false} is VALID [2022-02-20 22:30:06,361 INFO L272 TraceCheckUtils]: 110: Hoare triple {1917#false} call via_ircc_interrupt_#t~ret711#1.base, via_ircc_interrupt_#t~ret711#1.offset := netdev_priv(via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset); {1916#true} is VALID [2022-02-20 22:30:06,361 INFO L290 TraceCheckUtils]: 111: Hoare triple {1916#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3008 + ~dev.offset; {1916#true} is VALID [2022-02-20 22:30:06,362 INFO L290 TraceCheckUtils]: 112: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,362 INFO L284 TraceCheckUtils]: 113: Hoare quadruple {1916#true} {1917#false} #4211#return; {1917#false} is VALID [2022-02-20 22:30:06,362 INFO L290 TraceCheckUtils]: 114: Hoare triple {1917#false} via_ircc_interrupt_~tmp~44#1.base, via_ircc_interrupt_~tmp~44#1.offset := via_ircc_interrupt_#t~ret711#1.base, via_ircc_interrupt_#t~ret711#1.offset;havoc via_ircc_interrupt_#t~ret711#1.base, via_ircc_interrupt_#t~ret711#1.offset;via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset := via_ircc_interrupt_~tmp~44#1.base, via_ircc_interrupt_~tmp~44#1.offset;call via_ircc_interrupt_#t~mem712#1 := read~int(via_ircc_interrupt_~self~4#1.base, 292 + via_ircc_interrupt_~self~4#1.offset, 4);via_ircc_interrupt_~iobase~7#1 := via_ircc_interrupt_#t~mem712#1;havoc via_ircc_interrupt_#t~mem712#1;assume { :begin_inline_spin_lock } true;spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset := via_ircc_interrupt_~self~4#1.base, 457 + via_ircc_interrupt_~self~4#1.offset;havoc spin_lock_~lock#1.base, spin_lock_~lock#1.offset;spin_lock_~lock#1.base, spin_lock_~lock#1.offset := spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset; {1917#false} is VALID [2022-02-20 22:30:06,362 INFO L272 TraceCheckUtils]: 115: Hoare triple {1917#false} call ldv_spin_lock(); {2089#(= ~ldv_spin~0 |old(~ldv_spin~0)|)} is VALID [2022-02-20 22:30:06,362 INFO L290 TraceCheckUtils]: 116: Hoare triple {2089#(= ~ldv_spin~0 |old(~ldv_spin~0)|)} ~ldv_spin~0 := 1; {1916#true} is VALID [2022-02-20 22:30:06,362 INFO L290 TraceCheckUtils]: 117: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,362 INFO L284 TraceCheckUtils]: 118: Hoare quadruple {1916#true} {1917#false} #4213#return; {1917#false} is VALID [2022-02-20 22:30:06,362 INFO L290 TraceCheckUtils]: 119: Hoare triple {1917#false} assume { :begin_inline_ldv_spin_lock_5 } true;ldv_spin_lock_5_#in~lock#1.base, ldv_spin_lock_5_#in~lock#1.offset := spin_lock_~lock#1.base, spin_lock_~lock#1.offset;havoc ldv_spin_lock_5_~lock#1.base, ldv_spin_lock_5_~lock#1.offset;ldv_spin_lock_5_~lock#1.base, ldv_spin_lock_5_~lock#1.offset := ldv_spin_lock_5_#in~lock#1.base, ldv_spin_lock_5_#in~lock#1.offset;assume { :begin_inline__raw_spin_lock } true;_raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset := ldv_spin_lock_5_~lock#1.base, ldv_spin_lock_5_~lock#1.offset;havoc _raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset;_raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset := _raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset; {1917#false} is VALID [2022-02-20 22:30:06,363 INFO L290 TraceCheckUtils]: 120: Hoare triple {1917#false} assume { :end_inline__raw_spin_lock } true; {1917#false} is VALID [2022-02-20 22:30:06,363 INFO L290 TraceCheckUtils]: 121: Hoare triple {1917#false} assume { :end_inline_ldv_spin_lock_5 } true; {1917#false} is VALID [2022-02-20 22:30:06,363 INFO L290 TraceCheckUtils]: 122: Hoare triple {1917#false} assume { :end_inline_spin_lock } true; {1917#false} is VALID [2022-02-20 22:30:06,363 INFO L272 TraceCheckUtils]: 123: Hoare triple {1917#false} call via_ircc_interrupt_#t~ret713#1 := ReadReg(via_ircc_interrupt_~iobase~7#1, 33); {1916#true} is VALID [2022-02-20 22:30:06,363 INFO L290 TraceCheckUtils]: 124: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,363 INFO L272 TraceCheckUtils]: 125: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,363 INFO L290 TraceCheckUtils]: 126: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,364 INFO L290 TraceCheckUtils]: 127: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,364 INFO L284 TraceCheckUtils]: 128: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,364 INFO L290 TraceCheckUtils]: 129: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,364 INFO L290 TraceCheckUtils]: 130: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,364 INFO L284 TraceCheckUtils]: 131: Hoare quadruple {1916#true} {1917#false} #4215#return; {1917#false} is VALID [2022-02-20 22:30:06,364 INFO L290 TraceCheckUtils]: 132: Hoare triple {1917#false} via_ircc_interrupt_~iHostIntType~0#1 := via_ircc_interrupt_#t~ret713#1;havoc via_ircc_interrupt_#t~ret713#1;call write~$Pointer$(141, 0, via_ircc_interrupt_~#descriptor~11#1.base, via_ircc_interrupt_~#descriptor~11#1.offset, 8);call write~$Pointer$(142, 0, via_ircc_interrupt_~#descriptor~11#1.base, 8 + via_ircc_interrupt_~#descriptor~11#1.offset, 8);call write~$Pointer$(143, 0, via_ircc_interrupt_~#descriptor~11#1.base, 16 + via_ircc_interrupt_~#descriptor~11#1.offset, 8);call write~$Pointer$(144, 0, via_ircc_interrupt_~#descriptor~11#1.base, 24 + via_ircc_interrupt_~#descriptor~11#1.offset, 8);call write~int(1297, via_ircc_interrupt_~#descriptor~11#1.base, 32 + via_ircc_interrupt_~#descriptor~11#1.offset, 4);call write~int(0, via_ircc_interrupt_~#descriptor~11#1.base, 36 + via_ircc_interrupt_~#descriptor~11#1.offset, 1);call via_ircc_interrupt_#t~mem714#1 := read~int(via_ircc_interrupt_~#descriptor~11#1.base, 36 + via_ircc_interrupt_~#descriptor~11#1.offset, 1); {1917#false} is VALID [2022-02-20 22:30:06,364 INFO L272 TraceCheckUtils]: 133: Hoare triple {1917#false} call via_ircc_interrupt_#t~ret715#1 := ldv__builtin_expect(via_ircc_interrupt_#t~mem714#1 % 256, 0); {1916#true} is VALID [2022-02-20 22:30:06,364 INFO L290 TraceCheckUtils]: 134: Hoare triple {1916#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {1916#true} is VALID [2022-02-20 22:30:06,365 INFO L290 TraceCheckUtils]: 135: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,365 INFO L284 TraceCheckUtils]: 136: Hoare quadruple {1916#true} {1917#false} #4217#return; {1917#false} is VALID [2022-02-20 22:30:06,365 INFO L290 TraceCheckUtils]: 137: Hoare triple {1917#false} assume -9223372036854775808 <= via_ircc_interrupt_#t~ret715#1 && via_ircc_interrupt_#t~ret715#1 <= 9223372036854775807;via_ircc_interrupt_~tmp___0~17#1 := via_ircc_interrupt_#t~ret715#1;havoc via_ircc_interrupt_#t~mem714#1;havoc via_ircc_interrupt_#t~ret715#1; {1917#false} is VALID [2022-02-20 22:30:06,365 INFO L290 TraceCheckUtils]: 138: Hoare triple {1917#false} assume !(0 != via_ircc_interrupt_~tmp___0~17#1); {1917#false} is VALID [2022-02-20 22:30:06,365 INFO L290 TraceCheckUtils]: 139: Hoare triple {1917#false} assume !(0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 64)))); {1917#false} is VALID [2022-02-20 22:30:06,365 INFO L290 TraceCheckUtils]: 140: Hoare triple {1917#false} assume !(0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 32)))); {1917#false} is VALID [2022-02-20 22:30:06,365 INFO L290 TraceCheckUtils]: 141: Hoare triple {1917#false} assume 0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 16))); {1917#false} is VALID [2022-02-20 22:30:06,366 INFO L272 TraceCheckUtils]: 142: Hoare triple {1917#false} call via_ircc_interrupt_#t~ret742#1 := ReadReg(via_ircc_interrupt_~iobase~7#1, 39); {1916#true} is VALID [2022-02-20 22:30:06,366 INFO L290 TraceCheckUtils]: 143: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,366 INFO L272 TraceCheckUtils]: 144: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,366 INFO L290 TraceCheckUtils]: 145: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,366 INFO L290 TraceCheckUtils]: 146: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,366 INFO L284 TraceCheckUtils]: 147: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,366 INFO L290 TraceCheckUtils]: 148: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,366 INFO L290 TraceCheckUtils]: 149: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,367 INFO L284 TraceCheckUtils]: 150: Hoare quadruple {1916#true} {1917#false} #4311#return; {1917#false} is VALID [2022-02-20 22:30:06,367 INFO L290 TraceCheckUtils]: 151: Hoare triple {1917#false} via_ircc_interrupt_~iRxIntType~0#1 := via_ircc_interrupt_#t~ret742#1;havoc via_ircc_interrupt_#t~ret742#1;call write~$Pointer$(167, 0, via_ircc_interrupt_~#descriptor___1~3#1.base, via_ircc_interrupt_~#descriptor___1~3#1.offset, 8);call write~$Pointer$(168, 0, via_ircc_interrupt_~#descriptor___1~3#1.base, 8 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 8);call write~$Pointer$(169, 0, via_ircc_interrupt_~#descriptor___1~3#1.base, 16 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 8);call write~$Pointer$(170, 0, via_ircc_interrupt_~#descriptor___1~3#1.base, 24 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 8);call write~int(1354, via_ircc_interrupt_~#descriptor___1~3#1.base, 32 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 4);call write~int(0, via_ircc_interrupt_~#descriptor___1~3#1.base, 36 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 1);call via_ircc_interrupt_#t~mem743#1 := read~int(via_ircc_interrupt_~#descriptor___1~3#1.base, 36 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 1); {1917#false} is VALID [2022-02-20 22:30:06,367 INFO L272 TraceCheckUtils]: 152: Hoare triple {1917#false} call via_ircc_interrupt_#t~ret744#1 := ldv__builtin_expect(via_ircc_interrupt_#t~mem743#1 % 256, 0); {1916#true} is VALID [2022-02-20 22:30:06,367 INFO L290 TraceCheckUtils]: 153: Hoare triple {1916#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {1916#true} is VALID [2022-02-20 22:30:06,367 INFO L290 TraceCheckUtils]: 154: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,367 INFO L284 TraceCheckUtils]: 155: Hoare quadruple {1916#true} {1917#false} #4313#return; {1917#false} is VALID [2022-02-20 22:30:06,367 INFO L290 TraceCheckUtils]: 156: Hoare triple {1917#false} assume -9223372036854775808 <= via_ircc_interrupt_#t~ret744#1 && via_ircc_interrupt_#t~ret744#1 <= 9223372036854775807;via_ircc_interrupt_~tmp___5~5#1 := via_ircc_interrupt_#t~ret744#1;havoc via_ircc_interrupt_#t~mem743#1;havoc via_ircc_interrupt_#t~ret744#1; {1917#false} is VALID [2022-02-20 22:30:06,368 INFO L290 TraceCheckUtils]: 157: Hoare triple {1917#false} assume !(0 != via_ircc_interrupt_~tmp___5~5#1); {1917#false} is VALID [2022-02-20 22:30:06,368 INFO L290 TraceCheckUtils]: 158: Hoare triple {1917#false} assume !(0 == via_ircc_interrupt_~iRxIntType~0#1 % 256 % 4294967296); {1917#false} is VALID [2022-02-20 22:30:06,368 INFO L290 TraceCheckUtils]: 159: Hoare triple {1917#false} assume 0 != (if 0 == via_ircc_interrupt_~iRxIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iRxIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iRxIntType~0#1 % 256, 16)));assume { :begin_inline_via_ircc_dma_receive_complete } true;via_ircc_dma_receive_complete_#in~self#1.base, via_ircc_dma_receive_complete_#in~self#1.offset, via_ircc_dma_receive_complete_#in~iobase#1 := via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset, via_ircc_interrupt_~iobase~7#1;havoc via_ircc_dma_receive_complete_#res#1;havoc via_ircc_dma_receive_complete_#t~mem563#1, via_ircc_dma_receive_complete_#t~mem564#1, via_ircc_dma_receive_complete_#t~ret565#1, via_ircc_dma_receive_complete_#t~ret566#1.base, via_ircc_dma_receive_complete_#t~ret566#1.offset, via_ircc_dma_receive_complete_#t~ret567#1.base, via_ircc_dma_receive_complete_#t~ret567#1.offset, via_ircc_dma_receive_complete_#t~mem568#1, via_ircc_dma_receive_complete_#t~mem569#1.base, via_ircc_dma_receive_complete_#t~mem569#1.offset, via_ircc_dma_receive_complete_#t~mem570#1.base, via_ircc_dma_receive_complete_#t~mem570#1.offset, via_ircc_dma_receive_complete_#t~mem571#1, via_ircc_dma_receive_complete_#t~mem572#1, via_ircc_dma_receive_complete_#t~mem573#1.base, via_ircc_dma_receive_complete_#t~mem573#1.offset, via_ircc_dma_receive_complete_#t~mem574#1.base, via_ircc_dma_receive_complete_#t~mem574#1.offset, via_ircc_dma_receive_complete_#t~mem575#1, via_ircc_dma_receive_complete_#t~mem576#1.base, via_ircc_dma_receive_complete_#t~mem576#1.offset, via_ircc_dma_receive_complete_#t~mem577#1.base, via_ircc_dma_receive_complete_#t~mem577#1.offset, via_ircc_dma_receive_complete_#t~mem578#1.base, via_ircc_dma_receive_complete_#t~mem578#1.offset, via_ircc_dma_receive_complete_#t~mem579#1, via_ircc_dma_receive_complete_#t~mem580#1.base, via_ircc_dma_receive_complete_#t~mem580#1.offset, via_ircc_dma_receive_complete_#t~mem581#1.base, via_ircc_dma_receive_complete_#t~mem581#1.offset, via_ircc_dma_receive_complete_#t~mem582#1, via_ircc_dma_receive_complete_#t~mem583#1.base, via_ircc_dma_receive_complete_#t~mem583#1.offset, via_ircc_dma_receive_complete_#t~ret584#1, via_ircc_dma_receive_complete_#t~ret585#1, via_ircc_dma_receive_complete_#t~mem586#1, via_ircc_dma_receive_complete_#t~ret587#1, via_ircc_dma_receive_complete_#t~ret588#1, via_ircc_dma_receive_complete_#t~mem589#1, via_ircc_dma_receive_complete_#t~mem590#1, via_ircc_dma_receive_complete_#t~ret591#1, via_ircc_dma_receive_complete_#t~ret592#1, via_ircc_dma_receive_complete_#t~mem593#1, via_ircc_dma_receive_complete_#t~mem594#1, via_ircc_dma_receive_complete_#t~mem595#1, via_ircc_dma_receive_complete_#t~mem596#1, via_ircc_dma_receive_complete_#t~mem597#1, via_ircc_dma_receive_complete_#t~mem598#1, via_ircc_dma_receive_complete_#t~mem599#1, via_ircc_dma_receive_complete_#t~ret600#1, via_ircc_dma_receive_complete_#t~ret601#1, via_ircc_dma_receive_complete_#t~ret602#1, via_ircc_dma_receive_complete_#t~mem603#1, via_ircc_dma_receive_complete_#t~mem604#1, via_ircc_dma_receive_complete_#t~mem605#1, via_ircc_dma_receive_complete_#t~mem606#1, via_ircc_dma_receive_complete_#t~mem607#1, via_ircc_dma_receive_complete_#t~mem608#1, via_ircc_dma_receive_complete_#t~mem609#1, via_ircc_dma_receive_complete_#t~ret610#1.base, via_ircc_dma_receive_complete_#t~ret610#1.offset, via_ircc_dma_receive_complete_#t~mem611#1.base, via_ircc_dma_receive_complete_#t~mem611#1.offset, via_ircc_dma_receive_complete_#t~short612#1, via_ircc_dma_receive_complete_#t~mem613#1.base, via_ircc_dma_receive_complete_#t~mem613#1.offset, via_ircc_dma_receive_complete_#t~short614#1, via_ircc_dma_receive_complete_#t~mem615#1.base, via_ircc_dma_receive_complete_#t~mem615#1.offset, via_ircc_dma_receive_complete_#t~mem616#1.base, via_ircc_dma_receive_complete_#t~mem616#1.offset, via_ircc_dma_receive_complete_#t~mem617#1, via_ircc_dma_receive_complete_#t~ret618#1.base, via_ircc_dma_receive_complete_#t~ret618#1.offset, via_ircc_dma_receive_complete_#t~mem619#1.base, via_ircc_dma_receive_complete_#t~mem619#1.offset, via_ircc_dma_receive_complete_#t~mem620#1, via_ircc_dma_receive_complete_#t~ret621#1, via_ircc_dma_receive_complete_#t~mem622#1.base, via_ircc_dma_receive_complete_#t~mem622#1.offset, via_ircc_dma_receive_complete_#t~mem623#1.base, via_ircc_dma_receive_complete_#t~mem623#1.offset, via_ircc_dma_receive_complete_#t~mem624#1.base, via_ircc_dma_receive_complete_#t~mem624#1.offset, via_ircc_dma_receive_complete_#t~mem625#1.base, via_ircc_dma_receive_complete_#t~mem625#1.offset, via_ircc_dma_receive_complete_#t~mem626#1, via_ircc_dma_receive_complete_#t~mem627#1.base, via_ircc_dma_receive_complete_#t~mem627#1.offset, via_ircc_dma_receive_complete_#t~mem628#1.base, via_ircc_dma_receive_complete_#t~mem628#1.offset, via_ircc_dma_receive_complete_#t~mem629#1, via_ircc_dma_receive_complete_#t~mem630#1.base, via_ircc_dma_receive_complete_#t~mem630#1.offset, via_ircc_dma_receive_complete_#t~ret631#1, via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset, via_ircc_dma_receive_complete_~iobase#1, via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset, via_ircc_dma_receive_complete_~skb~0#1.base, via_ircc_dma_receive_complete_~skb~0#1.offset, via_ircc_dma_receive_complete_~len~0#1, via_ircc_dma_receive_complete_~i~8#1, via_ircc_dma_receive_complete_~status~0#1, via_ircc_dma_receive_complete_~tmp~41#1, via_ircc_dma_receive_complete_~tmp___0~14#1, via_ircc_dma_receive_complete_~#descriptor~8#1.base, via_ircc_dma_receive_complete_~#descriptor~8#1.offset, via_ircc_dma_receive_complete_~tmp___1~10#1, via_ircc_dma_receive_complete_~tmp___2~6#1, via_ircc_dma_receive_complete_~#descriptor___0~2#1.base, via_ircc_dma_receive_complete_~#descriptor___0~2#1.offset, via_ircc_dma_receive_complete_~tmp___3~3#1, via_ircc_dma_receive_complete_~tmp___4~3#1, via_ircc_dma_receive_complete_~#descriptor___1~2#1.base, via_ircc_dma_receive_complete_~#descriptor___1~2#1.offset, via_ircc_dma_receive_complete_~tmp___5~3#1;via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset := via_ircc_dma_receive_complete_#in~self#1.base, via_ircc_dma_receive_complete_#in~self#1.offset;via_ircc_dma_receive_complete_~iobase#1 := via_ircc_dma_receive_complete_#in~iobase#1;havoc via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset;havoc via_ircc_dma_receive_complete_~skb~0#1.base, via_ircc_dma_receive_complete_~skb~0#1.offset;havoc via_ircc_dma_receive_complete_~len~0#1;havoc via_ircc_dma_receive_complete_~i~8#1;havoc via_ircc_dma_receive_complete_~status~0#1;havoc via_ircc_dma_receive_complete_~tmp~41#1;havoc via_ircc_dma_receive_complete_~tmp___0~14#1;call via_ircc_dma_receive_complete_~#descriptor~8#1.base, via_ircc_dma_receive_complete_~#descriptor~8#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_dma_receive_complete_~tmp___1~10#1;havoc via_ircc_dma_receive_complete_~tmp___2~6#1;call via_ircc_dma_receive_complete_~#descriptor___0~2#1.base, via_ircc_dma_receive_complete_~#descriptor___0~2#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_dma_receive_complete_~tmp___3~3#1;havoc via_ircc_dma_receive_complete_~tmp___4~3#1;call via_ircc_dma_receive_complete_~#descriptor___1~2#1.base, via_ircc_dma_receive_complete_~#descriptor___1~2#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_dma_receive_complete_~tmp___5~3#1;via_ircc_dma_receive_complete_~status~0#1 := 0;call via_ircc_dma_receive_complete_#t~mem563#1 := read~int(via_ircc_dma_receive_complete_~self#1.base, 292 + via_ircc_dma_receive_complete_~self#1.offset, 4);via_ircc_dma_receive_complete_~iobase#1 := via_ircc_dma_receive_complete_#t~mem563#1;havoc via_ircc_dma_receive_complete_#t~mem563#1;via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset := via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset;call via_ircc_dma_receive_complete_#t~mem564#1 := read~int(via_ircc_dma_receive_complete_~self#1.base, 344 + via_ircc_dma_receive_complete_~self#1.offset, 4); {1917#false} is VALID [2022-02-20 22:30:06,368 INFO L290 TraceCheckUtils]: 160: Hoare triple {1917#false} assume via_ircc_dma_receive_complete_#t~mem564#1 % 4294967296 <= 3999999;havoc via_ircc_dma_receive_complete_#t~mem564#1; {1917#false} is VALID [2022-02-20 22:30:06,368 INFO L272 TraceCheckUtils]: 161: Hoare triple {1917#false} call via_ircc_dma_receive_complete_#t~ret565#1 := GetRecvByte(via_ircc_dma_receive_complete_~iobase#1 % 65536, via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset); {2088#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:30:06,368 INFO L290 TraceCheckUtils]: 162: Hoare triple {2088#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~iobase := #in~iobase;~self.base, ~self.offset := #in~self.base, #in~self.offset;havoc ~low~4;havoc ~high~4;havoc ~wTmp~2;havoc ~wTmp1~2;havoc ~ret~0; {1916#true} is VALID [2022-02-20 22:30:06,368 INFO L272 TraceCheckUtils]: 163: Hoare triple {1916#true} call #t~ret178 := ReadReg(~iobase % 65536, 44); {1916#true} is VALID [2022-02-20 22:30:06,369 INFO L290 TraceCheckUtils]: 164: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,369 INFO L272 TraceCheckUtils]: 165: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,369 INFO L290 TraceCheckUtils]: 166: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,369 INFO L290 TraceCheckUtils]: 167: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,369 INFO L284 TraceCheckUtils]: 168: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,369 INFO L290 TraceCheckUtils]: 169: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,369 INFO L290 TraceCheckUtils]: 170: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,370 INFO L284 TraceCheckUtils]: 171: Hoare quadruple {1916#true} {1916#true} #4207#return; {1916#true} is VALID [2022-02-20 22:30:06,370 INFO L290 TraceCheckUtils]: 172: Hoare triple {1916#true} ~low~4 := #t~ret178;havoc #t~ret178; {1916#true} is VALID [2022-02-20 22:30:06,370 INFO L272 TraceCheckUtils]: 173: Hoare triple {1916#true} call #t~ret179 := ReadReg(~iobase % 65536, 45); {1916#true} is VALID [2022-02-20 22:30:06,370 INFO L290 TraceCheckUtils]: 174: Hoare triple {1916#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,370 INFO L272 TraceCheckUtils]: 175: Hoare triple {1916#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {1916#true} is VALID [2022-02-20 22:30:06,370 INFO L290 TraceCheckUtils]: 176: Hoare triple {1916#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {1916#true} is VALID [2022-02-20 22:30:06,370 INFO L290 TraceCheckUtils]: 177: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,370 INFO L284 TraceCheckUtils]: 178: Hoare quadruple {1916#true} {1916#true} #3995#return; {1916#true} is VALID [2022-02-20 22:30:06,371 INFO L290 TraceCheckUtils]: 179: Hoare triple {1916#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {1916#true} is VALID [2022-02-20 22:30:06,371 INFO L290 TraceCheckUtils]: 180: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,371 INFO L284 TraceCheckUtils]: 181: Hoare quadruple {1916#true} {1916#true} #4209#return; {1916#true} is VALID [2022-02-20 22:30:06,371 INFO L290 TraceCheckUtils]: 182: Hoare triple {1916#true} ~high~4 := #t~ret179;havoc #t~ret179;~wTmp1~2 := ~high~4 % 256;~wTmp~2 := (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 0 == ~low~4 % 256 then (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) else (if 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256) then ~low~4 % 256 else (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256)) || ((1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 1 == ~low~4 % 256) then 1 else ~bitwiseOr((if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536), ~low~4 % 256))));call #t~mem180 := read~int(~self.base, 564 + ~self.offset, 4); {1916#true} is VALID [2022-02-20 22:30:06,371 INFO L290 TraceCheckUtils]: 183: Hoare triple {1916#true} assume ~wTmp~2 % 65536 % 4294967296 >= #t~mem180 % 4294967296;havoc #t~mem180;call #t~mem181 := read~int(~self.base, 564 + ~self.offset, 4);~ret~0 := ~wTmp~2 % 65536 - #t~mem181 % 65536;havoc #t~mem181; {1916#true} is VALID [2022-02-20 22:30:06,371 INFO L290 TraceCheckUtils]: 184: Hoare triple {1916#true} call write~int(~wTmp~2 % 65536, ~self.base, 564 + ~self.offset, 4);#res := ~ret~0; {1916#true} is VALID [2022-02-20 22:30:06,371 INFO L290 TraceCheckUtils]: 185: Hoare triple {1916#true} assume true; {1916#true} is VALID [2022-02-20 22:30:06,371 INFO L284 TraceCheckUtils]: 186: Hoare quadruple {1916#true} {1917#false} #4317#return; {1917#false} is VALID [2022-02-20 22:30:06,372 INFO L290 TraceCheckUtils]: 187: Hoare triple {1917#false} via_ircc_dma_receive_complete_~tmp~41#1 := via_ircc_dma_receive_complete_#t~ret565#1;havoc via_ircc_dma_receive_complete_#t~ret565#1;via_ircc_dma_receive_complete_~len~0#1 := via_ircc_dma_receive_complete_~tmp~41#1 % 65536; {1917#false} is VALID [2022-02-20 22:30:06,372 INFO L272 TraceCheckUtils]: 188: Hoare triple {1917#false} call via_ircc_dma_receive_complete_#t~ret566#1.base, via_ircc_dma_receive_complete_#t~ret566#1.offset := dev_alloc_skb(1 + via_ircc_dma_receive_complete_~len~0#1); {1917#false} is VALID [2022-02-20 22:30:06,372 INFO L290 TraceCheckUtils]: 189: Hoare triple {1917#false} ~length#1 := #in~length#1;havoc ~tmp~9#1.base, ~tmp~9#1.offset;assume { :begin_inline_netdev_alloc_skb } true;netdev_alloc_skb_#in~dev#1.base, netdev_alloc_skb_#in~dev#1.offset, netdev_alloc_skb_#in~length#1 := 0, 0, ~length#1;havoc netdev_alloc_skb_#res#1.base, netdev_alloc_skb_#res#1.offset;havoc netdev_alloc_skb_#t~ret78#1.base, netdev_alloc_skb_#t~ret78#1.offset, netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset, netdev_alloc_skb_~length#1, netdev_alloc_skb_~tmp~8#1.base, netdev_alloc_skb_~tmp~8#1.offset;netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset := netdev_alloc_skb_#in~dev#1.base, netdev_alloc_skb_#in~dev#1.offset;netdev_alloc_skb_~length#1 := netdev_alloc_skb_#in~length#1;havoc netdev_alloc_skb_~tmp~8#1.base, netdev_alloc_skb_~tmp~8#1.offset;assume { :begin_inline_ldv___netdev_alloc_skb_31 } true;ldv___netdev_alloc_skb_31_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_31_#in~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_31_#in~ldv_func_arg2#1, ldv___netdev_alloc_skb_31_#in~flags#1 := netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset, netdev_alloc_skb_~length#1, 32;havoc ldv___netdev_alloc_skb_31_#res#1.base, ldv___netdev_alloc_skb_31_#res#1.offset;havoc ldv___netdev_alloc_skb_31_#t~ret893#1.base, ldv___netdev_alloc_skb_31_#t~ret893#1.offset, ldv___netdev_alloc_skb_31_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_31_~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_31_~ldv_func_arg2#1, ldv___netdev_alloc_skb_31_~flags#1, ldv___netdev_alloc_skb_31_~tmp~58#1.base, ldv___netdev_alloc_skb_31_~tmp~58#1.offset;ldv___netdev_alloc_skb_31_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_31_~ldv_func_arg1#1.offset := ldv___netdev_alloc_skb_31_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_31_#in~ldv_func_arg1#1.offset;ldv___netdev_alloc_skb_31_~ldv_func_arg2#1 := ldv___netdev_alloc_skb_31_#in~ldv_func_arg2#1;ldv___netdev_alloc_skb_31_~flags#1 := ldv___netdev_alloc_skb_31_#in~flags#1;havoc ldv___netdev_alloc_skb_31_~tmp~58#1.base, ldv___netdev_alloc_skb_31_~tmp~58#1.offset; {1917#false} is VALID [2022-02-20 22:30:06,372 INFO L272 TraceCheckUtils]: 190: Hoare triple {1917#false} call ldv_check_alloc_flags(ldv___netdev_alloc_skb_31_~flags#1); {1917#false} is VALID [2022-02-20 22:30:06,372 INFO L290 TraceCheckUtils]: 191: Hoare triple {1917#false} ~flags := #in~flags; {1917#false} is VALID [2022-02-20 22:30:06,372 INFO L290 TraceCheckUtils]: 192: Hoare triple {1917#false} assume 0 != ~ldv_spin~0 && 0 != (if 0 == ~flags then 0 else (if 1 == ~flags then 0 else ~bitwiseAnd(~flags, 16))) % 4294967296; {1917#false} is VALID [2022-02-20 22:30:06,372 INFO L272 TraceCheckUtils]: 193: Hoare triple {1917#false} call ldv_error(); {1917#false} is VALID [2022-02-20 22:30:06,373 INFO L290 TraceCheckUtils]: 194: Hoare triple {1917#false} assume !false; {1917#false} is VALID [2022-02-20 22:30:06,373 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 196 trivial. 0 not checked. [2022-02-20 22:30:06,374 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:30:06,374 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264868256] [2022-02-20 22:30:06,374 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264868256] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:30:06,374 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:30:06,375 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-02-20 22:30:06,376 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795470213] [2022-02-20 22:30:06,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:30:06,380 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 2 states have internal predecessors, (74), 2 states have call successors, (23), 6 states have call predecessors, (23), 2 states have return successors, (19), 2 states have call predecessors, (19), 2 states have call successors, (19) Word has length 195 [2022-02-20 22:30:06,382 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:30:06,384 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 2 states have internal predecessors, (74), 2 states have call successors, (23), 6 states have call predecessors, (23), 2 states have return successors, (19), 2 states have call predecessors, (19), 2 states have call successors, (19) [2022-02-20 22:30:06,530 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 116 edges. 116 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:30:06,530 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-02-20 22:30:06,530 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:30:06,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-02-20 22:30:06,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-02-20 22:30:06,555 INFO L87 Difference]: Start difference. First operand has 1913 states, 1213 states have (on average 1.3437757625721352) internal successors, (1630), 1244 states have internal predecessors, (1630), 618 states have call successors, (618), 81 states have call predecessors, (618), 80 states have return successors, (611), 600 states have call predecessors, (611), 611 states have call successors, (611) Second operand has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 2 states have internal predecessors, (74), 2 states have call successors, (23), 6 states have call predecessors, (23), 2 states have return successors, (19), 2 states have call predecessors, (19), 2 states have call successors, (19) [2022-02-20 22:30:27,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:30:27,613 INFO L93 Difference]: Finished difference Result 3880 states and 5917 transitions. [2022-02-20 22:30:27,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-20 22:30:27,614 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 2 states have internal predecessors, (74), 2 states have call successors, (23), 6 states have call predecessors, (23), 2 states have return successors, (19), 2 states have call predecessors, (19), 2 states have call successors, (19) Word has length 195 [2022-02-20 22:30:27,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:30:27,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 2 states have internal predecessors, (74), 2 states have call successors, (23), 6 states have call predecessors, (23), 2 states have return successors, (19), 2 states have call predecessors, (19), 2 states have call successors, (19) [2022-02-20 22:30:27,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 5917 transitions. [2022-02-20 22:30:27,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 2 states have internal predecessors, (74), 2 states have call successors, (23), 6 states have call predecessors, (23), 2 states have return successors, (19), 2 states have call predecessors, (19), 2 states have call successors, (19) [2022-02-20 22:30:28,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 5917 transitions. [2022-02-20 22:30:28,300 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 7 states and 5917 transitions. [2022-02-20 22:30:32,962 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 5917 edges. 5917 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:30:33,236 INFO L225 Difference]: With dead ends: 3880 [2022-02-20 22:30:33,236 INFO L226 Difference]: Without dead ends: 1954 [2022-02-20 22:30:33,250 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 71 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2022-02-20 22:30:33,252 INFO L933 BasicCegarLoop]: 2371 mSDtfsCounter, 2357 mSDsluCounter, 1173 mSDsCounter, 0 mSdLazyCounter, 1867 mSolverCounterSat, 3110 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 7.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2628 SdHoareTripleChecker+Valid, 3544 SdHoareTripleChecker+Invalid, 4977 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 3110 IncrementalHoareTripleChecker+Valid, 1867 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 7.1s IncrementalHoareTripleChecker+Time [2022-02-20 22:30:33,252 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [2628 Valid, 3544 Invalid, 4977 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [3110 Valid, 1867 Invalid, 0 Unknown, 0 Unchecked, 7.1s Time] [2022-02-20 22:30:33,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1954 states. [2022-02-20 22:30:33,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1954 to 1895. [2022-02-20 22:30:33,370 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:30:33,381 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1954 states. Second operand has 1895 states, 1204 states have (on average 1.303986710963455) internal successors, (1570), 1226 states have internal predecessors, (1570), 611 states have call successors, (611), 80 states have call predecessors, (611), 79 states have return successors, (610), 599 states have call predecessors, (610), 610 states have call successors, (610) [2022-02-20 22:30:33,387 INFO L74 IsIncluded]: Start isIncluded. First operand 1954 states. Second operand has 1895 states, 1204 states have (on average 1.303986710963455) internal successors, (1570), 1226 states have internal predecessors, (1570), 611 states have call successors, (611), 80 states have call predecessors, (611), 79 states have return successors, (610), 599 states have call predecessors, (610), 610 states have call successors, (610) [2022-02-20 22:30:33,392 INFO L87 Difference]: Start difference. First operand 1954 states. Second operand has 1895 states, 1204 states have (on average 1.303986710963455) internal successors, (1570), 1226 states have internal predecessors, (1570), 611 states have call successors, (611), 80 states have call predecessors, (611), 79 states have return successors, (610), 599 states have call predecessors, (610), 610 states have call successors, (610) [2022-02-20 22:30:33,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:30:33,584 INFO L93 Difference]: Finished difference Result 1954 states and 2894 transitions. [2022-02-20 22:30:33,584 INFO L276 IsEmpty]: Start isEmpty. Operand 1954 states and 2894 transitions. [2022-02-20 22:30:33,599 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:30:33,599 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:30:33,604 INFO L74 IsIncluded]: Start isIncluded. First operand has 1895 states, 1204 states have (on average 1.303986710963455) internal successors, (1570), 1226 states have internal predecessors, (1570), 611 states have call successors, (611), 80 states have call predecessors, (611), 79 states have return successors, (610), 599 states have call predecessors, (610), 610 states have call successors, (610) Second operand 1954 states. [2022-02-20 22:30:33,607 INFO L87 Difference]: Start difference. First operand has 1895 states, 1204 states have (on average 1.303986710963455) internal successors, (1570), 1226 states have internal predecessors, (1570), 611 states have call successors, (611), 80 states have call predecessors, (611), 79 states have return successors, (610), 599 states have call predecessors, (610), 610 states have call successors, (610) Second operand 1954 states. [2022-02-20 22:30:33,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:30:33,759 INFO L93 Difference]: Finished difference Result 1954 states and 2894 transitions. [2022-02-20 22:30:33,759 INFO L276 IsEmpty]: Start isEmpty. Operand 1954 states and 2894 transitions. [2022-02-20 22:30:33,772 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:30:33,772 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:30:33,772 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:30:33,772 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:30:33,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1895 states, 1204 states have (on average 1.303986710963455) internal successors, (1570), 1226 states have internal predecessors, (1570), 611 states have call successors, (611), 80 states have call predecessors, (611), 79 states have return successors, (610), 599 states have call predecessors, (610), 610 states have call successors, (610) [2022-02-20 22:30:33,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1895 states to 1895 states and 2791 transitions. [2022-02-20 22:30:33,984 INFO L78 Accepts]: Start accepts. Automaton has 1895 states and 2791 transitions. Word has length 195 [2022-02-20 22:30:33,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:30:33,986 INFO L470 AbstractCegarLoop]: Abstraction has 1895 states and 2791 transitions. [2022-02-20 22:30:33,986 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 2 states have internal predecessors, (74), 2 states have call successors, (23), 6 states have call predecessors, (23), 2 states have return successors, (19), 2 states have call predecessors, (19), 2 states have call successors, (19) [2022-02-20 22:30:33,986 INFO L276 IsEmpty]: Start isEmpty. Operand 1895 states and 2791 transitions. [2022-02-20 22:30:33,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 193 [2022-02-20 22:30:33,996 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:30:33,996 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:30:33,997 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-02-20 22:30:33,997 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:30:33,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:30:33,998 INFO L85 PathProgramCache]: Analyzing trace with hash -432751907, now seen corresponding path program 1 times [2022-02-20 22:30:33,998 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:30:33,998 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578966618] [2022-02-20 22:30:33,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:30:33,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:30:34,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,242 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:30:34,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,259 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,266 INFO L290 TraceCheckUtils]: 0: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,268 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,269 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,269 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:34,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,274 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,275 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,275 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,275 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,275 INFO L290 TraceCheckUtils]: 0: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,276 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,276 INFO L290 TraceCheckUtils]: 2: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,276 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,276 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,276 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,276 INFO L272 TraceCheckUtils]: 6: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,277 INFO L290 TraceCheckUtils]: 7: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,277 INFO L290 TraceCheckUtils]: 8: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,277 INFO L290 TraceCheckUtils]: 9: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,277 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,277 INFO L290 TraceCheckUtils]: 11: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,277 INFO L290 TraceCheckUtils]: 12: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,278 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4821#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,278 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 18 [2022-02-20 22:30:34,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,290 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,295 INFO L290 TraceCheckUtils]: 0: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,295 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,295 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,295 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:34,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,300 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,300 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,301 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,301 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,301 INFO L290 TraceCheckUtils]: 0: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,302 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,302 INFO L290 TraceCheckUtils]: 2: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,302 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,302 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,302 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,302 INFO L272 TraceCheckUtils]: 6: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,303 INFO L290 TraceCheckUtils]: 7: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,303 INFO L290 TraceCheckUtils]: 8: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,303 INFO L290 TraceCheckUtils]: 9: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,303 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,303 INFO L290 TraceCheckUtils]: 11: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,304 INFO L290 TraceCheckUtils]: 12: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,304 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4823#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,305 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 34 [2022-02-20 22:30:34,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,316 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,320 INFO L290 TraceCheckUtils]: 0: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,321 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,321 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,321 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:34,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,326 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,326 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,326 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,326 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,326 INFO L290 TraceCheckUtils]: 0: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,327 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,327 INFO L290 TraceCheckUtils]: 2: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,327 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,327 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,328 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,328 INFO L272 TraceCheckUtils]: 6: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,328 INFO L290 TraceCheckUtils]: 7: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,328 INFO L290 TraceCheckUtils]: 8: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,328 INFO L290 TraceCheckUtils]: 9: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,328 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,328 INFO L290 TraceCheckUtils]: 11: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,328 INFO L290 TraceCheckUtils]: 12: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,329 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4825#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,329 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 50 [2022-02-20 22:30:34,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,342 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,348 INFO L290 TraceCheckUtils]: 0: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,349 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,349 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,349 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:34,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,353 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,353 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,353 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,354 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,354 INFO L290 TraceCheckUtils]: 0: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,354 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,355 INFO L290 TraceCheckUtils]: 2: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,355 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,355 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,355 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,355 INFO L272 TraceCheckUtils]: 6: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,355 INFO L290 TraceCheckUtils]: 7: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,355 INFO L290 TraceCheckUtils]: 8: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,355 INFO L290 TraceCheckUtils]: 9: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,355 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,356 INFO L290 TraceCheckUtils]: 11: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,356 INFO L290 TraceCheckUtils]: 12: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,356 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4827#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,356 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 66 [2022-02-20 22:30:34,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,366 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,370 INFO L290 TraceCheckUtils]: 0: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,371 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,371 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,371 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:30:34,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,379 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,379 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,379 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,379 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,380 INFO L290 TraceCheckUtils]: 0: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,380 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,380 INFO L290 TraceCheckUtils]: 2: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,381 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,381 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,381 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,381 INFO L272 TraceCheckUtils]: 6: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,381 INFO L290 TraceCheckUtils]: 7: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,381 INFO L290 TraceCheckUtils]: 8: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,381 INFO L290 TraceCheckUtils]: 9: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,381 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,382 INFO L290 TraceCheckUtils]: 11: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,382 INFO L290 TraceCheckUtils]: 12: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,382 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4829#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,389 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 83 [2022-02-20 22:30:34,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,409 INFO L290 TraceCheckUtils]: 0: Hoare triple {14499#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~s#1.base, ~s#1.offset := #in~s#1.base, #in~s#1.offset;~c#1 := #in~c#1;~n#1 := #in~n#1;havoc ~tmp~3#1.base, ~tmp~3#1.offset;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := ~s#1.base, ~s#1.offset, ~c#1, ~n#1;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr938#1;#Ultimate.C_memset_#t~loopctr938#1 := 0; {14324#true} is VALID [2022-02-20 22:30:34,409 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume !(#Ultimate.C_memset_#t~loopctr938#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {14324#true} is VALID [2022-02-20 22:30:34,410 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;#t~memset~res23#1.base, #t~memset~res23#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;~tmp~3#1.base, ~tmp~3#1.offset := ~s#1.base, ~s#1.offset;havoc #t~memset~res23#1.base, #t~memset~res23#1.offset;#res#1.base, #res#1.offset := ~tmp~3#1.base, ~tmp~3#1.offset; {14324#true} is VALID [2022-02-20 22:30:34,410 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,415 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4831#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,415 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 90 [2022-02-20 22:30:34,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,425 INFO L290 TraceCheckUtils]: 0: Hoare triple {14499#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~s#1.base, ~s#1.offset := #in~s#1.base, #in~s#1.offset;~c#1 := #in~c#1;~n#1 := #in~n#1;havoc ~tmp~3#1.base, ~tmp~3#1.offset;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := ~s#1.base, ~s#1.offset, ~c#1, ~n#1;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr938#1;#Ultimate.C_memset_#t~loopctr938#1 := 0; {14324#true} is VALID [2022-02-20 22:30:34,425 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume !(#Ultimate.C_memset_#t~loopctr938#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {14324#true} is VALID [2022-02-20 22:30:34,425 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;#t~memset~res23#1.base, #t~memset~res23#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;~tmp~3#1.base, ~tmp~3#1.offset := ~s#1.base, ~s#1.offset;havoc #t~memset~res23#1.base, #t~memset~res23#1.offset;#res#1.base, #res#1.offset := ~tmp~3#1.base, ~tmp~3#1.offset; {14324#true} is VALID [2022-02-20 22:30:34,425 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,426 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4833#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,426 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 107 [2022-02-20 22:30:34,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,431 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3008 + ~dev.offset; {14324#true} is VALID [2022-02-20 22:30:34,431 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,431 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14325#false} #4211#return; {14325#false} is VALID [2022-02-20 22:30:34,435 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 112 [2022-02-20 22:30:34,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,440 INFO L290 TraceCheckUtils]: 0: Hoare triple {14500#(= ~ldv_spin~0 |old(~ldv_spin~0)|)} ~ldv_spin~0 := 1; {14324#true} is VALID [2022-02-20 22:30:34,440 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,441 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14325#false} #4213#return; {14325#false} is VALID [2022-02-20 22:30:34,442 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 120 [2022-02-20 22:30:34,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,448 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,453 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,453 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,453 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,453 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,453 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,453 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,454 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,454 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,454 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,454 INFO L290 TraceCheckUtils]: 6: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,455 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {14324#true} {14325#false} #4215#return; {14325#false} is VALID [2022-02-20 22:30:34,455 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 130 [2022-02-20 22:30:34,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,459 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {14324#true} is VALID [2022-02-20 22:30:34,459 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,459 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14325#false} #4217#return; {14325#false} is VALID [2022-02-20 22:30:34,460 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 139 [2022-02-20 22:30:34,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,466 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,471 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,471 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,471 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,472 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,472 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,472 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,472 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,472 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,472 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,472 INFO L290 TraceCheckUtils]: 6: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,472 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {14324#true} {14325#false} #4311#return; {14325#false} is VALID [2022-02-20 22:30:34,473 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 149 [2022-02-20 22:30:34,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,476 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {14324#true} is VALID [2022-02-20 22:30:34,477 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,477 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14325#false} #4313#return; {14325#false} is VALID [2022-02-20 22:30:34,477 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 158 [2022-02-20 22:30:34,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,495 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,500 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,504 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,504 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,504 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,504 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,504 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,504 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,504 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,505 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,505 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,505 INFO L290 TraceCheckUtils]: 6: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,505 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {14324#true} {14324#true} #4207#return; {14324#true} is VALID [2022-02-20 22:30:34,505 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 11 [2022-02-20 22:30:34,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,511 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:30:34,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:30:34,514 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,515 INFO L290 TraceCheckUtils]: 1: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,515 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,515 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,515 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,515 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,515 INFO L290 TraceCheckUtils]: 3: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,515 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,516 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,516 INFO L290 TraceCheckUtils]: 6: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,516 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {14324#true} {14324#true} #4209#return; {14324#true} is VALID [2022-02-20 22:30:34,516 INFO L290 TraceCheckUtils]: 0: Hoare triple {14499#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~iobase := #in~iobase;~self.base, ~self.offset := #in~self.base, #in~self.offset;havoc ~low~4;havoc ~high~4;havoc ~wTmp~2;havoc ~wTmp1~2;havoc ~ret~0; {14324#true} is VALID [2022-02-20 22:30:34,516 INFO L272 TraceCheckUtils]: 1: Hoare triple {14324#true} call #t~ret178 := ReadReg(~iobase % 65536, 44); {14324#true} is VALID [2022-02-20 22:30:34,516 INFO L290 TraceCheckUtils]: 2: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,516 INFO L272 TraceCheckUtils]: 3: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,516 INFO L290 TraceCheckUtils]: 4: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,517 INFO L290 TraceCheckUtils]: 5: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,517 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,517 INFO L290 TraceCheckUtils]: 7: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,517 INFO L290 TraceCheckUtils]: 8: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,517 INFO L284 TraceCheckUtils]: 9: Hoare quadruple {14324#true} {14324#true} #4207#return; {14324#true} is VALID [2022-02-20 22:30:34,517 INFO L290 TraceCheckUtils]: 10: Hoare triple {14324#true} ~low~4 := #t~ret178;havoc #t~ret178; {14324#true} is VALID [2022-02-20 22:30:34,517 INFO L272 TraceCheckUtils]: 11: Hoare triple {14324#true} call #t~ret179 := ReadReg(~iobase % 65536, 45); {14324#true} is VALID [2022-02-20 22:30:34,517 INFO L290 TraceCheckUtils]: 12: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,518 INFO L272 TraceCheckUtils]: 13: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,518 INFO L290 TraceCheckUtils]: 14: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,518 INFO L290 TraceCheckUtils]: 15: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,518 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,518 INFO L290 TraceCheckUtils]: 17: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,518 INFO L290 TraceCheckUtils]: 18: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,518 INFO L284 TraceCheckUtils]: 19: Hoare quadruple {14324#true} {14324#true} #4209#return; {14324#true} is VALID [2022-02-20 22:30:34,518 INFO L290 TraceCheckUtils]: 20: Hoare triple {14324#true} ~high~4 := #t~ret179;havoc #t~ret179;~wTmp1~2 := ~high~4 % 256;~wTmp~2 := (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 0 == ~low~4 % 256 then (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) else (if 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256) then ~low~4 % 256 else (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256)) || ((1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 1 == ~low~4 % 256) then 1 else ~bitwiseOr((if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536), ~low~4 % 256))));call #t~mem180 := read~int(~self.base, 564 + ~self.offset, 4); {14324#true} is VALID [2022-02-20 22:30:34,519 INFO L290 TraceCheckUtils]: 21: Hoare triple {14324#true} assume ~wTmp~2 % 65536 % 4294967296 >= #t~mem180 % 4294967296;havoc #t~mem180;call #t~mem181 := read~int(~self.base, 564 + ~self.offset, 4);~ret~0 := ~wTmp~2 % 65536 - #t~mem181 % 65536;havoc #t~mem181; {14324#true} is VALID [2022-02-20 22:30:34,519 INFO L290 TraceCheckUtils]: 22: Hoare triple {14324#true} call write~int(~wTmp~2 % 65536, ~self.base, 564 + ~self.offset, 4);#res := ~ret~0; {14324#true} is VALID [2022-02-20 22:30:34,519 INFO L290 TraceCheckUtils]: 23: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,519 INFO L284 TraceCheckUtils]: 24: Hoare quadruple {14324#true} {14325#false} #4317#return; {14325#false} is VALID [2022-02-20 22:30:34,520 INFO L290 TraceCheckUtils]: 0: Hoare triple {14324#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(81, 2);call #Ultimate.allocInit(25, 3);call #Ultimate.allocInit(42, 4);call #Ultimate.allocInit(25, 5);call #Ultimate.allocInit(44, 6);call #Ultimate.allocInit(26, 7);call #Ultimate.allocInit(41, 8);call #Ultimate.allocInit(9, 9);call #Ultimate.allocInit(9, 10);call #Ultimate.allocInit(9, 11);call #Ultimate.allocInit(9, 12);call #Ultimate.allocInit(14, 13);call #Ultimate.allocInit(207, 14);call #Ultimate.allocInit(44, 15);call #Ultimate.allocInit(44, 16);call #Ultimate.allocInit(14, 17);call #Ultimate.allocInit(9, 18);call #Ultimate.allocInit(13, 19);call #Ultimate.allocInit(207, 20);call #Ultimate.allocInit(24, 21);call #Ultimate.allocInit(24, 22);call #Ultimate.allocInit(13, 23);call #Ultimate.allocInit(9, 24);call #Ultimate.allocInit(13, 25);call #Ultimate.allocInit(207, 26);call #Ultimate.allocInit(21, 27);call #Ultimate.allocInit(21, 28);call #Ultimate.allocInit(13, 29);call #Ultimate.allocInit(9, 30);call #Ultimate.allocInit(13, 31);call #Ultimate.allocInit(207, 32);call #Ultimate.allocInit(22, 33);call #Ultimate.allocInit(22, 34);call #Ultimate.allocInit(13, 35);call #Ultimate.allocInit(9, 36);call #Ultimate.allocInit(13, 37);call #Ultimate.allocInit(207, 38);call #Ultimate.allocInit(22, 39);call #Ultimate.allocInit(22, 40);call #Ultimate.allocInit(13, 41);call #Ultimate.allocInit(9, 42);call #Ultimate.allocInit(13, 43);call #Ultimate.allocInit(207, 44);call #Ultimate.allocInit(21, 45);call #Ultimate.allocInit(21, 46);call #Ultimate.allocInit(13, 47);call #Ultimate.allocInit(22, 48);call #Ultimate.allocInit(9, 49);call #Ultimate.allocInit(14, 50);call #Ultimate.allocInit(207, 51);call #Ultimate.allocInit(34, 52);call #Ultimate.allocInit(34, 53);call #Ultimate.allocInit(14, 54);call #Ultimate.allocInit(40, 55);call #Ultimate.allocInit(9, 56);call #Ultimate.allocInit(15, 57);call #Ultimate.allocInit(207, 58);call #Ultimate.allocInit(29, 59);call #Ultimate.allocInit(29, 60);call #Ultimate.allocInit(15, 61);call #Ultimate.allocInit(84, 62);call #Ultimate.allocInit(9, 63);call #Ultimate.allocInit(29, 64);call #Ultimate.allocInit(207, 65);call #Ultimate.allocInit(46, 66);call #Ultimate.allocInit(46, 67);call #Ultimate.allocInit(29, 68);call #Ultimate.allocInit(9, 69);call #Ultimate.allocInit(29, 70);call #Ultimate.allocInit(207, 71);call #Ultimate.allocInit(56, 72);call #Ultimate.allocInit(56, 73);call #Ultimate.allocInit(29, 74);call #Ultimate.allocInit(9, 75);call #Ultimate.allocInit(29, 76);call #Ultimate.allocInit(207, 77);call #Ultimate.allocInit(49, 78);call #Ultimate.allocInit(49, 79);call #Ultimate.allocInit(29, 80);call #Ultimate.allocInit(40, 81);call #Ultimate.allocInit(29, 82);call #Ultimate.allocInit(9, 83);call #Ultimate.allocInit(22, 84);call #Ultimate.allocInit(207, 85);call #Ultimate.allocInit(29, 86);call #Ultimate.allocInit(29, 87);call #Ultimate.allocInit(22, 88);call #Ultimate.allocInit(31, 89);call #Ultimate.allocInit(207, 90);call #Ultimate.allocInit(23, 91);call #Ultimate.allocInit(13, 92);call #Ultimate.allocInit(9, 93);call #Ultimate.allocInit(18, 94);call #Ultimate.allocInit(207, 95);call #Ultimate.allocInit(44, 96);call #Ultimate.allocInit(44, 97);call #Ultimate.allocInit(18, 98);call #Ultimate.allocInit(9, 99);call #Ultimate.allocInit(27, 100);call #Ultimate.allocInit(207, 101);call #Ultimate.allocInit(55, 102);call #Ultimate.allocInit(55, 103);call #Ultimate.allocInit(27, 104);call #Ultimate.allocInit(9, 105);call #Ultimate.allocInit(30, 106);call #Ultimate.allocInit(207, 107);call #Ultimate.allocInit(47, 108);call #Ultimate.allocInit(47, 109);call #Ultimate.allocInit(30, 110);call #Ultimate.allocInit(9, 111);call #Ultimate.allocInit(30, 112);call #Ultimate.allocInit(207, 113);call #Ultimate.allocInit(40, 114);call #Ultimate.allocInit(40, 115);call #Ultimate.allocInit(30, 116);call #Ultimate.allocInit(9, 117);call #Ultimate.allocInit(30, 118);call #Ultimate.allocInit(207, 119);call #Ultimate.allocInit(25, 120);call #Ultimate.allocInit(25, 121);call #Ultimate.allocInit(30, 122);call #Ultimate.allocInit(9, 123);call #Ultimate.allocInit(14, 124);call #Ultimate.allocInit(207, 125);call #Ultimate.allocInit(14, 126);call #Ultimate.allocInit(14, 127);call #Ultimate.allocInit(14, 128);call #Ultimate.allocInit(9, 129);call #Ultimate.allocInit(15, 130);call #Ultimate.allocInit(207, 131);call #Ultimate.allocInit(22, 132);call #Ultimate.allocInit(22, 133);call #Ultimate.allocInit(15, 134);call #Ultimate.allocInit(9, 135);call #Ultimate.allocInit(15, 136);call #Ultimate.allocInit(207, 137);call #Ultimate.allocInit(47, 138);call #Ultimate.allocInit(47, 139);call #Ultimate.allocInit(15, 140);call #Ultimate.allocInit(9, 141);call #Ultimate.allocInit(19, 142);call #Ultimate.allocInit(207, 143);call #Ultimate.allocInit(42, 144);call #Ultimate.allocInit(42, 145);call #Ultimate.allocInit(19, 146);call #Ultimate.allocInit(6, 147);call write~init~int(84, 147, 0, 1);call write~init~int(105, 147, 1, 1);call write~init~int(109, 147, 2, 1);call write~init~int(101, 147, 3, 1);call write~init~int(114, 147, 4, 1);call write~init~int(0, 147, 5, 1);call #Ultimate.allocInit(1, 148);call write~init~int(0, 148, 0, 1);call #Ultimate.allocInit(3, 149);call write~init~int(84, 149, 0, 1);call write~init~int(120, 149, 1, 1);call write~init~int(0, 149, 2, 1);call #Ultimate.allocInit(1, 150);call write~init~int(0, 150, 0, 1);call #Ultimate.allocInit(3, 151);call write~init~int(82, 151, 0, 1);call write~init~int(120, 151, 1, 1);call write~init~int(0, 151, 2, 1);call #Ultimate.allocInit(1, 152);call write~init~int(0, 152, 0, 1);call #Ultimate.allocInit(9, 153);call #Ultimate.allocInit(19, 154);call #Ultimate.allocInit(207, 155);call #Ultimate.allocInit(37, 156);call #Ultimate.allocInit(37, 157);call #Ultimate.allocInit(19, 158);call #Ultimate.allocInit(13, 159);call #Ultimate.allocInit(1, 160);call write~init~int(0, 160, 0, 1);call #Ultimate.allocInit(4, 161);call write~init~int(69, 161, 0, 1);call write~init~int(79, 161, 1, 1);call write~init~int(77, 161, 2, 1);call write~init~int(0, 161, 3, 1);call #Ultimate.allocInit(1, 162);call write~init~int(0, 162, 0, 1);call #Ultimate.allocInit(11, 163);call #Ultimate.allocInit(1, 164);call write~init~int(0, 164, 0, 1);call #Ultimate.allocInit(10, 165);call #Ultimate.allocInit(1, 166);call write~init~int(0, 166, 0, 1);call #Ultimate.allocInit(9, 167);call #Ultimate.allocInit(19, 168);call #Ultimate.allocInit(207, 169);call #Ultimate.allocInit(46, 170);call #Ultimate.allocInit(46, 171);call #Ultimate.allocInit(19, 172);call #Ultimate.allocInit(9, 173);call #Ultimate.allocInit(1, 174);call write~init~int(0, 174, 0, 1);call #Ultimate.allocInit(8, 175);call #Ultimate.allocInit(1, 176);call write~init~int(0, 176, 0, 1);call #Ultimate.allocInit(12, 177);call #Ultimate.allocInit(1, 178);call write~init~int(0, 178, 0, 1);call #Ultimate.allocInit(4, 179);call write~init~int(69, 179, 0, 1);call write~init~int(79, 179, 1, 1);call write~init~int(70, 179, 2, 1);call write~init~int(0, 179, 3, 1);call #Ultimate.allocInit(1, 180);call write~init~int(0, 180, 0, 1);call #Ultimate.allocInit(7, 181);call write~init~int(82, 181, 0, 1);call write~init~int(120, 181, 1, 1);call write~init~int(68, 181, 2, 1);call write~init~int(97, 181, 3, 1);call write~init~int(116, 181, 4, 1);call write~init~int(97, 181, 5, 1);call write~init~int(0, 181, 6, 1);call #Ultimate.allocInit(1, 182);call write~init~int(0, 182, 0, 1);call #Ultimate.allocInit(9, 183);call #Ultimate.allocInit(1, 184);call write~init~int(0, 184, 0, 1);call #Ultimate.allocInit(8, 185);call #Ultimate.allocInit(1, 186);call write~init~int(0, 186, 0, 1);call #Ultimate.allocInit(9, 187);call #Ultimate.allocInit(19, 188);call #Ultimate.allocInit(207, 189);call #Ultimate.allocInit(16, 190);call #Ultimate.allocInit(16, 191);call #Ultimate.allocInit(19, 192);call #Ultimate.allocInit(9, 193);call #Ultimate.allocInit(19, 194);call #Ultimate.allocInit(207, 195);call #Ultimate.allocInit(78, 196);call #Ultimate.allocInit(78, 197);call #Ultimate.allocInit(19, 198);call #Ultimate.allocInit(31, 199);call #Ultimate.allocInit(207, 200);call #Ultimate.allocInit(22, 201);call #Ultimate.allocInit(13, 202);call #Ultimate.allocInit(9, 203);call #Ultimate.allocInit(22, 204);call #Ultimate.allocInit(207, 205);call #Ultimate.allocInit(21, 206);call #Ultimate.allocInit(21, 207);call #Ultimate.allocInit(22, 208);call #Ultimate.allocInit(31, 209);call #Ultimate.allocInit(207, 210);call #Ultimate.allocInit(18, 211);call #Ultimate.allocInit(12, 212);call #Ultimate.allocInit(31, 213);call #Ultimate.allocInit(207, 214);call #Ultimate.allocInit(18, 215);call #Ultimate.allocInit(13, 216);call #Ultimate.allocInit(32, 217);call #Ultimate.allocInit(32, 218);call #Ultimate.allocInit(33, 219);call #Ultimate.allocInit(11, 220);call #Ultimate.allocInit(31, 221);call #Ultimate.allocInit(207, 222);call #Ultimate.allocInit(19, 223);call #Ultimate.allocInit(12, 224);call #Ultimate.allocInit(31, 225);call #Ultimate.allocInit(207, 226);call #Ultimate.allocInit(19, 227);call #Ultimate.allocInit(13, 228);call #Ultimate.allocInit(31, 229);call #Ultimate.allocInit(207, 230);call #Ultimate.allocInit(19, 231);call #Ultimate.allocInit(12, 232);call #Ultimate.allocInit(31, 233);call #Ultimate.allocInit(207, 234);call #Ultimate.allocInit(19, 235);call #Ultimate.allocInit(13, 236);call #Ultimate.allocInit(9, 237);call #Ultimate.allocInit(19, 238);call #Ultimate.allocInit(207, 239);call #Ultimate.allocInit(22, 240);call #Ultimate.allocInit(22, 241);call #Ultimate.allocInit(19, 242);~ldv_irq_1_3~0 := 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~pci_counter~0 := 0;~ldv_irq_1_0~0 := 0;~via_ircc_fir_ops_group1~0.base, ~via_ircc_fir_ops_group1~0.offset := 0, 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_1~0 := 0;~ldv_irq_line_1_3~0 := 0;~via_driver_group1~0.base, ~via_driver_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~ldv_state_variable_4~0 := 0;~via_ircc_sir_ops_group1~0.base, ~via_ircc_sir_ops_group1~0.offset := 0, 0;~driver_name~0.base, ~driver_name~0.offset := 9, 0;~qos_mtt_bits~0 := 7;~dongle_id~0 := 0;~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset := 243, 0;call #Ultimate.allocInit(192, 243);call write~init~int(4358, ~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, 4);call write~init~int(33329, ~#via_pci_tbl~0.base, 4 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 8 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 12 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 16 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 20 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 24 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 32 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12553, ~#via_pci_tbl~0.base, 36 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 40 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 44 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 48 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 52 + ~#via_pci_tbl~0.offset, 4);call write~init~int(1, ~#via_pci_tbl~0.base, 56 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 64 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12404, ~#via_pci_tbl~0.base, 68 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 72 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 76 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 80 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 84 + ~#via_pci_tbl~0.offset, 4);call write~init~int(2, ~#via_pci_tbl~0.base, 88 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 96 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12615, ~#via_pci_tbl~0.base, 100 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 104 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 108 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 112 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 116 + ~#via_pci_tbl~0.offset, 4);call write~init~int(3, ~#via_pci_tbl~0.base, 120 + ~#via_pci_tbl~0.offset, 8);call write~init~int(4358, ~#via_pci_tbl~0.base, 128 + ~#via_pci_tbl~0.offset, 4);call write~init~int(12663, ~#via_pci_tbl~0.base, 132 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 136 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#via_pci_tbl~0.base, 140 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 144 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 148 + ~#via_pci_tbl~0.offset, 4);call write~init~int(4, ~#via_pci_tbl~0.base, 152 + ~#via_pci_tbl~0.offset, 8);call write~init~int(0, ~#via_pci_tbl~0.base, 160 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 164 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 168 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 172 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 176 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 180 + ~#via_pci_tbl~0.offset, 4);call write~init~int(0, ~#via_pci_tbl~0.base, 184 + ~#via_pci_tbl~0.offset, 8);~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[0 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[1 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[2 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[3 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[4 := 0];~__mod_pci__via_pci_tbl_device_table~0.vendor := ~__mod_pci__via_pci_tbl_device_table~0.vendor[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.device := ~__mod_pci__via_pci_tbl_device_table~0.device[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.subvendor := ~__mod_pci__via_pci_tbl_device_table~0.subvendor[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.subdevice := ~__mod_pci__via_pci_tbl_device_table~0.subdevice[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.class := ~__mod_pci__via_pci_tbl_device_table~0.class[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.class_mask := ~__mod_pci__via_pci_tbl_device_table~0.class_mask[5 := 0];~__mod_pci__via_pci_tbl_device_table~0.driver_data := ~__mod_pci__via_pci_tbl_device_table~0.driver_data[5 := 0];~#via_driver~0.base, ~#via_driver~0.offset := 244, 0;call #Ultimate.allocInit(305, 244);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 8 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(10, 0, ~#via_driver~0.base, 16 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(~#via_pci_tbl~0.base, ~#via_pci_tbl~0.offset, ~#via_driver~0.base, 24 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_init_one.base, #funAddr~via_init_one.offset, ~#via_driver~0.base, 32 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~via_remove_one.base, #funAddr~via_remove_one.offset, ~#via_driver~0.base, 40 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 48 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 56 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 64 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 72 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 80 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 88 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 96 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 104 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 112 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 120 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 128 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 136 + ~#via_driver~0.offset, 1);call write~init~int(0, ~#via_driver~0.base, 137 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 141 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 149 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 157 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 165 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 173 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 181 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 189 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 197 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 205 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 213 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 221 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 225 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 229 + ~#via_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 233 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 241 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 249 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 257 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 265 + ~#via_driver~0.offset, 8);call write~init~int(0, ~#via_driver~0.base, 273 + ~#via_driver~0.offset, 4);call write~init~int(0, ~#via_driver~0.base, 277 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 289 + ~#via_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_driver~0.base, 297 + ~#via_driver~0.offset, 8);~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset := 245, 0;call #Ultimate.allocInit(528, 245);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 8 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_sir_ops~0.base, 16 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_sir_ops~0.base, 24 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_sir.base, #funAddr~via_ircc_hard_xmit_sir.offset, ~#via_ircc_sir_ops~0.base, 32 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 40 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 48 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 56 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 64 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 72 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_sir_ops~0.base, 80 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 88 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 96 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 104 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 112 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 120 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 128 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 136 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 144 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 152 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 160 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 168 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 176 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 184 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 192 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 200 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 208 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 216 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 224 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 232 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 240 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 248 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 256 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 264 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 272 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 280 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 288 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 296 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 304 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 312 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 320 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 328 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 336 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 344 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 352 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 360 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 368 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 376 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 384 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 392 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 400 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 408 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 416 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 424 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 432 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 440 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 448 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 456 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 464 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 472 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 480 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 488 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 496 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 504 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 512 + ~#via_ircc_sir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_sir_ops~0.base, 520 + ~#via_ircc_sir_ops~0.offset, 8);~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset := 246, 0;call #Ultimate.allocInit(528, 246);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 8 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_open.base, #funAddr~via_ircc_net_open.offset, ~#via_ircc_fir_ops~0.base, 16 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_close.base, #funAddr~via_ircc_net_close.offset, ~#via_ircc_fir_ops~0.base, 24 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_hard_xmit_fir.base, #funAddr~via_ircc_hard_xmit_fir.offset, ~#via_ircc_fir_ops~0.base, 32 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 40 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 48 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 56 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 64 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 72 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~via_ircc_net_ioctl.base, #funAddr~via_ircc_net_ioctl.offset, ~#via_ircc_fir_ops~0.base, 80 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 88 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 96 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 104 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 112 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 120 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 128 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 136 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 144 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 152 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 160 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 168 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 176 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 184 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 192 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 200 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 208 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 216 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 224 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 232 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 240 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 248 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 256 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 264 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 272 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 280 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 288 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 296 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 304 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 312 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 320 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 328 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 336 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 344 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 352 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 360 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 368 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 376 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 384 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 392 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 400 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 408 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 416 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 424 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 432 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 440 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 448 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 456 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 464 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 472 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 480 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 488 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 496 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 504 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 512 + ~#via_ircc_fir_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#via_ircc_fir_ops~0.base, 520 + ~#via_ircc_fir_ops~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_5~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_4~0 := 0;~ldv_retval_1~0 := 0;~ldv_retval_3~0 := 0;~ldv_spin~0 := 0; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,520 INFO L290 TraceCheckUtils]: 1: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret847#1.base, main_#t~ret847#1.offset, main_#t~ret848#1.base, main_#t~ret848#1.offset, main_#t~ret849#1.base, main_#t~ret849#1.offset, main_#t~ret850#1.base, main_#t~ret850#1.offset, main_#t~ret851#1.base, main_#t~ret851#1.offset, main_#t~ret852#1.base, main_#t~ret852#1.offset, main_#t~ret853#1.base, main_#t~ret853#1.offset, main_#t~nondet854#1, main_#t~switch855#1, main_#t~nondet856#1, main_#t~switch857#1, main_#t~ret858#1, main_#t~ret859#1, main_#t~nondet860#1, main_#t~switch861#1, main_#t~ret862#1, main_#t~nondet863#1, main_#t~switch864#1, main_#t~ret865#1, main_#t~mem866#1, main_#t~ret867#1, main_#t~mem868#1, main_#t~ret869#1, main_#t~mem870#1, main_#t~ret871#1, main_#t~ret872#1, main_#t~ret873#1, main_#t~ret874#1, main_#t~ret875#1, main_#t~nondet876#1, main_#t~switch877#1, main_#t~ret878#1, main_#t~mem879#1, main_#t~ret880#1, main_#t~mem881#1, main_#t~ret882#1, main_#t~mem883#1, main_#t~ret884#1, main_#t~ret885#1, main_#t~ret886#1, main_#t~ret887#1, main_#t~ret888#1, main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset, main_~tmp~54#1.base, main_~tmp~54#1.offset, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp___0~22#1.base, main_~tmp___0~22#1.offset, main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset, main_~tmp___1~15#1.base, main_~tmp___1~15#1.offset, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset, main_~tmp___2~11#1.base, main_~tmp___2~11#1.offset, main_~#ldvarg5~0#1.base, main_~#ldvarg5~0#1.offset, main_~ldvarg6~0#1.base, main_~ldvarg6~0#1.offset, main_~tmp___3~8#1.base, main_~tmp___3~8#1.offset, main_~tmp___4~8#1, main_~tmp___5~8#1, main_~tmp___6~5#1, main_~tmp___7~3#1, main_~tmp___8~3#1;havoc main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset;havoc main_~tmp~54#1.base, main_~tmp~54#1.offset;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp___0~22#1.base, main_~tmp___0~22#1.offset;havoc main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset;havoc main_~tmp___1~15#1.base, main_~tmp___1~15#1.offset;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset;havoc main_~tmp___2~11#1.base, main_~tmp___2~11#1.offset;call main_~#ldvarg5~0#1.base, main_~#ldvarg5~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~ldvarg6~0#1.base, main_~ldvarg6~0#1.offset;havoc main_~tmp___3~8#1.base, main_~tmp___3~8#1.offset;havoc main_~tmp___4~8#1;havoc main_~tmp___5~8#1;havoc main_~tmp___6~5#1;havoc main_~tmp___7~3#1;havoc main_~tmp___8~3#1; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,521 INFO L272 TraceCheckUtils]: 2: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} call main_#t~ret847#1.base, main_#t~ret847#1.offset := ldv_init_zalloc(32); {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:34,521 INFO L290 TraceCheckUtils]: 3: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,522 INFO L272 TraceCheckUtils]: 4: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,522 INFO L290 TraceCheckUtils]: 5: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,522 INFO L290 TraceCheckUtils]: 6: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,522 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,522 INFO L290 TraceCheckUtils]: 8: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,522 INFO L272 TraceCheckUtils]: 9: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,522 INFO L290 TraceCheckUtils]: 10: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,522 INFO L290 TraceCheckUtils]: 11: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,523 INFO L290 TraceCheckUtils]: 12: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,523 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,523 INFO L290 TraceCheckUtils]: 14: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,523 INFO L290 TraceCheckUtils]: 15: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,523 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4821#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,524 INFO L290 TraceCheckUtils]: 17: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} main_~tmp~54#1.base, main_~tmp~54#1.offset := main_#t~ret847#1.base, main_#t~ret847#1.offset;havoc main_#t~ret847#1.base, main_#t~ret847#1.offset;main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset := main_~tmp~54#1.base, main_~tmp~54#1.offset; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,524 INFO L272 TraceCheckUtils]: 18: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} call main_#t~ret848#1.base, main_#t~ret848#1.offset := ldv_init_zalloc(232); {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:34,525 INFO L290 TraceCheckUtils]: 19: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,525 INFO L272 TraceCheckUtils]: 20: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,525 INFO L290 TraceCheckUtils]: 21: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,525 INFO L290 TraceCheckUtils]: 22: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,525 INFO L284 TraceCheckUtils]: 23: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,526 INFO L290 TraceCheckUtils]: 24: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,526 INFO L272 TraceCheckUtils]: 25: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,526 INFO L290 TraceCheckUtils]: 26: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,526 INFO L290 TraceCheckUtils]: 27: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,526 INFO L290 TraceCheckUtils]: 28: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,526 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,526 INFO L290 TraceCheckUtils]: 30: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,526 INFO L290 TraceCheckUtils]: 31: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,527 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4823#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,527 INFO L290 TraceCheckUtils]: 33: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} main_~tmp___0~22#1.base, main_~tmp___0~22#1.offset := main_#t~ret848#1.base, main_#t~ret848#1.offset;havoc main_#t~ret848#1.base, main_#t~ret848#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp___0~22#1.base, main_~tmp___0~22#1.offset; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,527 INFO L272 TraceCheckUtils]: 34: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} call main_#t~ret849#1.base, main_#t~ret849#1.offset := ldv_init_zalloc(40); {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:34,528 INFO L290 TraceCheckUtils]: 35: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,528 INFO L272 TraceCheckUtils]: 36: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,528 INFO L290 TraceCheckUtils]: 37: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,528 INFO L290 TraceCheckUtils]: 38: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,528 INFO L284 TraceCheckUtils]: 39: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,529 INFO L290 TraceCheckUtils]: 40: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,529 INFO L272 TraceCheckUtils]: 41: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,530 INFO L290 TraceCheckUtils]: 42: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,530 INFO L290 TraceCheckUtils]: 43: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,530 INFO L290 TraceCheckUtils]: 44: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,530 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,530 INFO L290 TraceCheckUtils]: 46: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,530 INFO L290 TraceCheckUtils]: 47: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,531 INFO L284 TraceCheckUtils]: 48: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4825#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,531 INFO L290 TraceCheckUtils]: 49: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} main_~tmp___1~15#1.base, main_~tmp___1~15#1.offset := main_#t~ret849#1.base, main_#t~ret849#1.offset;havoc main_#t~ret849#1.base, main_#t~ret849#1.offset;main_~ldvarg3~0#1.base, main_~ldvarg3~0#1.offset := main_~tmp___1~15#1.base, main_~tmp___1~15#1.offset; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,531 INFO L272 TraceCheckUtils]: 50: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} call main_#t~ret850#1.base, main_#t~ret850#1.offset := ldv_init_zalloc(232); {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:34,531 INFO L290 TraceCheckUtils]: 51: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,532 INFO L272 TraceCheckUtils]: 52: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,532 INFO L290 TraceCheckUtils]: 53: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,532 INFO L290 TraceCheckUtils]: 54: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,532 INFO L284 TraceCheckUtils]: 55: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,532 INFO L290 TraceCheckUtils]: 56: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,532 INFO L272 TraceCheckUtils]: 57: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,534 INFO L290 TraceCheckUtils]: 58: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,535 INFO L290 TraceCheckUtils]: 59: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,535 INFO L290 TraceCheckUtils]: 60: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,535 INFO L284 TraceCheckUtils]: 61: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,535 INFO L290 TraceCheckUtils]: 62: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,535 INFO L290 TraceCheckUtils]: 63: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,536 INFO L284 TraceCheckUtils]: 64: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4827#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,536 INFO L290 TraceCheckUtils]: 65: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} main_~tmp___2~11#1.base, main_~tmp___2~11#1.offset := main_#t~ret850#1.base, main_#t~ret850#1.offset;havoc main_#t~ret850#1.base, main_#t~ret850#1.offset;main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset := main_~tmp___2~11#1.base, main_~tmp___2~11#1.offset; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,536 INFO L272 TraceCheckUtils]: 66: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} call main_#t~ret851#1.base, main_#t~ret851#1.offset := ldv_init_zalloc(40); {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:30:34,536 INFO L290 TraceCheckUtils]: 67: Hoare triple {14462#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc22.base, #t~malloc22.offset := #Ultimate.allocOnHeap(~size); {14324#true} is VALID [2022-02-20 22:30:34,537 INFO L272 TraceCheckUtils]: 68: Hoare triple {14324#true} call #Ultimate.meminit(#t~malloc22.base, #t~malloc22.offset, 1, ~size, ~size); {14470#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:30:34,537 INFO L290 TraceCheckUtils]: 69: Hoare triple {14470#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14324#true} is VALID [2022-02-20 22:30:34,537 INFO L290 TraceCheckUtils]: 70: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,537 INFO L284 TraceCheckUtils]: 71: Hoare quadruple {14324#true} {14324#true} #4165#return; {14324#true} is VALID [2022-02-20 22:30:34,537 INFO L290 TraceCheckUtils]: 72: Hoare triple {14324#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc22.base, #t~malloc22.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,537 INFO L272 TraceCheckUtils]: 73: Hoare triple {14324#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14324#true} is VALID [2022-02-20 22:30:34,538 INFO L290 TraceCheckUtils]: 74: Hoare triple {14324#true} ~cond := #in~cond; {14324#true} is VALID [2022-02-20 22:30:34,538 INFO L290 TraceCheckUtils]: 75: Hoare triple {14324#true} assume !(0 == ~cond); {14324#true} is VALID [2022-02-20 22:30:34,538 INFO L290 TraceCheckUtils]: 76: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,538 INFO L284 TraceCheckUtils]: 77: Hoare quadruple {14324#true} {14324#true} #4167#return; {14324#true} is VALID [2022-02-20 22:30:34,538 INFO L290 TraceCheckUtils]: 78: Hoare triple {14324#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14324#true} is VALID [2022-02-20 22:30:34,538 INFO L290 TraceCheckUtils]: 79: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,539 INFO L284 TraceCheckUtils]: 80: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4829#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,539 INFO L290 TraceCheckUtils]: 81: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} main_~tmp___3~8#1.base, main_~tmp___3~8#1.offset := main_#t~ret851#1.base, main_#t~ret851#1.offset;havoc main_#t~ret851#1.base, main_#t~ret851#1.offset;main_~ldvarg6~0#1.base, main_~ldvarg6~0#1.offset := main_~tmp___3~8#1.base, main_~tmp___3~8#1.offset;assume { :begin_inline_ldv_initialize } true; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,539 INFO L290 TraceCheckUtils]: 82: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_ldv_initialize } true; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,540 INFO L272 TraceCheckUtils]: 83: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} call main_#t~ret852#1.base, main_#t~ret852#1.offset := ldv_memset(main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4); {14499#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:30:34,540 INFO L290 TraceCheckUtils]: 84: Hoare triple {14499#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~s#1.base, ~s#1.offset := #in~s#1.base, #in~s#1.offset;~c#1 := #in~c#1;~n#1 := #in~n#1;havoc ~tmp~3#1.base, ~tmp~3#1.offset;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := ~s#1.base, ~s#1.offset, ~c#1, ~n#1;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr938#1;#Ultimate.C_memset_#t~loopctr938#1 := 0; {14324#true} is VALID [2022-02-20 22:30:34,540 INFO L290 TraceCheckUtils]: 85: Hoare triple {14324#true} assume !(#Ultimate.C_memset_#t~loopctr938#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {14324#true} is VALID [2022-02-20 22:30:34,540 INFO L290 TraceCheckUtils]: 86: Hoare triple {14324#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;#t~memset~res23#1.base, #t~memset~res23#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;~tmp~3#1.base, ~tmp~3#1.offset := ~s#1.base, ~s#1.offset;havoc #t~memset~res23#1.base, #t~memset~res23#1.offset;#res#1.base, #res#1.offset := ~tmp~3#1.base, ~tmp~3#1.offset; {14324#true} is VALID [2022-02-20 22:30:34,540 INFO L290 TraceCheckUtils]: 87: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,541 INFO L284 TraceCheckUtils]: 88: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4831#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,541 INFO L290 TraceCheckUtils]: 89: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} havoc main_#t~ret852#1.base, main_#t~ret852#1.offset; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,542 INFO L272 TraceCheckUtils]: 90: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} call main_#t~ret853#1.base, main_#t~ret853#1.offset := ldv_memset(main_~#ldvarg5~0#1.base, main_~#ldvarg5~0#1.offset, 0, 4); {14499#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:30:34,542 INFO L290 TraceCheckUtils]: 91: Hoare triple {14499#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~s#1.base, ~s#1.offset := #in~s#1.base, #in~s#1.offset;~c#1 := #in~c#1;~n#1 := #in~n#1;havoc ~tmp~3#1.base, ~tmp~3#1.offset;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := ~s#1.base, ~s#1.offset, ~c#1, ~n#1;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr938#1;#Ultimate.C_memset_#t~loopctr938#1 := 0; {14324#true} is VALID [2022-02-20 22:30:34,542 INFO L290 TraceCheckUtils]: 92: Hoare triple {14324#true} assume !(#Ultimate.C_memset_#t~loopctr938#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {14324#true} is VALID [2022-02-20 22:30:34,542 INFO L290 TraceCheckUtils]: 93: Hoare triple {14324#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;#t~memset~res23#1.base, #t~memset~res23#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;~tmp~3#1.base, ~tmp~3#1.offset := ~s#1.base, ~s#1.offset;havoc #t~memset~res23#1.base, #t~memset~res23#1.offset;#res#1.base, #res#1.offset := ~tmp~3#1.base, ~tmp~3#1.offset; {14324#true} is VALID [2022-02-20 22:30:34,542 INFO L290 TraceCheckUtils]: 94: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,543 INFO L284 TraceCheckUtils]: 95: Hoare quadruple {14324#true} {14326#(= ~ldv_irq_1_0~0 0)} #4833#return; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,543 INFO L290 TraceCheckUtils]: 96: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} havoc main_#t~ret853#1.base, main_#t~ret853#1.offset;~ldv_state_variable_4~0 := 0;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,543 INFO L290 TraceCheckUtils]: 97: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet854#1 && main_#t~nondet854#1 <= 2147483647;main_~tmp___4~8#1 := main_#t~nondet854#1;havoc main_#t~nondet854#1;main_#t~switch855#1 := 0 == main_~tmp___4~8#1; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,543 INFO L290 TraceCheckUtils]: 98: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} assume !main_#t~switch855#1;main_#t~switch855#1 := main_#t~switch855#1 || 1 == main_~tmp___4~8#1; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,544 INFO L290 TraceCheckUtils]: 99: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} assume main_#t~switch855#1; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,544 INFO L290 TraceCheckUtils]: 100: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet840#1, choose_interrupt_1_#t~switch841#1, choose_interrupt_1_#t~ret842#1, choose_interrupt_1_#t~ret843#1, choose_interrupt_1_#t~ret844#1, choose_interrupt_1_#t~ret845#1, choose_interrupt_1_~tmp~52#1;havoc choose_interrupt_1_~tmp~52#1;assume -2147483648 <= choose_interrupt_1_#t~nondet840#1 && choose_interrupt_1_#t~nondet840#1 <= 2147483647;choose_interrupt_1_~tmp~52#1 := choose_interrupt_1_#t~nondet840#1;havoc choose_interrupt_1_#t~nondet840#1;choose_interrupt_1_#t~switch841#1 := 0 == choose_interrupt_1_~tmp~52#1; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,544 INFO L290 TraceCheckUtils]: 101: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch841#1; {14326#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:30:34,545 INFO L272 TraceCheckUtils]: 102: Hoare triple {14326#(= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret842#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {14407#(= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:30:34,545 INFO L290 TraceCheckUtils]: 103: Hoare triple {14407#(= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~49#1;havoc ~tmp___0~21#1;assume -2147483648 <= #t~nondet834#1 && #t~nondet834#1 <= 2147483647;~tmp~49#1 := #t~nondet834#1;havoc #t~nondet834#1;~irq_retval~0#1 := ~tmp~49#1; {14408#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:30:34,545 INFO L290 TraceCheckUtils]: 104: Hoare triple {14408#(= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet835#1 && #t~nondet835#1 <= 2147483647;~tmp___0~21#1 := #t~nondet835#1;havoc #t~nondet835#1;#t~switch836#1 := 0 == ~tmp___0~21#1; {14325#false} is VALID [2022-02-20 22:30:34,546 INFO L290 TraceCheckUtils]: 105: Hoare triple {14325#false} assume #t~switch836#1; {14325#false} is VALID [2022-02-20 22:30:34,546 INFO L290 TraceCheckUtils]: 106: Hoare triple {14325#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_via_ircc_interrupt } true;via_ircc_interrupt_#in~dummy#1, via_ircc_interrupt_#in~dev_id#1.base, via_ircc_interrupt_#in~dev_id#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc via_ircc_interrupt_#res#1;havoc via_ircc_interrupt_#t~ret711#1.base, via_ircc_interrupt_#t~ret711#1.offset, via_ircc_interrupt_#t~mem712#1, via_ircc_interrupt_#t~ret713#1, via_ircc_interrupt_#t~mem714#1, via_ircc_interrupt_#t~ret715#1, via_ircc_interrupt_#t~ite716#1.base, via_ircc_interrupt_#t~ite716#1.offset, via_ircc_interrupt_#t~ite717#1.base, via_ircc_interrupt_#t~ite717#1.offset, via_ircc_interrupt_#t~ite718#1.base, via_ircc_interrupt_#t~ite718#1.offset, via_ircc_interrupt_#t~mem719#1, via_ircc_interrupt_#t~ret720#1, via_ircc_interrupt_#t~mem721#1, via_ircc_interrupt_#t~ret722#1, via_ircc_interrupt_#t~mem723#1, via_ircc_interrupt_#t~mem724#1, via_ircc_interrupt_#t~mem725#1.base, via_ircc_interrupt_#t~mem725#1.offset, via_ircc_interrupt_#t~ret726#1, via_ircc_interrupt_#t~ret727#1, via_ircc_interrupt_#t~ret728#1, via_ircc_interrupt_#t~ret729#1, via_ircc_interrupt_#t~mem730#1, via_ircc_interrupt_#t~ret731#1, via_ircc_interrupt_#t~ite732#1.base, via_ircc_interrupt_#t~ite732#1.offset, via_ircc_interrupt_#t~ite733#1.base, via_ircc_interrupt_#t~ite733#1.offset, via_ircc_interrupt_#t~ite734#1.base, via_ircc_interrupt_#t~ite734#1.offset, via_ircc_interrupt_#t~ite735#1.base, via_ircc_interrupt_#t~ite735#1.offset, via_ircc_interrupt_#t~mem736#1, via_ircc_interrupt_#t~ret737#1, via_ircc_interrupt_#t~mem738#1.base, via_ircc_interrupt_#t~mem738#1.offset, via_ircc_interrupt_#t~ret739#1, via_ircc_interrupt_#t~ret740#1, via_ircc_interrupt_#t~mem741#1, via_ircc_interrupt_#t~ret742#1, via_ircc_interrupt_#t~mem743#1, via_ircc_interrupt_#t~ret744#1, via_ircc_interrupt_#t~ite745#1.base, via_ircc_interrupt_#t~ite745#1.offset, via_ircc_interrupt_#t~ite746#1.base, via_ircc_interrupt_#t~ite746#1.offset, via_ircc_interrupt_#t~ite747#1.base, via_ircc_interrupt_#t~ite747#1.offset, via_ircc_interrupt_#t~ite748#1.base, via_ircc_interrupt_#t~ite748#1.offset, via_ircc_interrupt_#t~ite749#1.base, via_ircc_interrupt_#t~ite749#1.offset, via_ircc_interrupt_#t~ite750#1.base, via_ircc_interrupt_#t~ite750#1.offset, via_ircc_interrupt_#t~ite751#1.base, via_ircc_interrupt_#t~ite751#1.offset, via_ircc_interrupt_#t~mem752#1, via_ircc_interrupt_#t~ret753#1, via_ircc_interrupt_#t~ret754#1, via_ircc_interrupt_#t~ret755#1, via_ircc_interrupt_#t~mem756#1, via_ircc_interrupt_#t~ret757#1, via_ircc_interrupt_#t~ret758#1, via_ircc_interrupt_#t~mem759#1, via_ircc_interrupt_#t~ret760#1, via_ircc_interrupt_~dummy#1, via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset, via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset, via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset, via_ircc_interrupt_~tmp~44#1.base, via_ircc_interrupt_~tmp~44#1.offset, via_ircc_interrupt_~iobase~7#1, via_ircc_interrupt_~iHostIntType~0#1, via_ircc_interrupt_~iRxIntType~0#1, via_ircc_interrupt_~iTxIntType~0#1, via_ircc_interrupt_~#descriptor~11#1.base, via_ircc_interrupt_~#descriptor~11#1.offset, via_ircc_interrupt_~tmp___0~17#1, via_ircc_interrupt_~tmp___1~12#1, via_ircc_interrupt_~#descriptor___0~4#1.base, via_ircc_interrupt_~#descriptor___0~4#1.offset, via_ircc_interrupt_~tmp___2~8#1, via_ircc_interrupt_~tmp___3~5#1, via_ircc_interrupt_~tmp___4~5#1, via_ircc_interrupt_~#descriptor___1~3#1.base, via_ircc_interrupt_~#descriptor___1~3#1.offset, via_ircc_interrupt_~tmp___5~5#1, via_ircc_interrupt_~#descriptor___2~1#1.base, via_ircc_interrupt_~#descriptor___2~1#1.offset, via_ircc_interrupt_~tmp___6~4#1, via_ircc_interrupt_~tmp___7~2#1, via_ircc_interrupt_~#descriptor___3~1#1.base, via_ircc_interrupt_~#descriptor___3~1#1.offset, via_ircc_interrupt_~tmp___8~2#1, via_ircc_interrupt_~tmp___9~2#1;via_ircc_interrupt_~dummy#1 := via_ircc_interrupt_#in~dummy#1;via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset := via_ircc_interrupt_#in~dev_id#1.base, via_ircc_interrupt_#in~dev_id#1.offset;havoc via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset;havoc via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset;havoc via_ircc_interrupt_~tmp~44#1.base, via_ircc_interrupt_~tmp~44#1.offset;havoc via_ircc_interrupt_~iobase~7#1;havoc via_ircc_interrupt_~iHostIntType~0#1;havoc via_ircc_interrupt_~iRxIntType~0#1;havoc via_ircc_interrupt_~iTxIntType~0#1;call via_ircc_interrupt_~#descriptor~11#1.base, via_ircc_interrupt_~#descriptor~11#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___0~17#1;havoc via_ircc_interrupt_~tmp___1~12#1;call via_ircc_interrupt_~#descriptor___0~4#1.base, via_ircc_interrupt_~#descriptor___0~4#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___2~8#1;havoc via_ircc_interrupt_~tmp___3~5#1;havoc via_ircc_interrupt_~tmp___4~5#1;call via_ircc_interrupt_~#descriptor___1~3#1.base, via_ircc_interrupt_~#descriptor___1~3#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___5~5#1;call via_ircc_interrupt_~#descriptor___2~1#1.base, via_ircc_interrupt_~#descriptor___2~1#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___6~4#1;havoc via_ircc_interrupt_~tmp___7~2#1;call via_ircc_interrupt_~#descriptor___3~1#1.base, via_ircc_interrupt_~#descriptor___3~1#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_interrupt_~tmp___8~2#1;havoc via_ircc_interrupt_~tmp___9~2#1;via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset := via_ircc_interrupt_~dev_id#1.base, via_ircc_interrupt_~dev_id#1.offset; {14325#false} is VALID [2022-02-20 22:30:34,546 INFO L272 TraceCheckUtils]: 107: Hoare triple {14325#false} call via_ircc_interrupt_#t~ret711#1.base, via_ircc_interrupt_#t~ret711#1.offset := netdev_priv(via_ircc_interrupt_~dev~2#1.base, via_ircc_interrupt_~dev~2#1.offset); {14324#true} is VALID [2022-02-20 22:30:34,546 INFO L290 TraceCheckUtils]: 108: Hoare triple {14324#true} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;#res.base, #res.offset := ~dev.base, 3008 + ~dev.offset; {14324#true} is VALID [2022-02-20 22:30:34,546 INFO L290 TraceCheckUtils]: 109: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,546 INFO L284 TraceCheckUtils]: 110: Hoare quadruple {14324#true} {14325#false} #4211#return; {14325#false} is VALID [2022-02-20 22:30:34,546 INFO L290 TraceCheckUtils]: 111: Hoare triple {14325#false} via_ircc_interrupt_~tmp~44#1.base, via_ircc_interrupt_~tmp~44#1.offset := via_ircc_interrupt_#t~ret711#1.base, via_ircc_interrupt_#t~ret711#1.offset;havoc via_ircc_interrupt_#t~ret711#1.base, via_ircc_interrupt_#t~ret711#1.offset;via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset := via_ircc_interrupt_~tmp~44#1.base, via_ircc_interrupt_~tmp~44#1.offset;call via_ircc_interrupt_#t~mem712#1 := read~int(via_ircc_interrupt_~self~4#1.base, 292 + via_ircc_interrupt_~self~4#1.offset, 4);via_ircc_interrupt_~iobase~7#1 := via_ircc_interrupt_#t~mem712#1;havoc via_ircc_interrupt_#t~mem712#1;assume { :begin_inline_spin_lock } true;spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset := via_ircc_interrupt_~self~4#1.base, 457 + via_ircc_interrupt_~self~4#1.offset;havoc spin_lock_~lock#1.base, spin_lock_~lock#1.offset;spin_lock_~lock#1.base, spin_lock_~lock#1.offset := spin_lock_#in~lock#1.base, spin_lock_#in~lock#1.offset; {14325#false} is VALID [2022-02-20 22:30:34,546 INFO L272 TraceCheckUtils]: 112: Hoare triple {14325#false} call ldv_spin_lock(); {14500#(= ~ldv_spin~0 |old(~ldv_spin~0)|)} is VALID [2022-02-20 22:30:34,546 INFO L290 TraceCheckUtils]: 113: Hoare triple {14500#(= ~ldv_spin~0 |old(~ldv_spin~0)|)} ~ldv_spin~0 := 1; {14324#true} is VALID [2022-02-20 22:30:34,547 INFO L290 TraceCheckUtils]: 114: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,558 INFO L284 TraceCheckUtils]: 115: Hoare quadruple {14324#true} {14325#false} #4213#return; {14325#false} is VALID [2022-02-20 22:30:34,571 INFO L290 TraceCheckUtils]: 116: Hoare triple {14325#false} assume { :begin_inline_ldv_spin_lock_5 } true;ldv_spin_lock_5_#in~lock#1.base, ldv_spin_lock_5_#in~lock#1.offset := spin_lock_~lock#1.base, spin_lock_~lock#1.offset;havoc ldv_spin_lock_5_~lock#1.base, ldv_spin_lock_5_~lock#1.offset;ldv_spin_lock_5_~lock#1.base, ldv_spin_lock_5_~lock#1.offset := ldv_spin_lock_5_#in~lock#1.base, ldv_spin_lock_5_#in~lock#1.offset;assume { :begin_inline__raw_spin_lock } true;_raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset := ldv_spin_lock_5_~lock#1.base, ldv_spin_lock_5_~lock#1.offset;havoc _raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset;_raw_spin_lock_~arg0#1.base, _raw_spin_lock_~arg0#1.offset := _raw_spin_lock_#in~arg0#1.base, _raw_spin_lock_#in~arg0#1.offset; {14325#false} is VALID [2022-02-20 22:30:34,571 INFO L290 TraceCheckUtils]: 117: Hoare triple {14325#false} assume { :end_inline__raw_spin_lock } true; {14325#false} is VALID [2022-02-20 22:30:34,571 INFO L290 TraceCheckUtils]: 118: Hoare triple {14325#false} assume { :end_inline_ldv_spin_lock_5 } true; {14325#false} is VALID [2022-02-20 22:30:34,571 INFO L290 TraceCheckUtils]: 119: Hoare triple {14325#false} assume { :end_inline_spin_lock } true; {14325#false} is VALID [2022-02-20 22:30:34,572 INFO L272 TraceCheckUtils]: 120: Hoare triple {14325#false} call via_ircc_interrupt_#t~ret713#1 := ReadReg(via_ircc_interrupt_~iobase~7#1, 33); {14324#true} is VALID [2022-02-20 22:30:34,572 INFO L290 TraceCheckUtils]: 121: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,572 INFO L272 TraceCheckUtils]: 122: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,572 INFO L290 TraceCheckUtils]: 123: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,572 INFO L290 TraceCheckUtils]: 124: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,572 INFO L284 TraceCheckUtils]: 125: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,572 INFO L290 TraceCheckUtils]: 126: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,572 INFO L290 TraceCheckUtils]: 127: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,572 INFO L284 TraceCheckUtils]: 128: Hoare quadruple {14324#true} {14325#false} #4215#return; {14325#false} is VALID [2022-02-20 22:30:34,573 INFO L290 TraceCheckUtils]: 129: Hoare triple {14325#false} via_ircc_interrupt_~iHostIntType~0#1 := via_ircc_interrupt_#t~ret713#1;havoc via_ircc_interrupt_#t~ret713#1;call write~$Pointer$(141, 0, via_ircc_interrupt_~#descriptor~11#1.base, via_ircc_interrupt_~#descriptor~11#1.offset, 8);call write~$Pointer$(142, 0, via_ircc_interrupt_~#descriptor~11#1.base, 8 + via_ircc_interrupt_~#descriptor~11#1.offset, 8);call write~$Pointer$(143, 0, via_ircc_interrupt_~#descriptor~11#1.base, 16 + via_ircc_interrupt_~#descriptor~11#1.offset, 8);call write~$Pointer$(144, 0, via_ircc_interrupt_~#descriptor~11#1.base, 24 + via_ircc_interrupt_~#descriptor~11#1.offset, 8);call write~int(1297, via_ircc_interrupt_~#descriptor~11#1.base, 32 + via_ircc_interrupt_~#descriptor~11#1.offset, 4);call write~int(0, via_ircc_interrupt_~#descriptor~11#1.base, 36 + via_ircc_interrupt_~#descriptor~11#1.offset, 1);call via_ircc_interrupt_#t~mem714#1 := read~int(via_ircc_interrupt_~#descriptor~11#1.base, 36 + via_ircc_interrupt_~#descriptor~11#1.offset, 1); {14325#false} is VALID [2022-02-20 22:30:34,573 INFO L272 TraceCheckUtils]: 130: Hoare triple {14325#false} call via_ircc_interrupt_#t~ret715#1 := ldv__builtin_expect(via_ircc_interrupt_#t~mem714#1 % 256, 0); {14324#true} is VALID [2022-02-20 22:30:34,573 INFO L290 TraceCheckUtils]: 131: Hoare triple {14324#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {14324#true} is VALID [2022-02-20 22:30:34,573 INFO L290 TraceCheckUtils]: 132: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,573 INFO L284 TraceCheckUtils]: 133: Hoare quadruple {14324#true} {14325#false} #4217#return; {14325#false} is VALID [2022-02-20 22:30:34,573 INFO L290 TraceCheckUtils]: 134: Hoare triple {14325#false} assume -9223372036854775808 <= via_ircc_interrupt_#t~ret715#1 && via_ircc_interrupt_#t~ret715#1 <= 9223372036854775807;via_ircc_interrupt_~tmp___0~17#1 := via_ircc_interrupt_#t~ret715#1;havoc via_ircc_interrupt_#t~mem714#1;havoc via_ircc_interrupt_#t~ret715#1; {14325#false} is VALID [2022-02-20 22:30:34,573 INFO L290 TraceCheckUtils]: 135: Hoare triple {14325#false} assume !(0 != via_ircc_interrupt_~tmp___0~17#1); {14325#false} is VALID [2022-02-20 22:30:34,573 INFO L290 TraceCheckUtils]: 136: Hoare triple {14325#false} assume !(0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 64)))); {14325#false} is VALID [2022-02-20 22:30:34,573 INFO L290 TraceCheckUtils]: 137: Hoare triple {14325#false} assume !(0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 32)))); {14325#false} is VALID [2022-02-20 22:30:34,574 INFO L290 TraceCheckUtils]: 138: Hoare triple {14325#false} assume 0 != (if 0 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iHostIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iHostIntType~0#1 % 256, 16))); {14325#false} is VALID [2022-02-20 22:30:34,574 INFO L272 TraceCheckUtils]: 139: Hoare triple {14325#false} call via_ircc_interrupt_#t~ret742#1 := ReadReg(via_ircc_interrupt_~iobase~7#1, 39); {14324#true} is VALID [2022-02-20 22:30:34,574 INFO L290 TraceCheckUtils]: 140: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,574 INFO L272 TraceCheckUtils]: 141: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,574 INFO L290 TraceCheckUtils]: 142: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,574 INFO L290 TraceCheckUtils]: 143: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,574 INFO L284 TraceCheckUtils]: 144: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,574 INFO L290 TraceCheckUtils]: 145: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,574 INFO L290 TraceCheckUtils]: 146: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,575 INFO L284 TraceCheckUtils]: 147: Hoare quadruple {14324#true} {14325#false} #4311#return; {14325#false} is VALID [2022-02-20 22:30:34,575 INFO L290 TraceCheckUtils]: 148: Hoare triple {14325#false} via_ircc_interrupt_~iRxIntType~0#1 := via_ircc_interrupt_#t~ret742#1;havoc via_ircc_interrupt_#t~ret742#1;call write~$Pointer$(167, 0, via_ircc_interrupt_~#descriptor___1~3#1.base, via_ircc_interrupt_~#descriptor___1~3#1.offset, 8);call write~$Pointer$(168, 0, via_ircc_interrupt_~#descriptor___1~3#1.base, 8 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 8);call write~$Pointer$(169, 0, via_ircc_interrupt_~#descriptor___1~3#1.base, 16 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 8);call write~$Pointer$(170, 0, via_ircc_interrupt_~#descriptor___1~3#1.base, 24 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 8);call write~int(1354, via_ircc_interrupt_~#descriptor___1~3#1.base, 32 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 4);call write~int(0, via_ircc_interrupt_~#descriptor___1~3#1.base, 36 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 1);call via_ircc_interrupt_#t~mem743#1 := read~int(via_ircc_interrupt_~#descriptor___1~3#1.base, 36 + via_ircc_interrupt_~#descriptor___1~3#1.offset, 1); {14325#false} is VALID [2022-02-20 22:30:34,575 INFO L272 TraceCheckUtils]: 149: Hoare triple {14325#false} call via_ircc_interrupt_#t~ret744#1 := ldv__builtin_expect(via_ircc_interrupt_#t~mem743#1 % 256, 0); {14324#true} is VALID [2022-02-20 22:30:34,575 INFO L290 TraceCheckUtils]: 150: Hoare triple {14324#true} ~exp := #in~exp;~c := #in~c;#res := ~exp; {14324#true} is VALID [2022-02-20 22:30:34,575 INFO L290 TraceCheckUtils]: 151: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,575 INFO L284 TraceCheckUtils]: 152: Hoare quadruple {14324#true} {14325#false} #4313#return; {14325#false} is VALID [2022-02-20 22:30:34,575 INFO L290 TraceCheckUtils]: 153: Hoare triple {14325#false} assume -9223372036854775808 <= via_ircc_interrupt_#t~ret744#1 && via_ircc_interrupt_#t~ret744#1 <= 9223372036854775807;via_ircc_interrupt_~tmp___5~5#1 := via_ircc_interrupt_#t~ret744#1;havoc via_ircc_interrupt_#t~mem743#1;havoc via_ircc_interrupt_#t~ret744#1; {14325#false} is VALID [2022-02-20 22:30:34,575 INFO L290 TraceCheckUtils]: 154: Hoare triple {14325#false} assume !(0 != via_ircc_interrupt_~tmp___5~5#1); {14325#false} is VALID [2022-02-20 22:30:34,575 INFO L290 TraceCheckUtils]: 155: Hoare triple {14325#false} assume !(0 == via_ircc_interrupt_~iRxIntType~0#1 % 256 % 4294967296); {14325#false} is VALID [2022-02-20 22:30:34,576 INFO L290 TraceCheckUtils]: 156: Hoare triple {14325#false} assume 0 != (if 0 == via_ircc_interrupt_~iRxIntType~0#1 % 256 then 0 else (if 1 == via_ircc_interrupt_~iRxIntType~0#1 % 256 then 0 else ~bitwiseAnd(via_ircc_interrupt_~iRxIntType~0#1 % 256, 16)));assume { :begin_inline_via_ircc_dma_receive_complete } true;via_ircc_dma_receive_complete_#in~self#1.base, via_ircc_dma_receive_complete_#in~self#1.offset, via_ircc_dma_receive_complete_#in~iobase#1 := via_ircc_interrupt_~self~4#1.base, via_ircc_interrupt_~self~4#1.offset, via_ircc_interrupt_~iobase~7#1;havoc via_ircc_dma_receive_complete_#res#1;havoc via_ircc_dma_receive_complete_#t~mem563#1, via_ircc_dma_receive_complete_#t~mem564#1, via_ircc_dma_receive_complete_#t~ret565#1, via_ircc_dma_receive_complete_#t~ret566#1.base, via_ircc_dma_receive_complete_#t~ret566#1.offset, via_ircc_dma_receive_complete_#t~ret567#1.base, via_ircc_dma_receive_complete_#t~ret567#1.offset, via_ircc_dma_receive_complete_#t~mem568#1, via_ircc_dma_receive_complete_#t~mem569#1.base, via_ircc_dma_receive_complete_#t~mem569#1.offset, via_ircc_dma_receive_complete_#t~mem570#1.base, via_ircc_dma_receive_complete_#t~mem570#1.offset, via_ircc_dma_receive_complete_#t~mem571#1, via_ircc_dma_receive_complete_#t~mem572#1, via_ircc_dma_receive_complete_#t~mem573#1.base, via_ircc_dma_receive_complete_#t~mem573#1.offset, via_ircc_dma_receive_complete_#t~mem574#1.base, via_ircc_dma_receive_complete_#t~mem574#1.offset, via_ircc_dma_receive_complete_#t~mem575#1, via_ircc_dma_receive_complete_#t~mem576#1.base, via_ircc_dma_receive_complete_#t~mem576#1.offset, via_ircc_dma_receive_complete_#t~mem577#1.base, via_ircc_dma_receive_complete_#t~mem577#1.offset, via_ircc_dma_receive_complete_#t~mem578#1.base, via_ircc_dma_receive_complete_#t~mem578#1.offset, via_ircc_dma_receive_complete_#t~mem579#1, via_ircc_dma_receive_complete_#t~mem580#1.base, via_ircc_dma_receive_complete_#t~mem580#1.offset, via_ircc_dma_receive_complete_#t~mem581#1.base, via_ircc_dma_receive_complete_#t~mem581#1.offset, via_ircc_dma_receive_complete_#t~mem582#1, via_ircc_dma_receive_complete_#t~mem583#1.base, via_ircc_dma_receive_complete_#t~mem583#1.offset, via_ircc_dma_receive_complete_#t~ret584#1, via_ircc_dma_receive_complete_#t~ret585#1, via_ircc_dma_receive_complete_#t~mem586#1, via_ircc_dma_receive_complete_#t~ret587#1, via_ircc_dma_receive_complete_#t~ret588#1, via_ircc_dma_receive_complete_#t~mem589#1, via_ircc_dma_receive_complete_#t~mem590#1, via_ircc_dma_receive_complete_#t~ret591#1, via_ircc_dma_receive_complete_#t~ret592#1, via_ircc_dma_receive_complete_#t~mem593#1, via_ircc_dma_receive_complete_#t~mem594#1, via_ircc_dma_receive_complete_#t~mem595#1, via_ircc_dma_receive_complete_#t~mem596#1, via_ircc_dma_receive_complete_#t~mem597#1, via_ircc_dma_receive_complete_#t~mem598#1, via_ircc_dma_receive_complete_#t~mem599#1, via_ircc_dma_receive_complete_#t~ret600#1, via_ircc_dma_receive_complete_#t~ret601#1, via_ircc_dma_receive_complete_#t~ret602#1, via_ircc_dma_receive_complete_#t~mem603#1, via_ircc_dma_receive_complete_#t~mem604#1, via_ircc_dma_receive_complete_#t~mem605#1, via_ircc_dma_receive_complete_#t~mem606#1, via_ircc_dma_receive_complete_#t~mem607#1, via_ircc_dma_receive_complete_#t~mem608#1, via_ircc_dma_receive_complete_#t~mem609#1, via_ircc_dma_receive_complete_#t~ret610#1.base, via_ircc_dma_receive_complete_#t~ret610#1.offset, via_ircc_dma_receive_complete_#t~mem611#1.base, via_ircc_dma_receive_complete_#t~mem611#1.offset, via_ircc_dma_receive_complete_#t~short612#1, via_ircc_dma_receive_complete_#t~mem613#1.base, via_ircc_dma_receive_complete_#t~mem613#1.offset, via_ircc_dma_receive_complete_#t~short614#1, via_ircc_dma_receive_complete_#t~mem615#1.base, via_ircc_dma_receive_complete_#t~mem615#1.offset, via_ircc_dma_receive_complete_#t~mem616#1.base, via_ircc_dma_receive_complete_#t~mem616#1.offset, via_ircc_dma_receive_complete_#t~mem617#1, via_ircc_dma_receive_complete_#t~ret618#1.base, via_ircc_dma_receive_complete_#t~ret618#1.offset, via_ircc_dma_receive_complete_#t~mem619#1.base, via_ircc_dma_receive_complete_#t~mem619#1.offset, via_ircc_dma_receive_complete_#t~mem620#1, via_ircc_dma_receive_complete_#t~ret621#1, via_ircc_dma_receive_complete_#t~mem622#1.base, via_ircc_dma_receive_complete_#t~mem622#1.offset, via_ircc_dma_receive_complete_#t~mem623#1.base, via_ircc_dma_receive_complete_#t~mem623#1.offset, via_ircc_dma_receive_complete_#t~mem624#1.base, via_ircc_dma_receive_complete_#t~mem624#1.offset, via_ircc_dma_receive_complete_#t~mem625#1.base, via_ircc_dma_receive_complete_#t~mem625#1.offset, via_ircc_dma_receive_complete_#t~mem626#1, via_ircc_dma_receive_complete_#t~mem627#1.base, via_ircc_dma_receive_complete_#t~mem627#1.offset, via_ircc_dma_receive_complete_#t~mem628#1.base, via_ircc_dma_receive_complete_#t~mem628#1.offset, via_ircc_dma_receive_complete_#t~mem629#1, via_ircc_dma_receive_complete_#t~mem630#1.base, via_ircc_dma_receive_complete_#t~mem630#1.offset, via_ircc_dma_receive_complete_#t~ret631#1, via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset, via_ircc_dma_receive_complete_~iobase#1, via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset, via_ircc_dma_receive_complete_~skb~0#1.base, via_ircc_dma_receive_complete_~skb~0#1.offset, via_ircc_dma_receive_complete_~len~0#1, via_ircc_dma_receive_complete_~i~8#1, via_ircc_dma_receive_complete_~status~0#1, via_ircc_dma_receive_complete_~tmp~41#1, via_ircc_dma_receive_complete_~tmp___0~14#1, via_ircc_dma_receive_complete_~#descriptor~8#1.base, via_ircc_dma_receive_complete_~#descriptor~8#1.offset, via_ircc_dma_receive_complete_~tmp___1~10#1, via_ircc_dma_receive_complete_~tmp___2~6#1, via_ircc_dma_receive_complete_~#descriptor___0~2#1.base, via_ircc_dma_receive_complete_~#descriptor___0~2#1.offset, via_ircc_dma_receive_complete_~tmp___3~3#1, via_ircc_dma_receive_complete_~tmp___4~3#1, via_ircc_dma_receive_complete_~#descriptor___1~2#1.base, via_ircc_dma_receive_complete_~#descriptor___1~2#1.offset, via_ircc_dma_receive_complete_~tmp___5~3#1;via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset := via_ircc_dma_receive_complete_#in~self#1.base, via_ircc_dma_receive_complete_#in~self#1.offset;via_ircc_dma_receive_complete_~iobase#1 := via_ircc_dma_receive_complete_#in~iobase#1;havoc via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset;havoc via_ircc_dma_receive_complete_~skb~0#1.base, via_ircc_dma_receive_complete_~skb~0#1.offset;havoc via_ircc_dma_receive_complete_~len~0#1;havoc via_ircc_dma_receive_complete_~i~8#1;havoc via_ircc_dma_receive_complete_~status~0#1;havoc via_ircc_dma_receive_complete_~tmp~41#1;havoc via_ircc_dma_receive_complete_~tmp___0~14#1;call via_ircc_dma_receive_complete_~#descriptor~8#1.base, via_ircc_dma_receive_complete_~#descriptor~8#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_dma_receive_complete_~tmp___1~10#1;havoc via_ircc_dma_receive_complete_~tmp___2~6#1;call via_ircc_dma_receive_complete_~#descriptor___0~2#1.base, via_ircc_dma_receive_complete_~#descriptor___0~2#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_dma_receive_complete_~tmp___3~3#1;havoc via_ircc_dma_receive_complete_~tmp___4~3#1;call via_ircc_dma_receive_complete_~#descriptor___1~2#1.base, via_ircc_dma_receive_complete_~#descriptor___1~2#1.offset := #Ultimate.allocOnStack(37);havoc via_ircc_dma_receive_complete_~tmp___5~3#1;via_ircc_dma_receive_complete_~status~0#1 := 0;call via_ircc_dma_receive_complete_#t~mem563#1 := read~int(via_ircc_dma_receive_complete_~self#1.base, 292 + via_ircc_dma_receive_complete_~self#1.offset, 4);via_ircc_dma_receive_complete_~iobase#1 := via_ircc_dma_receive_complete_#t~mem563#1;havoc via_ircc_dma_receive_complete_#t~mem563#1;via_ircc_dma_receive_complete_~st_fifo~0#1.base, via_ircc_dma_receive_complete_~st_fifo~0#1.offset := via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset;call via_ircc_dma_receive_complete_#t~mem564#1 := read~int(via_ircc_dma_receive_complete_~self#1.base, 344 + via_ircc_dma_receive_complete_~self#1.offset, 4); {14325#false} is VALID [2022-02-20 22:30:34,576 INFO L290 TraceCheckUtils]: 157: Hoare triple {14325#false} assume via_ircc_dma_receive_complete_#t~mem564#1 % 4294967296 <= 3999999;havoc via_ircc_dma_receive_complete_#t~mem564#1; {14325#false} is VALID [2022-02-20 22:30:34,576 INFO L272 TraceCheckUtils]: 158: Hoare triple {14325#false} call via_ircc_dma_receive_complete_#t~ret565#1 := GetRecvByte(via_ircc_dma_receive_complete_~iobase#1 % 65536, via_ircc_dma_receive_complete_~self#1.base, via_ircc_dma_receive_complete_~self#1.offset); {14499#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:30:34,576 INFO L290 TraceCheckUtils]: 159: Hoare triple {14499#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} ~iobase := #in~iobase;~self.base, ~self.offset := #in~self.base, #in~self.offset;havoc ~low~4;havoc ~high~4;havoc ~wTmp~2;havoc ~wTmp1~2;havoc ~ret~0; {14324#true} is VALID [2022-02-20 22:30:34,576 INFO L272 TraceCheckUtils]: 160: Hoare triple {14324#true} call #t~ret178 := ReadReg(~iobase % 65536, 44); {14324#true} is VALID [2022-02-20 22:30:34,576 INFO L290 TraceCheckUtils]: 161: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,576 INFO L272 TraceCheckUtils]: 162: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,576 INFO L290 TraceCheckUtils]: 163: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,576 INFO L290 TraceCheckUtils]: 164: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,577 INFO L284 TraceCheckUtils]: 165: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,577 INFO L290 TraceCheckUtils]: 166: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,577 INFO L290 TraceCheckUtils]: 167: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,577 INFO L284 TraceCheckUtils]: 168: Hoare quadruple {14324#true} {14324#true} #4207#return; {14324#true} is VALID [2022-02-20 22:30:34,577 INFO L290 TraceCheckUtils]: 169: Hoare triple {14324#true} ~low~4 := #t~ret178;havoc #t~ret178; {14324#true} is VALID [2022-02-20 22:30:34,577 INFO L272 TraceCheckUtils]: 170: Hoare triple {14324#true} call #t~ret179 := ReadReg(~iobase % 65536, 45); {14324#true} is VALID [2022-02-20 22:30:34,577 INFO L290 TraceCheckUtils]: 171: Hoare triple {14324#true} ~BaseAddr := #in~BaseAddr;~iRegNum := #in~iRegNum;havoc ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,577 INFO L272 TraceCheckUtils]: 172: Hoare triple {14324#true} call #t~ret155 := inb((if (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 <= 2147483647 then (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 else (~BaseAddr + ~iRegNum) % 4294967296 % 4294967296 - 4294967296)); {14324#true} is VALID [2022-02-20 22:30:34,577 INFO L290 TraceCheckUtils]: 173: Hoare triple {14324#true} ~port := #in~port;havoc ~value~0;#res := ~value~0; {14324#true} is VALID [2022-02-20 22:30:34,578 INFO L290 TraceCheckUtils]: 174: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,578 INFO L284 TraceCheckUtils]: 175: Hoare quadruple {14324#true} {14324#true} #3995#return; {14324#true} is VALID [2022-02-20 22:30:34,578 INFO L290 TraceCheckUtils]: 176: Hoare triple {14324#true} ~tmp~19 := #t~ret155;havoc #t~ret155;#res := ~tmp~19; {14324#true} is VALID [2022-02-20 22:30:34,578 INFO L290 TraceCheckUtils]: 177: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,578 INFO L284 TraceCheckUtils]: 178: Hoare quadruple {14324#true} {14324#true} #4209#return; {14324#true} is VALID [2022-02-20 22:30:34,579 INFO L290 TraceCheckUtils]: 179: Hoare triple {14324#true} ~high~4 := #t~ret179;havoc #t~ret179;~wTmp1~2 := ~high~4 % 256;~wTmp~2 := (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 0 == ~low~4 % 256 then (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) else (if 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256) then ~low~4 % 256 else (if (1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) && (1 == ~low~4 % 256 || 0 == ~low~4 % 256)) || ((1 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536) || 0 == (if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536)) && 1 == ~low~4 % 256) then 1 else ~bitwiseOr((if 256 * (~wTmp1~2 % 65536) % 65536 <= 32767 then 256 * (~wTmp1~2 % 65536) % 65536 else 256 * (~wTmp1~2 % 65536) % 65536 - 65536), ~low~4 % 256))));call #t~mem180 := read~int(~self.base, 564 + ~self.offset, 4); {14324#true} is VALID [2022-02-20 22:30:34,579 INFO L290 TraceCheckUtils]: 180: Hoare triple {14324#true} assume ~wTmp~2 % 65536 % 4294967296 >= #t~mem180 % 4294967296;havoc #t~mem180;call #t~mem181 := read~int(~self.base, 564 + ~self.offset, 4);~ret~0 := ~wTmp~2 % 65536 - #t~mem181 % 65536;havoc #t~mem181; {14324#true} is VALID [2022-02-20 22:30:34,579 INFO L290 TraceCheckUtils]: 181: Hoare triple {14324#true} call write~int(~wTmp~2 % 65536, ~self.base, 564 + ~self.offset, 4);#res := ~ret~0; {14324#true} is VALID [2022-02-20 22:30:34,579 INFO L290 TraceCheckUtils]: 182: Hoare triple {14324#true} assume true; {14324#true} is VALID [2022-02-20 22:30:34,579 INFO L284 TraceCheckUtils]: 183: Hoare quadruple {14324#true} {14325#false} #4317#return; {14325#false} is VALID [2022-02-20 22:30:34,579 INFO L290 TraceCheckUtils]: 184: Hoare triple {14325#false} via_ircc_dma_receive_complete_~tmp~41#1 := via_ircc_dma_receive_complete_#t~ret565#1;havoc via_ircc_dma_receive_complete_#t~ret565#1;via_ircc_dma_receive_complete_~len~0#1 := via_ircc_dma_receive_complete_~tmp~41#1 % 65536; {14325#false} is VALID [2022-02-20 22:30:34,579 INFO L272 TraceCheckUtils]: 185: Hoare triple {14325#false} call via_ircc_dma_receive_complete_#t~ret566#1.base, via_ircc_dma_receive_complete_#t~ret566#1.offset := dev_alloc_skb(1 + via_ircc_dma_receive_complete_~len~0#1); {14325#false} is VALID [2022-02-20 22:30:34,579 INFO L290 TraceCheckUtils]: 186: Hoare triple {14325#false} ~length#1 := #in~length#1;havoc ~tmp~9#1.base, ~tmp~9#1.offset;assume { :begin_inline_netdev_alloc_skb } true;netdev_alloc_skb_#in~dev#1.base, netdev_alloc_skb_#in~dev#1.offset, netdev_alloc_skb_#in~length#1 := 0, 0, ~length#1;havoc netdev_alloc_skb_#res#1.base, netdev_alloc_skb_#res#1.offset;havoc netdev_alloc_skb_#t~ret78#1.base, netdev_alloc_skb_#t~ret78#1.offset, netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset, netdev_alloc_skb_~length#1, netdev_alloc_skb_~tmp~8#1.base, netdev_alloc_skb_~tmp~8#1.offset;netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset := netdev_alloc_skb_#in~dev#1.base, netdev_alloc_skb_#in~dev#1.offset;netdev_alloc_skb_~length#1 := netdev_alloc_skb_#in~length#1;havoc netdev_alloc_skb_~tmp~8#1.base, netdev_alloc_skb_~tmp~8#1.offset;assume { :begin_inline_ldv___netdev_alloc_skb_31 } true;ldv___netdev_alloc_skb_31_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_31_#in~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_31_#in~ldv_func_arg2#1, ldv___netdev_alloc_skb_31_#in~flags#1 := netdev_alloc_skb_~dev#1.base, netdev_alloc_skb_~dev#1.offset, netdev_alloc_skb_~length#1, 32;havoc ldv___netdev_alloc_skb_31_#res#1.base, ldv___netdev_alloc_skb_31_#res#1.offset;havoc ldv___netdev_alloc_skb_31_#t~ret893#1.base, ldv___netdev_alloc_skb_31_#t~ret893#1.offset, ldv___netdev_alloc_skb_31_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_31_~ldv_func_arg1#1.offset, ldv___netdev_alloc_skb_31_~ldv_func_arg2#1, ldv___netdev_alloc_skb_31_~flags#1, ldv___netdev_alloc_skb_31_~tmp~58#1.base, ldv___netdev_alloc_skb_31_~tmp~58#1.offset;ldv___netdev_alloc_skb_31_~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_31_~ldv_func_arg1#1.offset := ldv___netdev_alloc_skb_31_#in~ldv_func_arg1#1.base, ldv___netdev_alloc_skb_31_#in~ldv_func_arg1#1.offset;ldv___netdev_alloc_skb_31_~ldv_func_arg2#1 := ldv___netdev_alloc_skb_31_#in~ldv_func_arg2#1;ldv___netdev_alloc_skb_31_~flags#1 := ldv___netdev_alloc_skb_31_#in~flags#1;havoc ldv___netdev_alloc_skb_31_~tmp~58#1.base, ldv___netdev_alloc_skb_31_~tmp~58#1.offset; {14325#false} is VALID [2022-02-20 22:30:34,579 INFO L272 TraceCheckUtils]: 187: Hoare triple {14325#false} call ldv_check_alloc_flags(ldv___netdev_alloc_skb_31_~flags#1); {14325#false} is VALID [2022-02-20 22:30:34,580 INFO L290 TraceCheckUtils]: 188: Hoare triple {14325#false} ~flags := #in~flags; {14325#false} is VALID [2022-02-20 22:30:34,580 INFO L290 TraceCheckUtils]: 189: Hoare triple {14325#false} assume 0 != ~ldv_spin~0 && 0 != (if 0 == ~flags then 0 else (if 1 == ~flags then 0 else ~bitwiseAnd(~flags, 16))) % 4294967296; {14325#false} is VALID [2022-02-20 22:30:34,580 INFO L272 TraceCheckUtils]: 190: Hoare triple {14325#false} call ldv_error(); {14325#false} is VALID [2022-02-20 22:30:34,580 INFO L290 TraceCheckUtils]: 191: Hoare triple {14325#false} assume !false; {14325#false} is VALID [2022-02-20 22:30:34,580 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 196 trivial. 0 not checked. [2022-02-20 22:30:34,581 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:30:34,581 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578966618] [2022-02-20 22:30:34,581 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578966618] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:30:34,581 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:30:34,581 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2022-02-20 22:30:34,581 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242280172] [2022-02-20 22:30:34,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:30:34,583 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 7.888888888888889) internal successors, (71), 4 states have internal predecessors, (71), 3 states have call successors, (23), 7 states have call predecessors, (23), 1 states have return successors, (19), 3 states have call predecessors, (19), 3 states have call successors, (19) Word has length 192 [2022-02-20 22:30:34,584 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:30:34,584 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 9 states, 9 states have (on average 7.888888888888889) internal successors, (71), 4 states have internal predecessors, (71), 3 states have call successors, (23), 7 states have call predecessors, (23), 1 states have return successors, (19), 3 states have call predecessors, (19), 3 states have call successors, (19) [2022-02-20 22:30:34,683 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 113 edges. 113 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:30:34,683 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-02-20 22:30:34,683 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:30:34,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-02-20 22:30:34,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2022-02-20 22:30:34,684 INFO L87 Difference]: Start difference. First operand 1895 states and 2791 transitions. Second operand has 9 states, 9 states have (on average 7.888888888888889) internal successors, (71), 4 states have internal predecessors, (71), 3 states have call successors, (23), 7 states have call predecessors, (23), 1 states have return successors, (19), 3 states have call predecessors, (19), 3 states have call successors, (19) [2022-02-20 22:30:51,453 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.74s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:30:53,438 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.02s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:30:56,370 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.88s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:30:58,913 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.25s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers []