./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--scsi--initio.ko-entry_point.cil.out.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--scsi--initio.ko-entry_point.cil.out.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash bca836bbe3a531e36018faf0b4374aec0682953aa5034dcc910310719152fdea --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 22:32:29,384 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 22:32:29,386 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 22:32:29,419 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 22:32:29,419 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 22:32:29,422 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 22:32:29,422 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 22:32:29,425 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 22:32:29,426 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 22:32:29,429 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 22:32:29,430 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 22:32:29,431 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 22:32:29,431 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 22:32:29,433 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 22:32:29,433 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 22:32:29,435 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 22:32:29,436 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 22:32:29,437 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 22:32:29,438 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 22:32:29,442 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 22:32:29,443 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 22:32:29,443 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 22:32:29,444 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 22:32:29,445 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 22:32:29,449 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 22:32:29,449 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 22:32:29,450 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 22:32:29,451 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 22:32:29,451 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 22:32:29,451 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 22:32:29,452 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 22:32:29,452 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 22:32:29,453 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 22:32:29,454 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 22:32:29,455 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 22:32:29,455 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 22:32:29,455 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 22:32:29,456 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 22:32:29,456 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 22:32:29,456 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 22:32:29,457 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 22:32:29,458 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 22:32:29,477 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 22:32:29,478 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 22:32:29,478 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 22:32:29,478 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 22:32:29,479 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 22:32:29,479 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 22:32:29,479 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 22:32:29,480 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 22:32:29,480 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 22:32:29,480 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 22:32:29,480 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 22:32:29,481 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 22:32:29,481 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 22:32:29,481 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 22:32:29,481 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 22:32:29,481 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 22:32:29,481 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 22:32:29,481 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 22:32:29,482 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 22:32:29,482 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 22:32:29,482 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 22:32:29,482 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:32:29,482 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 22:32:29,482 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 22:32:29,483 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 22:32:29,483 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 22:32:29,483 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 22:32:29,484 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 22:32:29,484 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 22:32:29,484 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 22:32:29,484 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bca836bbe3a531e36018faf0b4374aec0682953aa5034dcc910310719152fdea [2022-02-20 22:32:29,636 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 22:32:29,654 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 22:32:29,655 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 22:32:29,656 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 22:32:29,657 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 22:32:29,657 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--scsi--initio.ko-entry_point.cil.out.i [2022-02-20 22:32:29,699 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f55f93860/4e006fc0c19e403ab1801f817c88040d/FLAG8291f9661 [2022-02-20 22:32:30,279 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 22:32:30,280 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--scsi--initio.ko-entry_point.cil.out.i [2022-02-20 22:32:30,315 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f55f93860/4e006fc0c19e403ab1801f817c88040d/FLAG8291f9661 [2022-02-20 22:32:30,689 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f55f93860/4e006fc0c19e403ab1801f817c88040d [2022-02-20 22:32:30,691 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 22:32:30,692 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 22:32:30,703 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 22:32:30,703 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 22:32:30,705 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 22:32:30,706 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:32:30" (1/1) ... [2022-02-20 22:32:30,707 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@55ef238d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:30, skipping insertion in model container [2022-02-20 22:32:30,707 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:32:30" (1/1) ... [2022-02-20 22:32:30,711 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 22:32:30,800 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 22:32:31,872 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--scsi--initio.ko-entry_point.cil.out.i[238430,238443] [2022-02-20 22:32:31,904 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:32:31,951 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 22:32:32,253 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-linux-4.2-rc1/linux-4.2-rc1.tar.xz-43_2a-drivers--scsi--initio.ko-entry_point.cil.out.i[238430,238443] [2022-02-20 22:32:32,259 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:32:32,316 INFO L208 MainTranslator]: Completed translation [2022-02-20 22:32:32,316 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32 WrapperNode [2022-02-20 22:32:32,317 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 22:32:32,318 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 22:32:32,318 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 22:32:32,318 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 22:32:32,323 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,400 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,550 INFO L137 Inliner]: procedures = 213, calls = 1959, calls flagged for inlining = 114, calls inlined = 111, statements flattened = 4615 [2022-02-20 22:32:32,550 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 22:32:32,551 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 22:32:32,551 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 22:32:32,551 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 22:32:32,558 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,558 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,583 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,584 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,692 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,708 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,725 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,760 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 22:32:32,762 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 22:32:32,762 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 22:32:32,762 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 22:32:32,763 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (1/1) ... [2022-02-20 22:32:32,767 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:32:32,775 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:32:32,788 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 22:32:32,803 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 22:32:32,831 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2022-02-20 22:32:32,831 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2022-02-20 22:32:32,832 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 22:32:32,832 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 22:32:32,832 INFO L130 BoogieDeclarations]: Found specification of procedure initio_status_msg [2022-02-20 22:32:32,832 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_status_msg [2022-02-20 22:32:32,832 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2022-02-20 22:32:32,833 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2022-02-20 22:32:32,833 INFO L130 BoogieDeclarations]: Found specification of procedure initio_select_atn_stop [2022-02-20 22:32:32,833 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_select_atn_stop [2022-02-20 22:32:32,833 INFO L130 BoogieDeclarations]: Found specification of procedure initio_msgin_accept [2022-02-20 22:32:32,835 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_msgin_accept [2022-02-20 22:32:32,835 INFO L130 BoogieDeclarations]: Found specification of procedure initio_remove_one [2022-02-20 22:32:32,835 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_remove_one [2022-02-20 22:32:32,835 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock [2022-02-20 22:32:32,835 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock [2022-02-20 22:32:32,836 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 22:32:32,836 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 22:32:32,836 INFO L130 BoogieDeclarations]: Found specification of procedure scsi_bufflen [2022-02-20 22:32:32,836 INFO L138 BoogieDeclarations]: Found implementation of procedure scsi_bufflen [2022-02-20 22:32:32,836 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2022-02-20 22:32:32,836 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2022-02-20 22:32:32,836 INFO L130 BoogieDeclarations]: Found specification of procedure int_initio_scsi_rst [2022-02-20 22:32:32,836 INFO L138 BoogieDeclarations]: Found implementation of procedure int_initio_scsi_rst [2022-02-20 22:32:32,836 INFO L130 BoogieDeclarations]: Found specification of procedure initio_abort_srb [2022-02-20 22:32:32,836 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_abort_srb [2022-02-20 22:32:32,836 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2022-02-20 22:32:32,836 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2022-02-20 22:32:32,836 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_scsi_host_template_3 [2022-02-20 22:32:32,836 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_scsi_host_template_3 [2022-02-20 22:32:32,836 INFO L130 BoogieDeclarations]: Found specification of procedure valid_dma_direction [2022-02-20 22:32:32,836 INFO L138 BoogieDeclarations]: Found implementation of procedure valid_dma_direction [2022-02-20 22:32:32,836 INFO L130 BoogieDeclarations]: Found specification of procedure initio_next_state [2022-02-20 22:32:32,837 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_next_state [2022-02-20 22:32:32,837 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2022-02-20 22:32:32,837 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2022-02-20 22:32:32,837 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2022-02-20 22:32:32,837 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2022-02-20 22:32:32,837 INFO L130 BoogieDeclarations]: Found specification of procedure initio_unlink_pend_scb [2022-02-20 22:32:32,837 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_unlink_pend_scb [2022-02-20 22:32:32,837 INFO L130 BoogieDeclarations]: Found specification of procedure spinlock_check [2022-02-20 22:32:32,838 INFO L138 BoogieDeclarations]: Found implementation of procedure spinlock_check [2022-02-20 22:32:32,838 INFO L130 BoogieDeclarations]: Found specification of procedure initio_append_busy_scb [2022-02-20 22:32:32,838 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_append_busy_scb [2022-02-20 22:32:32,838 INFO L130 BoogieDeclarations]: Found specification of procedure dma_unmap_single_attrs [2022-02-20 22:32:32,838 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_unmap_single_attrs [2022-02-20 22:32:32,838 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 22:32:32,838 INFO L130 BoogieDeclarations]: Found specification of procedure initio_msgout_reject [2022-02-20 22:32:32,839 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_msgout_reject [2022-02-20 22:32:32,839 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 22:32:32,839 INFO L130 BoogieDeclarations]: Found specification of procedure initio_se2_rd_all [2022-02-20 22:32:32,839 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_se2_rd_all [2022-02-20 22:32:32,839 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock [2022-02-20 22:32:32,839 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock [2022-02-20 22:32:32,839 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2022-02-20 22:32:32,840 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2022-02-20 22:32:32,840 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 22:32:32,840 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 22:32:32,841 INFO L130 BoogieDeclarations]: Found specification of procedure initio_release_scb [2022-02-20 22:32:32,841 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_release_scb [2022-02-20 22:32:32,841 INFO L130 BoogieDeclarations]: Found specification of procedure tulip_scsi [2022-02-20 22:32:32,842 INFO L138 BoogieDeclarations]: Found implementation of procedure tulip_scsi [2022-02-20 22:32:32,842 INFO L130 BoogieDeclarations]: Found specification of procedure outb [2022-02-20 22:32:32,842 INFO L138 BoogieDeclarations]: Found implementation of procedure outb [2022-02-20 22:32:32,842 INFO L130 BoogieDeclarations]: Found specification of procedure outl [2022-02-20 22:32:32,842 INFO L138 BoogieDeclarations]: Found implementation of procedure outl [2022-02-20 22:32:32,842 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2022-02-20 22:32:32,843 INFO L130 BoogieDeclarations]: Found specification of procedure get_dma_ops [2022-02-20 22:32:32,843 INFO L138 BoogieDeclarations]: Found implementation of procedure get_dma_ops [2022-02-20 22:32:32,843 INFO L130 BoogieDeclarations]: Found specification of procedure initio_msgout_abort_targ [2022-02-20 22:32:32,843 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_msgout_abort_targ [2022-02-20 22:32:32,843 INFO L130 BoogieDeclarations]: Found specification of procedure __raw_spin_lock_init [2022-02-20 22:32:32,844 INFO L138 BoogieDeclarations]: Found implementation of procedure __raw_spin_lock_init [2022-02-20 22:32:32,844 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2022-02-20 22:32:32,844 INFO L130 BoogieDeclarations]: Found specification of procedure initio_se2_instr [2022-02-20 22:32:32,844 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_se2_instr [2022-02-20 22:32:32,844 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 22:32:32,844 INFO L130 BoogieDeclarations]: Found specification of procedure initio_find_first_pend_scb [2022-02-20 22:32:32,844 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_find_first_pend_scb [2022-02-20 22:32:32,844 INFO L130 BoogieDeclarations]: Found specification of procedure __phys_addr [2022-02-20 22:32:32,844 INFO L138 BoogieDeclarations]: Found implementation of procedure __phys_addr [2022-02-20 22:32:32,845 INFO L130 BoogieDeclarations]: Found specification of procedure initio_unlink_busy_scb [2022-02-20 22:32:32,845 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_unlink_busy_scb [2022-02-20 22:32:32,845 INFO L130 BoogieDeclarations]: Found specification of procedure initio_wait_done_disc [2022-02-20 22:32:32,845 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_wait_done_disc [2022-02-20 22:32:32,845 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2022-02-20 22:32:32,845 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2022-02-20 22:32:32,845 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 22:32:32,845 INFO L130 BoogieDeclarations]: Found specification of procedure pci_disable_device [2022-02-20 22:32:32,845 INFO L138 BoogieDeclarations]: Found implementation of procedure pci_disable_device [2022-02-20 22:32:32,846 INFO L130 BoogieDeclarations]: Found specification of procedure initio_stop_bm [2022-02-20 22:32:32,846 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_stop_bm [2022-02-20 22:32:32,846 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2022-02-20 22:32:32,846 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2022-02-20 22:32:32,846 INFO L130 BoogieDeclarations]: Found specification of procedure wait_tulip [2022-02-20 22:32:32,847 INFO L138 BoogieDeclarations]: Found implementation of procedure wait_tulip [2022-02-20 22:32:32,847 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2022-02-20 22:32:32,847 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2022-02-20 22:32:32,847 INFO L130 BoogieDeclarations]: Found specification of procedure initio_pop_busy_scb [2022-02-20 22:32:32,848 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_pop_busy_scb [2022-02-20 22:32:32,848 INFO L130 BoogieDeclarations]: Found specification of procedure initio_bad_seq [2022-02-20 22:32:32,849 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_bad_seq [2022-02-20 22:32:32,849 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_init_zalloc [2022-02-20 22:32:32,849 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_init_zalloc [2022-02-20 22:32:32,849 INFO L130 BoogieDeclarations]: Found specification of procedure int_initio_resel [2022-02-20 22:32:32,849 INFO L138 BoogieDeclarations]: Found implementation of procedure int_initio_resel [2022-02-20 22:32:32,849 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 22:32:32,849 INFO L130 BoogieDeclarations]: Found specification of procedure dma_map_single_attrs [2022-02-20 22:32:32,850 INFO L138 BoogieDeclarations]: Found implementation of procedure dma_map_single_attrs [2022-02-20 22:32:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 22:32:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure initio_msgout_abort_tag [2022-02-20 22:32:32,850 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_msgout_abort_tag [2022-02-20 22:32:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2022-02-20 22:32:32,850 INFO L138 BoogieDeclarations]: Found implementation of procedure __const_udelay [2022-02-20 22:32:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-02-20 22:32:32,850 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2022-02-20 22:32:32,851 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2022-02-20 22:32:32,851 INFO L130 BoogieDeclarations]: Found specification of procedure scsi_host_put [2022-02-20 22:32:32,851 INFO L138 BoogieDeclarations]: Found implementation of procedure scsi_host_put [2022-02-20 22:32:32,852 INFO L130 BoogieDeclarations]: Found specification of procedure initio_reset_scsi [2022-02-20 22:32:32,853 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_reset_scsi [2022-02-20 22:32:32,854 INFO L130 BoogieDeclarations]: Found specification of procedure initio_append_done_scb [2022-02-20 22:32:32,854 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_append_done_scb [2022-02-20 22:32:32,854 INFO L130 BoogieDeclarations]: Found specification of procedure initio_append_pend_scb [2022-02-20 22:32:32,854 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_append_pend_scb [2022-02-20 22:32:32,855 INFO L130 BoogieDeclarations]: Found specification of procedure initio_msgin [2022-02-20 22:32:32,855 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_msgin [2022-02-20 22:32:32,856 INFO L130 BoogieDeclarations]: Found specification of procedure inb [2022-02-20 22:32:32,856 INFO L138 BoogieDeclarations]: Found implementation of procedure inb [2022-02-20 22:32:32,859 INFO L130 BoogieDeclarations]: Found specification of procedure tulip_main [2022-02-20 22:32:32,859 INFO L138 BoogieDeclarations]: Found implementation of procedure tulip_main [2022-02-20 22:32:32,860 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 22:32:32,860 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~$Pointer$~TO~VOID [2022-02-20 22:32:32,860 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~$Pointer$~TO~VOID [2022-02-20 22:32:32,860 INFO L130 BoogieDeclarations]: Found specification of procedure int_initio_busfree [2022-02-20 22:32:32,860 INFO L138 BoogieDeclarations]: Found implementation of procedure int_initio_busfree [2022-02-20 22:32:32,860 INFO L130 BoogieDeclarations]: Found specification of procedure initio_sync_done [2022-02-20 22:32:32,860 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_sync_done [2022-02-20 22:32:32,860 INFO L130 BoogieDeclarations]: Found specification of procedure initio_wait_disc [2022-02-20 22:32:32,860 INFO L138 BoogieDeclarations]: Found implementation of procedure initio_wait_disc [2022-02-20 22:32:32,860 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 22:32:32,861 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 22:32:32,861 INFO L130 BoogieDeclarations]: Found specification of procedure cpu_relax [2022-02-20 22:32:32,861 INFO L138 BoogieDeclarations]: Found implementation of procedure cpu_relax [2022-02-20 22:32:33,369 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 22:32:33,372 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 22:32:33,643 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 22:32:38,898 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 22:32:38,919 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 22:32:38,920 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-02-20 22:32:38,923 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:32:38 BoogieIcfgContainer [2022-02-20 22:32:38,924 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 22:32:38,925 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 22:32:38,925 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 22:32:38,927 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 22:32:38,927 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 10:32:30" (1/3) ... [2022-02-20 22:32:38,928 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@329d8959 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:32:38, skipping insertion in model container [2022-02-20 22:32:38,928 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:32:32" (2/3) ... [2022-02-20 22:32:38,928 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@329d8959 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:32:38, skipping insertion in model container [2022-02-20 22:32:38,928 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:32:38" (3/3) ... [2022-02-20 22:32:38,929 INFO L111 eAbstractionObserver]: Analyzing ICFG linux-4.2-rc1.tar.xz-43_2a-drivers--scsi--initio.ko-entry_point.cil.out.i [2022-02-20 22:32:38,934 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 22:32:38,934 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-02-20 22:32:38,982 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 22:32:38,990 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 22:32:38,990 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-02-20 22:32:39,050 INFO L276 IsEmpty]: Start isEmpty. Operand has 1825 states, 1247 states have (on average 1.347233360064154) internal successors, (1680), 1282 states have internal predecessors, (1680), 513 states have call successors, (513), 64 states have call predecessors, (513), 63 states have return successors, (507), 501 states have call predecessors, (507), 507 states have call successors, (507) [2022-02-20 22:32:39,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2022-02-20 22:32:39,068 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:32:39,069 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:32:39,070 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:32:39,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:32:39,074 INFO L85 PathProgramCache]: Analyzing trace with hash -2029228044, now seen corresponding path program 1 times [2022-02-20 22:32:39,080 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:32:39,081 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55296720] [2022-02-20 22:32:39,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:32:39,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:32:39,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,548 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:32:39,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,595 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:32:39,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,611 INFO L290 TraceCheckUtils]: 0: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,611 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,611 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,612 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:32:39,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,619 INFO L290 TraceCheckUtils]: 0: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,620 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,620 INFO L290 TraceCheckUtils]: 2: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,620 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,621 INFO L290 TraceCheckUtils]: 0: Hoare triple {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {1828#true} is VALID [2022-02-20 22:32:39,622 INFO L272 TraceCheckUtils]: 1: Hoare triple {1828#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {1914#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:32:39,622 INFO L290 TraceCheckUtils]: 2: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,622 INFO L290 TraceCheckUtils]: 3: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,622 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,622 INFO L290 TraceCheckUtils]: 5: Hoare triple {1828#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1828#true} is VALID [2022-02-20 22:32:39,623 INFO L272 TraceCheckUtils]: 6: Hoare triple {1828#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1828#true} is VALID [2022-02-20 22:32:39,623 INFO L290 TraceCheckUtils]: 7: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,623 INFO L290 TraceCheckUtils]: 8: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,623 INFO L290 TraceCheckUtils]: 9: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,623 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,624 INFO L290 TraceCheckUtils]: 11: Hoare triple {1829#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1829#false} is VALID [2022-02-20 22:32:39,624 INFO L290 TraceCheckUtils]: 12: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,625 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1829#false} {1828#true} #4638#return; {1829#false} is VALID [2022-02-20 22:32:39,627 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 18 [2022-02-20 22:32:39,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,648 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:32:39,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,655 INFO L290 TraceCheckUtils]: 0: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,656 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,656 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,656 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:32:39,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,663 INFO L290 TraceCheckUtils]: 0: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,664 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,664 INFO L290 TraceCheckUtils]: 2: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,664 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,664 INFO L290 TraceCheckUtils]: 0: Hoare triple {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {1828#true} is VALID [2022-02-20 22:32:39,665 INFO L272 TraceCheckUtils]: 1: Hoare triple {1828#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {1914#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:32:39,665 INFO L290 TraceCheckUtils]: 2: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,666 INFO L290 TraceCheckUtils]: 3: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,666 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,666 INFO L290 TraceCheckUtils]: 5: Hoare triple {1828#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1828#true} is VALID [2022-02-20 22:32:39,666 INFO L272 TraceCheckUtils]: 6: Hoare triple {1828#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1828#true} is VALID [2022-02-20 22:32:39,666 INFO L290 TraceCheckUtils]: 7: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,667 INFO L290 TraceCheckUtils]: 8: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,667 INFO L290 TraceCheckUtils]: 9: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,667 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,667 INFO L290 TraceCheckUtils]: 11: Hoare triple {1829#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1829#false} is VALID [2022-02-20 22:32:39,668 INFO L290 TraceCheckUtils]: 12: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,668 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1829#false} {1829#false} #4640#return; {1829#false} is VALID [2022-02-20 22:32:39,669 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 34 [2022-02-20 22:32:39,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,682 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:32:39,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,687 INFO L290 TraceCheckUtils]: 0: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,687 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,687 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,687 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:32:39,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,694 INFO L290 TraceCheckUtils]: 0: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,694 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,695 INFO L290 TraceCheckUtils]: 2: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,695 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,695 INFO L290 TraceCheckUtils]: 0: Hoare triple {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {1828#true} is VALID [2022-02-20 22:32:39,697 INFO L272 TraceCheckUtils]: 1: Hoare triple {1828#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {1914#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:32:39,698 INFO L290 TraceCheckUtils]: 2: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,698 INFO L290 TraceCheckUtils]: 3: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,698 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,698 INFO L290 TraceCheckUtils]: 5: Hoare triple {1828#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1828#true} is VALID [2022-02-20 22:32:39,698 INFO L272 TraceCheckUtils]: 6: Hoare triple {1828#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1828#true} is VALID [2022-02-20 22:32:39,698 INFO L290 TraceCheckUtils]: 7: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,699 INFO L290 TraceCheckUtils]: 8: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,699 INFO L290 TraceCheckUtils]: 9: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,700 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,700 INFO L290 TraceCheckUtils]: 11: Hoare triple {1829#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1829#false} is VALID [2022-02-20 22:32:39,701 INFO L290 TraceCheckUtils]: 12: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,701 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1829#false} {1829#false} #4642#return; {1829#false} is VALID [2022-02-20 22:32:39,706 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 50 [2022-02-20 22:32:39,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,714 INFO L290 TraceCheckUtils]: 0: Hoare triple {1929#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {1828#true} is VALID [2022-02-20 22:32:39,715 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {1828#true} is VALID [2022-02-20 22:32:39,715 INFO L290 TraceCheckUtils]: 2: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,715 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1828#true} {1829#false} #4644#return; {1829#false} is VALID [2022-02-20 22:32:39,716 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 56 [2022-02-20 22:32:39,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,730 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:32:39,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,737 INFO L290 TraceCheckUtils]: 0: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,737 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,738 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,738 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:32:39,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,745 INFO L290 TraceCheckUtils]: 0: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,745 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,746 INFO L290 TraceCheckUtils]: 2: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,746 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,746 INFO L290 TraceCheckUtils]: 0: Hoare triple {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {1828#true} is VALID [2022-02-20 22:32:39,747 INFO L272 TraceCheckUtils]: 1: Hoare triple {1828#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {1914#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:32:39,747 INFO L290 TraceCheckUtils]: 2: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,747 INFO L290 TraceCheckUtils]: 3: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,747 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,748 INFO L290 TraceCheckUtils]: 5: Hoare triple {1828#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1828#true} is VALID [2022-02-20 22:32:39,748 INFO L272 TraceCheckUtils]: 6: Hoare triple {1828#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1828#true} is VALID [2022-02-20 22:32:39,749 INFO L290 TraceCheckUtils]: 7: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,749 INFO L290 TraceCheckUtils]: 8: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,750 INFO L290 TraceCheckUtils]: 9: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,750 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,750 INFO L290 TraceCheckUtils]: 11: Hoare triple {1829#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1829#false} is VALID [2022-02-20 22:32:39,750 INFO L290 TraceCheckUtils]: 12: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,750 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1829#false} {1829#false} #4646#return; {1829#false} is VALID [2022-02-20 22:32:39,757 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 73 [2022-02-20 22:32:39,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,765 INFO L290 TraceCheckUtils]: 0: Hoare triple {1937#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} #t~loopctr1148 := 0; {1828#true} is VALID [2022-02-20 22:32:39,765 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume !(#t~loopctr1148 % 18446744073709551616 < #amount % 18446744073709551616); {1828#true} is VALID [2022-02-20 22:32:39,765 INFO L290 TraceCheckUtils]: 2: Hoare triple {1828#true} assume #res.base == #ptr.base && #res.offset == #ptr.offset; {1828#true} is VALID [2022-02-20 22:32:39,765 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1828#true} {1829#false} #4648#return; {1829#false} is VALID [2022-02-20 22:32:39,766 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 99 [2022-02-20 22:32:39,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,773 INFO L290 TraceCheckUtils]: 0: Hoare triple {1929#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {1828#true} is VALID [2022-02-20 22:32:39,773 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {1828#true} is VALID [2022-02-20 22:32:39,773 INFO L290 TraceCheckUtils]: 2: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,773 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1828#true} {1829#false} #4708#return; {1829#false} is VALID [2022-02-20 22:32:39,773 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 110 [2022-02-20 22:32:39,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,781 INFO L290 TraceCheckUtils]: 0: Hoare triple {1937#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} #t~loopctr1148 := 0; {1828#true} is VALID [2022-02-20 22:32:39,781 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume !(#t~loopctr1148 % 18446744073709551616 < #amount % 18446744073709551616); {1828#true} is VALID [2022-02-20 22:32:39,781 INFO L290 TraceCheckUtils]: 2: Hoare triple {1828#true} assume #res.base == #ptr.base && #res.offset == #ptr.offset; {1828#true} is VALID [2022-02-20 22:32:39,781 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1828#true} {1829#false} #4712#return; {1829#false} is VALID [2022-02-20 22:32:39,782 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 116 [2022-02-20 22:32:39,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:32:39,789 INFO L290 TraceCheckUtils]: 0: Hoare triple {1929#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {1828#true} is VALID [2022-02-20 22:32:39,789 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {1828#true} is VALID [2022-02-20 22:32:39,789 INFO L290 TraceCheckUtils]: 2: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,789 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1828#true} {1829#false} #4714#return; {1829#false} is VALID [2022-02-20 22:32:39,791 INFO L290 TraceCheckUtils]: 0: Hoare triple {1828#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(74, 2);call #Ultimate.allocInit(57, 3);call #Ultimate.allocInit(28, 4);call #Ultimate.allocInit(21, 5);call #Ultimate.allocInit(36, 6);call #Ultimate.allocInit(200, 7);call #Ultimate.allocInit(17, 8);call #Ultimate.allocInit(39, 9);call #Ultimate.allocInit(9, 10);call #Ultimate.allocInit(38, 11);call #Ultimate.allocInit(45, 12);call #Ultimate.allocInit(5, 13);call write~init~int(105, 13, 0, 1);call write~init~int(57, 13, 1, 1);call write~init~int(49, 13, 2, 1);call write~init~int(117, 13, 3, 1);call write~init~int(0, 13, 4, 1);call #Ultimate.allocInit(39, 14);call #Ultimate.allocInit(37, 15);call #Ultimate.allocInit(29, 16);call #Ultimate.allocInit(28, 17);call #Ultimate.allocInit(5, 18);call write~init~int(105, 18, 0, 1);call write~init~int(57, 18, 1, 1);call write~init~int(49, 18, 2, 1);call write~init~int(117, 18, 3, 1);call write~init~int(0, 18, 4, 1);call #Ultimate.allocInit(35, 19);call #Ultimate.allocInit(7, 20);call write~init~int(105, 20, 0, 1);call write~init~int(110, 20, 1, 1);call write~init~int(105, 20, 2, 1);call write~init~int(116, 20, 3, 1);call write~init~int(105, 20, 4, 1);call write~init~int(111, 20, 5, 1);call write~init~int(0, 20, 6, 1);call #Ultimate.allocInit(7, 21);call write~init~int(105, 21, 0, 1);call write~init~int(110, 21, 1, 1);call write~init~int(105, 21, 2, 1);call write~init~int(116, 21, 3, 1);call write~init~int(105, 21, 4, 1);call write~init~int(111, 21, 5, 1);call write~init~int(0, 21, 6, 1);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~pci_counter~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~initio_template_group0~0.base, ~initio_template_group0~0.offset := 0, 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~initio_pci_driver_group1~0.base, ~initio_pci_driver_group1~0.offset := 0, 0;~initio_tag_enable~0 := 1;~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[5 := 0];~#i91unvram~0.base, ~#i91unvram~0.offset := 22, 0;call #Ultimate.allocInit(64, 22);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#i91unvram~0.base);~i91unvramp~0.base, ~i91unvramp~0.offset := 0, 0;~#i91udftNvRam~0.base, ~#i91udftNvRam~0.offset := 23, 0;call #Ultimate.allocInit(64, 23);call write~init~int(37, ~#i91udftNvRam~0.base, ~#i91udftNvRam~0.offset, 1);call write~init~int(201, ~#i91udftNvRam~0.base, 1 + ~#i91udftNvRam~0.offset, 1);call write~init~int(64, ~#i91udftNvRam~0.base, 2 + ~#i91udftNvRam~0.offset, 1);call write~init~int(1, ~#i91udftNvRam~0.base, 3 + ~#i91udftNvRam~0.offset, 1);call write~init~int(149, ~#i91udftNvRam~0.base, 4 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 5 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 6 + ~#i91udftNvRam~0.offset, 1);call write~init~int(1, ~#i91udftNvRam~0.base, 7 + ~#i91udftNvRam~0.offset, 1);call write~init~int(1, ~#i91udftNvRam~0.base, 8 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 9 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 10 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 11 + ~#i91udftNvRam~0.offset, 1);call write~init~int(7, ~#i91udftNvRam~0.base, 12 + ~#i91udftNvRam~0.offset, 1);call write~init~int(19, ~#i91udftNvRam~0.base, 13 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 14 + ~#i91udftNvRam~0.offset, 1);call write~init~int(16, ~#i91udftNvRam~0.base, 15 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 16 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 17 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 18 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 19 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 20 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 21 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 22 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 23 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 24 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 25 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 26 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 27 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 28 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 29 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 30 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 31 + ~#i91udftNvRam~0.offset, 1);call write~init~int(7, ~#i91udftNvRam~0.base, 32 + ~#i91udftNvRam~0.offset, 1);call write~init~int(19, ~#i91udftNvRam~0.base, 33 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 34 + ~#i91udftNvRam~0.offset, 1);call write~init~int(16, ~#i91udftNvRam~0.base, 35 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 36 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 37 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 38 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 39 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 40 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 41 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 42 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 43 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 44 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 45 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 46 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 47 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 48 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 49 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 50 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 51 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 52 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 53 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 54 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 55 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 56 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 57 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 58 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 59 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 60 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 61 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 62 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 63 + ~#i91udftNvRam~0.offset, 1);~#initio_rate_tbl~0.base, ~#initio_rate_tbl~0.offset := 24, 0;call #Ultimate.allocInit(8, 24);call write~init~int(12, ~#initio_rate_tbl~0.base, ~#initio_rate_tbl~0.offset, 1);call write~init~int(18, ~#initio_rate_tbl~0.base, 1 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(25, ~#initio_rate_tbl~0.base, 2 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(31, ~#initio_rate_tbl~0.base, 3 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(37, ~#initio_rate_tbl~0.base, 4 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(43, ~#initio_rate_tbl~0.base, 5 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(50, ~#initio_rate_tbl~0.base, 6 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(62, ~#initio_rate_tbl~0.base, 7 + ~#initio_rate_tbl~0.offset, 1);~#initio_template~0.base, ~#initio_template~0.offset := 25, 0;call #Ultimate.allocInit(329, 25);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, ~#initio_template~0.offset, 8);call write~init~$Pointer$(9, 0, ~#initio_template~0.base, 8 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 16 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 24 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 32 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 40 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 48 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(#funAddr~i91u_queuecommand.base, #funAddr~i91u_queuecommand.offset, ~#initio_template~0.base, 56 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 64 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 72 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 80 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(#funAddr~i91u_bus_reset.base, #funAddr~i91u_bus_reset.offset, ~#initio_template~0.base, 88 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 96 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 104 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 112 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 120 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 128 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 136 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 144 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 152 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 160 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(#funAddr~i91u_biosparam.base, #funAddr~i91u_biosparam.offset, ~#initio_template~0.base, 168 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 176 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 184 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 192 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 200 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 208 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(10, 0, ~#initio_template~0.base, 216 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 224 + ~#initio_template~0.offset, 8);call write~init~int(32, ~#initio_template~0.base, 232 + ~#initio_template~0.offset, 4);call write~init~int(1, ~#initio_template~0.base, 236 + ~#initio_template~0.offset, 4);call write~init~int(128, ~#initio_template~0.base, 240 + ~#initio_template~0.offset, 2);call write~init~int(0, ~#initio_template~0.base, 242 + ~#initio_template~0.offset, 2);call write~init~int(0, ~#initio_template~0.base, 244 + ~#initio_template~0.offset, 4);call write~init~int(0, ~#initio_template~0.base, 248 + ~#initio_template~0.offset, 8);call write~init~int(0, ~#initio_template~0.base, 256 + ~#initio_template~0.offset, 2);call write~init~int(0, ~#initio_template~0.base, 258 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 259 + ~#initio_template~0.offset, 4);call write~init~int(0, ~#initio_template~0.base, 263 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 264 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 265 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 266 + ~#initio_template~0.offset, 1);call write~init~int(1, ~#initio_template~0.base, 267 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 268 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 269 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 270 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 271 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 272 + ~#initio_template~0.offset, 4);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 276 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 284 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 292 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 300 + ~#initio_template~0.offset, 8);call write~init~int(0, ~#initio_template~0.base, 308 + ~#initio_template~0.offset, 8);call write~init~int(0, ~#initio_template~0.base, 316 + ~#initio_template~0.offset, 4);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 320 + ~#initio_template~0.offset, 8);call write~init~int(0, ~#initio_template~0.base, 328 + ~#initio_template~0.offset, 1);~#initio_pci_tbl~0.base, ~#initio_pci_tbl~0.offset := 26, 0;call #Ultimate.allocInit(192, 26);call write~init~int(4353, ~#initio_pci_tbl~0.base, ~#initio_pci_tbl~0.offset, 4);call write~init~int(38144, ~#initio_pci_tbl~0.base, 4 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 8 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 12 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 16 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 20 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 24 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(4353, ~#initio_pci_tbl~0.base, 32 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(37888, ~#initio_pci_tbl~0.base, 36 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 40 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 44 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 48 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 52 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 56 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(4353, ~#initio_pci_tbl~0.base, 64 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(37889, ~#initio_pci_tbl~0.base, 68 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 72 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 76 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 80 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 84 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 88 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(4353, ~#initio_pci_tbl~0.base, 96 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(2, ~#initio_pci_tbl~0.base, 100 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 104 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 108 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 112 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 116 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 120 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(4938, ~#initio_pci_tbl~0.base, 128 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(2, ~#initio_pci_tbl~0.base, 132 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 136 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 140 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 144 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 148 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 152 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(0, ~#initio_pci_tbl~0.base, 160 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 164 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 168 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 172 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 176 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 180 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 184 + ~#initio_pci_tbl~0.offset, 8);~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[5 := 0];~#initio_pci_driver~0.base, ~#initio_pci_driver~0.offset := 27, 0;call #Ultimate.allocInit(305, 27);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 8 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(20, 0, ~#initio_pci_driver~0.base, 16 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(~#initio_pci_tbl~0.base, ~#initio_pci_tbl~0.offset, ~#initio_pci_driver~0.base, 24 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~initio_probe_one.base, #funAddr~initio_probe_one.offset, ~#initio_pci_driver~0.base, 32 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~initio_remove_one.base, #funAddr~initio_remove_one.offset, ~#initio_pci_driver~0.base, 40 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 48 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 56 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 64 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 72 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 80 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 88 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 96 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 104 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 112 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 120 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 128 + ~#initio_pci_driver~0.offset, 8);call write~init~int(0, ~#initio_pci_driver~0.base, 136 + ~#initio_pci_driver~0.offset, 1);call write~init~int(0, ~#initio_pci_driver~0.base, 137 + ~#initio_pci_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 141 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 149 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 157 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 165 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 173 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 181 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 189 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 197 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 205 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 213 + ~#initio_pci_driver~0.offset, 8);call write~init~int(0, ~#initio_pci_driver~0.base, 221 + ~#initio_pci_driver~0.offset, 4);call write~init~int(0, ~#initio_pci_driver~0.base, 225 + ~#initio_pci_driver~0.offset, 4);call write~init~int(0, ~#initio_pci_driver~0.base, 229 + ~#initio_pci_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 233 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 241 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 249 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 257 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 265 + ~#initio_pci_driver~0.offset, 8);call write~init~int(0, ~#initio_pci_driver~0.base, 273 + ~#initio_pci_driver~0.offset, 4);call write~init~int(0, ~#initio_pci_driver~0.base, 277 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 289 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 297 + ~#initio_pci_driver~0.offset, 8);~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_spin~0 := 0; {1828#true} is VALID [2022-02-20 22:32:39,792 INFO L290 TraceCheckUtils]: 1: Hoare triple {1828#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret1102#1.base, main_#t~ret1102#1.offset, main_#t~ret1103#1.base, main_#t~ret1103#1.offset, main_#t~ret1104#1.base, main_#t~ret1104#1.offset, main_#t~ret1105#1.base, main_#t~ret1105#1.offset, main_#t~ret1106#1.base, main_#t~ret1106#1.offset, main_#t~ret1107#1.base, main_#t~ret1107#1.offset, main_#t~nondet1108#1, main_#t~switch1109#1, main_#t~nondet1110#1, main_#t~switch1111#1, main_#t~ret1112#1, main_#t~nondet1113#1, main_#t~switch1114#1, main_#t~mem1115#1, main_#t~ret1116#1, main_#t~ret1117#1, main_#t~ret1118#1, main_#t~nondet1119#1, main_#t~switch1120#1, main_#t~ret1121#1, main_#t~ret1122#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~65#1.base, main_~tmp~65#1.offset, main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset, main_~tmp___0~35#1.base, main_~tmp___0~35#1.offset, main_~#ldvarg3~0#1.base, main_~#ldvarg3~0#1.offset, main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset, main_~tmp___1~22#1.base, main_~tmp___1~22#1.offset, main_~ldvarg2~0#1.base, main_~ldvarg2~0#1.offset, main_~ldvarg5~0#1.base, main_~ldvarg5~0#1.offset, main_~tmp___3~12#1.base, main_~tmp___3~12#1.offset, main_~tmp___4~9#1, main_~tmp___5~7#1, main_~tmp___6~5#1, main_~tmp___7~4#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~65#1.base, main_~tmp~65#1.offset;havoc main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset;havoc main_~tmp___0~35#1.base, main_~tmp___0~35#1.offset;call main_~#ldvarg3~0#1.base, main_~#ldvarg3~0#1.offset := #Ultimate.allocOnStack(8);havoc main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset;havoc main_~tmp___1~22#1.base, main_~tmp___1~22#1.offset;havoc main_~ldvarg2~0#1.base, main_~ldvarg2~0#1.offset;havoc main_~ldvarg5~0#1.base, main_~ldvarg5~0#1.offset;havoc main_~tmp___3~12#1.base, main_~tmp___3~12#1.offset;havoc main_~tmp___4~9#1;havoc main_~tmp___5~7#1;havoc main_~tmp___6~5#1;havoc main_~tmp___7~4#1; {1828#true} is VALID [2022-02-20 22:32:39,798 INFO L272 TraceCheckUtils]: 2: Hoare triple {1828#true} call main_#t~ret1102#1.base, main_#t~ret1102#1.offset := ldv_init_zalloc(4); {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:32:39,798 INFO L290 TraceCheckUtils]: 3: Hoare triple {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {1828#true} is VALID [2022-02-20 22:32:39,799 INFO L272 TraceCheckUtils]: 4: Hoare triple {1828#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {1914#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:32:39,799 INFO L290 TraceCheckUtils]: 5: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,799 INFO L290 TraceCheckUtils]: 6: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,800 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,800 INFO L290 TraceCheckUtils]: 8: Hoare triple {1828#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1828#true} is VALID [2022-02-20 22:32:39,800 INFO L272 TraceCheckUtils]: 9: Hoare triple {1828#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1828#true} is VALID [2022-02-20 22:32:39,800 INFO L290 TraceCheckUtils]: 10: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,800 INFO L290 TraceCheckUtils]: 11: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,801 INFO L290 TraceCheckUtils]: 12: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,801 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,801 INFO L290 TraceCheckUtils]: 14: Hoare triple {1829#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1829#false} is VALID [2022-02-20 22:32:39,801 INFO L290 TraceCheckUtils]: 15: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,801 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {1829#false} {1828#true} #4638#return; {1829#false} is VALID [2022-02-20 22:32:39,801 INFO L290 TraceCheckUtils]: 17: Hoare triple {1829#false} main_~tmp~65#1.base, main_~tmp~65#1.offset := main_#t~ret1102#1.base, main_#t~ret1102#1.offset;havoc main_#t~ret1102#1.base, main_#t~ret1102#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~65#1.base, main_~tmp~65#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,802 INFO L272 TraceCheckUtils]: 18: Hoare triple {1829#false} call main_#t~ret1103#1.base, main_#t~ret1103#1.offset := ldv_init_zalloc(480); {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:32:39,802 INFO L290 TraceCheckUtils]: 19: Hoare triple {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {1828#true} is VALID [2022-02-20 22:32:39,803 INFO L272 TraceCheckUtils]: 20: Hoare triple {1828#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {1914#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:32:39,803 INFO L290 TraceCheckUtils]: 21: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,803 INFO L290 TraceCheckUtils]: 22: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,803 INFO L284 TraceCheckUtils]: 23: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,803 INFO L290 TraceCheckUtils]: 24: Hoare triple {1828#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1828#true} is VALID [2022-02-20 22:32:39,804 INFO L272 TraceCheckUtils]: 25: Hoare triple {1828#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1828#true} is VALID [2022-02-20 22:32:39,804 INFO L290 TraceCheckUtils]: 26: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,804 INFO L290 TraceCheckUtils]: 27: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,804 INFO L290 TraceCheckUtils]: 28: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,804 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,805 INFO L290 TraceCheckUtils]: 30: Hoare triple {1829#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1829#false} is VALID [2022-02-20 22:32:39,805 INFO L290 TraceCheckUtils]: 31: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,805 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {1829#false} {1829#false} #4640#return; {1829#false} is VALID [2022-02-20 22:32:39,805 INFO L290 TraceCheckUtils]: 33: Hoare triple {1829#false} main_~tmp___0~35#1.base, main_~tmp___0~35#1.offset := main_#t~ret1103#1.base, main_#t~ret1103#1.offset;havoc main_#t~ret1103#1.base, main_#t~ret1103#1.offset;main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset := main_~tmp___0~35#1.base, main_~tmp___0~35#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,805 INFO L272 TraceCheckUtils]: 34: Hoare triple {1829#false} call main_#t~ret1104#1.base, main_#t~ret1104#1.offset := ldv_init_zalloc(3816); {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:32:39,805 INFO L290 TraceCheckUtils]: 35: Hoare triple {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {1828#true} is VALID [2022-02-20 22:32:39,806 INFO L272 TraceCheckUtils]: 36: Hoare triple {1828#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {1914#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:32:39,806 INFO L290 TraceCheckUtils]: 37: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,807 INFO L290 TraceCheckUtils]: 38: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,807 INFO L284 TraceCheckUtils]: 39: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,808 INFO L290 TraceCheckUtils]: 40: Hoare triple {1828#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1828#true} is VALID [2022-02-20 22:32:39,808 INFO L272 TraceCheckUtils]: 41: Hoare triple {1828#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1828#true} is VALID [2022-02-20 22:32:39,809 INFO L290 TraceCheckUtils]: 42: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,809 INFO L290 TraceCheckUtils]: 43: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,809 INFO L290 TraceCheckUtils]: 44: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,809 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,809 INFO L290 TraceCheckUtils]: 46: Hoare triple {1829#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1829#false} is VALID [2022-02-20 22:32:39,810 INFO L290 TraceCheckUtils]: 47: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,810 INFO L284 TraceCheckUtils]: 48: Hoare quadruple {1829#false} {1829#false} #4642#return; {1829#false} is VALID [2022-02-20 22:32:39,810 INFO L290 TraceCheckUtils]: 49: Hoare triple {1829#false} main_~tmp___1~22#1.base, main_~tmp___1~22#1.offset := main_#t~ret1104#1.base, main_#t~ret1104#1.offset;havoc main_#t~ret1104#1.base, main_#t~ret1104#1.offset;main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset := main_~tmp___1~22#1.base, main_~tmp___1~22#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,810 INFO L272 TraceCheckUtils]: 50: Hoare triple {1829#false} call main_#t~ret1105#1.base, main_#t~ret1105#1.offset := ldv_malloc(3314); {1929#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:32:39,810 INFO L290 TraceCheckUtils]: 51: Hoare triple {1929#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {1828#true} is VALID [2022-02-20 22:32:39,811 INFO L290 TraceCheckUtils]: 52: Hoare triple {1828#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {1828#true} is VALID [2022-02-20 22:32:39,811 INFO L290 TraceCheckUtils]: 53: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,811 INFO L284 TraceCheckUtils]: 54: Hoare quadruple {1828#true} {1829#false} #4644#return; {1829#false} is VALID [2022-02-20 22:32:39,811 INFO L290 TraceCheckUtils]: 55: Hoare triple {1829#false} main_~ldvarg2~0#1.base, main_~ldvarg2~0#1.offset := main_#t~ret1105#1.base, main_#t~ret1105#1.offset;havoc main_#t~ret1105#1.base, main_#t~ret1105#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,811 INFO L272 TraceCheckUtils]: 56: Hoare triple {1829#false} call main_#t~ret1106#1.base, main_#t~ret1106#1.offset := ldv_init_zalloc(32); {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:32:39,811 INFO L290 TraceCheckUtils]: 57: Hoare triple {1906#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {1828#true} is VALID [2022-02-20 22:32:39,812 INFO L272 TraceCheckUtils]: 58: Hoare triple {1828#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {1914#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:32:39,814 INFO L290 TraceCheckUtils]: 59: Hoare triple {1914#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {1828#true} is VALID [2022-02-20 22:32:39,814 INFO L290 TraceCheckUtils]: 60: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,814 INFO L284 TraceCheckUtils]: 61: Hoare quadruple {1828#true} {1828#true} #4548#return; {1828#true} is VALID [2022-02-20 22:32:39,814 INFO L290 TraceCheckUtils]: 62: Hoare triple {1828#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {1828#true} is VALID [2022-02-20 22:32:39,814 INFO L272 TraceCheckUtils]: 63: Hoare triple {1828#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {1828#true} is VALID [2022-02-20 22:32:39,814 INFO L290 TraceCheckUtils]: 64: Hoare triple {1828#true} ~cond := #in~cond; {1828#true} is VALID [2022-02-20 22:32:39,816 INFO L290 TraceCheckUtils]: 65: Hoare triple {1828#true} assume 0 == ~cond;assume false; {1829#false} is VALID [2022-02-20 22:32:39,816 INFO L290 TraceCheckUtils]: 66: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,816 INFO L284 TraceCheckUtils]: 67: Hoare quadruple {1829#false} {1828#true} #4550#return; {1829#false} is VALID [2022-02-20 22:32:39,817 INFO L290 TraceCheckUtils]: 68: Hoare triple {1829#false} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {1829#false} is VALID [2022-02-20 22:32:39,817 INFO L290 TraceCheckUtils]: 69: Hoare triple {1829#false} assume true; {1829#false} is VALID [2022-02-20 22:32:39,818 INFO L284 TraceCheckUtils]: 70: Hoare quadruple {1829#false} {1829#false} #4646#return; {1829#false} is VALID [2022-02-20 22:32:39,818 INFO L290 TraceCheckUtils]: 71: Hoare triple {1829#false} main_~tmp___3~12#1.base, main_~tmp___3~12#1.offset := main_#t~ret1106#1.base, main_#t~ret1106#1.offset;havoc main_#t~ret1106#1.base, main_#t~ret1106#1.offset;main_~ldvarg5~0#1.base, main_~ldvarg5~0#1.offset := main_~tmp___3~12#1.base, main_~tmp___3~12#1.offset;assume { :begin_inline_ldv_initialize } true; {1829#false} is VALID [2022-02-20 22:32:39,818 INFO L290 TraceCheckUtils]: 72: Hoare triple {1829#false} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_memset } true;ldv_memset_#in~s#1.base, ldv_memset_#in~s#1.offset, ldv_memset_#in~c#1, ldv_memset_#in~n#1 := main_~#ldvarg3~0#1.base, main_~#ldvarg3~0#1.offset, 0, 8;havoc ldv_memset_#res#1.base, ldv_memset_#res#1.offset;havoc ldv_memset_#t~memset~res13#1.base, ldv_memset_#t~memset~res13#1.offset, ldv_memset_~s#1.base, ldv_memset_~s#1.offset, ldv_memset_~c#1, ldv_memset_~n#1, ldv_memset_~tmp~3#1.base, ldv_memset_~tmp~3#1.offset;ldv_memset_~s#1.base, ldv_memset_~s#1.offset := ldv_memset_#in~s#1.base, ldv_memset_#in~s#1.offset;ldv_memset_~c#1 := ldv_memset_#in~c#1;ldv_memset_~n#1 := ldv_memset_#in~n#1;havoc ldv_memset_~tmp~3#1.base, ldv_memset_~tmp~3#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,818 INFO L272 TraceCheckUtils]: 73: Hoare triple {1829#false} call ldv_memset_#t~memset~res13#1.base, ldv_memset_#t~memset~res13#1.offset := #Ultimate.C_memset(ldv_memset_~s#1.base, ldv_memset_~s#1.offset, ldv_memset_~c#1, ldv_memset_~n#1); {1937#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:32:39,819 INFO L290 TraceCheckUtils]: 74: Hoare triple {1937#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} #t~loopctr1148 := 0; {1828#true} is VALID [2022-02-20 22:32:39,820 INFO L290 TraceCheckUtils]: 75: Hoare triple {1828#true} assume !(#t~loopctr1148 % 18446744073709551616 < #amount % 18446744073709551616); {1828#true} is VALID [2022-02-20 22:32:39,820 INFO L290 TraceCheckUtils]: 76: Hoare triple {1828#true} assume #res.base == #ptr.base && #res.offset == #ptr.offset; {1828#true} is VALID [2022-02-20 22:32:39,821 INFO L284 TraceCheckUtils]: 77: Hoare quadruple {1828#true} {1829#false} #4648#return; {1829#false} is VALID [2022-02-20 22:32:39,821 INFO L290 TraceCheckUtils]: 78: Hoare triple {1829#false} ldv_memset_~tmp~3#1.base, ldv_memset_~tmp~3#1.offset := ldv_memset_~s#1.base, ldv_memset_~s#1.offset;havoc ldv_memset_#t~memset~res13#1.base, ldv_memset_#t~memset~res13#1.offset;ldv_memset_#res#1.base, ldv_memset_#res#1.offset := ldv_memset_~tmp~3#1.base, ldv_memset_~tmp~3#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,821 INFO L290 TraceCheckUtils]: 79: Hoare triple {1829#false} main_#t~ret1107#1.base, main_#t~ret1107#1.offset := ldv_memset_#res#1.base, ldv_memset_#res#1.offset;assume { :end_inline_ldv_memset } true;havoc main_#t~ret1107#1.base, main_#t~ret1107#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {1829#false} is VALID [2022-02-20 22:32:39,822 INFO L290 TraceCheckUtils]: 80: Hoare triple {1829#false} assume -2147483648 <= main_#t~nondet1108#1 && main_#t~nondet1108#1 <= 2147483647;main_~tmp___4~9#1 := main_#t~nondet1108#1;havoc main_#t~nondet1108#1;main_#t~switch1109#1 := 0 == main_~tmp___4~9#1; {1829#false} is VALID [2022-02-20 22:32:39,822 INFO L290 TraceCheckUtils]: 81: Hoare triple {1829#false} assume !main_#t~switch1109#1;main_#t~switch1109#1 := main_#t~switch1109#1 || 1 == main_~tmp___4~9#1; {1829#false} is VALID [2022-02-20 22:32:39,822 INFO L290 TraceCheckUtils]: 82: Hoare triple {1829#false} assume !main_#t~switch1109#1;main_#t~switch1109#1 := main_#t~switch1109#1 || 2 == main_~tmp___4~9#1; {1829#false} is VALID [2022-02-20 22:32:39,822 INFO L290 TraceCheckUtils]: 83: Hoare triple {1829#false} assume !main_#t~switch1109#1;main_#t~switch1109#1 := main_#t~switch1109#1 || 3 == main_~tmp___4~9#1; {1829#false} is VALID [2022-02-20 22:32:39,822 INFO L290 TraceCheckUtils]: 84: Hoare triple {1829#false} assume main_#t~switch1109#1; {1829#false} is VALID [2022-02-20 22:32:39,822 INFO L290 TraceCheckUtils]: 85: Hoare triple {1829#false} assume 0 != ~ldv_state_variable_2~0;assume -2147483648 <= main_#t~nondet1119#1 && main_#t~nondet1119#1 <= 2147483647;main_~tmp___7~4#1 := main_#t~nondet1119#1;havoc main_#t~nondet1119#1;main_#t~switch1120#1 := 0 == main_~tmp___7~4#1; {1829#false} is VALID [2022-02-20 22:32:39,823 INFO L290 TraceCheckUtils]: 86: Hoare triple {1829#false} assume main_#t~switch1120#1; {1829#false} is VALID [2022-02-20 22:32:39,823 INFO L290 TraceCheckUtils]: 87: Hoare triple {1829#false} assume 1 == ~ldv_state_variable_2~0;assume { :begin_inline_initio_probe_one } true;initio_probe_one_#in~pdev#1.base, initio_probe_one_#in~pdev#1.offset, initio_probe_one_#in~id#1.base, initio_probe_one_#in~id#1.offset := ~initio_pci_driver_group1~0.base, ~initio_pci_driver_group1~0.offset, main_~ldvarg5~0#1.base, main_~ldvarg5~0#1.offset;havoc initio_probe_one_#res#1;havoc initio_probe_one_#t~ret1050#1, initio_probe_one_#t~ret1051#1, initio_probe_one_#t~mem1053#1, initio_probe_one_#t~mem1055#1, initio_probe_one_#t~mem1056#1, initio_probe_one_#t~ret1057#1, initio_probe_one_#t~nondet1058#1, initio_probe_one_#t~ret1059#1.base, initio_probe_one_#t~ret1059#1.offset, initio_probe_one_#t~nondet1060#1, initio_probe_one_#t~memset~res1061#1.base, initio_probe_one_#t~memset~res1061#1.offset, initio_probe_one_#t~mem1062#1, initio_probe_one_#t~mem1063#1, initio_probe_one_#t~ret1064#1.base, initio_probe_one_#t~ret1064#1.offset, initio_probe_one_#t~nondet1065#1, initio_probe_one_#t~mem1066#1, initio_probe_one_#t~ret1067#1.base, initio_probe_one_#t~ret1067#1.offset, initio_probe_one_#t~nondet1068#1, initio_probe_one_#t~ret1069#1.base, initio_probe_one_#t~ret1069#1.offset, initio_probe_one_#t~ret1070#1.base, initio_probe_one_#t~ret1070#1.offset, initio_probe_one_#t~ret1071#1.base, initio_probe_one_#t~ret1071#1.offset, initio_probe_one_#t~mem1072#1, initio_probe_one_#t~mem1073#1, initio_probe_one_#t~mem1074#1, initio_probe_one_#t~mem1075#1, initio_probe_one_#t~mem1076#1, initio_probe_one_#t~mem1077#1, initio_probe_one_#t~mem1078#1, initio_probe_one_#t~ret1079#1, initio_probe_one_#t~nondet1080#1, initio_probe_one_#t~mem1081#1, initio_probe_one_#t~ret1082#1, initio_probe_one_#t~mem1083#1, initio_probe_one_#t~mem1084#1.base, initio_probe_one_#t~mem1084#1.offset, initio_probe_one_#t~mem1085#1, initio_probe_one_#t~nondet1054#1, initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset, initio_probe_one_~id#1.base, initio_probe_one_~id#1.offset, initio_probe_one_~shost~0#1.base, initio_probe_one_~shost~0#1.offset, initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset, initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, initio_probe_one_~bios_seg~0#1, initio_probe_one_~scb~21#1.base, initio_probe_one_~scb~21#1.offset, initio_probe_one_~tmp~59#1.base, initio_probe_one_~tmp~59#1.offset, initio_probe_one_~prev~5#1.base, initio_probe_one_~prev~5#1.offset, initio_probe_one_~num_scb~0#1, initio_probe_one_~i~16#1, initio_probe_one_~error~0#1, initio_probe_one_~tmp___0~33#1, initio_probe_one_~tmp___1~21#1.base, initio_probe_one_~tmp___1~21#1.offset, initio_probe_one_~tmp___2~15#1.base, initio_probe_one_~tmp___2~15#1.offset, initio_probe_one_~#__key~0#1.base, initio_probe_one_~#__key~0#1.offset, initio_probe_one_~#__key___0~0#1.base, initio_probe_one_~#__key___0~0#1.offset, initio_probe_one_~tmp___3~11#1.base, initio_probe_one_~tmp___3~11#1.offset;initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset := initio_probe_one_#in~pdev#1.base, initio_probe_one_#in~pdev#1.offset;initio_probe_one_~id#1.base, initio_probe_one_~id#1.offset := initio_probe_one_#in~id#1.base, initio_probe_one_#in~id#1.offset;havoc initio_probe_one_~shost~0#1.base, initio_probe_one_~shost~0#1.offset;havoc initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset;call initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset := #Ultimate.allocOnStack(4);havoc initio_probe_one_~bios_seg~0#1;havoc initio_probe_one_~scb~21#1.base, initio_probe_one_~scb~21#1.offset;havoc initio_probe_one_~tmp~59#1.base, initio_probe_one_~tmp~59#1.offset;havoc initio_probe_one_~prev~5#1.base, initio_probe_one_~prev~5#1.offset;havoc initio_probe_one_~num_scb~0#1;havoc initio_probe_one_~i~16#1;havoc initio_probe_one_~error~0#1;havoc initio_probe_one_~tmp___0~33#1;havoc initio_probe_one_~tmp___1~21#1.base, initio_probe_one_~tmp___1~21#1.offset;havoc initio_probe_one_~tmp___2~15#1.base, initio_probe_one_~tmp___2~15#1.offset;call initio_probe_one_~#__key~0#1.base, initio_probe_one_~#__key~0#1.offset := #Ultimate.allocOnStack(8);call initio_probe_one_~#__key___0~0#1.base, initio_probe_one_~#__key___0~0#1.offset := #Ultimate.allocOnStack(8);havoc initio_probe_one_~tmp___3~11#1.base, initio_probe_one_~tmp___3~11#1.offset;initio_probe_one_~prev~5#1.base, initio_probe_one_~prev~5#1.offset := 0, 0;assume { :begin_inline_pci_enable_device } true;pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset := initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset;havoc pci_enable_device_#res#1;havoc pci_enable_device_#t~nondet1139#1, pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset;pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset := pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset;assume -2147483648 <= pci_enable_device_#t~nondet1139#1 && pci_enable_device_#t~nondet1139#1 <= 2147483647;pci_enable_device_#res#1 := pci_enable_device_#t~nondet1139#1;havoc pci_enable_device_#t~nondet1139#1; {1829#false} is VALID [2022-02-20 22:32:39,823 INFO L290 TraceCheckUtils]: 88: Hoare triple {1829#false} initio_probe_one_#t~ret1050#1 := pci_enable_device_#res#1;assume { :end_inline_pci_enable_device } true;assume -2147483648 <= initio_probe_one_#t~ret1050#1 && initio_probe_one_#t~ret1050#1 <= 2147483647;initio_probe_one_~error~0#1 := initio_probe_one_#t~ret1050#1;havoc initio_probe_one_#t~ret1050#1; {1829#false} is VALID [2022-02-20 22:32:39,823 INFO L290 TraceCheckUtils]: 89: Hoare triple {1829#false} assume !(0 != initio_probe_one_~error~0#1);assume { :begin_inline_pci_read_config_dword } true;pci_read_config_dword_#in~dev#1.base, pci_read_config_dword_#in~dev#1.offset, pci_read_config_dword_#in~where#1, pci_read_config_dword_#in~val#1.base, pci_read_config_dword_#in~val#1.offset := initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset, 68, initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset;havoc pci_read_config_dword_#res#1;havoc pci_read_config_dword_#t~mem47#1.base, pci_read_config_dword_#t~mem47#1.offset, pci_read_config_dword_#t~mem48#1, pci_read_config_dword_#t~ret49#1, pci_read_config_dword_~dev#1.base, pci_read_config_dword_~dev#1.offset, pci_read_config_dword_~where#1, pci_read_config_dword_~val#1.base, pci_read_config_dword_~val#1.offset, pci_read_config_dword_~tmp~6#1;pci_read_config_dword_~dev#1.base, pci_read_config_dword_~dev#1.offset := pci_read_config_dword_#in~dev#1.base, pci_read_config_dword_#in~dev#1.offset;pci_read_config_dword_~where#1 := pci_read_config_dword_#in~where#1;pci_read_config_dword_~val#1.base, pci_read_config_dword_~val#1.offset := pci_read_config_dword_#in~val#1.base, pci_read_config_dword_#in~val#1.offset;havoc pci_read_config_dword_~tmp~6#1;call pci_read_config_dword_#t~mem47#1.base, pci_read_config_dword_#t~mem47#1.offset := read~$Pointer$(pci_read_config_dword_~dev#1.base, 16 + pci_read_config_dword_~dev#1.offset, 8);call pci_read_config_dword_#t~mem48#1 := read~int(pci_read_config_dword_~dev#1.base, 56 + pci_read_config_dword_~dev#1.offset, 4);assume { :begin_inline_pci_bus_read_config_dword } true;pci_bus_read_config_dword_#in~arg0#1.base, pci_bus_read_config_dword_#in~arg0#1.offset, pci_bus_read_config_dword_#in~arg1#1, pci_bus_read_config_dword_#in~arg2#1, pci_bus_read_config_dword_#in~arg3#1.base, pci_bus_read_config_dword_#in~arg3#1.offset := pci_read_config_dword_#t~mem47#1.base, pci_read_config_dword_#t~mem47#1.offset, pci_read_config_dword_#t~mem48#1, pci_read_config_dword_~where#1, pci_read_config_dword_~val#1.base, pci_read_config_dword_~val#1.offset;havoc pci_bus_read_config_dword_#res#1;havoc pci_bus_read_config_dword_#t~nondet1138#1, pci_bus_read_config_dword_~arg0#1.base, pci_bus_read_config_dword_~arg0#1.offset, pci_bus_read_config_dword_~arg1#1, pci_bus_read_config_dword_~arg2#1, pci_bus_read_config_dword_~arg3#1.base, pci_bus_read_config_dword_~arg3#1.offset;pci_bus_read_config_dword_~arg0#1.base, pci_bus_read_config_dword_~arg0#1.offset := pci_bus_read_config_dword_#in~arg0#1.base, pci_bus_read_config_dword_#in~arg0#1.offset;pci_bus_read_config_dword_~arg1#1 := pci_bus_read_config_dword_#in~arg1#1;pci_bus_read_config_dword_~arg2#1 := pci_bus_read_config_dword_#in~arg2#1;pci_bus_read_config_dword_~arg3#1.base, pci_bus_read_config_dword_~arg3#1.offset := pci_bus_read_config_dword_#in~arg3#1.base, pci_bus_read_config_dword_#in~arg3#1.offset;assume -2147483648 <= pci_bus_read_config_dword_#t~nondet1138#1 && pci_bus_read_config_dword_#t~nondet1138#1 <= 2147483647;pci_bus_read_config_dword_#res#1 := pci_bus_read_config_dword_#t~nondet1138#1;havoc pci_bus_read_config_dword_#t~nondet1138#1; {1829#false} is VALID [2022-02-20 22:32:39,824 INFO L290 TraceCheckUtils]: 90: Hoare triple {1829#false} pci_read_config_dword_#t~ret49#1 := pci_bus_read_config_dword_#res#1;assume { :end_inline_pci_bus_read_config_dword } true;assume -2147483648 <= pci_read_config_dword_#t~ret49#1 && pci_read_config_dword_#t~ret49#1 <= 2147483647;pci_read_config_dword_~tmp~6#1 := pci_read_config_dword_#t~ret49#1;havoc pci_read_config_dword_#t~mem47#1.base, pci_read_config_dword_#t~mem47#1.offset;havoc pci_read_config_dword_#t~mem48#1;havoc pci_read_config_dword_#t~ret49#1;pci_read_config_dword_#res#1 := pci_read_config_dword_~tmp~6#1; {1829#false} is VALID [2022-02-20 22:32:39,824 INFO L290 TraceCheckUtils]: 91: Hoare triple {1829#false} initio_probe_one_#t~ret1051#1 := pci_read_config_dword_#res#1;assume { :end_inline_pci_read_config_dword } true;assume -2147483648 <= initio_probe_one_#t~ret1051#1 && initio_probe_one_#t~ret1051#1 <= 2147483647;havoc initio_probe_one_#t~ret1051#1;call initio_probe_one_#t~mem1053#1 := read~int(initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, 4); {1829#false} is VALID [2022-02-20 22:32:39,824 INFO L290 TraceCheckUtils]: 92: Hoare triple {1829#false} assume 0 == initio_probe_one_#t~mem1053#1 % 65536;initio_probe_one_~bios_seg~0#1 := 0; {1829#false} is VALID [2022-02-20 22:32:39,824 INFO L290 TraceCheckUtils]: 93: Hoare triple {1829#false} havoc initio_probe_one_#t~mem1053#1;call initio_probe_one_#t~mem1055#1 := read~int(initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, 4); {1829#false} is VALID [2022-02-20 22:32:39,824 INFO L290 TraceCheckUtils]: 94: Hoare triple {1829#false} assume 255 == (if 0 == initio_probe_one_#t~mem1055#1 then 0 else (if 1 == initio_probe_one_#t~mem1055#1 then 0 else ~bitwiseAnd(initio_probe_one_#t~mem1055#1, 65280))) / 256 % 4294967296;havoc initio_probe_one_#t~mem1055#1;call write~int(0, initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, 4); {1829#false} is VALID [2022-02-20 22:32:39,825 INFO L290 TraceCheckUtils]: 95: Hoare triple {1829#false} call initio_probe_one_#t~mem1056#1 := read~int(initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, 4);initio_probe_one_~bios_seg~0#1 := 256 * (initio_probe_one_~bios_seg~0#1 % 65536) + (if 0 == initio_probe_one_#t~mem1056#1 then 0 else (if 1 == initio_probe_one_#t~mem1056#1 then 0 else ~bitwiseAnd(initio_probe_one_#t~mem1056#1, 65280))) / 256 % 65536;havoc initio_probe_one_#t~mem1056#1;assume { :begin_inline_pci_set_dma_mask } true;pci_set_dma_mask_#in~dev#1.base, pci_set_dma_mask_#in~dev#1.offset, pci_set_dma_mask_#in~mask#1 := initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset, 4294967295;havoc pci_set_dma_mask_#res#1;havoc pci_set_dma_mask_#t~ret100#1, pci_set_dma_mask_~dev#1.base, pci_set_dma_mask_~dev#1.offset, pci_set_dma_mask_~mask#1, pci_set_dma_mask_~tmp~10#1;pci_set_dma_mask_~dev#1.base, pci_set_dma_mask_~dev#1.offset := pci_set_dma_mask_#in~dev#1.base, pci_set_dma_mask_#in~dev#1.offset;pci_set_dma_mask_~mask#1 := pci_set_dma_mask_#in~mask#1;havoc pci_set_dma_mask_~tmp~10#1;assume { :begin_inline_dma_set_mask } true;dma_set_mask_#in~arg0#1.base, dma_set_mask_#in~arg0#1.offset, dma_set_mask_#in~arg1#1 := pci_set_dma_mask_~dev#1.base, 148 + pci_set_dma_mask_~dev#1.offset, pci_set_dma_mask_~mask#1;havoc dma_set_mask_#res#1;havoc dma_set_mask_#t~nondet1135#1, dma_set_mask_~arg0#1.base, dma_set_mask_~arg0#1.offset, dma_set_mask_~arg1#1;dma_set_mask_~arg0#1.base, dma_set_mask_~arg0#1.offset := dma_set_mask_#in~arg0#1.base, dma_set_mask_#in~arg0#1.offset;dma_set_mask_~arg1#1 := dma_set_mask_#in~arg1#1;assume -2147483648 <= dma_set_mask_#t~nondet1135#1 && dma_set_mask_#t~nondet1135#1 <= 2147483647;dma_set_mask_#res#1 := dma_set_mask_#t~nondet1135#1;havoc dma_set_mask_#t~nondet1135#1; {1829#false} is VALID [2022-02-20 22:32:39,825 INFO L290 TraceCheckUtils]: 96: Hoare triple {1829#false} pci_set_dma_mask_#t~ret100#1 := dma_set_mask_#res#1;assume { :end_inline_dma_set_mask } true;assume -2147483648 <= pci_set_dma_mask_#t~ret100#1 && pci_set_dma_mask_#t~ret100#1 <= 2147483647;pci_set_dma_mask_~tmp~10#1 := pci_set_dma_mask_#t~ret100#1;havoc pci_set_dma_mask_#t~ret100#1;pci_set_dma_mask_#res#1 := pci_set_dma_mask_~tmp~10#1; {1829#false} is VALID [2022-02-20 22:32:39,825 INFO L290 TraceCheckUtils]: 97: Hoare triple {1829#false} initio_probe_one_#t~ret1057#1 := pci_set_dma_mask_#res#1;assume { :end_inline_pci_set_dma_mask } true;assume -2147483648 <= initio_probe_one_#t~ret1057#1 && initio_probe_one_#t~ret1057#1 <= 2147483647;initio_probe_one_~tmp___0~33#1 := initio_probe_one_#t~ret1057#1;havoc initio_probe_one_#t~ret1057#1; {1829#false} is VALID [2022-02-20 22:32:39,825 INFO L290 TraceCheckUtils]: 98: Hoare triple {1829#false} assume !(0 != initio_probe_one_~tmp___0~33#1);assume { :begin_inline_ldv_scsi_host_alloc_25 } true;ldv_scsi_host_alloc_25_#in~sht#1.base, ldv_scsi_host_alloc_25_#in~sht#1.offset, ldv_scsi_host_alloc_25_#in~privsize#1 := ~#initio_template~0.base, ~#initio_template~0.offset, 464;havoc ldv_scsi_host_alloc_25_#res#1.base, ldv_scsi_host_alloc_25_#res#1.offset;havoc ldv_scsi_host_alloc_25_#t~ret1125#1.base, ldv_scsi_host_alloc_25_#t~ret1125#1.offset, ldv_scsi_host_alloc_25_~sht#1.base, ldv_scsi_host_alloc_25_~sht#1.offset, ldv_scsi_host_alloc_25_~privsize#1, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset, ldv_scsi_host_alloc_25_~tmp~68#1.base, ldv_scsi_host_alloc_25_~tmp~68#1.offset;ldv_scsi_host_alloc_25_~sht#1.base, ldv_scsi_host_alloc_25_~sht#1.offset := ldv_scsi_host_alloc_25_#in~sht#1.base, ldv_scsi_host_alloc_25_#in~sht#1.offset;ldv_scsi_host_alloc_25_~privsize#1 := ldv_scsi_host_alloc_25_#in~privsize#1;havoc ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset;havoc ldv_scsi_host_alloc_25_~tmp~68#1.base, ldv_scsi_host_alloc_25_~tmp~68#1.offset;assume { :begin_inline_scsi_host_alloc } true;scsi_host_alloc_#in~arg0#1.base, scsi_host_alloc_#in~arg0#1.offset, scsi_host_alloc_#in~arg1#1 := ldv_scsi_host_alloc_25_~sht#1.base, ldv_scsi_host_alloc_25_~sht#1.offset, ldv_scsi_host_alloc_25_~privsize#1;havoc scsi_host_alloc_#res#1.base, scsi_host_alloc_#res#1.offset;havoc scsi_host_alloc_#t~ret1144#1.base, scsi_host_alloc_#t~ret1144#1.offset, scsi_host_alloc_~arg0#1.base, scsi_host_alloc_~arg0#1.offset, scsi_host_alloc_~arg1#1;scsi_host_alloc_~arg0#1.base, scsi_host_alloc_~arg0#1.offset := scsi_host_alloc_#in~arg0#1.base, scsi_host_alloc_#in~arg0#1.offset;scsi_host_alloc_~arg1#1 := scsi_host_alloc_#in~arg1#1; {1829#false} is VALID [2022-02-20 22:32:39,825 INFO L272 TraceCheckUtils]: 99: Hoare triple {1829#false} call scsi_host_alloc_#t~ret1144#1.base, scsi_host_alloc_#t~ret1144#1.offset := ldv_malloc(3601); {1929#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:32:39,826 INFO L290 TraceCheckUtils]: 100: Hoare triple {1929#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {1828#true} is VALID [2022-02-20 22:32:39,826 INFO L290 TraceCheckUtils]: 101: Hoare triple {1828#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {1828#true} is VALID [2022-02-20 22:32:39,826 INFO L290 TraceCheckUtils]: 102: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,826 INFO L284 TraceCheckUtils]: 103: Hoare quadruple {1828#true} {1829#false} #4708#return; {1829#false} is VALID [2022-02-20 22:32:39,826 INFO L290 TraceCheckUtils]: 104: Hoare triple {1829#false} scsi_host_alloc_#res#1.base, scsi_host_alloc_#res#1.offset := scsi_host_alloc_#t~ret1144#1.base, scsi_host_alloc_#t~ret1144#1.offset;havoc scsi_host_alloc_#t~ret1144#1.base, scsi_host_alloc_#t~ret1144#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,826 INFO L290 TraceCheckUtils]: 105: Hoare triple {1829#false} ldv_scsi_host_alloc_25_#t~ret1125#1.base, ldv_scsi_host_alloc_25_#t~ret1125#1.offset := scsi_host_alloc_#res#1.base, scsi_host_alloc_#res#1.offset;assume { :end_inline_scsi_host_alloc } true;ldv_scsi_host_alloc_25_~tmp~68#1.base, ldv_scsi_host_alloc_25_~tmp~68#1.offset := ldv_scsi_host_alloc_25_#t~ret1125#1.base, ldv_scsi_host_alloc_25_#t~ret1125#1.offset;havoc ldv_scsi_host_alloc_25_#t~ret1125#1.base, ldv_scsi_host_alloc_25_#t~ret1125#1.offset;ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset := ldv_scsi_host_alloc_25_~tmp~68#1.base, ldv_scsi_host_alloc_25_~tmp~68#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,827 INFO L290 TraceCheckUtils]: 106: Hoare triple {1829#false} assume !(0 != (ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base + ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset) % 18446744073709551616); {1829#false} is VALID [2022-02-20 22:32:39,827 INFO L290 TraceCheckUtils]: 107: Hoare triple {1829#false} ldv_scsi_host_alloc_25_#res#1.base, ldv_scsi_host_alloc_25_#res#1.offset := ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,827 INFO L290 TraceCheckUtils]: 108: Hoare triple {1829#false} initio_probe_one_#t~ret1059#1.base, initio_probe_one_#t~ret1059#1.offset := ldv_scsi_host_alloc_25_#res#1.base, ldv_scsi_host_alloc_25_#res#1.offset;assume { :end_inline_ldv_scsi_host_alloc_25 } true;initio_probe_one_~shost~0#1.base, initio_probe_one_~shost~0#1.offset := initio_probe_one_#t~ret1059#1.base, initio_probe_one_#t~ret1059#1.offset;havoc initio_probe_one_#t~ret1059#1.base, initio_probe_one_#t~ret1059#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,828 INFO L290 TraceCheckUtils]: 109: Hoare triple {1829#false} assume !(0 == (initio_probe_one_~shost~0#1.base + initio_probe_one_~shost~0#1.offset) % 18446744073709551616);initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset := initio_probe_one_~shost~0#1.base, 3601 + initio_probe_one_~shost~0#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,828 INFO L272 TraceCheckUtils]: 110: Hoare triple {1829#false} call initio_probe_one_#t~memset~res1061#1.base, initio_probe_one_#t~memset~res1061#1.offset := #Ultimate.C_memset(initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset, 0, 464); {1937#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:32:39,828 INFO L290 TraceCheckUtils]: 111: Hoare triple {1937#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} #t~loopctr1148 := 0; {1828#true} is VALID [2022-02-20 22:32:39,828 INFO L290 TraceCheckUtils]: 112: Hoare triple {1828#true} assume !(#t~loopctr1148 % 18446744073709551616 < #amount % 18446744073709551616); {1828#true} is VALID [2022-02-20 22:32:39,828 INFO L290 TraceCheckUtils]: 113: Hoare triple {1828#true} assume #res.base == #ptr.base && #res.offset == #ptr.offset; {1828#true} is VALID [2022-02-20 22:32:39,828 INFO L284 TraceCheckUtils]: 114: Hoare quadruple {1828#true} {1829#false} #4712#return; {1829#false} is VALID [2022-02-20 22:32:39,829 INFO L290 TraceCheckUtils]: 115: Hoare triple {1829#false} havoc initio_probe_one_#t~memset~res1061#1.base, initio_probe_one_#t~memset~res1061#1.offset;call initio_probe_one_#t~mem1062#1 := read~int(initio_probe_one_~pdev#1.base, 1493 + initio_probe_one_~pdev#1.offset, 8);call write~int(initio_probe_one_#t~mem1062#1, initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset, 2);havoc initio_probe_one_#t~mem1062#1;call write~int(initio_probe_one_~bios_seg~0#1, initio_probe_one_~host~4#1.base, 2 + initio_probe_one_~host~4#1.offset, 2);call initio_probe_one_#t~mem1063#1 := read~int(initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset, 2);assume { :begin_inline___request_region } true;__request_region_#in~arg0#1.base, __request_region_#in~arg0#1.offset, __request_region_#in~arg1#1, __request_region_#in~arg2#1, __request_region_#in~arg3#1.base, __request_region_#in~arg3#1.offset, __request_region_#in~arg4#1 := ~#ioport_resource~0.base, ~#ioport_resource~0.offset, initio_probe_one_#t~mem1063#1 % 65536, 256, 13, 0, 0;havoc __request_region_#res#1.base, __request_region_#res#1.offset;havoc __request_region_#t~ret1134#1.base, __request_region_#t~ret1134#1.offset, __request_region_~arg0#1.base, __request_region_~arg0#1.offset, __request_region_~arg1#1, __request_region_~arg2#1, __request_region_~arg3#1.base, __request_region_~arg3#1.offset, __request_region_~arg4#1;__request_region_~arg0#1.base, __request_region_~arg0#1.offset := __request_region_#in~arg0#1.base, __request_region_#in~arg0#1.offset;__request_region_~arg1#1 := __request_region_#in~arg1#1;__request_region_~arg2#1 := __request_region_#in~arg2#1;__request_region_~arg3#1.base, __request_region_~arg3#1.offset := __request_region_#in~arg3#1.base, __request_region_#in~arg3#1.offset;__request_region_~arg4#1 := __request_region_#in~arg4#1; {1829#false} is VALID [2022-02-20 22:32:39,829 INFO L272 TraceCheckUtils]: 116: Hoare triple {1829#false} call __request_region_#t~ret1134#1.base, __request_region_#t~ret1134#1.offset := ldv_malloc(56); {1929#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:32:39,829 INFO L290 TraceCheckUtils]: 117: Hoare triple {1929#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {1828#true} is VALID [2022-02-20 22:32:39,829 INFO L290 TraceCheckUtils]: 118: Hoare triple {1828#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {1828#true} is VALID [2022-02-20 22:32:39,829 INFO L290 TraceCheckUtils]: 119: Hoare triple {1828#true} assume true; {1828#true} is VALID [2022-02-20 22:32:39,830 INFO L284 TraceCheckUtils]: 120: Hoare quadruple {1828#true} {1829#false} #4714#return; {1829#false} is VALID [2022-02-20 22:32:39,830 INFO L290 TraceCheckUtils]: 121: Hoare triple {1829#false} __request_region_#res#1.base, __request_region_#res#1.offset := __request_region_#t~ret1134#1.base, __request_region_#t~ret1134#1.offset;havoc __request_region_#t~ret1134#1.base, __request_region_#t~ret1134#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,830 INFO L290 TraceCheckUtils]: 122: Hoare triple {1829#false} initio_probe_one_#t~ret1064#1.base, initio_probe_one_#t~ret1064#1.offset := __request_region_#res#1.base, __request_region_#res#1.offset;assume { :end_inline___request_region } true;initio_probe_one_~tmp___1~21#1.base, initio_probe_one_~tmp___1~21#1.offset := initio_probe_one_#t~ret1064#1.base, initio_probe_one_#t~ret1064#1.offset;havoc initio_probe_one_#t~mem1063#1;havoc initio_probe_one_#t~ret1064#1.base, initio_probe_one_#t~ret1064#1.offset; {1829#false} is VALID [2022-02-20 22:32:39,830 INFO L290 TraceCheckUtils]: 123: Hoare triple {1829#false} assume !(0 == (initio_probe_one_~tmp___1~21#1.base + initio_probe_one_~tmp___1~21#1.offset) % 18446744073709551616); {1829#false} is VALID [2022-02-20 22:32:39,830 INFO L290 TraceCheckUtils]: 124: Hoare triple {1829#false} assume 0 != ~initio_tag_enable~0;initio_probe_one_~num_scb~0#1 := 32; {1829#false} is VALID [2022-02-20 22:32:39,830 INFO L290 TraceCheckUtils]: 125: Hoare triple {1829#false} assume initio_probe_one_~num_scb~0#1 > 18; {1829#false} is VALID [2022-02-20 22:32:39,831 INFO L290 TraceCheckUtils]: 126: Hoare triple {1829#false} initio_probe_one_~i~16#1 := (if 352 * initio_probe_one_~num_scb~0#1 % 4294967296 % 4294967296 <= 2147483647 then 352 * initio_probe_one_~num_scb~0#1 % 4294967296 % 4294967296 else 352 * initio_probe_one_~num_scb~0#1 % 4294967296 % 4294967296 - 4294967296);assume { :begin_inline_kzalloc } true;kzalloc_#in~size#1, kzalloc_#in~flags#1 := initio_probe_one_~i~16#1, 1;havoc kzalloc_#res#1.base, kzalloc_#res#1.offset;havoc kzalloc_#t~ret1123#1.base, kzalloc_#t~ret1123#1.offset, kzalloc_~size#1, kzalloc_~flags#1, kzalloc_~tmp~66#1.base, kzalloc_~tmp~66#1.offset;kzalloc_~size#1 := kzalloc_#in~size#1;kzalloc_~flags#1 := kzalloc_#in~flags#1;havoc kzalloc_~tmp~66#1.base, kzalloc_~tmp~66#1.offset;assume { :begin_inline_ldv_check_alloc_flags } true;ldv_check_alloc_flags_#in~flags#1 := kzalloc_~flags#1;havoc ldv_check_alloc_flags_~flags#1;ldv_check_alloc_flags_~flags#1 := ldv_check_alloc_flags_#in~flags#1; {1829#false} is VALID [2022-02-20 22:32:39,831 INFO L290 TraceCheckUtils]: 127: Hoare triple {1829#false} assume 0 != ~ldv_spin~0 && 0 != (if 0 == ldv_check_alloc_flags_~flags#1 then 0 else (if 1 == ldv_check_alloc_flags_~flags#1 then 0 else ~bitwiseAnd(ldv_check_alloc_flags_~flags#1, 16))) % 4294967296; {1829#false} is VALID [2022-02-20 22:32:39,831 INFO L272 TraceCheckUtils]: 128: Hoare triple {1829#false} call ldv_error(); {1829#false} is VALID [2022-02-20 22:32:39,831 INFO L290 TraceCheckUtils]: 129: Hoare triple {1829#false} assume !false; {1829#false} is VALID [2022-02-20 22:32:39,833 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2022-02-20 22:32:39,833 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:32:39,834 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55296720] [2022-02-20 22:32:39,834 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55296720] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:32:39,839 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:32:39,839 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-02-20 22:32:39,840 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1658569931] [2022-02-20 22:32:39,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:32:39,844 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.833333333333334) internal successors, (59), 2 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 2 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) Word has length 130 [2022-02-20 22:32:39,845 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:32:39,847 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 9.833333333333334) internal successors, (59), 2 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 2 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) [2022-02-20 22:32:39,943 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:32:39,944 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-02-20 22:32:39,944 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:32:39,956 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-02-20 22:32:39,957 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2022-02-20 22:32:39,963 INFO L87 Difference]: Start difference. First operand has 1825 states, 1247 states have (on average 1.347233360064154) internal successors, (1680), 1282 states have internal predecessors, (1680), 513 states have call successors, (513), 64 states have call predecessors, (513), 63 states have return successors, (507), 501 states have call predecessors, (507), 507 states have call successors, (507) Second operand has 6 states, 6 states have (on average 9.833333333333334) internal successors, (59), 2 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 2 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) [2022-02-20 22:32:45,158 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:32:59,851 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.01s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:33:01,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:33:01,734 INFO L93 Difference]: Finished difference Result 3969 states and 6032 transitions. [2022-02-20 22:33:01,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-02-20 22:33:01,735 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.833333333333334) internal successors, (59), 2 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 2 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) Word has length 130 [2022-02-20 22:33:01,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:33:01,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 9.833333333333334) internal successors, (59), 2 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 2 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) [2022-02-20 22:33:02,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 6032 transitions. [2022-02-20 22:33:02,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 9.833333333333334) internal successors, (59), 2 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 2 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) [2022-02-20 22:33:02,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 6032 transitions. [2022-02-20 22:33:02,303 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 6032 transitions. [2022-02-20 22:33:07,465 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 6032 edges. 6032 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:33:07,791 INFO L225 Difference]: With dead ends: 3969 [2022-02-20 22:33:07,792 INFO L226 Difference]: Without dead ends: 2129 [2022-02-20 22:33:07,807 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2022-02-20 22:33:07,809 INFO L933 BasicCegarLoop]: 2082 mSDtfsCounter, 2078 mSDsluCounter, 879 mSDsCounter, 0 mSdLazyCounter, 4008 mSolverCounterSat, 1576 mSolverCounterUnsat, 2 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 10.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2438 SdHoareTripleChecker+Valid, 2961 SdHoareTripleChecker+Invalid, 5586 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 1576 IncrementalHoareTripleChecker+Valid, 4008 IncrementalHoareTripleChecker+Invalid, 2 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 10.4s IncrementalHoareTripleChecker+Time [2022-02-20 22:33:07,810 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [2438 Valid, 2961 Invalid, 5586 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [1576 Valid, 4008 Invalid, 2 Unknown, 0 Unchecked, 10.4s Time] [2022-02-20 22:33:07,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2129 states. [2022-02-20 22:33:07,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2129 to 1805. [2022-02-20 22:33:07,963 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:33:07,976 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2129 states. Second operand has 1805 states, 1235 states have (on average 1.323076923076923) internal successors, (1634), 1262 states have internal predecessors, (1634), 507 states have call successors, (507), 63 states have call predecessors, (507), 62 states have return successors, (506), 500 states have call predecessors, (506), 506 states have call successors, (506) [2022-02-20 22:33:07,984 INFO L74 IsIncluded]: Start isIncluded. First operand 2129 states. Second operand has 1805 states, 1235 states have (on average 1.323076923076923) internal successors, (1634), 1262 states have internal predecessors, (1634), 507 states have call successors, (507), 63 states have call predecessors, (507), 62 states have return successors, (506), 500 states have call predecessors, (506), 506 states have call successors, (506) [2022-02-20 22:33:07,988 INFO L87 Difference]: Start difference. First operand 2129 states. Second operand has 1805 states, 1235 states have (on average 1.323076923076923) internal successors, (1634), 1262 states have internal predecessors, (1634), 507 states have call successors, (507), 63 states have call predecessors, (507), 62 states have return successors, (506), 500 states have call predecessors, (506), 506 states have call successors, (506) [2022-02-20 22:33:08,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:33:08,193 INFO L93 Difference]: Finished difference Result 2129 states and 3171 transitions. [2022-02-20 22:33:08,193 INFO L276 IsEmpty]: Start isEmpty. Operand 2129 states and 3171 transitions. [2022-02-20 22:33:08,211 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:33:08,211 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:33:08,217 INFO L74 IsIncluded]: Start isIncluded. First operand has 1805 states, 1235 states have (on average 1.323076923076923) internal successors, (1634), 1262 states have internal predecessors, (1634), 507 states have call successors, (507), 63 states have call predecessors, (507), 62 states have return successors, (506), 500 states have call predecessors, (506), 506 states have call successors, (506) Second operand 2129 states. [2022-02-20 22:33:08,221 INFO L87 Difference]: Start difference. First operand has 1805 states, 1235 states have (on average 1.323076923076923) internal successors, (1634), 1262 states have internal predecessors, (1634), 507 states have call successors, (507), 63 states have call predecessors, (507), 62 states have return successors, (506), 500 states have call predecessors, (506), 506 states have call successors, (506) Second operand 2129 states. [2022-02-20 22:33:08,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:33:08,425 INFO L93 Difference]: Finished difference Result 2129 states and 3171 transitions. [2022-02-20 22:33:08,425 INFO L276 IsEmpty]: Start isEmpty. Operand 2129 states and 3171 transitions. [2022-02-20 22:33:08,437 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:33:08,438 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:33:08,438 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:33:08,438 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:33:08,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1235 states have (on average 1.323076923076923) internal successors, (1634), 1262 states have internal predecessors, (1634), 507 states have call successors, (507), 63 states have call predecessors, (507), 62 states have return successors, (506), 500 states have call predecessors, (506), 506 states have call successors, (506) [2022-02-20 22:33:08,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2647 transitions. [2022-02-20 22:33:08,660 INFO L78 Accepts]: Start accepts. Automaton has 1805 states and 2647 transitions. Word has length 130 [2022-02-20 22:33:08,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:33:08,662 INFO L470 AbstractCegarLoop]: Abstraction has 1805 states and 2647 transitions. [2022-02-20 22:33:08,662 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.833333333333334) internal successors, (59), 2 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 2 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) [2022-02-20 22:33:08,662 INFO L276 IsEmpty]: Start isEmpty. Operand 1805 states and 2647 transitions. [2022-02-20 22:33:08,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2022-02-20 22:33:08,669 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:33:08,669 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:33:08,670 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-02-20 22:33:08,670 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:33:08,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:33:08,671 INFO L85 PathProgramCache]: Analyzing trace with hash 972684156, now seen corresponding path program 1 times [2022-02-20 22:33:08,671 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:33:08,671 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598024233] [2022-02-20 22:33:08,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:33:08,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:33:08,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,818 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:33:08,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,833 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:33:08,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,838 INFO L290 TraceCheckUtils]: 0: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:08,838 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,842 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:08,842 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:33:08,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,855 INFO L290 TraceCheckUtils]: 0: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:08,855 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:08,855 INFO L290 TraceCheckUtils]: 2: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,856 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:08,856 INFO L290 TraceCheckUtils]: 0: Hoare triple {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {14431#true} is VALID [2022-02-20 22:33:08,857 INFO L272 TraceCheckUtils]: 1: Hoare triple {14431#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {14518#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:33:08,857 INFO L290 TraceCheckUtils]: 2: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:08,857 INFO L290 TraceCheckUtils]: 3: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,857 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:08,857 INFO L290 TraceCheckUtils]: 5: Hoare triple {14431#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14431#true} is VALID [2022-02-20 22:33:08,858 INFO L272 TraceCheckUtils]: 6: Hoare triple {14431#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14431#true} is VALID [2022-02-20 22:33:08,858 INFO L290 TraceCheckUtils]: 7: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:08,858 INFO L290 TraceCheckUtils]: 8: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:08,858 INFO L290 TraceCheckUtils]: 9: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,858 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:08,858 INFO L290 TraceCheckUtils]: 11: Hoare triple {14431#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14431#true} is VALID [2022-02-20 22:33:08,858 INFO L290 TraceCheckUtils]: 12: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,859 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14431#true} {14431#true} #4638#return; {14431#true} is VALID [2022-02-20 22:33:08,859 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 18 [2022-02-20 22:33:08,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,876 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:33:08,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,885 INFO L290 TraceCheckUtils]: 0: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:08,887 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,887 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:08,887 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:33:08,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,893 INFO L290 TraceCheckUtils]: 0: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:08,893 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:08,893 INFO L290 TraceCheckUtils]: 2: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,893 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:08,894 INFO L290 TraceCheckUtils]: 0: Hoare triple {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {14431#true} is VALID [2022-02-20 22:33:08,894 INFO L272 TraceCheckUtils]: 1: Hoare triple {14431#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {14518#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:33:08,894 INFO L290 TraceCheckUtils]: 2: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:08,894 INFO L290 TraceCheckUtils]: 3: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,895 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:08,895 INFO L290 TraceCheckUtils]: 5: Hoare triple {14431#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14431#true} is VALID [2022-02-20 22:33:08,895 INFO L272 TraceCheckUtils]: 6: Hoare triple {14431#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14431#true} is VALID [2022-02-20 22:33:08,895 INFO L290 TraceCheckUtils]: 7: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:08,895 INFO L290 TraceCheckUtils]: 8: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:08,895 INFO L290 TraceCheckUtils]: 9: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,895 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:08,896 INFO L290 TraceCheckUtils]: 11: Hoare triple {14431#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14431#true} is VALID [2022-02-20 22:33:08,896 INFO L290 TraceCheckUtils]: 12: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,896 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14431#true} {14431#true} #4640#return; {14431#true} is VALID [2022-02-20 22:33:08,896 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 34 [2022-02-20 22:33:08,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,910 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:33:08,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,920 INFO L290 TraceCheckUtils]: 0: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:08,920 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,921 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:08,921 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:33:08,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,925 INFO L290 TraceCheckUtils]: 0: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:08,925 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:08,925 INFO L290 TraceCheckUtils]: 2: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,925 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:08,926 INFO L290 TraceCheckUtils]: 0: Hoare triple {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {14431#true} is VALID [2022-02-20 22:33:08,927 INFO L272 TraceCheckUtils]: 1: Hoare triple {14431#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {14518#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:33:08,927 INFO L290 TraceCheckUtils]: 2: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:08,927 INFO L290 TraceCheckUtils]: 3: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,927 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:08,928 INFO L290 TraceCheckUtils]: 5: Hoare triple {14431#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14431#true} is VALID [2022-02-20 22:33:08,928 INFO L272 TraceCheckUtils]: 6: Hoare triple {14431#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14431#true} is VALID [2022-02-20 22:33:08,928 INFO L290 TraceCheckUtils]: 7: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:08,928 INFO L290 TraceCheckUtils]: 8: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:08,928 INFO L290 TraceCheckUtils]: 9: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,928 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:08,928 INFO L290 TraceCheckUtils]: 11: Hoare triple {14431#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14431#true} is VALID [2022-02-20 22:33:08,928 INFO L290 TraceCheckUtils]: 12: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,929 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14431#true} {14431#true} #4642#return; {14431#true} is VALID [2022-02-20 22:33:08,933 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 50 [2022-02-20 22:33:08,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,950 INFO L290 TraceCheckUtils]: 0: Hoare triple {14533#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {14431#true} is VALID [2022-02-20 22:33:08,950 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {14431#true} is VALID [2022-02-20 22:33:08,951 INFO L290 TraceCheckUtils]: 2: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,951 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14431#true} {14431#true} #4644#return; {14431#true} is VALID [2022-02-20 22:33:08,951 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 56 [2022-02-20 22:33:08,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,963 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:33:08,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,967 INFO L290 TraceCheckUtils]: 0: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:08,967 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,968 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:08,968 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 6 [2022-02-20 22:33:08,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,978 INFO L290 TraceCheckUtils]: 0: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:08,979 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:08,979 INFO L290 TraceCheckUtils]: 2: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,979 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:08,979 INFO L290 TraceCheckUtils]: 0: Hoare triple {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {14431#true} is VALID [2022-02-20 22:33:08,980 INFO L272 TraceCheckUtils]: 1: Hoare triple {14431#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {14518#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:33:08,980 INFO L290 TraceCheckUtils]: 2: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:08,980 INFO L290 TraceCheckUtils]: 3: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,980 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:08,981 INFO L290 TraceCheckUtils]: 5: Hoare triple {14431#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14431#true} is VALID [2022-02-20 22:33:08,981 INFO L272 TraceCheckUtils]: 6: Hoare triple {14431#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14431#true} is VALID [2022-02-20 22:33:08,981 INFO L290 TraceCheckUtils]: 7: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:08,981 INFO L290 TraceCheckUtils]: 8: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:08,981 INFO L290 TraceCheckUtils]: 9: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,981 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:08,981 INFO L290 TraceCheckUtils]: 11: Hoare triple {14431#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14431#true} is VALID [2022-02-20 22:33:08,981 INFO L290 TraceCheckUtils]: 12: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:08,981 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14431#true} {14431#true} #4646#return; {14431#true} is VALID [2022-02-20 22:33:08,987 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 73 [2022-02-20 22:33:08,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:08,995 INFO L290 TraceCheckUtils]: 0: Hoare triple {14541#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} #t~loopctr1148 := 0; {14431#true} is VALID [2022-02-20 22:33:08,999 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume !(#t~loopctr1148 % 18446744073709551616 < #amount % 18446744073709551616); {14431#true} is VALID [2022-02-20 22:33:09,000 INFO L290 TraceCheckUtils]: 2: Hoare triple {14431#true} assume #res.base == #ptr.base && #res.offset == #ptr.offset; {14431#true} is VALID [2022-02-20 22:33:09,000 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14431#true} {14431#true} #4648#return; {14431#true} is VALID [2022-02-20 22:33:09,000 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 99 [2022-02-20 22:33:09,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:09,006 INFO L290 TraceCheckUtils]: 0: Hoare triple {14533#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {14431#true} is VALID [2022-02-20 22:33:09,006 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {14431#true} is VALID [2022-02-20 22:33:09,006 INFO L290 TraceCheckUtils]: 2: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,006 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14431#true} {14432#false} #4708#return; {14432#false} is VALID [2022-02-20 22:33:09,007 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 110 [2022-02-20 22:33:09,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:09,013 INFO L290 TraceCheckUtils]: 0: Hoare triple {14541#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} #t~loopctr1148 := 0; {14431#true} is VALID [2022-02-20 22:33:09,014 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume !(#t~loopctr1148 % 18446744073709551616 < #amount % 18446744073709551616); {14431#true} is VALID [2022-02-20 22:33:09,014 INFO L290 TraceCheckUtils]: 2: Hoare triple {14431#true} assume #res.base == #ptr.base && #res.offset == #ptr.offset; {14431#true} is VALID [2022-02-20 22:33:09,014 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14431#true} {14432#false} #4712#return; {14432#false} is VALID [2022-02-20 22:33:09,014 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 116 [2022-02-20 22:33:09,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:33:09,020 INFO L290 TraceCheckUtils]: 0: Hoare triple {14533#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {14431#true} is VALID [2022-02-20 22:33:09,020 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {14431#true} is VALID [2022-02-20 22:33:09,020 INFO L290 TraceCheckUtils]: 2: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,020 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {14431#true} {14432#false} #4714#return; {14432#false} is VALID [2022-02-20 22:33:09,021 INFO L290 TraceCheckUtils]: 0: Hoare triple {14431#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(74, 2);call #Ultimate.allocInit(57, 3);call #Ultimate.allocInit(28, 4);call #Ultimate.allocInit(21, 5);call #Ultimate.allocInit(36, 6);call #Ultimate.allocInit(200, 7);call #Ultimate.allocInit(17, 8);call #Ultimate.allocInit(39, 9);call #Ultimate.allocInit(9, 10);call #Ultimate.allocInit(38, 11);call #Ultimate.allocInit(45, 12);call #Ultimate.allocInit(5, 13);call write~init~int(105, 13, 0, 1);call write~init~int(57, 13, 1, 1);call write~init~int(49, 13, 2, 1);call write~init~int(117, 13, 3, 1);call write~init~int(0, 13, 4, 1);call #Ultimate.allocInit(39, 14);call #Ultimate.allocInit(37, 15);call #Ultimate.allocInit(29, 16);call #Ultimate.allocInit(28, 17);call #Ultimate.allocInit(5, 18);call write~init~int(105, 18, 0, 1);call write~init~int(57, 18, 1, 1);call write~init~int(49, 18, 2, 1);call write~init~int(117, 18, 3, 1);call write~init~int(0, 18, 4, 1);call #Ultimate.allocInit(35, 19);call #Ultimate.allocInit(7, 20);call write~init~int(105, 20, 0, 1);call write~init~int(110, 20, 1, 1);call write~init~int(105, 20, 2, 1);call write~init~int(116, 20, 3, 1);call write~init~int(105, 20, 4, 1);call write~init~int(111, 20, 5, 1);call write~init~int(0, 20, 6, 1);call #Ultimate.allocInit(7, 21);call write~init~int(105, 21, 0, 1);call write~init~int(110, 21, 1, 1);call write~init~int(105, 21, 2, 1);call write~init~int(116, 21, 3, 1);call write~init~int(105, 21, 4, 1);call write~init~int(111, 21, 5, 1);call write~init~int(0, 21, 6, 1);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~pci_counter~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~initio_template_group0~0.base, ~initio_template_group0~0.offset := 0, 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~initio_pci_driver_group1~0.base, ~initio_pci_driver_group1~0.offset := 0, 0;~initio_tag_enable~0 := 1;~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[0 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[1 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[2 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[3 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[4 := 0];~__mod_pci__i91u_pci_devices_device_table~0.vendor := ~__mod_pci__i91u_pci_devices_device_table~0.vendor[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.device := ~__mod_pci__i91u_pci_devices_device_table~0.device[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subvendor := ~__mod_pci__i91u_pci_devices_device_table~0.subvendor[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.subdevice := ~__mod_pci__i91u_pci_devices_device_table~0.subdevice[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class := ~__mod_pci__i91u_pci_devices_device_table~0.class[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.class_mask := ~__mod_pci__i91u_pci_devices_device_table~0.class_mask[5 := 0];~__mod_pci__i91u_pci_devices_device_table~0.driver_data := ~__mod_pci__i91u_pci_devices_device_table~0.driver_data[5 := 0];~#i91unvram~0.base, ~#i91unvram~0.offset := 22, 0;call #Ultimate.allocInit(64, 22);#memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, ~#i91unvram~0.base);~i91unvramp~0.base, ~i91unvramp~0.offset := 0, 0;~#i91udftNvRam~0.base, ~#i91udftNvRam~0.offset := 23, 0;call #Ultimate.allocInit(64, 23);call write~init~int(37, ~#i91udftNvRam~0.base, ~#i91udftNvRam~0.offset, 1);call write~init~int(201, ~#i91udftNvRam~0.base, 1 + ~#i91udftNvRam~0.offset, 1);call write~init~int(64, ~#i91udftNvRam~0.base, 2 + ~#i91udftNvRam~0.offset, 1);call write~init~int(1, ~#i91udftNvRam~0.base, 3 + ~#i91udftNvRam~0.offset, 1);call write~init~int(149, ~#i91udftNvRam~0.base, 4 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 5 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 6 + ~#i91udftNvRam~0.offset, 1);call write~init~int(1, ~#i91udftNvRam~0.base, 7 + ~#i91udftNvRam~0.offset, 1);call write~init~int(1, ~#i91udftNvRam~0.base, 8 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 9 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 10 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 11 + ~#i91udftNvRam~0.offset, 1);call write~init~int(7, ~#i91udftNvRam~0.base, 12 + ~#i91udftNvRam~0.offset, 1);call write~init~int(19, ~#i91udftNvRam~0.base, 13 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 14 + ~#i91udftNvRam~0.offset, 1);call write~init~int(16, ~#i91udftNvRam~0.base, 15 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 16 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 17 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 18 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 19 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 20 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 21 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 22 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 23 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 24 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 25 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 26 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 27 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 28 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 29 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 30 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 31 + ~#i91udftNvRam~0.offset, 1);call write~init~int(7, ~#i91udftNvRam~0.base, 32 + ~#i91udftNvRam~0.offset, 1);call write~init~int(19, ~#i91udftNvRam~0.base, 33 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 34 + ~#i91udftNvRam~0.offset, 1);call write~init~int(16, ~#i91udftNvRam~0.base, 35 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 36 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 37 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 38 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 39 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 40 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 41 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 42 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 43 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 44 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 45 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 46 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 47 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 48 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 49 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 50 + ~#i91udftNvRam~0.offset, 1);call write~init~int(104, ~#i91udftNvRam~0.base, 51 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 52 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 53 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 54 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 55 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 56 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 57 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 58 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 59 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 60 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 61 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 62 + ~#i91udftNvRam~0.offset, 1);call write~init~int(0, ~#i91udftNvRam~0.base, 63 + ~#i91udftNvRam~0.offset, 1);~#initio_rate_tbl~0.base, ~#initio_rate_tbl~0.offset := 24, 0;call #Ultimate.allocInit(8, 24);call write~init~int(12, ~#initio_rate_tbl~0.base, ~#initio_rate_tbl~0.offset, 1);call write~init~int(18, ~#initio_rate_tbl~0.base, 1 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(25, ~#initio_rate_tbl~0.base, 2 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(31, ~#initio_rate_tbl~0.base, 3 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(37, ~#initio_rate_tbl~0.base, 4 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(43, ~#initio_rate_tbl~0.base, 5 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(50, ~#initio_rate_tbl~0.base, 6 + ~#initio_rate_tbl~0.offset, 1);call write~init~int(62, ~#initio_rate_tbl~0.base, 7 + ~#initio_rate_tbl~0.offset, 1);~#initio_template~0.base, ~#initio_template~0.offset := 25, 0;call #Ultimate.allocInit(329, 25);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, ~#initio_template~0.offset, 8);call write~init~$Pointer$(9, 0, ~#initio_template~0.base, 8 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 16 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 24 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 32 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 40 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 48 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(#funAddr~i91u_queuecommand.base, #funAddr~i91u_queuecommand.offset, ~#initio_template~0.base, 56 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 64 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 72 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 80 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(#funAddr~i91u_bus_reset.base, #funAddr~i91u_bus_reset.offset, ~#initio_template~0.base, 88 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 96 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 104 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 112 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 120 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 128 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 136 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 144 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 152 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 160 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(#funAddr~i91u_biosparam.base, #funAddr~i91u_biosparam.offset, ~#initio_template~0.base, 168 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 176 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 184 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 192 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 200 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 208 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(10, 0, ~#initio_template~0.base, 216 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 224 + ~#initio_template~0.offset, 8);call write~init~int(32, ~#initio_template~0.base, 232 + ~#initio_template~0.offset, 4);call write~init~int(1, ~#initio_template~0.base, 236 + ~#initio_template~0.offset, 4);call write~init~int(128, ~#initio_template~0.base, 240 + ~#initio_template~0.offset, 2);call write~init~int(0, ~#initio_template~0.base, 242 + ~#initio_template~0.offset, 2);call write~init~int(0, ~#initio_template~0.base, 244 + ~#initio_template~0.offset, 4);call write~init~int(0, ~#initio_template~0.base, 248 + ~#initio_template~0.offset, 8);call write~init~int(0, ~#initio_template~0.base, 256 + ~#initio_template~0.offset, 2);call write~init~int(0, ~#initio_template~0.base, 258 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 259 + ~#initio_template~0.offset, 4);call write~init~int(0, ~#initio_template~0.base, 263 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 264 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 265 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 266 + ~#initio_template~0.offset, 1);call write~init~int(1, ~#initio_template~0.base, 267 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 268 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 269 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 270 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 271 + ~#initio_template~0.offset, 1);call write~init~int(0, ~#initio_template~0.base, 272 + ~#initio_template~0.offset, 4);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 276 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 284 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 292 + ~#initio_template~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 300 + ~#initio_template~0.offset, 8);call write~init~int(0, ~#initio_template~0.base, 308 + ~#initio_template~0.offset, 8);call write~init~int(0, ~#initio_template~0.base, 316 + ~#initio_template~0.offset, 4);call write~init~$Pointer$(0, 0, ~#initio_template~0.base, 320 + ~#initio_template~0.offset, 8);call write~init~int(0, ~#initio_template~0.base, 328 + ~#initio_template~0.offset, 1);~#initio_pci_tbl~0.base, ~#initio_pci_tbl~0.offset := 26, 0;call #Ultimate.allocInit(192, 26);call write~init~int(4353, ~#initio_pci_tbl~0.base, ~#initio_pci_tbl~0.offset, 4);call write~init~int(38144, ~#initio_pci_tbl~0.base, 4 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 8 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 12 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 16 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 20 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 24 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(4353, ~#initio_pci_tbl~0.base, 32 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(37888, ~#initio_pci_tbl~0.base, 36 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 40 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 44 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 48 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 52 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 56 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(4353, ~#initio_pci_tbl~0.base, 64 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(37889, ~#initio_pci_tbl~0.base, 68 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 72 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 76 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 80 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 84 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 88 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(4353, ~#initio_pci_tbl~0.base, 96 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(2, ~#initio_pci_tbl~0.base, 100 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 104 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 108 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 112 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 116 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 120 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(4938, ~#initio_pci_tbl~0.base, 128 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(2, ~#initio_pci_tbl~0.base, 132 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 136 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(4294967295, ~#initio_pci_tbl~0.base, 140 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 144 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 148 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 152 + ~#initio_pci_tbl~0.offset, 8);call write~init~int(0, ~#initio_pci_tbl~0.base, 160 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 164 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 168 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 172 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 176 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 180 + ~#initio_pci_tbl~0.offset, 4);call write~init~int(0, ~#initio_pci_tbl~0.base, 184 + ~#initio_pci_tbl~0.offset, 8);~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[0 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[1 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[2 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[3 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[4 := 0];~__mod_pci__initio_pci_tbl_device_table~0.vendor := ~__mod_pci__initio_pci_tbl_device_table~0.vendor[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.device := ~__mod_pci__initio_pci_tbl_device_table~0.device[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subvendor := ~__mod_pci__initio_pci_tbl_device_table~0.subvendor[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.subdevice := ~__mod_pci__initio_pci_tbl_device_table~0.subdevice[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class := ~__mod_pci__initio_pci_tbl_device_table~0.class[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.class_mask := ~__mod_pci__initio_pci_tbl_device_table~0.class_mask[5 := 0];~__mod_pci__initio_pci_tbl_device_table~0.driver_data := ~__mod_pci__initio_pci_tbl_device_table~0.driver_data[5 := 0];~#initio_pci_driver~0.base, ~#initio_pci_driver~0.offset := 27, 0;call #Ultimate.allocInit(305, 27);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 8 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(20, 0, ~#initio_pci_driver~0.base, 16 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(~#initio_pci_tbl~0.base, ~#initio_pci_tbl~0.offset, ~#initio_pci_driver~0.base, 24 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~initio_probe_one.base, #funAddr~initio_probe_one.offset, ~#initio_pci_driver~0.base, 32 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~initio_remove_one.base, #funAddr~initio_remove_one.offset, ~#initio_pci_driver~0.base, 40 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 48 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 56 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 64 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 72 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 80 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 88 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 96 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 104 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 112 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 120 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 128 + ~#initio_pci_driver~0.offset, 8);call write~init~int(0, ~#initio_pci_driver~0.base, 136 + ~#initio_pci_driver~0.offset, 1);call write~init~int(0, ~#initio_pci_driver~0.base, 137 + ~#initio_pci_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 141 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 149 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 157 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 165 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 173 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 181 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 189 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 197 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 205 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 213 + ~#initio_pci_driver~0.offset, 8);call write~init~int(0, ~#initio_pci_driver~0.base, 221 + ~#initio_pci_driver~0.offset, 4);call write~init~int(0, ~#initio_pci_driver~0.base, 225 + ~#initio_pci_driver~0.offset, 4);call write~init~int(0, ~#initio_pci_driver~0.base, 229 + ~#initio_pci_driver~0.offset, 4);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 233 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 241 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 249 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 257 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 265 + ~#initio_pci_driver~0.offset, 8);call write~init~int(0, ~#initio_pci_driver~0.base, 273 + ~#initio_pci_driver~0.offset, 4);call write~init~int(0, ~#initio_pci_driver~0.base, 277 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 289 + ~#initio_pci_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#initio_pci_driver~0.base, 297 + ~#initio_pci_driver~0.offset, 8);~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_spin~0 := 0; {14431#true} is VALID [2022-02-20 22:33:09,021 INFO L290 TraceCheckUtils]: 1: Hoare triple {14431#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret1102#1.base, main_#t~ret1102#1.offset, main_#t~ret1103#1.base, main_#t~ret1103#1.offset, main_#t~ret1104#1.base, main_#t~ret1104#1.offset, main_#t~ret1105#1.base, main_#t~ret1105#1.offset, main_#t~ret1106#1.base, main_#t~ret1106#1.offset, main_#t~ret1107#1.base, main_#t~ret1107#1.offset, main_#t~nondet1108#1, main_#t~switch1109#1, main_#t~nondet1110#1, main_#t~switch1111#1, main_#t~ret1112#1, main_#t~nondet1113#1, main_#t~switch1114#1, main_#t~mem1115#1, main_#t~ret1116#1, main_#t~ret1117#1, main_#t~ret1118#1, main_#t~nondet1119#1, main_#t~switch1120#1, main_#t~ret1121#1, main_#t~ret1122#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~65#1.base, main_~tmp~65#1.offset, main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset, main_~tmp___0~35#1.base, main_~tmp___0~35#1.offset, main_~#ldvarg3~0#1.base, main_~#ldvarg3~0#1.offset, main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset, main_~tmp___1~22#1.base, main_~tmp___1~22#1.offset, main_~ldvarg2~0#1.base, main_~ldvarg2~0#1.offset, main_~ldvarg5~0#1.base, main_~ldvarg5~0#1.offset, main_~tmp___3~12#1.base, main_~tmp___3~12#1.offset, main_~tmp___4~9#1, main_~tmp___5~7#1, main_~tmp___6~5#1, main_~tmp___7~4#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~65#1.base, main_~tmp~65#1.offset;havoc main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset;havoc main_~tmp___0~35#1.base, main_~tmp___0~35#1.offset;call main_~#ldvarg3~0#1.base, main_~#ldvarg3~0#1.offset := #Ultimate.allocOnStack(8);havoc main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset;havoc main_~tmp___1~22#1.base, main_~tmp___1~22#1.offset;havoc main_~ldvarg2~0#1.base, main_~ldvarg2~0#1.offset;havoc main_~ldvarg5~0#1.base, main_~ldvarg5~0#1.offset;havoc main_~tmp___3~12#1.base, main_~tmp___3~12#1.offset;havoc main_~tmp___4~9#1;havoc main_~tmp___5~7#1;havoc main_~tmp___6~5#1;havoc main_~tmp___7~4#1; {14431#true} is VALID [2022-02-20 22:33:09,022 INFO L272 TraceCheckUtils]: 2: Hoare triple {14431#true} call main_#t~ret1102#1.base, main_#t~ret1102#1.offset := ldv_init_zalloc(4); {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:33:09,022 INFO L290 TraceCheckUtils]: 3: Hoare triple {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {14431#true} is VALID [2022-02-20 22:33:09,022 INFO L272 TraceCheckUtils]: 4: Hoare triple {14431#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {14518#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:33:09,022 INFO L290 TraceCheckUtils]: 5: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:09,023 INFO L290 TraceCheckUtils]: 6: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,023 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:09,023 INFO L290 TraceCheckUtils]: 8: Hoare triple {14431#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14431#true} is VALID [2022-02-20 22:33:09,023 INFO L272 TraceCheckUtils]: 9: Hoare triple {14431#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14431#true} is VALID [2022-02-20 22:33:09,023 INFO L290 TraceCheckUtils]: 10: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:09,023 INFO L290 TraceCheckUtils]: 11: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:09,023 INFO L290 TraceCheckUtils]: 12: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,023 INFO L284 TraceCheckUtils]: 13: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:09,024 INFO L290 TraceCheckUtils]: 14: Hoare triple {14431#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14431#true} is VALID [2022-02-20 22:33:09,024 INFO L290 TraceCheckUtils]: 15: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,024 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {14431#true} {14431#true} #4638#return; {14431#true} is VALID [2022-02-20 22:33:09,024 INFO L290 TraceCheckUtils]: 17: Hoare triple {14431#true} main_~tmp~65#1.base, main_~tmp~65#1.offset := main_#t~ret1102#1.base, main_#t~ret1102#1.offset;havoc main_#t~ret1102#1.base, main_#t~ret1102#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~65#1.base, main_~tmp~65#1.offset; {14431#true} is VALID [2022-02-20 22:33:09,024 INFO L272 TraceCheckUtils]: 18: Hoare triple {14431#true} call main_#t~ret1103#1.base, main_#t~ret1103#1.offset := ldv_init_zalloc(480); {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:33:09,024 INFO L290 TraceCheckUtils]: 19: Hoare triple {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {14431#true} is VALID [2022-02-20 22:33:09,025 INFO L272 TraceCheckUtils]: 20: Hoare triple {14431#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {14518#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:33:09,025 INFO L290 TraceCheckUtils]: 21: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:09,025 INFO L290 TraceCheckUtils]: 22: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,025 INFO L284 TraceCheckUtils]: 23: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:09,025 INFO L290 TraceCheckUtils]: 24: Hoare triple {14431#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14431#true} is VALID [2022-02-20 22:33:09,026 INFO L272 TraceCheckUtils]: 25: Hoare triple {14431#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14431#true} is VALID [2022-02-20 22:33:09,026 INFO L290 TraceCheckUtils]: 26: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:09,027 INFO L290 TraceCheckUtils]: 27: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:09,027 INFO L290 TraceCheckUtils]: 28: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,027 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:09,029 INFO L290 TraceCheckUtils]: 30: Hoare triple {14431#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14431#true} is VALID [2022-02-20 22:33:09,031 INFO L290 TraceCheckUtils]: 31: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,031 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {14431#true} {14431#true} #4640#return; {14431#true} is VALID [2022-02-20 22:33:09,031 INFO L290 TraceCheckUtils]: 33: Hoare triple {14431#true} main_~tmp___0~35#1.base, main_~tmp___0~35#1.offset := main_#t~ret1103#1.base, main_#t~ret1103#1.offset;havoc main_#t~ret1103#1.base, main_#t~ret1103#1.offset;main_~ldvarg4~0#1.base, main_~ldvarg4~0#1.offset := main_~tmp___0~35#1.base, main_~tmp___0~35#1.offset; {14431#true} is VALID [2022-02-20 22:33:09,031 INFO L272 TraceCheckUtils]: 34: Hoare triple {14431#true} call main_#t~ret1104#1.base, main_#t~ret1104#1.offset := ldv_init_zalloc(3816); {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:33:09,032 INFO L290 TraceCheckUtils]: 35: Hoare triple {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {14431#true} is VALID [2022-02-20 22:33:09,033 INFO L272 TraceCheckUtils]: 36: Hoare triple {14431#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {14518#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:33:09,033 INFO L290 TraceCheckUtils]: 37: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:09,033 INFO L290 TraceCheckUtils]: 38: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,033 INFO L284 TraceCheckUtils]: 39: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:09,034 INFO L290 TraceCheckUtils]: 40: Hoare triple {14431#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14431#true} is VALID [2022-02-20 22:33:09,035 INFO L272 TraceCheckUtils]: 41: Hoare triple {14431#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14431#true} is VALID [2022-02-20 22:33:09,037 INFO L290 TraceCheckUtils]: 42: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:09,038 INFO L290 TraceCheckUtils]: 43: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:09,038 INFO L290 TraceCheckUtils]: 44: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,038 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:09,038 INFO L290 TraceCheckUtils]: 46: Hoare triple {14431#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14431#true} is VALID [2022-02-20 22:33:09,038 INFO L290 TraceCheckUtils]: 47: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,039 INFO L284 TraceCheckUtils]: 48: Hoare quadruple {14431#true} {14431#true} #4642#return; {14431#true} is VALID [2022-02-20 22:33:09,039 INFO L290 TraceCheckUtils]: 49: Hoare triple {14431#true} main_~tmp___1~22#1.base, main_~tmp___1~22#1.offset := main_#t~ret1104#1.base, main_#t~ret1104#1.offset;havoc main_#t~ret1104#1.base, main_#t~ret1104#1.offset;main_~ldvarg0~0#1.base, main_~ldvarg0~0#1.offset := main_~tmp___1~22#1.base, main_~tmp___1~22#1.offset; {14431#true} is VALID [2022-02-20 22:33:09,039 INFO L272 TraceCheckUtils]: 50: Hoare triple {14431#true} call main_#t~ret1105#1.base, main_#t~ret1105#1.offset := ldv_malloc(3314); {14533#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:33:09,039 INFO L290 TraceCheckUtils]: 51: Hoare triple {14533#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {14431#true} is VALID [2022-02-20 22:33:09,039 INFO L290 TraceCheckUtils]: 52: Hoare triple {14431#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {14431#true} is VALID [2022-02-20 22:33:09,039 INFO L290 TraceCheckUtils]: 53: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,040 INFO L284 TraceCheckUtils]: 54: Hoare quadruple {14431#true} {14431#true} #4644#return; {14431#true} is VALID [2022-02-20 22:33:09,040 INFO L290 TraceCheckUtils]: 55: Hoare triple {14431#true} main_~ldvarg2~0#1.base, main_~ldvarg2~0#1.offset := main_#t~ret1105#1.base, main_#t~ret1105#1.offset;havoc main_#t~ret1105#1.base, main_#t~ret1105#1.offset; {14431#true} is VALID [2022-02-20 22:33:09,040 INFO L272 TraceCheckUtils]: 56: Hoare triple {14431#true} call main_#t~ret1106#1.base, main_#t~ret1106#1.offset := ldv_init_zalloc(32); {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:33:09,040 INFO L290 TraceCheckUtils]: 57: Hoare triple {14510#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~2.base, ~p~2.offset;havoc ~tmp~2.base, ~tmp~2.offset;call #t~malloc12.base, #t~malloc12.offset := #Ultimate.allocOnHeap(~size); {14431#true} is VALID [2022-02-20 22:33:09,041 INFO L272 TraceCheckUtils]: 58: Hoare triple {14431#true} call #Ultimate.meminit(#t~malloc12.base, #t~malloc12.offset, 1, ~size, ~size); {14518#(= |#memory_int| |old(#memory_int)|)} is VALID [2022-02-20 22:33:09,041 INFO L290 TraceCheckUtils]: 59: Hoare triple {14518#(= |#memory_int| |old(#memory_int)|)} #memory_int := ~initToZeroAtPointerBaseAddress~int(#memory_int, #ptr.base); {14431#true} is VALID [2022-02-20 22:33:09,041 INFO L290 TraceCheckUtils]: 60: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,041 INFO L284 TraceCheckUtils]: 61: Hoare quadruple {14431#true} {14431#true} #4548#return; {14431#true} is VALID [2022-02-20 22:33:09,041 INFO L290 TraceCheckUtils]: 62: Hoare triple {14431#true} ~tmp~2.base, ~tmp~2.offset := #t~malloc12.base, #t~malloc12.offset;~p~2.base, ~p~2.offset := ~tmp~2.base, ~tmp~2.offset; {14431#true} is VALID [2022-02-20 22:33:09,041 INFO L272 TraceCheckUtils]: 63: Hoare triple {14431#true} call assume_abort_if_not((if 0 != (~p~2.base + ~p~2.offset) % 18446744073709551616 then 1 else 0)); {14431#true} is VALID [2022-02-20 22:33:09,041 INFO L290 TraceCheckUtils]: 64: Hoare triple {14431#true} ~cond := #in~cond; {14431#true} is VALID [2022-02-20 22:33:09,042 INFO L290 TraceCheckUtils]: 65: Hoare triple {14431#true} assume !(0 == ~cond); {14431#true} is VALID [2022-02-20 22:33:09,042 INFO L290 TraceCheckUtils]: 66: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,042 INFO L284 TraceCheckUtils]: 67: Hoare quadruple {14431#true} {14431#true} #4550#return; {14431#true} is VALID [2022-02-20 22:33:09,042 INFO L290 TraceCheckUtils]: 68: Hoare triple {14431#true} #res.base, #res.offset := ~p~2.base, ~p~2.offset; {14431#true} is VALID [2022-02-20 22:33:09,042 INFO L290 TraceCheckUtils]: 69: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,047 INFO L284 TraceCheckUtils]: 70: Hoare quadruple {14431#true} {14431#true} #4646#return; {14431#true} is VALID [2022-02-20 22:33:09,047 INFO L290 TraceCheckUtils]: 71: Hoare triple {14431#true} main_~tmp___3~12#1.base, main_~tmp___3~12#1.offset := main_#t~ret1106#1.base, main_#t~ret1106#1.offset;havoc main_#t~ret1106#1.base, main_#t~ret1106#1.offset;main_~ldvarg5~0#1.base, main_~ldvarg5~0#1.offset := main_~tmp___3~12#1.base, main_~tmp___3~12#1.offset;assume { :begin_inline_ldv_initialize } true; {14431#true} is VALID [2022-02-20 22:33:09,047 INFO L290 TraceCheckUtils]: 72: Hoare triple {14431#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_memset } true;ldv_memset_#in~s#1.base, ldv_memset_#in~s#1.offset, ldv_memset_#in~c#1, ldv_memset_#in~n#1 := main_~#ldvarg3~0#1.base, main_~#ldvarg3~0#1.offset, 0, 8;havoc ldv_memset_#res#1.base, ldv_memset_#res#1.offset;havoc ldv_memset_#t~memset~res13#1.base, ldv_memset_#t~memset~res13#1.offset, ldv_memset_~s#1.base, ldv_memset_~s#1.offset, ldv_memset_~c#1, ldv_memset_~n#1, ldv_memset_~tmp~3#1.base, ldv_memset_~tmp~3#1.offset;ldv_memset_~s#1.base, ldv_memset_~s#1.offset := ldv_memset_#in~s#1.base, ldv_memset_#in~s#1.offset;ldv_memset_~c#1 := ldv_memset_#in~c#1;ldv_memset_~n#1 := ldv_memset_#in~n#1;havoc ldv_memset_~tmp~3#1.base, ldv_memset_~tmp~3#1.offset; {14431#true} is VALID [2022-02-20 22:33:09,048 INFO L272 TraceCheckUtils]: 73: Hoare triple {14431#true} call ldv_memset_#t~memset~res13#1.base, ldv_memset_#t~memset~res13#1.offset := #Ultimate.C_memset(ldv_memset_~s#1.base, ldv_memset_~s#1.offset, ldv_memset_~c#1, ldv_memset_~n#1); {14541#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:33:09,048 INFO L290 TraceCheckUtils]: 74: Hoare triple {14541#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} #t~loopctr1148 := 0; {14431#true} is VALID [2022-02-20 22:33:09,048 INFO L290 TraceCheckUtils]: 75: Hoare triple {14431#true} assume !(#t~loopctr1148 % 18446744073709551616 < #amount % 18446744073709551616); {14431#true} is VALID [2022-02-20 22:33:09,048 INFO L290 TraceCheckUtils]: 76: Hoare triple {14431#true} assume #res.base == #ptr.base && #res.offset == #ptr.offset; {14431#true} is VALID [2022-02-20 22:33:09,049 INFO L284 TraceCheckUtils]: 77: Hoare quadruple {14431#true} {14431#true} #4648#return; {14431#true} is VALID [2022-02-20 22:33:09,049 INFO L290 TraceCheckUtils]: 78: Hoare triple {14431#true} ldv_memset_~tmp~3#1.base, ldv_memset_~tmp~3#1.offset := ldv_memset_~s#1.base, ldv_memset_~s#1.offset;havoc ldv_memset_#t~memset~res13#1.base, ldv_memset_#t~memset~res13#1.offset;ldv_memset_#res#1.base, ldv_memset_#res#1.offset := ldv_memset_~tmp~3#1.base, ldv_memset_~tmp~3#1.offset; {14431#true} is VALID [2022-02-20 22:33:09,049 INFO L290 TraceCheckUtils]: 79: Hoare triple {14431#true} main_#t~ret1107#1.base, main_#t~ret1107#1.offset := ldv_memset_#res#1.base, ldv_memset_#res#1.offset;assume { :end_inline_ldv_memset } true;havoc main_#t~ret1107#1.base, main_#t~ret1107#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {14497#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:33:09,049 INFO L290 TraceCheckUtils]: 80: Hoare triple {14497#(= ~ldv_state_variable_2~0 0)} assume -2147483648 <= main_#t~nondet1108#1 && main_#t~nondet1108#1 <= 2147483647;main_~tmp___4~9#1 := main_#t~nondet1108#1;havoc main_#t~nondet1108#1;main_#t~switch1109#1 := 0 == main_~tmp___4~9#1; {14497#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:33:09,050 INFO L290 TraceCheckUtils]: 81: Hoare triple {14497#(= ~ldv_state_variable_2~0 0)} assume !main_#t~switch1109#1;main_#t~switch1109#1 := main_#t~switch1109#1 || 1 == main_~tmp___4~9#1; {14497#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:33:09,050 INFO L290 TraceCheckUtils]: 82: Hoare triple {14497#(= ~ldv_state_variable_2~0 0)} assume !main_#t~switch1109#1;main_#t~switch1109#1 := main_#t~switch1109#1 || 2 == main_~tmp___4~9#1; {14497#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:33:09,050 INFO L290 TraceCheckUtils]: 83: Hoare triple {14497#(= ~ldv_state_variable_2~0 0)} assume !main_#t~switch1109#1;main_#t~switch1109#1 := main_#t~switch1109#1 || 3 == main_~tmp___4~9#1; {14497#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:33:09,050 INFO L290 TraceCheckUtils]: 84: Hoare triple {14497#(= ~ldv_state_variable_2~0 0)} assume main_#t~switch1109#1; {14497#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:33:09,051 INFO L290 TraceCheckUtils]: 85: Hoare triple {14497#(= ~ldv_state_variable_2~0 0)} assume 0 != ~ldv_state_variable_2~0;assume -2147483648 <= main_#t~nondet1119#1 && main_#t~nondet1119#1 <= 2147483647;main_~tmp___7~4#1 := main_#t~nondet1119#1;havoc main_#t~nondet1119#1;main_#t~switch1120#1 := 0 == main_~tmp___7~4#1; {14432#false} is VALID [2022-02-20 22:33:09,051 INFO L290 TraceCheckUtils]: 86: Hoare triple {14432#false} assume main_#t~switch1120#1; {14432#false} is VALID [2022-02-20 22:33:09,051 INFO L290 TraceCheckUtils]: 87: Hoare triple {14432#false} assume 1 == ~ldv_state_variable_2~0;assume { :begin_inline_initio_probe_one } true;initio_probe_one_#in~pdev#1.base, initio_probe_one_#in~pdev#1.offset, initio_probe_one_#in~id#1.base, initio_probe_one_#in~id#1.offset := ~initio_pci_driver_group1~0.base, ~initio_pci_driver_group1~0.offset, main_~ldvarg5~0#1.base, main_~ldvarg5~0#1.offset;havoc initio_probe_one_#res#1;havoc initio_probe_one_#t~ret1050#1, initio_probe_one_#t~ret1051#1, initio_probe_one_#t~mem1053#1, initio_probe_one_#t~mem1055#1, initio_probe_one_#t~mem1056#1, initio_probe_one_#t~ret1057#1, initio_probe_one_#t~nondet1058#1, initio_probe_one_#t~ret1059#1.base, initio_probe_one_#t~ret1059#1.offset, initio_probe_one_#t~nondet1060#1, initio_probe_one_#t~memset~res1061#1.base, initio_probe_one_#t~memset~res1061#1.offset, initio_probe_one_#t~mem1062#1, initio_probe_one_#t~mem1063#1, initio_probe_one_#t~ret1064#1.base, initio_probe_one_#t~ret1064#1.offset, initio_probe_one_#t~nondet1065#1, initio_probe_one_#t~mem1066#1, initio_probe_one_#t~ret1067#1.base, initio_probe_one_#t~ret1067#1.offset, initio_probe_one_#t~nondet1068#1, initio_probe_one_#t~ret1069#1.base, initio_probe_one_#t~ret1069#1.offset, initio_probe_one_#t~ret1070#1.base, initio_probe_one_#t~ret1070#1.offset, initio_probe_one_#t~ret1071#1.base, initio_probe_one_#t~ret1071#1.offset, initio_probe_one_#t~mem1072#1, initio_probe_one_#t~mem1073#1, initio_probe_one_#t~mem1074#1, initio_probe_one_#t~mem1075#1, initio_probe_one_#t~mem1076#1, initio_probe_one_#t~mem1077#1, initio_probe_one_#t~mem1078#1, initio_probe_one_#t~ret1079#1, initio_probe_one_#t~nondet1080#1, initio_probe_one_#t~mem1081#1, initio_probe_one_#t~ret1082#1, initio_probe_one_#t~mem1083#1, initio_probe_one_#t~mem1084#1.base, initio_probe_one_#t~mem1084#1.offset, initio_probe_one_#t~mem1085#1, initio_probe_one_#t~nondet1054#1, initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset, initio_probe_one_~id#1.base, initio_probe_one_~id#1.offset, initio_probe_one_~shost~0#1.base, initio_probe_one_~shost~0#1.offset, initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset, initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, initio_probe_one_~bios_seg~0#1, initio_probe_one_~scb~21#1.base, initio_probe_one_~scb~21#1.offset, initio_probe_one_~tmp~59#1.base, initio_probe_one_~tmp~59#1.offset, initio_probe_one_~prev~5#1.base, initio_probe_one_~prev~5#1.offset, initio_probe_one_~num_scb~0#1, initio_probe_one_~i~16#1, initio_probe_one_~error~0#1, initio_probe_one_~tmp___0~33#1, initio_probe_one_~tmp___1~21#1.base, initio_probe_one_~tmp___1~21#1.offset, initio_probe_one_~tmp___2~15#1.base, initio_probe_one_~tmp___2~15#1.offset, initio_probe_one_~#__key~0#1.base, initio_probe_one_~#__key~0#1.offset, initio_probe_one_~#__key___0~0#1.base, initio_probe_one_~#__key___0~0#1.offset, initio_probe_one_~tmp___3~11#1.base, initio_probe_one_~tmp___3~11#1.offset;initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset := initio_probe_one_#in~pdev#1.base, initio_probe_one_#in~pdev#1.offset;initio_probe_one_~id#1.base, initio_probe_one_~id#1.offset := initio_probe_one_#in~id#1.base, initio_probe_one_#in~id#1.offset;havoc initio_probe_one_~shost~0#1.base, initio_probe_one_~shost~0#1.offset;havoc initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset;call initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset := #Ultimate.allocOnStack(4);havoc initio_probe_one_~bios_seg~0#1;havoc initio_probe_one_~scb~21#1.base, initio_probe_one_~scb~21#1.offset;havoc initio_probe_one_~tmp~59#1.base, initio_probe_one_~tmp~59#1.offset;havoc initio_probe_one_~prev~5#1.base, initio_probe_one_~prev~5#1.offset;havoc initio_probe_one_~num_scb~0#1;havoc initio_probe_one_~i~16#1;havoc initio_probe_one_~error~0#1;havoc initio_probe_one_~tmp___0~33#1;havoc initio_probe_one_~tmp___1~21#1.base, initio_probe_one_~tmp___1~21#1.offset;havoc initio_probe_one_~tmp___2~15#1.base, initio_probe_one_~tmp___2~15#1.offset;call initio_probe_one_~#__key~0#1.base, initio_probe_one_~#__key~0#1.offset := #Ultimate.allocOnStack(8);call initio_probe_one_~#__key___0~0#1.base, initio_probe_one_~#__key___0~0#1.offset := #Ultimate.allocOnStack(8);havoc initio_probe_one_~tmp___3~11#1.base, initio_probe_one_~tmp___3~11#1.offset;initio_probe_one_~prev~5#1.base, initio_probe_one_~prev~5#1.offset := 0, 0;assume { :begin_inline_pci_enable_device } true;pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset := initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset;havoc pci_enable_device_#res#1;havoc pci_enable_device_#t~nondet1139#1, pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset;pci_enable_device_~arg0#1.base, pci_enable_device_~arg0#1.offset := pci_enable_device_#in~arg0#1.base, pci_enable_device_#in~arg0#1.offset;assume -2147483648 <= pci_enable_device_#t~nondet1139#1 && pci_enable_device_#t~nondet1139#1 <= 2147483647;pci_enable_device_#res#1 := pci_enable_device_#t~nondet1139#1;havoc pci_enable_device_#t~nondet1139#1; {14432#false} is VALID [2022-02-20 22:33:09,051 INFO L290 TraceCheckUtils]: 88: Hoare triple {14432#false} initio_probe_one_#t~ret1050#1 := pci_enable_device_#res#1;assume { :end_inline_pci_enable_device } true;assume -2147483648 <= initio_probe_one_#t~ret1050#1 && initio_probe_one_#t~ret1050#1 <= 2147483647;initio_probe_one_~error~0#1 := initio_probe_one_#t~ret1050#1;havoc initio_probe_one_#t~ret1050#1; {14432#false} is VALID [2022-02-20 22:33:09,051 INFO L290 TraceCheckUtils]: 89: Hoare triple {14432#false} assume !(0 != initio_probe_one_~error~0#1);assume { :begin_inline_pci_read_config_dword } true;pci_read_config_dword_#in~dev#1.base, pci_read_config_dword_#in~dev#1.offset, pci_read_config_dword_#in~where#1, pci_read_config_dword_#in~val#1.base, pci_read_config_dword_#in~val#1.offset := initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset, 68, initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset;havoc pci_read_config_dword_#res#1;havoc pci_read_config_dword_#t~mem47#1.base, pci_read_config_dword_#t~mem47#1.offset, pci_read_config_dword_#t~mem48#1, pci_read_config_dword_#t~ret49#1, pci_read_config_dword_~dev#1.base, pci_read_config_dword_~dev#1.offset, pci_read_config_dword_~where#1, pci_read_config_dword_~val#1.base, pci_read_config_dword_~val#1.offset, pci_read_config_dword_~tmp~6#1;pci_read_config_dword_~dev#1.base, pci_read_config_dword_~dev#1.offset := pci_read_config_dword_#in~dev#1.base, pci_read_config_dword_#in~dev#1.offset;pci_read_config_dword_~where#1 := pci_read_config_dword_#in~where#1;pci_read_config_dword_~val#1.base, pci_read_config_dword_~val#1.offset := pci_read_config_dword_#in~val#1.base, pci_read_config_dword_#in~val#1.offset;havoc pci_read_config_dword_~tmp~6#1;call pci_read_config_dword_#t~mem47#1.base, pci_read_config_dword_#t~mem47#1.offset := read~$Pointer$(pci_read_config_dword_~dev#1.base, 16 + pci_read_config_dword_~dev#1.offset, 8);call pci_read_config_dword_#t~mem48#1 := read~int(pci_read_config_dword_~dev#1.base, 56 + pci_read_config_dword_~dev#1.offset, 4);assume { :begin_inline_pci_bus_read_config_dword } true;pci_bus_read_config_dword_#in~arg0#1.base, pci_bus_read_config_dword_#in~arg0#1.offset, pci_bus_read_config_dword_#in~arg1#1, pci_bus_read_config_dword_#in~arg2#1, pci_bus_read_config_dword_#in~arg3#1.base, pci_bus_read_config_dword_#in~arg3#1.offset := pci_read_config_dword_#t~mem47#1.base, pci_read_config_dword_#t~mem47#1.offset, pci_read_config_dword_#t~mem48#1, pci_read_config_dword_~where#1, pci_read_config_dword_~val#1.base, pci_read_config_dword_~val#1.offset;havoc pci_bus_read_config_dword_#res#1;havoc pci_bus_read_config_dword_#t~nondet1138#1, pci_bus_read_config_dword_~arg0#1.base, pci_bus_read_config_dword_~arg0#1.offset, pci_bus_read_config_dword_~arg1#1, pci_bus_read_config_dword_~arg2#1, pci_bus_read_config_dword_~arg3#1.base, pci_bus_read_config_dword_~arg3#1.offset;pci_bus_read_config_dword_~arg0#1.base, pci_bus_read_config_dword_~arg0#1.offset := pci_bus_read_config_dword_#in~arg0#1.base, pci_bus_read_config_dword_#in~arg0#1.offset;pci_bus_read_config_dword_~arg1#1 := pci_bus_read_config_dword_#in~arg1#1;pci_bus_read_config_dword_~arg2#1 := pci_bus_read_config_dword_#in~arg2#1;pci_bus_read_config_dword_~arg3#1.base, pci_bus_read_config_dword_~arg3#1.offset := pci_bus_read_config_dword_#in~arg3#1.base, pci_bus_read_config_dword_#in~arg3#1.offset;assume -2147483648 <= pci_bus_read_config_dword_#t~nondet1138#1 && pci_bus_read_config_dword_#t~nondet1138#1 <= 2147483647;pci_bus_read_config_dword_#res#1 := pci_bus_read_config_dword_#t~nondet1138#1;havoc pci_bus_read_config_dword_#t~nondet1138#1; {14432#false} is VALID [2022-02-20 22:33:09,051 INFO L290 TraceCheckUtils]: 90: Hoare triple {14432#false} pci_read_config_dword_#t~ret49#1 := pci_bus_read_config_dword_#res#1;assume { :end_inline_pci_bus_read_config_dword } true;assume -2147483648 <= pci_read_config_dword_#t~ret49#1 && pci_read_config_dword_#t~ret49#1 <= 2147483647;pci_read_config_dword_~tmp~6#1 := pci_read_config_dword_#t~ret49#1;havoc pci_read_config_dword_#t~mem47#1.base, pci_read_config_dword_#t~mem47#1.offset;havoc pci_read_config_dword_#t~mem48#1;havoc pci_read_config_dword_#t~ret49#1;pci_read_config_dword_#res#1 := pci_read_config_dword_~tmp~6#1; {14432#false} is VALID [2022-02-20 22:33:09,051 INFO L290 TraceCheckUtils]: 91: Hoare triple {14432#false} initio_probe_one_#t~ret1051#1 := pci_read_config_dword_#res#1;assume { :end_inline_pci_read_config_dword } true;assume -2147483648 <= initio_probe_one_#t~ret1051#1 && initio_probe_one_#t~ret1051#1 <= 2147483647;havoc initio_probe_one_#t~ret1051#1;call initio_probe_one_#t~mem1053#1 := read~int(initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, 4); {14432#false} is VALID [2022-02-20 22:33:09,051 INFO L290 TraceCheckUtils]: 92: Hoare triple {14432#false} assume 0 == initio_probe_one_#t~mem1053#1 % 65536;initio_probe_one_~bios_seg~0#1 := 0; {14432#false} is VALID [2022-02-20 22:33:09,052 INFO L290 TraceCheckUtils]: 93: Hoare triple {14432#false} havoc initio_probe_one_#t~mem1053#1;call initio_probe_one_#t~mem1055#1 := read~int(initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, 4); {14432#false} is VALID [2022-02-20 22:33:09,052 INFO L290 TraceCheckUtils]: 94: Hoare triple {14432#false} assume 255 == (if 0 == initio_probe_one_#t~mem1055#1 then 0 else (if 1 == initio_probe_one_#t~mem1055#1 then 0 else ~bitwiseAnd(initio_probe_one_#t~mem1055#1, 65280))) / 256 % 4294967296;havoc initio_probe_one_#t~mem1055#1;call write~int(0, initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, 4); {14432#false} is VALID [2022-02-20 22:33:09,052 INFO L290 TraceCheckUtils]: 95: Hoare triple {14432#false} call initio_probe_one_#t~mem1056#1 := read~int(initio_probe_one_~#reg~0#1.base, initio_probe_one_~#reg~0#1.offset, 4);initio_probe_one_~bios_seg~0#1 := 256 * (initio_probe_one_~bios_seg~0#1 % 65536) + (if 0 == initio_probe_one_#t~mem1056#1 then 0 else (if 1 == initio_probe_one_#t~mem1056#1 then 0 else ~bitwiseAnd(initio_probe_one_#t~mem1056#1, 65280))) / 256 % 65536;havoc initio_probe_one_#t~mem1056#1;assume { :begin_inline_pci_set_dma_mask } true;pci_set_dma_mask_#in~dev#1.base, pci_set_dma_mask_#in~dev#1.offset, pci_set_dma_mask_#in~mask#1 := initio_probe_one_~pdev#1.base, initio_probe_one_~pdev#1.offset, 4294967295;havoc pci_set_dma_mask_#res#1;havoc pci_set_dma_mask_#t~ret100#1, pci_set_dma_mask_~dev#1.base, pci_set_dma_mask_~dev#1.offset, pci_set_dma_mask_~mask#1, pci_set_dma_mask_~tmp~10#1;pci_set_dma_mask_~dev#1.base, pci_set_dma_mask_~dev#1.offset := pci_set_dma_mask_#in~dev#1.base, pci_set_dma_mask_#in~dev#1.offset;pci_set_dma_mask_~mask#1 := pci_set_dma_mask_#in~mask#1;havoc pci_set_dma_mask_~tmp~10#1;assume { :begin_inline_dma_set_mask } true;dma_set_mask_#in~arg0#1.base, dma_set_mask_#in~arg0#1.offset, dma_set_mask_#in~arg1#1 := pci_set_dma_mask_~dev#1.base, 148 + pci_set_dma_mask_~dev#1.offset, pci_set_dma_mask_~mask#1;havoc dma_set_mask_#res#1;havoc dma_set_mask_#t~nondet1135#1, dma_set_mask_~arg0#1.base, dma_set_mask_~arg0#1.offset, dma_set_mask_~arg1#1;dma_set_mask_~arg0#1.base, dma_set_mask_~arg0#1.offset := dma_set_mask_#in~arg0#1.base, dma_set_mask_#in~arg0#1.offset;dma_set_mask_~arg1#1 := dma_set_mask_#in~arg1#1;assume -2147483648 <= dma_set_mask_#t~nondet1135#1 && dma_set_mask_#t~nondet1135#1 <= 2147483647;dma_set_mask_#res#1 := dma_set_mask_#t~nondet1135#1;havoc dma_set_mask_#t~nondet1135#1; {14432#false} is VALID [2022-02-20 22:33:09,052 INFO L290 TraceCheckUtils]: 96: Hoare triple {14432#false} pci_set_dma_mask_#t~ret100#1 := dma_set_mask_#res#1;assume { :end_inline_dma_set_mask } true;assume -2147483648 <= pci_set_dma_mask_#t~ret100#1 && pci_set_dma_mask_#t~ret100#1 <= 2147483647;pci_set_dma_mask_~tmp~10#1 := pci_set_dma_mask_#t~ret100#1;havoc pci_set_dma_mask_#t~ret100#1;pci_set_dma_mask_#res#1 := pci_set_dma_mask_~tmp~10#1; {14432#false} is VALID [2022-02-20 22:33:09,052 INFO L290 TraceCheckUtils]: 97: Hoare triple {14432#false} initio_probe_one_#t~ret1057#1 := pci_set_dma_mask_#res#1;assume { :end_inline_pci_set_dma_mask } true;assume -2147483648 <= initio_probe_one_#t~ret1057#1 && initio_probe_one_#t~ret1057#1 <= 2147483647;initio_probe_one_~tmp___0~33#1 := initio_probe_one_#t~ret1057#1;havoc initio_probe_one_#t~ret1057#1; {14432#false} is VALID [2022-02-20 22:33:09,052 INFO L290 TraceCheckUtils]: 98: Hoare triple {14432#false} assume !(0 != initio_probe_one_~tmp___0~33#1);assume { :begin_inline_ldv_scsi_host_alloc_25 } true;ldv_scsi_host_alloc_25_#in~sht#1.base, ldv_scsi_host_alloc_25_#in~sht#1.offset, ldv_scsi_host_alloc_25_#in~privsize#1 := ~#initio_template~0.base, ~#initio_template~0.offset, 464;havoc ldv_scsi_host_alloc_25_#res#1.base, ldv_scsi_host_alloc_25_#res#1.offset;havoc ldv_scsi_host_alloc_25_#t~ret1125#1.base, ldv_scsi_host_alloc_25_#t~ret1125#1.offset, ldv_scsi_host_alloc_25_~sht#1.base, ldv_scsi_host_alloc_25_~sht#1.offset, ldv_scsi_host_alloc_25_~privsize#1, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset, ldv_scsi_host_alloc_25_~tmp~68#1.base, ldv_scsi_host_alloc_25_~tmp~68#1.offset;ldv_scsi_host_alloc_25_~sht#1.base, ldv_scsi_host_alloc_25_~sht#1.offset := ldv_scsi_host_alloc_25_#in~sht#1.base, ldv_scsi_host_alloc_25_#in~sht#1.offset;ldv_scsi_host_alloc_25_~privsize#1 := ldv_scsi_host_alloc_25_#in~privsize#1;havoc ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset;havoc ldv_scsi_host_alloc_25_~tmp~68#1.base, ldv_scsi_host_alloc_25_~tmp~68#1.offset;assume { :begin_inline_scsi_host_alloc } true;scsi_host_alloc_#in~arg0#1.base, scsi_host_alloc_#in~arg0#1.offset, scsi_host_alloc_#in~arg1#1 := ldv_scsi_host_alloc_25_~sht#1.base, ldv_scsi_host_alloc_25_~sht#1.offset, ldv_scsi_host_alloc_25_~privsize#1;havoc scsi_host_alloc_#res#1.base, scsi_host_alloc_#res#1.offset;havoc scsi_host_alloc_#t~ret1144#1.base, scsi_host_alloc_#t~ret1144#1.offset, scsi_host_alloc_~arg0#1.base, scsi_host_alloc_~arg0#1.offset, scsi_host_alloc_~arg1#1;scsi_host_alloc_~arg0#1.base, scsi_host_alloc_~arg0#1.offset := scsi_host_alloc_#in~arg0#1.base, scsi_host_alloc_#in~arg0#1.offset;scsi_host_alloc_~arg1#1 := scsi_host_alloc_#in~arg1#1; {14432#false} is VALID [2022-02-20 22:33:09,052 INFO L272 TraceCheckUtils]: 99: Hoare triple {14432#false} call scsi_host_alloc_#t~ret1144#1.base, scsi_host_alloc_#t~ret1144#1.offset := ldv_malloc(3601); {14533#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:33:09,053 INFO L290 TraceCheckUtils]: 100: Hoare triple {14533#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {14431#true} is VALID [2022-02-20 22:33:09,053 INFO L290 TraceCheckUtils]: 101: Hoare triple {14431#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {14431#true} is VALID [2022-02-20 22:33:09,053 INFO L290 TraceCheckUtils]: 102: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,053 INFO L284 TraceCheckUtils]: 103: Hoare quadruple {14431#true} {14432#false} #4708#return; {14432#false} is VALID [2022-02-20 22:33:09,053 INFO L290 TraceCheckUtils]: 104: Hoare triple {14432#false} scsi_host_alloc_#res#1.base, scsi_host_alloc_#res#1.offset := scsi_host_alloc_#t~ret1144#1.base, scsi_host_alloc_#t~ret1144#1.offset;havoc scsi_host_alloc_#t~ret1144#1.base, scsi_host_alloc_#t~ret1144#1.offset; {14432#false} is VALID [2022-02-20 22:33:09,053 INFO L290 TraceCheckUtils]: 105: Hoare triple {14432#false} ldv_scsi_host_alloc_25_#t~ret1125#1.base, ldv_scsi_host_alloc_25_#t~ret1125#1.offset := scsi_host_alloc_#res#1.base, scsi_host_alloc_#res#1.offset;assume { :end_inline_scsi_host_alloc } true;ldv_scsi_host_alloc_25_~tmp~68#1.base, ldv_scsi_host_alloc_25_~tmp~68#1.offset := ldv_scsi_host_alloc_25_#t~ret1125#1.base, ldv_scsi_host_alloc_25_#t~ret1125#1.offset;havoc ldv_scsi_host_alloc_25_#t~ret1125#1.base, ldv_scsi_host_alloc_25_#t~ret1125#1.offset;ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset := ldv_scsi_host_alloc_25_~tmp~68#1.base, ldv_scsi_host_alloc_25_~tmp~68#1.offset; {14432#false} is VALID [2022-02-20 22:33:09,053 INFO L290 TraceCheckUtils]: 106: Hoare triple {14432#false} assume !(0 != (ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base + ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset) % 18446744073709551616); {14432#false} is VALID [2022-02-20 22:33:09,053 INFO L290 TraceCheckUtils]: 107: Hoare triple {14432#false} ldv_scsi_host_alloc_25_#res#1.base, ldv_scsi_host_alloc_25_#res#1.offset := ldv_scsi_host_alloc_25_~ldv_func_res~1#1.base, ldv_scsi_host_alloc_25_~ldv_func_res~1#1.offset; {14432#false} is VALID [2022-02-20 22:33:09,053 INFO L290 TraceCheckUtils]: 108: Hoare triple {14432#false} initio_probe_one_#t~ret1059#1.base, initio_probe_one_#t~ret1059#1.offset := ldv_scsi_host_alloc_25_#res#1.base, ldv_scsi_host_alloc_25_#res#1.offset;assume { :end_inline_ldv_scsi_host_alloc_25 } true;initio_probe_one_~shost~0#1.base, initio_probe_one_~shost~0#1.offset := initio_probe_one_#t~ret1059#1.base, initio_probe_one_#t~ret1059#1.offset;havoc initio_probe_one_#t~ret1059#1.base, initio_probe_one_#t~ret1059#1.offset; {14432#false} is VALID [2022-02-20 22:33:09,054 INFO L290 TraceCheckUtils]: 109: Hoare triple {14432#false} assume !(0 == (initio_probe_one_~shost~0#1.base + initio_probe_one_~shost~0#1.offset) % 18446744073709551616);initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset := initio_probe_one_~shost~0#1.base, 3601 + initio_probe_one_~shost~0#1.offset; {14432#false} is VALID [2022-02-20 22:33:09,054 INFO L272 TraceCheckUtils]: 110: Hoare triple {14432#false} call initio_probe_one_#t~memset~res1061#1.base, initio_probe_one_#t~memset~res1061#1.offset := #Ultimate.C_memset(initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset, 0, 464); {14541#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} is VALID [2022-02-20 22:33:09,054 INFO L290 TraceCheckUtils]: 111: Hoare triple {14541#(and (= |#memory_int| |old(#memory_int)|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|))} #t~loopctr1148 := 0; {14431#true} is VALID [2022-02-20 22:33:09,054 INFO L290 TraceCheckUtils]: 112: Hoare triple {14431#true} assume !(#t~loopctr1148 % 18446744073709551616 < #amount % 18446744073709551616); {14431#true} is VALID [2022-02-20 22:33:09,054 INFO L290 TraceCheckUtils]: 113: Hoare triple {14431#true} assume #res.base == #ptr.base && #res.offset == #ptr.offset; {14431#true} is VALID [2022-02-20 22:33:09,054 INFO L284 TraceCheckUtils]: 114: Hoare quadruple {14431#true} {14432#false} #4712#return; {14432#false} is VALID [2022-02-20 22:33:09,054 INFO L290 TraceCheckUtils]: 115: Hoare triple {14432#false} havoc initio_probe_one_#t~memset~res1061#1.base, initio_probe_one_#t~memset~res1061#1.offset;call initio_probe_one_#t~mem1062#1 := read~int(initio_probe_one_~pdev#1.base, 1493 + initio_probe_one_~pdev#1.offset, 8);call write~int(initio_probe_one_#t~mem1062#1, initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset, 2);havoc initio_probe_one_#t~mem1062#1;call write~int(initio_probe_one_~bios_seg~0#1, initio_probe_one_~host~4#1.base, 2 + initio_probe_one_~host~4#1.offset, 2);call initio_probe_one_#t~mem1063#1 := read~int(initio_probe_one_~host~4#1.base, initio_probe_one_~host~4#1.offset, 2);assume { :begin_inline___request_region } true;__request_region_#in~arg0#1.base, __request_region_#in~arg0#1.offset, __request_region_#in~arg1#1, __request_region_#in~arg2#1, __request_region_#in~arg3#1.base, __request_region_#in~arg3#1.offset, __request_region_#in~arg4#1 := ~#ioport_resource~0.base, ~#ioport_resource~0.offset, initio_probe_one_#t~mem1063#1 % 65536, 256, 13, 0, 0;havoc __request_region_#res#1.base, __request_region_#res#1.offset;havoc __request_region_#t~ret1134#1.base, __request_region_#t~ret1134#1.offset, __request_region_~arg0#1.base, __request_region_~arg0#1.offset, __request_region_~arg1#1, __request_region_~arg2#1, __request_region_~arg3#1.base, __request_region_~arg3#1.offset, __request_region_~arg4#1;__request_region_~arg0#1.base, __request_region_~arg0#1.offset := __request_region_#in~arg0#1.base, __request_region_#in~arg0#1.offset;__request_region_~arg1#1 := __request_region_#in~arg1#1;__request_region_~arg2#1 := __request_region_#in~arg2#1;__request_region_~arg3#1.base, __request_region_~arg3#1.offset := __request_region_#in~arg3#1.base, __request_region_#in~arg3#1.offset;__request_region_~arg4#1 := __request_region_#in~arg4#1; {14432#false} is VALID [2022-02-20 22:33:09,054 INFO L272 TraceCheckUtils]: 116: Hoare triple {14432#false} call __request_region_#t~ret1134#1.base, __request_region_#t~ret1134#1.offset := ldv_malloc(56); {14533#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:33:09,054 INFO L290 TraceCheckUtils]: 117: Hoare triple {14533#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet8 && #t~nondet8 <= 2147483647;~tmp___0~0 := #t~nondet8;havoc #t~nondet8; {14431#true} is VALID [2022-02-20 22:33:09,055 INFO L290 TraceCheckUtils]: 118: Hoare triple {14431#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {14431#true} is VALID [2022-02-20 22:33:09,055 INFO L290 TraceCheckUtils]: 119: Hoare triple {14431#true} assume true; {14431#true} is VALID [2022-02-20 22:33:09,055 INFO L284 TraceCheckUtils]: 120: Hoare quadruple {14431#true} {14432#false} #4714#return; {14432#false} is VALID [2022-02-20 22:33:09,055 INFO L290 TraceCheckUtils]: 121: Hoare triple {14432#false} __request_region_#res#1.base, __request_region_#res#1.offset := __request_region_#t~ret1134#1.base, __request_region_#t~ret1134#1.offset;havoc __request_region_#t~ret1134#1.base, __request_region_#t~ret1134#1.offset; {14432#false} is VALID [2022-02-20 22:33:09,055 INFO L290 TraceCheckUtils]: 122: Hoare triple {14432#false} initio_probe_one_#t~ret1064#1.base, initio_probe_one_#t~ret1064#1.offset := __request_region_#res#1.base, __request_region_#res#1.offset;assume { :end_inline___request_region } true;initio_probe_one_~tmp___1~21#1.base, initio_probe_one_~tmp___1~21#1.offset := initio_probe_one_#t~ret1064#1.base, initio_probe_one_#t~ret1064#1.offset;havoc initio_probe_one_#t~mem1063#1;havoc initio_probe_one_#t~ret1064#1.base, initio_probe_one_#t~ret1064#1.offset; {14432#false} is VALID [2022-02-20 22:33:09,055 INFO L290 TraceCheckUtils]: 123: Hoare triple {14432#false} assume !(0 == (initio_probe_one_~tmp___1~21#1.base + initio_probe_one_~tmp___1~21#1.offset) % 18446744073709551616); {14432#false} is VALID [2022-02-20 22:33:09,055 INFO L290 TraceCheckUtils]: 124: Hoare triple {14432#false} assume 0 != ~initio_tag_enable~0;initio_probe_one_~num_scb~0#1 := 32; {14432#false} is VALID [2022-02-20 22:33:09,055 INFO L290 TraceCheckUtils]: 125: Hoare triple {14432#false} assume initio_probe_one_~num_scb~0#1 > 18; {14432#false} is VALID [2022-02-20 22:33:09,055 INFO L290 TraceCheckUtils]: 126: Hoare triple {14432#false} initio_probe_one_~i~16#1 := (if 352 * initio_probe_one_~num_scb~0#1 % 4294967296 % 4294967296 <= 2147483647 then 352 * initio_probe_one_~num_scb~0#1 % 4294967296 % 4294967296 else 352 * initio_probe_one_~num_scb~0#1 % 4294967296 % 4294967296 - 4294967296);assume { :begin_inline_kzalloc } true;kzalloc_#in~size#1, kzalloc_#in~flags#1 := initio_probe_one_~i~16#1, 1;havoc kzalloc_#res#1.base, kzalloc_#res#1.offset;havoc kzalloc_#t~ret1123#1.base, kzalloc_#t~ret1123#1.offset, kzalloc_~size#1, kzalloc_~flags#1, kzalloc_~tmp~66#1.base, kzalloc_~tmp~66#1.offset;kzalloc_~size#1 := kzalloc_#in~size#1;kzalloc_~flags#1 := kzalloc_#in~flags#1;havoc kzalloc_~tmp~66#1.base, kzalloc_~tmp~66#1.offset;assume { :begin_inline_ldv_check_alloc_flags } true;ldv_check_alloc_flags_#in~flags#1 := kzalloc_~flags#1;havoc ldv_check_alloc_flags_~flags#1;ldv_check_alloc_flags_~flags#1 := ldv_check_alloc_flags_#in~flags#1; {14432#false} is VALID [2022-02-20 22:33:09,056 INFO L290 TraceCheckUtils]: 127: Hoare triple {14432#false} assume 0 != ~ldv_spin~0 && 0 != (if 0 == ldv_check_alloc_flags_~flags#1 then 0 else (if 1 == ldv_check_alloc_flags_~flags#1 then 0 else ~bitwiseAnd(ldv_check_alloc_flags_~flags#1, 16))) % 4294967296; {14432#false} is VALID [2022-02-20 22:33:09,056 INFO L272 TraceCheckUtils]: 128: Hoare triple {14432#false} call ldv_error(); {14432#false} is VALID [2022-02-20 22:33:09,056 INFO L290 TraceCheckUtils]: 129: Hoare triple {14432#false} assume !false; {14432#false} is VALID [2022-02-20 22:33:09,057 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2022-02-20 22:33:09,057 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:33:09,057 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598024233] [2022-02-20 22:33:09,057 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [598024233] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:33:09,057 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:33:09,057 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-02-20 22:33:09,058 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1963369939] [2022-02-20 22:33:09,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:33:09,061 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 8.428571428571429) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 1 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) Word has length 130 [2022-02-20 22:33:09,062 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:33:09,062 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 8.428571428571429) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 1 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) [2022-02-20 22:33:09,128 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:33:09,128 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-02-20 22:33:09,129 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:33:09,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-02-20 22:33:09,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2022-02-20 22:33:09,129 INFO L87 Difference]: Start difference. First operand 1805 states and 2647 transitions. Second operand has 7 states, 7 states have (on average 8.428571428571429) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (12), 6 states have call predecessors, (12), 1 states have return successors, (11), 2 states have call predecessors, (11), 2 states have call successors, (11) [2022-02-20 22:33:13,705 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:33:25,396 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:33:27,401 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:33:32,575 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.86s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [] [2022-02-20 22:33:34,582 WARN L534 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers []