./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i --full-output -ea --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 440f273968b34677cc4ba81db9f48373d3cac4b8a75ac1f970ae3fdbbff89c17 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-20 22:04:47,619 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-20 22:04:47,622 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-20 22:04:47,669 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-20 22:04:47,670 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-20 22:04:47,674 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-20 22:04:47,675 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-20 22:04:47,678 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-20 22:04:47,680 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-20 22:04:47,683 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-20 22:04:47,684 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-20 22:04:47,685 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-20 22:04:47,686 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-20 22:04:47,688 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-20 22:04:47,689 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-20 22:04:47,692 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-20 22:04:47,692 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-20 22:04:47,693 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-20 22:04:47,695 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-20 22:04:47,700 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-20 22:04:47,701 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-20 22:04:47,702 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-20 22:04:47,707 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-20 22:04:47,708 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-20 22:04:47,711 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-20 22:04:47,711 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-20 22:04:47,711 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-20 22:04:47,713 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-20 22:04:47,713 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-20 22:04:47,714 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-20 22:04:47,714 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-20 22:04:47,715 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-20 22:04:47,716 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-20 22:04:47,718 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-20 22:04:47,719 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-20 22:04:47,719 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-20 22:04:47,720 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-20 22:04:47,720 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-20 22:04:47,720 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-20 22:04:47,721 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-20 22:04:47,721 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-20 22:04:47,722 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-64bit-Automizer_Default.epf [2022-02-20 22:04:47,753 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-20 22:04:47,753 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-20 22:04:47,753 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-20 22:04:47,754 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-20 22:04:47,754 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-20 22:04:47,755 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-20 22:04:47,755 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-20 22:04:47,755 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-20 22:04:47,755 INFO L138 SettingsManager]: * Use SBE=true [2022-02-20 22:04:47,756 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-20 22:04:47,756 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-20 22:04:47,757 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-20 22:04:47,757 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-20 22:04:47,757 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-20 22:04:47,757 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-20 22:04:47,757 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-20 22:04:47,758 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-20 22:04:47,758 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-20 22:04:47,758 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-20 22:04:47,758 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-20 22:04:47,758 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-20 22:04:47,759 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:04:47,759 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-20 22:04:47,759 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-20 22:04:47,759 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-20 22:04:47,759 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-20 22:04:47,760 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-20 22:04:47,761 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-20 22:04:47,761 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2022-02-20 22:04:47,761 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-20 22:04:47,761 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 440f273968b34677cc4ba81db9f48373d3cac4b8a75ac1f970ae3fdbbff89c17 [2022-02-20 22:04:47,995 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-20 22:04:48,018 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-20 22:04:48,021 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-20 22:04:48,022 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-20 22:04:48,023 INFO L275 PluginConnector]: CDTParser initialized [2022-02-20 22:04:48,024 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i [2022-02-20 22:04:48,081 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ac4f1c889/ca6c9e99aa074e34b87d0358be5932f1/FLAG8ab904702 [2022-02-20 22:04:48,658 INFO L306 CDTParser]: Found 1 translation units. [2022-02-20 22:04:48,661 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i [2022-02-20 22:04:48,686 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ac4f1c889/ca6c9e99aa074e34b87d0358be5932f1/FLAG8ab904702 [2022-02-20 22:04:48,905 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ac4f1c889/ca6c9e99aa074e34b87d0358be5932f1 [2022-02-20 22:04:48,907 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-20 22:04:48,908 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-20 22:04:48,909 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-20 22:04:48,909 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-20 22:04:48,917 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-20 22:04:48,918 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:04:48" (1/1) ... [2022-02-20 22:04:48,919 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c980141 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:48, skipping insertion in model container [2022-02-20 22:04:48,919 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 20.02 10:04:48" (1/1) ... [2022-02-20 22:04:48,925 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-20 22:04:48,994 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-20 22:04:49,326 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i[49178,49191] [2022-02-20 22:04:49,583 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:04:49,603 INFO L203 MainTranslator]: Completed pre-run [2022-02-20 22:04:49,703 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i[49178,49191] [2022-02-20 22:04:49,768 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-20 22:04:49,803 INFO L208 MainTranslator]: Completed translation [2022-02-20 22:04:49,803 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49 WrapperNode [2022-02-20 22:04:49,805 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-20 22:04:49,806 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-20 22:04:49,806 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-20 22:04:49,806 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-20 22:04:49,813 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:49,849 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:49,920 INFO L137 Inliner]: procedures = 117, calls = 360, calls flagged for inlining = 51, calls inlined = 35, statements flattened = 863 [2022-02-20 22:04:49,920 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-20 22:04:49,921 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-20 22:04:49,921 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-20 22:04:49,921 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-20 22:04:49,929 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:49,929 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:49,937 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:49,937 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:49,964 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:49,971 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:49,976 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:49,998 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-20 22:04:49,999 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-20 22:04:50,000 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-20 22:04:50,000 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-20 22:04:50,006 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (1/1) ... [2022-02-20 22:04:50,011 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-20 22:04:50,019 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:04:50,028 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-20 22:04:50,030 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-20 22:04:50,066 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2022-02-20 22:04:50,067 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_get_drvdata [2022-02-20 22:04:50,067 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2022-02-20 22:04:50,067 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2022-02-20 22:04:50,067 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-02-20 22:04:50,067 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2022-02-20 22:04:50,067 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_time_to_tm [2022-02-20 22:04:50,068 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2022-02-20 22:04:50,068 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2022-02-20 22:04:50,068 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2022-02-20 22:04:50,068 INFO L138 BoogieDeclarations]: Found implementation of procedure irq_set_irq_wake [2022-02-20 22:04:50,068 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2022-02-20 22:04:50,068 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2022-02-20 22:04:50,068 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2022-02-20 22:04:50,069 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2022-02-20 22:04:50,069 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2022-02-20 22:04:50,069 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2022-02-20 22:04:50,069 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2022-02-20 22:04:50,069 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2022-02-20 22:04:50,069 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2022-02-20 22:04:50,069 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_tm_to_time [2022-02-20 22:04:50,070 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2022-02-20 22:04:50,070 INFO L138 BoogieDeclarations]: Found implementation of procedure __release_region [2022-02-20 22:04:50,070 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2022-02-20 22:04:50,070 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2022-02-20 22:04:50,070 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2022-02-20 22:04:50,070 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2022-02-20 22:04:50,070 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-02-20 22:04:50,070 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2022-02-20 22:04:50,071 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2022-02-20 22:04:50,071 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2022-02-20 22:04:50,071 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2022-02-20 22:04:50,071 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2022-02-20 22:04:50,071 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2022-02-20 22:04:50,071 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2022-02-20 22:04:50,072 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_iounmap [2022-02-20 22:04:50,072 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2022-02-20 22:04:50,072 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2022-02-20 22:04:50,072 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-02-20 22:04:50,072 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-20 22:04:50,073 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2022-02-20 22:04:50,073 INFO L138 BoogieDeclarations]: Found implementation of procedure rtc_device_unregister [2022-02-20 22:04:50,073 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-02-20 22:04:50,073 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2022-02-20 22:04:50,073 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2022-02-20 22:04:50,074 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-02-20 22:04:50,074 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_is_err [2022-02-20 22:04:50,074 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_is_err [2022-02-20 22:04:50,074 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2022-02-20 22:04:50,074 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2022-02-20 22:04:50,074 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2022-02-20 22:04:50,074 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2022-02-20 22:04:50,074 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2022-02-20 22:04:50,075 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_resource [2022-02-20 22:04:50,075 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-02-20 22:04:50,075 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2022-02-20 22:04:50,075 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2022-02-20 22:04:50,076 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2022-02-20 22:04:50,076 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2022-02-20 22:04:50,077 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2022-02-20 22:04:50,077 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2022-02-20 22:04:50,077 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2022-02-20 22:04:50,077 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2022-02-20 22:04:50,077 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2022-02-20 22:04:50,077 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-20 22:04:50,077 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2022-02-20 22:04:50,077 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2022-02-20 22:04:50,077 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2022-02-20 22:04:50,077 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2022-02-20 22:04:50,077 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2022-02-20 22:04:50,078 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2022-02-20 22:04:50,078 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-20 22:04:50,078 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-20 22:04:50,423 INFO L234 CfgBuilder]: Building ICFG [2022-02-20 22:04:50,425 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-20 22:04:50,643 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2022-02-20 22:04:51,431 INFO L275 CfgBuilder]: Performing block encoding [2022-02-20 22:04:51,450 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-20 22:04:51,451 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-02-20 22:04:51,453 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:04:51 BoogieIcfgContainer [2022-02-20 22:04:51,453 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-20 22:04:51,455 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-20 22:04:51,455 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-20 22:04:51,458 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-20 22:04:51,459 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 20.02 10:04:48" (1/3) ... [2022-02-20 22:04:51,459 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@118e536c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:04:51, skipping insertion in model container [2022-02-20 22:04:51,460 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 20.02 10:04:49" (2/3) ... [2022-02-20 22:04:51,460 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@118e536c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 20.02 10:04:51, skipping insertion in model container [2022-02-20 22:04:51,460 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 20.02 10:04:51" (3/3) ... [2022-02-20 22:04:51,464 INFO L111 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point.cil.out.i [2022-02-20 22:04:51,472 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-20 22:04:51,473 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-02-20 22:04:51,528 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-20 22:04:51,535 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-20 22:04:51,535 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-02-20 22:04:51,573 INFO L276 IsEmpty]: Start isEmpty. Operand has 399 states, 288 states have (on average 1.375) internal successors, (396), 298 states have internal predecessors, (396), 79 states have call successors, (79), 31 states have call predecessors, (79), 30 states have return successors, (73), 73 states have call predecessors, (73), 73 states have call successors, (73) [2022-02-20 22:04:51,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2022-02-20 22:04:51,583 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:04:51,584 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:04:51,584 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:04:51,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:04:51,589 INFO L85 PathProgramCache]: Analyzing trace with hash 863061951, now seen corresponding path program 1 times [2022-02-20 22:04:51,597 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:04:51,598 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991599515] [2022-02-20 22:04:51,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:04:51,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:04:51,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:51,896 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:04:51,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:51,914 INFO L290 TraceCheckUtils]: 0: Hoare triple {418#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {402#true} is VALID [2022-02-20 22:04:51,914 INFO L290 TraceCheckUtils]: 1: Hoare triple {402#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {402#true} is VALID [2022-02-20 22:04:51,924 INFO L290 TraceCheckUtils]: 2: Hoare triple {402#true} assume true; {402#true} is VALID [2022-02-20 22:04:51,924 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {402#true} {402#true} #979#return; {402#true} is VALID [2022-02-20 22:04:51,931 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 24 [2022-02-20 22:04:51,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:51,957 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:04:51,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:51,978 INFO L290 TraceCheckUtils]: 0: Hoare triple {419#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {402#true} is VALID [2022-02-20 22:04:51,979 INFO L290 TraceCheckUtils]: 1: Hoare triple {402#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {402#true} is VALID [2022-02-20 22:04:51,980 INFO L290 TraceCheckUtils]: 2: Hoare triple {402#true} assume true; {402#true} is VALID [2022-02-20 22:04:51,981 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {402#true} {402#true} #893#return; {402#true} is VALID [2022-02-20 22:04:51,981 INFO L290 TraceCheckUtils]: 0: Hoare triple {419#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {402#true} is VALID [2022-02-20 22:04:51,986 INFO L272 TraceCheckUtils]: 1: Hoare triple {402#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {419#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:51,986 INFO L290 TraceCheckUtils]: 2: Hoare triple {419#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {402#true} is VALID [2022-02-20 22:04:51,987 INFO L290 TraceCheckUtils]: 3: Hoare triple {402#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {402#true} is VALID [2022-02-20 22:04:51,987 INFO L290 TraceCheckUtils]: 4: Hoare triple {402#true} assume true; {402#true} is VALID [2022-02-20 22:04:51,988 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {402#true} {402#true} #893#return; {402#true} is VALID [2022-02-20 22:04:51,988 INFO L290 TraceCheckUtils]: 6: Hoare triple {402#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {402#true} is VALID [2022-02-20 22:04:51,988 INFO L290 TraceCheckUtils]: 7: Hoare triple {402#true} assume true; {402#true} is VALID [2022-02-20 22:04:51,989 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {402#true} {403#false} #907#return; {403#false} is VALID [2022-02-20 22:04:51,990 INFO L290 TraceCheckUtils]: 0: Hoare triple {402#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {402#true} is VALID [2022-02-20 22:04:51,995 INFO L290 TraceCheckUtils]: 1: Hoare triple {402#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {402#true} is VALID [2022-02-20 22:04:51,996 INFO L272 TraceCheckUtils]: 2: Hoare triple {402#true} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {418#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:51,996 INFO L290 TraceCheckUtils]: 3: Hoare triple {418#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {402#true} is VALID [2022-02-20 22:04:51,996 INFO L290 TraceCheckUtils]: 4: Hoare triple {402#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {402#true} is VALID [2022-02-20 22:04:51,997 INFO L290 TraceCheckUtils]: 5: Hoare triple {402#true} assume true; {402#true} is VALID [2022-02-20 22:04:51,997 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {402#true} {402#true} #979#return; {402#true} is VALID [2022-02-20 22:04:51,997 INFO L290 TraceCheckUtils]: 7: Hoare triple {402#true} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {402#true} is VALID [2022-02-20 22:04:51,997 INFO L290 TraceCheckUtils]: 8: Hoare triple {402#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {402#true} is VALID [2022-02-20 22:04:51,998 INFO L290 TraceCheckUtils]: 9: Hoare triple {402#true} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {402#true} is VALID [2022-02-20 22:04:51,998 INFO L290 TraceCheckUtils]: 10: Hoare triple {402#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {408#(= ~ldv_state_variable_3~0 0)} is VALID [2022-02-20 22:04:51,999 INFO L290 TraceCheckUtils]: 11: Hoare triple {408#(= ~ldv_state_variable_3~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {408#(= ~ldv_state_variable_3~0 0)} is VALID [2022-02-20 22:04:52,000 INFO L290 TraceCheckUtils]: 12: Hoare triple {408#(= ~ldv_state_variable_3~0 0)} assume !main_#t~switch236#1;main_#t~switch236#1 := main_#t~switch236#1 || 1 == main_~tmp___1~5#1; {408#(= ~ldv_state_variable_3~0 0)} is VALID [2022-02-20 22:04:52,001 INFO L290 TraceCheckUtils]: 13: Hoare triple {408#(= ~ldv_state_variable_3~0 0)} assume !main_#t~switch236#1;main_#t~switch236#1 := main_#t~switch236#1 || 2 == main_~tmp___1~5#1; {408#(= ~ldv_state_variable_3~0 0)} is VALID [2022-02-20 22:04:52,001 INFO L290 TraceCheckUtils]: 14: Hoare triple {408#(= ~ldv_state_variable_3~0 0)} assume main_#t~switch236#1; {408#(= ~ldv_state_variable_3~0 0)} is VALID [2022-02-20 22:04:52,002 INFO L290 TraceCheckUtils]: 15: Hoare triple {408#(= ~ldv_state_variable_3~0 0)} assume 0 != ~ldv_state_variable_3~0;assume -2147483648 <= main_#t~nondet240#1 && main_#t~nondet240#1 <= 2147483647;main_~tmp___3~1#1 := main_#t~nondet240#1;havoc main_#t~nondet240#1;main_#t~switch241#1 := 0 == main_~tmp___3~1#1; {403#false} is VALID [2022-02-20 22:04:52,002 INFO L290 TraceCheckUtils]: 16: Hoare triple {403#false} assume !main_#t~switch241#1;main_#t~switch241#1 := main_#t~switch241#1 || 1 == main_~tmp___3~1#1; {403#false} is VALID [2022-02-20 22:04:52,002 INFO L290 TraceCheckUtils]: 17: Hoare triple {403#false} assume !main_#t~switch241#1;main_#t~switch241#1 := main_#t~switch241#1 || 2 == main_~tmp___3~1#1; {403#false} is VALID [2022-02-20 22:04:52,003 INFO L290 TraceCheckUtils]: 18: Hoare triple {403#false} assume !main_#t~switch241#1;main_#t~switch241#1 := main_#t~switch241#1 || 3 == main_~tmp___3~1#1; {403#false} is VALID [2022-02-20 22:04:52,003 INFO L290 TraceCheckUtils]: 19: Hoare triple {403#false} assume main_#t~switch241#1; {403#false} is VALID [2022-02-20 22:04:52,004 INFO L290 TraceCheckUtils]: 20: Hoare triple {403#false} assume !(1 == ~ldv_state_variable_3~0); {403#false} is VALID [2022-02-20 22:04:52,004 INFO L290 TraceCheckUtils]: 21: Hoare triple {403#false} assume 2 == ~ldv_state_variable_3~0; {403#false} is VALID [2022-02-20 22:04:52,004 INFO L272 TraceCheckUtils]: 22: Hoare triple {403#false} call main_#t~ret248#1 := tegra_rtc_read_time(~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset, ~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset); {403#false} is VALID [2022-02-20 22:04:52,005 INFO L290 TraceCheckUtils]: 23: Hoare triple {403#false} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;~tm.base, ~tm.offset := #in~tm.base, #in~tm.offset;havoc ~info~1.base, ~info~1.offset;havoc ~tmp~10.base, ~tmp~10.offset;havoc ~sec~0;havoc ~msec~0;havoc ~sl_irq_flags~0;havoc ~__v~1;havoc ~__v___0~1;havoc ~__v___1~0;havoc ~__v___2~0; {403#false} is VALID [2022-02-20 22:04:52,005 INFO L272 TraceCheckUtils]: 24: Hoare triple {403#false} call #t~ret92.base, #t~ret92.offset := dev_get_drvdata(~dev.base, ~dev.offset); {419#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:52,005 INFO L290 TraceCheckUtils]: 25: Hoare triple {419#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {402#true} is VALID [2022-02-20 22:04:52,006 INFO L272 TraceCheckUtils]: 26: Hoare triple {402#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {419#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:52,006 INFO L290 TraceCheckUtils]: 27: Hoare triple {419#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {402#true} is VALID [2022-02-20 22:04:52,007 INFO L290 TraceCheckUtils]: 28: Hoare triple {402#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {402#true} is VALID [2022-02-20 22:04:52,007 INFO L290 TraceCheckUtils]: 29: Hoare triple {402#true} assume true; {402#true} is VALID [2022-02-20 22:04:52,007 INFO L284 TraceCheckUtils]: 30: Hoare quadruple {402#true} {402#true} #893#return; {402#true} is VALID [2022-02-20 22:04:52,007 INFO L290 TraceCheckUtils]: 31: Hoare triple {402#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {402#true} is VALID [2022-02-20 22:04:52,010 INFO L290 TraceCheckUtils]: 32: Hoare triple {402#true} assume true; {402#true} is VALID [2022-02-20 22:04:52,011 INFO L284 TraceCheckUtils]: 33: Hoare quadruple {402#true} {403#false} #907#return; {403#false} is VALID [2022-02-20 22:04:52,011 INFO L290 TraceCheckUtils]: 34: Hoare triple {403#false} ~tmp~10.base, ~tmp~10.offset := #t~ret92.base, #t~ret92.offset;havoc #t~ret92.base, #t~ret92.offset;~info~1.base, ~info~1.offset := ~tmp~10.base, ~tmp~10.offset; {403#false} is VALID [2022-02-20 22:04:52,011 INFO L272 TraceCheckUtils]: 35: Hoare triple {403#false} call ldv_spin_lock_check(); {403#false} is VALID [2022-02-20 22:04:52,012 INFO L290 TraceCheckUtils]: 36: Hoare triple {403#false} assume !(1 == ~ldv_init~0); {403#false} is VALID [2022-02-20 22:04:52,012 INFO L272 TraceCheckUtils]: 37: Hoare triple {403#false} call ldv_error(); {403#false} is VALID [2022-02-20 22:04:52,012 INFO L290 TraceCheckUtils]: 38: Hoare triple {403#false} assume !false; {403#false} is VALID [2022-02-20 22:04:52,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-20 22:04:52,015 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:04:52,015 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991599515] [2022-02-20 22:04:52,016 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1991599515] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:04:52,016 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:04:52,016 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-20 22:04:52,018 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [195526981] [2022-02-20 22:04:52,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:04:52,024 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 6.0) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) Word has length 39 [2022-02-20 22:04:52,026 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:04:52,029 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 6.0) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2022-02-20 22:04:52,081 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:04:52,082 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-02-20 22:04:52,082 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:04:52,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-20 22:04:52,109 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2022-02-20 22:04:52,115 INFO L87 Difference]: Start difference. First operand has 399 states, 288 states have (on average 1.375) internal successors, (396), 298 states have internal predecessors, (396), 79 states have call successors, (79), 31 states have call predecessors, (79), 30 states have return successors, (73), 73 states have call predecessors, (73), 73 states have call successors, (73) Second operand has 5 states, 5 states have (on average 6.0) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2022-02-20 22:04:54,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:04:54,014 INFO L93 Difference]: Finished difference Result 776 states and 1124 transitions. [2022-02-20 22:04:54,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-02-20 22:04:54,015 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 6.0) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) Word has length 39 [2022-02-20 22:04:54,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:04:54,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 6.0) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2022-02-20 22:04:54,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 1124 transitions. [2022-02-20 22:04:54,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 6.0) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2022-02-20 22:04:54,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 1124 transitions. [2022-02-20 22:04:54,100 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 5 states and 1124 transitions. [2022-02-20 22:04:55,113 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 1124 edges. 1124 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:04:55,145 INFO L225 Difference]: With dead ends: 776 [2022-02-20 22:04:55,145 INFO L226 Difference]: Without dead ends: 367 [2022-02-20 22:04:55,151 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2022-02-20 22:04:55,154 INFO L933 BasicCegarLoop]: 383 mSDtfsCounter, 544 mSDsluCounter, 359 mSDsCounter, 0 mSdLazyCounter, 224 mSolverCounterSat, 134 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 575 SdHoareTripleChecker+Valid, 742 SdHoareTripleChecker+Invalid, 358 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 134 IncrementalHoareTripleChecker+Valid, 224 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-02-20 22:04:55,155 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [575 Valid, 742 Invalid, 358 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [134 Valid, 224 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-02-20 22:04:55,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2022-02-20 22:04:55,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 277. [2022-02-20 22:04:55,204 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:04:55,207 INFO L82 GeneralOperation]: Start isEquivalent. First operand 367 states. Second operand has 277 states, 205 states have (on average 1.2829268292682927) internal successors, (263), 206 states have internal predecessors, (263), 48 states have call successors, (48), 24 states have call predecessors, (48), 23 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2022-02-20 22:04:55,208 INFO L74 IsIncluded]: Start isIncluded. First operand 367 states. Second operand has 277 states, 205 states have (on average 1.2829268292682927) internal successors, (263), 206 states have internal predecessors, (263), 48 states have call successors, (48), 24 states have call predecessors, (48), 23 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2022-02-20 22:04:55,209 INFO L87 Difference]: Start difference. First operand 367 states. Second operand has 277 states, 205 states have (on average 1.2829268292682927) internal successors, (263), 206 states have internal predecessors, (263), 48 states have call successors, (48), 24 states have call predecessors, (48), 23 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2022-02-20 22:04:55,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:04:55,236 INFO L93 Difference]: Finished difference Result 367 states and 496 transitions. [2022-02-20 22:04:55,236 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 496 transitions. [2022-02-20 22:04:55,240 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:04:55,241 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:04:55,242 INFO L74 IsIncluded]: Start isIncluded. First operand has 277 states, 205 states have (on average 1.2829268292682927) internal successors, (263), 206 states have internal predecessors, (263), 48 states have call successors, (48), 24 states have call predecessors, (48), 23 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) Second operand 367 states. [2022-02-20 22:04:55,243 INFO L87 Difference]: Start difference. First operand has 277 states, 205 states have (on average 1.2829268292682927) internal successors, (263), 206 states have internal predecessors, (263), 48 states have call successors, (48), 24 states have call predecessors, (48), 23 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) Second operand 367 states. [2022-02-20 22:04:55,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:04:55,262 INFO L93 Difference]: Finished difference Result 367 states and 496 transitions. [2022-02-20 22:04:55,262 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 496 transitions. [2022-02-20 22:04:55,264 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:04:55,264 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:04:55,264 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:04:55,265 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:04:55,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277 states, 205 states have (on average 1.2829268292682927) internal successors, (263), 206 states have internal predecessors, (263), 48 states have call successors, (48), 24 states have call predecessors, (48), 23 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2022-02-20 22:04:55,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 358 transitions. [2022-02-20 22:04:55,279 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 358 transitions. Word has length 39 [2022-02-20 22:04:55,280 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:04:55,280 INFO L470 AbstractCegarLoop]: Abstraction has 277 states and 358 transitions. [2022-02-20 22:04:55,280 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 6.0) internal successors, (30), 3 states have internal predecessors, (30), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2022-02-20 22:04:55,281 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 358 transitions. [2022-02-20 22:04:55,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2022-02-20 22:04:55,283 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:04:55,283 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:04:55,283 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-02-20 22:04:55,284 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:04:55,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:04:55,285 INFO L85 PathProgramCache]: Analyzing trace with hash -1622348299, now seen corresponding path program 1 times [2022-02-20 22:04:55,285 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:04:55,285 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505084766] [2022-02-20 22:04:55,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:04:55,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:04:55,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:55,378 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:04:55,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:55,387 INFO L290 TraceCheckUtils]: 0: Hoare triple {2631#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {2598#true} is VALID [2022-02-20 22:04:55,387 INFO L290 TraceCheckUtils]: 1: Hoare triple {2598#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {2598#true} is VALID [2022-02-20 22:04:55,388 INFO L290 TraceCheckUtils]: 2: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,388 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2598#true} {2598#true} #979#return; {2598#true} is VALID [2022-02-20 22:04:55,393 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2022-02-20 22:04:55,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:55,402 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:04:55,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:55,416 INFO L290 TraceCheckUtils]: 0: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {2598#true} is VALID [2022-02-20 22:04:55,416 INFO L290 TraceCheckUtils]: 1: Hoare triple {2598#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {2598#true} is VALID [2022-02-20 22:04:55,416 INFO L290 TraceCheckUtils]: 2: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,416 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2598#true} {2598#true} #893#return; {2598#true} is VALID [2022-02-20 22:04:55,416 INFO L290 TraceCheckUtils]: 0: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {2598#true} is VALID [2022-02-20 22:04:55,417 INFO L272 TraceCheckUtils]: 1: Hoare triple {2598#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,418 INFO L290 TraceCheckUtils]: 2: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {2598#true} is VALID [2022-02-20 22:04:55,418 INFO L290 TraceCheckUtils]: 3: Hoare triple {2598#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {2598#true} is VALID [2022-02-20 22:04:55,418 INFO L290 TraceCheckUtils]: 4: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,418 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {2598#true} {2598#true} #893#return; {2598#true} is VALID [2022-02-20 22:04:55,418 INFO L290 TraceCheckUtils]: 6: Hoare triple {2598#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {2598#true} is VALID [2022-02-20 22:04:55,418 INFO L290 TraceCheckUtils]: 7: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,419 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {2598#true} {2599#false} #929#return; {2599#false} is VALID [2022-02-20 22:04:55,419 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 34 [2022-02-20 22:04:55,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:55,447 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:04:55,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:55,462 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:04:55,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:55,470 INFO L290 TraceCheckUtils]: 0: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {2598#true} is VALID [2022-02-20 22:04:55,470 INFO L290 TraceCheckUtils]: 1: Hoare triple {2598#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {2598#true} is VALID [2022-02-20 22:04:55,471 INFO L290 TraceCheckUtils]: 2: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,471 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2598#true} {2598#true} #893#return; {2598#true} is VALID [2022-02-20 22:04:55,471 INFO L290 TraceCheckUtils]: 0: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {2598#true} is VALID [2022-02-20 22:04:55,472 INFO L272 TraceCheckUtils]: 1: Hoare triple {2598#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,472 INFO L290 TraceCheckUtils]: 2: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {2598#true} is VALID [2022-02-20 22:04:55,472 INFO L290 TraceCheckUtils]: 3: Hoare triple {2598#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {2598#true} is VALID [2022-02-20 22:04:55,472 INFO L290 TraceCheckUtils]: 4: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,473 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {2598#true} {2598#true} #893#return; {2598#true} is VALID [2022-02-20 22:04:55,473 INFO L290 TraceCheckUtils]: 6: Hoare triple {2598#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {2598#true} is VALID [2022-02-20 22:04:55,473 INFO L290 TraceCheckUtils]: 7: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,473 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {2598#true} {2598#true} #927#return; {2598#true} is VALID [2022-02-20 22:04:55,474 INFO L290 TraceCheckUtils]: 0: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {2598#true} is VALID [2022-02-20 22:04:55,474 INFO L272 TraceCheckUtils]: 1: Hoare triple {2598#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,475 INFO L290 TraceCheckUtils]: 2: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {2598#true} is VALID [2022-02-20 22:04:55,475 INFO L272 TraceCheckUtils]: 3: Hoare triple {2598#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,476 INFO L290 TraceCheckUtils]: 4: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {2598#true} is VALID [2022-02-20 22:04:55,476 INFO L290 TraceCheckUtils]: 5: Hoare triple {2598#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {2598#true} is VALID [2022-02-20 22:04:55,476 INFO L290 TraceCheckUtils]: 6: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,476 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {2598#true} {2598#true} #893#return; {2598#true} is VALID [2022-02-20 22:04:55,476 INFO L290 TraceCheckUtils]: 8: Hoare triple {2598#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {2598#true} is VALID [2022-02-20 22:04:55,477 INFO L290 TraceCheckUtils]: 9: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,477 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {2598#true} {2598#true} #927#return; {2598#true} is VALID [2022-02-20 22:04:55,477 INFO L290 TraceCheckUtils]: 11: Hoare triple {2598#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {2598#true} is VALID [2022-02-20 22:04:55,477 INFO L290 TraceCheckUtils]: 12: Hoare triple {2598#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {2598#true} is VALID [2022-02-20 22:04:55,478 INFO L290 TraceCheckUtils]: 13: Hoare triple {2598#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {2598#true} is VALID [2022-02-20 22:04:55,478 INFO L290 TraceCheckUtils]: 14: Hoare triple {2598#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {2598#true} is VALID [2022-02-20 22:04:55,478 INFO L290 TraceCheckUtils]: 15: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,478 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {2598#true} {2599#false} #931#return; {2599#false} is VALID [2022-02-20 22:04:55,479 INFO L290 TraceCheckUtils]: 0: Hoare triple {2598#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {2598#true} is VALID [2022-02-20 22:04:55,479 INFO L290 TraceCheckUtils]: 1: Hoare triple {2598#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {2598#true} is VALID [2022-02-20 22:04:55,480 INFO L272 TraceCheckUtils]: 2: Hoare triple {2598#true} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {2631#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,480 INFO L290 TraceCheckUtils]: 3: Hoare triple {2631#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {2598#true} is VALID [2022-02-20 22:04:55,480 INFO L290 TraceCheckUtils]: 4: Hoare triple {2598#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {2598#true} is VALID [2022-02-20 22:04:55,480 INFO L290 TraceCheckUtils]: 5: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,480 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {2598#true} {2598#true} #979#return; {2598#true} is VALID [2022-02-20 22:04:55,481 INFO L290 TraceCheckUtils]: 7: Hoare triple {2598#true} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {2598#true} is VALID [2022-02-20 22:04:55,481 INFO L290 TraceCheckUtils]: 8: Hoare triple {2598#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {2598#true} is VALID [2022-02-20 22:04:55,481 INFO L290 TraceCheckUtils]: 9: Hoare triple {2598#true} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {2598#true} is VALID [2022-02-20 22:04:55,482 INFO L290 TraceCheckUtils]: 10: Hoare triple {2598#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {2604#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:04:55,482 INFO L290 TraceCheckUtils]: 11: Hoare triple {2604#(= ~ldv_state_variable_2~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {2604#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:04:55,483 INFO L290 TraceCheckUtils]: 12: Hoare triple {2604#(= ~ldv_state_variable_2~0 0)} assume !main_#t~switch236#1;main_#t~switch236#1 := main_#t~switch236#1 || 1 == main_~tmp___1~5#1; {2604#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:04:55,483 INFO L290 TraceCheckUtils]: 13: Hoare triple {2604#(= ~ldv_state_variable_2~0 0)} assume !main_#t~switch236#1;main_#t~switch236#1 := main_#t~switch236#1 || 2 == main_~tmp___1~5#1; {2604#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:04:55,483 INFO L290 TraceCheckUtils]: 14: Hoare triple {2604#(= ~ldv_state_variable_2~0 0)} assume !main_#t~switch236#1;main_#t~switch236#1 := main_#t~switch236#1 || 3 == main_~tmp___1~5#1; {2604#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:04:55,484 INFO L290 TraceCheckUtils]: 15: Hoare triple {2604#(= ~ldv_state_variable_2~0 0)} assume main_#t~switch236#1; {2604#(= ~ldv_state_variable_2~0 0)} is VALID [2022-02-20 22:04:55,484 INFO L290 TraceCheckUtils]: 16: Hoare triple {2604#(= ~ldv_state_variable_2~0 0)} assume 0 != ~ldv_state_variable_2~0;assume -2147483648 <= main_#t~nondet255#1 && main_#t~nondet255#1 <= 2147483647;main_~tmp___4~1#1 := main_#t~nondet255#1;havoc main_#t~nondet255#1;main_#t~switch256#1 := 0 == main_~tmp___4~1#1; {2599#false} is VALID [2022-02-20 22:04:55,484 INFO L290 TraceCheckUtils]: 17: Hoare triple {2599#false} assume main_#t~switch256#1; {2599#false} is VALID [2022-02-20 22:04:55,485 INFO L290 TraceCheckUtils]: 18: Hoare triple {2599#false} assume 4 == ~ldv_state_variable_2~0; {2599#false} is VALID [2022-02-20 22:04:55,485 INFO L272 TraceCheckUtils]: 19: Hoare triple {2599#false} call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset); {2599#false} is VALID [2022-02-20 22:04:55,485 INFO L290 TraceCheckUtils]: 20: Hoare triple {2599#false} ~pdev.base, ~pdev.offset := #in~pdev.base, #in~pdev.offset; {2599#false} is VALID [2022-02-20 22:04:55,485 INFO L272 TraceCheckUtils]: 21: Hoare triple {2599#false} call #t~ret217 := tegra_rtc_alarm_irq_enable(~pdev.base, 12 + ~pdev.offset, 0); {2599#false} is VALID [2022-02-20 22:04:55,486 INFO L290 TraceCheckUtils]: 22: Hoare triple {2599#false} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;~enabled := #in~enabled;havoc ~info~4.base, ~info~4.offset;havoc ~tmp~13.base, ~tmp~13.offset;havoc ~status~0;havoc ~sl_irq_flags~1;havoc ~__v~3;havoc ~__v___0~3; {2599#false} is VALID [2022-02-20 22:04:55,486 INFO L272 TraceCheckUtils]: 23: Hoare triple {2599#false} call #t~ret108.base, #t~ret108.offset := dev_get_drvdata(~dev.base, ~dev.offset); {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,486 INFO L290 TraceCheckUtils]: 24: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {2598#true} is VALID [2022-02-20 22:04:55,487 INFO L272 TraceCheckUtils]: 25: Hoare triple {2598#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,487 INFO L290 TraceCheckUtils]: 26: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {2598#true} is VALID [2022-02-20 22:04:55,487 INFO L290 TraceCheckUtils]: 27: Hoare triple {2598#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {2598#true} is VALID [2022-02-20 22:04:55,487 INFO L290 TraceCheckUtils]: 28: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,487 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {2598#true} {2598#true} #893#return; {2598#true} is VALID [2022-02-20 22:04:55,488 INFO L290 TraceCheckUtils]: 30: Hoare triple {2598#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {2598#true} is VALID [2022-02-20 22:04:55,488 INFO L290 TraceCheckUtils]: 31: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,488 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {2598#true} {2599#false} #929#return; {2599#false} is VALID [2022-02-20 22:04:55,488 INFO L290 TraceCheckUtils]: 33: Hoare triple {2599#false} ~tmp~13.base, ~tmp~13.offset := #t~ret108.base, #t~ret108.offset;havoc #t~ret108.base, #t~ret108.offset;~info~4.base, ~info~4.offset := ~tmp~13.base, ~tmp~13.offset; {2599#false} is VALID [2022-02-20 22:04:55,488 INFO L272 TraceCheckUtils]: 34: Hoare triple {2599#false} call #t~ret109 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,489 INFO L290 TraceCheckUtils]: 35: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {2598#true} is VALID [2022-02-20 22:04:55,489 INFO L272 TraceCheckUtils]: 36: Hoare triple {2598#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,490 INFO L290 TraceCheckUtils]: 37: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {2598#true} is VALID [2022-02-20 22:04:55,490 INFO L272 TraceCheckUtils]: 38: Hoare triple {2598#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:55,490 INFO L290 TraceCheckUtils]: 39: Hoare triple {2632#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {2598#true} is VALID [2022-02-20 22:04:55,491 INFO L290 TraceCheckUtils]: 40: Hoare triple {2598#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {2598#true} is VALID [2022-02-20 22:04:55,491 INFO L290 TraceCheckUtils]: 41: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,491 INFO L284 TraceCheckUtils]: 42: Hoare quadruple {2598#true} {2598#true} #893#return; {2598#true} is VALID [2022-02-20 22:04:55,491 INFO L290 TraceCheckUtils]: 43: Hoare triple {2598#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {2598#true} is VALID [2022-02-20 22:04:55,491 INFO L290 TraceCheckUtils]: 44: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,492 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {2598#true} {2598#true} #927#return; {2598#true} is VALID [2022-02-20 22:04:55,492 INFO L290 TraceCheckUtils]: 46: Hoare triple {2598#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {2598#true} is VALID [2022-02-20 22:04:55,492 INFO L290 TraceCheckUtils]: 47: Hoare triple {2598#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {2598#true} is VALID [2022-02-20 22:04:55,492 INFO L290 TraceCheckUtils]: 48: Hoare triple {2598#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {2598#true} is VALID [2022-02-20 22:04:55,493 INFO L290 TraceCheckUtils]: 49: Hoare triple {2598#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {2598#true} is VALID [2022-02-20 22:04:55,493 INFO L290 TraceCheckUtils]: 50: Hoare triple {2598#true} assume true; {2598#true} is VALID [2022-02-20 22:04:55,493 INFO L284 TraceCheckUtils]: 51: Hoare quadruple {2598#true} {2599#false} #931#return; {2599#false} is VALID [2022-02-20 22:04:55,493 INFO L290 TraceCheckUtils]: 52: Hoare triple {2599#false} assume -2147483648 <= #t~ret109 && #t~ret109 <= 2147483647;havoc #t~ret109; {2599#false} is VALID [2022-02-20 22:04:55,493 INFO L272 TraceCheckUtils]: 53: Hoare triple {2599#false} call ldv_spin_lock_check(); {2599#false} is VALID [2022-02-20 22:04:55,494 INFO L290 TraceCheckUtils]: 54: Hoare triple {2599#false} assume !(1 == ~ldv_init~0); {2599#false} is VALID [2022-02-20 22:04:55,494 INFO L272 TraceCheckUtils]: 55: Hoare triple {2599#false} call ldv_error(); {2599#false} is VALID [2022-02-20 22:04:55,494 INFO L290 TraceCheckUtils]: 56: Hoare triple {2599#false} assume !false; {2599#false} is VALID [2022-02-20 22:04:55,494 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:04:55,495 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:04:55,495 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [505084766] [2022-02-20 22:04:55,495 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [505084766] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:04:55,495 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:04:55,495 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-20 22:04:55,496 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743623283] [2022-02-20 22:04:55,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:04:55,497 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 7.0) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 57 [2022-02-20 22:04:55,497 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:04:55,498 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 7.0) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-02-20 22:04:55,534 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 49 edges. 49 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:04:55,534 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-02-20 22:04:55,535 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:04:55,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-20 22:04:55,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2022-02-20 22:04:55,536 INFO L87 Difference]: Start difference. First operand 277 states and 358 transitions. Second operand has 5 states, 5 states have (on average 7.0) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-02-20 22:04:57,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:04:57,450 INFO L93 Difference]: Finished difference Result 796 states and 1053 transitions. [2022-02-20 22:04:57,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-20 22:04:57,451 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 7.0) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 57 [2022-02-20 22:04:57,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:04:57,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 7.0) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-02-20 22:04:57,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 1053 transitions. [2022-02-20 22:04:57,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 7.0) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-02-20 22:04:57,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 1053 transitions. [2022-02-20 22:04:57,485 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 1053 transitions. [2022-02-20 22:04:58,295 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 1053 edges. 1053 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:04:58,320 INFO L225 Difference]: With dead ends: 796 [2022-02-20 22:04:58,321 INFO L226 Difference]: Without dead ends: 526 [2022-02-20 22:04:58,322 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2022-02-20 22:04:58,323 INFO L933 BasicCegarLoop]: 380 mSDtfsCounter, 386 mSDsluCounter, 509 mSDsCounter, 0 mSdLazyCounter, 478 mSolverCounterSat, 117 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 410 SdHoareTripleChecker+Valid, 889 SdHoareTripleChecker+Invalid, 595 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 117 IncrementalHoareTripleChecker+Valid, 478 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-02-20 22:04:58,323 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [410 Valid, 889 Invalid, 595 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [117 Valid, 478 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-02-20 22:04:58,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 526 states. [2022-02-20 22:04:58,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 526 to 395. [2022-02-20 22:04:58,349 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:04:58,351 INFO L82 GeneralOperation]: Start isEquivalent. First operand 526 states. Second operand has 395 states, 297 states have (on average 1.2861952861952861) internal successors, (382), 299 states have internal predecessors, (382), 65 states have call successors, (65), 33 states have call predecessors, (65), 32 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) [2022-02-20 22:04:58,352 INFO L74 IsIncluded]: Start isIncluded. First operand 526 states. Second operand has 395 states, 297 states have (on average 1.2861952861952861) internal successors, (382), 299 states have internal predecessors, (382), 65 states have call successors, (65), 33 states have call predecessors, (65), 32 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) [2022-02-20 22:04:58,353 INFO L87 Difference]: Start difference. First operand 526 states. Second operand has 395 states, 297 states have (on average 1.2861952861952861) internal successors, (382), 299 states have internal predecessors, (382), 65 states have call successors, (65), 33 states have call predecessors, (65), 32 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) [2022-02-20 22:04:58,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:04:58,390 INFO L93 Difference]: Finished difference Result 526 states and 703 transitions. [2022-02-20 22:04:58,390 INFO L276 IsEmpty]: Start isEmpty. Operand 526 states and 703 transitions. [2022-02-20 22:04:58,392 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:04:58,392 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:04:58,394 INFO L74 IsIncluded]: Start isIncluded. First operand has 395 states, 297 states have (on average 1.2861952861952861) internal successors, (382), 299 states have internal predecessors, (382), 65 states have call successors, (65), 33 states have call predecessors, (65), 32 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) Second operand 526 states. [2022-02-20 22:04:58,395 INFO L87 Difference]: Start difference. First operand has 395 states, 297 states have (on average 1.2861952861952861) internal successors, (382), 299 states have internal predecessors, (382), 65 states have call successors, (65), 33 states have call predecessors, (65), 32 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) Second operand 526 states. [2022-02-20 22:04:58,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:04:58,423 INFO L93 Difference]: Finished difference Result 526 states and 703 transitions. [2022-02-20 22:04:58,423 INFO L276 IsEmpty]: Start isEmpty. Operand 526 states and 703 transitions. [2022-02-20 22:04:58,425 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:04:58,426 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:04:58,426 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:04:58,426 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:04:58,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 395 states, 297 states have (on average 1.2861952861952861) internal successors, (382), 299 states have internal predecessors, (382), 65 states have call successors, (65), 33 states have call predecessors, (65), 32 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) [2022-02-20 22:04:58,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 511 transitions. [2022-02-20 22:04:58,460 INFO L78 Accepts]: Start accepts. Automaton has 395 states and 511 transitions. Word has length 57 [2022-02-20 22:04:58,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:04:58,461 INFO L470 AbstractCegarLoop]: Abstraction has 395 states and 511 transitions. [2022-02-20 22:04:58,461 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 7.0) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-02-20 22:04:58,461 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 511 transitions. [2022-02-20 22:04:58,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2022-02-20 22:04:58,464 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:04:58,465 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:04:58,465 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-02-20 22:04:58,466 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:04:58,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:04:58,466 INFO L85 PathProgramCache]: Analyzing trace with hash 1789312131, now seen corresponding path program 1 times [2022-02-20 22:04:58,467 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:04:58,467 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744025420] [2022-02-20 22:04:58,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:04:58,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:04:58,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:58,561 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:04:58,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:58,571 INFO L290 TraceCheckUtils]: 0: Hoare triple {5343#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {5308#true} is VALID [2022-02-20 22:04:58,571 INFO L290 TraceCheckUtils]: 1: Hoare triple {5308#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {5308#true} is VALID [2022-02-20 22:04:58,572 INFO L290 TraceCheckUtils]: 2: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,572 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5308#true} {5310#(= ~ldv_irq_1_3~0 0)} #979#return; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,579 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2022-02-20 22:04:58,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:58,589 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:04:58,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:58,595 INFO L290 TraceCheckUtils]: 0: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {5308#true} is VALID [2022-02-20 22:04:58,596 INFO L290 TraceCheckUtils]: 1: Hoare triple {5308#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {5308#true} is VALID [2022-02-20 22:04:58,596 INFO L290 TraceCheckUtils]: 2: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,596 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5308#true} {5308#true} #893#return; {5308#true} is VALID [2022-02-20 22:04:58,596 INFO L290 TraceCheckUtils]: 0: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {5308#true} is VALID [2022-02-20 22:04:58,597 INFO L272 TraceCheckUtils]: 1: Hoare triple {5308#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,605 INFO L290 TraceCheckUtils]: 2: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {5308#true} is VALID [2022-02-20 22:04:58,605 INFO L290 TraceCheckUtils]: 3: Hoare triple {5308#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {5308#true} is VALID [2022-02-20 22:04:58,606 INFO L290 TraceCheckUtils]: 4: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,606 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {5308#true} {5308#true} #893#return; {5308#true} is VALID [2022-02-20 22:04:58,606 INFO L290 TraceCheckUtils]: 6: Hoare triple {5308#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {5308#true} is VALID [2022-02-20 22:04:58,606 INFO L290 TraceCheckUtils]: 7: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,606 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {5308#true} {5309#false} #915#return; {5309#false} is VALID [2022-02-20 22:04:58,608 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2022-02-20 22:04:58,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:58,619 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:04:58,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:58,626 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:04:58,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:04:58,637 INFO L290 TraceCheckUtils]: 0: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {5308#true} is VALID [2022-02-20 22:04:58,637 INFO L290 TraceCheckUtils]: 1: Hoare triple {5308#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {5308#true} is VALID [2022-02-20 22:04:58,638 INFO L290 TraceCheckUtils]: 2: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,638 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5308#true} {5308#true} #893#return; {5308#true} is VALID [2022-02-20 22:04:58,639 INFO L290 TraceCheckUtils]: 0: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {5308#true} is VALID [2022-02-20 22:04:58,639 INFO L272 TraceCheckUtils]: 1: Hoare triple {5308#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,640 INFO L290 TraceCheckUtils]: 2: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {5308#true} is VALID [2022-02-20 22:04:58,640 INFO L290 TraceCheckUtils]: 3: Hoare triple {5308#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {5308#true} is VALID [2022-02-20 22:04:58,640 INFO L290 TraceCheckUtils]: 4: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,640 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {5308#true} {5308#true} #893#return; {5308#true} is VALID [2022-02-20 22:04:58,640 INFO L290 TraceCheckUtils]: 6: Hoare triple {5308#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {5308#true} is VALID [2022-02-20 22:04:58,641 INFO L290 TraceCheckUtils]: 7: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,641 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {5308#true} {5308#true} #927#return; {5308#true} is VALID [2022-02-20 22:04:58,641 INFO L290 TraceCheckUtils]: 0: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {5308#true} is VALID [2022-02-20 22:04:58,642 INFO L272 TraceCheckUtils]: 1: Hoare triple {5308#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,642 INFO L290 TraceCheckUtils]: 2: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {5308#true} is VALID [2022-02-20 22:04:58,643 INFO L272 TraceCheckUtils]: 3: Hoare triple {5308#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,643 INFO L290 TraceCheckUtils]: 4: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {5308#true} is VALID [2022-02-20 22:04:58,643 INFO L290 TraceCheckUtils]: 5: Hoare triple {5308#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {5308#true} is VALID [2022-02-20 22:04:58,643 INFO L290 TraceCheckUtils]: 6: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,643 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {5308#true} {5308#true} #893#return; {5308#true} is VALID [2022-02-20 22:04:58,643 INFO L290 TraceCheckUtils]: 8: Hoare triple {5308#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {5308#true} is VALID [2022-02-20 22:04:58,644 INFO L290 TraceCheckUtils]: 9: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,644 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {5308#true} {5308#true} #927#return; {5308#true} is VALID [2022-02-20 22:04:58,644 INFO L290 TraceCheckUtils]: 11: Hoare triple {5308#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {5308#true} is VALID [2022-02-20 22:04:58,644 INFO L290 TraceCheckUtils]: 12: Hoare triple {5308#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {5308#true} is VALID [2022-02-20 22:04:58,644 INFO L290 TraceCheckUtils]: 13: Hoare triple {5308#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {5308#true} is VALID [2022-02-20 22:04:58,645 INFO L290 TraceCheckUtils]: 14: Hoare triple {5308#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {5308#true} is VALID [2022-02-20 22:04:58,645 INFO L290 TraceCheckUtils]: 15: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,645 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {5308#true} {5309#false} #917#return; {5309#false} is VALID [2022-02-20 22:04:58,645 INFO L290 TraceCheckUtils]: 0: Hoare triple {5308#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,646 INFO L290 TraceCheckUtils]: 1: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,647 INFO L272 TraceCheckUtils]: 2: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {5343#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,647 INFO L290 TraceCheckUtils]: 3: Hoare triple {5343#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {5308#true} is VALID [2022-02-20 22:04:58,647 INFO L290 TraceCheckUtils]: 4: Hoare triple {5308#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {5308#true} is VALID [2022-02-20 22:04:58,647 INFO L290 TraceCheckUtils]: 5: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,648 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {5308#true} {5310#(= ~ldv_irq_1_3~0 0)} #979#return; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,648 INFO L290 TraceCheckUtils]: 7: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,649 INFO L290 TraceCheckUtils]: 8: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,649 INFO L290 TraceCheckUtils]: 9: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,649 INFO L290 TraceCheckUtils]: 10: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,650 INFO L290 TraceCheckUtils]: 11: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,650 INFO L290 TraceCheckUtils]: 12: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume main_#t~switch236#1; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,651 INFO L290 TraceCheckUtils]: 13: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,651 INFO L290 TraceCheckUtils]: 14: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,651 INFO L290 TraceCheckUtils]: 15: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 2 == choose_interrupt_1_~tmp~23#1; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,652 INFO L290 TraceCheckUtils]: 16: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 3 == choose_interrupt_1_~tmp~23#1; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,652 INFO L290 TraceCheckUtils]: 17: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} assume choose_interrupt_1_#t~switch223#1; {5310#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:04:58,653 INFO L272 TraceCheckUtils]: 18: Hoare triple {5310#(= ~ldv_irq_1_3~0 0)} call choose_interrupt_1_#t~ret227#1 := ldv_irq_1(~ldv_irq_1_3~0, ~ldv_irq_line_1_3~0, ~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset); {5315#(= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:04:58,654 INFO L290 TraceCheckUtils]: 19: Hoare triple {5315#(= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {5316#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:04:58,654 INFO L290 TraceCheckUtils]: 20: Hoare triple {5316#(= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {5309#false} is VALID [2022-02-20 22:04:58,654 INFO L290 TraceCheckUtils]: 21: Hoare triple {5309#false} assume #t~switch220#1; {5309#false} is VALID [2022-02-20 22:04:58,654 INFO L290 TraceCheckUtils]: 22: Hoare triple {5309#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {5309#false} is VALID [2022-02-20 22:04:58,655 INFO L272 TraceCheckUtils]: 23: Hoare triple {5309#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,655 INFO L290 TraceCheckUtils]: 24: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {5308#true} is VALID [2022-02-20 22:04:58,655 INFO L272 TraceCheckUtils]: 25: Hoare triple {5308#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,656 INFO L290 TraceCheckUtils]: 26: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {5308#true} is VALID [2022-02-20 22:04:58,656 INFO L290 TraceCheckUtils]: 27: Hoare triple {5308#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {5308#true} is VALID [2022-02-20 22:04:58,656 INFO L290 TraceCheckUtils]: 28: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,656 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {5308#true} {5308#true} #893#return; {5308#true} is VALID [2022-02-20 22:04:58,656 INFO L290 TraceCheckUtils]: 30: Hoare triple {5308#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {5308#true} is VALID [2022-02-20 22:04:58,656 INFO L290 TraceCheckUtils]: 31: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,657 INFO L284 TraceCheckUtils]: 32: Hoare quadruple {5308#true} {5309#false} #915#return; {5309#false} is VALID [2022-02-20 22:04:58,657 INFO L290 TraceCheckUtils]: 33: Hoare triple {5309#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {5309#false} is VALID [2022-02-20 22:04:58,657 INFO L290 TraceCheckUtils]: 34: Hoare triple {5309#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {5309#false} is VALID [2022-02-20 22:04:58,657 INFO L272 TraceCheckUtils]: 35: Hoare triple {5309#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,657 INFO L290 TraceCheckUtils]: 36: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {5308#true} is VALID [2022-02-20 22:04:58,658 INFO L272 TraceCheckUtils]: 37: Hoare triple {5308#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,658 INFO L290 TraceCheckUtils]: 38: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {5308#true} is VALID [2022-02-20 22:04:58,659 INFO L272 TraceCheckUtils]: 39: Hoare triple {5308#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:04:58,659 INFO L290 TraceCheckUtils]: 40: Hoare triple {5344#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {5308#true} is VALID [2022-02-20 22:04:58,659 INFO L290 TraceCheckUtils]: 41: Hoare triple {5308#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {5308#true} is VALID [2022-02-20 22:04:58,659 INFO L290 TraceCheckUtils]: 42: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,659 INFO L284 TraceCheckUtils]: 43: Hoare quadruple {5308#true} {5308#true} #893#return; {5308#true} is VALID [2022-02-20 22:04:58,660 INFO L290 TraceCheckUtils]: 44: Hoare triple {5308#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {5308#true} is VALID [2022-02-20 22:04:58,660 INFO L290 TraceCheckUtils]: 45: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,660 INFO L284 TraceCheckUtils]: 46: Hoare quadruple {5308#true} {5308#true} #927#return; {5308#true} is VALID [2022-02-20 22:04:58,660 INFO L290 TraceCheckUtils]: 47: Hoare triple {5308#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {5308#true} is VALID [2022-02-20 22:04:58,660 INFO L290 TraceCheckUtils]: 48: Hoare triple {5308#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {5308#true} is VALID [2022-02-20 22:04:58,661 INFO L290 TraceCheckUtils]: 49: Hoare triple {5308#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {5308#true} is VALID [2022-02-20 22:04:58,661 INFO L290 TraceCheckUtils]: 50: Hoare triple {5308#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {5308#true} is VALID [2022-02-20 22:04:58,661 INFO L290 TraceCheckUtils]: 51: Hoare triple {5308#true} assume true; {5308#true} is VALID [2022-02-20 22:04:58,661 INFO L284 TraceCheckUtils]: 52: Hoare quadruple {5308#true} {5309#false} #917#return; {5309#false} is VALID [2022-02-20 22:04:58,661 INFO L290 TraceCheckUtils]: 53: Hoare triple {5309#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {5309#false} is VALID [2022-02-20 22:04:58,661 INFO L272 TraceCheckUtils]: 54: Hoare triple {5309#false} call ldv_spin_lock_check(); {5309#false} is VALID [2022-02-20 22:04:58,662 INFO L290 TraceCheckUtils]: 55: Hoare triple {5309#false} assume !(1 == ~ldv_init~0); {5309#false} is VALID [2022-02-20 22:04:58,662 INFO L272 TraceCheckUtils]: 56: Hoare triple {5309#false} call ldv_error(); {5309#false} is VALID [2022-02-20 22:04:58,662 INFO L290 TraceCheckUtils]: 57: Hoare triple {5309#false} assume !false; {5309#false} is VALID [2022-02-20 22:04:58,662 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:04:58,663 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:04:58,663 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744025420] [2022-02-20 22:04:58,663 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744025420] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:04:58,663 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:04:58,663 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-02-20 22:04:58,663 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343777287] [2022-02-20 22:04:58,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:04:58,664 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 5.285714285714286) internal successors, (37), 4 states have internal predecessors, (37), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 58 [2022-02-20 22:04:58,664 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:04:58,665 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 5.285714285714286) internal successors, (37), 4 states have internal predecessors, (37), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:04:58,700 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:04:58,701 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-02-20 22:04:58,701 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:04:58,701 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-02-20 22:04:58,701 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-02-20 22:04:58,702 INFO L87 Difference]: Start difference. First operand 395 states and 511 transitions. Second operand has 7 states, 7 states have (on average 5.285714285714286) internal successors, (37), 4 states have internal predecessors, (37), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:00,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:00,948 INFO L93 Difference]: Finished difference Result 917 states and 1213 transitions. [2022-02-20 22:05:00,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-02-20 22:05:00,949 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 5.285714285714286) internal successors, (37), 4 states have internal predecessors, (37), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 58 [2022-02-20 22:05:00,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:05:00,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 5.285714285714286) internal successors, (37), 4 states have internal predecessors, (37), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:00,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 858 transitions. [2022-02-20 22:05:00,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 5.285714285714286) internal successors, (37), 4 states have internal predecessors, (37), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:00,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 858 transitions. [2022-02-20 22:05:00,971 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states and 858 transitions. [2022-02-20 22:05:01,694 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 858 edges. 858 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:01,718 INFO L225 Difference]: With dead ends: 917 [2022-02-20 22:05:01,718 INFO L226 Difference]: Without dead ends: 539 [2022-02-20 22:05:01,719 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=83, Unknown=0, NotChecked=0, Total=132 [2022-02-20 22:05:01,720 INFO L933 BasicCegarLoop]: 365 mSDtfsCounter, 524 mSDsluCounter, 755 mSDsCounter, 0 mSdLazyCounter, 615 mSolverCounterSat, 128 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 554 SdHoareTripleChecker+Valid, 1120 SdHoareTripleChecker+Invalid, 743 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 128 IncrementalHoareTripleChecker+Valid, 615 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-02-20 22:05:01,721 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [554 Valid, 1120 Invalid, 743 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [128 Valid, 615 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-02-20 22:05:01,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 539 states. [2022-02-20 22:05:01,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 539 to 405. [2022-02-20 22:05:01,742 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:05:01,743 INFO L82 GeneralOperation]: Start isEquivalent. First operand 539 states. Second operand has 405 states, 305 states have (on average 1.2754098360655737) internal successors, (389), 307 states have internal predecessors, (389), 65 states have call successors, (65), 35 states have call predecessors, (65), 34 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) [2022-02-20 22:05:01,744 INFO L74 IsIncluded]: Start isIncluded. First operand 539 states. Second operand has 405 states, 305 states have (on average 1.2754098360655737) internal successors, (389), 307 states have internal predecessors, (389), 65 states have call successors, (65), 35 states have call predecessors, (65), 34 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) [2022-02-20 22:05:01,745 INFO L87 Difference]: Start difference. First operand 539 states. Second operand has 405 states, 305 states have (on average 1.2754098360655737) internal successors, (389), 307 states have internal predecessors, (389), 65 states have call successors, (65), 35 states have call predecessors, (65), 34 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) [2022-02-20 22:05:01,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:01,768 INFO L93 Difference]: Finished difference Result 539 states and 715 transitions. [2022-02-20 22:05:01,768 INFO L276 IsEmpty]: Start isEmpty. Operand 539 states and 715 transitions. [2022-02-20 22:05:01,769 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:01,770 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:01,771 INFO L74 IsIncluded]: Start isIncluded. First operand has 405 states, 305 states have (on average 1.2754098360655737) internal successors, (389), 307 states have internal predecessors, (389), 65 states have call successors, (65), 35 states have call predecessors, (65), 34 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) Second operand 539 states. [2022-02-20 22:05:01,772 INFO L87 Difference]: Start difference. First operand has 405 states, 305 states have (on average 1.2754098360655737) internal successors, (389), 307 states have internal predecessors, (389), 65 states have call successors, (65), 35 states have call predecessors, (65), 34 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) Second operand 539 states. [2022-02-20 22:05:01,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:01,795 INFO L93 Difference]: Finished difference Result 539 states and 715 transitions. [2022-02-20 22:05:01,795 INFO L276 IsEmpty]: Start isEmpty. Operand 539 states and 715 transitions. [2022-02-20 22:05:01,797 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:01,797 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:01,797 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:05:01,797 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:05:01,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 405 states, 305 states have (on average 1.2754098360655737) internal successors, (389), 307 states have internal predecessors, (389), 65 states have call successors, (65), 35 states have call predecessors, (65), 34 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) [2022-02-20 22:05:01,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 405 states to 405 states and 518 transitions. [2022-02-20 22:05:01,815 INFO L78 Accepts]: Start accepts. Automaton has 405 states and 518 transitions. Word has length 58 [2022-02-20 22:05:01,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:05:01,816 INFO L470 AbstractCegarLoop]: Abstraction has 405 states and 518 transitions. [2022-02-20 22:05:01,816 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 5.285714285714286) internal successors, (37), 4 states have internal predecessors, (37), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:01,816 INFO L276 IsEmpty]: Start isEmpty. Operand 405 states and 518 transitions. [2022-02-20 22:05:01,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2022-02-20 22:05:01,817 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:05:01,818 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:05:01,818 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-02-20 22:05:01,818 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:05:01,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:05:01,819 INFO L85 PathProgramCache]: Analyzing trace with hash 118188198, now seen corresponding path program 1 times [2022-02-20 22:05:01,821 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:05:01,824 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133852954] [2022-02-20 22:05:01,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:01,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:05:01,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:01,915 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:05:01,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:01,932 INFO L290 TraceCheckUtils]: 0: Hoare triple {8264#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {8229#true} is VALID [2022-02-20 22:05:01,932 INFO L290 TraceCheckUtils]: 1: Hoare triple {8229#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {8229#true} is VALID [2022-02-20 22:05:01,932 INFO L290 TraceCheckUtils]: 2: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,933 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8229#true} {8231#(= ~ldv_irq_1_0~0 0)} #979#return; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,942 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 20 [2022-02-20 22:05:01,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:01,951 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:01,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:01,956 INFO L290 TraceCheckUtils]: 0: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {8229#true} is VALID [2022-02-20 22:05:01,956 INFO L290 TraceCheckUtils]: 1: Hoare triple {8229#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {8229#true} is VALID [2022-02-20 22:05:01,956 INFO L290 TraceCheckUtils]: 2: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,957 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8229#true} {8229#true} #893#return; {8229#true} is VALID [2022-02-20 22:05:01,957 INFO L290 TraceCheckUtils]: 0: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {8229#true} is VALID [2022-02-20 22:05:01,958 INFO L272 TraceCheckUtils]: 1: Hoare triple {8229#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:01,958 INFO L290 TraceCheckUtils]: 2: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {8229#true} is VALID [2022-02-20 22:05:01,958 INFO L290 TraceCheckUtils]: 3: Hoare triple {8229#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {8229#true} is VALID [2022-02-20 22:05:01,958 INFO L290 TraceCheckUtils]: 4: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,958 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {8229#true} {8229#true} #893#return; {8229#true} is VALID [2022-02-20 22:05:01,958 INFO L290 TraceCheckUtils]: 6: Hoare triple {8229#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {8229#true} is VALID [2022-02-20 22:05:01,959 INFO L290 TraceCheckUtils]: 7: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,959 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {8229#true} {8230#false} #915#return; {8230#false} is VALID [2022-02-20 22:05:01,959 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 32 [2022-02-20 22:05:01,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:01,969 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:01,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:01,975 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:01,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:01,981 INFO L290 TraceCheckUtils]: 0: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {8229#true} is VALID [2022-02-20 22:05:01,981 INFO L290 TraceCheckUtils]: 1: Hoare triple {8229#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {8229#true} is VALID [2022-02-20 22:05:01,981 INFO L290 TraceCheckUtils]: 2: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,981 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8229#true} {8229#true} #893#return; {8229#true} is VALID [2022-02-20 22:05:01,982 INFO L290 TraceCheckUtils]: 0: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {8229#true} is VALID [2022-02-20 22:05:01,982 INFO L272 TraceCheckUtils]: 1: Hoare triple {8229#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:01,982 INFO L290 TraceCheckUtils]: 2: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {8229#true} is VALID [2022-02-20 22:05:01,983 INFO L290 TraceCheckUtils]: 3: Hoare triple {8229#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {8229#true} is VALID [2022-02-20 22:05:01,983 INFO L290 TraceCheckUtils]: 4: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,983 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {8229#true} {8229#true} #893#return; {8229#true} is VALID [2022-02-20 22:05:01,983 INFO L290 TraceCheckUtils]: 6: Hoare triple {8229#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {8229#true} is VALID [2022-02-20 22:05:01,983 INFO L290 TraceCheckUtils]: 7: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,983 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {8229#true} {8229#true} #927#return; {8229#true} is VALID [2022-02-20 22:05:01,984 INFO L290 TraceCheckUtils]: 0: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {8229#true} is VALID [2022-02-20 22:05:01,984 INFO L272 TraceCheckUtils]: 1: Hoare triple {8229#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:01,985 INFO L290 TraceCheckUtils]: 2: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {8229#true} is VALID [2022-02-20 22:05:01,986 INFO L272 TraceCheckUtils]: 3: Hoare triple {8229#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:01,986 INFO L290 TraceCheckUtils]: 4: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {8229#true} is VALID [2022-02-20 22:05:01,986 INFO L290 TraceCheckUtils]: 5: Hoare triple {8229#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {8229#true} is VALID [2022-02-20 22:05:01,987 INFO L290 TraceCheckUtils]: 6: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,987 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {8229#true} {8229#true} #893#return; {8229#true} is VALID [2022-02-20 22:05:01,987 INFO L290 TraceCheckUtils]: 8: Hoare triple {8229#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {8229#true} is VALID [2022-02-20 22:05:01,987 INFO L290 TraceCheckUtils]: 9: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,987 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {8229#true} {8229#true} #927#return; {8229#true} is VALID [2022-02-20 22:05:01,987 INFO L290 TraceCheckUtils]: 11: Hoare triple {8229#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {8229#true} is VALID [2022-02-20 22:05:01,988 INFO L290 TraceCheckUtils]: 12: Hoare triple {8229#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {8229#true} is VALID [2022-02-20 22:05:01,988 INFO L290 TraceCheckUtils]: 13: Hoare triple {8229#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {8229#true} is VALID [2022-02-20 22:05:01,988 INFO L290 TraceCheckUtils]: 14: Hoare triple {8229#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {8229#true} is VALID [2022-02-20 22:05:01,988 INFO L290 TraceCheckUtils]: 15: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,988 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {8229#true} {8230#false} #917#return; {8230#false} is VALID [2022-02-20 22:05:01,989 INFO L290 TraceCheckUtils]: 0: Hoare triple {8229#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,989 INFO L290 TraceCheckUtils]: 1: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,990 INFO L272 TraceCheckUtils]: 2: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {8264#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:01,990 INFO L290 TraceCheckUtils]: 3: Hoare triple {8264#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {8229#true} is VALID [2022-02-20 22:05:01,990 INFO L290 TraceCheckUtils]: 4: Hoare triple {8229#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {8229#true} is VALID [2022-02-20 22:05:01,990 INFO L290 TraceCheckUtils]: 5: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:01,991 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {8229#true} {8231#(= ~ldv_irq_1_0~0 0)} #979#return; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,991 INFO L290 TraceCheckUtils]: 7: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,992 INFO L290 TraceCheckUtils]: 8: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,992 INFO L290 TraceCheckUtils]: 9: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,993 INFO L290 TraceCheckUtils]: 10: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,993 INFO L290 TraceCheckUtils]: 11: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,993 INFO L290 TraceCheckUtils]: 12: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,994 INFO L290 TraceCheckUtils]: 13: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,994 INFO L290 TraceCheckUtils]: 14: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {8231#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:01,997 INFO L272 TraceCheckUtils]: 15: Hoare triple {8231#(= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {8236#(= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:01,998 INFO L290 TraceCheckUtils]: 16: Hoare triple {8236#(= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {8237#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:01,998 INFO L290 TraceCheckUtils]: 17: Hoare triple {8237#(= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {8230#false} is VALID [2022-02-20 22:05:01,998 INFO L290 TraceCheckUtils]: 18: Hoare triple {8230#false} assume #t~switch220#1; {8230#false} is VALID [2022-02-20 22:05:01,998 INFO L290 TraceCheckUtils]: 19: Hoare triple {8230#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {8230#false} is VALID [2022-02-20 22:05:01,998 INFO L272 TraceCheckUtils]: 20: Hoare triple {8230#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:01,999 INFO L290 TraceCheckUtils]: 21: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {8229#true} is VALID [2022-02-20 22:05:01,999 INFO L272 TraceCheckUtils]: 22: Hoare triple {8229#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:01,999 INFO L290 TraceCheckUtils]: 23: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {8229#true} is VALID [2022-02-20 22:05:01,999 INFO L290 TraceCheckUtils]: 24: Hoare triple {8229#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {8229#true} is VALID [2022-02-20 22:05:02,000 INFO L290 TraceCheckUtils]: 25: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:02,000 INFO L284 TraceCheckUtils]: 26: Hoare quadruple {8229#true} {8229#true} #893#return; {8229#true} is VALID [2022-02-20 22:05:02,000 INFO L290 TraceCheckUtils]: 27: Hoare triple {8229#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {8229#true} is VALID [2022-02-20 22:05:02,000 INFO L290 TraceCheckUtils]: 28: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:02,000 INFO L284 TraceCheckUtils]: 29: Hoare quadruple {8229#true} {8230#false} #915#return; {8230#false} is VALID [2022-02-20 22:05:02,001 INFO L290 TraceCheckUtils]: 30: Hoare triple {8230#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {8230#false} is VALID [2022-02-20 22:05:02,001 INFO L290 TraceCheckUtils]: 31: Hoare triple {8230#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {8230#false} is VALID [2022-02-20 22:05:02,001 INFO L272 TraceCheckUtils]: 32: Hoare triple {8230#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:02,001 INFO L290 TraceCheckUtils]: 33: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {8229#true} is VALID [2022-02-20 22:05:02,002 INFO L272 TraceCheckUtils]: 34: Hoare triple {8229#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:02,002 INFO L290 TraceCheckUtils]: 35: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {8229#true} is VALID [2022-02-20 22:05:02,002 INFO L272 TraceCheckUtils]: 36: Hoare triple {8229#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:02,003 INFO L290 TraceCheckUtils]: 37: Hoare triple {8265#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {8229#true} is VALID [2022-02-20 22:05:02,003 INFO L290 TraceCheckUtils]: 38: Hoare triple {8229#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {8229#true} is VALID [2022-02-20 22:05:02,003 INFO L290 TraceCheckUtils]: 39: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:02,003 INFO L284 TraceCheckUtils]: 40: Hoare quadruple {8229#true} {8229#true} #893#return; {8229#true} is VALID [2022-02-20 22:05:02,003 INFO L290 TraceCheckUtils]: 41: Hoare triple {8229#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {8229#true} is VALID [2022-02-20 22:05:02,004 INFO L290 TraceCheckUtils]: 42: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:02,004 INFO L284 TraceCheckUtils]: 43: Hoare quadruple {8229#true} {8229#true} #927#return; {8229#true} is VALID [2022-02-20 22:05:02,004 INFO L290 TraceCheckUtils]: 44: Hoare triple {8229#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {8229#true} is VALID [2022-02-20 22:05:02,004 INFO L290 TraceCheckUtils]: 45: Hoare triple {8229#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {8229#true} is VALID [2022-02-20 22:05:02,004 INFO L290 TraceCheckUtils]: 46: Hoare triple {8229#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {8229#true} is VALID [2022-02-20 22:05:02,004 INFO L290 TraceCheckUtils]: 47: Hoare triple {8229#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {8229#true} is VALID [2022-02-20 22:05:02,005 INFO L290 TraceCheckUtils]: 48: Hoare triple {8229#true} assume true; {8229#true} is VALID [2022-02-20 22:05:02,005 INFO L284 TraceCheckUtils]: 49: Hoare quadruple {8229#true} {8230#false} #917#return; {8230#false} is VALID [2022-02-20 22:05:02,005 INFO L290 TraceCheckUtils]: 50: Hoare triple {8230#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {8230#false} is VALID [2022-02-20 22:05:02,006 INFO L272 TraceCheckUtils]: 51: Hoare triple {8230#false} call ldv_spin_lock_check(); {8230#false} is VALID [2022-02-20 22:05:02,006 INFO L290 TraceCheckUtils]: 52: Hoare triple {8230#false} assume !(1 == ~ldv_init~0); {8230#false} is VALID [2022-02-20 22:05:02,006 INFO L272 TraceCheckUtils]: 53: Hoare triple {8230#false} call ldv_error(); {8230#false} is VALID [2022-02-20 22:05:02,007 INFO L290 TraceCheckUtils]: 54: Hoare triple {8230#false} assume !false; {8230#false} is VALID [2022-02-20 22:05:02,007 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:02,007 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:05:02,007 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133852954] [2022-02-20 22:05:02,007 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133852954] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:05:02,008 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:05:02,008 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-02-20 22:05:02,008 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829844433] [2022-02-20 22:05:02,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:05:02,009 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 4.857142857142857) internal successors, (34), 4 states have internal predecessors, (34), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 55 [2022-02-20 22:05:02,009 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:05:02,009 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 4.857142857142857) internal successors, (34), 4 states have internal predecessors, (34), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:02,044 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:02,044 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-02-20 22:05:02,044 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:05:02,045 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-02-20 22:05:02,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-02-20 22:05:02,046 INFO L87 Difference]: Start difference. First operand 405 states and 518 transitions. Second operand has 7 states, 7 states have (on average 4.857142857142857) internal successors, (34), 4 states have internal predecessors, (34), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:05,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:05,790 INFO L93 Difference]: Finished difference Result 1457 states and 1916 transitions. [2022-02-20 22:05:05,790 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-02-20 22:05:05,790 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 4.857142857142857) internal successors, (34), 4 states have internal predecessors, (34), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 55 [2022-02-20 22:05:05,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:05:05,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 4.857142857142857) internal successors, (34), 4 states have internal predecessors, (34), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:05,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 1344 transitions. [2022-02-20 22:05:05,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 4.857142857142857) internal successors, (34), 4 states have internal predecessors, (34), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:05,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 1344 transitions. [2022-02-20 22:05:05,824 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 11 states and 1344 transitions. [2022-02-20 22:05:06,881 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 1344 edges. 1344 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:06,961 INFO L225 Difference]: With dead ends: 1457 [2022-02-20 22:05:06,961 INFO L226 Difference]: Without dead ends: 1069 [2022-02-20 22:05:06,962 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=56, Invalid=100, Unknown=0, NotChecked=0, Total=156 [2022-02-20 22:05:06,964 INFO L933 BasicCegarLoop]: 452 mSDtfsCounter, 668 mSDsluCounter, 1126 mSDsCounter, 0 mSdLazyCounter, 1108 mSolverCounterSat, 188 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 708 SdHoareTripleChecker+Valid, 1578 SdHoareTripleChecker+Invalid, 1296 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 188 IncrementalHoareTripleChecker+Valid, 1108 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2022-02-20 22:05:06,965 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [708 Valid, 1578 Invalid, 1296 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [188 Valid, 1108 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2022-02-20 22:05:06,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1069 states. [2022-02-20 22:05:07,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1069 to 797. [2022-02-20 22:05:07,010 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:05:07,012 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1069 states. Second operand has 797 states, 600 states have (on average 1.2766666666666666) internal successors, (766), 611 states have internal predecessors, (766), 124 states have call successors, (124), 68 states have call predecessors, (124), 72 states have return successors, (140), 121 states have call predecessors, (140), 123 states have call successors, (140) [2022-02-20 22:05:07,014 INFO L74 IsIncluded]: Start isIncluded. First operand 1069 states. Second operand has 797 states, 600 states have (on average 1.2766666666666666) internal successors, (766), 611 states have internal predecessors, (766), 124 states have call successors, (124), 68 states have call predecessors, (124), 72 states have return successors, (140), 121 states have call predecessors, (140), 123 states have call successors, (140) [2022-02-20 22:05:07,015 INFO L87 Difference]: Start difference. First operand 1069 states. Second operand has 797 states, 600 states have (on average 1.2766666666666666) internal successors, (766), 611 states have internal predecessors, (766), 124 states have call successors, (124), 68 states have call predecessors, (124), 72 states have return successors, (140), 121 states have call predecessors, (140), 123 states have call successors, (140) [2022-02-20 22:05:07,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:07,081 INFO L93 Difference]: Finished difference Result 1069 states and 1411 transitions. [2022-02-20 22:05:07,081 INFO L276 IsEmpty]: Start isEmpty. Operand 1069 states and 1411 transitions. [2022-02-20 22:05:07,084 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:07,085 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:07,087 INFO L74 IsIncluded]: Start isIncluded. First operand has 797 states, 600 states have (on average 1.2766666666666666) internal successors, (766), 611 states have internal predecessors, (766), 124 states have call successors, (124), 68 states have call predecessors, (124), 72 states have return successors, (140), 121 states have call predecessors, (140), 123 states have call successors, (140) Second operand 1069 states. [2022-02-20 22:05:07,089 INFO L87 Difference]: Start difference. First operand has 797 states, 600 states have (on average 1.2766666666666666) internal successors, (766), 611 states have internal predecessors, (766), 124 states have call successors, (124), 68 states have call predecessors, (124), 72 states have return successors, (140), 121 states have call predecessors, (140), 123 states have call successors, (140) Second operand 1069 states. [2022-02-20 22:05:07,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:07,155 INFO L93 Difference]: Finished difference Result 1069 states and 1411 transitions. [2022-02-20 22:05:07,155 INFO L276 IsEmpty]: Start isEmpty. Operand 1069 states and 1411 transitions. [2022-02-20 22:05:07,160 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:07,160 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:07,161 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:05:07,161 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:05:07,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 797 states, 600 states have (on average 1.2766666666666666) internal successors, (766), 611 states have internal predecessors, (766), 124 states have call successors, (124), 68 states have call predecessors, (124), 72 states have return successors, (140), 121 states have call predecessors, (140), 123 states have call successors, (140) [2022-02-20 22:05:07,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 797 states to 797 states and 1030 transitions. [2022-02-20 22:05:07,214 INFO L78 Accepts]: Start accepts. Automaton has 797 states and 1030 transitions. Word has length 55 [2022-02-20 22:05:07,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:05:07,214 INFO L470 AbstractCegarLoop]: Abstraction has 797 states and 1030 transitions. [2022-02-20 22:05:07,214 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 4.857142857142857) internal successors, (34), 4 states have internal predecessors, (34), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:07,214 INFO L276 IsEmpty]: Start isEmpty. Operand 797 states and 1030 transitions. [2022-02-20 22:05:07,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2022-02-20 22:05:07,217 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:05:07,217 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:05:07,217 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-02-20 22:05:07,217 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:05:07,218 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:05:07,218 INFO L85 PathProgramCache]: Analyzing trace with hash 967197344, now seen corresponding path program 1 times [2022-02-20 22:05:07,218 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:05:07,218 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452010579] [2022-02-20 22:05:07,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:07,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:05:07,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:07,324 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:05:07,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:07,332 INFO L290 TraceCheckUtils]: 0: Hoare triple {13492#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {13457#true} is VALID [2022-02-20 22:05:07,332 INFO L290 TraceCheckUtils]: 1: Hoare triple {13457#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {13457#true} is VALID [2022-02-20 22:05:07,332 INFO L290 TraceCheckUtils]: 2: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,333 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13457#true} {13459#(= ~ldv_irq_1_1~0 0)} #979#return; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,341 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2022-02-20 22:05:07,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:07,348 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:07,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:07,356 INFO L290 TraceCheckUtils]: 0: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {13457#true} is VALID [2022-02-20 22:05:07,357 INFO L290 TraceCheckUtils]: 1: Hoare triple {13457#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {13457#true} is VALID [2022-02-20 22:05:07,357 INFO L290 TraceCheckUtils]: 2: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,359 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13457#true} {13457#true} #893#return; {13457#true} is VALID [2022-02-20 22:05:07,359 INFO L290 TraceCheckUtils]: 0: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {13457#true} is VALID [2022-02-20 22:05:07,367 INFO L272 TraceCheckUtils]: 1: Hoare triple {13457#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,368 INFO L290 TraceCheckUtils]: 2: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {13457#true} is VALID [2022-02-20 22:05:07,368 INFO L290 TraceCheckUtils]: 3: Hoare triple {13457#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {13457#true} is VALID [2022-02-20 22:05:07,369 INFO L290 TraceCheckUtils]: 4: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,369 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {13457#true} {13457#true} #893#return; {13457#true} is VALID [2022-02-20 22:05:07,370 INFO L290 TraceCheckUtils]: 6: Hoare triple {13457#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {13457#true} is VALID [2022-02-20 22:05:07,370 INFO L290 TraceCheckUtils]: 7: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,370 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {13457#true} {13458#false} #915#return; {13458#false} is VALID [2022-02-20 22:05:07,373 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 33 [2022-02-20 22:05:07,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:07,388 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:07,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:07,395 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:07,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:07,401 INFO L290 TraceCheckUtils]: 0: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {13457#true} is VALID [2022-02-20 22:05:07,401 INFO L290 TraceCheckUtils]: 1: Hoare triple {13457#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {13457#true} is VALID [2022-02-20 22:05:07,402 INFO L290 TraceCheckUtils]: 2: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,402 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {13457#true} {13457#true} #893#return; {13457#true} is VALID [2022-02-20 22:05:07,402 INFO L290 TraceCheckUtils]: 0: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {13457#true} is VALID [2022-02-20 22:05:07,403 INFO L272 TraceCheckUtils]: 1: Hoare triple {13457#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,403 INFO L290 TraceCheckUtils]: 2: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {13457#true} is VALID [2022-02-20 22:05:07,403 INFO L290 TraceCheckUtils]: 3: Hoare triple {13457#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {13457#true} is VALID [2022-02-20 22:05:07,403 INFO L290 TraceCheckUtils]: 4: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,403 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {13457#true} {13457#true} #893#return; {13457#true} is VALID [2022-02-20 22:05:07,403 INFO L290 TraceCheckUtils]: 6: Hoare triple {13457#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {13457#true} is VALID [2022-02-20 22:05:07,404 INFO L290 TraceCheckUtils]: 7: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,404 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {13457#true} {13457#true} #927#return; {13457#true} is VALID [2022-02-20 22:05:07,404 INFO L290 TraceCheckUtils]: 0: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {13457#true} is VALID [2022-02-20 22:05:07,405 INFO L272 TraceCheckUtils]: 1: Hoare triple {13457#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,405 INFO L290 TraceCheckUtils]: 2: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {13457#true} is VALID [2022-02-20 22:05:07,405 INFO L272 TraceCheckUtils]: 3: Hoare triple {13457#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,405 INFO L290 TraceCheckUtils]: 4: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {13457#true} is VALID [2022-02-20 22:05:07,406 INFO L290 TraceCheckUtils]: 5: Hoare triple {13457#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {13457#true} is VALID [2022-02-20 22:05:07,406 INFO L290 TraceCheckUtils]: 6: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,406 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {13457#true} {13457#true} #893#return; {13457#true} is VALID [2022-02-20 22:05:07,406 INFO L290 TraceCheckUtils]: 8: Hoare triple {13457#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {13457#true} is VALID [2022-02-20 22:05:07,406 INFO L290 TraceCheckUtils]: 9: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,406 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {13457#true} {13457#true} #927#return; {13457#true} is VALID [2022-02-20 22:05:07,406 INFO L290 TraceCheckUtils]: 11: Hoare triple {13457#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {13457#true} is VALID [2022-02-20 22:05:07,407 INFO L290 TraceCheckUtils]: 12: Hoare triple {13457#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {13457#true} is VALID [2022-02-20 22:05:07,407 INFO L290 TraceCheckUtils]: 13: Hoare triple {13457#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {13457#true} is VALID [2022-02-20 22:05:07,407 INFO L290 TraceCheckUtils]: 14: Hoare triple {13457#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {13457#true} is VALID [2022-02-20 22:05:07,407 INFO L290 TraceCheckUtils]: 15: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,407 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {13457#true} {13458#false} #917#return; {13458#false} is VALID [2022-02-20 22:05:07,408 INFO L290 TraceCheckUtils]: 0: Hoare triple {13457#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,408 INFO L290 TraceCheckUtils]: 1: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,409 INFO L272 TraceCheckUtils]: 2: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {13492#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,409 INFO L290 TraceCheckUtils]: 3: Hoare triple {13492#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {13457#true} is VALID [2022-02-20 22:05:07,409 INFO L290 TraceCheckUtils]: 4: Hoare triple {13457#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {13457#true} is VALID [2022-02-20 22:05:07,409 INFO L290 TraceCheckUtils]: 5: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,410 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {13457#true} {13459#(= ~ldv_irq_1_1~0 0)} #979#return; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,410 INFO L290 TraceCheckUtils]: 7: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,411 INFO L290 TraceCheckUtils]: 8: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,411 INFO L290 TraceCheckUtils]: 9: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,411 INFO L290 TraceCheckUtils]: 10: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,412 INFO L290 TraceCheckUtils]: 11: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,413 INFO L290 TraceCheckUtils]: 12: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} assume main_#t~switch236#1; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,413 INFO L290 TraceCheckUtils]: 13: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,413 INFO L290 TraceCheckUtils]: 14: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,414 INFO L290 TraceCheckUtils]: 15: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} assume choose_interrupt_1_#t~switch223#1; {13459#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:07,414 INFO L272 TraceCheckUtils]: 16: Hoare triple {13459#(= ~ldv_irq_1_1~0 0)} call choose_interrupt_1_#t~ret225#1 := ldv_irq_1(~ldv_irq_1_1~0, ~ldv_irq_line_1_1~0, ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset); {13464#(= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:07,415 INFO L290 TraceCheckUtils]: 17: Hoare triple {13464#(= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {13465#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:07,415 INFO L290 TraceCheckUtils]: 18: Hoare triple {13465#(= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {13458#false} is VALID [2022-02-20 22:05:07,415 INFO L290 TraceCheckUtils]: 19: Hoare triple {13458#false} assume #t~switch220#1; {13458#false} is VALID [2022-02-20 22:05:07,416 INFO L290 TraceCheckUtils]: 20: Hoare triple {13458#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {13458#false} is VALID [2022-02-20 22:05:07,416 INFO L272 TraceCheckUtils]: 21: Hoare triple {13458#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,416 INFO L290 TraceCheckUtils]: 22: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {13457#true} is VALID [2022-02-20 22:05:07,417 INFO L272 TraceCheckUtils]: 23: Hoare triple {13457#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,417 INFO L290 TraceCheckUtils]: 24: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {13457#true} is VALID [2022-02-20 22:05:07,417 INFO L290 TraceCheckUtils]: 25: Hoare triple {13457#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {13457#true} is VALID [2022-02-20 22:05:07,417 INFO L290 TraceCheckUtils]: 26: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,417 INFO L284 TraceCheckUtils]: 27: Hoare quadruple {13457#true} {13457#true} #893#return; {13457#true} is VALID [2022-02-20 22:05:07,417 INFO L290 TraceCheckUtils]: 28: Hoare triple {13457#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {13457#true} is VALID [2022-02-20 22:05:07,417 INFO L290 TraceCheckUtils]: 29: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,418 INFO L284 TraceCheckUtils]: 30: Hoare quadruple {13457#true} {13458#false} #915#return; {13458#false} is VALID [2022-02-20 22:05:07,418 INFO L290 TraceCheckUtils]: 31: Hoare triple {13458#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {13458#false} is VALID [2022-02-20 22:05:07,418 INFO L290 TraceCheckUtils]: 32: Hoare triple {13458#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {13458#false} is VALID [2022-02-20 22:05:07,418 INFO L272 TraceCheckUtils]: 33: Hoare triple {13458#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,418 INFO L290 TraceCheckUtils]: 34: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {13457#true} is VALID [2022-02-20 22:05:07,419 INFO L272 TraceCheckUtils]: 35: Hoare triple {13457#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,419 INFO L290 TraceCheckUtils]: 36: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {13457#true} is VALID [2022-02-20 22:05:07,420 INFO L272 TraceCheckUtils]: 37: Hoare triple {13457#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:07,420 INFO L290 TraceCheckUtils]: 38: Hoare triple {13493#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {13457#true} is VALID [2022-02-20 22:05:07,420 INFO L290 TraceCheckUtils]: 39: Hoare triple {13457#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {13457#true} is VALID [2022-02-20 22:05:07,420 INFO L290 TraceCheckUtils]: 40: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,420 INFO L284 TraceCheckUtils]: 41: Hoare quadruple {13457#true} {13457#true} #893#return; {13457#true} is VALID [2022-02-20 22:05:07,420 INFO L290 TraceCheckUtils]: 42: Hoare triple {13457#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {13457#true} is VALID [2022-02-20 22:05:07,420 INFO L290 TraceCheckUtils]: 43: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,420 INFO L284 TraceCheckUtils]: 44: Hoare quadruple {13457#true} {13457#true} #927#return; {13457#true} is VALID [2022-02-20 22:05:07,421 INFO L290 TraceCheckUtils]: 45: Hoare triple {13457#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {13457#true} is VALID [2022-02-20 22:05:07,421 INFO L290 TraceCheckUtils]: 46: Hoare triple {13457#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {13457#true} is VALID [2022-02-20 22:05:07,421 INFO L290 TraceCheckUtils]: 47: Hoare triple {13457#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {13457#true} is VALID [2022-02-20 22:05:07,421 INFO L290 TraceCheckUtils]: 48: Hoare triple {13457#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {13457#true} is VALID [2022-02-20 22:05:07,421 INFO L290 TraceCheckUtils]: 49: Hoare triple {13457#true} assume true; {13457#true} is VALID [2022-02-20 22:05:07,421 INFO L284 TraceCheckUtils]: 50: Hoare quadruple {13457#true} {13458#false} #917#return; {13458#false} is VALID [2022-02-20 22:05:07,421 INFO L290 TraceCheckUtils]: 51: Hoare triple {13458#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {13458#false} is VALID [2022-02-20 22:05:07,422 INFO L272 TraceCheckUtils]: 52: Hoare triple {13458#false} call ldv_spin_lock_check(); {13458#false} is VALID [2022-02-20 22:05:07,422 INFO L290 TraceCheckUtils]: 53: Hoare triple {13458#false} assume !(1 == ~ldv_init~0); {13458#false} is VALID [2022-02-20 22:05:07,422 INFO L272 TraceCheckUtils]: 54: Hoare triple {13458#false} call ldv_error(); {13458#false} is VALID [2022-02-20 22:05:07,422 INFO L290 TraceCheckUtils]: 55: Hoare triple {13458#false} assume !false; {13458#false} is VALID [2022-02-20 22:05:07,424 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:07,424 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:05:07,425 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452010579] [2022-02-20 22:05:07,425 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [452010579] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:05:07,425 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:05:07,425 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-02-20 22:05:07,425 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537839473] [2022-02-20 22:05:07,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:05:07,426 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 5.0) internal successors, (35), 4 states have internal predecessors, (35), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 56 [2022-02-20 22:05:07,427 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:05:07,427 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 5.0) internal successors, (35), 4 states have internal predecessors, (35), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:07,461 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 48 edges. 48 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:07,461 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-02-20 22:05:07,461 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:05:07,462 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-02-20 22:05:07,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-02-20 22:05:07,462 INFO L87 Difference]: Start difference. First operand 797 states and 1030 transitions. Second operand has 7 states, 7 states have (on average 5.0) internal successors, (35), 4 states have internal predecessors, (35), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:09,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:09,697 INFO L93 Difference]: Finished difference Result 1846 states and 2419 transitions. [2022-02-20 22:05:09,698 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-02-20 22:05:09,698 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 5.0) internal successors, (35), 4 states have internal predecessors, (35), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 56 [2022-02-20 22:05:09,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:05:09,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 5.0) internal successors, (35), 4 states have internal predecessors, (35), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:09,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 853 transitions. [2022-02-20 22:05:09,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 5.0) internal successors, (35), 4 states have internal predecessors, (35), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:09,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 853 transitions. [2022-02-20 22:05:09,733 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states and 853 transitions. [2022-02-20 22:05:10,430 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 853 edges. 853 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:10,510 INFO L225 Difference]: With dead ends: 1846 [2022-02-20 22:05:10,510 INFO L226 Difference]: Without dead ends: 1066 [2022-02-20 22:05:10,512 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=83, Unknown=0, NotChecked=0, Total=132 [2022-02-20 22:05:10,513 INFO L933 BasicCegarLoop]: 350 mSDtfsCounter, 667 mSDsluCounter, 589 mSDsCounter, 0 mSdLazyCounter, 486 mSolverCounterSat, 206 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 700 SdHoareTripleChecker+Valid, 939 SdHoareTripleChecker+Invalid, 692 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 206 IncrementalHoareTripleChecker+Valid, 486 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-02-20 22:05:10,513 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [700 Valid, 939 Invalid, 692 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [206 Valid, 486 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-02-20 22:05:10,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1066 states. [2022-02-20 22:05:10,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1066 to 805. [2022-02-20 22:05:10,548 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:05:10,550 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1066 states. Second operand has 805 states, 608 states have (on average 1.269736842105263) internal successors, (772), 617 states have internal predecessors, (772), 122 states have call successors, (122), 70 states have call predecessors, (122), 74 states have return successors, (138), 121 states have call predecessors, (138), 121 states have call successors, (138) [2022-02-20 22:05:10,552 INFO L74 IsIncluded]: Start isIncluded. First operand 1066 states. Second operand has 805 states, 608 states have (on average 1.269736842105263) internal successors, (772), 617 states have internal predecessors, (772), 122 states have call successors, (122), 70 states have call predecessors, (122), 74 states have return successors, (138), 121 states have call predecessors, (138), 121 states have call successors, (138) [2022-02-20 22:05:10,553 INFO L87 Difference]: Start difference. First operand 1066 states. Second operand has 805 states, 608 states have (on average 1.269736842105263) internal successors, (772), 617 states have internal predecessors, (772), 122 states have call successors, (122), 70 states have call predecessors, (122), 74 states have return successors, (138), 121 states have call predecessors, (138), 121 states have call successors, (138) [2022-02-20 22:05:10,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:10,617 INFO L93 Difference]: Finished difference Result 1066 states and 1393 transitions. [2022-02-20 22:05:10,617 INFO L276 IsEmpty]: Start isEmpty. Operand 1066 states and 1393 transitions. [2022-02-20 22:05:10,621 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:10,621 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:10,624 INFO L74 IsIncluded]: Start isIncluded. First operand has 805 states, 608 states have (on average 1.269736842105263) internal successors, (772), 617 states have internal predecessors, (772), 122 states have call successors, (122), 70 states have call predecessors, (122), 74 states have return successors, (138), 121 states have call predecessors, (138), 121 states have call successors, (138) Second operand 1066 states. [2022-02-20 22:05:10,625 INFO L87 Difference]: Start difference. First operand has 805 states, 608 states have (on average 1.269736842105263) internal successors, (772), 617 states have internal predecessors, (772), 122 states have call successors, (122), 70 states have call predecessors, (122), 74 states have return successors, (138), 121 states have call predecessors, (138), 121 states have call successors, (138) Second operand 1066 states. [2022-02-20 22:05:10,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:10,692 INFO L93 Difference]: Finished difference Result 1066 states and 1393 transitions. [2022-02-20 22:05:10,693 INFO L276 IsEmpty]: Start isEmpty. Operand 1066 states and 1393 transitions. [2022-02-20 22:05:10,696 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:10,696 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:10,696 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:05:10,696 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:05:10,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 805 states, 608 states have (on average 1.269736842105263) internal successors, (772), 617 states have internal predecessors, (772), 122 states have call successors, (122), 70 states have call predecessors, (122), 74 states have return successors, (138), 121 states have call predecessors, (138), 121 states have call successors, (138) [2022-02-20 22:05:10,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1032 transitions. [2022-02-20 22:05:10,751 INFO L78 Accepts]: Start accepts. Automaton has 805 states and 1032 transitions. Word has length 56 [2022-02-20 22:05:10,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:05:10,751 INFO L470 AbstractCegarLoop]: Abstraction has 805 states and 1032 transitions. [2022-02-20 22:05:10,752 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 5.0) internal successors, (35), 4 states have internal predecessors, (35), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:10,752 INFO L276 IsEmpty]: Start isEmpty. Operand 805 states and 1032 transitions. [2022-02-20 22:05:10,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2022-02-20 22:05:10,753 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:05:10,753 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:05:10,753 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2022-02-20 22:05:10,754 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:05:10,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:05:10,754 INFO L85 PathProgramCache]: Analyzing trace with hash -943497047, now seen corresponding path program 1 times [2022-02-20 22:05:10,769 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:05:10,769 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830922599] [2022-02-20 22:05:10,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:10,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:05:10,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:10,855 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:05:10,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:10,874 INFO L290 TraceCheckUtils]: 0: Hoare triple {19244#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {19209#true} is VALID [2022-02-20 22:05:10,875 INFO L290 TraceCheckUtils]: 1: Hoare triple {19209#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {19209#true} is VALID [2022-02-20 22:05:10,875 INFO L290 TraceCheckUtils]: 2: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,875 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {19209#true} {19211#(= ~ldv_irq_1_2~0 0)} #979#return; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,882 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 22 [2022-02-20 22:05:10,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:10,893 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:10,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:10,900 INFO L290 TraceCheckUtils]: 0: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {19209#true} is VALID [2022-02-20 22:05:10,900 INFO L290 TraceCheckUtils]: 1: Hoare triple {19209#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {19209#true} is VALID [2022-02-20 22:05:10,900 INFO L290 TraceCheckUtils]: 2: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,901 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {19209#true} {19209#true} #893#return; {19209#true} is VALID [2022-02-20 22:05:10,901 INFO L290 TraceCheckUtils]: 0: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {19209#true} is VALID [2022-02-20 22:05:10,901 INFO L272 TraceCheckUtils]: 1: Hoare triple {19209#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,901 INFO L290 TraceCheckUtils]: 2: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {19209#true} is VALID [2022-02-20 22:05:10,902 INFO L290 TraceCheckUtils]: 3: Hoare triple {19209#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {19209#true} is VALID [2022-02-20 22:05:10,902 INFO L290 TraceCheckUtils]: 4: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,902 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {19209#true} {19209#true} #893#return; {19209#true} is VALID [2022-02-20 22:05:10,902 INFO L290 TraceCheckUtils]: 6: Hoare triple {19209#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {19209#true} is VALID [2022-02-20 22:05:10,902 INFO L290 TraceCheckUtils]: 7: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,902 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {19209#true} {19210#false} #915#return; {19210#false} is VALID [2022-02-20 22:05:10,903 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 34 [2022-02-20 22:05:10,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:10,920 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:10,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:10,926 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:10,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:10,931 INFO L290 TraceCheckUtils]: 0: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {19209#true} is VALID [2022-02-20 22:05:10,932 INFO L290 TraceCheckUtils]: 1: Hoare triple {19209#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {19209#true} is VALID [2022-02-20 22:05:10,932 INFO L290 TraceCheckUtils]: 2: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,932 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {19209#true} {19209#true} #893#return; {19209#true} is VALID [2022-02-20 22:05:10,932 INFO L290 TraceCheckUtils]: 0: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {19209#true} is VALID [2022-02-20 22:05:10,933 INFO L272 TraceCheckUtils]: 1: Hoare triple {19209#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,933 INFO L290 TraceCheckUtils]: 2: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {19209#true} is VALID [2022-02-20 22:05:10,933 INFO L290 TraceCheckUtils]: 3: Hoare triple {19209#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {19209#true} is VALID [2022-02-20 22:05:10,933 INFO L290 TraceCheckUtils]: 4: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,933 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {19209#true} {19209#true} #893#return; {19209#true} is VALID [2022-02-20 22:05:10,933 INFO L290 TraceCheckUtils]: 6: Hoare triple {19209#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {19209#true} is VALID [2022-02-20 22:05:10,934 INFO L290 TraceCheckUtils]: 7: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,934 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {19209#true} {19209#true} #927#return; {19209#true} is VALID [2022-02-20 22:05:10,934 INFO L290 TraceCheckUtils]: 0: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {19209#true} is VALID [2022-02-20 22:05:10,935 INFO L272 TraceCheckUtils]: 1: Hoare triple {19209#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,935 INFO L290 TraceCheckUtils]: 2: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {19209#true} is VALID [2022-02-20 22:05:10,936 INFO L272 TraceCheckUtils]: 3: Hoare triple {19209#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,936 INFO L290 TraceCheckUtils]: 4: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {19209#true} is VALID [2022-02-20 22:05:10,936 INFO L290 TraceCheckUtils]: 5: Hoare triple {19209#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {19209#true} is VALID [2022-02-20 22:05:10,936 INFO L290 TraceCheckUtils]: 6: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,936 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {19209#true} {19209#true} #893#return; {19209#true} is VALID [2022-02-20 22:05:10,936 INFO L290 TraceCheckUtils]: 8: Hoare triple {19209#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {19209#true} is VALID [2022-02-20 22:05:10,936 INFO L290 TraceCheckUtils]: 9: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,937 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {19209#true} {19209#true} #927#return; {19209#true} is VALID [2022-02-20 22:05:10,937 INFO L290 TraceCheckUtils]: 11: Hoare triple {19209#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {19209#true} is VALID [2022-02-20 22:05:10,937 INFO L290 TraceCheckUtils]: 12: Hoare triple {19209#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {19209#true} is VALID [2022-02-20 22:05:10,937 INFO L290 TraceCheckUtils]: 13: Hoare triple {19209#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {19209#true} is VALID [2022-02-20 22:05:10,937 INFO L290 TraceCheckUtils]: 14: Hoare triple {19209#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {19209#true} is VALID [2022-02-20 22:05:10,937 INFO L290 TraceCheckUtils]: 15: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,937 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {19209#true} {19210#false} #917#return; {19210#false} is VALID [2022-02-20 22:05:10,938 INFO L290 TraceCheckUtils]: 0: Hoare triple {19209#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,938 INFO L290 TraceCheckUtils]: 1: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,939 INFO L272 TraceCheckUtils]: 2: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {19244#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,939 INFO L290 TraceCheckUtils]: 3: Hoare triple {19244#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {19209#true} is VALID [2022-02-20 22:05:10,939 INFO L290 TraceCheckUtils]: 4: Hoare triple {19209#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {19209#true} is VALID [2022-02-20 22:05:10,939 INFO L290 TraceCheckUtils]: 5: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,940 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {19209#true} {19211#(= ~ldv_irq_1_2~0 0)} #979#return; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,940 INFO L290 TraceCheckUtils]: 7: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,941 INFO L290 TraceCheckUtils]: 8: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,941 INFO L290 TraceCheckUtils]: 9: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,941 INFO L290 TraceCheckUtils]: 10: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,942 INFO L290 TraceCheckUtils]: 11: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,943 INFO L290 TraceCheckUtils]: 12: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume main_#t~switch236#1; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,943 INFO L290 TraceCheckUtils]: 13: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,943 INFO L290 TraceCheckUtils]: 14: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,944 INFO L290 TraceCheckUtils]: 15: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 2 == choose_interrupt_1_~tmp~23#1; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,944 INFO L290 TraceCheckUtils]: 16: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} assume choose_interrupt_1_#t~switch223#1; {19211#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:10,945 INFO L272 TraceCheckUtils]: 17: Hoare triple {19211#(= ~ldv_irq_1_2~0 0)} call choose_interrupt_1_#t~ret226#1 := ldv_irq_1(~ldv_irq_1_2~0, ~ldv_irq_line_1_2~0, ~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset); {19216#(= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:10,945 INFO L290 TraceCheckUtils]: 18: Hoare triple {19216#(= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {19217#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:10,946 INFO L290 TraceCheckUtils]: 19: Hoare triple {19217#(= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {19210#false} is VALID [2022-02-20 22:05:10,946 INFO L290 TraceCheckUtils]: 20: Hoare triple {19210#false} assume #t~switch220#1; {19210#false} is VALID [2022-02-20 22:05:10,946 INFO L290 TraceCheckUtils]: 21: Hoare triple {19210#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {19210#false} is VALID [2022-02-20 22:05:10,946 INFO L272 TraceCheckUtils]: 22: Hoare triple {19210#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,946 INFO L290 TraceCheckUtils]: 23: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {19209#true} is VALID [2022-02-20 22:05:10,947 INFO L272 TraceCheckUtils]: 24: Hoare triple {19209#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,947 INFO L290 TraceCheckUtils]: 25: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {19209#true} is VALID [2022-02-20 22:05:10,947 INFO L290 TraceCheckUtils]: 26: Hoare triple {19209#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {19209#true} is VALID [2022-02-20 22:05:10,947 INFO L290 TraceCheckUtils]: 27: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,947 INFO L284 TraceCheckUtils]: 28: Hoare quadruple {19209#true} {19209#true} #893#return; {19209#true} is VALID [2022-02-20 22:05:10,947 INFO L290 TraceCheckUtils]: 29: Hoare triple {19209#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {19209#true} is VALID [2022-02-20 22:05:10,947 INFO L290 TraceCheckUtils]: 30: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,948 INFO L284 TraceCheckUtils]: 31: Hoare quadruple {19209#true} {19210#false} #915#return; {19210#false} is VALID [2022-02-20 22:05:10,948 INFO L290 TraceCheckUtils]: 32: Hoare triple {19210#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {19210#false} is VALID [2022-02-20 22:05:10,948 INFO L290 TraceCheckUtils]: 33: Hoare triple {19210#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {19210#false} is VALID [2022-02-20 22:05:10,948 INFO L272 TraceCheckUtils]: 34: Hoare triple {19210#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,948 INFO L290 TraceCheckUtils]: 35: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {19209#true} is VALID [2022-02-20 22:05:10,949 INFO L272 TraceCheckUtils]: 36: Hoare triple {19209#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,949 INFO L290 TraceCheckUtils]: 37: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {19209#true} is VALID [2022-02-20 22:05:10,949 INFO L272 TraceCheckUtils]: 38: Hoare triple {19209#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:10,950 INFO L290 TraceCheckUtils]: 39: Hoare triple {19245#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {19209#true} is VALID [2022-02-20 22:05:10,950 INFO L290 TraceCheckUtils]: 40: Hoare triple {19209#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {19209#true} is VALID [2022-02-20 22:05:10,950 INFO L290 TraceCheckUtils]: 41: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,950 INFO L284 TraceCheckUtils]: 42: Hoare quadruple {19209#true} {19209#true} #893#return; {19209#true} is VALID [2022-02-20 22:05:10,950 INFO L290 TraceCheckUtils]: 43: Hoare triple {19209#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {19209#true} is VALID [2022-02-20 22:05:10,950 INFO L290 TraceCheckUtils]: 44: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,950 INFO L284 TraceCheckUtils]: 45: Hoare quadruple {19209#true} {19209#true} #927#return; {19209#true} is VALID [2022-02-20 22:05:10,950 INFO L290 TraceCheckUtils]: 46: Hoare triple {19209#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {19209#true} is VALID [2022-02-20 22:05:10,951 INFO L290 TraceCheckUtils]: 47: Hoare triple {19209#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {19209#true} is VALID [2022-02-20 22:05:10,951 INFO L290 TraceCheckUtils]: 48: Hoare triple {19209#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {19209#true} is VALID [2022-02-20 22:05:10,951 INFO L290 TraceCheckUtils]: 49: Hoare triple {19209#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {19209#true} is VALID [2022-02-20 22:05:10,951 INFO L290 TraceCheckUtils]: 50: Hoare triple {19209#true} assume true; {19209#true} is VALID [2022-02-20 22:05:10,951 INFO L284 TraceCheckUtils]: 51: Hoare quadruple {19209#true} {19210#false} #917#return; {19210#false} is VALID [2022-02-20 22:05:10,951 INFO L290 TraceCheckUtils]: 52: Hoare triple {19210#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {19210#false} is VALID [2022-02-20 22:05:10,951 INFO L272 TraceCheckUtils]: 53: Hoare triple {19210#false} call ldv_spin_lock_check(); {19210#false} is VALID [2022-02-20 22:05:10,952 INFO L290 TraceCheckUtils]: 54: Hoare triple {19210#false} assume !(1 == ~ldv_init~0); {19210#false} is VALID [2022-02-20 22:05:10,952 INFO L272 TraceCheckUtils]: 55: Hoare triple {19210#false} call ldv_error(); {19210#false} is VALID [2022-02-20 22:05:10,952 INFO L290 TraceCheckUtils]: 56: Hoare triple {19210#false} assume !false; {19210#false} is VALID [2022-02-20 22:05:10,953 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:10,953 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:05:10,953 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830922599] [2022-02-20 22:05:10,953 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830922599] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:05:10,953 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:05:10,953 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-02-20 22:05:10,954 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47344783] [2022-02-20 22:05:10,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:05:10,954 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 5.142857142857143) internal successors, (36), 4 states have internal predecessors, (36), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 57 [2022-02-20 22:05:10,954 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:05:10,955 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 5.142857142857143) internal successors, (36), 4 states have internal predecessors, (36), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:10,992 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 49 edges. 49 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:10,992 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-02-20 22:05:10,992 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:05:10,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-02-20 22:05:10,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-02-20 22:05:10,993 INFO L87 Difference]: Start difference. First operand 805 states and 1032 transitions. Second operand has 7 states, 7 states have (on average 5.142857142857143) internal successors, (36), 4 states have internal predecessors, (36), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:13,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:13,084 INFO L93 Difference]: Finished difference Result 1705 states and 2210 transitions. [2022-02-20 22:05:13,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-02-20 22:05:13,085 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 5.142857142857143) internal successors, (36), 4 states have internal predecessors, (36), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 57 [2022-02-20 22:05:13,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:05:13,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 5.142857142857143) internal successors, (36), 4 states have internal predecessors, (36), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:13,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 848 transitions. [2022-02-20 22:05:13,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 5.142857142857143) internal successors, (36), 4 states have internal predecessors, (36), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:13,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 848 transitions. [2022-02-20 22:05:13,116 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 8 states and 848 transitions. [2022-02-20 22:05:13,774 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 848 edges. 848 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:13,832 INFO L225 Difference]: With dead ends: 1705 [2022-02-20 22:05:13,832 INFO L226 Difference]: Without dead ends: 917 [2022-02-20 22:05:13,834 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=83, Unknown=0, NotChecked=0, Total=132 [2022-02-20 22:05:13,835 INFO L933 BasicCegarLoop]: 348 mSDtfsCounter, 661 mSDsluCounter, 585 mSDsCounter, 0 mSdLazyCounter, 484 mSolverCounterSat, 206 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 694 SdHoareTripleChecker+Valid, 933 SdHoareTripleChecker+Invalid, 690 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 206 IncrementalHoareTripleChecker+Valid, 484 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-02-20 22:05:13,835 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [694 Valid, 933 Invalid, 690 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [206 Valid, 484 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-02-20 22:05:13,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 917 states. [2022-02-20 22:05:13,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 917 to 719. [2022-02-20 22:05:13,866 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:05:13,868 INFO L82 GeneralOperation]: Start isEquivalent. First operand 917 states. Second operand has 719 states, 543 states have (on average 1.2615101289134438) internal successors, (685), 548 states have internal predecessors, (685), 106 states have call successors, (106), 65 states have call predecessors, (106), 69 states have return successors, (121), 107 states have call predecessors, (121), 105 states have call successors, (121) [2022-02-20 22:05:13,870 INFO L74 IsIncluded]: Start isIncluded. First operand 917 states. Second operand has 719 states, 543 states have (on average 1.2615101289134438) internal successors, (685), 548 states have internal predecessors, (685), 106 states have call successors, (106), 65 states have call predecessors, (106), 69 states have return successors, (121), 107 states have call predecessors, (121), 105 states have call successors, (121) [2022-02-20 22:05:13,871 INFO L87 Difference]: Start difference. First operand 917 states. Second operand has 719 states, 543 states have (on average 1.2615101289134438) internal successors, (685), 548 states have internal predecessors, (685), 106 states have call successors, (106), 65 states have call predecessors, (106), 69 states have return successors, (121), 107 states have call predecessors, (121), 105 states have call successors, (121) [2022-02-20 22:05:13,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:13,919 INFO L93 Difference]: Finished difference Result 917 states and 1182 transitions. [2022-02-20 22:05:13,919 INFO L276 IsEmpty]: Start isEmpty. Operand 917 states and 1182 transitions. [2022-02-20 22:05:13,922 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:13,922 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:13,924 INFO L74 IsIncluded]: Start isIncluded. First operand has 719 states, 543 states have (on average 1.2615101289134438) internal successors, (685), 548 states have internal predecessors, (685), 106 states have call successors, (106), 65 states have call predecessors, (106), 69 states have return successors, (121), 107 states have call predecessors, (121), 105 states have call successors, (121) Second operand 917 states. [2022-02-20 22:05:13,925 INFO L87 Difference]: Start difference. First operand has 719 states, 543 states have (on average 1.2615101289134438) internal successors, (685), 548 states have internal predecessors, (685), 106 states have call successors, (106), 65 states have call predecessors, (106), 69 states have return successors, (121), 107 states have call predecessors, (121), 105 states have call successors, (121) Second operand 917 states. [2022-02-20 22:05:13,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:13,975 INFO L93 Difference]: Finished difference Result 917 states and 1182 transitions. [2022-02-20 22:05:13,975 INFO L276 IsEmpty]: Start isEmpty. Operand 917 states and 1182 transitions. [2022-02-20 22:05:13,978 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:13,978 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:13,978 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:05:13,978 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:05:13,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 719 states, 543 states have (on average 1.2615101289134438) internal successors, (685), 548 states have internal predecessors, (685), 106 states have call successors, (106), 65 states have call predecessors, (106), 69 states have return successors, (121), 107 states have call predecessors, (121), 105 states have call successors, (121) [2022-02-20 22:05:14,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 719 states to 719 states and 912 transitions. [2022-02-20 22:05:14,019 INFO L78 Accepts]: Start accepts. Automaton has 719 states and 912 transitions. Word has length 57 [2022-02-20 22:05:14,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:05:14,019 INFO L470 AbstractCegarLoop]: Abstraction has 719 states and 912 transitions. [2022-02-20 22:05:14,019 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 5.142857142857143) internal successors, (36), 4 states have internal predecessors, (36), 3 states have call successors, (8), 4 states have call predecessors, (8), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2022-02-20 22:05:14,019 INFO L276 IsEmpty]: Start isEmpty. Operand 719 states and 912 transitions. [2022-02-20 22:05:14,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-02-20 22:05:14,021 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:05:14,021 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:05:14,021 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-02-20 22:05:14,021 INFO L402 AbstractCegarLoop]: === Iteration 7 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:05:14,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:05:14,022 INFO L85 PathProgramCache]: Analyzing trace with hash 1665561776, now seen corresponding path program 1 times [2022-02-20 22:05:14,022 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:05:14,022 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [995872177] [2022-02-20 22:05:14,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:14,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:05:14,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,116 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:05:14,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,131 INFO L290 TraceCheckUtils]: 0: Hoare triple {24398#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {24357#true} is VALID [2022-02-20 22:05:14,131 INFO L290 TraceCheckUtils]: 1: Hoare triple {24357#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,131 INFO L290 TraceCheckUtils]: 2: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,132 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {24357#true} {24359#(= ~ldv_irq_1_0~0 0)} #979#return; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,142 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 15 [2022-02-20 22:05:14,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,170 INFO L290 TraceCheckUtils]: 0: Hoare triple {24399#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {24357#true} is VALID [2022-02-20 22:05:14,171 INFO L290 TraceCheckUtils]: 1: Hoare triple {24357#true} assume !(0 != ~state#1); {24371#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:14,171 INFO L290 TraceCheckUtils]: 2: Hoare triple {24371#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {24400#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:14,172 INFO L290 TraceCheckUtils]: 3: Hoare triple {24400#(= |ldv_irq_1_#res#1| 0)} assume true; {24400#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:14,173 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {24400#(= |ldv_irq_1_#res#1| 0)} {24359#(= ~ldv_irq_1_0~0 0)} #981#return; {24369#(= |ULTIMATE.start_choose_interrupt_1_#t~ret224#1| 0)} is VALID [2022-02-20 22:05:14,180 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 32 [2022-02-20 22:05:14,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,192 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:14,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,197 INFO L290 TraceCheckUtils]: 0: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {24357#true} is VALID [2022-02-20 22:05:14,197 INFO L290 TraceCheckUtils]: 1: Hoare triple {24357#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,197 INFO L290 TraceCheckUtils]: 2: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,197 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {24357#true} {24357#true} #893#return; {24357#true} is VALID [2022-02-20 22:05:14,197 INFO L290 TraceCheckUtils]: 0: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {24357#true} is VALID [2022-02-20 22:05:14,198 INFO L272 TraceCheckUtils]: 1: Hoare triple {24357#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,198 INFO L290 TraceCheckUtils]: 2: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {24357#true} is VALID [2022-02-20 22:05:14,198 INFO L290 TraceCheckUtils]: 3: Hoare triple {24357#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,198 INFO L290 TraceCheckUtils]: 4: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,198 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {24357#true} {24357#true} #893#return; {24357#true} is VALID [2022-02-20 22:05:14,198 INFO L290 TraceCheckUtils]: 6: Hoare triple {24357#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {24357#true} is VALID [2022-02-20 22:05:14,199 INFO L290 TraceCheckUtils]: 7: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,199 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {24357#true} {24358#false} #915#return; {24358#false} is VALID [2022-02-20 22:05:14,199 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 44 [2022-02-20 22:05:14,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,208 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:14,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,214 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:14,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,221 INFO L290 TraceCheckUtils]: 0: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {24357#true} is VALID [2022-02-20 22:05:14,221 INFO L290 TraceCheckUtils]: 1: Hoare triple {24357#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,221 INFO L290 TraceCheckUtils]: 2: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,221 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {24357#true} {24357#true} #893#return; {24357#true} is VALID [2022-02-20 22:05:14,221 INFO L290 TraceCheckUtils]: 0: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {24357#true} is VALID [2022-02-20 22:05:14,222 INFO L272 TraceCheckUtils]: 1: Hoare triple {24357#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,222 INFO L290 TraceCheckUtils]: 2: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {24357#true} is VALID [2022-02-20 22:05:14,222 INFO L290 TraceCheckUtils]: 3: Hoare triple {24357#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,222 INFO L290 TraceCheckUtils]: 4: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,223 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {24357#true} {24357#true} #893#return; {24357#true} is VALID [2022-02-20 22:05:14,223 INFO L290 TraceCheckUtils]: 6: Hoare triple {24357#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {24357#true} is VALID [2022-02-20 22:05:14,223 INFO L290 TraceCheckUtils]: 7: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,223 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {24357#true} {24357#true} #927#return; {24357#true} is VALID [2022-02-20 22:05:14,223 INFO L290 TraceCheckUtils]: 0: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {24357#true} is VALID [2022-02-20 22:05:14,224 INFO L272 TraceCheckUtils]: 1: Hoare triple {24357#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,224 INFO L290 TraceCheckUtils]: 2: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {24357#true} is VALID [2022-02-20 22:05:14,224 INFO L272 TraceCheckUtils]: 3: Hoare triple {24357#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,225 INFO L290 TraceCheckUtils]: 4: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {24357#true} is VALID [2022-02-20 22:05:14,225 INFO L290 TraceCheckUtils]: 5: Hoare triple {24357#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,225 INFO L290 TraceCheckUtils]: 6: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,225 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {24357#true} {24357#true} #893#return; {24357#true} is VALID [2022-02-20 22:05:14,225 INFO L290 TraceCheckUtils]: 8: Hoare triple {24357#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {24357#true} is VALID [2022-02-20 22:05:14,225 INFO L290 TraceCheckUtils]: 9: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,225 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {24357#true} {24357#true} #927#return; {24357#true} is VALID [2022-02-20 22:05:14,226 INFO L290 TraceCheckUtils]: 11: Hoare triple {24357#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {24357#true} is VALID [2022-02-20 22:05:14,226 INFO L290 TraceCheckUtils]: 12: Hoare triple {24357#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {24357#true} is VALID [2022-02-20 22:05:14,226 INFO L290 TraceCheckUtils]: 13: Hoare triple {24357#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {24357#true} is VALID [2022-02-20 22:05:14,226 INFO L290 TraceCheckUtils]: 14: Hoare triple {24357#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {24357#true} is VALID [2022-02-20 22:05:14,226 INFO L290 TraceCheckUtils]: 15: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,226 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {24357#true} {24358#false} #917#return; {24358#false} is VALID [2022-02-20 22:05:14,227 INFO L290 TraceCheckUtils]: 0: Hoare triple {24357#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,227 INFO L290 TraceCheckUtils]: 1: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,228 INFO L272 TraceCheckUtils]: 2: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {24398#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,228 INFO L290 TraceCheckUtils]: 3: Hoare triple {24398#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {24357#true} is VALID [2022-02-20 22:05:14,228 INFO L290 TraceCheckUtils]: 4: Hoare triple {24357#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,228 INFO L290 TraceCheckUtils]: 5: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,229 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {24357#true} {24359#(= ~ldv_irq_1_0~0 0)} #979#return; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,229 INFO L290 TraceCheckUtils]: 7: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,229 INFO L290 TraceCheckUtils]: 8: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,230 INFO L290 TraceCheckUtils]: 9: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,230 INFO L290 TraceCheckUtils]: 10: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,230 INFO L290 TraceCheckUtils]: 11: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,231 INFO L290 TraceCheckUtils]: 12: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,231 INFO L290 TraceCheckUtils]: 13: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,231 INFO L290 TraceCheckUtils]: 14: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,232 INFO L272 TraceCheckUtils]: 15: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {24399#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} is VALID [2022-02-20 22:05:14,232 INFO L290 TraceCheckUtils]: 16: Hoare triple {24399#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {24357#true} is VALID [2022-02-20 22:05:14,233 INFO L290 TraceCheckUtils]: 17: Hoare triple {24357#true} assume !(0 != ~state#1); {24371#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:14,233 INFO L290 TraceCheckUtils]: 18: Hoare triple {24371#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {24400#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:14,233 INFO L290 TraceCheckUtils]: 19: Hoare triple {24400#(= |ldv_irq_1_#res#1| 0)} assume true; {24400#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:14,234 INFO L284 TraceCheckUtils]: 20: Hoare quadruple {24400#(= |ldv_irq_1_#res#1| 0)} {24359#(= ~ldv_irq_1_0~0 0)} #981#return; {24369#(= |ULTIMATE.start_choose_interrupt_1_#t~ret224#1| 0)} is VALID [2022-02-20 22:05:14,235 INFO L290 TraceCheckUtils]: 21: Hoare triple {24369#(= |ULTIMATE.start_choose_interrupt_1_#t~ret224#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret224#1 && choose_interrupt_1_#t~ret224#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret224#1;havoc choose_interrupt_1_#t~ret224#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,235 INFO L290 TraceCheckUtils]: 22: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,236 INFO L290 TraceCheckUtils]: 23: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,236 INFO L290 TraceCheckUtils]: 24: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,236 INFO L290 TraceCheckUtils]: 25: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,237 INFO L290 TraceCheckUtils]: 26: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {24359#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,237 INFO L272 TraceCheckUtils]: 27: Hoare triple {24359#(= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {24370#(= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:14,240 INFO L290 TraceCheckUtils]: 28: Hoare triple {24370#(= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {24371#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:14,241 INFO L290 TraceCheckUtils]: 29: Hoare triple {24371#(= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {24358#false} is VALID [2022-02-20 22:05:14,241 INFO L290 TraceCheckUtils]: 30: Hoare triple {24358#false} assume #t~switch220#1; {24358#false} is VALID [2022-02-20 22:05:14,241 INFO L290 TraceCheckUtils]: 31: Hoare triple {24358#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {24358#false} is VALID [2022-02-20 22:05:14,241 INFO L272 TraceCheckUtils]: 32: Hoare triple {24358#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,241 INFO L290 TraceCheckUtils]: 33: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {24357#true} is VALID [2022-02-20 22:05:14,242 INFO L272 TraceCheckUtils]: 34: Hoare triple {24357#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,242 INFO L290 TraceCheckUtils]: 35: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {24357#true} is VALID [2022-02-20 22:05:14,242 INFO L290 TraceCheckUtils]: 36: Hoare triple {24357#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,242 INFO L290 TraceCheckUtils]: 37: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,242 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {24357#true} {24357#true} #893#return; {24357#true} is VALID [2022-02-20 22:05:14,242 INFO L290 TraceCheckUtils]: 39: Hoare triple {24357#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {24357#true} is VALID [2022-02-20 22:05:14,243 INFO L290 TraceCheckUtils]: 40: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,243 INFO L284 TraceCheckUtils]: 41: Hoare quadruple {24357#true} {24358#false} #915#return; {24358#false} is VALID [2022-02-20 22:05:14,243 INFO L290 TraceCheckUtils]: 42: Hoare triple {24358#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {24358#false} is VALID [2022-02-20 22:05:14,243 INFO L290 TraceCheckUtils]: 43: Hoare triple {24358#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {24358#false} is VALID [2022-02-20 22:05:14,243 INFO L272 TraceCheckUtils]: 44: Hoare triple {24358#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,243 INFO L290 TraceCheckUtils]: 45: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {24357#true} is VALID [2022-02-20 22:05:14,244 INFO L272 TraceCheckUtils]: 46: Hoare triple {24357#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,244 INFO L290 TraceCheckUtils]: 47: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {24357#true} is VALID [2022-02-20 22:05:14,245 INFO L272 TraceCheckUtils]: 48: Hoare triple {24357#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:14,245 INFO L290 TraceCheckUtils]: 49: Hoare triple {24401#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {24357#true} is VALID [2022-02-20 22:05:14,245 INFO L290 TraceCheckUtils]: 50: Hoare triple {24357#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,245 INFO L290 TraceCheckUtils]: 51: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,245 INFO L284 TraceCheckUtils]: 52: Hoare quadruple {24357#true} {24357#true} #893#return; {24357#true} is VALID [2022-02-20 22:05:14,245 INFO L290 TraceCheckUtils]: 53: Hoare triple {24357#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {24357#true} is VALID [2022-02-20 22:05:14,245 INFO L290 TraceCheckUtils]: 54: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,246 INFO L284 TraceCheckUtils]: 55: Hoare quadruple {24357#true} {24357#true} #927#return; {24357#true} is VALID [2022-02-20 22:05:14,246 INFO L290 TraceCheckUtils]: 56: Hoare triple {24357#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {24357#true} is VALID [2022-02-20 22:05:14,246 INFO L290 TraceCheckUtils]: 57: Hoare triple {24357#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {24357#true} is VALID [2022-02-20 22:05:14,246 INFO L290 TraceCheckUtils]: 58: Hoare triple {24357#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {24357#true} is VALID [2022-02-20 22:05:14,246 INFO L290 TraceCheckUtils]: 59: Hoare triple {24357#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {24357#true} is VALID [2022-02-20 22:05:14,246 INFO L290 TraceCheckUtils]: 60: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,246 INFO L284 TraceCheckUtils]: 61: Hoare quadruple {24357#true} {24358#false} #917#return; {24358#false} is VALID [2022-02-20 22:05:14,247 INFO L290 TraceCheckUtils]: 62: Hoare triple {24358#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {24358#false} is VALID [2022-02-20 22:05:14,247 INFO L272 TraceCheckUtils]: 63: Hoare triple {24358#false} call ldv_spin_lock_check(); {24358#false} is VALID [2022-02-20 22:05:14,247 INFO L290 TraceCheckUtils]: 64: Hoare triple {24358#false} assume !(1 == ~ldv_init~0); {24358#false} is VALID [2022-02-20 22:05:14,247 INFO L272 TraceCheckUtils]: 65: Hoare triple {24358#false} call ldv_error(); {24358#false} is VALID [2022-02-20 22:05:14,247 INFO L290 TraceCheckUtils]: 66: Hoare triple {24358#false} assume !false; {24358#false} is VALID [2022-02-20 22:05:14,248 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2022-02-20 22:05:14,248 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:05:14,248 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [995872177] [2022-02-20 22:05:14,248 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [995872177] provided 0 perfect and 1 imperfect interpolant sequences [2022-02-20 22:05:14,248 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [574367162] [2022-02-20 22:05:14,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:14,249 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-02-20 22:05:14,249 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:05:14,255 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-02-20 22:05:14,318 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-02-20 22:05:14,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,529 INFO L263 TraceCheckSpWp]: Trace formula consists of 627 conjuncts, 7 conjunts are in the unsatisfiable core [2022-02-20 22:05:14,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:14,598 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-02-20 22:05:14,901 INFO L290 TraceCheckUtils]: 0: Hoare triple {24357#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {24357#true} is VALID [2022-02-20 22:05:14,901 INFO L290 TraceCheckUtils]: 1: Hoare triple {24357#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {24357#true} is VALID [2022-02-20 22:05:14,901 INFO L272 TraceCheckUtils]: 2: Hoare triple {24357#true} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {24357#true} is VALID [2022-02-20 22:05:14,901 INFO L290 TraceCheckUtils]: 3: Hoare triple {24357#true} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {24357#true} is VALID [2022-02-20 22:05:14,901 INFO L290 TraceCheckUtils]: 4: Hoare triple {24357#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {24357#true} is VALID [2022-02-20 22:05:14,902 INFO L290 TraceCheckUtils]: 5: Hoare triple {24357#true} assume true; {24357#true} is VALID [2022-02-20 22:05:14,902 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {24357#true} {24357#true} #979#return; {24357#true} is VALID [2022-02-20 22:05:14,902 INFO L290 TraceCheckUtils]: 7: Hoare triple {24357#true} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {24357#true} is VALID [2022-02-20 22:05:14,902 INFO L290 TraceCheckUtils]: 8: Hoare triple {24357#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {24357#true} is VALID [2022-02-20 22:05:14,902 INFO L290 TraceCheckUtils]: 9: Hoare triple {24357#true} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {24357#true} is VALID [2022-02-20 22:05:14,902 INFO L290 TraceCheckUtils]: 10: Hoare triple {24357#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {24357#true} is VALID [2022-02-20 22:05:14,902 INFO L290 TraceCheckUtils]: 11: Hoare triple {24357#true} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {24357#true} is VALID [2022-02-20 22:05:14,915 INFO L290 TraceCheckUtils]: 12: Hoare triple {24357#true} assume main_#t~switch236#1; {24357#true} is VALID [2022-02-20 22:05:14,915 INFO L290 TraceCheckUtils]: 13: Hoare triple {24357#true} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {24357#true} is VALID [2022-02-20 22:05:14,915 INFO L290 TraceCheckUtils]: 14: Hoare triple {24357#true} assume choose_interrupt_1_#t~switch223#1; {24357#true} is VALID [2022-02-20 22:05:14,915 INFO L272 TraceCheckUtils]: 15: Hoare triple {24357#true} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {24357#true} is VALID [2022-02-20 22:05:14,915 INFO L290 TraceCheckUtils]: 16: Hoare triple {24357#true} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {24357#true} is VALID [2022-02-20 22:05:14,921 INFO L290 TraceCheckUtils]: 17: Hoare triple {24357#true} assume !(0 != ~state#1); {24473#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:14,924 INFO L290 TraceCheckUtils]: 18: Hoare triple {24473#(<= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {24477#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:14,925 INFO L290 TraceCheckUtils]: 19: Hoare triple {24477#(<= |ldv_irq_1_#res#1| 0)} assume true; {24477#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:14,926 INFO L284 TraceCheckUtils]: 20: Hoare quadruple {24477#(<= |ldv_irq_1_#res#1| 0)} {24357#true} #981#return; {24484#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret224#1| 0)} is VALID [2022-02-20 22:05:14,926 INFO L290 TraceCheckUtils]: 21: Hoare triple {24484#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret224#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret224#1 && choose_interrupt_1_#t~ret224#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret224#1;havoc choose_interrupt_1_#t~ret224#1; {24488#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,926 INFO L290 TraceCheckUtils]: 22: Hoare triple {24488#(<= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {24488#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,927 INFO L290 TraceCheckUtils]: 23: Hoare triple {24488#(<= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {24488#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,927 INFO L290 TraceCheckUtils]: 24: Hoare triple {24488#(<= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {24488#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,927 INFO L290 TraceCheckUtils]: 25: Hoare triple {24488#(<= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {24488#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,928 INFO L290 TraceCheckUtils]: 26: Hoare triple {24488#(<= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {24488#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:14,928 INFO L272 TraceCheckUtils]: 27: Hoare triple {24488#(<= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {24507#(<= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:14,929 INFO L290 TraceCheckUtils]: 28: Hoare triple {24507#(<= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {24473#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:14,929 INFO L290 TraceCheckUtils]: 29: Hoare triple {24473#(<= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {24473#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:14,929 INFO L290 TraceCheckUtils]: 30: Hoare triple {24473#(<= |ldv_irq_1_~state#1| 0)} assume #t~switch220#1; {24473#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:14,934 INFO L290 TraceCheckUtils]: 31: Hoare triple {24473#(<= |ldv_irq_1_~state#1| 0)} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {24358#false} is VALID [2022-02-20 22:05:14,935 INFO L272 TraceCheckUtils]: 32: Hoare triple {24358#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {24358#false} is VALID [2022-02-20 22:05:14,935 INFO L290 TraceCheckUtils]: 33: Hoare triple {24358#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {24358#false} is VALID [2022-02-20 22:05:14,935 INFO L272 TraceCheckUtils]: 34: Hoare triple {24358#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {24358#false} is VALID [2022-02-20 22:05:14,935 INFO L290 TraceCheckUtils]: 35: Hoare triple {24358#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {24358#false} is VALID [2022-02-20 22:05:14,935 INFO L290 TraceCheckUtils]: 36: Hoare triple {24358#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {24358#false} is VALID [2022-02-20 22:05:14,935 INFO L290 TraceCheckUtils]: 37: Hoare triple {24358#false} assume true; {24358#false} is VALID [2022-02-20 22:05:14,935 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {24358#false} {24358#false} #893#return; {24358#false} is VALID [2022-02-20 22:05:14,935 INFO L290 TraceCheckUtils]: 39: Hoare triple {24358#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {24358#false} is VALID [2022-02-20 22:05:14,935 INFO L290 TraceCheckUtils]: 40: Hoare triple {24358#false} assume true; {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L284 TraceCheckUtils]: 41: Hoare quadruple {24358#false} {24358#false} #915#return; {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L290 TraceCheckUtils]: 42: Hoare triple {24358#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L290 TraceCheckUtils]: 43: Hoare triple {24358#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L272 TraceCheckUtils]: 44: Hoare triple {24358#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L290 TraceCheckUtils]: 45: Hoare triple {24358#false} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L272 TraceCheckUtils]: 46: Hoare triple {24358#false} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L290 TraceCheckUtils]: 47: Hoare triple {24358#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L272 TraceCheckUtils]: 48: Hoare triple {24358#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L290 TraceCheckUtils]: 49: Hoare triple {24358#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {24358#false} is VALID [2022-02-20 22:05:14,936 INFO L290 TraceCheckUtils]: 50: Hoare triple {24358#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L290 TraceCheckUtils]: 51: Hoare triple {24358#false} assume true; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L284 TraceCheckUtils]: 52: Hoare quadruple {24358#false} {24358#false} #893#return; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L290 TraceCheckUtils]: 53: Hoare triple {24358#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L290 TraceCheckUtils]: 54: Hoare triple {24358#false} assume true; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L284 TraceCheckUtils]: 55: Hoare quadruple {24358#false} {24358#false} #927#return; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L290 TraceCheckUtils]: 56: Hoare triple {24358#false} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L290 TraceCheckUtils]: 57: Hoare triple {24358#false} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L290 TraceCheckUtils]: 58: Hoare triple {24358#false} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L290 TraceCheckUtils]: 59: Hoare triple {24358#false} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {24358#false} is VALID [2022-02-20 22:05:14,937 INFO L290 TraceCheckUtils]: 60: Hoare triple {24358#false} assume true; {24358#false} is VALID [2022-02-20 22:05:14,938 INFO L284 TraceCheckUtils]: 61: Hoare quadruple {24358#false} {24358#false} #917#return; {24358#false} is VALID [2022-02-20 22:05:14,938 INFO L290 TraceCheckUtils]: 62: Hoare triple {24358#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {24358#false} is VALID [2022-02-20 22:05:14,938 INFO L272 TraceCheckUtils]: 63: Hoare triple {24358#false} call ldv_spin_lock_check(); {24358#false} is VALID [2022-02-20 22:05:14,938 INFO L290 TraceCheckUtils]: 64: Hoare triple {24358#false} assume !(1 == ~ldv_init~0); {24358#false} is VALID [2022-02-20 22:05:14,938 INFO L272 TraceCheckUtils]: 65: Hoare triple {24358#false} call ldv_error(); {24358#false} is VALID [2022-02-20 22:05:14,938 INFO L290 TraceCheckUtils]: 66: Hoare triple {24358#false} assume !false; {24358#false} is VALID [2022-02-20 22:05:14,938 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:14,939 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-02-20 22:05:14,939 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [574367162] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:05:14,939 INFO L191 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-02-20 22:05:14,939 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [10] total 15 [2022-02-20 22:05:14,939 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908868022] [2022-02-20 22:05:14,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:05:14,940 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.285714285714286) internal successors, (44), 5 states have internal predecessors, (44), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) Word has length 67 [2022-02-20 22:05:14,940 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:05:14,940 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 6.285714285714286) internal successors, (44), 5 states have internal predecessors, (44), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:14,988 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 59 edges. 59 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:14,989 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-02-20 22:05:14,989 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:05:14,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-02-20 22:05:14,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=176, Unknown=0, NotChecked=0, Total=210 [2022-02-20 22:05:14,990 INFO L87 Difference]: Start difference. First operand 719 states and 912 transitions. Second operand has 7 states, 7 states have (on average 6.285714285714286) internal successors, (44), 5 states have internal predecessors, (44), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:16,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:16,724 INFO L93 Difference]: Finished difference Result 1747 states and 2216 transitions. [2022-02-20 22:05:16,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-02-20 22:05:16,724 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.285714285714286) internal successors, (44), 5 states have internal predecessors, (44), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) Word has length 67 [2022-02-20 22:05:16,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:05:16,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 6.285714285714286) internal successors, (44), 5 states have internal predecessors, (44), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:16,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 1030 transitions. [2022-02-20 22:05:16,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 6.285714285714286) internal successors, (44), 5 states have internal predecessors, (44), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:16,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 1030 transitions. [2022-02-20 22:05:16,747 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states and 1030 transitions. [2022-02-20 22:05:17,469 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 1030 edges. 1030 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:17,528 INFO L225 Difference]: With dead ends: 1747 [2022-02-20 22:05:17,529 INFO L226 Difference]: Without dead ends: 1052 [2022-02-20 22:05:17,531 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=75, Invalid=387, Unknown=0, NotChecked=0, Total=462 [2022-02-20 22:05:17,532 INFO L933 BasicCegarLoop]: 406 mSDtfsCounter, 337 mSDsluCounter, 1958 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 341 SdHoareTripleChecker+Valid, 2364 SdHoareTripleChecker+Invalid, 57 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-02-20 22:05:17,532 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [341 Valid, 2364 Invalid, 57 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 54 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-02-20 22:05:17,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1052 states. [2022-02-20 22:05:17,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1052 to 1005. [2022-02-20 22:05:17,696 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:05:17,711 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1052 states. Second operand has 1005 states, 763 states have (on average 1.2699868938401049) internal successors, (969), 770 states have internal predecessors, (969), 146 states have call successors, (146), 89 states have call predecessors, (146), 95 states have return successors, (166), 147 states have call predecessors, (166), 145 states have call successors, (166) [2022-02-20 22:05:17,714 INFO L74 IsIncluded]: Start isIncluded. First operand 1052 states. Second operand has 1005 states, 763 states have (on average 1.2699868938401049) internal successors, (969), 770 states have internal predecessors, (969), 146 states have call successors, (146), 89 states have call predecessors, (146), 95 states have return successors, (166), 147 states have call predecessors, (166), 145 states have call successors, (166) [2022-02-20 22:05:17,716 INFO L87 Difference]: Start difference. First operand 1052 states. Second operand has 1005 states, 763 states have (on average 1.2699868938401049) internal successors, (969), 770 states have internal predecessors, (969), 146 states have call successors, (146), 89 states have call predecessors, (146), 95 states have return successors, (166), 147 states have call predecessors, (166), 145 states have call successors, (166) [2022-02-20 22:05:17,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:17,772 INFO L93 Difference]: Finished difference Result 1052 states and 1327 transitions. [2022-02-20 22:05:17,772 INFO L276 IsEmpty]: Start isEmpty. Operand 1052 states and 1327 transitions. [2022-02-20 22:05:17,775 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:17,775 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:17,779 INFO L74 IsIncluded]: Start isIncluded. First operand has 1005 states, 763 states have (on average 1.2699868938401049) internal successors, (969), 770 states have internal predecessors, (969), 146 states have call successors, (146), 89 states have call predecessors, (146), 95 states have return successors, (166), 147 states have call predecessors, (166), 145 states have call successors, (166) Second operand 1052 states. [2022-02-20 22:05:17,780 INFO L87 Difference]: Start difference. First operand has 1005 states, 763 states have (on average 1.2699868938401049) internal successors, (969), 770 states have internal predecessors, (969), 146 states have call successors, (146), 89 states have call predecessors, (146), 95 states have return successors, (166), 147 states have call predecessors, (166), 145 states have call successors, (166) Second operand 1052 states. [2022-02-20 22:05:17,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:17,839 INFO L93 Difference]: Finished difference Result 1052 states and 1327 transitions. [2022-02-20 22:05:17,839 INFO L276 IsEmpty]: Start isEmpty. Operand 1052 states and 1327 transitions. [2022-02-20 22:05:17,844 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:17,844 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:17,844 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:05:17,844 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:05:17,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1005 states, 763 states have (on average 1.2699868938401049) internal successors, (969), 770 states have internal predecessors, (969), 146 states have call successors, (146), 89 states have call predecessors, (146), 95 states have return successors, (166), 147 states have call predecessors, (166), 145 states have call successors, (166) [2022-02-20 22:05:17,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1005 states to 1005 states and 1281 transitions. [2022-02-20 22:05:17,901 INFO L78 Accepts]: Start accepts. Automaton has 1005 states and 1281 transitions. Word has length 67 [2022-02-20 22:05:17,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:05:17,901 INFO L470 AbstractCegarLoop]: Abstraction has 1005 states and 1281 transitions. [2022-02-20 22:05:17,902 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 6.285714285714286) internal successors, (44), 5 states have internal predecessors, (44), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:17,902 INFO L276 IsEmpty]: Start isEmpty. Operand 1005 states and 1281 transitions. [2022-02-20 22:05:17,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-02-20 22:05:17,904 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:05:17,904 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:05:17,931 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-02-20 22:05:18,119 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-02-20 22:05:18,120 INFO L402 AbstractCegarLoop]: === Iteration 8 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:05:18,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:05:18,120 INFO L85 PathProgramCache]: Analyzing trace with hash 2022790021, now seen corresponding path program 1 times [2022-02-20 22:05:18,121 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:05:18,121 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675432583] [2022-02-20 22:05:18,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:18,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:05:18,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,212 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:05:18,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,219 INFO L290 TraceCheckUtils]: 0: Hoare triple {30474#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {30432#true} is VALID [2022-02-20 22:05:18,219 INFO L290 TraceCheckUtils]: 1: Hoare triple {30432#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,219 INFO L290 TraceCheckUtils]: 2: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,220 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {30432#true} {30434#(= ~ldv_irq_1_1~0 0)} #979#return; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,232 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 16 [2022-02-20 22:05:18,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,253 INFO L290 TraceCheckUtils]: 0: Hoare triple {30475#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {30432#true} is VALID [2022-02-20 22:05:18,254 INFO L290 TraceCheckUtils]: 1: Hoare triple {30432#true} assume !(0 != ~state#1); {30447#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:18,254 INFO L290 TraceCheckUtils]: 2: Hoare triple {30447#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {30476#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:18,255 INFO L290 TraceCheckUtils]: 3: Hoare triple {30476#(= |ldv_irq_1_#res#1| 0)} assume true; {30476#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:18,256 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {30476#(= |ldv_irq_1_#res#1| 0)} {30434#(= ~ldv_irq_1_1~0 0)} #983#return; {30444#(= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} is VALID [2022-02-20 22:05:18,268 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 33 [2022-02-20 22:05:18,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,276 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:18,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,283 INFO L290 TraceCheckUtils]: 0: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {30432#true} is VALID [2022-02-20 22:05:18,283 INFO L290 TraceCheckUtils]: 1: Hoare triple {30432#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,283 INFO L290 TraceCheckUtils]: 2: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,283 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {30432#true} {30432#true} #893#return; {30432#true} is VALID [2022-02-20 22:05:18,284 INFO L290 TraceCheckUtils]: 0: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {30432#true} is VALID [2022-02-20 22:05:18,284 INFO L272 TraceCheckUtils]: 1: Hoare triple {30432#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,284 INFO L290 TraceCheckUtils]: 2: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {30432#true} is VALID [2022-02-20 22:05:18,285 INFO L290 TraceCheckUtils]: 3: Hoare triple {30432#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,285 INFO L290 TraceCheckUtils]: 4: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,285 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {30432#true} {30432#true} #893#return; {30432#true} is VALID [2022-02-20 22:05:18,285 INFO L290 TraceCheckUtils]: 6: Hoare triple {30432#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {30432#true} is VALID [2022-02-20 22:05:18,285 INFO L290 TraceCheckUtils]: 7: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,285 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {30432#true} {30433#false} #915#return; {30433#false} is VALID [2022-02-20 22:05:18,286 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 45 [2022-02-20 22:05:18,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,296 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:18,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,302 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:18,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,306 INFO L290 TraceCheckUtils]: 0: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {30432#true} is VALID [2022-02-20 22:05:18,306 INFO L290 TraceCheckUtils]: 1: Hoare triple {30432#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,307 INFO L290 TraceCheckUtils]: 2: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,307 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {30432#true} {30432#true} #893#return; {30432#true} is VALID [2022-02-20 22:05:18,307 INFO L290 TraceCheckUtils]: 0: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {30432#true} is VALID [2022-02-20 22:05:18,308 INFO L272 TraceCheckUtils]: 1: Hoare triple {30432#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,308 INFO L290 TraceCheckUtils]: 2: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {30432#true} is VALID [2022-02-20 22:05:18,308 INFO L290 TraceCheckUtils]: 3: Hoare triple {30432#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,308 INFO L290 TraceCheckUtils]: 4: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,308 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {30432#true} {30432#true} #893#return; {30432#true} is VALID [2022-02-20 22:05:18,308 INFO L290 TraceCheckUtils]: 6: Hoare triple {30432#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {30432#true} is VALID [2022-02-20 22:05:18,309 INFO L290 TraceCheckUtils]: 7: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,316 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {30432#true} {30432#true} #927#return; {30432#true} is VALID [2022-02-20 22:05:18,316 INFO L290 TraceCheckUtils]: 0: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {30432#true} is VALID [2022-02-20 22:05:18,317 INFO L272 TraceCheckUtils]: 1: Hoare triple {30432#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,317 INFO L290 TraceCheckUtils]: 2: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {30432#true} is VALID [2022-02-20 22:05:18,318 INFO L272 TraceCheckUtils]: 3: Hoare triple {30432#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,318 INFO L290 TraceCheckUtils]: 4: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {30432#true} is VALID [2022-02-20 22:05:18,318 INFO L290 TraceCheckUtils]: 5: Hoare triple {30432#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,318 INFO L290 TraceCheckUtils]: 6: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,318 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {30432#true} {30432#true} #893#return; {30432#true} is VALID [2022-02-20 22:05:18,318 INFO L290 TraceCheckUtils]: 8: Hoare triple {30432#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {30432#true} is VALID [2022-02-20 22:05:18,319 INFO L290 TraceCheckUtils]: 9: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,319 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {30432#true} {30432#true} #927#return; {30432#true} is VALID [2022-02-20 22:05:18,319 INFO L290 TraceCheckUtils]: 11: Hoare triple {30432#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {30432#true} is VALID [2022-02-20 22:05:18,319 INFO L290 TraceCheckUtils]: 12: Hoare triple {30432#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {30432#true} is VALID [2022-02-20 22:05:18,319 INFO L290 TraceCheckUtils]: 13: Hoare triple {30432#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {30432#true} is VALID [2022-02-20 22:05:18,319 INFO L290 TraceCheckUtils]: 14: Hoare triple {30432#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {30432#true} is VALID [2022-02-20 22:05:18,320 INFO L290 TraceCheckUtils]: 15: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,320 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {30432#true} {30433#false} #917#return; {30433#false} is VALID [2022-02-20 22:05:18,320 INFO L290 TraceCheckUtils]: 0: Hoare triple {30432#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,321 INFO L290 TraceCheckUtils]: 1: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,321 INFO L272 TraceCheckUtils]: 2: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {30474#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,322 INFO L290 TraceCheckUtils]: 3: Hoare triple {30474#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {30432#true} is VALID [2022-02-20 22:05:18,322 INFO L290 TraceCheckUtils]: 4: Hoare triple {30432#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,322 INFO L290 TraceCheckUtils]: 5: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,323 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {30432#true} {30434#(= ~ldv_irq_1_1~0 0)} #979#return; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,323 INFO L290 TraceCheckUtils]: 7: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,323 INFO L290 TraceCheckUtils]: 8: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,324 INFO L290 TraceCheckUtils]: 9: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,324 INFO L290 TraceCheckUtils]: 10: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,324 INFO L290 TraceCheckUtils]: 11: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,325 INFO L290 TraceCheckUtils]: 12: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} assume main_#t~switch236#1; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,325 INFO L290 TraceCheckUtils]: 13: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,325 INFO L290 TraceCheckUtils]: 14: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,326 INFO L290 TraceCheckUtils]: 15: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} assume choose_interrupt_1_#t~switch223#1; {30434#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:18,327 INFO L272 TraceCheckUtils]: 16: Hoare triple {30434#(= ~ldv_irq_1_1~0 0)} call choose_interrupt_1_#t~ret225#1 := ldv_irq_1(~ldv_irq_1_1~0, ~ldv_irq_line_1_1~0, ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset); {30475#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} is VALID [2022-02-20 22:05:18,327 INFO L290 TraceCheckUtils]: 17: Hoare triple {30475#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {30432#true} is VALID [2022-02-20 22:05:18,328 INFO L290 TraceCheckUtils]: 18: Hoare triple {30432#true} assume !(0 != ~state#1); {30447#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:18,328 INFO L290 TraceCheckUtils]: 19: Hoare triple {30447#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {30476#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:18,328 INFO L290 TraceCheckUtils]: 20: Hoare triple {30476#(= |ldv_irq_1_#res#1| 0)} assume true; {30476#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:18,329 INFO L284 TraceCheckUtils]: 21: Hoare quadruple {30476#(= |ldv_irq_1_#res#1| 0)} {30434#(= ~ldv_irq_1_1~0 0)} #983#return; {30444#(= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} is VALID [2022-02-20 22:05:18,330 INFO L290 TraceCheckUtils]: 22: Hoare triple {30444#(= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret225#1 && choose_interrupt_1_#t~ret225#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret225#1;havoc choose_interrupt_1_#t~ret225#1; {30445#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,330 INFO L290 TraceCheckUtils]: 23: Hoare triple {30445#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {30445#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,331 INFO L290 TraceCheckUtils]: 24: Hoare triple {30445#(= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {30445#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,331 INFO L290 TraceCheckUtils]: 25: Hoare triple {30445#(= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {30445#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,331 INFO L290 TraceCheckUtils]: 26: Hoare triple {30445#(= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {30445#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,332 INFO L290 TraceCheckUtils]: 27: Hoare triple {30445#(= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {30445#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,333 INFO L272 TraceCheckUtils]: 28: Hoare triple {30445#(= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {30446#(= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:18,333 INFO L290 TraceCheckUtils]: 29: Hoare triple {30446#(= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {30447#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:18,333 INFO L290 TraceCheckUtils]: 30: Hoare triple {30447#(= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {30433#false} is VALID [2022-02-20 22:05:18,334 INFO L290 TraceCheckUtils]: 31: Hoare triple {30433#false} assume #t~switch220#1; {30433#false} is VALID [2022-02-20 22:05:18,334 INFO L290 TraceCheckUtils]: 32: Hoare triple {30433#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {30433#false} is VALID [2022-02-20 22:05:18,334 INFO L272 TraceCheckUtils]: 33: Hoare triple {30433#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,334 INFO L290 TraceCheckUtils]: 34: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {30432#true} is VALID [2022-02-20 22:05:18,335 INFO L272 TraceCheckUtils]: 35: Hoare triple {30432#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,335 INFO L290 TraceCheckUtils]: 36: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {30432#true} is VALID [2022-02-20 22:05:18,335 INFO L290 TraceCheckUtils]: 37: Hoare triple {30432#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,335 INFO L290 TraceCheckUtils]: 38: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,335 INFO L284 TraceCheckUtils]: 39: Hoare quadruple {30432#true} {30432#true} #893#return; {30432#true} is VALID [2022-02-20 22:05:18,335 INFO L290 TraceCheckUtils]: 40: Hoare triple {30432#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {30432#true} is VALID [2022-02-20 22:05:18,336 INFO L290 TraceCheckUtils]: 41: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,336 INFO L284 TraceCheckUtils]: 42: Hoare quadruple {30432#true} {30433#false} #915#return; {30433#false} is VALID [2022-02-20 22:05:18,336 INFO L290 TraceCheckUtils]: 43: Hoare triple {30433#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {30433#false} is VALID [2022-02-20 22:05:18,336 INFO L290 TraceCheckUtils]: 44: Hoare triple {30433#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {30433#false} is VALID [2022-02-20 22:05:18,336 INFO L272 TraceCheckUtils]: 45: Hoare triple {30433#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,336 INFO L290 TraceCheckUtils]: 46: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {30432#true} is VALID [2022-02-20 22:05:18,337 INFO L272 TraceCheckUtils]: 47: Hoare triple {30432#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,337 INFO L290 TraceCheckUtils]: 48: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {30432#true} is VALID [2022-02-20 22:05:18,338 INFO L272 TraceCheckUtils]: 49: Hoare triple {30432#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:18,338 INFO L290 TraceCheckUtils]: 50: Hoare triple {30477#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {30432#true} is VALID [2022-02-20 22:05:18,338 INFO L290 TraceCheckUtils]: 51: Hoare triple {30432#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,338 INFO L290 TraceCheckUtils]: 52: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,338 INFO L284 TraceCheckUtils]: 53: Hoare quadruple {30432#true} {30432#true} #893#return; {30432#true} is VALID [2022-02-20 22:05:18,339 INFO L290 TraceCheckUtils]: 54: Hoare triple {30432#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {30432#true} is VALID [2022-02-20 22:05:18,339 INFO L290 TraceCheckUtils]: 55: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,339 INFO L284 TraceCheckUtils]: 56: Hoare quadruple {30432#true} {30432#true} #927#return; {30432#true} is VALID [2022-02-20 22:05:18,339 INFO L290 TraceCheckUtils]: 57: Hoare triple {30432#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {30432#true} is VALID [2022-02-20 22:05:18,339 INFO L290 TraceCheckUtils]: 58: Hoare triple {30432#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {30432#true} is VALID [2022-02-20 22:05:18,339 INFO L290 TraceCheckUtils]: 59: Hoare triple {30432#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {30432#true} is VALID [2022-02-20 22:05:18,339 INFO L290 TraceCheckUtils]: 60: Hoare triple {30432#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {30432#true} is VALID [2022-02-20 22:05:18,340 INFO L290 TraceCheckUtils]: 61: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,340 INFO L284 TraceCheckUtils]: 62: Hoare quadruple {30432#true} {30433#false} #917#return; {30433#false} is VALID [2022-02-20 22:05:18,340 INFO L290 TraceCheckUtils]: 63: Hoare triple {30433#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {30433#false} is VALID [2022-02-20 22:05:18,340 INFO L272 TraceCheckUtils]: 64: Hoare triple {30433#false} call ldv_spin_lock_check(); {30433#false} is VALID [2022-02-20 22:05:18,340 INFO L290 TraceCheckUtils]: 65: Hoare triple {30433#false} assume !(1 == ~ldv_init~0); {30433#false} is VALID [2022-02-20 22:05:18,340 INFO L272 TraceCheckUtils]: 66: Hoare triple {30433#false} call ldv_error(); {30433#false} is VALID [2022-02-20 22:05:18,340 INFO L290 TraceCheckUtils]: 67: Hoare triple {30433#false} assume !false; {30433#false} is VALID [2022-02-20 22:05:18,341 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:18,341 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:05:18,341 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675432583] [2022-02-20 22:05:18,342 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675432583] provided 0 perfect and 1 imperfect interpolant sequences [2022-02-20 22:05:18,342 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1436488949] [2022-02-20 22:05:18,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:18,342 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-02-20 22:05:18,342 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:05:18,343 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-02-20 22:05:18,345 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-02-20 22:05:18,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,547 INFO L263 TraceCheckSpWp]: Trace formula consists of 629 conjuncts, 7 conjunts are in the unsatisfiable core [2022-02-20 22:05:18,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:18,593 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-02-20 22:05:18,879 INFO L290 TraceCheckUtils]: 0: Hoare triple {30432#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L290 TraceCheckUtils]: 1: Hoare triple {30432#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L272 TraceCheckUtils]: 2: Hoare triple {30432#true} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L290 TraceCheckUtils]: 3: Hoare triple {30432#true} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L290 TraceCheckUtils]: 4: Hoare triple {30432#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L290 TraceCheckUtils]: 5: Hoare triple {30432#true} assume true; {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {30432#true} {30432#true} #979#return; {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L290 TraceCheckUtils]: 7: Hoare triple {30432#true} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L290 TraceCheckUtils]: 8: Hoare triple {30432#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L290 TraceCheckUtils]: 9: Hoare triple {30432#true} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {30432#true} is VALID [2022-02-20 22:05:18,880 INFO L290 TraceCheckUtils]: 10: Hoare triple {30432#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {30432#true} is VALID [2022-02-20 22:05:18,881 INFO L290 TraceCheckUtils]: 11: Hoare triple {30432#true} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {30432#true} is VALID [2022-02-20 22:05:18,881 INFO L290 TraceCheckUtils]: 12: Hoare triple {30432#true} assume main_#t~switch236#1; {30432#true} is VALID [2022-02-20 22:05:18,881 INFO L290 TraceCheckUtils]: 13: Hoare triple {30432#true} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {30432#true} is VALID [2022-02-20 22:05:18,881 INFO L290 TraceCheckUtils]: 14: Hoare triple {30432#true} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {30432#true} is VALID [2022-02-20 22:05:18,881 INFO L290 TraceCheckUtils]: 15: Hoare triple {30432#true} assume choose_interrupt_1_#t~switch223#1; {30432#true} is VALID [2022-02-20 22:05:18,881 INFO L272 TraceCheckUtils]: 16: Hoare triple {30432#true} call choose_interrupt_1_#t~ret225#1 := ldv_irq_1(~ldv_irq_1_1~0, ~ldv_irq_line_1_1~0, ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset); {30432#true} is VALID [2022-02-20 22:05:18,881 INFO L290 TraceCheckUtils]: 17: Hoare triple {30432#true} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {30432#true} is VALID [2022-02-20 22:05:18,891 INFO L290 TraceCheckUtils]: 18: Hoare triple {30432#true} assume !(0 != ~state#1); {30552#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:18,892 INFO L290 TraceCheckUtils]: 19: Hoare triple {30552#(<= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {30556#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:18,892 INFO L290 TraceCheckUtils]: 20: Hoare triple {30556#(<= |ldv_irq_1_#res#1| 0)} assume true; {30556#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:18,893 INFO L284 TraceCheckUtils]: 21: Hoare quadruple {30556#(<= |ldv_irq_1_#res#1| 0)} {30432#true} #983#return; {30563#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} is VALID [2022-02-20 22:05:18,894 INFO L290 TraceCheckUtils]: 22: Hoare triple {30563#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret225#1 && choose_interrupt_1_#t~ret225#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret225#1;havoc choose_interrupt_1_#t~ret225#1; {30567#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,894 INFO L290 TraceCheckUtils]: 23: Hoare triple {30567#(<= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {30567#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,895 INFO L290 TraceCheckUtils]: 24: Hoare triple {30567#(<= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {30567#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,895 INFO L290 TraceCheckUtils]: 25: Hoare triple {30567#(<= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {30567#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,895 INFO L290 TraceCheckUtils]: 26: Hoare triple {30567#(<= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {30567#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,896 INFO L290 TraceCheckUtils]: 27: Hoare triple {30567#(<= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {30567#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:18,897 INFO L272 TraceCheckUtils]: 28: Hoare triple {30567#(<= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {30586#(<= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:18,897 INFO L290 TraceCheckUtils]: 29: Hoare triple {30586#(<= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {30552#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:18,898 INFO L290 TraceCheckUtils]: 30: Hoare triple {30552#(<= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {30552#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:18,898 INFO L290 TraceCheckUtils]: 31: Hoare triple {30552#(<= |ldv_irq_1_~state#1| 0)} assume #t~switch220#1; {30552#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:18,899 INFO L290 TraceCheckUtils]: 32: Hoare triple {30552#(<= |ldv_irq_1_~state#1| 0)} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {30433#false} is VALID [2022-02-20 22:05:18,899 INFO L272 TraceCheckUtils]: 33: Hoare triple {30433#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {30433#false} is VALID [2022-02-20 22:05:18,899 INFO L290 TraceCheckUtils]: 34: Hoare triple {30433#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {30433#false} is VALID [2022-02-20 22:05:18,899 INFO L272 TraceCheckUtils]: 35: Hoare triple {30433#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {30433#false} is VALID [2022-02-20 22:05:18,899 INFO L290 TraceCheckUtils]: 36: Hoare triple {30433#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {30433#false} is VALID [2022-02-20 22:05:18,900 INFO L290 TraceCheckUtils]: 37: Hoare triple {30433#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {30433#false} is VALID [2022-02-20 22:05:18,900 INFO L290 TraceCheckUtils]: 38: Hoare triple {30433#false} assume true; {30433#false} is VALID [2022-02-20 22:05:18,900 INFO L284 TraceCheckUtils]: 39: Hoare quadruple {30433#false} {30433#false} #893#return; {30433#false} is VALID [2022-02-20 22:05:18,900 INFO L290 TraceCheckUtils]: 40: Hoare triple {30433#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {30433#false} is VALID [2022-02-20 22:05:18,900 INFO L290 TraceCheckUtils]: 41: Hoare triple {30433#false} assume true; {30433#false} is VALID [2022-02-20 22:05:18,900 INFO L284 TraceCheckUtils]: 42: Hoare quadruple {30433#false} {30433#false} #915#return; {30433#false} is VALID [2022-02-20 22:05:18,901 INFO L290 TraceCheckUtils]: 43: Hoare triple {30433#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {30433#false} is VALID [2022-02-20 22:05:18,901 INFO L290 TraceCheckUtils]: 44: Hoare triple {30433#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {30433#false} is VALID [2022-02-20 22:05:18,901 INFO L272 TraceCheckUtils]: 45: Hoare triple {30433#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {30433#false} is VALID [2022-02-20 22:05:18,901 INFO L290 TraceCheckUtils]: 46: Hoare triple {30433#false} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {30433#false} is VALID [2022-02-20 22:05:18,901 INFO L272 TraceCheckUtils]: 47: Hoare triple {30433#false} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {30433#false} is VALID [2022-02-20 22:05:18,901 INFO L290 TraceCheckUtils]: 48: Hoare triple {30433#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {30433#false} is VALID [2022-02-20 22:05:18,901 INFO L272 TraceCheckUtils]: 49: Hoare triple {30433#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {30433#false} is VALID [2022-02-20 22:05:18,902 INFO L290 TraceCheckUtils]: 50: Hoare triple {30433#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {30433#false} is VALID [2022-02-20 22:05:18,902 INFO L290 TraceCheckUtils]: 51: Hoare triple {30433#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {30433#false} is VALID [2022-02-20 22:05:18,902 INFO L290 TraceCheckUtils]: 52: Hoare triple {30433#false} assume true; {30433#false} is VALID [2022-02-20 22:05:18,902 INFO L284 TraceCheckUtils]: 53: Hoare quadruple {30433#false} {30433#false} #893#return; {30433#false} is VALID [2022-02-20 22:05:18,902 INFO L290 TraceCheckUtils]: 54: Hoare triple {30433#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {30433#false} is VALID [2022-02-20 22:05:18,902 INFO L290 TraceCheckUtils]: 55: Hoare triple {30433#false} assume true; {30433#false} is VALID [2022-02-20 22:05:18,902 INFO L284 TraceCheckUtils]: 56: Hoare quadruple {30433#false} {30433#false} #927#return; {30433#false} is VALID [2022-02-20 22:05:18,903 INFO L290 TraceCheckUtils]: 57: Hoare triple {30433#false} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {30433#false} is VALID [2022-02-20 22:05:18,903 INFO L290 TraceCheckUtils]: 58: Hoare triple {30433#false} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {30433#false} is VALID [2022-02-20 22:05:18,903 INFO L290 TraceCheckUtils]: 59: Hoare triple {30433#false} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {30433#false} is VALID [2022-02-20 22:05:18,903 INFO L290 TraceCheckUtils]: 60: Hoare triple {30433#false} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {30433#false} is VALID [2022-02-20 22:05:18,903 INFO L290 TraceCheckUtils]: 61: Hoare triple {30433#false} assume true; {30433#false} is VALID [2022-02-20 22:05:18,903 INFO L284 TraceCheckUtils]: 62: Hoare quadruple {30433#false} {30433#false} #917#return; {30433#false} is VALID [2022-02-20 22:05:18,904 INFO L290 TraceCheckUtils]: 63: Hoare triple {30433#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {30433#false} is VALID [2022-02-20 22:05:18,904 INFO L272 TraceCheckUtils]: 64: Hoare triple {30433#false} call ldv_spin_lock_check(); {30433#false} is VALID [2022-02-20 22:05:18,904 INFO L290 TraceCheckUtils]: 65: Hoare triple {30433#false} assume !(1 == ~ldv_init~0); {30433#false} is VALID [2022-02-20 22:05:18,904 INFO L272 TraceCheckUtils]: 66: Hoare triple {30433#false} call ldv_error(); {30433#false} is VALID [2022-02-20 22:05:18,904 INFO L290 TraceCheckUtils]: 67: Hoare triple {30433#false} assume !false; {30433#false} is VALID [2022-02-20 22:05:18,904 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:18,905 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-02-20 22:05:18,905 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1436488949] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:05:18,905 INFO L191 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-02-20 22:05:18,905 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [11] total 16 [2022-02-20 22:05:18,905 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247214609] [2022-02-20 22:05:18,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:05:18,907 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.428571428571429) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) Word has length 68 [2022-02-20 22:05:18,907 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:05:18,908 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 6.428571428571429) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:18,963 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:18,963 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-02-20 22:05:18,963 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:05:18,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-02-20 22:05:18,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=204, Unknown=0, NotChecked=0, Total=240 [2022-02-20 22:05:18,965 INFO L87 Difference]: Start difference. First operand 1005 states and 1281 transitions. Second operand has 7 states, 7 states have (on average 6.428571428571429) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:20,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:20,859 INFO L93 Difference]: Finished difference Result 2325 states and 2960 transitions. [2022-02-20 22:05:20,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-02-20 22:05:20,860 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.428571428571429) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) Word has length 68 [2022-02-20 22:05:20,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:05:20,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 6.428571428571429) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:20,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 1029 transitions. [2022-02-20 22:05:20,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 6.428571428571429) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:20,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 1029 transitions. [2022-02-20 22:05:20,882 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states and 1029 transitions. [2022-02-20 22:05:21,629 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 1029 edges. 1029 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:21,727 INFO L225 Difference]: With dead ends: 2325 [2022-02-20 22:05:21,728 INFO L226 Difference]: Without dead ends: 1344 [2022-02-20 22:05:21,730 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=77, Invalid=429, Unknown=0, NotChecked=0, Total=506 [2022-02-20 22:05:21,730 INFO L933 BasicCegarLoop]: 413 mSDtfsCounter, 337 mSDsluCounter, 1972 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 341 SdHoareTripleChecker+Valid, 2385 SdHoareTripleChecker+Invalid, 56 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-02-20 22:05:21,731 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [341 Valid, 2385 Invalid, 56 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 54 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-02-20 22:05:21,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1344 states. [2022-02-20 22:05:21,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1344 to 1289. [2022-02-20 22:05:21,973 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:05:21,975 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1344 states. Second operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:21,977 INFO L74 IsIncluded]: Start isIncluded. First operand 1344 states. Second operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:21,980 INFO L87 Difference]: Start difference. First operand 1344 states. Second operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:22,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:22,056 INFO L93 Difference]: Finished difference Result 1344 states and 1702 transitions. [2022-02-20 22:05:22,056 INFO L276 IsEmpty]: Start isEmpty. Operand 1344 states and 1702 transitions. [2022-02-20 22:05:22,059 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:22,059 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:22,061 INFO L74 IsIncluded]: Start isIncluded. First operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) Second operand 1344 states. [2022-02-20 22:05:22,063 INFO L87 Difference]: Start difference. First operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) Second operand 1344 states. [2022-02-20 22:05:22,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:22,146 INFO L93 Difference]: Finished difference Result 1344 states and 1702 transitions. [2022-02-20 22:05:22,146 INFO L276 IsEmpty]: Start isEmpty. Operand 1344 states and 1702 transitions. [2022-02-20 22:05:22,149 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:22,149 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:22,149 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:05:22,149 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:05:22,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:22,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1648 transitions. [2022-02-20 22:05:22,264 INFO L78 Accepts]: Start accepts. Automaton has 1289 states and 1648 transitions. Word has length 68 [2022-02-20 22:05:22,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:05:22,264 INFO L470 AbstractCegarLoop]: Abstraction has 1289 states and 1648 transitions. [2022-02-20 22:05:22,264 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 6.428571428571429) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:22,264 INFO L276 IsEmpty]: Start isEmpty. Operand 1289 states and 1648 transitions. [2022-02-20 22:05:22,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2022-02-20 22:05:22,268 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:05:22,268 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:05:22,295 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-02-20 22:05:22,483 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable7 [2022-02-20 22:05:22,483 INFO L402 AbstractCegarLoop]: === Iteration 9 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:05:22,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:05:22,484 INFO L85 PathProgramCache]: Analyzing trace with hash 2110117865, now seen corresponding path program 1 times [2022-02-20 22:05:22,484 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:05:22,484 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033789646] [2022-02-20 22:05:22,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:22,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:05:22,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,579 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:05:22,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,585 INFO L290 TraceCheckUtils]: 0: Hoare triple {38283#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {38241#true} is VALID [2022-02-20 22:05:22,585 INFO L290 TraceCheckUtils]: 1: Hoare triple {38241#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:22,585 INFO L290 TraceCheckUtils]: 2: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,586 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {38241#true} {38243#(= ~ldv_irq_1_2~0 0)} #979#return; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,599 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 17 [2022-02-20 22:05:22,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,616 INFO L290 TraceCheckUtils]: 0: Hoare triple {38284#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {38241#true} is VALID [2022-02-20 22:05:22,617 INFO L290 TraceCheckUtils]: 1: Hoare triple {38241#true} assume !(0 != ~state#1); {38256#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:22,617 INFO L290 TraceCheckUtils]: 2: Hoare triple {38256#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {38285#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:22,617 INFO L290 TraceCheckUtils]: 3: Hoare triple {38285#(= |ldv_irq_1_#res#1| 0)} assume true; {38285#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:22,618 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {38285#(= |ldv_irq_1_#res#1| 0)} {38243#(= ~ldv_irq_1_2~0 0)} #985#return; {38253#(= |ULTIMATE.start_choose_interrupt_1_#t~ret226#1| 0)} is VALID [2022-02-20 22:05:22,628 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 34 [2022-02-20 22:05:22,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,633 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:22,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,638 INFO L290 TraceCheckUtils]: 0: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {38241#true} is VALID [2022-02-20 22:05:22,638 INFO L290 TraceCheckUtils]: 1: Hoare triple {38241#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:22,638 INFO L290 TraceCheckUtils]: 2: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,638 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {38241#true} {38241#true} #893#return; {38241#true} is VALID [2022-02-20 22:05:22,638 INFO L290 TraceCheckUtils]: 0: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {38241#true} is VALID [2022-02-20 22:05:22,639 INFO L272 TraceCheckUtils]: 1: Hoare triple {38241#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,639 INFO L290 TraceCheckUtils]: 2: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {38241#true} is VALID [2022-02-20 22:05:22,639 INFO L290 TraceCheckUtils]: 3: Hoare triple {38241#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:22,639 INFO L290 TraceCheckUtils]: 4: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,639 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {38241#true} {38241#true} #893#return; {38241#true} is VALID [2022-02-20 22:05:22,639 INFO L290 TraceCheckUtils]: 6: Hoare triple {38241#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {38241#true} is VALID [2022-02-20 22:05:22,639 INFO L290 TraceCheckUtils]: 7: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,639 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {38241#true} {38242#false} #915#return; {38242#false} is VALID [2022-02-20 22:05:22,640 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 46 [2022-02-20 22:05:22,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,647 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:22,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,654 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:22,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,659 INFO L290 TraceCheckUtils]: 0: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {38241#true} is VALID [2022-02-20 22:05:22,659 INFO L290 TraceCheckUtils]: 1: Hoare triple {38241#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:22,659 INFO L290 TraceCheckUtils]: 2: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,659 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {38241#true} {38241#true} #893#return; {38241#true} is VALID [2022-02-20 22:05:22,659 INFO L290 TraceCheckUtils]: 0: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {38241#true} is VALID [2022-02-20 22:05:22,660 INFO L272 TraceCheckUtils]: 1: Hoare triple {38241#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,660 INFO L290 TraceCheckUtils]: 2: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {38241#true} is VALID [2022-02-20 22:05:22,660 INFO L290 TraceCheckUtils]: 3: Hoare triple {38241#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:22,660 INFO L290 TraceCheckUtils]: 4: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,660 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {38241#true} {38241#true} #893#return; {38241#true} is VALID [2022-02-20 22:05:22,660 INFO L290 TraceCheckUtils]: 6: Hoare triple {38241#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {38241#true} is VALID [2022-02-20 22:05:22,660 INFO L290 TraceCheckUtils]: 7: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,660 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {38241#true} {38241#true} #927#return; {38241#true} is VALID [2022-02-20 22:05:22,660 INFO L290 TraceCheckUtils]: 0: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {38241#true} is VALID [2022-02-20 22:05:22,661 INFO L272 TraceCheckUtils]: 1: Hoare triple {38241#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,661 INFO L290 TraceCheckUtils]: 2: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {38241#true} is VALID [2022-02-20 22:05:22,662 INFO L272 TraceCheckUtils]: 3: Hoare triple {38241#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,662 INFO L290 TraceCheckUtils]: 4: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {38241#true} is VALID [2022-02-20 22:05:22,662 INFO L290 TraceCheckUtils]: 5: Hoare triple {38241#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:22,662 INFO L290 TraceCheckUtils]: 6: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,662 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {38241#true} {38241#true} #893#return; {38241#true} is VALID [2022-02-20 22:05:22,662 INFO L290 TraceCheckUtils]: 8: Hoare triple {38241#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {38241#true} is VALID [2022-02-20 22:05:22,662 INFO L290 TraceCheckUtils]: 9: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,662 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {38241#true} {38241#true} #927#return; {38241#true} is VALID [2022-02-20 22:05:22,662 INFO L290 TraceCheckUtils]: 11: Hoare triple {38241#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {38241#true} is VALID [2022-02-20 22:05:22,663 INFO L290 TraceCheckUtils]: 12: Hoare triple {38241#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {38241#true} is VALID [2022-02-20 22:05:22,663 INFO L290 TraceCheckUtils]: 13: Hoare triple {38241#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {38241#true} is VALID [2022-02-20 22:05:22,663 INFO L290 TraceCheckUtils]: 14: Hoare triple {38241#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {38241#true} is VALID [2022-02-20 22:05:22,663 INFO L290 TraceCheckUtils]: 15: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,663 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {38241#true} {38242#false} #917#return; {38242#false} is VALID [2022-02-20 22:05:22,663 INFO L290 TraceCheckUtils]: 0: Hoare triple {38241#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,664 INFO L290 TraceCheckUtils]: 1: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,664 INFO L272 TraceCheckUtils]: 2: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {38283#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,665 INFO L290 TraceCheckUtils]: 3: Hoare triple {38283#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {38241#true} is VALID [2022-02-20 22:05:22,665 INFO L290 TraceCheckUtils]: 4: Hoare triple {38241#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:22,665 INFO L290 TraceCheckUtils]: 5: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,665 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {38241#true} {38243#(= ~ldv_irq_1_2~0 0)} #979#return; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,666 INFO L290 TraceCheckUtils]: 7: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,666 INFO L290 TraceCheckUtils]: 8: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,666 INFO L290 TraceCheckUtils]: 9: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,667 INFO L290 TraceCheckUtils]: 10: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,667 INFO L290 TraceCheckUtils]: 11: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,667 INFO L290 TraceCheckUtils]: 12: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume main_#t~switch236#1; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,667 INFO L290 TraceCheckUtils]: 13: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,668 INFO L290 TraceCheckUtils]: 14: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,668 INFO L290 TraceCheckUtils]: 15: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 2 == choose_interrupt_1_~tmp~23#1; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,668 INFO L290 TraceCheckUtils]: 16: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} assume choose_interrupt_1_#t~switch223#1; {38243#(= ~ldv_irq_1_2~0 0)} is VALID [2022-02-20 22:05:22,669 INFO L272 TraceCheckUtils]: 17: Hoare triple {38243#(= ~ldv_irq_1_2~0 0)} call choose_interrupt_1_#t~ret226#1 := ldv_irq_1(~ldv_irq_1_2~0, ~ldv_irq_line_1_2~0, ~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset); {38284#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} is VALID [2022-02-20 22:05:22,670 INFO L290 TraceCheckUtils]: 18: Hoare triple {38284#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {38241#true} is VALID [2022-02-20 22:05:22,670 INFO L290 TraceCheckUtils]: 19: Hoare triple {38241#true} assume !(0 != ~state#1); {38256#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:22,670 INFO L290 TraceCheckUtils]: 20: Hoare triple {38256#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {38285#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:22,670 INFO L290 TraceCheckUtils]: 21: Hoare triple {38285#(= |ldv_irq_1_#res#1| 0)} assume true; {38285#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:22,671 INFO L284 TraceCheckUtils]: 22: Hoare quadruple {38285#(= |ldv_irq_1_#res#1| 0)} {38243#(= ~ldv_irq_1_2~0 0)} #985#return; {38253#(= |ULTIMATE.start_choose_interrupt_1_#t~ret226#1| 0)} is VALID [2022-02-20 22:05:22,672 INFO L290 TraceCheckUtils]: 23: Hoare triple {38253#(= |ULTIMATE.start_choose_interrupt_1_#t~ret226#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret226#1 && choose_interrupt_1_#t~ret226#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret226#1;havoc choose_interrupt_1_#t~ret226#1; {38254#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:22,675 INFO L290 TraceCheckUtils]: 24: Hoare triple {38254#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {38254#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:22,675 INFO L290 TraceCheckUtils]: 25: Hoare triple {38254#(= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {38254#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:22,676 INFO L290 TraceCheckUtils]: 26: Hoare triple {38254#(= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {38254#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:22,676 INFO L290 TraceCheckUtils]: 27: Hoare triple {38254#(= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {38254#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:22,676 INFO L290 TraceCheckUtils]: 28: Hoare triple {38254#(= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {38254#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:22,677 INFO L272 TraceCheckUtils]: 29: Hoare triple {38254#(= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {38255#(= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:22,677 INFO L290 TraceCheckUtils]: 30: Hoare triple {38255#(= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {38256#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:22,678 INFO L290 TraceCheckUtils]: 31: Hoare triple {38256#(= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {38242#false} is VALID [2022-02-20 22:05:22,678 INFO L290 TraceCheckUtils]: 32: Hoare triple {38242#false} assume #t~switch220#1; {38242#false} is VALID [2022-02-20 22:05:22,678 INFO L290 TraceCheckUtils]: 33: Hoare triple {38242#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {38242#false} is VALID [2022-02-20 22:05:22,678 INFO L272 TraceCheckUtils]: 34: Hoare triple {38242#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,678 INFO L290 TraceCheckUtils]: 35: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {38241#true} is VALID [2022-02-20 22:05:22,679 INFO L272 TraceCheckUtils]: 36: Hoare triple {38241#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,679 INFO L290 TraceCheckUtils]: 37: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {38241#true} is VALID [2022-02-20 22:05:22,679 INFO L290 TraceCheckUtils]: 38: Hoare triple {38241#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:22,679 INFO L290 TraceCheckUtils]: 39: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,679 INFO L284 TraceCheckUtils]: 40: Hoare quadruple {38241#true} {38241#true} #893#return; {38241#true} is VALID [2022-02-20 22:05:22,679 INFO L290 TraceCheckUtils]: 41: Hoare triple {38241#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {38241#true} is VALID [2022-02-20 22:05:22,679 INFO L290 TraceCheckUtils]: 42: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,679 INFO L284 TraceCheckUtils]: 43: Hoare quadruple {38241#true} {38242#false} #915#return; {38242#false} is VALID [2022-02-20 22:05:22,679 INFO L290 TraceCheckUtils]: 44: Hoare triple {38242#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {38242#false} is VALID [2022-02-20 22:05:22,679 INFO L290 TraceCheckUtils]: 45: Hoare triple {38242#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {38242#false} is VALID [2022-02-20 22:05:22,680 INFO L272 TraceCheckUtils]: 46: Hoare triple {38242#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,680 INFO L290 TraceCheckUtils]: 47: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {38241#true} is VALID [2022-02-20 22:05:22,680 INFO L272 TraceCheckUtils]: 48: Hoare triple {38241#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,680 INFO L290 TraceCheckUtils]: 49: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {38241#true} is VALID [2022-02-20 22:05:22,681 INFO L272 TraceCheckUtils]: 50: Hoare triple {38241#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:22,681 INFO L290 TraceCheckUtils]: 51: Hoare triple {38286#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {38241#true} is VALID [2022-02-20 22:05:22,681 INFO L290 TraceCheckUtils]: 52: Hoare triple {38241#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:22,681 INFO L290 TraceCheckUtils]: 53: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,681 INFO L284 TraceCheckUtils]: 54: Hoare quadruple {38241#true} {38241#true} #893#return; {38241#true} is VALID [2022-02-20 22:05:22,681 INFO L290 TraceCheckUtils]: 55: Hoare triple {38241#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {38241#true} is VALID [2022-02-20 22:05:22,682 INFO L290 TraceCheckUtils]: 56: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,682 INFO L284 TraceCheckUtils]: 57: Hoare quadruple {38241#true} {38241#true} #927#return; {38241#true} is VALID [2022-02-20 22:05:22,682 INFO L290 TraceCheckUtils]: 58: Hoare triple {38241#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {38241#true} is VALID [2022-02-20 22:05:22,682 INFO L290 TraceCheckUtils]: 59: Hoare triple {38241#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {38241#true} is VALID [2022-02-20 22:05:22,682 INFO L290 TraceCheckUtils]: 60: Hoare triple {38241#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {38241#true} is VALID [2022-02-20 22:05:22,682 INFO L290 TraceCheckUtils]: 61: Hoare triple {38241#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {38241#true} is VALID [2022-02-20 22:05:22,682 INFO L290 TraceCheckUtils]: 62: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:22,682 INFO L284 TraceCheckUtils]: 63: Hoare quadruple {38241#true} {38242#false} #917#return; {38242#false} is VALID [2022-02-20 22:05:22,682 INFO L290 TraceCheckUtils]: 64: Hoare triple {38242#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {38242#false} is VALID [2022-02-20 22:05:22,682 INFO L272 TraceCheckUtils]: 65: Hoare triple {38242#false} call ldv_spin_lock_check(); {38242#false} is VALID [2022-02-20 22:05:22,682 INFO L290 TraceCheckUtils]: 66: Hoare triple {38242#false} assume !(1 == ~ldv_init~0); {38242#false} is VALID [2022-02-20 22:05:22,683 INFO L272 TraceCheckUtils]: 67: Hoare triple {38242#false} call ldv_error(); {38242#false} is VALID [2022-02-20 22:05:22,683 INFO L290 TraceCheckUtils]: 68: Hoare triple {38242#false} assume !false; {38242#false} is VALID [2022-02-20 22:05:22,683 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:22,683 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:05:22,683 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2033789646] [2022-02-20 22:05:22,683 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2033789646] provided 0 perfect and 1 imperfect interpolant sequences [2022-02-20 22:05:22,683 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [109495892] [2022-02-20 22:05:22,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:22,684 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-02-20 22:05:22,684 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:05:22,685 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-02-20 22:05:22,686 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-02-20 22:05:22,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,877 INFO L263 TraceCheckSpWp]: Trace formula consists of 631 conjuncts, 7 conjunts are in the unsatisfiable core [2022-02-20 22:05:22,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:22,919 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-02-20 22:05:23,224 INFO L290 TraceCheckUtils]: 0: Hoare triple {38241#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {38241#true} is VALID [2022-02-20 22:05:23,224 INFO L290 TraceCheckUtils]: 1: Hoare triple {38241#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {38241#true} is VALID [2022-02-20 22:05:23,224 INFO L272 TraceCheckUtils]: 2: Hoare triple {38241#true} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {38241#true} is VALID [2022-02-20 22:05:23,225 INFO L290 TraceCheckUtils]: 3: Hoare triple {38241#true} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {38241#true} is VALID [2022-02-20 22:05:23,225 INFO L290 TraceCheckUtils]: 4: Hoare triple {38241#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {38241#true} is VALID [2022-02-20 22:05:23,225 INFO L290 TraceCheckUtils]: 5: Hoare triple {38241#true} assume true; {38241#true} is VALID [2022-02-20 22:05:23,225 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {38241#true} {38241#true} #979#return; {38241#true} is VALID [2022-02-20 22:05:23,225 INFO L290 TraceCheckUtils]: 7: Hoare triple {38241#true} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {38241#true} is VALID [2022-02-20 22:05:23,225 INFO L290 TraceCheckUtils]: 8: Hoare triple {38241#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {38241#true} is VALID [2022-02-20 22:05:23,225 INFO L290 TraceCheckUtils]: 9: Hoare triple {38241#true} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {38241#true} is VALID [2022-02-20 22:05:23,226 INFO L290 TraceCheckUtils]: 10: Hoare triple {38241#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {38241#true} is VALID [2022-02-20 22:05:23,226 INFO L290 TraceCheckUtils]: 11: Hoare triple {38241#true} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {38241#true} is VALID [2022-02-20 22:05:23,226 INFO L290 TraceCheckUtils]: 12: Hoare triple {38241#true} assume main_#t~switch236#1; {38241#true} is VALID [2022-02-20 22:05:23,226 INFO L290 TraceCheckUtils]: 13: Hoare triple {38241#true} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {38241#true} is VALID [2022-02-20 22:05:23,227 INFO L290 TraceCheckUtils]: 14: Hoare triple {38241#true} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {38241#true} is VALID [2022-02-20 22:05:23,227 INFO L290 TraceCheckUtils]: 15: Hoare triple {38241#true} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 2 == choose_interrupt_1_~tmp~23#1; {38241#true} is VALID [2022-02-20 22:05:23,227 INFO L290 TraceCheckUtils]: 16: Hoare triple {38241#true} assume choose_interrupt_1_#t~switch223#1; {38241#true} is VALID [2022-02-20 22:05:23,227 INFO L272 TraceCheckUtils]: 17: Hoare triple {38241#true} call choose_interrupt_1_#t~ret226#1 := ldv_irq_1(~ldv_irq_1_2~0, ~ldv_irq_line_1_2~0, ~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset); {38241#true} is VALID [2022-02-20 22:05:23,227 INFO L290 TraceCheckUtils]: 18: Hoare triple {38241#true} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {38241#true} is VALID [2022-02-20 22:05:23,228 INFO L290 TraceCheckUtils]: 19: Hoare triple {38241#true} assume !(0 != ~state#1); {38364#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:23,228 INFO L290 TraceCheckUtils]: 20: Hoare triple {38364#(<= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {38368#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:23,229 INFO L290 TraceCheckUtils]: 21: Hoare triple {38368#(<= |ldv_irq_1_#res#1| 0)} assume true; {38368#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:23,230 INFO L284 TraceCheckUtils]: 22: Hoare quadruple {38368#(<= |ldv_irq_1_#res#1| 0)} {38241#true} #985#return; {38375#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret226#1| 0)} is VALID [2022-02-20 22:05:23,230 INFO L290 TraceCheckUtils]: 23: Hoare triple {38375#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret226#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret226#1 && choose_interrupt_1_#t~ret226#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret226#1;havoc choose_interrupt_1_#t~ret226#1; {38379#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:23,231 INFO L290 TraceCheckUtils]: 24: Hoare triple {38379#(<= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {38379#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:23,231 INFO L290 TraceCheckUtils]: 25: Hoare triple {38379#(<= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {38379#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:23,231 INFO L290 TraceCheckUtils]: 26: Hoare triple {38379#(<= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {38379#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:23,232 INFO L290 TraceCheckUtils]: 27: Hoare triple {38379#(<= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {38379#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:23,232 INFO L290 TraceCheckUtils]: 28: Hoare triple {38379#(<= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {38379#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:23,233 INFO L272 TraceCheckUtils]: 29: Hoare triple {38379#(<= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {38398#(<= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:23,234 INFO L290 TraceCheckUtils]: 30: Hoare triple {38398#(<= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {38364#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:23,234 INFO L290 TraceCheckUtils]: 31: Hoare triple {38364#(<= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {38364#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:23,234 INFO L290 TraceCheckUtils]: 32: Hoare triple {38364#(<= |ldv_irq_1_~state#1| 0)} assume #t~switch220#1; {38364#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:23,235 INFO L290 TraceCheckUtils]: 33: Hoare triple {38364#(<= |ldv_irq_1_~state#1| 0)} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {38242#false} is VALID [2022-02-20 22:05:23,235 INFO L272 TraceCheckUtils]: 34: Hoare triple {38242#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {38242#false} is VALID [2022-02-20 22:05:23,235 INFO L290 TraceCheckUtils]: 35: Hoare triple {38242#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {38242#false} is VALID [2022-02-20 22:05:23,235 INFO L272 TraceCheckUtils]: 36: Hoare triple {38242#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {38242#false} is VALID [2022-02-20 22:05:23,235 INFO L290 TraceCheckUtils]: 37: Hoare triple {38242#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {38242#false} is VALID [2022-02-20 22:05:23,235 INFO L290 TraceCheckUtils]: 38: Hoare triple {38242#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L290 TraceCheckUtils]: 39: Hoare triple {38242#false} assume true; {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L284 TraceCheckUtils]: 40: Hoare quadruple {38242#false} {38242#false} #893#return; {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L290 TraceCheckUtils]: 41: Hoare triple {38242#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L290 TraceCheckUtils]: 42: Hoare triple {38242#false} assume true; {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L284 TraceCheckUtils]: 43: Hoare quadruple {38242#false} {38242#false} #915#return; {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L290 TraceCheckUtils]: 44: Hoare triple {38242#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L290 TraceCheckUtils]: 45: Hoare triple {38242#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L272 TraceCheckUtils]: 46: Hoare triple {38242#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L290 TraceCheckUtils]: 47: Hoare triple {38242#false} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {38242#false} is VALID [2022-02-20 22:05:23,236 INFO L272 TraceCheckUtils]: 48: Hoare triple {38242#false} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L290 TraceCheckUtils]: 49: Hoare triple {38242#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L272 TraceCheckUtils]: 50: Hoare triple {38242#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L290 TraceCheckUtils]: 51: Hoare triple {38242#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L290 TraceCheckUtils]: 52: Hoare triple {38242#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L290 TraceCheckUtils]: 53: Hoare triple {38242#false} assume true; {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L284 TraceCheckUtils]: 54: Hoare quadruple {38242#false} {38242#false} #893#return; {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L290 TraceCheckUtils]: 55: Hoare triple {38242#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L290 TraceCheckUtils]: 56: Hoare triple {38242#false} assume true; {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L284 TraceCheckUtils]: 57: Hoare quadruple {38242#false} {38242#false} #927#return; {38242#false} is VALID [2022-02-20 22:05:23,237 INFO L290 TraceCheckUtils]: 58: Hoare triple {38242#false} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {38242#false} is VALID [2022-02-20 22:05:23,238 INFO L290 TraceCheckUtils]: 59: Hoare triple {38242#false} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {38242#false} is VALID [2022-02-20 22:05:23,238 INFO L290 TraceCheckUtils]: 60: Hoare triple {38242#false} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {38242#false} is VALID [2022-02-20 22:05:23,238 INFO L290 TraceCheckUtils]: 61: Hoare triple {38242#false} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {38242#false} is VALID [2022-02-20 22:05:23,238 INFO L290 TraceCheckUtils]: 62: Hoare triple {38242#false} assume true; {38242#false} is VALID [2022-02-20 22:05:23,238 INFO L284 TraceCheckUtils]: 63: Hoare quadruple {38242#false} {38242#false} #917#return; {38242#false} is VALID [2022-02-20 22:05:23,238 INFO L290 TraceCheckUtils]: 64: Hoare triple {38242#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {38242#false} is VALID [2022-02-20 22:05:23,238 INFO L272 TraceCheckUtils]: 65: Hoare triple {38242#false} call ldv_spin_lock_check(); {38242#false} is VALID [2022-02-20 22:05:23,238 INFO L290 TraceCheckUtils]: 66: Hoare triple {38242#false} assume !(1 == ~ldv_init~0); {38242#false} is VALID [2022-02-20 22:05:23,239 INFO L272 TraceCheckUtils]: 67: Hoare triple {38242#false} call ldv_error(); {38242#false} is VALID [2022-02-20 22:05:23,239 INFO L290 TraceCheckUtils]: 68: Hoare triple {38242#false} assume !false; {38242#false} is VALID [2022-02-20 22:05:23,239 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:23,239 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-02-20 22:05:23,239 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [109495892] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:05:23,240 INFO L191 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-02-20 22:05:23,240 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [11] total 16 [2022-02-20 22:05:23,240 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15578106] [2022-02-20 22:05:23,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:05:23,241 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) Word has length 69 [2022-02-20 22:05:23,241 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:05:23,241 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:23,297 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:23,297 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-02-20 22:05:23,298 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:05:23,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-02-20 22:05:23,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=204, Unknown=0, NotChecked=0, Total=240 [2022-02-20 22:05:23,299 INFO L87 Difference]: Start difference. First operand 1289 states and 1648 transitions. Second operand has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:25,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:25,395 INFO L93 Difference]: Finished difference Result 2893 states and 3694 transitions. [2022-02-20 22:05:25,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-02-20 22:05:25,395 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) Word has length 69 [2022-02-20 22:05:25,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:05:25,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:25,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 1029 transitions. [2022-02-20 22:05:25,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:25,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 1029 transitions. [2022-02-20 22:05:25,414 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states and 1029 transitions. [2022-02-20 22:05:26,170 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 1029 edges. 1029 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:26,315 INFO L225 Difference]: With dead ends: 2893 [2022-02-20 22:05:26,315 INFO L226 Difference]: Without dead ends: 1628 [2022-02-20 22:05:26,318 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=77, Invalid=429, Unknown=0, NotChecked=0, Total=506 [2022-02-20 22:05:26,320 INFO L933 BasicCegarLoop]: 413 mSDtfsCounter, 337 mSDsluCounter, 1972 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 341 SdHoareTripleChecker+Valid, 2385 SdHoareTripleChecker+Invalid, 56 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-02-20 22:05:26,320 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [341 Valid, 2385 Invalid, 56 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 54 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-02-20 22:05:26,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1628 states. [2022-02-20 22:05:26,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1628 to 1289. [2022-02-20 22:05:26,545 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:05:26,548 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1628 states. Second operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:26,549 INFO L74 IsIncluded]: Start isIncluded. First operand 1628 states. Second operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:26,551 INFO L87 Difference]: Start difference. First operand 1628 states. Second operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:26,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:26,693 INFO L93 Difference]: Finished difference Result 1628 states and 2069 transitions. [2022-02-20 22:05:26,694 INFO L276 IsEmpty]: Start isEmpty. Operand 1628 states and 2069 transitions. [2022-02-20 22:05:26,698 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:26,698 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:26,708 INFO L74 IsIncluded]: Start isIncluded. First operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) Second operand 1628 states. [2022-02-20 22:05:26,711 INFO L87 Difference]: Start difference. First operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) Second operand 1628 states. [2022-02-20 22:05:26,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:26,850 INFO L93 Difference]: Finished difference Result 1628 states and 2069 transitions. [2022-02-20 22:05:26,850 INFO L276 IsEmpty]: Start isEmpty. Operand 1628 states and 2069 transitions. [2022-02-20 22:05:26,854 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:26,855 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:26,855 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:05:26,855 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:05:26,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:26,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1648 transitions. [2022-02-20 22:05:26,975 INFO L78 Accepts]: Start accepts. Automaton has 1289 states and 1648 transitions. Word has length 69 [2022-02-20 22:05:26,975 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:05:26,975 INFO L470 AbstractCegarLoop]: Abstraction has 1289 states and 1648 transitions. [2022-02-20 22:05:26,975 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:26,976 INFO L276 IsEmpty]: Start isEmpty. Operand 1289 states and 1648 transitions. [2022-02-20 22:05:26,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-02-20 22:05:26,982 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:05:26,982 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:05:27,003 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-02-20 22:05:27,194 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-02-20 22:05:27,195 INFO L402 AbstractCegarLoop]: === Iteration 10 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:05:27,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:05:27,195 INFO L85 PathProgramCache]: Analyzing trace with hash -1874499426, now seen corresponding path program 1 times [2022-02-20 22:05:27,195 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:05:27,195 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374563865] [2022-02-20 22:05:27,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:27,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:05:27,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,269 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:05:27,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,276 INFO L290 TraceCheckUtils]: 0: Hoare triple {47419#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {47377#true} is VALID [2022-02-20 22:05:27,276 INFO L290 TraceCheckUtils]: 1: Hoare triple {47377#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,276 INFO L290 TraceCheckUtils]: 2: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,277 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {47377#true} {47379#(= ~ldv_irq_1_3~0 0)} #979#return; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,289 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 18 [2022-02-20 22:05:27,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,305 INFO L290 TraceCheckUtils]: 0: Hoare triple {47420#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {47377#true} is VALID [2022-02-20 22:05:27,306 INFO L290 TraceCheckUtils]: 1: Hoare triple {47377#true} assume !(0 != ~state#1); {47392#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:27,306 INFO L290 TraceCheckUtils]: 2: Hoare triple {47392#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {47421#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:27,306 INFO L290 TraceCheckUtils]: 3: Hoare triple {47421#(= |ldv_irq_1_#res#1| 0)} assume true; {47421#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:27,307 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {47421#(= |ldv_irq_1_#res#1| 0)} {47379#(= ~ldv_irq_1_3~0 0)} #987#return; {47389#(= |ULTIMATE.start_choose_interrupt_1_#t~ret227#1| 0)} is VALID [2022-02-20 22:05:27,317 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2022-02-20 22:05:27,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,323 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:27,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,327 INFO L290 TraceCheckUtils]: 0: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {47377#true} is VALID [2022-02-20 22:05:27,327 INFO L290 TraceCheckUtils]: 1: Hoare triple {47377#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,327 INFO L290 TraceCheckUtils]: 2: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,327 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {47377#true} {47377#true} #893#return; {47377#true} is VALID [2022-02-20 22:05:27,328 INFO L290 TraceCheckUtils]: 0: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {47377#true} is VALID [2022-02-20 22:05:27,328 INFO L272 TraceCheckUtils]: 1: Hoare triple {47377#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,328 INFO L290 TraceCheckUtils]: 2: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {47377#true} is VALID [2022-02-20 22:05:27,329 INFO L290 TraceCheckUtils]: 3: Hoare triple {47377#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,329 INFO L290 TraceCheckUtils]: 4: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,329 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {47377#true} {47377#true} #893#return; {47377#true} is VALID [2022-02-20 22:05:27,329 INFO L290 TraceCheckUtils]: 6: Hoare triple {47377#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {47377#true} is VALID [2022-02-20 22:05:27,329 INFO L290 TraceCheckUtils]: 7: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,329 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {47377#true} {47378#false} #915#return; {47378#false} is VALID [2022-02-20 22:05:27,329 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 47 [2022-02-20 22:05:27,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,337 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:27,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,343 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:27,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,347 INFO L290 TraceCheckUtils]: 0: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {47377#true} is VALID [2022-02-20 22:05:27,348 INFO L290 TraceCheckUtils]: 1: Hoare triple {47377#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,348 INFO L290 TraceCheckUtils]: 2: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,348 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {47377#true} {47377#true} #893#return; {47377#true} is VALID [2022-02-20 22:05:27,348 INFO L290 TraceCheckUtils]: 0: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {47377#true} is VALID [2022-02-20 22:05:27,349 INFO L272 TraceCheckUtils]: 1: Hoare triple {47377#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,349 INFO L290 TraceCheckUtils]: 2: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {47377#true} is VALID [2022-02-20 22:05:27,349 INFO L290 TraceCheckUtils]: 3: Hoare triple {47377#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,349 INFO L290 TraceCheckUtils]: 4: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,349 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {47377#true} {47377#true} #893#return; {47377#true} is VALID [2022-02-20 22:05:27,350 INFO L290 TraceCheckUtils]: 6: Hoare triple {47377#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {47377#true} is VALID [2022-02-20 22:05:27,350 INFO L290 TraceCheckUtils]: 7: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,350 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {47377#true} {47377#true} #927#return; {47377#true} is VALID [2022-02-20 22:05:27,350 INFO L290 TraceCheckUtils]: 0: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {47377#true} is VALID [2022-02-20 22:05:27,351 INFO L272 TraceCheckUtils]: 1: Hoare triple {47377#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,351 INFO L290 TraceCheckUtils]: 2: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {47377#true} is VALID [2022-02-20 22:05:27,351 INFO L272 TraceCheckUtils]: 3: Hoare triple {47377#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,352 INFO L290 TraceCheckUtils]: 4: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {47377#true} is VALID [2022-02-20 22:05:27,352 INFO L290 TraceCheckUtils]: 5: Hoare triple {47377#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,352 INFO L290 TraceCheckUtils]: 6: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,352 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {47377#true} {47377#true} #893#return; {47377#true} is VALID [2022-02-20 22:05:27,352 INFO L290 TraceCheckUtils]: 8: Hoare triple {47377#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {47377#true} is VALID [2022-02-20 22:05:27,352 INFO L290 TraceCheckUtils]: 9: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,352 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {47377#true} {47377#true} #927#return; {47377#true} is VALID [2022-02-20 22:05:27,353 INFO L290 TraceCheckUtils]: 11: Hoare triple {47377#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {47377#true} is VALID [2022-02-20 22:05:27,353 INFO L290 TraceCheckUtils]: 12: Hoare triple {47377#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {47377#true} is VALID [2022-02-20 22:05:27,353 INFO L290 TraceCheckUtils]: 13: Hoare triple {47377#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {47377#true} is VALID [2022-02-20 22:05:27,353 INFO L290 TraceCheckUtils]: 14: Hoare triple {47377#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {47377#true} is VALID [2022-02-20 22:05:27,353 INFO L290 TraceCheckUtils]: 15: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,353 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {47377#true} {47378#false} #917#return; {47378#false} is VALID [2022-02-20 22:05:27,354 INFO L290 TraceCheckUtils]: 0: Hoare triple {47377#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,354 INFO L290 TraceCheckUtils]: 1: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,355 INFO L272 TraceCheckUtils]: 2: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {47419#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,355 INFO L290 TraceCheckUtils]: 3: Hoare triple {47419#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {47377#true} is VALID [2022-02-20 22:05:27,355 INFO L290 TraceCheckUtils]: 4: Hoare triple {47377#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,355 INFO L290 TraceCheckUtils]: 5: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,356 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {47377#true} {47379#(= ~ldv_irq_1_3~0 0)} #979#return; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,356 INFO L290 TraceCheckUtils]: 7: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,357 INFO L290 TraceCheckUtils]: 8: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,357 INFO L290 TraceCheckUtils]: 9: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,357 INFO L290 TraceCheckUtils]: 10: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,358 INFO L290 TraceCheckUtils]: 11: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,358 INFO L290 TraceCheckUtils]: 12: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume main_#t~switch236#1; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,358 INFO L290 TraceCheckUtils]: 13: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,359 INFO L290 TraceCheckUtils]: 14: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,359 INFO L290 TraceCheckUtils]: 15: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 2 == choose_interrupt_1_~tmp~23#1; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,359 INFO L290 TraceCheckUtils]: 16: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 3 == choose_interrupt_1_~tmp~23#1; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,360 INFO L290 TraceCheckUtils]: 17: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} assume choose_interrupt_1_#t~switch223#1; {47379#(= ~ldv_irq_1_3~0 0)} is VALID [2022-02-20 22:05:27,361 INFO L272 TraceCheckUtils]: 18: Hoare triple {47379#(= ~ldv_irq_1_3~0 0)} call choose_interrupt_1_#t~ret227#1 := ldv_irq_1(~ldv_irq_1_3~0, ~ldv_irq_line_1_3~0, ~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset); {47420#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} is VALID [2022-02-20 22:05:27,361 INFO L290 TraceCheckUtils]: 19: Hoare triple {47420#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {47377#true} is VALID [2022-02-20 22:05:27,361 INFO L290 TraceCheckUtils]: 20: Hoare triple {47377#true} assume !(0 != ~state#1); {47392#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:27,362 INFO L290 TraceCheckUtils]: 21: Hoare triple {47392#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {47421#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:27,362 INFO L290 TraceCheckUtils]: 22: Hoare triple {47421#(= |ldv_irq_1_#res#1| 0)} assume true; {47421#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:27,363 INFO L284 TraceCheckUtils]: 23: Hoare quadruple {47421#(= |ldv_irq_1_#res#1| 0)} {47379#(= ~ldv_irq_1_3~0 0)} #987#return; {47389#(= |ULTIMATE.start_choose_interrupt_1_#t~ret227#1| 0)} is VALID [2022-02-20 22:05:27,364 INFO L290 TraceCheckUtils]: 24: Hoare triple {47389#(= |ULTIMATE.start_choose_interrupt_1_#t~ret227#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret227#1 && choose_interrupt_1_#t~ret227#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret227#1;havoc choose_interrupt_1_#t~ret227#1; {47390#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,364 INFO L290 TraceCheckUtils]: 25: Hoare triple {47390#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {47390#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,364 INFO L290 TraceCheckUtils]: 26: Hoare triple {47390#(= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {47390#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,365 INFO L290 TraceCheckUtils]: 27: Hoare triple {47390#(= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {47390#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,365 INFO L290 TraceCheckUtils]: 28: Hoare triple {47390#(= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {47390#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,365 INFO L290 TraceCheckUtils]: 29: Hoare triple {47390#(= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {47390#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,366 INFO L272 TraceCheckUtils]: 30: Hoare triple {47390#(= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {47391#(= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:27,367 INFO L290 TraceCheckUtils]: 31: Hoare triple {47391#(= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {47392#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:27,367 INFO L290 TraceCheckUtils]: 32: Hoare triple {47392#(= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {47378#false} is VALID [2022-02-20 22:05:27,367 INFO L290 TraceCheckUtils]: 33: Hoare triple {47378#false} assume #t~switch220#1; {47378#false} is VALID [2022-02-20 22:05:27,367 INFO L290 TraceCheckUtils]: 34: Hoare triple {47378#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {47378#false} is VALID [2022-02-20 22:05:27,367 INFO L272 TraceCheckUtils]: 35: Hoare triple {47378#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,368 INFO L290 TraceCheckUtils]: 36: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {47377#true} is VALID [2022-02-20 22:05:27,368 INFO L272 TraceCheckUtils]: 37: Hoare triple {47377#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,368 INFO L290 TraceCheckUtils]: 38: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {47377#true} is VALID [2022-02-20 22:05:27,368 INFO L290 TraceCheckUtils]: 39: Hoare triple {47377#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,369 INFO L290 TraceCheckUtils]: 40: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,369 INFO L284 TraceCheckUtils]: 41: Hoare quadruple {47377#true} {47377#true} #893#return; {47377#true} is VALID [2022-02-20 22:05:27,369 INFO L290 TraceCheckUtils]: 42: Hoare triple {47377#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {47377#true} is VALID [2022-02-20 22:05:27,369 INFO L290 TraceCheckUtils]: 43: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,369 INFO L284 TraceCheckUtils]: 44: Hoare quadruple {47377#true} {47378#false} #915#return; {47378#false} is VALID [2022-02-20 22:05:27,369 INFO L290 TraceCheckUtils]: 45: Hoare triple {47378#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {47378#false} is VALID [2022-02-20 22:05:27,369 INFO L290 TraceCheckUtils]: 46: Hoare triple {47378#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {47378#false} is VALID [2022-02-20 22:05:27,370 INFO L272 TraceCheckUtils]: 47: Hoare triple {47378#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,370 INFO L290 TraceCheckUtils]: 48: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {47377#true} is VALID [2022-02-20 22:05:27,370 INFO L272 TraceCheckUtils]: 49: Hoare triple {47377#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,370 INFO L290 TraceCheckUtils]: 50: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {47377#true} is VALID [2022-02-20 22:05:27,371 INFO L272 TraceCheckUtils]: 51: Hoare triple {47377#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:27,371 INFO L290 TraceCheckUtils]: 52: Hoare triple {47422#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {47377#true} is VALID [2022-02-20 22:05:27,371 INFO L290 TraceCheckUtils]: 53: Hoare triple {47377#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,371 INFO L290 TraceCheckUtils]: 54: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,372 INFO L284 TraceCheckUtils]: 55: Hoare quadruple {47377#true} {47377#true} #893#return; {47377#true} is VALID [2022-02-20 22:05:27,372 INFO L290 TraceCheckUtils]: 56: Hoare triple {47377#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {47377#true} is VALID [2022-02-20 22:05:27,372 INFO L290 TraceCheckUtils]: 57: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,372 INFO L284 TraceCheckUtils]: 58: Hoare quadruple {47377#true} {47377#true} #927#return; {47377#true} is VALID [2022-02-20 22:05:27,372 INFO L290 TraceCheckUtils]: 59: Hoare triple {47377#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {47377#true} is VALID [2022-02-20 22:05:27,372 INFO L290 TraceCheckUtils]: 60: Hoare triple {47377#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {47377#true} is VALID [2022-02-20 22:05:27,372 INFO L290 TraceCheckUtils]: 61: Hoare triple {47377#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {47377#true} is VALID [2022-02-20 22:05:27,373 INFO L290 TraceCheckUtils]: 62: Hoare triple {47377#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {47377#true} is VALID [2022-02-20 22:05:27,373 INFO L290 TraceCheckUtils]: 63: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,373 INFO L284 TraceCheckUtils]: 64: Hoare quadruple {47377#true} {47378#false} #917#return; {47378#false} is VALID [2022-02-20 22:05:27,373 INFO L290 TraceCheckUtils]: 65: Hoare triple {47378#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {47378#false} is VALID [2022-02-20 22:05:27,373 INFO L272 TraceCheckUtils]: 66: Hoare triple {47378#false} call ldv_spin_lock_check(); {47378#false} is VALID [2022-02-20 22:05:27,373 INFO L290 TraceCheckUtils]: 67: Hoare triple {47378#false} assume !(1 == ~ldv_init~0); {47378#false} is VALID [2022-02-20 22:05:27,373 INFO L272 TraceCheckUtils]: 68: Hoare triple {47378#false} call ldv_error(); {47378#false} is VALID [2022-02-20 22:05:27,374 INFO L290 TraceCheckUtils]: 69: Hoare triple {47378#false} assume !false; {47378#false} is VALID [2022-02-20 22:05:27,374 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:27,374 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:05:27,374 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374563865] [2022-02-20 22:05:27,374 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [374563865] provided 0 perfect and 1 imperfect interpolant sequences [2022-02-20 22:05:27,374 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [841248229] [2022-02-20 22:05:27,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:27,375 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-02-20 22:05:27,375 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:05:27,380 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-02-20 22:05:27,381 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-02-20 22:05:27,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,585 INFO L263 TraceCheckSpWp]: Trace formula consists of 633 conjuncts, 7 conjunts are in the unsatisfiable core [2022-02-20 22:05:27,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:27,625 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-02-20 22:05:27,902 INFO L290 TraceCheckUtils]: 0: Hoare triple {47377#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {47377#true} is VALID [2022-02-20 22:05:27,902 INFO L290 TraceCheckUtils]: 1: Hoare triple {47377#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {47377#true} is VALID [2022-02-20 22:05:27,902 INFO L272 TraceCheckUtils]: 2: Hoare triple {47377#true} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {47377#true} is VALID [2022-02-20 22:05:27,902 INFO L290 TraceCheckUtils]: 3: Hoare triple {47377#true} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 4: Hoare triple {47377#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 5: Hoare triple {47377#true} assume true; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {47377#true} {47377#true} #979#return; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 7: Hoare triple {47377#true} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 8: Hoare triple {47377#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 9: Hoare triple {47377#true} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 10: Hoare triple {47377#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 11: Hoare triple {47377#true} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 12: Hoare triple {47377#true} assume main_#t~switch236#1; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 13: Hoare triple {47377#true} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 14: Hoare triple {47377#true} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {47377#true} is VALID [2022-02-20 22:05:27,903 INFO L290 TraceCheckUtils]: 15: Hoare triple {47377#true} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 2 == choose_interrupt_1_~tmp~23#1; {47377#true} is VALID [2022-02-20 22:05:27,904 INFO L290 TraceCheckUtils]: 16: Hoare triple {47377#true} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 3 == choose_interrupt_1_~tmp~23#1; {47377#true} is VALID [2022-02-20 22:05:27,904 INFO L290 TraceCheckUtils]: 17: Hoare triple {47377#true} assume choose_interrupt_1_#t~switch223#1; {47377#true} is VALID [2022-02-20 22:05:27,904 INFO L272 TraceCheckUtils]: 18: Hoare triple {47377#true} call choose_interrupt_1_#t~ret227#1 := ldv_irq_1(~ldv_irq_1_3~0, ~ldv_irq_line_1_3~0, ~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset); {47377#true} is VALID [2022-02-20 22:05:27,904 INFO L290 TraceCheckUtils]: 19: Hoare triple {47377#true} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {47377#true} is VALID [2022-02-20 22:05:27,908 INFO L290 TraceCheckUtils]: 20: Hoare triple {47377#true} assume !(0 != ~state#1); {47503#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:27,909 INFO L290 TraceCheckUtils]: 21: Hoare triple {47503#(<= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {47507#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:27,909 INFO L290 TraceCheckUtils]: 22: Hoare triple {47507#(<= |ldv_irq_1_#res#1| 0)} assume true; {47507#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:27,910 INFO L284 TraceCheckUtils]: 23: Hoare quadruple {47507#(<= |ldv_irq_1_#res#1| 0)} {47377#true} #987#return; {47514#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret227#1| 0)} is VALID [2022-02-20 22:05:27,910 INFO L290 TraceCheckUtils]: 24: Hoare triple {47514#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret227#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret227#1 && choose_interrupt_1_#t~ret227#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret227#1;havoc choose_interrupt_1_#t~ret227#1; {47518#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,911 INFO L290 TraceCheckUtils]: 25: Hoare triple {47518#(<= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {47518#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,911 INFO L290 TraceCheckUtils]: 26: Hoare triple {47518#(<= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {47518#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,911 INFO L290 TraceCheckUtils]: 27: Hoare triple {47518#(<= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {47518#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,912 INFO L290 TraceCheckUtils]: 28: Hoare triple {47518#(<= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {47518#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,912 INFO L290 TraceCheckUtils]: 29: Hoare triple {47518#(<= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {47518#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:27,913 INFO L272 TraceCheckUtils]: 30: Hoare triple {47518#(<= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {47537#(<= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:27,913 INFO L290 TraceCheckUtils]: 31: Hoare triple {47537#(<= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {47503#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:27,913 INFO L290 TraceCheckUtils]: 32: Hoare triple {47503#(<= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {47503#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:27,914 INFO L290 TraceCheckUtils]: 33: Hoare triple {47503#(<= |ldv_irq_1_~state#1| 0)} assume #t~switch220#1; {47503#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:27,915 INFO L290 TraceCheckUtils]: 34: Hoare triple {47503#(<= |ldv_irq_1_~state#1| 0)} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {47378#false} is VALID [2022-02-20 22:05:27,915 INFO L272 TraceCheckUtils]: 35: Hoare triple {47378#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {47378#false} is VALID [2022-02-20 22:05:27,916 INFO L290 TraceCheckUtils]: 36: Hoare triple {47378#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {47378#false} is VALID [2022-02-20 22:05:27,916 INFO L272 TraceCheckUtils]: 37: Hoare triple {47378#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {47378#false} is VALID [2022-02-20 22:05:27,916 INFO L290 TraceCheckUtils]: 38: Hoare triple {47378#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {47378#false} is VALID [2022-02-20 22:05:27,916 INFO L290 TraceCheckUtils]: 39: Hoare triple {47378#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {47378#false} is VALID [2022-02-20 22:05:27,916 INFO L290 TraceCheckUtils]: 40: Hoare triple {47378#false} assume true; {47378#false} is VALID [2022-02-20 22:05:27,916 INFO L284 TraceCheckUtils]: 41: Hoare quadruple {47378#false} {47378#false} #893#return; {47378#false} is VALID [2022-02-20 22:05:27,916 INFO L290 TraceCheckUtils]: 42: Hoare triple {47378#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {47378#false} is VALID [2022-02-20 22:05:27,917 INFO L290 TraceCheckUtils]: 43: Hoare triple {47378#false} assume true; {47378#false} is VALID [2022-02-20 22:05:27,917 INFO L284 TraceCheckUtils]: 44: Hoare quadruple {47378#false} {47378#false} #915#return; {47378#false} is VALID [2022-02-20 22:05:27,917 INFO L290 TraceCheckUtils]: 45: Hoare triple {47378#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {47378#false} is VALID [2022-02-20 22:05:27,917 INFO L290 TraceCheckUtils]: 46: Hoare triple {47378#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {47378#false} is VALID [2022-02-20 22:05:27,917 INFO L272 TraceCheckUtils]: 47: Hoare triple {47378#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {47378#false} is VALID [2022-02-20 22:05:27,917 INFO L290 TraceCheckUtils]: 48: Hoare triple {47378#false} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {47378#false} is VALID [2022-02-20 22:05:27,917 INFO L272 TraceCheckUtils]: 49: Hoare triple {47378#false} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {47378#false} is VALID [2022-02-20 22:05:27,918 INFO L290 TraceCheckUtils]: 50: Hoare triple {47378#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {47378#false} is VALID [2022-02-20 22:05:27,918 INFO L272 TraceCheckUtils]: 51: Hoare triple {47378#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {47378#false} is VALID [2022-02-20 22:05:27,918 INFO L290 TraceCheckUtils]: 52: Hoare triple {47378#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {47378#false} is VALID [2022-02-20 22:05:27,918 INFO L290 TraceCheckUtils]: 53: Hoare triple {47378#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {47378#false} is VALID [2022-02-20 22:05:27,918 INFO L290 TraceCheckUtils]: 54: Hoare triple {47378#false} assume true; {47378#false} is VALID [2022-02-20 22:05:27,918 INFO L284 TraceCheckUtils]: 55: Hoare quadruple {47378#false} {47378#false} #893#return; {47378#false} is VALID [2022-02-20 22:05:27,918 INFO L290 TraceCheckUtils]: 56: Hoare triple {47378#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {47378#false} is VALID [2022-02-20 22:05:27,919 INFO L290 TraceCheckUtils]: 57: Hoare triple {47378#false} assume true; {47378#false} is VALID [2022-02-20 22:05:27,919 INFO L284 TraceCheckUtils]: 58: Hoare quadruple {47378#false} {47378#false} #927#return; {47378#false} is VALID [2022-02-20 22:05:27,919 INFO L290 TraceCheckUtils]: 59: Hoare triple {47378#false} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {47378#false} is VALID [2022-02-20 22:05:27,919 INFO L290 TraceCheckUtils]: 60: Hoare triple {47378#false} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {47378#false} is VALID [2022-02-20 22:05:27,919 INFO L290 TraceCheckUtils]: 61: Hoare triple {47378#false} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {47378#false} is VALID [2022-02-20 22:05:27,919 INFO L290 TraceCheckUtils]: 62: Hoare triple {47378#false} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {47378#false} is VALID [2022-02-20 22:05:27,919 INFO L290 TraceCheckUtils]: 63: Hoare triple {47378#false} assume true; {47378#false} is VALID [2022-02-20 22:05:27,920 INFO L284 TraceCheckUtils]: 64: Hoare quadruple {47378#false} {47378#false} #917#return; {47378#false} is VALID [2022-02-20 22:05:27,920 INFO L290 TraceCheckUtils]: 65: Hoare triple {47378#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {47378#false} is VALID [2022-02-20 22:05:27,920 INFO L272 TraceCheckUtils]: 66: Hoare triple {47378#false} call ldv_spin_lock_check(); {47378#false} is VALID [2022-02-20 22:05:27,920 INFO L290 TraceCheckUtils]: 67: Hoare triple {47378#false} assume !(1 == ~ldv_init~0); {47378#false} is VALID [2022-02-20 22:05:27,920 INFO L272 TraceCheckUtils]: 68: Hoare triple {47378#false} call ldv_error(); {47378#false} is VALID [2022-02-20 22:05:27,920 INFO L290 TraceCheckUtils]: 69: Hoare triple {47378#false} assume !false; {47378#false} is VALID [2022-02-20 22:05:27,921 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-02-20 22:05:27,921 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-02-20 22:05:27,921 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [841248229] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:05:27,921 INFO L191 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-02-20 22:05:27,921 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [11] total 16 [2022-02-20 22:05:27,921 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174105381] [2022-02-20 22:05:27,921 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:05:27,922 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.714285714285714) internal successors, (47), 5 states have internal predecessors, (47), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) Word has length 70 [2022-02-20 22:05:27,922 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:05:27,922 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 6.714285714285714) internal successors, (47), 5 states have internal predecessors, (47), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:27,973 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:27,974 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-02-20 22:05:27,974 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:05:27,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-02-20 22:05:27,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=204, Unknown=0, NotChecked=0, Total=240 [2022-02-20 22:05:27,974 INFO L87 Difference]: Start difference. First operand 1289 states and 1648 transitions. Second operand has 7 states, 7 states have (on average 6.714285714285714) internal successors, (47), 5 states have internal predecessors, (47), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:29,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:29,948 INFO L93 Difference]: Finished difference Result 2893 states and 3694 transitions. [2022-02-20 22:05:29,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-02-20 22:05:29,948 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.714285714285714) internal successors, (47), 5 states have internal predecessors, (47), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) Word has length 70 [2022-02-20 22:05:29,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:05:29,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 6.714285714285714) internal successors, (47), 5 states have internal predecessors, (47), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:29,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 1029 transitions. [2022-02-20 22:05:29,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 6.714285714285714) internal successors, (47), 5 states have internal predecessors, (47), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:29,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 1029 transitions. [2022-02-20 22:05:29,966 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 12 states and 1029 transitions. [2022-02-20 22:05:30,705 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 1029 edges. 1029 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:30,822 INFO L225 Difference]: With dead ends: 2893 [2022-02-20 22:05:30,822 INFO L226 Difference]: Without dead ends: 1628 [2022-02-20 22:05:30,824 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 78 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=77, Invalid=429, Unknown=0, NotChecked=0, Total=506 [2022-02-20 22:05:30,825 INFO L933 BasicCegarLoop]: 402 mSDtfsCounter, 337 mSDsluCounter, 1928 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 341 SdHoareTripleChecker+Valid, 2330 SdHoareTripleChecker+Invalid, 56 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-02-20 22:05:30,825 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [341 Valid, 2330 Invalid, 56 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 54 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-02-20 22:05:30,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1628 states. [2022-02-20 22:05:31,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1628 to 1289. [2022-02-20 22:05:31,046 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:05:31,048 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1628 states. Second operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:31,050 INFO L74 IsIncluded]: Start isIncluded. First operand 1628 states. Second operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:31,051 INFO L87 Difference]: Start difference. First operand 1628 states. Second operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:31,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:31,175 INFO L93 Difference]: Finished difference Result 1628 states and 2069 transitions. [2022-02-20 22:05:31,175 INFO L276 IsEmpty]: Start isEmpty. Operand 1628 states and 2069 transitions. [2022-02-20 22:05:31,179 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:31,179 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:31,182 INFO L74 IsIncluded]: Start isIncluded. First operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) Second operand 1628 states. [2022-02-20 22:05:31,183 INFO L87 Difference]: Start difference. First operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) Second operand 1628 states. [2022-02-20 22:05:31,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:31,321 INFO L93 Difference]: Finished difference Result 1628 states and 2069 transitions. [2022-02-20 22:05:31,321 INFO L276 IsEmpty]: Start isEmpty. Operand 1628 states and 2069 transitions. [2022-02-20 22:05:31,325 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:31,325 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:31,325 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:05:31,325 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:05:31,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 981 states have (on average 1.275229357798165) internal successors, (1251), 992 states have internal predecessors, (1251), 186 states have call successors, (186), 113 states have call predecessors, (186), 121 states have return successors, (211), 185 states have call predecessors, (211), 185 states have call successors, (211) [2022-02-20 22:05:31,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1648 transitions. [2022-02-20 22:05:31,441 INFO L78 Accepts]: Start accepts. Automaton has 1289 states and 1648 transitions. Word has length 70 [2022-02-20 22:05:31,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:05:31,441 INFO L470 AbstractCegarLoop]: Abstraction has 1289 states and 1648 transitions. [2022-02-20 22:05:31,441 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 6.714285714285714) internal successors, (47), 5 states have internal predecessors, (47), 3 states have call successors, (9), 3 states have call predecessors, (9), 3 states have return successors, (6), 3 states have call predecessors, (6), 2 states have call successors, (6) [2022-02-20 22:05:31,441 INFO L276 IsEmpty]: Start isEmpty. Operand 1289 states and 1648 transitions. [2022-02-20 22:05:31,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2022-02-20 22:05:31,443 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:05:31,443 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:05:31,461 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-02-20 22:05:31,647 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-02-20 22:05:31,647 INFO L402 AbstractCegarLoop]: === Iteration 11 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:05:31,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:05:31,648 INFO L85 PathProgramCache]: Analyzing trace with hash -628405765, now seen corresponding path program 1 times [2022-02-20 22:05:31,648 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:05:31,648 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226381064] [2022-02-20 22:05:31,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:31,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:05:31,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:31,704 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:05:31,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:31,710 INFO L290 TraceCheckUtils]: 0: Hoare triple {56553#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {56516#true} is VALID [2022-02-20 22:05:31,710 INFO L290 TraceCheckUtils]: 1: Hoare triple {56516#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,710 INFO L290 TraceCheckUtils]: 2: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,710 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {56516#true} {56516#true} #979#return; {56516#true} is VALID [2022-02-20 22:05:31,710 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2022-02-20 22:05:31,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:31,716 INFO L290 TraceCheckUtils]: 0: Hoare triple {56553#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {56516#true} is VALID [2022-02-20 22:05:31,716 INFO L290 TraceCheckUtils]: 1: Hoare triple {56516#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,716 INFO L290 TraceCheckUtils]: 2: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,717 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {56516#true} {56522#(= ~ldv_state_variable_2~0 1)} #991#return; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,722 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 41 [2022-02-20 22:05:31,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:31,729 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:31,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:31,733 INFO L290 TraceCheckUtils]: 0: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {56516#true} is VALID [2022-02-20 22:05:31,734 INFO L290 TraceCheckUtils]: 1: Hoare triple {56516#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,734 INFO L290 TraceCheckUtils]: 2: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,734 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {56516#true} {56516#true} #893#return; {56516#true} is VALID [2022-02-20 22:05:31,734 INFO L290 TraceCheckUtils]: 0: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {56516#true} is VALID [2022-02-20 22:05:31,735 INFO L272 TraceCheckUtils]: 1: Hoare triple {56516#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,735 INFO L290 TraceCheckUtils]: 2: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {56516#true} is VALID [2022-02-20 22:05:31,735 INFO L290 TraceCheckUtils]: 3: Hoare triple {56516#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,735 INFO L290 TraceCheckUtils]: 4: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,735 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {56516#true} {56516#true} #893#return; {56516#true} is VALID [2022-02-20 22:05:31,735 INFO L290 TraceCheckUtils]: 6: Hoare triple {56516#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {56516#true} is VALID [2022-02-20 22:05:31,736 INFO L290 TraceCheckUtils]: 7: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,736 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {56516#true} {56517#false} #929#return; {56517#false} is VALID [2022-02-20 22:05:31,736 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 52 [2022-02-20 22:05:31,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:31,744 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:31,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:31,751 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:31,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:31,760 INFO L290 TraceCheckUtils]: 0: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {56516#true} is VALID [2022-02-20 22:05:31,760 INFO L290 TraceCheckUtils]: 1: Hoare triple {56516#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,761 INFO L290 TraceCheckUtils]: 2: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,761 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {56516#true} {56516#true} #893#return; {56516#true} is VALID [2022-02-20 22:05:31,761 INFO L290 TraceCheckUtils]: 0: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {56516#true} is VALID [2022-02-20 22:05:31,762 INFO L272 TraceCheckUtils]: 1: Hoare triple {56516#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,762 INFO L290 TraceCheckUtils]: 2: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {56516#true} is VALID [2022-02-20 22:05:31,762 INFO L290 TraceCheckUtils]: 3: Hoare triple {56516#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,762 INFO L290 TraceCheckUtils]: 4: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,762 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {56516#true} {56516#true} #893#return; {56516#true} is VALID [2022-02-20 22:05:31,762 INFO L290 TraceCheckUtils]: 6: Hoare triple {56516#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {56516#true} is VALID [2022-02-20 22:05:31,762 INFO L290 TraceCheckUtils]: 7: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,763 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {56516#true} {56516#true} #927#return; {56516#true} is VALID [2022-02-20 22:05:31,763 INFO L290 TraceCheckUtils]: 0: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {56516#true} is VALID [2022-02-20 22:05:31,763 INFO L272 TraceCheckUtils]: 1: Hoare triple {56516#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,764 INFO L290 TraceCheckUtils]: 2: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {56516#true} is VALID [2022-02-20 22:05:31,764 INFO L272 TraceCheckUtils]: 3: Hoare triple {56516#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,764 INFO L290 TraceCheckUtils]: 4: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {56516#true} is VALID [2022-02-20 22:05:31,764 INFO L290 TraceCheckUtils]: 5: Hoare triple {56516#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,765 INFO L290 TraceCheckUtils]: 6: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,765 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {56516#true} {56516#true} #893#return; {56516#true} is VALID [2022-02-20 22:05:31,765 INFO L290 TraceCheckUtils]: 8: Hoare triple {56516#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {56516#true} is VALID [2022-02-20 22:05:31,765 INFO L290 TraceCheckUtils]: 9: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,765 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {56516#true} {56516#true} #927#return; {56516#true} is VALID [2022-02-20 22:05:31,765 INFO L290 TraceCheckUtils]: 11: Hoare triple {56516#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {56516#true} is VALID [2022-02-20 22:05:31,765 INFO L290 TraceCheckUtils]: 12: Hoare triple {56516#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {56516#true} is VALID [2022-02-20 22:05:31,766 INFO L290 TraceCheckUtils]: 13: Hoare triple {56516#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {56516#true} is VALID [2022-02-20 22:05:31,766 INFO L290 TraceCheckUtils]: 14: Hoare triple {56516#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {56516#true} is VALID [2022-02-20 22:05:31,766 INFO L290 TraceCheckUtils]: 15: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,766 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {56516#true} {56517#false} #931#return; {56517#false} is VALID [2022-02-20 22:05:31,766 INFO L290 TraceCheckUtils]: 0: Hoare triple {56516#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {56516#true} is VALID [2022-02-20 22:05:31,766 INFO L290 TraceCheckUtils]: 1: Hoare triple {56516#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {56516#true} is VALID [2022-02-20 22:05:31,767 INFO L272 TraceCheckUtils]: 2: Hoare triple {56516#true} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {56553#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,767 INFO L290 TraceCheckUtils]: 3: Hoare triple {56553#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {56516#true} is VALID [2022-02-20 22:05:31,767 INFO L290 TraceCheckUtils]: 4: Hoare triple {56516#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,767 INFO L290 TraceCheckUtils]: 5: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,768 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {56516#true} {56516#true} #979#return; {56516#true} is VALID [2022-02-20 22:05:31,768 INFO L290 TraceCheckUtils]: 7: Hoare triple {56516#true} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {56516#true} is VALID [2022-02-20 22:05:31,768 INFO L290 TraceCheckUtils]: 8: Hoare triple {56516#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {56516#true} is VALID [2022-02-20 22:05:31,768 INFO L290 TraceCheckUtils]: 9: Hoare triple {56516#true} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {56516#true} is VALID [2022-02-20 22:05:31,768 INFO L290 TraceCheckUtils]: 10: Hoare triple {56516#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {56516#true} is VALID [2022-02-20 22:05:31,768 INFO L290 TraceCheckUtils]: 11: Hoare triple {56516#true} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {56516#true} is VALID [2022-02-20 22:05:31,768 INFO L290 TraceCheckUtils]: 12: Hoare triple {56516#true} assume !main_#t~switch236#1;main_#t~switch236#1 := main_#t~switch236#1 || 1 == main_~tmp___1~5#1; {56516#true} is VALID [2022-02-20 22:05:31,769 INFO L290 TraceCheckUtils]: 13: Hoare triple {56516#true} assume main_#t~switch236#1; {56516#true} is VALID [2022-02-20 22:05:31,769 INFO L290 TraceCheckUtils]: 14: Hoare triple {56516#true} assume 0 != ~ldv_state_variable_0~0;assume -2147483648 <= main_#t~nondet237#1 && main_#t~nondet237#1 <= 2147483647;main_~tmp___2~1#1 := main_#t~nondet237#1;havoc main_#t~nondet237#1;main_#t~switch238#1 := 0 == main_~tmp___2~1#1; {56516#true} is VALID [2022-02-20 22:05:31,769 INFO L290 TraceCheckUtils]: 15: Hoare triple {56516#true} assume !main_#t~switch238#1;main_#t~switch238#1 := main_#t~switch238#1 || 1 == main_~tmp___2~1#1; {56516#true} is VALID [2022-02-20 22:05:31,769 INFO L290 TraceCheckUtils]: 16: Hoare triple {56516#true} assume main_#t~switch238#1; {56516#true} is VALID [2022-02-20 22:05:31,769 INFO L290 TraceCheckUtils]: 17: Hoare triple {56516#true} assume 1 == ~ldv_state_variable_0~0;assume { :begin_inline_tegra_rtc_init } true;havoc tegra_rtc_init_#res#1;havoc tegra_rtc_init_#t~ret218#1, tegra_rtc_init_~tmp~21#1;havoc tegra_rtc_init_~tmp~21#1;assume { :begin_inline_platform_driver_probe } true;platform_driver_probe_#in~arg0#1.base, platform_driver_probe_#in~arg0#1.offset, platform_driver_probe_#in~arg1#1.base, platform_driver_probe_#in~arg1#1.offset := ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, #funAddr~tegra_rtc_probe.base, #funAddr~tegra_rtc_probe.offset;havoc platform_driver_probe_#res#1;havoc platform_driver_probe_#t~nondet282#1, platform_driver_probe_~arg0#1.base, platform_driver_probe_~arg0#1.offset, platform_driver_probe_~arg1#1.base, platform_driver_probe_~arg1#1.offset;platform_driver_probe_~arg0#1.base, platform_driver_probe_~arg0#1.offset := platform_driver_probe_#in~arg0#1.base, platform_driver_probe_#in~arg0#1.offset;platform_driver_probe_~arg1#1.base, platform_driver_probe_~arg1#1.offset := platform_driver_probe_#in~arg1#1.base, platform_driver_probe_#in~arg1#1.offset;assume -2147483648 <= platform_driver_probe_#t~nondet282#1 && platform_driver_probe_#t~nondet282#1 <= 2147483647;platform_driver_probe_#res#1 := platform_driver_probe_#t~nondet282#1;havoc platform_driver_probe_#t~nondet282#1; {56516#true} is VALID [2022-02-20 22:05:31,769 INFO L290 TraceCheckUtils]: 18: Hoare triple {56516#true} tegra_rtc_init_#t~ret218#1 := platform_driver_probe_#res#1;assume { :end_inline_platform_driver_probe } true;assume -2147483648 <= tegra_rtc_init_#t~ret218#1 && tegra_rtc_init_#t~ret218#1 <= 2147483647;tegra_rtc_init_~tmp~21#1 := tegra_rtc_init_#t~ret218#1;havoc tegra_rtc_init_#t~ret218#1;tegra_rtc_init_#res#1 := tegra_rtc_init_~tmp~21#1; {56516#true} is VALID [2022-02-20 22:05:31,770 INFO L290 TraceCheckUtils]: 19: Hoare triple {56516#true} main_#t~ret239#1 := tegra_rtc_init_#res#1;assume { :end_inline_tegra_rtc_init } true;assume -2147483648 <= main_#t~ret239#1 && main_#t~ret239#1 <= 2147483647;~ldv_retval_0~0 := main_#t~ret239#1;havoc main_#t~ret239#1; {56516#true} is VALID [2022-02-20 22:05:31,770 INFO L290 TraceCheckUtils]: 20: Hoare triple {56516#true} assume 0 == ~ldv_retval_0~0;~ldv_state_variable_0~0 := 3;~ldv_state_variable_2~0 := 1;assume { :begin_inline_ldv_initialize_platform_driver_2 } true;havoc ldv_initialize_platform_driver_2_#t~ret231#1.base, ldv_initialize_platform_driver_2_#t~ret231#1.offset, ldv_initialize_platform_driver_2_~tmp~25#1.base, ldv_initialize_platform_driver_2_~tmp~25#1.offset;havoc ldv_initialize_platform_driver_2_~tmp~25#1.base, ldv_initialize_platform_driver_2_~tmp~25#1.offset; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,771 INFO L272 TraceCheckUtils]: 21: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} call ldv_initialize_platform_driver_2_#t~ret231#1.base, ldv_initialize_platform_driver_2_#t~ret231#1.offset := ldv_zalloc(624); {56553#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,771 INFO L290 TraceCheckUtils]: 22: Hoare triple {56553#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {56516#true} is VALID [2022-02-20 22:05:31,771 INFO L290 TraceCheckUtils]: 23: Hoare triple {56516#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,771 INFO L290 TraceCheckUtils]: 24: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,772 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {56516#true} {56522#(= ~ldv_state_variable_2~0 1)} #991#return; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,772 INFO L290 TraceCheckUtils]: 26: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} ldv_initialize_platform_driver_2_~tmp~25#1.base, ldv_initialize_platform_driver_2_~tmp~25#1.offset := ldv_initialize_platform_driver_2_#t~ret231#1.base, ldv_initialize_platform_driver_2_#t~ret231#1.offset;havoc ldv_initialize_platform_driver_2_#t~ret231#1.base, ldv_initialize_platform_driver_2_#t~ret231#1.offset;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := ldv_initialize_platform_driver_2_~tmp~25#1.base, ldv_initialize_platform_driver_2_~tmp~25#1.offset; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,773 INFO L290 TraceCheckUtils]: 27: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume { :end_inline_ldv_initialize_platform_driver_2 } true; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,773 INFO L290 TraceCheckUtils]: 28: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume !(0 != ~ldv_retval_0~0); {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,773 INFO L290 TraceCheckUtils]: 29: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,774 INFO L290 TraceCheckUtils]: 30: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume !main_#t~switch236#1;main_#t~switch236#1 := main_#t~switch236#1 || 1 == main_~tmp___1~5#1; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,774 INFO L290 TraceCheckUtils]: 31: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume !main_#t~switch236#1;main_#t~switch236#1 := main_#t~switch236#1 || 2 == main_~tmp___1~5#1; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,774 INFO L290 TraceCheckUtils]: 32: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume !main_#t~switch236#1;main_#t~switch236#1 := main_#t~switch236#1 || 3 == main_~tmp___1~5#1; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,775 INFO L290 TraceCheckUtils]: 33: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume main_#t~switch236#1; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,775 INFO L290 TraceCheckUtils]: 34: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume 0 != ~ldv_state_variable_2~0;assume -2147483648 <= main_#t~nondet255#1 && main_#t~nondet255#1 <= 2147483647;main_~tmp___4~1#1 := main_#t~nondet255#1;havoc main_#t~nondet255#1;main_#t~switch256#1 := 0 == main_~tmp___4~1#1; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,775 INFO L290 TraceCheckUtils]: 35: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume main_#t~switch256#1; {56522#(= ~ldv_state_variable_2~0 1)} is VALID [2022-02-20 22:05:31,776 INFO L290 TraceCheckUtils]: 36: Hoare triple {56522#(= ~ldv_state_variable_2~0 1)} assume 4 == ~ldv_state_variable_2~0; {56517#false} is VALID [2022-02-20 22:05:31,776 INFO L272 TraceCheckUtils]: 37: Hoare triple {56517#false} call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset); {56517#false} is VALID [2022-02-20 22:05:31,776 INFO L290 TraceCheckUtils]: 38: Hoare triple {56517#false} ~pdev.base, ~pdev.offset := #in~pdev.base, #in~pdev.offset; {56517#false} is VALID [2022-02-20 22:05:31,776 INFO L272 TraceCheckUtils]: 39: Hoare triple {56517#false} call #t~ret217 := tegra_rtc_alarm_irq_enable(~pdev.base, 12 + ~pdev.offset, 0); {56517#false} is VALID [2022-02-20 22:05:31,776 INFO L290 TraceCheckUtils]: 40: Hoare triple {56517#false} ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;~enabled := #in~enabled;havoc ~info~4.base, ~info~4.offset;havoc ~tmp~13.base, ~tmp~13.offset;havoc ~status~0;havoc ~sl_irq_flags~1;havoc ~__v~3;havoc ~__v___0~3; {56517#false} is VALID [2022-02-20 22:05:31,777 INFO L272 TraceCheckUtils]: 41: Hoare triple {56517#false} call #t~ret108.base, #t~ret108.offset := dev_get_drvdata(~dev.base, ~dev.offset); {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,777 INFO L290 TraceCheckUtils]: 42: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {56516#true} is VALID [2022-02-20 22:05:31,777 INFO L272 TraceCheckUtils]: 43: Hoare triple {56516#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,777 INFO L290 TraceCheckUtils]: 44: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {56516#true} is VALID [2022-02-20 22:05:31,777 INFO L290 TraceCheckUtils]: 45: Hoare triple {56516#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,778 INFO L290 TraceCheckUtils]: 46: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,778 INFO L284 TraceCheckUtils]: 47: Hoare quadruple {56516#true} {56516#true} #893#return; {56516#true} is VALID [2022-02-20 22:05:31,778 INFO L290 TraceCheckUtils]: 48: Hoare triple {56516#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {56516#true} is VALID [2022-02-20 22:05:31,778 INFO L290 TraceCheckUtils]: 49: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,778 INFO L284 TraceCheckUtils]: 50: Hoare quadruple {56516#true} {56517#false} #929#return; {56517#false} is VALID [2022-02-20 22:05:31,778 INFO L290 TraceCheckUtils]: 51: Hoare triple {56517#false} ~tmp~13.base, ~tmp~13.offset := #t~ret108.base, #t~ret108.offset;havoc #t~ret108.base, #t~ret108.offset;~info~4.base, ~info~4.offset := ~tmp~13.base, ~tmp~13.offset; {56517#false} is VALID [2022-02-20 22:05:31,778 INFO L272 TraceCheckUtils]: 52: Hoare triple {56517#false} call #t~ret109 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,779 INFO L290 TraceCheckUtils]: 53: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {56516#true} is VALID [2022-02-20 22:05:31,779 INFO L272 TraceCheckUtils]: 54: Hoare triple {56516#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,779 INFO L290 TraceCheckUtils]: 55: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {56516#true} is VALID [2022-02-20 22:05:31,780 INFO L272 TraceCheckUtils]: 56: Hoare triple {56516#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:31,780 INFO L290 TraceCheckUtils]: 57: Hoare triple {56554#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {56516#true} is VALID [2022-02-20 22:05:31,780 INFO L290 TraceCheckUtils]: 58: Hoare triple {56516#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {56516#true} is VALID [2022-02-20 22:05:31,780 INFO L290 TraceCheckUtils]: 59: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,780 INFO L284 TraceCheckUtils]: 60: Hoare quadruple {56516#true} {56516#true} #893#return; {56516#true} is VALID [2022-02-20 22:05:31,781 INFO L290 TraceCheckUtils]: 61: Hoare triple {56516#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {56516#true} is VALID [2022-02-20 22:05:31,781 INFO L290 TraceCheckUtils]: 62: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,781 INFO L284 TraceCheckUtils]: 63: Hoare quadruple {56516#true} {56516#true} #927#return; {56516#true} is VALID [2022-02-20 22:05:31,781 INFO L290 TraceCheckUtils]: 64: Hoare triple {56516#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {56516#true} is VALID [2022-02-20 22:05:31,781 INFO L290 TraceCheckUtils]: 65: Hoare triple {56516#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {56516#true} is VALID [2022-02-20 22:05:31,781 INFO L290 TraceCheckUtils]: 66: Hoare triple {56516#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {56516#true} is VALID [2022-02-20 22:05:31,781 INFO L290 TraceCheckUtils]: 67: Hoare triple {56516#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {56516#true} is VALID [2022-02-20 22:05:31,782 INFO L290 TraceCheckUtils]: 68: Hoare triple {56516#true} assume true; {56516#true} is VALID [2022-02-20 22:05:31,782 INFO L284 TraceCheckUtils]: 69: Hoare quadruple {56516#true} {56517#false} #931#return; {56517#false} is VALID [2022-02-20 22:05:31,782 INFO L290 TraceCheckUtils]: 70: Hoare triple {56517#false} assume -2147483648 <= #t~ret109 && #t~ret109 <= 2147483647;havoc #t~ret109; {56517#false} is VALID [2022-02-20 22:05:31,782 INFO L272 TraceCheckUtils]: 71: Hoare triple {56517#false} call ldv_spin_lock_check(); {56517#false} is VALID [2022-02-20 22:05:31,782 INFO L290 TraceCheckUtils]: 72: Hoare triple {56517#false} assume !(1 == ~ldv_init~0); {56517#false} is VALID [2022-02-20 22:05:31,782 INFO L272 TraceCheckUtils]: 73: Hoare triple {56517#false} call ldv_error(); {56517#false} is VALID [2022-02-20 22:05:31,782 INFO L290 TraceCheckUtils]: 74: Hoare triple {56517#false} assume !false; {56517#false} is VALID [2022-02-20 22:05:31,783 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-02-20 22:05:31,783 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:05:31,783 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226381064] [2022-02-20 22:05:31,783 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226381064] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-20 22:05:31,784 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-20 22:05:31,784 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-20 22:05:31,784 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1711914193] [2022-02-20 22:05:31,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-20 22:05:31,784 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 9.6) internal successors, (48), 3 states have internal predecessors, (48), 3 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 75 [2022-02-20 22:05:31,785 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:05:31,785 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 9.6) internal successors, (48), 3 states have internal predecessors, (48), 3 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2022-02-20 22:05:31,834 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 64 edges. 64 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:31,834 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-02-20 22:05:31,834 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:05:31,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-20 22:05:31,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2022-02-20 22:05:31,835 INFO L87 Difference]: Start difference. First operand 1289 states and 1648 transitions. Second operand has 5 states, 5 states have (on average 9.6) internal successors, (48), 3 states have internal predecessors, (48), 3 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2022-02-20 22:05:34,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:34,432 INFO L93 Difference]: Finished difference Result 3232 states and 4215 transitions. [2022-02-20 22:05:34,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-20 22:05:34,433 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 9.6) internal successors, (48), 3 states have internal predecessors, (48), 3 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 75 [2022-02-20 22:05:34,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-02-20 22:05:34,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 9.6) internal successors, (48), 3 states have internal predecessors, (48), 3 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2022-02-20 22:05:34,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 1066 transitions. [2022-02-20 22:05:34,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 9.6) internal successors, (48), 3 states have internal predecessors, (48), 3 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2022-02-20 22:05:34,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 1066 transitions. [2022-02-20 22:05:34,453 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with 6 states and 1066 transitions. [2022-02-20 22:05:35,351 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 1066 edges. 1066 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:35,519 INFO L225 Difference]: With dead ends: 3232 [2022-02-20 22:05:35,519 INFO L226 Difference]: Without dead ends: 1967 [2022-02-20 22:05:35,521 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2022-02-20 22:05:35,521 INFO L933 BasicCegarLoop]: 543 mSDtfsCounter, 324 mSDsluCounter, 677 mSDsCounter, 0 mSdLazyCounter, 545 mSolverCounterSat, 100 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 346 SdHoareTripleChecker+Valid, 1220 SdHoareTripleChecker+Invalid, 645 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 100 IncrementalHoareTripleChecker+Valid, 545 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-02-20 22:05:35,522 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [346 Valid, 1220 Invalid, 645 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [100 Valid, 545 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-02-20 22:05:35,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1967 states. [2022-02-20 22:05:35,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1967 to 1610. [2022-02-20 22:05:35,776 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-20 22:05:35,779 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1967 states. Second operand has 1610 states, 1263 states have (on average 1.2866191607284243) internal successors, (1625), 1279 states have internal predecessors, (1625), 203 states have call successors, (203), 133 states have call predecessors, (203), 143 states have return successors, (230), 200 states have call predecessors, (230), 202 states have call successors, (230) [2022-02-20 22:05:35,780 INFO L74 IsIncluded]: Start isIncluded. First operand 1967 states. Second operand has 1610 states, 1263 states have (on average 1.2866191607284243) internal successors, (1625), 1279 states have internal predecessors, (1625), 203 states have call successors, (203), 133 states have call predecessors, (203), 143 states have return successors, (230), 200 states have call predecessors, (230), 202 states have call successors, (230) [2022-02-20 22:05:35,782 INFO L87 Difference]: Start difference. First operand 1967 states. Second operand has 1610 states, 1263 states have (on average 1.2866191607284243) internal successors, (1625), 1279 states have internal predecessors, (1625), 203 states have call successors, (203), 133 states have call predecessors, (203), 143 states have return successors, (230), 200 states have call predecessors, (230), 202 states have call successors, (230) [2022-02-20 22:05:35,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:35,938 INFO L93 Difference]: Finished difference Result 1967 states and 2558 transitions. [2022-02-20 22:05:35,938 INFO L276 IsEmpty]: Start isEmpty. Operand 1967 states and 2558 transitions. [2022-02-20 22:05:35,942 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:35,942 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:35,944 INFO L74 IsIncluded]: Start isIncluded. First operand has 1610 states, 1263 states have (on average 1.2866191607284243) internal successors, (1625), 1279 states have internal predecessors, (1625), 203 states have call successors, (203), 133 states have call predecessors, (203), 143 states have return successors, (230), 200 states have call predecessors, (230), 202 states have call successors, (230) Second operand 1967 states. [2022-02-20 22:05:35,945 INFO L87 Difference]: Start difference. First operand has 1610 states, 1263 states have (on average 1.2866191607284243) internal successors, (1625), 1279 states have internal predecessors, (1625), 203 states have call successors, (203), 133 states have call predecessors, (203), 143 states have return successors, (230), 200 states have call predecessors, (230), 202 states have call successors, (230) Second operand 1967 states. [2022-02-20 22:05:36,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-20 22:05:36,079 INFO L93 Difference]: Finished difference Result 1967 states and 2558 transitions. [2022-02-20 22:05:36,079 INFO L276 IsEmpty]: Start isEmpty. Operand 1967 states and 2558 transitions. [2022-02-20 22:05:36,082 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-20 22:05:36,082 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-20 22:05:36,082 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-20 22:05:36,082 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-20 22:05:36,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1610 states, 1263 states have (on average 1.2866191607284243) internal successors, (1625), 1279 states have internal predecessors, (1625), 203 states have call successors, (203), 133 states have call predecessors, (203), 143 states have return successors, (230), 200 states have call predecessors, (230), 202 states have call successors, (230) [2022-02-20 22:05:36,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1610 states to 1610 states and 2058 transitions. [2022-02-20 22:05:36,245 INFO L78 Accepts]: Start accepts. Automaton has 1610 states and 2058 transitions. Word has length 75 [2022-02-20 22:05:36,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-02-20 22:05:36,245 INFO L470 AbstractCegarLoop]: Abstraction has 1610 states and 2058 transitions. [2022-02-20 22:05:36,245 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 9.6) internal successors, (48), 3 states have internal predecessors, (48), 3 states have call successors, (10), 3 states have call predecessors, (10), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2022-02-20 22:05:36,245 INFO L276 IsEmpty]: Start isEmpty. Operand 1610 states and 2058 transitions. [2022-02-20 22:05:36,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2022-02-20 22:05:36,247 INFO L506 BasicCegarLoop]: Found error trace [2022-02-20 22:05:36,248 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-20 22:05:36,248 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2022-02-20 22:05:36,248 INFO L402 AbstractCegarLoop]: === Iteration 12 === Targeting ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-02-20 22:05:36,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-20 22:05:36,248 INFO L85 PathProgramCache]: Analyzing trace with hash 1055310527, now seen corresponding path program 1 times [2022-02-20 22:05:36,249 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-20 22:05:36,249 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391803846] [2022-02-20 22:05:36,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:36,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-20 22:05:36,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,326 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 2 [2022-02-20 22:05:36,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,332 INFO L290 TraceCheckUtils]: 0: Hoare triple {66937#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {66890#true} is VALID [2022-02-20 22:05:36,332 INFO L290 TraceCheckUtils]: 1: Hoare triple {66890#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:36,332 INFO L290 TraceCheckUtils]: 2: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,333 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {66890#true} {66892#(= ~ldv_irq_1_1~0 0)} #979#return; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,343 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 16 [2022-02-20 22:05:36,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,364 INFO L290 TraceCheckUtils]: 0: Hoare triple {66938#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {66890#true} is VALID [2022-02-20 22:05:36,364 INFO L290 TraceCheckUtils]: 1: Hoare triple {66890#true} assume !(0 != ~state#1); {66939#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:36,365 INFO L290 TraceCheckUtils]: 2: Hoare triple {66939#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {66940#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:36,365 INFO L290 TraceCheckUtils]: 3: Hoare triple {66940#(= |ldv_irq_1_#res#1| 0)} assume true; {66940#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:36,366 INFO L284 TraceCheckUtils]: 4: Hoare quadruple {66940#(= |ldv_irq_1_#res#1| 0)} {66892#(= ~ldv_irq_1_1~0 0)} #983#return; {66902#(= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} is VALID [2022-02-20 22:05:36,366 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 28 [2022-02-20 22:05:36,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,418 INFO L290 TraceCheckUtils]: 0: Hoare triple {66938#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {66941#(= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|)} is VALID [2022-02-20 22:05:36,418 INFO L290 TraceCheckUtils]: 1: Hoare triple {66941#(= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,419 INFO L290 TraceCheckUtils]: 2: Hoare triple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} assume #t~switch220#1; {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,419 INFO L290 TraceCheckUtils]: 3: Hoare triple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} assume !(1 == ~state#1); {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,420 INFO L290 TraceCheckUtils]: 4: Hoare triple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} #res#1 := ~state#1; {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,420 INFO L290 TraceCheckUtils]: 5: Hoare triple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} assume true; {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,421 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} {66903#(= ~ldv_irq_1_0~0 0)} #981#return; {66891#false} is VALID [2022-02-20 22:05:36,431 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 47 [2022-02-20 22:05:36,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,437 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:36,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,441 INFO L290 TraceCheckUtils]: 0: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66890#true} is VALID [2022-02-20 22:05:36,442 INFO L290 TraceCheckUtils]: 1: Hoare triple {66890#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:36,442 INFO L290 TraceCheckUtils]: 2: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,442 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {66890#true} {66890#true} #893#return; {66890#true} is VALID [2022-02-20 22:05:36,442 INFO L290 TraceCheckUtils]: 0: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {66890#true} is VALID [2022-02-20 22:05:36,443 INFO L272 TraceCheckUtils]: 1: Hoare triple {66890#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,443 INFO L290 TraceCheckUtils]: 2: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66890#true} is VALID [2022-02-20 22:05:36,443 INFO L290 TraceCheckUtils]: 3: Hoare triple {66890#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:36,443 INFO L290 TraceCheckUtils]: 4: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,443 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {66890#true} {66890#true} #893#return; {66890#true} is VALID [2022-02-20 22:05:36,443 INFO L290 TraceCheckUtils]: 6: Hoare triple {66890#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {66890#true} is VALID [2022-02-20 22:05:36,443 INFO L290 TraceCheckUtils]: 7: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,444 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {66890#true} {66891#false} #915#return; {66891#false} is VALID [2022-02-20 22:05:36,444 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 59 [2022-02-20 22:05:36,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,451 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:36,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,456 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 1 [2022-02-20 22:05:36,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,460 INFO L290 TraceCheckUtils]: 0: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66890#true} is VALID [2022-02-20 22:05:36,461 INFO L290 TraceCheckUtils]: 1: Hoare triple {66890#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:36,461 INFO L290 TraceCheckUtils]: 2: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,461 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {66890#true} {66890#true} #893#return; {66890#true} is VALID [2022-02-20 22:05:36,461 INFO L290 TraceCheckUtils]: 0: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {66890#true} is VALID [2022-02-20 22:05:36,462 INFO L272 TraceCheckUtils]: 1: Hoare triple {66890#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,462 INFO L290 TraceCheckUtils]: 2: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66890#true} is VALID [2022-02-20 22:05:36,462 INFO L290 TraceCheckUtils]: 3: Hoare triple {66890#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:36,462 INFO L290 TraceCheckUtils]: 4: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,462 INFO L284 TraceCheckUtils]: 5: Hoare quadruple {66890#true} {66890#true} #893#return; {66890#true} is VALID [2022-02-20 22:05:36,462 INFO L290 TraceCheckUtils]: 6: Hoare triple {66890#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {66890#true} is VALID [2022-02-20 22:05:36,463 INFO L290 TraceCheckUtils]: 7: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,463 INFO L284 TraceCheckUtils]: 8: Hoare quadruple {66890#true} {66890#true} #927#return; {66890#true} is VALID [2022-02-20 22:05:36,463 INFO L290 TraceCheckUtils]: 0: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {66890#true} is VALID [2022-02-20 22:05:36,464 INFO L272 TraceCheckUtils]: 1: Hoare triple {66890#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,464 INFO L290 TraceCheckUtils]: 2: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {66890#true} is VALID [2022-02-20 22:05:36,464 INFO L272 TraceCheckUtils]: 3: Hoare triple {66890#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,464 INFO L290 TraceCheckUtils]: 4: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66890#true} is VALID [2022-02-20 22:05:36,465 INFO L290 TraceCheckUtils]: 5: Hoare triple {66890#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:36,465 INFO L290 TraceCheckUtils]: 6: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,465 INFO L284 TraceCheckUtils]: 7: Hoare quadruple {66890#true} {66890#true} #893#return; {66890#true} is VALID [2022-02-20 22:05:36,465 INFO L290 TraceCheckUtils]: 8: Hoare triple {66890#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {66890#true} is VALID [2022-02-20 22:05:36,465 INFO L290 TraceCheckUtils]: 9: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,465 INFO L284 TraceCheckUtils]: 10: Hoare quadruple {66890#true} {66890#true} #927#return; {66890#true} is VALID [2022-02-20 22:05:36,465 INFO L290 TraceCheckUtils]: 11: Hoare triple {66890#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {66890#true} is VALID [2022-02-20 22:05:36,466 INFO L290 TraceCheckUtils]: 12: Hoare triple {66890#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {66890#true} is VALID [2022-02-20 22:05:36,466 INFO L290 TraceCheckUtils]: 13: Hoare triple {66890#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {66890#true} is VALID [2022-02-20 22:05:36,466 INFO L290 TraceCheckUtils]: 14: Hoare triple {66890#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {66890#true} is VALID [2022-02-20 22:05:36,466 INFO L290 TraceCheckUtils]: 15: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,466 INFO L284 TraceCheckUtils]: 16: Hoare quadruple {66890#true} {66891#false} #917#return; {66891#false} is VALID [2022-02-20 22:05:36,467 INFO L290 TraceCheckUtils]: 0: Hoare triple {66890#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,467 INFO L290 TraceCheckUtils]: 1: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,468 INFO L272 TraceCheckUtils]: 2: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {66937#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,468 INFO L290 TraceCheckUtils]: 3: Hoare triple {66937#(and (= |old(#length)| |#length|) (= |#memory_int| |old(#memory_int)|) (= |old(#valid)| |#valid|))} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {66890#true} is VALID [2022-02-20 22:05:36,468 INFO L290 TraceCheckUtils]: 4: Hoare triple {66890#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:36,468 INFO L290 TraceCheckUtils]: 5: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,469 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {66890#true} {66892#(= ~ldv_irq_1_1~0 0)} #979#return; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,469 INFO L290 TraceCheckUtils]: 7: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,469 INFO L290 TraceCheckUtils]: 8: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,470 INFO L290 TraceCheckUtils]: 9: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,470 INFO L290 TraceCheckUtils]: 10: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,471 INFO L290 TraceCheckUtils]: 11: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,471 INFO L290 TraceCheckUtils]: 12: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} assume main_#t~switch236#1; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,471 INFO L290 TraceCheckUtils]: 13: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,472 INFO L290 TraceCheckUtils]: 14: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,472 INFO L290 TraceCheckUtils]: 15: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} assume choose_interrupt_1_#t~switch223#1; {66892#(= ~ldv_irq_1_1~0 0)} is VALID [2022-02-20 22:05:36,473 INFO L272 TraceCheckUtils]: 16: Hoare triple {66892#(= ~ldv_irq_1_1~0 0)} call choose_interrupt_1_#t~ret225#1 := ldv_irq_1(~ldv_irq_1_1~0, ~ldv_irq_line_1_1~0, ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset); {66938#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} is VALID [2022-02-20 22:05:36,473 INFO L290 TraceCheckUtils]: 17: Hoare triple {66938#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {66890#true} is VALID [2022-02-20 22:05:36,474 INFO L290 TraceCheckUtils]: 18: Hoare triple {66890#true} assume !(0 != ~state#1); {66939#(= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:36,474 INFO L290 TraceCheckUtils]: 19: Hoare triple {66939#(= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {66940#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:36,474 INFO L290 TraceCheckUtils]: 20: Hoare triple {66940#(= |ldv_irq_1_#res#1| 0)} assume true; {66940#(= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:36,475 INFO L284 TraceCheckUtils]: 21: Hoare quadruple {66940#(= |ldv_irq_1_#res#1| 0)} {66892#(= ~ldv_irq_1_1~0 0)} #983#return; {66902#(= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} is VALID [2022-02-20 22:05:36,476 INFO L290 TraceCheckUtils]: 22: Hoare triple {66902#(= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret225#1 && choose_interrupt_1_#t~ret225#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret225#1;havoc choose_interrupt_1_#t~ret225#1; {66903#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:36,476 INFO L290 TraceCheckUtils]: 23: Hoare triple {66903#(= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {66903#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:36,476 INFO L290 TraceCheckUtils]: 24: Hoare triple {66903#(= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {66903#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:36,477 INFO L290 TraceCheckUtils]: 25: Hoare triple {66903#(= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {66903#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:36,477 INFO L290 TraceCheckUtils]: 26: Hoare triple {66903#(= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {66903#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:36,477 INFO L290 TraceCheckUtils]: 27: Hoare triple {66903#(= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {66903#(= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:36,478 INFO L272 TraceCheckUtils]: 28: Hoare triple {66903#(= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {66938#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} is VALID [2022-02-20 22:05:36,479 INFO L290 TraceCheckUtils]: 29: Hoare triple {66938#(and (= |old(#length)| |#length|) (= |old(abs_2047)| abs_2047) (= |old(abs_2051)| abs_2051) (= |old(#valid)| |#valid|) (= |old(~LDV_IN_INTERRUPT~0)| ~LDV_IN_INTERRUPT~0))} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {66941#(= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|)} is VALID [2022-02-20 22:05:36,479 INFO L290 TraceCheckUtils]: 30: Hoare triple {66941#(= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,480 INFO L290 TraceCheckUtils]: 31: Hoare triple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} assume #t~switch220#1; {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,480 INFO L290 TraceCheckUtils]: 32: Hoare triple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} assume !(1 == ~state#1); {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,480 INFO L290 TraceCheckUtils]: 33: Hoare triple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} #res#1 := ~state#1; {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,481 INFO L290 TraceCheckUtils]: 34: Hoare triple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} assume true; {66942#(not (= |ldv_irq_1_#in~state#1| 0))} is VALID [2022-02-20 22:05:36,482 INFO L284 TraceCheckUtils]: 35: Hoare quadruple {66942#(not (= |ldv_irq_1_#in~state#1| 0))} {66903#(= ~ldv_irq_1_0~0 0)} #981#return; {66891#false} is VALID [2022-02-20 22:05:36,482 INFO L290 TraceCheckUtils]: 36: Hoare triple {66891#false} assume -2147483648 <= choose_interrupt_1_#t~ret224#1 && choose_interrupt_1_#t~ret224#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret224#1;havoc choose_interrupt_1_#t~ret224#1; {66891#false} is VALID [2022-02-20 22:05:36,482 INFO L290 TraceCheckUtils]: 37: Hoare triple {66891#false} assume { :end_inline_choose_interrupt_1 } true; {66891#false} is VALID [2022-02-20 22:05:36,482 INFO L290 TraceCheckUtils]: 38: Hoare triple {66891#false} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {66891#false} is VALID [2022-02-20 22:05:36,482 INFO L290 TraceCheckUtils]: 39: Hoare triple {66891#false} assume main_#t~switch236#1; {66891#false} is VALID [2022-02-20 22:05:36,482 INFO L290 TraceCheckUtils]: 40: Hoare triple {66891#false} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {66891#false} is VALID [2022-02-20 22:05:36,482 INFO L290 TraceCheckUtils]: 41: Hoare triple {66891#false} assume choose_interrupt_1_#t~switch223#1; {66891#false} is VALID [2022-02-20 22:05:36,483 INFO L272 TraceCheckUtils]: 42: Hoare triple {66891#false} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {66891#false} is VALID [2022-02-20 22:05:36,483 INFO L290 TraceCheckUtils]: 43: Hoare triple {66891#false} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {66891#false} is VALID [2022-02-20 22:05:36,483 INFO L290 TraceCheckUtils]: 44: Hoare triple {66891#false} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {66891#false} is VALID [2022-02-20 22:05:36,483 INFO L290 TraceCheckUtils]: 45: Hoare triple {66891#false} assume #t~switch220#1; {66891#false} is VALID [2022-02-20 22:05:36,483 INFO L290 TraceCheckUtils]: 46: Hoare triple {66891#false} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {66891#false} is VALID [2022-02-20 22:05:36,483 INFO L272 TraceCheckUtils]: 47: Hoare triple {66891#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,483 INFO L290 TraceCheckUtils]: 48: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {66890#true} is VALID [2022-02-20 22:05:36,484 INFO L272 TraceCheckUtils]: 49: Hoare triple {66890#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,484 INFO L290 TraceCheckUtils]: 50: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66890#true} is VALID [2022-02-20 22:05:36,484 INFO L290 TraceCheckUtils]: 51: Hoare triple {66890#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:36,484 INFO L290 TraceCheckUtils]: 52: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,485 INFO L284 TraceCheckUtils]: 53: Hoare quadruple {66890#true} {66890#true} #893#return; {66890#true} is VALID [2022-02-20 22:05:36,485 INFO L290 TraceCheckUtils]: 54: Hoare triple {66890#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {66890#true} is VALID [2022-02-20 22:05:36,485 INFO L290 TraceCheckUtils]: 55: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,485 INFO L284 TraceCheckUtils]: 56: Hoare quadruple {66890#true} {66891#false} #915#return; {66891#false} is VALID [2022-02-20 22:05:36,485 INFO L290 TraceCheckUtils]: 57: Hoare triple {66891#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {66891#false} is VALID [2022-02-20 22:05:36,485 INFO L290 TraceCheckUtils]: 58: Hoare triple {66891#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {66891#false} is VALID [2022-02-20 22:05:36,485 INFO L272 TraceCheckUtils]: 59: Hoare triple {66891#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,485 INFO L290 TraceCheckUtils]: 60: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {66890#true} is VALID [2022-02-20 22:05:36,486 INFO L272 TraceCheckUtils]: 61: Hoare triple {66890#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,486 INFO L290 TraceCheckUtils]: 62: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {66890#true} is VALID [2022-02-20 22:05:36,487 INFO L272 TraceCheckUtils]: 63: Hoare triple {66890#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} is VALID [2022-02-20 22:05:36,487 INFO L290 TraceCheckUtils]: 64: Hoare triple {66943#(and (= |old(#length)| |#length|) (= |old(#valid)| |#valid|))} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66890#true} is VALID [2022-02-20 22:05:36,487 INFO L290 TraceCheckUtils]: 65: Hoare triple {66890#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:36,487 INFO L290 TraceCheckUtils]: 66: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,487 INFO L284 TraceCheckUtils]: 67: Hoare quadruple {66890#true} {66890#true} #893#return; {66890#true} is VALID [2022-02-20 22:05:36,488 INFO L290 TraceCheckUtils]: 68: Hoare triple {66890#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {66890#true} is VALID [2022-02-20 22:05:36,488 INFO L290 TraceCheckUtils]: 69: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,488 INFO L284 TraceCheckUtils]: 70: Hoare quadruple {66890#true} {66890#true} #927#return; {66890#true} is VALID [2022-02-20 22:05:36,488 INFO L290 TraceCheckUtils]: 71: Hoare triple {66890#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {66890#true} is VALID [2022-02-20 22:05:36,488 INFO L290 TraceCheckUtils]: 72: Hoare triple {66890#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {66890#true} is VALID [2022-02-20 22:05:36,488 INFO L290 TraceCheckUtils]: 73: Hoare triple {66890#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {66890#true} is VALID [2022-02-20 22:05:36,488 INFO L290 TraceCheckUtils]: 74: Hoare triple {66890#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {66890#true} is VALID [2022-02-20 22:05:36,488 INFO L290 TraceCheckUtils]: 75: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:36,489 INFO L284 TraceCheckUtils]: 76: Hoare quadruple {66890#true} {66891#false} #917#return; {66891#false} is VALID [2022-02-20 22:05:36,489 INFO L290 TraceCheckUtils]: 77: Hoare triple {66891#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {66891#false} is VALID [2022-02-20 22:05:36,489 INFO L272 TraceCheckUtils]: 78: Hoare triple {66891#false} call ldv_spin_lock_check(); {66891#false} is VALID [2022-02-20 22:05:36,489 INFO L290 TraceCheckUtils]: 79: Hoare triple {66891#false} assume !(1 == ~ldv_init~0); {66891#false} is VALID [2022-02-20 22:05:36,489 INFO L272 TraceCheckUtils]: 80: Hoare triple {66891#false} call ldv_error(); {66891#false} is VALID [2022-02-20 22:05:36,489 INFO L290 TraceCheckUtils]: 81: Hoare triple {66891#false} assume !false; {66891#false} is VALID [2022-02-20 22:05:36,490 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 17 proven. 7 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2022-02-20 22:05:36,490 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-20 22:05:36,490 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [391803846] [2022-02-20 22:05:36,490 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [391803846] provided 0 perfect and 1 imperfect interpolant sequences [2022-02-20 22:05:36,490 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [931477054] [2022-02-20 22:05:36,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-20 22:05:36,491 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-02-20 22:05:36,491 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-20 22:05:36,492 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-02-20 22:05:36,519 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-02-20 22:05:36,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,690 INFO L263 TraceCheckSpWp]: Trace formula consists of 690 conjuncts, 12 conjunts are in the unsatisfiable core [2022-02-20 22:05:36,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-20 22:05:36,727 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-02-20 22:05:37,115 INFO L290 TraceCheckUtils]: 0: Hoare triple {66890#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {66890#true} is VALID [2022-02-20 22:05:37,115 INFO L290 TraceCheckUtils]: 1: Hoare triple {66890#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {66890#true} is VALID [2022-02-20 22:05:37,115 INFO L272 TraceCheckUtils]: 2: Hoare triple {66890#true} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {66890#true} is VALID [2022-02-20 22:05:37,115 INFO L290 TraceCheckUtils]: 3: Hoare triple {66890#true} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {66890#true} is VALID [2022-02-20 22:05:37,115 INFO L290 TraceCheckUtils]: 4: Hoare triple {66890#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:37,115 INFO L290 TraceCheckUtils]: 5: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {66890#true} {66890#true} #979#return; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 7: Hoare triple {66890#true} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 8: Hoare triple {66890#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 9: Hoare triple {66890#true} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 10: Hoare triple {66890#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 11: Hoare triple {66890#true} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 12: Hoare triple {66890#true} assume main_#t~switch236#1; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 13: Hoare triple {66890#true} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 14: Hoare triple {66890#true} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 15: Hoare triple {66890#true} assume choose_interrupt_1_#t~switch223#1; {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L272 TraceCheckUtils]: 16: Hoare triple {66890#true} call choose_interrupt_1_#t~ret225#1 := ldv_irq_1(~ldv_irq_1_1~0, ~ldv_irq_line_1_1~0, ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset); {66890#true} is VALID [2022-02-20 22:05:37,116 INFO L290 TraceCheckUtils]: 17: Hoare triple {66890#true} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {66890#true} is VALID [2022-02-20 22:05:37,117 INFO L290 TraceCheckUtils]: 18: Hoare triple {66890#true} assume !(0 != ~state#1); {67018#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:37,123 INFO L290 TraceCheckUtils]: 19: Hoare triple {67018#(<= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {67022#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:37,124 INFO L290 TraceCheckUtils]: 20: Hoare triple {67022#(<= |ldv_irq_1_#res#1| 0)} assume true; {67022#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:37,125 INFO L284 TraceCheckUtils]: 21: Hoare quadruple {67022#(<= |ldv_irq_1_#res#1| 0)} {66890#true} #983#return; {67029#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} is VALID [2022-02-20 22:05:37,125 INFO L290 TraceCheckUtils]: 22: Hoare triple {67029#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret225#1 && choose_interrupt_1_#t~ret225#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret225#1;havoc choose_interrupt_1_#t~ret225#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,126 INFO L290 TraceCheckUtils]: 23: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,126 INFO L290 TraceCheckUtils]: 24: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,127 INFO L290 TraceCheckUtils]: 25: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,127 INFO L290 TraceCheckUtils]: 26: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,127 INFO L290 TraceCheckUtils]: 27: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,128 INFO L272 TraceCheckUtils]: 28: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,129 INFO L290 TraceCheckUtils]: 29: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {67055#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|))} is VALID [2022-02-20 22:05:37,129 INFO L290 TraceCheckUtils]: 30: Hoare triple {67055#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|))} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {67055#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|))} is VALID [2022-02-20 22:05:37,130 INFO L290 TraceCheckUtils]: 31: Hoare triple {67055#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|))} assume #t~switch220#1; {67055#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|))} is VALID [2022-02-20 22:05:37,130 INFO L290 TraceCheckUtils]: 32: Hoare triple {67055#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|))} assume !(1 == ~state#1); {67055#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|))} is VALID [2022-02-20 22:05:37,131 INFO L290 TraceCheckUtils]: 33: Hoare triple {67055#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_~state#1| |ldv_irq_1_#in~state#1|))} #res#1 := ~state#1; {67068#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_#res#1| |ldv_irq_1_#in~state#1|))} is VALID [2022-02-20 22:05:37,131 INFO L290 TraceCheckUtils]: 34: Hoare triple {67068#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_#res#1| |ldv_irq_1_#in~state#1|))} assume true; {67068#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_#res#1| |ldv_irq_1_#in~state#1|))} is VALID [2022-02-20 22:05:37,132 INFO L284 TraceCheckUtils]: 35: Hoare quadruple {67068#(and (<= ~ldv_irq_1_0~0 0) (<= |ldv_irq_1_#res#1| |ldv_irq_1_#in~state#1|))} {67033#(<= ~ldv_irq_1_0~0 0)} #981#return; {67075#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret224#1| 0)} is VALID [2022-02-20 22:05:37,133 INFO L290 TraceCheckUtils]: 36: Hoare triple {67075#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret224#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret224#1 && choose_interrupt_1_#t~ret224#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret224#1;havoc choose_interrupt_1_#t~ret224#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,133 INFO L290 TraceCheckUtils]: 37: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,134 INFO L290 TraceCheckUtils]: 38: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,134 INFO L290 TraceCheckUtils]: 39: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,135 INFO L290 TraceCheckUtils]: 40: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,135 INFO L290 TraceCheckUtils]: 41: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,136 INFO L272 TraceCheckUtils]: 42: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {67097#(<= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:37,141 INFO L290 TraceCheckUtils]: 43: Hoare triple {67097#(<= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {67018#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:37,142 INFO L290 TraceCheckUtils]: 44: Hoare triple {67018#(<= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {67018#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:37,142 INFO L290 TraceCheckUtils]: 45: Hoare triple {67018#(<= |ldv_irq_1_~state#1| 0)} assume #t~switch220#1; {67018#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:37,143 INFO L290 TraceCheckUtils]: 46: Hoare triple {67018#(<= |ldv_irq_1_~state#1| 0)} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {66891#false} is VALID [2022-02-20 22:05:37,143 INFO L272 TraceCheckUtils]: 47: Hoare triple {66891#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {66891#false} is VALID [2022-02-20 22:05:37,143 INFO L290 TraceCheckUtils]: 48: Hoare triple {66891#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {66891#false} is VALID [2022-02-20 22:05:37,143 INFO L272 TraceCheckUtils]: 49: Hoare triple {66891#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {66891#false} is VALID [2022-02-20 22:05:37,143 INFO L290 TraceCheckUtils]: 50: Hoare triple {66891#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66891#false} is VALID [2022-02-20 22:05:37,144 INFO L290 TraceCheckUtils]: 51: Hoare triple {66891#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66891#false} is VALID [2022-02-20 22:05:37,144 INFO L290 TraceCheckUtils]: 52: Hoare triple {66891#false} assume true; {66891#false} is VALID [2022-02-20 22:05:37,144 INFO L284 TraceCheckUtils]: 53: Hoare quadruple {66891#false} {66891#false} #893#return; {66891#false} is VALID [2022-02-20 22:05:37,144 INFO L290 TraceCheckUtils]: 54: Hoare triple {66891#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {66891#false} is VALID [2022-02-20 22:05:37,144 INFO L290 TraceCheckUtils]: 55: Hoare triple {66891#false} assume true; {66891#false} is VALID [2022-02-20 22:05:37,144 INFO L284 TraceCheckUtils]: 56: Hoare quadruple {66891#false} {66891#false} #915#return; {66891#false} is VALID [2022-02-20 22:05:37,144 INFO L290 TraceCheckUtils]: 57: Hoare triple {66891#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {66891#false} is VALID [2022-02-20 22:05:37,145 INFO L290 TraceCheckUtils]: 58: Hoare triple {66891#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {66891#false} is VALID [2022-02-20 22:05:37,145 INFO L272 TraceCheckUtils]: 59: Hoare triple {66891#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {66891#false} is VALID [2022-02-20 22:05:37,145 INFO L290 TraceCheckUtils]: 60: Hoare triple {66891#false} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {66891#false} is VALID [2022-02-20 22:05:37,145 INFO L272 TraceCheckUtils]: 61: Hoare triple {66891#false} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {66891#false} is VALID [2022-02-20 22:05:37,145 INFO L290 TraceCheckUtils]: 62: Hoare triple {66891#false} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {66891#false} is VALID [2022-02-20 22:05:37,145 INFO L272 TraceCheckUtils]: 63: Hoare triple {66891#false} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {66891#false} is VALID [2022-02-20 22:05:37,145 INFO L290 TraceCheckUtils]: 64: Hoare triple {66891#false} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66891#false} is VALID [2022-02-20 22:05:37,146 INFO L290 TraceCheckUtils]: 65: Hoare triple {66891#false} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66891#false} is VALID [2022-02-20 22:05:37,146 INFO L290 TraceCheckUtils]: 66: Hoare triple {66891#false} assume true; {66891#false} is VALID [2022-02-20 22:05:37,146 INFO L284 TraceCheckUtils]: 67: Hoare quadruple {66891#false} {66891#false} #893#return; {66891#false} is VALID [2022-02-20 22:05:37,146 INFO L290 TraceCheckUtils]: 68: Hoare triple {66891#false} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {66891#false} is VALID [2022-02-20 22:05:37,146 INFO L290 TraceCheckUtils]: 69: Hoare triple {66891#false} assume true; {66891#false} is VALID [2022-02-20 22:05:37,146 INFO L284 TraceCheckUtils]: 70: Hoare quadruple {66891#false} {66891#false} #927#return; {66891#false} is VALID [2022-02-20 22:05:37,146 INFO L290 TraceCheckUtils]: 71: Hoare triple {66891#false} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {66891#false} is VALID [2022-02-20 22:05:37,147 INFO L290 TraceCheckUtils]: 72: Hoare triple {66891#false} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {66891#false} is VALID [2022-02-20 22:05:37,147 INFO L290 TraceCheckUtils]: 73: Hoare triple {66891#false} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {66891#false} is VALID [2022-02-20 22:05:37,147 INFO L290 TraceCheckUtils]: 74: Hoare triple {66891#false} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {66891#false} is VALID [2022-02-20 22:05:37,148 INFO L290 TraceCheckUtils]: 75: Hoare triple {66891#false} assume true; {66891#false} is VALID [2022-02-20 22:05:37,148 INFO L284 TraceCheckUtils]: 76: Hoare quadruple {66891#false} {66891#false} #917#return; {66891#false} is VALID [2022-02-20 22:05:37,148 INFO L290 TraceCheckUtils]: 77: Hoare triple {66891#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {66891#false} is VALID [2022-02-20 22:05:37,148 INFO L272 TraceCheckUtils]: 78: Hoare triple {66891#false} call ldv_spin_lock_check(); {66891#false} is VALID [2022-02-20 22:05:37,148 INFO L290 TraceCheckUtils]: 79: Hoare triple {66891#false} assume !(1 == ~ldv_init~0); {66891#false} is VALID [2022-02-20 22:05:37,148 INFO L272 TraceCheckUtils]: 80: Hoare triple {66891#false} call ldv_error(); {66891#false} is VALID [2022-02-20 22:05:37,148 INFO L290 TraceCheckUtils]: 81: Hoare triple {66891#false} assume !false; {66891#false} is VALID [2022-02-20 22:05:37,149 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 12 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2022-02-20 22:05:37,149 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-02-20 22:05:37,788 INFO L290 TraceCheckUtils]: 81: Hoare triple {66891#false} assume !false; {66891#false} is VALID [2022-02-20 22:05:37,788 INFO L272 TraceCheckUtils]: 80: Hoare triple {66891#false} call ldv_error(); {66891#false} is VALID [2022-02-20 22:05:37,788 INFO L290 TraceCheckUtils]: 79: Hoare triple {66891#false} assume !(1 == ~ldv_init~0); {66891#false} is VALID [2022-02-20 22:05:37,788 INFO L272 TraceCheckUtils]: 78: Hoare triple {66891#false} call ldv_spin_lock_check(); {66891#false} is VALID [2022-02-20 22:05:37,788 INFO L290 TraceCheckUtils]: 77: Hoare triple {66891#false} assume -2147483648 <= tegra_rtc_irq_handler_#t~ret131#1 && tegra_rtc_irq_handler_#t~ret131#1 <= 2147483647;havoc tegra_rtc_irq_handler_#t~ret131#1; {66891#false} is VALID [2022-02-20 22:05:37,789 INFO L284 TraceCheckUtils]: 76: Hoare quadruple {66890#true} {66891#false} #917#return; {66891#false} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 75: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 74: Hoare triple {66890#true} assume !(0 != ~tmp___1~0#1 % 4294967296);#res#1 := 0; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 73: Hoare triple {66890#true} #t~ret90#1 := tegra_rtc_check_busy_#res#1;assume { :end_inline_tegra_rtc_check_busy } true;~tmp___1~0#1 := #t~ret90#1;havoc #t~ret90#1; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 72: Hoare triple {66890#true} assume { :begin_inline_tegra_rtc_check_busy } true;tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset := ~info~0#1.base, ~info~0#1.offset;havoc tegra_rtc_check_busy_#res#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset, tegra_rtc_check_busy_#t~mem88#1, tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset, tegra_rtc_check_busy_~__v~0#1, tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_~info#1.base, tegra_rtc_check_busy_~info#1.offset := tegra_rtc_check_busy_#in~info#1.base, tegra_rtc_check_busy_#in~info#1.offset;havoc tegra_rtc_check_busy_~__v~0#1;havoc tegra_rtc_check_busy_~__v___0~0#1;call tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset := read~$Pointer$(tegra_rtc_check_busy_~info#1.base, 16 + tegra_rtc_check_busy_~info#1.offset, 8);call tegra_rtc_check_busy_#t~mem88#1 := read~int(tegra_rtc_check_busy_#t~mem87#1.base, 16 + tegra_rtc_check_busy_#t~mem87#1.offset, 4);tegra_rtc_check_busy_~__v___0~0#1 := tegra_rtc_check_busy_#t~mem88#1;havoc tegra_rtc_check_busy_#t~mem87#1.base, tegra_rtc_check_busy_#t~mem87#1.offset;havoc tegra_rtc_check_busy_#t~mem88#1;tegra_rtc_check_busy_~__v~0#1 := tegra_rtc_check_busy_~__v___0~0#1;tegra_rtc_check_busy_#res#1 := tegra_rtc_check_busy_~__v~0#1; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 71: Hoare triple {66890#true} ~tmp~9#1.base, ~tmp~9#1.offset := #t~ret89#1.base, #t~ret89#1.offset;havoc #t~ret89#1.base, #t~ret89#1.offset;~info~0#1.base, ~info~0#1.offset := ~tmp~9#1.base, ~tmp~9#1.offset;~retries~0#1 := 500; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L284 TraceCheckUtils]: 70: Hoare quadruple {66890#true} {66890#true} #927#return; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 69: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 68: Hoare triple {66890#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L284 TraceCheckUtils]: 67: Hoare quadruple {66890#true} {66890#true} #893#return; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 66: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 65: Hoare triple {66890#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 64: Hoare triple {66890#true} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L272 TraceCheckUtils]: 63: Hoare triple {66890#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 62: Hoare triple {66890#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L272 TraceCheckUtils]: 61: Hoare triple {66890#true} call #t~ret89#1.base, #t~ret89#1.offset := dev_get_drvdata(~dev#1.base, ~dev#1.offset); {66890#true} is VALID [2022-02-20 22:05:37,789 INFO L290 TraceCheckUtils]: 60: Hoare triple {66890#true} ~dev#1.base, ~dev#1.offset := #in~dev#1.base, #in~dev#1.offset;havoc ~info~0#1.base, ~info~0#1.offset;havoc ~tmp~9#1.base, ~tmp~9#1.offset;havoc ~retries~0#1;havoc ~tmp___0~2#1;havoc ~tmp___1~0#1; {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L272 TraceCheckUtils]: 59: Hoare triple {66891#false} call tegra_rtc_irq_handler_#t~ret131#1 := tegra_rtc_wait_while_busy(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L290 TraceCheckUtils]: 58: Hoare triple {66891#false} assume 0 != tegra_rtc_irq_handler_~status~1#1 % 4294967296; {66891#false} is VALID [2022-02-20 22:05:37,790 INFO L290 TraceCheckUtils]: 57: Hoare triple {66891#false} tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset := tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset;tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset := tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;tegra_rtc_irq_handler_~events~0#1 := 0;call tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset := read~$Pointer$(tegra_rtc_irq_handler_~info~6#1.base, 16 + tegra_rtc_irq_handler_~info~6#1.offset, 8);call tegra_rtc_irq_handler_#t~mem130#1 := read~int(tegra_rtc_irq_handler_#t~mem129#1.base, 176 + tegra_rtc_irq_handler_#t~mem129#1.offset, 4);tegra_rtc_irq_handler_~__v___0~4#1 := tegra_rtc_irq_handler_#t~mem130#1;havoc tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset;havoc tegra_rtc_irq_handler_#t~mem130#1;tegra_rtc_irq_handler_~__v~4#1 := tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~status~1#1 := tegra_rtc_irq_handler_~__v~4#1; {66891#false} is VALID [2022-02-20 22:05:37,790 INFO L284 TraceCheckUtils]: 56: Hoare quadruple {66890#true} {66891#false} #915#return; {66891#false} is VALID [2022-02-20 22:05:37,790 INFO L290 TraceCheckUtils]: 55: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L290 TraceCheckUtils]: 54: Hoare triple {66890#true} #res.base, #res.offset := #t~ret274.base, #t~ret274.offset;havoc #t~ret274.base, #t~ret274.offset; {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L284 TraceCheckUtils]: 53: Hoare quadruple {66890#true} {66890#true} #893#return; {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L290 TraceCheckUtils]: 52: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L290 TraceCheckUtils]: 51: Hoare triple {66890#true} assume 0 != ~tmp___0~0;#res.base, #res.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L290 TraceCheckUtils]: 50: Hoare triple {66890#true} ~size := #in~size;havoc ~p~0.base, ~p~0.offset;havoc ~tmp~0.base, ~tmp~0.offset;havoc ~tmp___0~0;assume -2147483648 <= #t~nondet11 && #t~nondet11 <= 2147483647;~tmp___0~0 := #t~nondet11;havoc #t~nondet11; {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L272 TraceCheckUtils]: 49: Hoare triple {66890#true} call #t~ret274.base, #t~ret274.offset := ldv_malloc(0); {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L290 TraceCheckUtils]: 48: Hoare triple {66890#true} ~arg0.base, ~arg0.offset := #in~arg0.base, #in~arg0.offset; {66890#true} is VALID [2022-02-20 22:05:37,790 INFO L272 TraceCheckUtils]: 47: Hoare triple {66891#false} call tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset := dev_get_drvdata(tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset); {66890#true} is VALID [2022-02-20 22:05:37,791 INFO L290 TraceCheckUtils]: 46: Hoare triple {67018#(<= |ldv_irq_1_~state#1| 0)} assume 1 == ~state#1;~LDV_IN_INTERRUPT~0 := 2;assume { :begin_inline_tegra_rtc_irq_handler } true;tegra_rtc_irq_handler_#in~irq#1, tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset := ~line#1, ~data#1.base, ~data#1.offset;havoc tegra_rtc_irq_handler_#res#1;havoc tegra_rtc_irq_handler_#t~ret128#1.base, tegra_rtc_irq_handler_#t~ret128#1.offset, tegra_rtc_irq_handler_#t~mem129#1.base, tegra_rtc_irq_handler_#t~mem129#1.offset, tegra_rtc_irq_handler_#t~mem130#1, tegra_rtc_irq_handler_#t~ret131#1, tegra_rtc_irq_handler_#t~nondet132#1, tegra_rtc_irq_handler_#t~nondet133#1, tegra_rtc_irq_handler_#t~mem134#1.base, tegra_rtc_irq_handler_#t~mem134#1.offset, tegra_rtc_irq_handler_~irq#1, tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset, tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset, tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset, tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset, tegra_rtc_irq_handler_~events~0#1, tegra_rtc_irq_handler_~status~1#1, tegra_rtc_irq_handler_~sl_irq_flags~2#1, tegra_rtc_irq_handler_~__v~4#1, tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~irq#1 := tegra_rtc_irq_handler_#in~irq#1;tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset := tegra_rtc_irq_handler_#in~data#1.base, tegra_rtc_irq_handler_#in~data#1.offset;havoc tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset;havoc tegra_rtc_irq_handler_~info~6#1.base, tegra_rtc_irq_handler_~info~6#1.offset;havoc tegra_rtc_irq_handler_~tmp~16#1.base, tegra_rtc_irq_handler_~tmp~16#1.offset;havoc tegra_rtc_irq_handler_~events~0#1;havoc tegra_rtc_irq_handler_~status~1#1;havoc tegra_rtc_irq_handler_~sl_irq_flags~2#1;havoc tegra_rtc_irq_handler_~__v~4#1;havoc tegra_rtc_irq_handler_~__v___0~4#1;tegra_rtc_irq_handler_~dev~0#1.base, tegra_rtc_irq_handler_~dev~0#1.offset := tegra_rtc_irq_handler_~data#1.base, tegra_rtc_irq_handler_~data#1.offset; {66891#false} is VALID [2022-02-20 22:05:37,791 INFO L290 TraceCheckUtils]: 45: Hoare triple {67018#(<= |ldv_irq_1_~state#1| 0)} assume #t~switch220#1; {67018#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:37,791 INFO L290 TraceCheckUtils]: 44: Hoare triple {67018#(<= |ldv_irq_1_~state#1| 0)} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {67018#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:37,792 INFO L290 TraceCheckUtils]: 43: Hoare triple {67097#(<= |ldv_irq_1_#in~state#1| 0)} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {67018#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:37,792 INFO L272 TraceCheckUtils]: 42: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {67097#(<= |ldv_irq_1_#in~state#1| 0)} is VALID [2022-02-20 22:05:37,793 INFO L290 TraceCheckUtils]: 41: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,793 INFO L290 TraceCheckUtils]: 40: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,793 INFO L290 TraceCheckUtils]: 39: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,794 INFO L290 TraceCheckUtils]: 38: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,794 INFO L290 TraceCheckUtils]: 37: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,794 INFO L290 TraceCheckUtils]: 36: Hoare triple {67075#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret224#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret224#1 && choose_interrupt_1_#t~ret224#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret224#1;havoc choose_interrupt_1_#t~ret224#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,795 INFO L284 TraceCheckUtils]: 35: Hoare quadruple {67356#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_#res#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} {67033#(<= ~ldv_irq_1_0~0 0)} #981#return; {67075#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret224#1| 0)} is VALID [2022-02-20 22:05:37,795 INFO L290 TraceCheckUtils]: 34: Hoare triple {67356#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_#res#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} assume true; {67356#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_#res#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} is VALID [2022-02-20 22:05:37,796 INFO L290 TraceCheckUtils]: 33: Hoare triple {67363#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_~state#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} #res#1 := ~state#1; {67356#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_#res#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} is VALID [2022-02-20 22:05:37,796 INFO L290 TraceCheckUtils]: 32: Hoare triple {67363#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_~state#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} assume !(1 == ~state#1); {67363#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_~state#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} is VALID [2022-02-20 22:05:37,797 INFO L290 TraceCheckUtils]: 31: Hoare triple {67363#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_~state#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} assume #t~switch220#1; {67363#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_~state#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} is VALID [2022-02-20 22:05:37,797 INFO L290 TraceCheckUtils]: 30: Hoare triple {67363#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_~state#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} assume 0 != ~state#1;assume -2147483648 <= #t~nondet219#1 && #t~nondet219#1 <= 2147483647;~tmp~22#1 := #t~nondet219#1;havoc #t~nondet219#1;#t~switch220#1 := 0 == ~tmp~22#1; {67363#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_~state#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} is VALID [2022-02-20 22:05:37,797 INFO L290 TraceCheckUtils]: 29: Hoare triple {66890#true} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {67363#(or (not (<= ~ldv_irq_1_0~0 0)) (<= |ldv_irq_1_~state#1| 0) (not (<= |ldv_irq_1_#in~state#1| ~ldv_irq_1_0~0)))} is VALID [2022-02-20 22:05:37,797 INFO L272 TraceCheckUtils]: 28: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} call choose_interrupt_1_#t~ret224#1 := ldv_irq_1(~ldv_irq_1_0~0, ~ldv_irq_line_1_0~0, ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset); {66890#true} is VALID [2022-02-20 22:05:37,798 INFO L290 TraceCheckUtils]: 27: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume choose_interrupt_1_#t~switch223#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,798 INFO L290 TraceCheckUtils]: 26: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,799 INFO L290 TraceCheckUtils]: 25: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume main_#t~switch236#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,799 INFO L290 TraceCheckUtils]: 24: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,799 INFO L290 TraceCheckUtils]: 23: Hoare triple {67033#(<= ~ldv_irq_1_0~0 0)} assume { :end_inline_choose_interrupt_1 } true; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,800 INFO L290 TraceCheckUtils]: 22: Hoare triple {67029#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} assume -2147483648 <= choose_interrupt_1_#t~ret225#1 && choose_interrupt_1_#t~ret225#1 <= 2147483647;~ldv_irq_1_0~0 := choose_interrupt_1_#t~ret225#1;havoc choose_interrupt_1_#t~ret225#1; {67033#(<= ~ldv_irq_1_0~0 0)} is VALID [2022-02-20 22:05:37,800 INFO L284 TraceCheckUtils]: 21: Hoare quadruple {67022#(<= |ldv_irq_1_#res#1| 0)} {66890#true} #983#return; {67029#(<= |ULTIMATE.start_choose_interrupt_1_#t~ret225#1| 0)} is VALID [2022-02-20 22:05:37,801 INFO L290 TraceCheckUtils]: 20: Hoare triple {67022#(<= |ldv_irq_1_#res#1| 0)} assume true; {67022#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:37,801 INFO L290 TraceCheckUtils]: 19: Hoare triple {67018#(<= |ldv_irq_1_~state#1| 0)} #res#1 := ~state#1; {67022#(<= |ldv_irq_1_#res#1| 0)} is VALID [2022-02-20 22:05:37,801 INFO L290 TraceCheckUtils]: 18: Hoare triple {66890#true} assume !(0 != ~state#1); {67018#(<= |ldv_irq_1_~state#1| 0)} is VALID [2022-02-20 22:05:37,801 INFO L290 TraceCheckUtils]: 17: Hoare triple {66890#true} ~state#1 := #in~state#1;~line#1 := #in~line#1;~data#1.base, ~data#1.offset := #in~data#1.base, #in~data#1.offset;havoc ~irq_retval~0#1;havoc ~tmp~22#1; {66890#true} is VALID [2022-02-20 22:05:37,801 INFO L272 TraceCheckUtils]: 16: Hoare triple {66890#true} call choose_interrupt_1_#t~ret225#1 := ldv_irq_1(~ldv_irq_1_1~0, ~ldv_irq_line_1_1~0, ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset); {66890#true} is VALID [2022-02-20 22:05:37,801 INFO L290 TraceCheckUtils]: 15: Hoare triple {66890#true} assume choose_interrupt_1_#t~switch223#1; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 14: Hoare triple {66890#true} assume !choose_interrupt_1_#t~switch223#1;choose_interrupt_1_#t~switch223#1 := choose_interrupt_1_#t~switch223#1 || 1 == choose_interrupt_1_~tmp~23#1; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 13: Hoare triple {66890#true} assume 0 != ~ldv_state_variable_1~0;assume { :begin_inline_choose_interrupt_1 } true;havoc choose_interrupt_1_#t~nondet222#1, choose_interrupt_1_#t~switch223#1, choose_interrupt_1_#t~ret224#1, choose_interrupt_1_#t~ret225#1, choose_interrupt_1_#t~ret226#1, choose_interrupt_1_#t~ret227#1, choose_interrupt_1_~tmp~23#1;havoc choose_interrupt_1_~tmp~23#1;assume -2147483648 <= choose_interrupt_1_#t~nondet222#1 && choose_interrupt_1_#t~nondet222#1 <= 2147483647;choose_interrupt_1_~tmp~23#1 := choose_interrupt_1_#t~nondet222#1;havoc choose_interrupt_1_#t~nondet222#1;choose_interrupt_1_#t~switch223#1 := 0 == choose_interrupt_1_~tmp~23#1; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 12: Hoare triple {66890#true} assume main_#t~switch236#1; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 11: Hoare triple {66890#true} assume -2147483648 <= main_#t~nondet235#1 && main_#t~nondet235#1 <= 2147483647;main_~tmp___1~5#1 := main_#t~nondet235#1;havoc main_#t~nondet235#1;main_#t~switch236#1 := 0 == main_~tmp___1~5#1; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 10: Hoare triple {66890#true} assume #Ultimate.C_memset_#res#1.base == #Ultimate.C_memset_#ptr#1.base && #Ultimate.C_memset_#res#1.offset == #Ultimate.C_memset_#ptr#1.offset;main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset := #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;assume { :end_inline_#Ultimate.C_memset } true;havoc main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 9: Hoare triple {66890#true} assume !(#Ultimate.C_memset_#t~loopctr293#1 % 18446744073709551616 < #Ultimate.C_memset_#amount#1 % 18446744073709551616); {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 8: Hoare triple {66890#true} assume { :end_inline_ldv_initialize } true;assume { :begin_inline_#Ultimate.C_memset } true;#Ultimate.C_memset_#ptr#1.base, #Ultimate.C_memset_#ptr#1.offset, #Ultimate.C_memset_#value#1, #Ultimate.C_memset_#amount#1 := main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, 0, 4;havoc #Ultimate.C_memset_#res#1.base, #Ultimate.C_memset_#res#1.offset;havoc #Ultimate.C_memset_#t~loopctr293#1;#Ultimate.C_memset_#t~loopctr293#1 := 0; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 7: Hoare triple {66890#true} main_~tmp~26#1.base, main_~tmp~26#1.offset := main_#t~ret232#1.base, main_#t~ret232#1.offset;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset;main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset := main_~tmp~26#1.base, main_~tmp~26#1.offset;main_~tmp___0~8#1 := main_#t~nondet233#1;havoc main_#t~nondet233#1;main_~ldvarg0~0#1 := main_~tmp___0~8#1;assume { :begin_inline_ldv_initialize } true; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L284 TraceCheckUtils]: 6: Hoare quadruple {66890#true} {66890#true} #979#return; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 5: Hoare triple {66890#true} assume true; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 4: Hoare triple {66890#true} assume 0 != ~tmp___0~1#1;#res#1.base, #res#1.offset := 0, 0; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L290 TraceCheckUtils]: 3: Hoare triple {66890#true} ~size#1 := #in~size#1;havoc ~p~1#1.base, ~p~1#1.offset;havoc ~tmp~1#1.base, ~tmp~1#1.offset;havoc ~tmp___0~1#1;assume -2147483648 <= #t~nondet14#1 && #t~nondet14#1 <= 2147483647;~tmp___0~1#1 := #t~nondet14#1;havoc #t~nondet14#1; {66890#true} is VALID [2022-02-20 22:05:37,802 INFO L272 TraceCheckUtils]: 2: Hoare triple {66890#true} call main_#t~ret232#1.base, main_#t~ret232#1.offset := ldv_zalloc(136); {66890#true} is VALID [2022-02-20 22:05:37,803 INFO L290 TraceCheckUtils]: 1: Hoare triple {66890#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret232#1.base, main_#t~ret232#1.offset, main_#t~nondet233#1, main_#t~memset~res234#1.base, main_#t~memset~res234#1.offset, main_#t~nondet235#1, main_#t~switch236#1, main_#t~nondet237#1, main_#t~switch238#1, main_#t~ret239#1, main_#t~nondet240#1, main_#t~switch241#1, main_#t~ret242#1, main_#t~ret243#1, main_#t~ret244#1, main_#t~ret245#1, main_#t~ret246#1, main_#t~ret247#1, main_#t~ret248#1, main_#t~ret249#1, main_#t~ret250#1, main_#t~ret251#1, main_#t~ret252#1, main_#t~ret253#1, main_#t~ret254#1, main_#t~nondet255#1, main_#t~switch256#1, main_#t~mem257#1, main_#t~ret258#1, main_#t~ret259#1, main_#t~ret260#1, main_#t~ret261#1, main_#t~ret262#1, main_#t~ret263#1, main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset, main_~tmp~26#1.base, main_~tmp~26#1.offset, main_~ldvarg0~0#1, main_~tmp___0~8#1, main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset, main_~tmp___1~5#1, main_~tmp___2~1#1, main_~tmp___3~1#1, main_~tmp___4~1#1;havoc main_~ldvarg1~0#1.base, main_~ldvarg1~0#1.offset;havoc main_~tmp~26#1.base, main_~tmp~26#1.offset;havoc main_~ldvarg0~0#1;havoc main_~tmp___0~8#1;call main_~#ldvarg2~0#1.base, main_~#ldvarg2~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~tmp___1~5#1;havoc main_~tmp___2~1#1;havoc main_~tmp___3~1#1;havoc main_~tmp___4~1#1; {66890#true} is VALID [2022-02-20 22:05:37,803 INFO L290 TraceCheckUtils]: 0: Hoare triple {66890#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(79, 2);call #Ultimate.allocInit(36, 3);call #Ultimate.allocInit(12, 4);call #Ultimate.allocInit(42, 5);call #Ultimate.allocInit(42, 6);call #Ultimate.allocInit(32, 7);call #Ultimate.allocInit(21, 8);call #Ultimate.allocInit(37, 9);call #Ultimate.allocInit(10, 10);call #Ultimate.allocInit(50, 11);call #Ultimate.allocInit(32, 12);call #Ultimate.allocInit(10, 13);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := 14, 0;call #Ultimate.allocInit(88, 14);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := 15, 0;call #Ultimate.allocInit(153, 15);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(13, 0, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8);~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0; {66890#true} is VALID [2022-02-20 22:05:37,803 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 15 proven. 3 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2022-02-20 22:05:37,803 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [931477054] provided 0 perfect and 2 imperfect interpolant sequences [2022-02-20 22:05:37,803 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-02-20 22:05:37,804 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 10, 10] total 22 [2022-02-20 22:05:37,804 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871901911] [2022-02-20 22:05:37,804 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-02-20 22:05:37,805 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 5.045454545454546) internal successors, (111), 15 states have internal predecessors, (111), 5 states have call successors, (23), 7 states have call predecessors, (23), 7 states have return successors, (15), 6 states have call predecessors, (15), 5 states have call successors, (15) Word has length 82 [2022-02-20 22:05:37,808 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-02-20 22:05:37,809 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 22 states, 22 states have (on average 5.045454545454546) internal successors, (111), 15 states have internal predecessors, (111), 5 states have call successors, (23), 7 states have call predecessors, (23), 7 states have return successors, (15), 6 states have call predecessors, (15), 5 states have call successors, (15) [2022-02-20 22:05:37,910 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 149 edges. 149 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-20 22:05:37,911 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 22 states [2022-02-20 22:05:37,911 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-20 22:05:37,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2022-02-20 22:05:37,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=406, Unknown=0, NotChecked=0, Total=462 [2022-02-20 22:05:37,912 INFO L87 Difference]: Start difference. First operand 1610 states and 2058 transitions. Second operand has 22 states, 22 states have (on average 5.045454545454546) internal successors, (111), 15 states have internal predecessors, (111), 5 states have call successors, (23), 7 states have call predecessors, (23), 7 states have return successors, (15), 6 states have call predecessors, (15), 5 states have call successors, (15)