./Ultimate.py --spec ../../sv-benchmarks/c/Systems_DeviceDriversLinux64_ReachSafety.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/config/KojakReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/config/svcomp-Reach-64bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/config/KojakReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/config/svcomp-Reach-64bit-Kojak_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 .......................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: IllegalArgumentException: Indexed Sort BitVec undefined --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-10-26 21:50:53,018 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-26 21:50:53,019 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-26 21:50:53,028 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-26 21:50:53,028 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-26 21:50:53,029 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-26 21:50:53,030 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-26 21:50:53,031 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-26 21:50:53,033 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-26 21:50:53,033 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-26 21:50:53,034 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-26 21:50:53,034 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-26 21:50:53,035 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-26 21:50:53,036 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-26 21:50:53,036 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-26 21:50:53,037 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-26 21:50:53,038 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-26 21:50:53,039 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-26 21:50:53,040 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-26 21:50:53,042 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-26 21:50:53,042 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-26 21:50:53,044 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-26 21:50:53,045 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-26 21:50:53,045 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-26 21:50:53,045 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-26 21:50:53,046 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-26 21:50:53,047 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-26 21:50:53,048 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-26 21:50:53,048 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-26 21:50:53,049 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-26 21:50:53,049 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-26 21:50:53,050 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-26 21:50:53,050 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-26 21:50:53,050 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-26 21:50:53,051 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-26 21:50:53,051 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-26 21:50:53,051 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/config/svcomp-Reach-64bit-Kojak_Default.epf [2018-10-26 21:50:53,062 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-26 21:50:53,062 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-26 21:50:53,062 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-26 21:50:53,062 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-10-26 21:50:53,063 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-26 21:50:53,063 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-26 21:50:53,063 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-26 21:50:53,063 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-26 21:50:53,063 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-26 21:50:53,064 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-26 21:50:53,064 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-26 21:50:53,064 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-26 21:50:53,064 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-26 21:50:53,064 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-26 21:50:53,065 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-10-26 21:50:53,066 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-10-26 21:50:53,066 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-26 21:50:53,066 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-26 21:50:53,066 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-26 21:50:53,066 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-26 21:50:53,066 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-26 21:50:53,066 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-26 21:50:53,067 INFO L133 SettingsManager]: * Trace refinement strategy=PENGUIN [2018-10-26 21:50:53,067 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-26 21:50:53,067 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-10-26 21:50:53,067 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-10-26 21:50:53,067 INFO L133 SettingsManager]: * To the following directory=dump/ Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 [2018-10-26 21:50:53,093 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-26 21:50:53,102 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-26 21:50:53,105 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-26 21:50:53,106 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-26 21:50:53,106 INFO L276 PluginConnector]: CDTParser initialized [2018-10-26 21:50:53,107 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 21:50:53,149 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data/cdb3431d0/f67d8ca9db5d4227b9a308d49a9c7f61/FLAG28df7f923 [2018-10-26 21:50:53,653 INFO L298 CDTParser]: Found 1 translation units. [2018-10-26 21:50:53,653 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 21:50:53,672 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data/cdb3431d0/f67d8ca9db5d4227b9a308d49a9c7f61/FLAG28df7f923 [2018-10-26 21:50:53,683 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data/cdb3431d0/f67d8ca9db5d4227b9a308d49a9c7f61 [2018-10-26 21:50:53,686 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-26 21:50:53,687 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-26 21:50:53,688 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-26 21:50:53,688 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-26 21:50:53,691 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-26 21:50:53,692 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 09:50:53" (1/1) ... [2018-10-26 21:50:53,694 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@25e9bda7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:53, skipping insertion in model container [2018-10-26 21:50:53,694 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 09:50:53" (1/1) ... [2018-10-26 21:50:53,703 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-26 21:50:53,760 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-26 21:50:54,499 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 21:50:54,530 INFO L189 MainTranslator]: Completed pre-run [2018-10-26 21:50:54,959 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 21:50:55,027 INFO L193 MainTranslator]: Completed translation [2018-10-26 21:50:55,028 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55 WrapperNode [2018-10-26 21:50:55,028 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-26 21:50:55,029 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-26 21:50:55,029 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-26 21:50:55,029 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-26 21:50:55,037 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... [2018-10-26 21:50:55,062 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... [2018-10-26 21:50:55,098 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-26 21:50:55,098 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-26 21:50:55,099 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-26 21:50:55,099 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-26 21:50:55,107 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... [2018-10-26 21:50:55,107 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... [2018-10-26 21:50:55,115 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... [2018-10-26 21:50:55,115 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... [2018-10-26 21:50:55,135 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... [2018-10-26 21:50:55,142 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... [2018-10-26 21:50:55,147 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... [2018-10-26 21:50:55,153 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-26 21:50:55,153 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-26 21:50:55,153 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-26 21:50:55,154 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-26 21:50:55,154 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:50:55" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-26 21:50:55,207 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-10-26 21:50:55,208 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-10-26 21:50:55,208 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-10-26 21:50:55,208 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-10-26 21:50:55,208 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-10-26 21:50:55,208 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-10-26 21:50:55,208 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-10-26 21:50:55,208 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-10-26 21:50:55,209 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-10-26 21:50:55,209 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-10-26 21:50:55,209 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-10-26 21:50:55,209 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-10-26 21:50:55,209 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-10-26 21:50:55,209 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-10-26 21:50:55,209 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-10-26 21:50:55,209 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-10-26 21:50:55,209 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-10-26 21:50:55,210 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-10-26 21:50:55,210 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-10-26 21:50:55,210 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-10-26 21:50:55,210 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-10-26 21:50:55,210 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-10-26 21:50:55,210 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-10-26 21:50:55,210 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-10-26 21:50:55,211 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-10-26 21:50:55,211 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-10-26 21:50:55,211 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-10-26 21:50:55,211 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-10-26 21:50:55,211 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-10-26 21:50:55,211 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-10-26 21:50:55,211 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-10-26 21:50:55,211 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-10-26 21:50:55,211 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-10-26 21:50:55,211 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-10-26 21:50:55,211 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-10-26 21:50:55,212 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-10-26 21:50:55,212 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-10-26 21:50:55,212 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-10-26 21:50:55,212 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-10-26 21:50:55,212 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-10-26 21:50:55,212 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-10-26 21:50:55,212 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-10-26 21:50:55,212 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-10-26 21:50:55,212 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-10-26 21:50:55,212 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-10-26 21:50:55,212 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-10-26 21:50:55,213 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-10-26 21:50:55,213 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-10-26 21:50:55,213 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-10-26 21:50:55,213 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-10-26 21:50:55,213 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-10-26 21:50:55,213 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-10-26 21:50:55,213 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-10-26 21:50:55,213 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-26 21:50:55,213 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-26 21:51:01,176 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-26 21:51:01,176 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 09:51:01 BoogieIcfgContainer [2018-10-26 21:51:01,176 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-26 21:51:01,177 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-10-26 21:51:01,177 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-10-26 21:51:01,186 INFO L276 PluginConnector]: CodeCheck initialized [2018-10-26 21:51:01,186 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 09:51:01" (1/1) ... [2018-10-26 21:51:01,196 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:51:01,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:01,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 222 states and 316 transitions. [2018-10-26 21:51:01,236 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 316 transitions. [2018-10-26 21:51:01,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-10-26 21:51:01,243 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:01,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:01,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:02,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:02,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 349 states to 226 states and 349 transitions. [2018-10-26 21:51:02,020 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 349 transitions. [2018-10-26 21:51:02,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-10-26 21:51:02,023 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:02,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:02,190 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:02,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:02,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 229 states and 382 transitions. [2018-10-26 21:51:02,714 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 382 transitions. [2018-10-26 21:51:02,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-10-26 21:51:02,717 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:02,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:02,822 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:03,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:03,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 233 states and 416 transitions. [2018-10-26 21:51:03,022 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 416 transitions. [2018-10-26 21:51:03,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-10-26 21:51:03,025 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:03,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:03,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:03,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:03,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 241 states and 459 transitions. [2018-10-26 21:51:03,621 INFO L276 IsEmpty]: Start isEmpty. Operand 241 states and 459 transitions. [2018-10-26 21:51:03,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-10-26 21:51:03,625 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:03,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:03,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:04,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:04,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 246 states and 496 transitions. [2018-10-26 21:51:04,123 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 496 transitions. [2018-10-26 21:51:04,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-10-26 21:51:04,125 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:04,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:04,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:04,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:04,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 252 states and 531 transitions. [2018-10-26 21:51:04,619 INFO L276 IsEmpty]: Start isEmpty. Operand 252 states and 531 transitions. [2018-10-26 21:51:04,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-10-26 21:51:04,620 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:04,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:04,655 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:51:04,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:04,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 255 states and 536 transitions. [2018-10-26 21:51:04,931 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 536 transitions. [2018-10-26 21:51:04,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-10-26 21:51:04,932 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:04,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:04,968 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:05,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:05,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 546 states to 257 states and 538 transitions. [2018-10-26 21:51:05,098 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 538 transitions. [2018-10-26 21:51:05,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-10-26 21:51:05,100 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:05,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:05,135 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:05,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:05,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 584 states to 262 states and 576 transitions. [2018-10-26 21:51:05,664 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 576 transitions. [2018-10-26 21:51:05,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-10-26 21:51:05,666 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:05,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:05,712 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:06,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:06,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 618 states to 265 states and 610 transitions. [2018-10-26 21:51:06,052 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 610 transitions. [2018-10-26 21:51:06,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-26 21:51:06,053 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:06,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:06,087 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:06,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:06,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 624 states to 268 states and 616 transitions. [2018-10-26 21:51:06,363 INFO L276 IsEmpty]: Start isEmpty. Operand 268 states and 616 transitions. [2018-10-26 21:51:06,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-26 21:51:06,364 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:06,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:06,398 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:06,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:06,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 270 states and 618 transitions. [2018-10-26 21:51:06,528 INFO L276 IsEmpty]: Start isEmpty. Operand 270 states and 618 transitions. [2018-10-26 21:51:06,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-26 21:51:06,529 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:06,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:06,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:07,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:07,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 671 states to 278 states and 659 transitions. [2018-10-26 21:51:07,667 INFO L276 IsEmpty]: Start isEmpty. Operand 278 states and 659 transitions. [2018-10-26 21:51:07,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-26 21:51:07,668 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:07,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:07,702 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:08,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:08,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 709 states to 283 states and 697 transitions. [2018-10-26 21:51:08,604 INFO L276 IsEmpty]: Start isEmpty. Operand 283 states and 697 transitions. [2018-10-26 21:51:08,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-26 21:51:08,605 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:08,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:08,636 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:09,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:09,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 743 states to 286 states and 731 transitions. [2018-10-26 21:51:09,655 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 731 transitions. [2018-10-26 21:51:09,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-10-26 21:51:09,656 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:09,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:09,685 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:10,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:10,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 749 states to 289 states and 737 transitions. [2018-10-26 21:51:10,092 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 737 transitions. [2018-10-26 21:51:10,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-10-26 21:51:10,093 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:10,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:10,121 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:10,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:10,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 751 states to 291 states and 739 transitions. [2018-10-26 21:51:10,229 INFO L276 IsEmpty]: Start isEmpty. Operand 291 states and 739 transitions. [2018-10-26 21:51:10,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-26 21:51:10,230 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:10,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:10,445 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:10,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:10,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 758 states to 294 states and 746 transitions. [2018-10-26 21:51:10,583 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 746 transitions. [2018-10-26 21:51:10,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-26 21:51:10,584 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:10,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:10,700 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:10,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:10,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 745 states to 293 states and 733 transitions. [2018-10-26 21:51:10,835 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states and 733 transitions. [2018-10-26 21:51:10,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-10-26 21:51:10,836 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:10,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:11,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:12,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:12,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 788 states to 300 states and 772 transitions. [2018-10-26 21:51:12,186 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 772 transitions. [2018-10-26 21:51:12,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-26 21:51:12,187 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:12,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:12,984 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:13,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:13,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 774 states to 299 states and 758 transitions. [2018-10-26 21:51:13,030 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 758 transitions. [2018-10-26 21:51:13,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-26 21:51:13,031 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:13,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:13,052 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:13,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:13,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 780 states to 302 states and 764 transitions. [2018-10-26 21:51:13,637 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 764 transitions. [2018-10-26 21:51:13,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-10-26 21:51:13,638 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:13,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:13,777 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:13,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:13,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 781 states to 303 states and 765 transitions. [2018-10-26 21:51:13,842 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 765 transitions. [2018-10-26 21:51:13,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-10-26 21:51:13,843 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:13,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:14,478 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:15,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:15,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 820 states to 309 states and 804 transitions. [2018-10-26 21:51:15,235 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 804 transitions. [2018-10-26 21:51:15,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-10-26 21:51:15,236 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:15,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:15,257 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:15,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:15,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 822 states to 311 states and 806 transitions. [2018-10-26 21:51:15,391 INFO L276 IsEmpty]: Start isEmpty. Operand 311 states and 806 transitions. [2018-10-26 21:51:15,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-10-26 21:51:15,392 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:15,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:15,412 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:51:15,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:15,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 825 states to 313 states and 809 transitions. [2018-10-26 21:51:15,666 INFO L276 IsEmpty]: Start isEmpty. Operand 313 states and 809 transitions. [2018-10-26 21:51:15,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-26 21:51:15,666 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:15,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:15,908 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:16,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:16,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 870 states to 318 states and 854 transitions. [2018-10-26 21:51:16,665 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 854 transitions. [2018-10-26 21:51:16,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-26 21:51:16,666 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:16,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:16,691 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:16,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:16,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 896 states to 320 states and 880 transitions. [2018-10-26 21:51:16,922 INFO L276 IsEmpty]: Start isEmpty. Operand 320 states and 880 transitions. [2018-10-26 21:51:16,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-26 21:51:16,923 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:16,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:16,948 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:51:17,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:17,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 898 states to 322 states and 882 transitions. [2018-10-26 21:51:17,098 INFO L276 IsEmpty]: Start isEmpty. Operand 322 states and 882 transitions. [2018-10-26 21:51:17,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-26 21:51:17,099 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:17,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:17,169 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:17,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:17,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 898 states to 323 states and 882 transitions. [2018-10-26 21:51:17,232 INFO L276 IsEmpty]: Start isEmpty. Operand 323 states and 882 transitions. [2018-10-26 21:51:17,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-26 21:51:17,233 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:17,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:17,432 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:17,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:17,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 896 states to 322 states and 880 transitions. [2018-10-26 21:51:17,490 INFO L276 IsEmpty]: Start isEmpty. Operand 322 states and 880 transitions. [2018-10-26 21:51:17,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-10-26 21:51:17,490 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:17,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:17,513 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:51:18,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:18,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 935 states to 328 states and 919 transitions. [2018-10-26 21:51:18,395 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 919 transitions. [2018-10-26 21:51:18,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-10-26 21:51:18,397 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:18,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:18,418 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:51:18,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:18,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 956 states to 330 states and 940 transitions. [2018-10-26 21:51:18,822 INFO L276 IsEmpty]: Start isEmpty. Operand 330 states and 940 transitions. [2018-10-26 21:51:18,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-26 21:51:18,823 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:18,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:18,846 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:20,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:20,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 339 states and 981 transitions. [2018-10-26 21:51:20,083 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 981 transitions. [2018-10-26 21:51:20,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-26 21:51:20,084 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:20,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:20,105 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:20,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:20,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1013 states to 344 states and 996 transitions. [2018-10-26 21:51:20,963 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 996 transitions. [2018-10-26 21:51:20,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-26 21:51:20,964 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:20,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:20,986 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-10-26 21:51:21,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:21,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1013 states to 345 states and 996 transitions. [2018-10-26 21:51:21,117 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 996 transitions. [2018-10-26 21:51:21,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-26 21:51:21,118 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:21,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:21,143 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:51:22,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:22,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1059 states to 352 states and 1042 transitions. [2018-10-26 21:51:22,473 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 1042 transitions. [2018-10-26 21:51:22,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-10-26 21:51:22,474 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:22,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:22,499 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:51:22,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:22,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1060 states to 353 states and 1043 transitions. [2018-10-26 21:51:22,818 INFO L276 IsEmpty]: Start isEmpty. Operand 353 states and 1043 transitions. [2018-10-26 21:51:22,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-10-26 21:51:22,819 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:22,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:22,843 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:23,666 WARN L179 SmtUtils]: Spent 203.00 ms on a formula simplification that was a NOOP. DAG size: 18 [2018-10-26 21:51:24,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:24,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1090 states to 358 states and 1073 transitions. [2018-10-26 21:51:24,595 INFO L276 IsEmpty]: Start isEmpty. Operand 358 states and 1073 transitions. [2018-10-26 21:51:24,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-10-26 21:51:24,595 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:24,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:24,618 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:24,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:24,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 361 states and 1077 transitions. [2018-10-26 21:51:24,655 INFO L276 IsEmpty]: Start isEmpty. Operand 361 states and 1077 transitions. [2018-10-26 21:51:24,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-10-26 21:51:24,656 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:24,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:24,679 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:25,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:25,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1102 states to 364 states and 1085 transitions. [2018-10-26 21:51:25,366 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 1085 transitions. [2018-10-26 21:51:25,367 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-10-26 21:51:25,367 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:25,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:25,389 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:25,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:25,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1124 states to 366 states and 1107 transitions. [2018-10-26 21:51:25,822 INFO L276 IsEmpty]: Start isEmpty. Operand 366 states and 1107 transitions. [2018-10-26 21:51:25,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-10-26 21:51:25,823 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:25,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:25,845 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:26,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:26,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1152 states to 369 states and 1135 transitions. [2018-10-26 21:51:26,405 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 1135 transitions. [2018-10-26 21:51:26,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-10-26 21:51:26,406 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:26,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:26,428 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:27,397 WARN L179 SmtUtils]: Spent 260.00 ms on a formula simplification that was a NOOP. DAG size: 23 [2018-10-26 21:51:27,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:27,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1179 states to 372 states and 1162 transitions. [2018-10-26 21:51:27,927 INFO L276 IsEmpty]: Start isEmpty. Operand 372 states and 1162 transitions. [2018-10-26 21:51:27,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-10-26 21:51:27,928 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:27,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:28,229 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:51:29,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:29,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1227 states to 379 states and 1204 transitions. [2018-10-26 21:51:29,365 INFO L276 IsEmpty]: Start isEmpty. Operand 379 states and 1204 transitions. [2018-10-26 21:51:29,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-10-26 21:51:29,366 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:29,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:29,388 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:29,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:29,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1230 states to 381 states and 1207 transitions. [2018-10-26 21:51:29,487 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 1207 transitions. [2018-10-26 21:51:29,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-10-26 21:51:29,488 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:29,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:29,515 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:51:29,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:29,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1263 states to 384 states and 1240 transitions. [2018-10-26 21:51:29,988 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 1240 transitions. [2018-10-26 21:51:29,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-10-26 21:51:29,989 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:29,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:30,012 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:51:30,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:30,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1270 states to 387 states and 1247 transitions. [2018-10-26 21:51:30,368 INFO L276 IsEmpty]: Start isEmpty. Operand 387 states and 1247 transitions. [2018-10-26 21:51:30,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:51:30,369 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:30,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:30,513 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:30,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:30,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1307 states to 391 states and 1284 transitions. [2018-10-26 21:51:30,753 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 1284 transitions. [2018-10-26 21:51:30,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:51:30,753 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:30,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:30,801 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:51:31,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:31,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1308 states to 392 states and 1285 transitions. [2018-10-26 21:51:31,029 INFO L276 IsEmpty]: Start isEmpty. Operand 392 states and 1285 transitions. [2018-10-26 21:51:31,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:51:31,029 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:31,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:31,281 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:51:32,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:32,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1330 states to 395 states and 1307 transitions. [2018-10-26 21:51:32,178 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 1307 transitions. [2018-10-26 21:51:32,179 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-10-26 21:51:32,179 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:32,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:32,201 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:32,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:32,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1332 states to 397 states and 1309 transitions. [2018-10-26 21:51:32,256 INFO L276 IsEmpty]: Start isEmpty. Operand 397 states and 1309 transitions. [2018-10-26 21:51:32,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-10-26 21:51:32,257 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:32,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:32,275 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:32,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:32,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1342 states to 400 states and 1318 transitions. [2018-10-26 21:51:32,920 INFO L276 IsEmpty]: Start isEmpty. Operand 400 states and 1318 transitions. [2018-10-26 21:51:32,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-10-26 21:51:32,921 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:32,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:32,940 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:33,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:33,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1351 states to 403 states and 1326 transitions. [2018-10-26 21:51:33,606 INFO L276 IsEmpty]: Start isEmpty. Operand 403 states and 1326 transitions. [2018-10-26 21:51:33,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-10-26 21:51:33,607 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:33,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:33,627 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:51:34,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:34,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1360 states to 409 states and 1335 transitions. [2018-10-26 21:51:34,032 INFO L276 IsEmpty]: Start isEmpty. Operand 409 states and 1335 transitions. [2018-10-26 21:51:34,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-10-26 21:51:34,033 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:34,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:34,052 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 5 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:34,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:34,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1367 states to 412 states and 1342 transitions. [2018-10-26 21:51:34,601 INFO L276 IsEmpty]: Start isEmpty. Operand 412 states and 1342 transitions. [2018-10-26 21:51:34,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-10-26 21:51:34,601 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:34,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:34,614 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:35,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:35,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1380 states to 415 states and 1354 transitions. [2018-10-26 21:51:35,464 INFO L276 IsEmpty]: Start isEmpty. Operand 415 states and 1354 transitions. [2018-10-26 21:51:35,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-10-26 21:51:35,464 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:35,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:35,482 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:36,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:36,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1413 states to 418 states and 1387 transitions. [2018-10-26 21:51:36,004 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 1387 transitions. [2018-10-26 21:51:36,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-10-26 21:51:36,005 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:36,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:36,024 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:36,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:36,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1421 states to 421 states and 1394 transitions. [2018-10-26 21:51:36,335 INFO L276 IsEmpty]: Start isEmpty. Operand 421 states and 1394 transitions. [2018-10-26 21:51:36,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-10-26 21:51:36,336 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:36,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:36,351 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 8 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:36,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:36,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1422 states to 422 states and 1395 transitions. [2018-10-26 21:51:36,579 INFO L276 IsEmpty]: Start isEmpty. Operand 422 states and 1395 transitions. [2018-10-26 21:51:36,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-10-26 21:51:36,579 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:36,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:36,594 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 9 proven. 5 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:36,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:36,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1424 states to 424 states and 1397 transitions. [2018-10-26 21:51:36,609 INFO L276 IsEmpty]: Start isEmpty. Operand 424 states and 1397 transitions. [2018-10-26 21:51:36,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-10-26 21:51:36,610 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:36,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:36,626 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:51:36,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:36,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1427 states to 426 states and 1400 transitions. [2018-10-26 21:51:36,802 INFO L276 IsEmpty]: Start isEmpty. Operand 426 states and 1400 transitions. [2018-10-26 21:51:36,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-26 21:51:36,803 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:36,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:36,883 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:38,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:38,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1472 states to 433 states and 1444 transitions. [2018-10-26 21:51:38,301 INFO L276 IsEmpty]: Start isEmpty. Operand 433 states and 1444 transitions. [2018-10-26 21:51:38,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-26 21:51:38,302 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:38,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:38,363 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:38,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:38,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1498 states to 435 states and 1470 transitions. [2018-10-26 21:51:38,648 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 1470 transitions. [2018-10-26 21:51:38,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-26 21:51:38,648 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:38,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:38,661 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:39,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:39,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1508 states to 438 states and 1479 transitions. [2018-10-26 21:51:39,483 INFO L276 IsEmpty]: Start isEmpty. Operand 438 states and 1479 transitions. [2018-10-26 21:51:39,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-26 21:51:39,483 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:39,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:39,497 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:51:39,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:39,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1510 states to 440 states and 1481 transitions. [2018-10-26 21:51:39,540 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 1481 transitions. [2018-10-26 21:51:39,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:51:39,541 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:39,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:39,558 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:51:39,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:39,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1510 states to 441 states and 1481 transitions. [2018-10-26 21:51:39,586 INFO L276 IsEmpty]: Start isEmpty. Operand 441 states and 1481 transitions. [2018-10-26 21:51:39,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:51:39,586 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:39,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:39,603 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:40,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:40,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1551 states to 448 states and 1521 transitions. [2018-10-26 21:51:40,867 INFO L276 IsEmpty]: Start isEmpty. Operand 448 states and 1521 transitions. [2018-10-26 21:51:40,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:51:40,867 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:40,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:40,882 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:41,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:41,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 450 states and 1541 transitions. [2018-10-26 21:51:41,151 INFO L276 IsEmpty]: Start isEmpty. Operand 450 states and 1541 transitions. [2018-10-26 21:51:41,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:51:41,152 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:41,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:41,172 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:51:41,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:41,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1592 states to 452 states and 1562 transitions. [2018-10-26 21:51:41,730 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 1562 transitions. [2018-10-26 21:51:41,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:51:41,731 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:41,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:41,855 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:51:42,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:42,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1593 states to 453 states and 1563 transitions. [2018-10-26 21:51:42,315 INFO L276 IsEmpty]: Start isEmpty. Operand 453 states and 1563 transitions. [2018-10-26 21:51:42,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:51:42,316 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:42,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:42,338 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:51:43,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:43,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1600 states to 456 states and 1570 transitions. [2018-10-26 21:51:43,149 INFO L276 IsEmpty]: Start isEmpty. Operand 456 states and 1570 transitions. [2018-10-26 21:51:43,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:51:43,150 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:43,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:43,166 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:51:43,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:43,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1625 states to 459 states and 1595 transitions. [2018-10-26 21:51:43,869 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 1595 transitions. [2018-10-26 21:51:43,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:51:43,870 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:43,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:43,892 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:44,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:44,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1637 states to 462 states and 1606 transitions. [2018-10-26 21:51:44,822 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 1606 transitions. [2018-10-26 21:51:44,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:51:44,823 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:44,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:44,847 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:46,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:46,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1673 states to 467 states and 1642 transitions. [2018-10-26 21:51:46,111 INFO L276 IsEmpty]: Start isEmpty. Operand 467 states and 1642 transitions. [2018-10-26 21:51:46,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:51:46,111 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:46,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:46,131 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:46,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:46,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 470 states and 1669 transitions. [2018-10-26 21:51:46,778 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 1669 transitions. [2018-10-26 21:51:46,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:51:46,779 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:46,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:46,845 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:47,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:47,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1723 states to 472 states and 1691 transitions. [2018-10-26 21:51:47,191 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 1691 transitions. [2018-10-26 21:51:47,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:51:47,192 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:47,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:47,209 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:51:47,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:47,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1728 states to 475 states and 1696 transitions. [2018-10-26 21:51:47,448 INFO L276 IsEmpty]: Start isEmpty. Operand 475 states and 1696 transitions. [2018-10-26 21:51:47,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:47,449 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:47,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:47,470 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:48,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:48,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1740 states to 478 states and 1707 transitions. [2018-10-26 21:51:48,196 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 1707 transitions. [2018-10-26 21:51:48,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:48,197 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:48,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:48,211 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:49,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:49,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1777 states to 483 states and 1744 transitions. [2018-10-26 21:51:49,624 INFO L276 IsEmpty]: Start isEmpty. Operand 483 states and 1744 transitions. [2018-10-26 21:51:49,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:49,625 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:49,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:49,638 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:50,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:50,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1804 states to 486 states and 1771 transitions. [2018-10-26 21:51:50,398 INFO L276 IsEmpty]: Start isEmpty. Operand 486 states and 1771 transitions. [2018-10-26 21:51:50,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:50,398 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:50,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:50,415 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:51:50,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:50,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1826 states to 488 states and 1792 transitions. [2018-10-26 21:51:50,750 INFO L276 IsEmpty]: Start isEmpty. Operand 488 states and 1792 transitions. [2018-10-26 21:51:50,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:50,751 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:50,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:50,767 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:51:52,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:52,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1858 states to 493 states and 1824 transitions. [2018-10-26 21:51:52,111 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 1824 transitions. [2018-10-26 21:51:52,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:52,112 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:52,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:52,126 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:51:53,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:53,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1890 states to 497 states and 1856 transitions. [2018-10-26 21:51:53,119 INFO L276 IsEmpty]: Start isEmpty. Operand 497 states and 1856 transitions. [2018-10-26 21:51:53,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:53,120 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:53,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:53,147 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:51:53,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:53,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1915 states to 499 states and 1881 transitions. [2018-10-26 21:51:53,631 INFO L276 IsEmpty]: Start isEmpty. Operand 499 states and 1881 transitions. [2018-10-26 21:51:53,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:53,631 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:53,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:53,647 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:51:54,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:54,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1941 states to 501 states and 1907 transitions. [2018-10-26 21:51:54,025 INFO L276 IsEmpty]: Start isEmpty. Operand 501 states and 1907 transitions. [2018-10-26 21:51:54,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:54,026 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:54,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:54,045 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:51:54,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:54,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1944 states to 503 states and 1910 transitions. [2018-10-26 21:51:54,056 INFO L276 IsEmpty]: Start isEmpty. Operand 503 states and 1910 transitions. [2018-10-26 21:51:54,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:51:54,057 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:54,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:54,071 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:51:55,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:55,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1957 states to 506 states and 1922 transitions. [2018-10-26 21:51:55,182 INFO L276 IsEmpty]: Start isEmpty. Operand 506 states and 1922 transitions. [2018-10-26 21:51:55,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:51:55,183 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:55,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:55,196 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:51:55,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:55,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1992 states to 509 states and 1957 transitions. [2018-10-26 21:51:55,852 INFO L276 IsEmpty]: Start isEmpty. Operand 509 states and 1957 transitions. [2018-10-26 21:51:55,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:51:55,853 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:55,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:55,870 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:51:56,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:56,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2007 states to 512 states and 1972 transitions. [2018-10-26 21:51:56,969 INFO L276 IsEmpty]: Start isEmpty. Operand 512 states and 1972 transitions. [2018-10-26 21:51:56,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:51:56,970 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:56,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:56,992 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:51:58,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:58,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2035 states to 515 states and 1999 transitions. [2018-10-26 21:51:58,157 INFO L276 IsEmpty]: Start isEmpty. Operand 515 states and 1999 transitions. [2018-10-26 21:51:58,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:51:58,157 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:58,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:58,177 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:51:58,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:58,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2063 states to 517 states and 2027 transitions. [2018-10-26 21:51:58,540 INFO L276 IsEmpty]: Start isEmpty. Operand 517 states and 2027 transitions. [2018-10-26 21:51:58,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:58,541 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:58,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:58,562 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:51:59,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:51:59,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2072 states to 523 states and 2036 transitions. [2018-10-26 21:51:59,348 INFO L276 IsEmpty]: Start isEmpty. Operand 523 states and 2036 transitions. [2018-10-26 21:51:59,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:51:59,349 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:51:59,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:51:59,509 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:52:00,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:00,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2073 states to 524 states and 2037 transitions. [2018-10-26 21:52:00,123 INFO L276 IsEmpty]: Start isEmpty. Operand 524 states and 2037 transitions. [2018-10-26 21:52:00,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:00,124 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:00,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:00,147 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 21:52:00,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:00,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2074 states to 525 states and 2038 transitions. [2018-10-26 21:52:00,499 INFO L276 IsEmpty]: Start isEmpty. Operand 525 states and 2038 transitions. [2018-10-26 21:52:00,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:00,500 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:00,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:00,555 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 8 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:52:01,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:01,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2082 states to 528 states and 2045 transitions. [2018-10-26 21:52:01,766 INFO L276 IsEmpty]: Start isEmpty. Operand 528 states and 2045 transitions. [2018-10-26 21:52:01,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:01,767 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:01,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:01,785 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-10-26 21:52:02,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:02,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2087 states to 530 states and 2050 transitions. [2018-10-26 21:52:02,539 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 2050 transitions. [2018-10-26 21:52:02,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:02,540 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:02,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:02,560 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-10-26 21:52:03,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:03,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2087 states to 531 states and 2050 transitions. [2018-10-26 21:52:03,018 INFO L276 IsEmpty]: Start isEmpty. Operand 531 states and 2050 transitions. [2018-10-26 21:52:03,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:03,018 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:03,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:03,038 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 21:52:03,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:03,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2088 states to 532 states and 2051 transitions. [2018-10-26 21:52:03,369 INFO L276 IsEmpty]: Start isEmpty. Operand 532 states and 2051 transitions. [2018-10-26 21:52:03,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:52:03,370 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:03,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:03,392 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:52:03,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:03,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2090 states to 533 states and 2053 transitions. [2018-10-26 21:52:03,776 INFO L276 IsEmpty]: Start isEmpty. Operand 533 states and 2053 transitions. [2018-10-26 21:52:03,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:52:03,777 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:03,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:03,792 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:52:04,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:04,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2122 states to 537 states and 2085 transitions. [2018-10-26 21:52:04,601 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 2085 transitions. [2018-10-26 21:52:04,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:52:04,602 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:04,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:04,624 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:52:04,821 WARN L179 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 25 [2018-10-26 21:52:05,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:05,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2148 states to 539 states and 2111 transitions. [2018-10-26 21:52:05,180 INFO L276 IsEmpty]: Start isEmpty. Operand 539 states and 2111 transitions. [2018-10-26 21:52:05,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:52:05,181 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:05,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:05,194 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:52:05,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:05,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2173 states to 541 states and 2136 transitions. [2018-10-26 21:52:05,602 INFO L276 IsEmpty]: Start isEmpty. Operand 541 states and 2136 transitions. [2018-10-26 21:52:05,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:52:05,603 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:05,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:05,625 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:52:05,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:05,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2175 states to 543 states and 2138 transitions. [2018-10-26 21:52:05,644 INFO L276 IsEmpty]: Start isEmpty. Operand 543 states and 2138 transitions. [2018-10-26 21:52:05,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:52:05,644 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:05,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:05,660 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:07,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:07,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2213 states to 548 states and 2175 transitions. [2018-10-26 21:52:07,318 INFO L276 IsEmpty]: Start isEmpty. Operand 548 states and 2175 transitions. [2018-10-26 21:52:07,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:52:07,319 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:07,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:07,336 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:07,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:07,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2238 states to 550 states and 2200 transitions. [2018-10-26 21:52:07,742 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 2200 transitions. [2018-10-26 21:52:07,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:52:07,743 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:07,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:07,762 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:08,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:08,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2264 states to 552 states and 2226 transitions. [2018-10-26 21:52:08,213 INFO L276 IsEmpty]: Start isEmpty. Operand 552 states and 2226 transitions. [2018-10-26 21:52:08,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:52:08,213 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:08,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:08,233 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:52:08,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:08,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2268 states to 553 states and 2230 transitions. [2018-10-26 21:52:08,733 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 2230 transitions. [2018-10-26 21:52:08,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:52:08,734 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:08,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:08,748 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:09,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:09,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2292 states to 555 states and 2254 transitions. [2018-10-26 21:52:09,231 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 2254 transitions. [2018-10-26 21:52:09,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:52:09,232 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:09,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:09,246 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:09,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:09,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2317 states to 557 states and 2279 transitions. [2018-10-26 21:52:09,701 INFO L276 IsEmpty]: Start isEmpty. Operand 557 states and 2279 transitions. [2018-10-26 21:52:09,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:52:09,701 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:09,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:09,717 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:10,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:10,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2343 states to 559 states and 2305 transitions. [2018-10-26 21:52:10,207 INFO L276 IsEmpty]: Start isEmpty. Operand 559 states and 2305 transitions. [2018-10-26 21:52:10,207 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:10,207 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:10,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:10,225 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 21:52:10,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:10,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2345 states to 561 states and 2307 transitions. [2018-10-26 21:52:10,244 INFO L276 IsEmpty]: Start isEmpty. Operand 561 states and 2307 transitions. [2018-10-26 21:52:10,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:10,245 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:10,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:10,259 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 21:52:10,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:10,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2345 states to 562 states and 2307 transitions. [2018-10-26 21:52:10,447 INFO L276 IsEmpty]: Start isEmpty. Operand 562 states and 2307 transitions. [2018-10-26 21:52:10,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:52:10,448 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:10,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:10,461 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:11,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:11,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2353 states to 565 states and 2314 transitions. [2018-10-26 21:52:11,108 INFO L276 IsEmpty]: Start isEmpty. Operand 565 states and 2314 transitions. [2018-10-26 21:52:11,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-10-26 21:52:11,108 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:11,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:11,119 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:52:12,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:12,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2360 states to 568 states and 2320 transitions. [2018-10-26 21:52:12,423 INFO L276 IsEmpty]: Start isEmpty. Operand 568 states and 2320 transitions. [2018-10-26 21:52:12,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:52:12,424 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:12,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:12,438 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:13,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:13,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2370 states to 574 states and 2330 transitions. [2018-10-26 21:52:13,429 INFO L276 IsEmpty]: Start isEmpty. Operand 574 states and 2330 transitions. [2018-10-26 21:52:13,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:52:13,429 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:13,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:13,441 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-10-26 21:52:13,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:13,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2370 states to 575 states and 2330 transitions. [2018-10-26 21:52:13,704 INFO L276 IsEmpty]: Start isEmpty. Operand 575 states and 2330 transitions. [2018-10-26 21:52:13,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:52:13,705 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:13,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:13,717 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:52:14,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:14,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2370 states to 576 states and 2330 transitions. [2018-10-26 21:52:14,141 INFO L276 IsEmpty]: Start isEmpty. Operand 576 states and 2330 transitions. [2018-10-26 21:52:14,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:52:14,141 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:14,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:14,197 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:52:15,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:15,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2377 states to 579 states and 2336 transitions. [2018-10-26 21:52:15,615 INFO L276 IsEmpty]: Start isEmpty. Operand 579 states and 2336 transitions. [2018-10-26 21:52:15,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-26 21:52:15,616 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:15,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:15,627 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:52:16,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:16,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2384 states to 582 states and 2342 transitions. [2018-10-26 21:52:16,569 INFO L276 IsEmpty]: Start isEmpty. Operand 582 states and 2342 transitions. [2018-10-26 21:52:16,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:52:16,570 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:16,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:16,584 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:52:17,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:17,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2391 states to 585 states and 2348 transitions. [2018-10-26 21:52:17,513 INFO L276 IsEmpty]: Start isEmpty. Operand 585 states and 2348 transitions. [2018-10-26 21:52:17,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:17,514 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:17,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:17,809 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:19,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:19,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2420 states to 585 states and 2327 transitions. [2018-10-26 21:52:19,172 INFO L276 IsEmpty]: Start isEmpty. Operand 585 states and 2327 transitions. [2018-10-26 21:52:19,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:19,173 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:19,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:19,190 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:52:19,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:19,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2422 states to 587 states and 2329 transitions. [2018-10-26 21:52:19,201 INFO L276 IsEmpty]: Start isEmpty. Operand 587 states and 2329 transitions. [2018-10-26 21:52:19,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:19,202 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:19,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:19,222 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:52:19,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:19,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2433 states to 591 states and 2339 transitions. [2018-10-26 21:52:19,780 INFO L276 IsEmpty]: Start isEmpty. Operand 591 states and 2339 transitions. [2018-10-26 21:52:19,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:19,781 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:19,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:20,002 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 8 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-26 21:52:21,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:21,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2440 states to 594 states and 2345 transitions. [2018-10-26 21:52:21,031 INFO L276 IsEmpty]: Start isEmpty. Operand 594 states and 2345 transitions. [2018-10-26 21:52:21,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:52:21,032 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:21,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:21,049 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:21,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:21,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2440 states to 595 states and 2345 transitions. [2018-10-26 21:52:21,532 INFO L276 IsEmpty]: Start isEmpty. Operand 595 states and 2345 transitions. [2018-10-26 21:52:21,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:52:21,533 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:21,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:21,546 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:52:23,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:23,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2447 states to 598 states and 2351 transitions. [2018-10-26 21:52:23,275 INFO L276 IsEmpty]: Start isEmpty. Operand 598 states and 2351 transitions. [2018-10-26 21:52:23,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-26 21:52:23,276 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:23,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:23,293 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:24,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:24,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2457 states to 602 states and 2360 transitions. [2018-10-26 21:52:24,728 INFO L276 IsEmpty]: Start isEmpty. Operand 602 states and 2360 transitions. [2018-10-26 21:52:24,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:24,729 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:24,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:24,923 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:28,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:28,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2532 states to 610 states and 2405 transitions. [2018-10-26 21:52:28,267 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 2405 transitions. [2018-10-26 21:52:28,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:28,268 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:28,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:28,282 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:29,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:29,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2567 states to 613 states and 2439 transitions. [2018-10-26 21:52:29,396 INFO L276 IsEmpty]: Start isEmpty. Operand 613 states and 2439 transitions. [2018-10-26 21:52:29,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:29,396 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:29,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:29,410 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:29,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:29,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2589 states to 615 states and 2460 transitions. [2018-10-26 21:52:29,957 INFO L276 IsEmpty]: Start isEmpty. Operand 615 states and 2460 transitions. [2018-10-26 21:52:29,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:52:29,958 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:29,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:29,973 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:31,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:31,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2598 states to 621 states and 2469 transitions. [2018-10-26 21:52:31,598 INFO L276 IsEmpty]: Start isEmpty. Operand 621 states and 2469 transitions. [2018-10-26 21:52:31,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:31,599 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:31,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:31,611 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:32,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:32,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2620 states to 623 states and 2490 transitions. [2018-10-26 21:52:32,177 INFO L276 IsEmpty]: Start isEmpty. Operand 623 states and 2490 transitions. [2018-10-26 21:52:32,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:32,178 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:32,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:32,191 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:32,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:32,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2641 states to 625 states and 2510 transitions. [2018-10-26 21:52:32,727 INFO L276 IsEmpty]: Start isEmpty. Operand 625 states and 2510 transitions. [2018-10-26 21:52:32,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:32,728 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:32,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:32,853 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:33,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:33,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2663 states to 627 states and 2531 transitions. [2018-10-26 21:52:33,430 INFO L276 IsEmpty]: Start isEmpty. Operand 627 states and 2531 transitions. [2018-10-26 21:52:33,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:33,431 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:33,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:33,452 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:34,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:34,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2684 states to 629 states and 2551 transitions. [2018-10-26 21:52:34,089 INFO L276 IsEmpty]: Start isEmpty. Operand 629 states and 2551 transitions. [2018-10-26 21:52:34,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:34,090 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:34,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:34,104 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:34,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:34,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2705 states to 631 states and 2571 transitions. [2018-10-26 21:52:34,707 INFO L276 IsEmpty]: Start isEmpty. Operand 631 states and 2571 transitions. [2018-10-26 21:52:34,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:34,708 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:34,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:34,722 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:35,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:35,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2726 states to 633 states and 2591 transitions. [2018-10-26 21:52:35,303 INFO L276 IsEmpty]: Start isEmpty. Operand 633 states and 2591 transitions. [2018-10-26 21:52:35,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-10-26 21:52:35,304 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:35,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:35,321 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:52:35,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:35,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2728 states to 635 states and 2593 transitions. [2018-10-26 21:52:35,336 INFO L276 IsEmpty]: Start isEmpty. Operand 635 states and 2593 transitions. [2018-10-26 21:52:35,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:35,337 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:35,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:35,350 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:52:36,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:36,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2735 states to 638 states and 2599 transitions. [2018-10-26 21:52:36,592 INFO L276 IsEmpty]: Start isEmpty. Operand 638 states and 2599 transitions. [2018-10-26 21:52:36,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-10-26 21:52:36,592 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:36,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:36,612 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:52:37,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:37,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2741 states to 641 states and 2604 transitions. [2018-10-26 21:52:37,677 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 2604 transitions. [2018-10-26 21:52:37,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-26 21:52:37,678 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:37,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:37,718 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:52:39,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:39,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2752 states to 645 states and 2614 transitions. [2018-10-26 21:52:39,202 INFO L276 IsEmpty]: Start isEmpty. Operand 645 states and 2614 transitions. [2018-10-26 21:52:39,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-26 21:52:39,203 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:39,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:39,223 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:52:39,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:39,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2773 states to 647 states and 2634 transitions. [2018-10-26 21:52:39,600 INFO L276 IsEmpty]: Start isEmpty. Operand 647 states and 2634 transitions. [2018-10-26 21:52:39,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:52:39,601 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:39,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:39,616 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:40,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:40,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2782 states to 650 states and 2642 transitions. [2018-10-26 21:52:40,701 INFO L276 IsEmpty]: Start isEmpty. Operand 650 states and 2642 transitions. [2018-10-26 21:52:40,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:52:40,702 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:40,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:40,719 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:40,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:40,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2785 states to 651 states and 2645 transitions. [2018-10-26 21:52:40,992 INFO L276 IsEmpty]: Start isEmpty. Operand 651 states and 2645 transitions. [2018-10-26 21:52:40,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-10-26 21:52:40,994 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:41,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:41,013 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-10-26 21:52:41,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:41,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2788 states to 652 states and 2648 transitions. [2018-10-26 21:52:41,279 INFO L276 IsEmpty]: Start isEmpty. Operand 652 states and 2648 transitions. [2018-10-26 21:52:41,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:41,280 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:41,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:41,292 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:52:41,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:41,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2813 states to 653 states and 2673 transitions. [2018-10-26 21:52:41,353 INFO L276 IsEmpty]: Start isEmpty. Operand 653 states and 2673 transitions. [2018-10-26 21:52:41,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:41,354 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:41,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:41,367 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:52:42,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:42,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2823 states to 656 states and 2682 transitions. [2018-10-26 21:52:42,511 INFO L276 IsEmpty]: Start isEmpty. Operand 656 states and 2682 transitions. [2018-10-26 21:52:42,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:42,512 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:42,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:42,532 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:52:42,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:42,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2827 states to 657 states and 2686 transitions. [2018-10-26 21:52:42,897 INFO L276 IsEmpty]: Start isEmpty. Operand 657 states and 2686 transitions. [2018-10-26 21:52:42,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:42,898 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:42,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:42,912 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:52:44,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:44,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2837 states to 660 states and 2695 transitions. [2018-10-26 21:52:44,373 INFO L276 IsEmpty]: Start isEmpty. Operand 660 states and 2695 transitions. [2018-10-26 21:52:44,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:44,374 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:44,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:44,388 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:52:44,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:44,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2841 states to 661 states and 2699 transitions. [2018-10-26 21:52:44,942 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 2699 transitions. [2018-10-26 21:52:44,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:52:44,943 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:44,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:44,967 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-10-26 21:52:45,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:45,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2844 states to 663 states and 2702 transitions. [2018-10-26 21:52:45,587 INFO L276 IsEmpty]: Start isEmpty. Operand 663 states and 2702 transitions. [2018-10-26 21:52:45,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:45,588 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:45,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:45,604 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:47,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:47,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2856 states to 669 states and 2714 transitions. [2018-10-26 21:52:47,854 INFO L276 IsEmpty]: Start isEmpty. Operand 669 states and 2714 transitions. [2018-10-26 21:52:47,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:47,855 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:47,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:47,869 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:48,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:48,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2878 states to 671 states and 2735 transitions. [2018-10-26 21:52:48,447 INFO L276 IsEmpty]: Start isEmpty. Operand 671 states and 2735 transitions. [2018-10-26 21:52:48,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:48,448 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:48,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:48,474 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:49,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:49,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2901 states to 673 states and 2757 transitions. [2018-10-26 21:52:49,104 INFO L276 IsEmpty]: Start isEmpty. Operand 673 states and 2757 transitions. [2018-10-26 21:52:49,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:49,105 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:49,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:49,121 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:50,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:50,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2907 states to 676 states and 2762 transitions. [2018-10-26 21:52:50,606 INFO L276 IsEmpty]: Start isEmpty. Operand 676 states and 2762 transitions. [2018-10-26 21:52:50,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:52:50,606 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:50,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:50,620 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:52:51,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:51,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2907 states to 677 states and 2762 transitions. [2018-10-26 21:52:51,343 INFO L276 IsEmpty]: Start isEmpty. Operand 677 states and 2762 transitions. [2018-10-26 21:52:51,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:51,344 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:51,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:51,361 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:52,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:52,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2910 states to 679 states and 2764 transitions. [2018-10-26 21:52:52,182 INFO L276 IsEmpty]: Start isEmpty. Operand 679 states and 2764 transitions. [2018-10-26 21:52:52,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-26 21:52:52,183 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:52,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:52,199 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 21:52:52,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:52,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2912 states to 681 states and 2766 transitions. [2018-10-26 21:52:52,803 INFO L276 IsEmpty]: Start isEmpty. Operand 681 states and 2766 transitions. [2018-10-26 21:52:52,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:52,804 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:52,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:52,822 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:54,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:54,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2921 states to 687 states and 2775 transitions. [2018-10-26 21:52:54,837 INFO L276 IsEmpty]: Start isEmpty. Operand 687 states and 2775 transitions. [2018-10-26 21:52:54,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:54,839 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:54,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:54,861 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:52:55,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:55,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2921 states to 688 states and 2775 transitions. [2018-10-26 21:52:55,459 INFO L276 IsEmpty]: Start isEmpty. Operand 688 states and 2775 transitions. [2018-10-26 21:52:55,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:55,460 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:55,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:55,474 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 10 proven. 5 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:56,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:56,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2927 states to 690 states and 2781 transitions. [2018-10-26 21:52:56,624 INFO L276 IsEmpty]: Start isEmpty. Operand 690 states and 2781 transitions. [2018-10-26 21:52:56,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:56,625 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:56,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:56,638 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 10 proven. 5 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:52:57,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:57,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2930 states to 692 states and 2784 transitions. [2018-10-26 21:52:57,341 INFO L276 IsEmpty]: Start isEmpty. Operand 692 states and 2784 transitions. [2018-10-26 21:52:57,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-10-26 21:52:57,342 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:57,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:57,355 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:52:57,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:57,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2930 states to 693 states and 2784 transitions. [2018-10-26 21:52:57,372 INFO L276 IsEmpty]: Start isEmpty. Operand 693 states and 2784 transitions. [2018-10-26 21:52:57,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-10-26 21:52:57,373 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:57,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:57,389 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:52:57,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:57,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2931 states to 694 states and 2785 transitions. [2018-10-26 21:52:57,992 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 2785 transitions. [2018-10-26 21:52:57,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:57,993 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:57,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:58,006 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 6 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:52:59,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:59,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2936 states to 696 states and 2790 transitions. [2018-10-26 21:52:59,194 INFO L276 IsEmpty]: Start isEmpty. Operand 696 states and 2790 transitions. [2018-10-26 21:52:59,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:59,195 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:59,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:59,209 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 6 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:52:59,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:52:59,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2942 states to 699 states and 2796 transitions. [2018-10-26 21:52:59,469 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 2796 transitions. [2018-10-26 21:52:59,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:52:59,470 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:52:59,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:52:59,483 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 8 proven. 6 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:00,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:00,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2943 states to 700 states and 2797 transitions. [2018-10-26 21:53:00,041 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 2797 transitions. [2018-10-26 21:53:00,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:53:00,042 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:00,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:00,056 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-10-26 21:53:00,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:00,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2952 states to 705 states and 2806 transitions. [2018-10-26 21:53:00,660 INFO L276 IsEmpty]: Start isEmpty. Operand 705 states and 2806 transitions. [2018-10-26 21:53:00,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:53:00,661 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:00,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:00,675 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-10-26 21:53:00,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:00,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2953 states to 707 states and 2807 transitions. [2018-10-26 21:53:00,768 INFO L276 IsEmpty]: Start isEmpty. Operand 707 states and 2807 transitions. [2018-10-26 21:53:00,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:53:00,769 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:00,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:00,784 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:01,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:01,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2980 states to 710 states and 2834 transitions. [2018-10-26 21:53:01,796 INFO L276 IsEmpty]: Start isEmpty. Operand 710 states and 2834 transitions. [2018-10-26 21:53:01,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:53:01,797 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:01,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:01,811 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:03,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:03,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3032 states to 714 states and 2886 transitions. [2018-10-26 21:53:03,516 INFO L276 IsEmpty]: Start isEmpty. Operand 714 states and 2886 transitions. [2018-10-26 21:53:03,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:53:03,517 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:03,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:03,665 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:04,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:04,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3044 states to 715 states and 2898 transitions. [2018-10-26 21:53:04,384 INFO L276 IsEmpty]: Start isEmpty. Operand 715 states and 2898 transitions. [2018-10-26 21:53:04,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-26 21:53:04,386 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:04,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:04,457 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:53:05,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:05,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3048 states to 717 states and 2902 transitions. [2018-10-26 21:53:05,068 INFO L276 IsEmpty]: Start isEmpty. Operand 717 states and 2902 transitions. [2018-10-26 21:53:05,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-10-26 21:53:05,069 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:05,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:05,087 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 8 proven. 6 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 21:53:05,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:05,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3050 states to 719 states and 2904 transitions. [2018-10-26 21:53:05,766 INFO L276 IsEmpty]: Start isEmpty. Operand 719 states and 2904 transitions. [2018-10-26 21:53:05,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-10-26 21:53:05,767 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:05,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:05,865 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:53:06,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:06,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3046 states to 719 states and 2900 transitions. [2018-10-26 21:53:06,576 INFO L276 IsEmpty]: Start isEmpty. Operand 719 states and 2900 transitions. [2018-10-26 21:53:06,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-10-26 21:53:06,577 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:06,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:06,705 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:53:07,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:07,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3043 states to 718 states and 2897 transitions. [2018-10-26 21:53:07,080 INFO L276 IsEmpty]: Start isEmpty. Operand 718 states and 2897 transitions. [2018-10-26 21:53:07,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:07,081 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:07,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:07,096 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:53:07,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:07,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3043 states to 719 states and 2897 transitions. [2018-10-26 21:53:07,746 INFO L276 IsEmpty]: Start isEmpty. Operand 719 states and 2897 transitions. [2018-10-26 21:53:07,747 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:07,747 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:07,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:07,763 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:08,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:08,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3052 states to 724 states and 2906 transitions. [2018-10-26 21:53:08,069 INFO L276 IsEmpty]: Start isEmpty. Operand 724 states and 2906 transitions. [2018-10-26 21:53:08,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:08,071 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:08,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:08,096 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:08,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:08,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3053 states to 726 states and 2907 transitions. [2018-10-26 21:53:08,150 INFO L276 IsEmpty]: Start isEmpty. Operand 726 states and 2907 transitions. [2018-10-26 21:53:08,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-26 21:53:08,151 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:08,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:08,212 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-10-26 21:53:08,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:08,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3055 states to 728 states and 2909 transitions. [2018-10-26 21:53:08,232 INFO L276 IsEmpty]: Start isEmpty. Operand 728 states and 2909 transitions. [2018-10-26 21:53:08,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:53:08,233 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:08,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:08,304 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:53:08,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:08,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3049 states to 728 states and 2903 transitions. [2018-10-26 21:53:08,419 INFO L276 IsEmpty]: Start isEmpty. Operand 728 states and 2903 transitions. [2018-10-26 21:53:08,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:08,420 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:08,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:08,436 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:09,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:09,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3058 states to 731 states and 2912 transitions. [2018-10-26 21:53:09,370 INFO L276 IsEmpty]: Start isEmpty. Operand 731 states and 2912 transitions. [2018-10-26 21:53:09,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:09,371 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:09,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:09,386 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:11,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:11,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3093 states to 735 states and 2945 transitions. [2018-10-26 21:53:11,405 INFO L276 IsEmpty]: Start isEmpty. Operand 735 states and 2945 transitions. [2018-10-26 21:53:11,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:11,406 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:11,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:11,421 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:53:12,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:12,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3093 states to 736 states and 2945 transitions. [2018-10-26 21:53:12,040 INFO L276 IsEmpty]: Start isEmpty. Operand 736 states and 2945 transitions. [2018-10-26 21:53:12,041 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:12,041 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:12,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:12,057 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:12,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:12,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3093 states to 737 states and 2945 transitions. [2018-10-26 21:53:12,632 INFO L276 IsEmpty]: Start isEmpty. Operand 737 states and 2945 transitions. [2018-10-26 21:53:12,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:12,633 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:12,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:12,649 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:13,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:13,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3116 states to 739 states and 2967 transitions. [2018-10-26 21:53:13,347 INFO L276 IsEmpty]: Start isEmpty. Operand 739 states and 2967 transitions. [2018-10-26 21:53:13,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:13,348 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:13,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:13,363 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:14,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:14,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3142 states to 741 states and 2991 transitions. [2018-10-26 21:53:14,020 INFO L276 IsEmpty]: Start isEmpty. Operand 741 states and 2991 transitions. [2018-10-26 21:53:14,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:14,021 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:14,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:14,038 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:14,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:14,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3165 states to 743 states and 3012 transitions. [2018-10-26 21:53:14,932 INFO L276 IsEmpty]: Start isEmpty. Operand 743 states and 3012 transitions. [2018-10-26 21:53:14,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:14,933 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:14,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:14,948 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:15,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:15,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3194 states to 745 states and 3039 transitions. [2018-10-26 21:53:15,592 INFO L276 IsEmpty]: Start isEmpty. Operand 745 states and 3039 transitions. [2018-10-26 21:53:15,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:15,593 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:15,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:15,606 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:53:16,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:16,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3216 states to 748 states and 3060 transitions. [2018-10-26 21:53:16,931 INFO L276 IsEmpty]: Start isEmpty. Operand 748 states and 3060 transitions. [2018-10-26 21:53:16,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:16,933 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:16,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:16,954 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:53:18,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:18,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3219 states to 750 states and 3062 transitions. [2018-10-26 21:53:18,069 INFO L276 IsEmpty]: Start isEmpty. Operand 750 states and 3062 transitions. [2018-10-26 21:53:18,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:53:18,070 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:18,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:18,089 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:18,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:18,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3225 states to 753 states and 3068 transitions. [2018-10-26 21:53:18,306 INFO L276 IsEmpty]: Start isEmpty. Operand 753 states and 3068 transitions. [2018-10-26 21:53:18,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:53:18,307 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:18,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:18,326 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:18,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:18,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3226 states to 754 states and 3069 transitions. [2018-10-26 21:53:18,366 INFO L276 IsEmpty]: Start isEmpty. Operand 754 states and 3069 transitions. [2018-10-26 21:53:18,367 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:18,367 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:18,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:18,381 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-10-26 21:53:19,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:19,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3229 states to 755 states and 3072 transitions. [2018-10-26 21:53:19,027 INFO L276 IsEmpty]: Start isEmpty. Operand 755 states and 3072 transitions. [2018-10-26 21:53:19,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:19,029 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:19,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:19,043 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-10-26 21:53:20,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:20,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3234 states to 757 states and 3077 transitions. [2018-10-26 21:53:20,309 INFO L276 IsEmpty]: Start isEmpty. Operand 757 states and 3077 transitions. [2018-10-26 21:53:20,310 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:20,310 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:20,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:20,325 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-10-26 21:53:20,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:20,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3235 states to 758 states and 3078 transitions. [2018-10-26 21:53:20,956 INFO L276 IsEmpty]: Start isEmpty. Operand 758 states and 3078 transitions. [2018-10-26 21:53:20,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:20,957 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:20,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:20,971 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-10-26 21:53:20,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:20,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3237 states to 760 states and 3080 transitions. [2018-10-26 21:53:20,985 INFO L276 IsEmpty]: Start isEmpty. Operand 760 states and 3080 transitions. [2018-10-26 21:53:20,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:20,986 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:20,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:21,003 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 21:53:22,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:22,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3243 states to 762 states and 3086 transitions. [2018-10-26 21:53:22,480 INFO L276 IsEmpty]: Start isEmpty. Operand 762 states and 3086 transitions. [2018-10-26 21:53:22,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:22,482 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:22,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:22,506 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 21:53:23,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:23,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3248 states to 764 states and 3091 transitions. [2018-10-26 21:53:23,894 INFO L276 IsEmpty]: Start isEmpty. Operand 764 states and 3091 transitions. [2018-10-26 21:53:23,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:23,895 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:23,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:23,912 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 21:53:24,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:24,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3273 states to 766 states and 3115 transitions. [2018-10-26 21:53:24,487 INFO L276 IsEmpty]: Start isEmpty. Operand 766 states and 3115 transitions. [2018-10-26 21:53:24,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:24,488 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:24,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:24,675 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-10-26 21:53:24,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:24,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3275 states to 768 states and 3117 transitions. [2018-10-26 21:53:24,718 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 3117 transitions. [2018-10-26 21:53:24,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-26 21:53:24,720 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:24,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:24,743 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-10-26 21:53:24,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:24,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3277 states to 770 states and 3119 transitions. [2018-10-26 21:53:24,804 INFO L276 IsEmpty]: Start isEmpty. Operand 770 states and 3119 transitions. [2018-10-26 21:53:24,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-26 21:53:24,805 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:24,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:24,820 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:25,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:25,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3280 states to 772 states and 3122 transitions. [2018-10-26 21:53:25,180 INFO L276 IsEmpty]: Start isEmpty. Operand 772 states and 3122 transitions. [2018-10-26 21:53:25,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:25,181 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:25,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:25,194 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:53:25,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:25,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3280 states to 773 states and 3122 transitions. [2018-10-26 21:53:25,848 INFO L276 IsEmpty]: Start isEmpty. Operand 773 states and 3122 transitions. [2018-10-26 21:53:25,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:25,850 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:25,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:25,863 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-10-26 21:53:26,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:26,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3280 states to 774 states and 3122 transitions. [2018-10-26 21:53:26,492 INFO L276 IsEmpty]: Start isEmpty. Operand 774 states and 3122 transitions. [2018-10-26 21:53:26,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:26,493 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:26,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:26,508 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 21:53:26,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:26,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3282 states to 775 states and 3124 transitions. [2018-10-26 21:53:26,521 INFO L276 IsEmpty]: Start isEmpty. Operand 775 states and 3124 transitions. [2018-10-26 21:53:26,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:26,522 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:26,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:26,537 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:27,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:27,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3289 states to 778 states and 3131 transitions. [2018-10-26 21:53:27,930 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 3131 transitions. [2018-10-26 21:53:27,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:27,931 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:27,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:27,948 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:28,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:28,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3292 states to 779 states and 3134 transitions. [2018-10-26 21:53:28,691 INFO L276 IsEmpty]: Start isEmpty. Operand 779 states and 3134 transitions. [2018-10-26 21:53:28,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:28,692 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:28,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:28,709 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:29,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:29,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3310 states to 781 states and 3151 transitions. [2018-10-26 21:53:29,367 INFO L276 IsEmpty]: Start isEmpty. Operand 781 states and 3151 transitions. [2018-10-26 21:53:29,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:29,368 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:29,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:29,382 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:30,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:30,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3328 states to 783 states and 3168 transitions. [2018-10-26 21:53:30,112 INFO L276 IsEmpty]: Start isEmpty. Operand 783 states and 3168 transitions. [2018-10-26 21:53:30,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-26 21:53:30,114 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:30,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:30,129 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-10-26 21:53:30,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:30,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3333 states to 786 states and 3173 transitions. [2018-10-26 21:53:30,176 INFO L276 IsEmpty]: Start isEmpty. Operand 786 states and 3173 transitions. [2018-10-26 21:53:30,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-26 21:53:30,177 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:30,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:30,191 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-10-26 21:53:30,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:30,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3334 states to 787 states and 3174 transitions. [2018-10-26 21:53:30,239 INFO L276 IsEmpty]: Start isEmpty. Operand 787 states and 3174 transitions. [2018-10-26 21:53:30,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-26 21:53:30,240 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:30,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:30,256 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:31,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:31,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3349 states to 792 states and 3189 transitions. [2018-10-26 21:53:31,975 INFO L276 IsEmpty]: Start isEmpty. Operand 792 states and 3189 transitions. [2018-10-26 21:53:31,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-26 21:53:31,977 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:31,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:31,997 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:32,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:32,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3356 states to 795 states and 3196 transitions. [2018-10-26 21:53:32,047 INFO L276 IsEmpty]: Start isEmpty. Operand 795 states and 3196 transitions. [2018-10-26 21:53:32,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:32,048 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:32,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:32,064 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-10-26 21:53:32,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:32,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3358 states to 797 states and 3198 transitions. [2018-10-26 21:53:32,093 INFO L276 IsEmpty]: Start isEmpty. Operand 797 states and 3198 transitions. [2018-10-26 21:53:32,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-26 21:53:32,094 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:32,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:32,111 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:33,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:33,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3369 states to 802 states and 3209 transitions. [2018-10-26 21:53:33,773 INFO L276 IsEmpty]: Start isEmpty. Operand 802 states and 3209 transitions. [2018-10-26 21:53:33,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-26 21:53:33,774 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:33,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:33,791 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:34,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:34,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3371 states to 804 states and 3211 transitions. [2018-10-26 21:53:34,548 INFO L276 IsEmpty]: Start isEmpty. Operand 804 states and 3211 transitions. [2018-10-26 21:53:34,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:53:34,549 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:34,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:34,567 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-10-26 21:53:36,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:36,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3376 states to 806 states and 3216 transitions. [2018-10-26 21:53:36,173 INFO L276 IsEmpty]: Start isEmpty. Operand 806 states and 3216 transitions. [2018-10-26 21:53:36,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:53:36,175 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:36,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:36,191 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-10-26 21:53:36,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:36,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3376 states to 807 states and 3216 transitions. [2018-10-26 21:53:36,824 INFO L276 IsEmpty]: Start isEmpty. Operand 807 states and 3216 transitions. [2018-10-26 21:53:36,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-26 21:53:36,825 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:36,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:36,842 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:36,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:36,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3382 states to 810 states and 3222 transitions. [2018-10-26 21:53:36,892 INFO L276 IsEmpty]: Start isEmpty. Operand 810 states and 3222 transitions. [2018-10-26 21:53:36,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-26 21:53:36,893 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:36,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:36,910 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:36,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:36,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3383 states to 811 states and 3223 transitions. [2018-10-26 21:53:36,963 INFO L276 IsEmpty]: Start isEmpty. Operand 811 states and 3223 transitions. [2018-10-26 21:53:36,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-26 21:53:36,964 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:36,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:36,986 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-10-26 21:53:37,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:37,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3385 states to 812 states and 3225 transitions. [2018-10-26 21:53:37,015 INFO L276 IsEmpty]: Start isEmpty. Operand 812 states and 3225 transitions. [2018-10-26 21:53:37,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:37,016 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:37,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:37,032 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:37,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:37,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3391 states to 815 states and 3231 transitions. [2018-10-26 21:53:37,377 INFO L276 IsEmpty]: Start isEmpty. Operand 815 states and 3231 transitions. [2018-10-26 21:53:37,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:37,378 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:37,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:37,393 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:37,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:37,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3391 states to 816 states and 3231 transitions. [2018-10-26 21:53:37,714 INFO L276 IsEmpty]: Start isEmpty. Operand 816 states and 3231 transitions. [2018-10-26 21:53:37,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:37,715 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:37,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:37,728 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:38,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:38,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3393 states to 818 states and 3233 transitions. [2018-10-26 21:53:38,229 INFO L276 IsEmpty]: Start isEmpty. Operand 818 states and 3233 transitions. [2018-10-26 21:53:38,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:38,230 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:38,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:38,245 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:53:38,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:38,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3395 states to 819 states and 3235 transitions. [2018-10-26 21:53:38,591 INFO L276 IsEmpty]: Start isEmpty. Operand 819 states and 3235 transitions. [2018-10-26 21:53:38,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:38,592 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:38,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:38,612 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-10-26 21:53:38,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:38,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3398 states to 820 states and 3238 transitions. [2018-10-26 21:53:38,964 INFO L276 IsEmpty]: Start isEmpty. Operand 820 states and 3238 transitions. [2018-10-26 21:53:38,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:38,965 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:38,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:38,980 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:53:39,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:39,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3401 states to 822 states and 3241 transitions. [2018-10-26 21:53:39,657 INFO L276 IsEmpty]: Start isEmpty. Operand 822 states and 3241 transitions. [2018-10-26 21:53:39,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:39,658 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:39,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:39,672 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-10-26 21:53:40,480 WARN L179 SmtUtils]: Spent 196.00 ms on a formula simplification that was a NOOP. DAG size: 22 [2018-10-26 21:53:40,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:40,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3401 states to 823 states and 3241 transitions. [2018-10-26 21:53:40,490 INFO L276 IsEmpty]: Start isEmpty. Operand 823 states and 3241 transitions. [2018-10-26 21:53:40,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:40,491 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:40,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:40,507 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:40,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:40,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3403 states to 825 states and 3243 transitions. [2018-10-26 21:53:40,527 INFO L276 IsEmpty]: Start isEmpty. Operand 825 states and 3243 transitions. [2018-10-26 21:53:40,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:40,529 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:40,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:40,545 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 21:53:41,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:41,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3406 states to 827 states and 3246 transitions. [2018-10-26 21:53:41,248 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 3246 transitions. [2018-10-26 21:53:41,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:41,249 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:41,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:41,264 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 5 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:53:42,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:42,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3415 states to 832 states and 3255 transitions. [2018-10-26 21:53:42,627 INFO L276 IsEmpty]: Start isEmpty. Operand 832 states and 3255 transitions. [2018-10-26 21:53:42,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:42,628 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:42,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:42,643 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-10-26 21:53:42,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:42,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3422 states to 835 states and 3262 transitions. [2018-10-26 21:53:42,689 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 3262 transitions. [2018-10-26 21:53:42,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-10-26 21:53:42,690 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:42,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:42,708 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 5 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:53:43,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:43,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3424 states to 837 states and 3264 transitions. [2018-10-26 21:53:43,594 INFO L276 IsEmpty]: Start isEmpty. Operand 837 states and 3264 transitions. [2018-10-26 21:53:43,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:43,595 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:43,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:43,614 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-10-26 21:53:44,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:44,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3429 states to 840 states and 3268 transitions. [2018-10-26 21:53:44,290 INFO L276 IsEmpty]: Start isEmpty. Operand 840 states and 3268 transitions. [2018-10-26 21:53:44,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:44,291 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:44,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:44,311 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:45,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:45,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3448 states to 845 states and 3287 transitions. [2018-10-26 21:53:45,528 INFO L276 IsEmpty]: Start isEmpty. Operand 845 states and 3287 transitions. [2018-10-26 21:53:45,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:45,529 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:45,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:45,851 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:46,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:46,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3367 states to 844 states and 3206 transitions. [2018-10-26 21:53:46,173 INFO L276 IsEmpty]: Start isEmpty. Operand 844 states and 3206 transitions. [2018-10-26 21:53:46,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:46,174 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:46,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:46,189 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:46,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:46,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3374 states to 847 states and 3213 transitions. [2018-10-26 21:53:46,236 INFO L276 IsEmpty]: Start isEmpty. Operand 847 states and 3213 transitions. [2018-10-26 21:53:46,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:46,237 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:46,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:46,252 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-10-26 21:53:46,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:46,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3376 states to 849 states and 3215 transitions. [2018-10-26 21:53:46,281 INFO L276 IsEmpty]: Start isEmpty. Operand 849 states and 3215 transitions. [2018-10-26 21:53:46,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:46,283 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:46,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:46,298 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-10-26 21:53:46,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:46,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3378 states to 851 states and 3217 transitions. [2018-10-26 21:53:46,326 INFO L276 IsEmpty]: Start isEmpty. Operand 851 states and 3217 transitions. [2018-10-26 21:53:46,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-26 21:53:46,327 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:46,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:46,342 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:46,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:46,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3386 states to 853 states and 3225 transitions. [2018-10-26 21:53:46,389 INFO L276 IsEmpty]: Start isEmpty. Operand 853 states and 3225 transitions. [2018-10-26 21:53:46,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:53:46,390 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:46,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:46,405 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:46,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:46,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3388 states to 855 states and 3227 transitions. [2018-10-26 21:53:46,794 INFO L276 IsEmpty]: Start isEmpty. Operand 855 states and 3227 transitions. [2018-10-26 21:53:46,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:46,795 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:46,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:46,811 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 5 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:53:46,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:46,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3394 states to 858 states and 3233 transitions. [2018-10-26 21:53:46,844 INFO L276 IsEmpty]: Start isEmpty. Operand 858 states and 3233 transitions. [2018-10-26 21:53:46,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:46,845 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:46,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:46,860 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 5 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:53:46,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:46,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3395 states to 859 states and 3234 transitions. [2018-10-26 21:53:46,896 INFO L276 IsEmpty]: Start isEmpty. Operand 859 states and 3234 transitions. [2018-10-26 21:53:46,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-10-26 21:53:46,897 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:46,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:46,911 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-10-26 21:53:46,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:46,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3395 states to 860 states and 3234 transitions. [2018-10-26 21:53:46,941 INFO L276 IsEmpty]: Start isEmpty. Operand 860 states and 3234 transitions. [2018-10-26 21:53:46,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-26 21:53:46,942 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:46,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:47,041 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 29 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:47,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:47,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3397 states to 861 states and 3236 transitions. [2018-10-26 21:53:47,720 INFO L276 IsEmpty]: Start isEmpty. Operand 861 states and 3236 transitions. [2018-10-26 21:53:47,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:53:47,721 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:47,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:47,738 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:47,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:47,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3404 states to 866 states and 3243 transitions. [2018-10-26 21:53:47,759 INFO L276 IsEmpty]: Start isEmpty. Operand 866 states and 3243 transitions. [2018-10-26 21:53:47,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-26 21:53:47,760 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:47,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:47,784 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:48,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:48,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3430 states to 869 states and 3269 transitions. [2018-10-26 21:53:48,836 INFO L276 IsEmpty]: Start isEmpty. Operand 869 states and 3269 transitions. [2018-10-26 21:53:48,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-26 21:53:48,837 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:48,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:48,855 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:48,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:48,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3445 states to 870 states and 3284 transitions. [2018-10-26 21:53:48,920 INFO L276 IsEmpty]: Start isEmpty. Operand 870 states and 3284 transitions. [2018-10-26 21:53:48,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-26 21:53:48,921 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:48,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:48,937 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 5 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:53:48,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:48,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3452 states to 873 states and 3291 transitions. [2018-10-26 21:53:48,975 INFO L276 IsEmpty]: Start isEmpty. Operand 873 states and 3291 transitions. [2018-10-26 21:53:48,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:53:48,977 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:48,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:48,992 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:53:49,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:49,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3454 states to 875 states and 3293 transitions. [2018-10-26 21:53:49,014 INFO L276 IsEmpty]: Start isEmpty. Operand 875 states and 3293 transitions. [2018-10-26 21:53:49,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:53:49,016 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:49,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:49,029 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:53:49,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:49,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3458 states to 876 states and 3297 transitions. [2018-10-26 21:53:49,768 INFO L276 IsEmpty]: Start isEmpty. Operand 876 states and 3297 transitions. [2018-10-26 21:53:49,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-26 21:53:49,771 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:49,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:49,807 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-10-26 21:53:49,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:49,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3458 states to 877 states and 3297 transitions. [2018-10-26 21:53:49,822 INFO L276 IsEmpty]: Start isEmpty. Operand 877 states and 3297 transitions. [2018-10-26 21:53:49,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:49,823 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:49,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:49,838 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-10-26 21:53:50,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:50,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3458 states to 878 states and 3297 transitions. [2018-10-26 21:53:50,552 INFO L276 IsEmpty]: Start isEmpty. Operand 878 states and 3297 transitions. [2018-10-26 21:53:50,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:50,553 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:50,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:50,574 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-10-26 21:53:51,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:51,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3458 states to 879 states and 3297 transitions. [2018-10-26 21:53:51,279 INFO L276 IsEmpty]: Start isEmpty. Operand 879 states and 3297 transitions. [2018-10-26 21:53:51,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:51,280 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:51,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:51,295 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-10-26 21:53:52,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:52,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3477 states to 882 states and 3315 transitions. [2018-10-26 21:53:52,517 INFO L276 IsEmpty]: Start isEmpty. Operand 882 states and 3315 transitions. [2018-10-26 21:53:52,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:52,518 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:52,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:52,812 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:56,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:56,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3553 states to 890 states and 3389 transitions. [2018-10-26 21:53:56,514 INFO L276 IsEmpty]: Start isEmpty. Operand 890 states and 3389 transitions. [2018-10-26 21:53:56,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:56,516 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:56,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:56,530 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:57,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:57,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3577 states to 892 states and 3411 transitions. [2018-10-26 21:53:57,502 INFO L276 IsEmpty]: Start isEmpty. Operand 892 states and 3411 transitions. [2018-10-26 21:53:57,504 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:57,504 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:57,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:57,521 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:59,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:59,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3623 states to 895 states and 3455 transitions. [2018-10-26 21:53:59,049 INFO L276 IsEmpty]: Start isEmpty. Operand 895 states and 3455 transitions. [2018-10-26 21:53:59,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:59,050 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:59,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:59,064 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:53:59,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:53:59,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3647 states to 897 states and 3477 transitions. [2018-10-26 21:53:59,810 INFO L276 IsEmpty]: Start isEmpty. Operand 897 states and 3477 transitions. [2018-10-26 21:53:59,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:53:59,812 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:53:59,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:53:59,828 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:54:00,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:00,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3670 states to 899 states and 3498 transitions. [2018-10-26 21:54:00,751 INFO L276 IsEmpty]: Start isEmpty. Operand 899 states and 3498 transitions. [2018-10-26 21:54:00,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:54:00,753 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:00,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:00,766 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:54:01,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:01,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3693 states to 901 states and 3519 transitions. [2018-10-26 21:54:01,526 INFO L276 IsEmpty]: Start isEmpty. Operand 901 states and 3519 transitions. [2018-10-26 21:54:01,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:54:01,528 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:01,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:02,026 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:54:02,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:02,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3705 states to 904 states and 3531 transitions. [2018-10-26 21:54:02,764 INFO L276 IsEmpty]: Start isEmpty. Operand 904 states and 3531 transitions. [2018-10-26 21:54:02,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-10-26 21:54:02,765 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:02,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:02,780 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-10-26 21:54:02,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:02,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3738 states to 907 states and 3564 transitions. [2018-10-26 21:54:02,845 INFO L276 IsEmpty]: Start isEmpty. Operand 907 states and 3564 transitions. [2018-10-26 21:54:02,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:02,847 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:02,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:02,865 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-10-26 21:54:03,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:03,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3738 states to 908 states and 3564 transitions. [2018-10-26 21:54:03,653 INFO L276 IsEmpty]: Start isEmpty. Operand 908 states and 3564 transitions. [2018-10-26 21:54:03,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-10-26 21:54:03,654 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:03,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:03,674 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-10-26 21:54:05,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:05,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3744 states to 911 states and 3569 transitions. [2018-10-26 21:54:05,569 INFO L276 IsEmpty]: Start isEmpty. Operand 911 states and 3569 transitions. [2018-10-26 21:54:05,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-10-26 21:54:05,571 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:05,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:05,604 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-10-26 21:54:05,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:05,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3744 states to 912 states and 3569 transitions. [2018-10-26 21:54:05,680 INFO L276 IsEmpty]: Start isEmpty. Operand 912 states and 3569 transitions. [2018-10-26 21:54:05,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-26 21:54:05,682 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:05,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:05,708 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:54:05,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:05,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3745 states to 914 states and 3570 transitions. [2018-10-26 21:54:05,799 INFO L276 IsEmpty]: Start isEmpty. Operand 914 states and 3570 transitions. [2018-10-26 21:54:05,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:05,802 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:05,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:05,834 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:54:08,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:08,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3764 states to 919 states and 3588 transitions. [2018-10-26 21:54:08,412 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 3588 transitions. [2018-10-26 21:54:08,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:08,413 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:08,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:08,429 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:54:09,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:09,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3768 states to 921 states and 3592 transitions. [2018-10-26 21:54:09,163 INFO L276 IsEmpty]: Start isEmpty. Operand 921 states and 3592 transitions. [2018-10-26 21:54:09,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:09,164 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:09,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:09,181 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-10-26 21:54:09,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:09,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 922 states and 3595 transitions. [2018-10-26 21:54:09,398 INFO L276 IsEmpty]: Start isEmpty. Operand 922 states and 3595 transitions. [2018-10-26 21:54:09,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:09,399 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:09,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:09,421 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:54:10,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:10,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3780 states to 925 states and 3604 transitions. [2018-10-26 21:54:10,211 INFO L276 IsEmpty]: Start isEmpty. Operand 925 states and 3604 transitions. [2018-10-26 21:54:10,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:10,212 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:10,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:10,227 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:54:11,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:11,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3782 states to 927 states and 3606 transitions. [2018-10-26 21:54:11,605 INFO L276 IsEmpty]: Start isEmpty. Operand 927 states and 3606 transitions. [2018-10-26 21:54:11,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:11,606 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:11,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:11,622 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:54:12,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:12,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3784 states to 929 states and 3608 transitions. [2018-10-26 21:54:12,395 INFO L276 IsEmpty]: Start isEmpty. Operand 929 states and 3608 transitions. [2018-10-26 21:54:12,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:54:12,396 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:12,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:12,418 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-10-26 21:54:14,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:14,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3793 states to 932 states and 3617 transitions. [2018-10-26 21:54:14,675 INFO L276 IsEmpty]: Start isEmpty. Operand 932 states and 3617 transitions. [2018-10-26 21:54:14,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:54:14,676 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:14,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:14,695 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-10-26 21:54:14,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:14,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3794 states to 933 states and 3618 transitions. [2018-10-26 21:54:14,742 INFO L276 IsEmpty]: Start isEmpty. Operand 933 states and 3618 transitions. [2018-10-26 21:54:14,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:54:14,744 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:14,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:14,760 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-10-26 21:54:15,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:15,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3795 states to 934 states and 3619 transitions. [2018-10-26 21:54:15,385 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 3619 transitions. [2018-10-26 21:54:15,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:15,386 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:15,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:15,401 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:54:17,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:17,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3797 states to 936 states and 3621 transitions. [2018-10-26 21:54:17,154 INFO L276 IsEmpty]: Start isEmpty. Operand 936 states and 3621 transitions. [2018-10-26 21:54:17,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:17,155 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:17,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:17,170 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-10-26 21:54:17,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:17,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3797 states to 937 states and 3621 transitions. [2018-10-26 21:54:17,895 INFO L276 IsEmpty]: Start isEmpty. Operand 937 states and 3621 transitions. [2018-10-26 21:54:17,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:54:17,897 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:17,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:17,919 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-10-26 21:54:18,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:18,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3816 states to 939 states and 3639 transitions. [2018-10-26 21:54:18,585 INFO L276 IsEmpty]: Start isEmpty. Operand 939 states and 3639 transitions. [2018-10-26 21:54:18,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:54:18,587 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:18,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:18,603 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-10-26 21:54:18,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:18,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3816 states to 940 states and 3639 transitions. [2018-10-26 21:54:18,975 INFO L276 IsEmpty]: Start isEmpty. Operand 940 states and 3639 transitions. [2018-10-26 21:54:18,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:54:18,977 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:18,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:19,005 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-10-26 21:54:19,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:19,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3818 states to 941 states and 3641 transitions. [2018-10-26 21:54:19,724 INFO L276 IsEmpty]: Start isEmpty. Operand 941 states and 3641 transitions. [2018-10-26 21:54:19,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-10-26 21:54:19,726 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:19,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:19,744 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-10-26 21:54:19,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:19,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3823 states to 944 states and 3646 transitions. [2018-10-26 21:54:19,767 INFO L276 IsEmpty]: Start isEmpty. Operand 944 states and 3646 transitions. [2018-10-26 21:54:19,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-26 21:54:19,768 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:19,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:20,753 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 21:54:22,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:22,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3825 states to 945 states and 3648 transitions. [2018-10-26 21:54:22,036 INFO L276 IsEmpty]: Start isEmpty. Operand 945 states and 3648 transitions. [2018-10-26 21:54:22,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-10-26 21:54:22,038 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:22,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:23,167 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 21:54:24,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:24,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3827 states to 946 states and 3650 transitions. [2018-10-26 21:54:24,488 INFO L276 IsEmpty]: Start isEmpty. Operand 946 states and 3650 transitions. [2018-10-26 21:54:24,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-10-26 21:54:24,490 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:24,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:24,911 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 21:54:26,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:26,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3828 states to 947 states and 3651 transitions. [2018-10-26 21:54:26,264 INFO L276 IsEmpty]: Start isEmpty. Operand 947 states and 3651 transitions. [2018-10-26 21:54:26,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-10-26 21:54:26,265 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:26,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-26 21:54:26,736 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-10-26 21:54:28,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:54:28,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3829 states to 948 states and 3652 transitions. [2018-10-26 21:54:28,115 INFO L276 IsEmpty]: Start isEmpty. Operand 948 states and 3652 transitions. [2018-10-26 21:54:28,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-10-26 21:54:28,117 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:54:28,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 21:54:28,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 21:54:29,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 21:54:29,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-26 21:54:30,084 WARN L496 CodeCheckObserver]: This program is UNSAFE, Check terminated with 289 iterations. [2018-10-26 21:54:30,114 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,115 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,116 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,116 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,118 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,119 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,119 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,120 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,120 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,121 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,121 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,122 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,122 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,122 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,122 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,123 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,123 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,123 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,124 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,124 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,132 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,132 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,133 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,133 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,133 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,134 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,134 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,134 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,135 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,135 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,135 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,136 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,136 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,143 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,143 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,144 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,144 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,144 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,145 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,145 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,146 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,146 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,146 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,147 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,147 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,147 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,158 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,158 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,158 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,159 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,159 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,159 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,160 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,160 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,160 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,161 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,161 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,161 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,162 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,162 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,162 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,163 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,163 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,163 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,164 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,164 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,175 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,176 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,176 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,176 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,177 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,177 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,177 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,178 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,178 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,178 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,179 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,179 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,179 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,180 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,180 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,180 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,181 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,181 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,181 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,182 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,182 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,183 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,183 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,183 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,184 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,196 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,197 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,197 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,198 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,198 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,198 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,198 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,199 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,199 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,199 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,200 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,200 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,201 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,201 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,201 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,202 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,202 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,202 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,203 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,203 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,203 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,204 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,204 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,204 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,205 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,205 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,206 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,206 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,206 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,207 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,207 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,208 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,208 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,220 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,221 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,221 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,222 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,222 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,222 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,223 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,223 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,223 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,223 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,224 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,224 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled [2018-10-26 21:54:30,224 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,225 WARN L387 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled [2018-10-26 21:54:30,319 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 21:54:30,331 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 21:54:30,333 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 21:54:30,335 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 21:54:30,336 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 21:54:30,339 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 21:54:30,343 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 21:54:30,345 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 21:54:30,346 WARN L1239 BoogieBacktranslator]: unknown boogie variable platform_driver_probe_#in~82 [2018-10-26 21:54:30,387 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 26.10 09:54:30 ImpRootNode [2018-10-26 21:54:30,387 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2018-10-26 21:54:30,388 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-10-26 21:54:30,388 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-10-26 21:54:30,388 INFO L276 PluginConnector]: Witness Printer initialized [2018-10-26 21:54:30,391 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 09:51:01" (3/4) ... [2018-10-26 21:54:30,396 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-10-26 21:54:30,396 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-10-26 21:54:30,397 INFO L168 Benchmark]: Toolchain (without parser) took 216710.37 ms. Allocated memory was 1.0 GB in the beginning and 3.6 GB in the end (delta: 2.6 GB). Free memory was 949.1 MB in the beginning and 796.6 MB in the end (delta: 152.5 MB). Peak memory consumption was 2.7 GB. Max. memory is 11.5 GB. [2018-10-26 21:54:30,397 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 979.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 21:54:30,397 INFO L168 Benchmark]: CACSL2BoogieTranslator took 1340.72 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.3 MB). Free memory was 949.1 MB in the beginning and 1.1 GB in the end (delta: -130.8 MB). Peak memory consumption was 102.9 MB. Max. memory is 11.5 GB. [2018-10-26 21:54:30,398 INFO L168 Benchmark]: Boogie Procedure Inliner took 69.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.1 MB). Peak memory consumption was 6.1 MB. Max. memory is 11.5 GB. [2018-10-26 21:54:30,398 INFO L168 Benchmark]: Boogie Preprocessor took 54.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 11.5 GB. [2018-10-26 21:54:30,398 INFO L168 Benchmark]: RCFGBuilder took 6023.10 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 983.1 MB in the end (delta: 87.7 MB). Peak memory consumption was 194.5 MB. Max. memory is 11.5 GB. [2018-10-26 21:54:30,398 INFO L168 Benchmark]: CodeCheck took 209210.75 ms. Allocated memory was 1.2 GB in the beginning and 3.6 GB in the end (delta: 2.4 GB). Free memory was 983.1 MB in the beginning and 796.6 MB in the end (delta: 186.5 MB). Peak memory consumption was 2.6 GB. Max. memory is 11.5 GB. [2018-10-26 21:54:30,399 INFO L168 Benchmark]: Witness Printer took 8.25 ms. Allocated memory is still 3.6 GB. Free memory is still 796.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 21:54:30,406 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 20 procedures, 450 locations, 1 error locations. UNSAFE Result, 208.8s OverallTime, 289 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 127926272 SDtfs, -1266408768 SDslu, -819163392 SDs, 0 SdLazy, -237813096 SolverSat, 197918824 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1374.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 193708 GetRequests, 191767 SyntacticMatches, 381 SemanticMatches, 1560 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1335974 ImplicationChecksByTransitivity, 187.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, traceCheckStatistics: 0.5s SsaConstructionTime, 2.3s SatisfiabilityAnalysisTime, 12.8s InterpolantComputationTime, 13529 NumberOfCodeBlocks, 13529 NumberOfCodeBlocksAsserted, 289 NumberOfCheckSat, 13179 ConstructedInterpolants, 0 QuantifiedInterpolants, 1172331 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 288 InterpolantComputations, 252 PerfectInterpolantSequences, 3143/3278 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - UnprovableResult [Line: 1684]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2323, overapproximation of bitwiseAnd at line 1870. Possible FailurePath: [L1905] FCALL "write failed:retry count exceeded.\n" [L2072] FCALL "name\t\t: %s\n" [L2150] FCALL "Unable to allocate resources for device.\n" [L2159] FCALL "Unable to request mem region for device.\n" [L2175] FCALL "Unable to grab IOs for device.\n" [L2189] FCALL "info->tegra_rtc_lock" [L2211] FCALL "Unable to register device (err=%d).\n" [L2218] FCALL "rtc alarm" [L2220] FCALL "Unable to request interrupt for device (err=%d).\n" [L2226] FCALL "Tegra internal Real Time Clock\n" [L2323] EXPR, FCALL "tegra_rtc" [L1713] int ldv_irq_1_2 = 0; [L1714] int LDV_IN_INTERRUPT = 1; [L1715] int ldv_irq_1_3 = 0; [L1717] void *ldv_irq_data_1_1 ; [L1718] int ldv_irq_1_1 = 0; [L1719] int ldv_irq_1_0 = 0; [L1720] int ldv_irq_line_1_3 ; [L1721] void *ldv_irq_data_1_0 ; [L1722] int ldv_state_variable_0 ; [L1724] int ldv_state_variable_3 ; [L1725] int ldv_irq_line_1_0 ; [L1726] int ldv_state_variable_2 ; [L1727] void *ldv_irq_data_1_3 ; [L1728] int ref_cnt ; [L1729] int ldv_irq_line_1_1 ; [L1731] void *ldv_irq_data_1_2 ; [L1732] int ldv_state_variable_1 ; [L1733] int ldv_irq_line_1_2 ; [L2342] int ldv_retval_2 ; [L2343] int ldv_retval_0 ; [L2345] int ldv_retval_1 ; [L2943] int ldv_init = 0; [L1716] struct platform_device *tegra_rtc_driver_group0 ; [L1723] struct device *tegra_rtc_ops_group1 ; [L1730] struct rtc_time *tegra_rtc_ops_group0 ; [L1734] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2123-L2125] FCALL static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2322-L2323] FCALL static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2322-L2323] RET static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; [L2518] struct seq_file *ldvarg1 ; [L2519] void *tmp ; [L2520] unsigned int ldvarg0 ; [L2521] unsigned int tmp___0 ; [L2522] FCALL pm_message_t ldvarg2 ; [L2523] int tmp___1 ; [L2524] int tmp___2 ; [L2525] int tmp___3 ; [L2526] int tmp___4 ; VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] CALL, EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] EXPR ldv_zalloc(136U) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] tmp = ldv_zalloc(136U) [L2530] ldvarg1 = (struct seq_file *)tmp [L2531] tmp___0 = __VERIFIER_nondet_uint() [L2532] ldvarg0 = tmp___0 [L2533] FCALL ldv_initialize() [L2534] FCALL memset((void *)(& ldvarg2), 0, 4U) [L2535] ldv_state_variable_1 = 1 [L2536] ref_cnt = 0 [L2537] ldv_state_variable_0 = 1 [L2538] ldv_state_variable_3 = 0 [L2539] ldv_state_variable_2 = 0 VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2551] COND TRUE ldv_state_variable_0 != 0 [L2552] tmp___2 = __VERIFIER_nondet_int() [L2554] case 0: [L2563] case 1: VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2564] COND TRUE ldv_state_variable_0 == 1 [L2565] CALL, EXPR tegra_rtc_init() [L2326] int tmp ; [L2329] EXPR, FCALL platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2329] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2330] RET return (tmp); [L2565] EXPR tegra_rtc_init() [L2565] ldv_retval_0 = tegra_rtc_init() [L2566] COND TRUE ldv_retval_0 == 0 [L2567] ldv_state_variable_0 = 3 [L2568] ldv_state_variable_2 = 1 [L2569] CALL ldv_initialize_platform_driver_2() [L2476] void *tmp ; VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] CALL, EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] RET return (0); VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] EXPR ldv_zalloc(624U) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] tmp = ldv_zalloc(624U) [L2480] RET tegra_rtc_driver_group0 = (struct platform_device *)tmp [L2569] ldv_initialize_platform_driver_2() [L2573] COND FALSE !(ldv_retval_0 != 0) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=0, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: [L2717] case 1: [L2729] case 2: [L2752] case 3: [L2764] case 4: [L2765] COND TRUE ldv_state_variable_2 == 1 [L2766] FCALL ldv_probe_2() [L2767] ldv_state_variable_2 = 2 [L2768] ref_cnt = ref_cnt + 1 VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2704] COND FALSE !(ldv_state_variable_2 == 4) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2710] COND TRUE ldv_state_variable_2 == 2 VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, platform_driver_probe_#in~82={-1:11}, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2711] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2318] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, \old(enabled)=0, __this_module={76:58}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2006] struct tegra_rtc_info *info ; [L2007] void *tmp ; [L2008] unsigned int status ; [L2009] unsigned long sl_irq_flags ; [L2010] u32 __v ; [L2011] u32 __v___0 ; [L2014] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L2014] tmp = dev_get_drvdata((struct device const *)dev) [L2015] info = (struct tegra_rtc_info *)tmp VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, \old(enabled)=0, __this_module={76:58}, dev={0:12}, dev={0:12}, enabled=0, info={178:179}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={178:179}] [L2016] CALL tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1875] struct tegra_rtc_info *info ; [L1876] void *tmp ; [L1877] int retries ; [L1878] int tmp___0 ; [L1879] u32 tmp___1 ; [L1882] EXPR, FCALL dev_get_drvdata((struct device const *)dev) [L1882] tmp = dev_get_drvdata((struct device const *)dev) [L1883] info = (struct tegra_rtc_info *)tmp [L1884] retries = 500 VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] CALL, EXPR tegra_rtc_check_busy(info) [L1863] u32 __v ; [L1864] u32 __v___0 ; [L1867] EXPR, FCALL info->rtc_base [L1867] EXPR, FCALL (unsigned int volatile *)info->rtc_base + 4U [L1867] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1868] __v = __v___0 [L1870] RET return (__v & 1U); [L1896] EXPR tegra_rtc_check_busy(info) [L1896] tmp___1 = tegra_rtc_check_busy(info) [L1897] COND FALSE !(tmp___1 != 0U) [L1903] RET return (0); VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2016] tegra_rtc_wait_while_busy(dev) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, \old(enabled)=0, __this_module={76:58}, dev={0:12}, dev={0:12}, enabled=0, info={178:179}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={178:179}] [L2017] CALL ldv_spin_lock_check() VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2962] COND FALSE !(ldv_init == 1) VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2965] CALL ldv_error() VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1684] __VERIFIER_error() VAL ["info->tegra_rtc_lock"={27:0}, "name\t\t: %s\n"={20:0}, "rtc alarm"={29:0}, "Tegra internal Real Time Clock\n"={31:0}, "tegra_rtc"={34:0}, "Unable to allocate resources for device.\n"={22:0}, "Unable to grab IOs for device.\n"={26:0}, "Unable to register device (err=%d).\n"={28:0}, "Unable to request interrupt for device (err=%d).\n"={30:0}, "Unable to request mem region for device.\n"={23:0}, "write failed:retry count exceeded.\n"={18:0}, __this_module={76:58}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={155:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={35:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 979.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 1340.72 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 157.3 MB). Free memory was 949.1 MB in the beginning and 1.1 GB in the end (delta: -130.8 MB). Peak memory consumption was 102.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 69.38 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.1 MB). Peak memory consumption was 6.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 54.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 11.5 GB. * RCFGBuilder took 6023.10 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 983.1 MB in the end (delta: 87.7 MB). Peak memory consumption was 194.5 MB. Max. memory is 11.5 GB. * CodeCheck took 209210.75 ms. Allocated memory was 1.2 GB in the beginning and 3.6 GB in the end (delta: 2.4 GB). Free memory was 983.1 MB in the beginning and 796.6 MB in the end (delta: 186.5 MB). Peak memory consumption was 2.6 GB. Max. memory is 11.5 GB. * Witness Printer took 8.25 ms. Allocated memory is still 3.6 GB. Free memory is still 796.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#res : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.C_memset_#ptr : $Pointer$ not handled * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 - GenericResult: Unfinished Backtranslation unknown boogie variable platform_driver_probe_#in~82 RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [MP z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Forcibly destroying the process Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-1dbac8b [2018-10-26 21:54:32,485 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-26 21:54:32,486 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-26 21:54:32,496 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-26 21:54:32,496 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-26 21:54:32,497 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-26 21:54:32,498 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-26 21:54:32,499 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-26 21:54:32,501 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-26 21:54:32,502 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-26 21:54:32,503 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-26 21:54:32,503 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-26 21:54:32,504 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-26 21:54:32,505 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-26 21:54:32,506 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-26 21:54:32,507 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-26 21:54:32,507 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-26 21:54:32,509 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-26 21:54:32,511 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-26 21:54:32,512 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-26 21:54:32,513 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-26 21:54:32,514 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-26 21:54:32,516 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-26 21:54:32,516 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-26 21:54:32,517 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-26 21:54:32,517 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-26 21:54:32,518 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-26 21:54:32,519 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-26 21:54:32,519 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-26 21:54:32,521 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-26 21:54:32,521 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-26 21:54:32,522 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-26 21:54:32,522 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-26 21:54:32,522 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-26 21:54:32,523 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-26 21:54:32,523 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-26 21:54:32,524 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/config/svcomp-Reach-64bit-Kojak_Bitvector.epf [2018-10-26 21:54:32,545 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-26 21:54:32,546 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-26 21:54:32,546 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-26 21:54:32,546 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-10-26 21:54:32,547 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-26 21:54:32,547 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-26 21:54:32,547 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-26 21:54:32,547 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-26 21:54:32,548 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-26 21:54:32,548 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-26 21:54:32,548 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-26 21:54:32,548 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-10-26 21:54:32,552 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-10-26 21:54:32,552 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-26 21:54:32,552 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-26 21:54:32,552 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-10-26 21:54:32,553 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-10-26 21:54:32,553 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-26 21:54:32,553 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-26 21:54:32,553 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-26 21:54:32,553 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-26 21:54:32,553 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-26 21:54:32,553 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-26 21:54:32,554 INFO L133 SettingsManager]: * Use separate solver for trace checks=false [2018-10-26 21:54:32,554 INFO L133 SettingsManager]: * Trace refinement strategy=WALRUS [2018-10-26 21:54:32,554 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-26 21:54:32,554 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-10-26 21:54:32,554 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-10-26 21:54:32,554 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-10-26 21:54:32,554 INFO L133 SettingsManager]: * To the following directory=dump/ Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 [2018-10-26 21:54:32,605 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-26 21:54:32,617 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-26 21:54:32,619 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-26 21:54:32,619 INFO L271 PluginConnector]: Initializing CDTParser... [2018-10-26 21:54:32,620 INFO L276 PluginConnector]: CDTParser initialized [2018-10-26 21:54:32,620 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 21:54:32,664 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data/e768f80dc/7d8a1ada61404989823b4e7826329c5c/FLAG0b227c1e4 [2018-10-26 21:54:33,216 INFO L298 CDTParser]: Found 1 translation units. [2018-10-26 21:54:33,217 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-10-26 21:54:33,243 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data/e768f80dc/7d8a1ada61404989823b4e7826329c5c/FLAG0b227c1e4 [2018-10-26 21:54:33,258 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/data/e768f80dc/7d8a1ada61404989823b4e7826329c5c [2018-10-26 21:54:33,262 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-26 21:54:33,264 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-10-26 21:54:33,265 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-10-26 21:54:33,267 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-10-26 21:54:33,270 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-10-26 21:54:33,271 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 09:54:33" (1/1) ... [2018-10-26 21:54:33,273 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@24e27545 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:33, skipping insertion in model container [2018-10-26 21:54:33,274 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 09:54:33" (1/1) ... [2018-10-26 21:54:33,282 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-10-26 21:54:33,347 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-10-26 21:54:34,998 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 21:54:35,037 INFO L189 MainTranslator]: Completed pre-run [2018-10-26 21:54:35,930 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-10-26 21:54:36,013 INFO L193 MainTranslator]: Completed translation [2018-10-26 21:54:36,013 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36 WrapperNode [2018-10-26 21:54:36,014 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-10-26 21:54:36,014 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-26 21:54:36,015 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-26 21:54:36,015 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-26 21:54:36,023 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... [2018-10-26 21:54:36,060 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... [2018-10-26 21:54:36,109 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-26 21:54:36,109 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-26 21:54:36,109 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-26 21:54:36,109 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-26 21:54:36,118 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... [2018-10-26 21:54:36,118 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... [2018-10-26 21:54:36,127 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... [2018-10-26 21:54:36,131 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... [2018-10-26 21:54:36,155 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... [2018-10-26 21:54:36,163 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... [2018-10-26 21:54:36,169 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... [2018-10-26 21:54:36,184 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-26 21:54:36,184 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-26 21:54:36,184 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-26 21:54:36,188 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-26 21:54:36,189 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 09:54:36" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9da554db-6009-4e0c-828a-8d99443537d7/bin-2019/ukojak/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-26 21:54:36,254 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-10-26 21:54:36,254 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1 [2018-10-26 21:54:36,255 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE8 [2018-10-26 21:54:36,255 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-10-26 21:54:36,255 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE4 [2018-10-26 21:54:36,255 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-10-26 21:54:36,255 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-10-26 21:54:36,255 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-10-26 21:54:36,255 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-10-26 21:54:36,255 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-10-26 21:54:36,256 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-10-26 21:54:36,256 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-10-26 21:54:36,256 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-10-26 21:54:36,256 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-10-26 21:54:36,258 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-10-26 21:54:36,258 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-10-26 21:54:36,258 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-10-26 21:54:36,258 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-10-26 21:54:36,259 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-10-26 21:54:36,259 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-10-26 21:54:36,259 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-10-26 21:54:36,259 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-10-26 21:54:36,260 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-10-26 21:54:36,260 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-10-26 21:54:36,260 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-10-26 21:54:36,260 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-10-26 21:54:36,260 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-10-26 21:54:36,260 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-10-26 21:54:36,260 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-10-26 21:54:36,260 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-10-26 21:54:36,260 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-10-26 21:54:36,261 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-10-26 21:54:36,261 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-10-26 21:54:36,261 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-10-26 21:54:36,261 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-10-26 21:54:36,261 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-10-26 21:54:36,261 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-10-26 21:54:36,261 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-10-26 21:54:36,261 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE8 [2018-10-26 21:54:36,261 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-10-26 21:54:36,262 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1 [2018-10-26 21:54:36,262 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-10-26 21:54:36,262 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-10-26 21:54:36,262 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-10-26 21:54:36,262 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE4 [2018-10-26 21:54:36,262 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-10-26 21:54:36,262 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-10-26 21:54:36,262 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-10-26 21:54:36,262 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-10-26 21:54:36,262 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-10-26 21:54:36,263 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-10-26 21:54:36,263 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-10-26 21:54:36,263 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-10-26 21:54:36,263 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-10-26 21:54:36,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-10-26 21:54:36,263 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-10-26 21:54:36,263 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-10-26 21:54:36,263 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-26 21:54:36,263 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-26 21:56:21,110 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-26 21:56:21,110 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 09:56:21 BoogieIcfgContainer [2018-10-26 21:56:21,110 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-26 21:56:21,111 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-10-26 21:56:21,111 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-10-26 21:56:21,119 INFO L276 PluginConnector]: CodeCheck initialized [2018-10-26 21:56:21,120 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 09:56:21" (1/1) ... [2018-10-26 21:56:21,128 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-10-26 21:56:21,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-26 21:56:21,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 222 states and 316 transitions. [2018-10-26 21:56:21,168 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 316 transitions. [2018-10-26 21:56:21,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-10-26 21:56:21,175 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-26 21:56:21,217 FATAL L292 ToolchainWalker]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck has thrown an exception: java.lang.IllegalArgumentException: Indexed Sort BitVec undefined at de.uni_freiburg.informatik.ultimate.logic.SortSymbol.checkArity(SortSymbol.java:153) at de.uni_freiburg.informatik.ultimate.logic.SortSymbol.getSort(SortSymbol.java:177) at de.uni_freiburg.informatik.ultimate.logic.Theory.getSort(Theory.java:1243) at de.uni_freiburg.informatik.ultimate.logic.NoopScript.sort(NoopScript.java:287) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.TermTransferrer.transferSort(TermTransferrer.java:147) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.TermTransferrer.convertApplicationTerm(TermTransferrer.java:177) at de.uni_freiburg.informatik.ultimate.logic.TermTransformer$BuildApplicationTerm.walk(TermTransformer.java:320) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.logic.TermTransformer.transform(TermTransformer.java:253) at de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck.CodeCheckObserver.process(CodeCheckObserver.java:452) at de.uni_freiburg.informatik.ultimate.core.coreplugin.modelwalker.CFGWalker.runObserver(CFGWalker.java:57) at de.uni_freiburg.informatik.ultimate.core.coreplugin.modelwalker.BaseWalker.runObserver(BaseWalker.java:93) at de.uni_freiburg.informatik.ultimate.core.coreplugin.modelwalker.BaseWalker.run(BaseWalker.java:86) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:167) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-10-26 21:56:21,219 INFO L168 Benchmark]: Toolchain (without parser) took 107956.30 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 385.4 MB). Free memory was 946.5 MB in the beginning and 944.0 MB in the end (delta: 2.6 MB). Peak memory consumption was 387.9 MB. Max. memory is 11.5 GB. [2018-10-26 21:56:21,221 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 978.8 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 21:56:21,221 INFO L168 Benchmark]: CACSL2BoogieTranslator took 2749.25 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 385.4 MB). Free memory was 946.5 MB in the beginning and 1.3 GB in the end (delta: -397.8 MB). Peak memory consumption was 447.9 MB. Max. memory is 11.5 GB. [2018-10-26 21:56:21,222 INFO L168 Benchmark]: Boogie Procedure Inliner took 94.54 ms. Allocated memory is still 1.4 GB. Free memory is still 1.3 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-10-26 21:56:21,222 INFO L168 Benchmark]: Boogie Preprocessor took 74.53 ms. Allocated memory is still 1.4 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 13.3 MB). Peak memory consumption was 13.3 MB. Max. memory is 11.5 GB. [2018-10-26 21:56:21,223 INFO L168 Benchmark]: RCFGBuilder took 104926.50 ms. Allocated memory is still 1.4 GB. Free memory was 1.3 GB in the beginning and 957.2 MB in the end (delta: 373.9 MB). Peak memory consumption was 373.9 MB. Max. memory is 11.5 GB. [2018-10-26 21:56:21,223 INFO L168 Benchmark]: CodeCheck took 108.05 ms. Allocated memory is still 1.4 GB. Free memory was 957.2 MB in the beginning and 944.0 MB in the end (delta: 13.3 MB). Peak memory consumption was 13.3 MB. Max. memory is 11.5 GB. [2018-10-26 21:56:21,226 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - ExceptionOrErrorResult: IllegalArgumentException: Indexed Sort BitVec undefined de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: IllegalArgumentException: Indexed Sort BitVec undefined: de.uni_freiburg.informatik.ultimate.logic.SortSymbol.checkArity(SortSymbol.java:153) * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 978.8 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 2749.25 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 385.4 MB). Free memory was 946.5 MB in the beginning and 1.3 GB in the end (delta: -397.8 MB). Peak memory consumption was 447.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 94.54 ms. Allocated memory is still 1.4 GB. Free memory is still 1.3 GB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 74.53 ms. Allocated memory is still 1.4 GB. Free memory was 1.3 GB in the beginning and 1.3 GB in the end (delta: 13.3 MB). Peak memory consumption was 13.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 104926.50 ms. Allocated memory is still 1.4 GB. Free memory was 1.3 GB in the beginning and 957.2 MB in the end (delta: 373.9 MB). Peak memory consumption was 373.9 MB. Max. memory is 11.5 GB. * CodeCheck took 108.05 ms. Allocated memory is still 1.4 GB. Free memory was 957.2 MB in the beginning and 944.0 MB in the end (delta: 13.3 MB). Peak memory consumption was 13.3 MB. Max. memory is 11.5 GB. RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...