./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/transmitter.15_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0e3598d1a4e9129bf22e72269576449e67f0febd ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 02:01:04,904 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 02:01:04,906 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 02:01:04,912 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 02:01:04,913 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 02:01:04,914 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 02:01:04,915 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 02:01:04,916 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 02:01:04,917 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 02:01:04,918 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 02:01:04,918 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 02:01:04,918 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 02:01:04,919 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 02:01:04,920 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 02:01:04,921 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 02:01:04,921 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 02:01:04,922 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 02:01:04,923 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 02:01:04,925 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 02:01:04,926 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 02:01:04,927 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 02:01:04,928 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 02:01:04,929 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 02:01:04,930 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 02:01:04,930 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 02:01:04,931 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 02:01:04,931 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 02:01:04,932 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 02:01:04,933 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 02:01:04,933 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 02:01:04,934 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 02:01:04,934 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 02:01:04,934 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 02:01:04,934 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 02:01:04,935 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 02:01:04,936 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 02:01:04,936 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf [2018-11-10 02:01:04,945 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 02:01:04,945 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 02:01:04,946 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-10 02:01:04,946 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-10 02:01:04,946 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 02:01:04,946 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 02:01:04,947 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 02:01:04,947 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 02:01:04,947 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 02:01:04,947 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 02:01:04,947 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 02:01:04,947 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-10 02:01:04,948 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-10 02:01:04,948 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-10 02:01:04,948 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 02:01:04,948 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 02:01:04,948 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-10 02:01:04,948 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-11-10 02:01:04,949 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-11-10 02:01:04,949 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 02:01:04,949 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-10 02:01:04,949 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-10 02:01:04,949 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 02:01:04,949 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-10 02:01:04,950 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-10 02:01:04,950 INFO L133 SettingsManager]: * Trace refinement strategy=PENGUIN [2018-11-10 02:01:04,950 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-10 02:01:04,950 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-10 02:01:04,950 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0e3598d1a4e9129bf22e72269576449e67f0febd [2018-11-10 02:01:04,974 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 02:01:04,984 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 02:01:04,987 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 02:01:04,988 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 02:01:04,988 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 02:01:04,989 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/../../sv-benchmarks/c/systemc/transmitter.15_false-unreach-call_false-termination.cil.c [2018-11-10 02:01:05,034 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/data/4885b8432/0a0f96dc83dd4ee09a8e689d8d7b7be1/FLAG3e313f051 [2018-11-10 02:01:05,404 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 02:01:05,404 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/sv-benchmarks/c/systemc/transmitter.15_false-unreach-call_false-termination.cil.c [2018-11-10 02:01:05,417 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/data/4885b8432/0a0f96dc83dd4ee09a8e689d8d7b7be1/FLAG3e313f051 [2018-11-10 02:01:05,430 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/data/4885b8432/0a0f96dc83dd4ee09a8e689d8d7b7be1 [2018-11-10 02:01:05,433 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 02:01:05,434 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 02:01:05,435 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 02:01:05,435 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 02:01:05,438 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 02:01:05,439 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,441 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@65b664f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05, skipping insertion in model container [2018-11-10 02:01:05,441 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,449 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 02:01:05,483 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 02:01:05,688 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 02:01:05,694 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 02:01:05,757 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 02:01:05,776 INFO L193 MainTranslator]: Completed translation [2018-11-10 02:01:05,776 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05 WrapperNode [2018-11-10 02:01:05,776 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 02:01:05,777 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 02:01:05,777 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 02:01:05,777 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 02:01:05,784 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,794 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,884 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 02:01:05,884 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 02:01:05,884 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 02:01:05,884 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 02:01:05,894 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,894 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,897 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,897 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,907 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,921 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,924 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... [2018-11-10 02:01:05,929 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 02:01:05,929 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 02:01:05,929 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 02:01:05,930 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 02:01:05,930 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 02:01:05" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-10 02:01:05,991 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-10 02:01:05,992 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-10 02:01:05,992 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-10 02:01:05,992 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-10 02:01:05,992 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-10 02:01:05,993 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-10 02:01:05,993 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-10 02:01:05,993 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-10 02:01:05,993 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-10 02:01:05,993 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-10 02:01:05,993 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-10 02:01:05,993 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-10 02:01:05,994 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 02:01:05,994 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 02:01:07,890 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 02:01:07,891 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 02:01:07 BoogieIcfgContainer [2018-11-10 02:01:07,891 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 02:01:07,892 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-11-10 02:01:07,892 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-11-10 02:01:07,900 INFO L276 PluginConnector]: CodeCheck initialized [2018-11-10 02:01:07,901 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 02:01:07" (1/1) ... [2018-11-10 02:01:07,909 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 02:01:07,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:07,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 197 states and 307 transitions. [2018-11-10 02:01:07,980 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 307 transitions. [2018-11-10 02:01:07,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:07,987 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:08,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:08,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:08,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:08,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 238 states and 385 transitions. [2018-11-10 02:01:08,746 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 385 transitions. [2018-11-10 02:01:08,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:08,748 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:08,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:08,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:09,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:09,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 239 states and 385 transitions. [2018-11-10 02:01:09,123 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 385 transitions. [2018-11-10 02:01:09,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:09,125 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:09,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:09,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:09,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:09,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 240 states and 385 transitions. [2018-11-10 02:01:09,615 INFO L276 IsEmpty]: Start isEmpty. Operand 240 states and 385 transitions. [2018-11-10 02:01:09,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:09,618 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:09,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:09,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:10,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:10,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 241 states and 385 transitions. [2018-11-10 02:01:10,023 INFO L276 IsEmpty]: Start isEmpty. Operand 241 states and 385 transitions. [2018-11-10 02:01:10,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:10,028 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:10,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:10,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:10,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:10,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 242 states and 385 transitions. [2018-11-10 02:01:10,423 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 385 transitions. [2018-11-10 02:01:10,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:10,428 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:10,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:10,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:10,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:10,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 243 states and 385 transitions. [2018-11-10 02:01:10,779 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 385 transitions. [2018-11-10 02:01:10,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:10,780 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:10,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:10,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:11,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:11,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 244 states and 385 transitions. [2018-11-10 02:01:11,106 INFO L276 IsEmpty]: Start isEmpty. Operand 244 states and 385 transitions. [2018-11-10 02:01:11,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:11,106 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:11,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:11,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:11,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:11,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 245 states and 385 transitions. [2018-11-10 02:01:11,537 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 385 transitions. [2018-11-10 02:01:11,538 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:11,538 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:11,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:11,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:11,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:11,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 246 states and 385 transitions. [2018-11-10 02:01:11,920 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 385 transitions. [2018-11-10 02:01:11,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:11,921 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:11,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:11,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:12,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:12,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 247 states and 385 transitions. [2018-11-10 02:01:12,349 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 385 transitions. [2018-11-10 02:01:12,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:12,350 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:12,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:12,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:12,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:12,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 248 states and 385 transitions. [2018-11-10 02:01:12,803 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 385 transitions. [2018-11-10 02:01:12,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:12,804 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:12,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:12,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:13,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:13,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 249 states and 385 transitions. [2018-11-10 02:01:13,222 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 385 transitions. [2018-11-10 02:01:13,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:13,222 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:13,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:13,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:13,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:13,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 250 states and 385 transitions. [2018-11-10 02:01:13,601 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 385 transitions. [2018-11-10 02:01:13,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:13,602 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:13,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:13,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:14,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:14,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 251 states and 385 transitions. [2018-11-10 02:01:14,034 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 385 transitions. [2018-11-10 02:01:14,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:14,035 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:14,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:14,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:14,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:14,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 286 states and 456 transitions. [2018-11-10 02:01:14,569 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 456 transitions. [2018-11-10 02:01:14,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:14,570 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:14,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:14,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:14,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:14,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 287 states and 456 transitions. [2018-11-10 02:01:14,894 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 456 transitions. [2018-11-10 02:01:14,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:14,894 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:14,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:14,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:15,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:15,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 288 states and 456 transitions. [2018-11-10 02:01:15,198 INFO L276 IsEmpty]: Start isEmpty. Operand 288 states and 456 transitions. [2018-11-10 02:01:15,199 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:15,199 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:15,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:15,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:15,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:15,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 289 states and 456 transitions. [2018-11-10 02:01:15,459 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 456 transitions. [2018-11-10 02:01:15,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:15,460 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:15,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:15,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:15,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:15,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 290 states and 456 transitions. [2018-11-10 02:01:15,769 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 456 transitions. [2018-11-10 02:01:15,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:15,770 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:15,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:15,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:16,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:16,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 291 states and 456 transitions. [2018-11-10 02:01:16,068 INFO L276 IsEmpty]: Start isEmpty. Operand 291 states and 456 transitions. [2018-11-10 02:01:16,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:16,069 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:16,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:16,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:16,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:16,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 292 states and 456 transitions. [2018-11-10 02:01:16,314 INFO L276 IsEmpty]: Start isEmpty. Operand 292 states and 456 transitions. [2018-11-10 02:01:16,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:16,315 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:16,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:16,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:16,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:16,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 293 states and 456 transitions. [2018-11-10 02:01:16,513 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states and 456 transitions. [2018-11-10 02:01:16,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:16,513 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:16,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:16,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:16,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:16,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 294 states and 456 transitions. [2018-11-10 02:01:16,701 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 456 transitions. [2018-11-10 02:01:16,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:16,701 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:16,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:16,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:16,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:16,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 295 states and 456 transitions. [2018-11-10 02:01:16,881 INFO L276 IsEmpty]: Start isEmpty. Operand 295 states and 456 transitions. [2018-11-10 02:01:16,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:16,882 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:16,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:16,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:17,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:17,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 296 states and 456 transitions. [2018-11-10 02:01:17,114 INFO L276 IsEmpty]: Start isEmpty. Operand 296 states and 456 transitions. [2018-11-10 02:01:17,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:17,114 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:17,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:17,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:17,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:17,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 297 states and 456 transitions. [2018-11-10 02:01:17,281 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 456 transitions. [2018-11-10 02:01:17,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:17,282 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:17,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:17,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:17,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:17,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 326 states and 515 transitions. [2018-11-10 02:01:17,560 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 515 transitions. [2018-11-10 02:01:17,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:17,561 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:17,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:17,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:17,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:17,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 327 states and 515 transitions. [2018-11-10 02:01:17,800 INFO L276 IsEmpty]: Start isEmpty. Operand 327 states and 515 transitions. [2018-11-10 02:01:17,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:17,800 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:17,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:17,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:18,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:18,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 328 states and 515 transitions. [2018-11-10 02:01:18,029 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 515 transitions. [2018-11-10 02:01:18,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:18,029 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:18,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:18,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:18,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:18,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 329 states and 515 transitions. [2018-11-10 02:01:18,245 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 515 transitions. [2018-11-10 02:01:18,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:18,246 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:18,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:18,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:18,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:18,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 330 states and 515 transitions. [2018-11-10 02:01:18,477 INFO L276 IsEmpty]: Start isEmpty. Operand 330 states and 515 transitions. [2018-11-10 02:01:18,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:18,478 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:18,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:18,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:18,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:18,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 331 states and 515 transitions. [2018-11-10 02:01:18,717 INFO L276 IsEmpty]: Start isEmpty. Operand 331 states and 515 transitions. [2018-11-10 02:01:18,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:18,718 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:18,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:18,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:18,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:18,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 332 states and 515 transitions. [2018-11-10 02:01:18,972 INFO L276 IsEmpty]: Start isEmpty. Operand 332 states and 515 transitions. [2018-11-10 02:01:18,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:18,973 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:18,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:18,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:19,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:19,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 333 states and 515 transitions. [2018-11-10 02:01:19,190 INFO L276 IsEmpty]: Start isEmpty. Operand 333 states and 515 transitions. [2018-11-10 02:01:19,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:19,190 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:19,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:19,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:19,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:19,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 334 states and 515 transitions. [2018-11-10 02:01:19,413 INFO L276 IsEmpty]: Start isEmpty. Operand 334 states and 515 transitions. [2018-11-10 02:01:19,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:19,413 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:19,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:19,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:19,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:19,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 335 states and 515 transitions. [2018-11-10 02:01:19,642 INFO L276 IsEmpty]: Start isEmpty. Operand 335 states and 515 transitions. [2018-11-10 02:01:19,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:19,643 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:19,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:19,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:20,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:20,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 361 states and 568 transitions. [2018-11-10 02:01:20,009 INFO L276 IsEmpty]: Start isEmpty. Operand 361 states and 568 transitions. [2018-11-10 02:01:20,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:20,010 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:20,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:20,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:20,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:20,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 362 states and 568 transitions. [2018-11-10 02:01:20,276 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 568 transitions. [2018-11-10 02:01:20,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:20,277 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:20,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:20,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:20,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:20,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 363 states and 568 transitions. [2018-11-10 02:01:20,520 INFO L276 IsEmpty]: Start isEmpty. Operand 363 states and 568 transitions. [2018-11-10 02:01:20,521 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:20,521 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:20,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:20,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:20,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:20,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 364 states and 568 transitions. [2018-11-10 02:01:20,768 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 568 transitions. [2018-11-10 02:01:20,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:20,768 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:20,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:20,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:21,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:21,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 365 states and 568 transitions. [2018-11-10 02:01:21,028 INFO L276 IsEmpty]: Start isEmpty. Operand 365 states and 568 transitions. [2018-11-10 02:01:21,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:21,028 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:21,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:21,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:21,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:21,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 366 states and 568 transitions. [2018-11-10 02:01:21,297 INFO L276 IsEmpty]: Start isEmpty. Operand 366 states and 568 transitions. [2018-11-10 02:01:21,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:21,297 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:21,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:21,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:21,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:21,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 367 states and 568 transitions. [2018-11-10 02:01:21,553 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 568 transitions. [2018-11-10 02:01:21,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:21,554 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:21,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:21,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:21,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:21,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 368 states and 568 transitions. [2018-11-10 02:01:21,841 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 568 transitions. [2018-11-10 02:01:21,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:21,841 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:21,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:21,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:22,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:22,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 369 states and 568 transitions. [2018-11-10 02:01:22,132 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 568 transitions. [2018-11-10 02:01:22,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:22,132 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:22,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:22,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:22,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:22,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 639 states to 389 states and 609 transitions. [2018-11-10 02:01:22,464 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 609 transitions. [2018-11-10 02:01:22,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:22,464 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:22,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:22,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:22,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:22,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 639 states to 390 states and 609 transitions. [2018-11-10 02:01:22,719 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 609 transitions. [2018-11-10 02:01:22,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:22,720 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:22,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:22,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:22,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:23,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 639 states to 391 states and 609 transitions. [2018-11-10 02:01:23,000 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 609 transitions. [2018-11-10 02:01:23,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:23,000 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:23,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:23,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:23,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:23,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 639 states to 392 states and 609 transitions. [2018-11-10 02:01:23,254 INFO L276 IsEmpty]: Start isEmpty. Operand 392 states and 609 transitions. [2018-11-10 02:01:23,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:23,255 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:23,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:23,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:23,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:23,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 639 states to 393 states and 609 transitions. [2018-11-10 02:01:23,510 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 609 transitions. [2018-11-10 02:01:23,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:23,510 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:23,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:23,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:23,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:23,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 639 states to 394 states and 609 transitions. [2018-11-10 02:01:23,763 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 609 transitions. [2018-11-10 02:01:23,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:23,764 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:23,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:23,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:24,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:24,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 639 states to 395 states and 609 transitions. [2018-11-10 02:01:24,045 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 609 transitions. [2018-11-10 02:01:24,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:24,045 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:24,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:24,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:24,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:24,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 409 states and 638 transitions. [2018-11-10 02:01:24,403 INFO L276 IsEmpty]: Start isEmpty. Operand 409 states and 638 transitions. [2018-11-10 02:01:24,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:24,403 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:24,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:24,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:24,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:24,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 410 states and 638 transitions. [2018-11-10 02:01:24,669 INFO L276 IsEmpty]: Start isEmpty. Operand 410 states and 638 transitions. [2018-11-10 02:01:24,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:24,669 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:24,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:24,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:24,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:24,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 411 states and 638 transitions. [2018-11-10 02:01:24,930 INFO L276 IsEmpty]: Start isEmpty. Operand 411 states and 638 transitions. [2018-11-10 02:01:24,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:24,930 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:24,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:24,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:25,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:25,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 412 states and 638 transitions. [2018-11-10 02:01:25,181 INFO L276 IsEmpty]: Start isEmpty. Operand 412 states and 638 transitions. [2018-11-10 02:01:25,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:25,182 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:25,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:25,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:25,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:25,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 413 states and 638 transitions. [2018-11-10 02:01:25,433 INFO L276 IsEmpty]: Start isEmpty. Operand 413 states and 638 transitions. [2018-11-10 02:01:25,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:25,433 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:25,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:25,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:25,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:25,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 697 states to 421 states and 655 transitions. [2018-11-10 02:01:25,780 INFO L276 IsEmpty]: Start isEmpty. Operand 421 states and 655 transitions. [2018-11-10 02:01:25,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:25,781 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:25,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:25,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:26,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:26,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 697 states to 422 states and 655 transitions. [2018-11-10 02:01:26,001 INFO L276 IsEmpty]: Start isEmpty. Operand 422 states and 655 transitions. [2018-11-10 02:01:26,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:26,002 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:26,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:26,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:26,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:26,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 697 states to 423 states and 655 transitions. [2018-11-10 02:01:26,224 INFO L276 IsEmpty]: Start isEmpty. Operand 423 states and 655 transitions. [2018-11-10 02:01:26,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:26,225 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:26,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:26,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:26,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:26,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 708 states to 425 states and 660 transitions. [2018-11-10 02:01:26,513 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 660 transitions. [2018-11-10 02:01:26,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:26,513 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:26,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:26,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:28,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:28,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 824 states to 476 states and 760 transitions. [2018-11-10 02:01:28,049 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 760 transitions. [2018-11-10 02:01:28,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:28,050 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:28,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:28,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:29,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:29,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 843 states to 481 states and 771 transitions. [2018-11-10 02:01:29,163 INFO L276 IsEmpty]: Start isEmpty. Operand 481 states and 771 transitions. [2018-11-10 02:01:29,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:29,164 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:29,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:29,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:31,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:31,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 874 states to 492 states and 794 transitions. [2018-11-10 02:01:31,055 INFO L276 IsEmpty]: Start isEmpty. Operand 492 states and 794 transitions. [2018-11-10 02:01:31,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:31,056 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:31,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:31,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:33,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:33,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 917 states to 509 states and 829 transitions. [2018-11-10 02:01:33,947 INFO L276 IsEmpty]: Start isEmpty. Operand 509 states and 829 transitions. [2018-11-10 02:01:33,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:33,948 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:33,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:34,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:38,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:38,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 972 states to 532 states and 876 transitions. [2018-11-10 02:01:38,243 INFO L276 IsEmpty]: Start isEmpty. Operand 532 states and 876 transitions. [2018-11-10 02:01:38,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:38,244 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:38,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:38,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:44,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:44,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1045 states to 564 states and 941 transitions. [2018-11-10 02:01:44,997 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 941 transitions. [2018-11-10 02:01:44,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-10 02:01:44,998 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:45,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:45,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:54,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:54,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1130 states to 602 states and 1018 transitions. [2018-11-10 02:01:54,396 INFO L276 IsEmpty]: Start isEmpty. Operand 602 states and 1018 transitions. [2018-11-10 02:01:54,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 02:01:54,396 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:54,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:54,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:54,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:54,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1125 states to 600 states and 1013 transitions. [2018-11-10 02:01:54,591 INFO L276 IsEmpty]: Start isEmpty. Operand 600 states and 1013 transitions. [2018-11-10 02:01:54,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 02:01:54,592 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:54,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:54,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:54,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:54,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1126 states to 601 states and 1014 transitions. [2018-11-10 02:01:54,872 INFO L276 IsEmpty]: Start isEmpty. Operand 601 states and 1014 transitions. [2018-11-10 02:01:54,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 02:01:54,872 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:54,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:54,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:55,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:55,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1127 states to 602 states and 1015 transitions. [2018-11-10 02:01:55,299 INFO L276 IsEmpty]: Start isEmpty. Operand 602 states and 1015 transitions. [2018-11-10 02:01:55,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 02:01:55,299 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:55,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:55,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:55,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:55,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1128 states to 603 states and 1016 transitions. [2018-11-10 02:01:55,713 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 1016 transitions. [2018-11-10 02:01:55,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 02:01:55,714 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:55,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:55,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:56,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:56,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 604 states and 1017 transitions. [2018-11-10 02:01:56,133 INFO L276 IsEmpty]: Start isEmpty. Operand 604 states and 1017 transitions. [2018-11-10 02:01:56,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 02:01:56,133 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:56,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:56,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:56,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:56,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1130 states to 605 states and 1018 transitions. [2018-11-10 02:01:56,556 INFO L276 IsEmpty]: Start isEmpty. Operand 605 states and 1018 transitions. [2018-11-10 02:01:56,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 02:01:56,557 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:56,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:56,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:56,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:56,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1131 states to 606 states and 1019 transitions. [2018-11-10 02:01:56,934 INFO L276 IsEmpty]: Start isEmpty. Operand 606 states and 1019 transitions. [2018-11-10 02:01:56,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 02:01:56,935 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:56,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 02:01:56,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 02:01:57,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 02:01:57,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1132 states to 607 states and 1020 transitions. [2018-11-10 02:01:57,282 INFO L276 IsEmpty]: Start isEmpty. Operand 607 states and 1020 transitions. [2018-11-10 02:01:57,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-10 02:01:57,282 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 02:01:57,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 02:01:57,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 02:01:57,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 02:01:57,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 02:01:57,628 WARN L496 CodeCheckObserver]: This program is UNSAFE, Check terminated with 77 iterations. [2018-11-10 02:01:57,748 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 10.11 02:01:57 ImpRootNode [2018-11-10 02:01:57,748 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2018-11-10 02:01:57,749 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 02:01:57,749 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 02:01:57,749 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 02:01:57,749 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 02:01:07" (3/4) ... [2018-11-10 02:01:57,751 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-10 02:01:57,875 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_2b2c1a6e-1f4a-4844-89b5-4abaa6528430/bin-2019/ukojak/witness.graphml [2018-11-10 02:01:57,875 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 02:01:57,876 INFO L168 Benchmark]: Toolchain (without parser) took 52442.44 ms. Allocated memory was 1.0 GB in the beginning and 2.1 GB in the end (delta: 1.0 GB). Free memory was 959.1 MB in the beginning and 1.5 GB in the end (delta: -549.6 MB). Peak memory consumption was 498.4 MB. Max. memory is 11.5 GB. [2018-11-10 02:01:57,877 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 02:01:57,877 INFO L168 Benchmark]: CACSL2BoogieTranslator took 341.75 ms. Allocated memory is still 1.0 GB. Free memory was 956.5 MB in the beginning and 929.5 MB in the end (delta: 26.9 MB). Peak memory consumption was 26.9 MB. Max. memory is 11.5 GB. [2018-11-10 02:01:57,877 INFO L168 Benchmark]: Boogie Procedure Inliner took 107.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 152.6 MB). Free memory was 929.5 MB in the beginning and 1.1 GB in the end (delta: -216.1 MB). Peak memory consumption was 19.6 MB. Max. memory is 11.5 GB. [2018-11-10 02:01:57,877 INFO L168 Benchmark]: Boogie Preprocessor took 44.92 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.5 MB). Peak memory consumption was 3.5 MB. Max. memory is 11.5 GB. [2018-11-10 02:01:57,878 INFO L168 Benchmark]: RCFGBuilder took 1961.99 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 813.7 MB in the end (delta: 328.4 MB). Peak memory consumption was 328.4 MB. Max. memory is 11.5 GB. [2018-11-10 02:01:57,878 INFO L168 Benchmark]: CodeCheck took 49856.27 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 895.5 MB). Free memory was 813.7 MB in the beginning and 1.5 GB in the end (delta: -719.4 MB). Peak memory consumption was 176.0 MB. Max. memory is 11.5 GB. [2018-11-10 02:01:57,878 INFO L168 Benchmark]: Witness Printer took 126.48 ms. Allocated memory is still 2.1 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 24.4 MB). Peak memory consumption was 24.4 MB. Max. memory is 11.5 GB. [2018-11-10 02:01:57,880 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 419 locations, 1 error locations. UNSAFE Result, 49.7s OverallTime, 77 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 244706304 SDtfs, 412445688 SDslu, 1412171768 SDs, 0 SdLazy, 211493372 SolverSat, 140078592 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 10.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 47599 GetRequests, 38077 SyntacticMatches, 9150 SemanticMatches, 372 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 227172 ImplicationChecksByTransitivity, 45.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, traceCheckStatistics: 0.2s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 2.3s InterpolantComputationTime, 5322 NumberOfCodeBlocks, 5322 NumberOfCodeBlocksAsserted, 77 NumberOfCheckSat, 5176 ConstructedInterpolants, 0 QuantifiedInterpolants, 703166 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 76 InterpolantComputations, 76 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int t9_pc = 0; [L25] int t10_pc = 0; [L26] int t11_pc = 0; [L27] int t12_pc = 0; [L28] int t13_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int t5_st ; [L35] int t6_st ; [L36] int t7_st ; [L37] int t8_st ; [L38] int t9_st ; [L39] int t10_st ; [L40] int t11_st ; [L41] int t12_st ; [L42] int t13_st ; [L43] int m_i ; [L44] int t1_i ; [L45] int t2_i ; [L46] int t3_i ; [L47] int t4_i ; [L48] int t5_i ; [L49] int t6_i ; [L50] int t7_i ; [L51] int t8_i ; [L52] int t9_i ; [L53] int t10_i ; [L54] int t11_i ; [L55] int t12_i ; [L56] int t13_i ; [L57] int M_E = 2; [L58] int T1_E = 2; [L59] int T2_E = 2; [L60] int T3_E = 2; [L61] int T4_E = 2; [L62] int T5_E = 2; [L63] int T6_E = 2; [L64] int T7_E = 2; [L65] int T8_E = 2; [L66] int T9_E = 2; [L67] int T10_E = 2; [L68] int T11_E = 2; [L69] int T12_E = 2; [L70] int T13_E = 2; [L71] int E_1 = 2; [L72] int E_2 = 2; [L73] int E_3 = 2; [L74] int E_4 = 2; [L75] int E_5 = 2; [L76] int E_6 = 2; [L77] int E_7 = 2; [L78] int E_8 = 2; [L79] int E_9 = 2; [L80] int E_10 = 2; [L81] int E_11 = 2; [L82] int E_12 = 2; [L83] int E_13 = 2; [L1927] int __retres1 ; [L1931] CALL init_model() [L1830] m_i = 1 [L1831] t1_i = 1 [L1832] t2_i = 1 [L1833] t3_i = 1 [L1834] t4_i = 1 [L1835] t5_i = 1 [L1836] t6_i = 1 [L1837] t7_i = 1 [L1838] t8_i = 1 [L1839] t9_i = 1 [L1840] t10_i = 1 [L1841] t11_i = 1 [L1842] t12_i = 1 [L1843] RET t13_i = 1 [L1931] init_model() [L1932] CALL start_simulation() [L1868] int kernel_st ; [L1869] int tmp ; [L1870] int tmp___0 ; [L1874] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1875] FCALL update_channels() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1876] CALL init_threads() [L871] COND TRUE m_i == 1 [L872] m_st = 0 [L876] COND TRUE t1_i == 1 [L877] t1_st = 0 [L881] COND TRUE t2_i == 1 [L882] t2_st = 0 [L886] COND TRUE t3_i == 1 [L887] t3_st = 0 [L891] COND TRUE t4_i == 1 [L892] t4_st = 0 [L896] COND TRUE t5_i == 1 [L897] t5_st = 0 [L901] COND TRUE t6_i == 1 [L902] t6_st = 0 [L906] COND TRUE t7_i == 1 [L907] t7_st = 0 [L911] COND TRUE t8_i == 1 [L912] t8_st = 0 [L916] COND TRUE t9_i == 1 [L917] t9_st = 0 [L921] COND TRUE t10_i == 1 [L922] t10_st = 0 [L926] COND TRUE t11_i == 1 [L927] t11_st = 0 [L931] COND TRUE t12_i == 1 [L932] t12_st = 0 [L936] COND TRUE t13_i == 1 [L937] RET t13_st = 0 [L1876] init_threads() [L1877] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1248] COND FALSE !(M_E == 0) [L1253] COND FALSE !(T1_E == 0) [L1258] COND FALSE !(T2_E == 0) [L1263] COND FALSE !(T3_E == 0) [L1268] COND FALSE !(T4_E == 0) [L1273] COND FALSE !(T5_E == 0) [L1278] COND FALSE !(T6_E == 0) [L1283] COND FALSE !(T7_E == 0) [L1288] COND FALSE !(T8_E == 0) [L1293] COND FALSE !(T9_E == 0) [L1298] COND FALSE !(T10_E == 0) [L1303] COND FALSE !(T11_E == 0) [L1308] COND FALSE !(T12_E == 0) [L1313] COND FALSE !(T13_E == 0) [L1318] COND FALSE !(E_1 == 0) [L1323] COND FALSE !(E_2 == 0) [L1328] COND FALSE !(E_3 == 0) [L1333] COND FALSE !(E_4 == 0) [L1338] COND FALSE !(E_5 == 0) [L1343] COND FALSE !(E_6 == 0) [L1348] COND FALSE !(E_7 == 0) [L1353] COND FALSE !(E_8 == 0) [L1358] COND FALSE !(E_9 == 0) [L1363] COND FALSE !(E_10 == 0) [L1368] COND FALSE !(E_11 == 0) [L1373] COND FALSE !(E_12 == 0) [L1378] COND FALSE, RET !(E_13 == 0) [L1877] fire_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1878] CALL activate_threads() VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1531] int tmp ; [L1532] int tmp___0 ; [L1533] int tmp___1 ; [L1534] int tmp___2 ; [L1535] int tmp___3 ; [L1536] int tmp___4 ; [L1537] int tmp___5 ; [L1538] int tmp___6 ; [L1539] int tmp___7 ; [L1540] int tmp___8 ; [L1541] int tmp___9 ; [L1542] int tmp___10 ; [L1543] int tmp___11 ; [L1544] int tmp___12 ; [L1548] CALL, EXPR is_master_triggered() [L594] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L597] COND FALSE !(m_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L607] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L609] RET return (__retres1); [L1548] EXPR is_master_triggered() [L1548] tmp = is_master_triggered() [L1550] COND FALSE !(\read(tmp)) [L1556] CALL, EXPR is_transmit1_triggered() [L613] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L616] COND FALSE !(t1_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L626] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L628] RET return (__retres1); [L1556] EXPR is_transmit1_triggered() [L1556] tmp___0 = is_transmit1_triggered() [L1558] COND FALSE !(\read(tmp___0)) [L1564] CALL, EXPR is_transmit2_triggered() [L632] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L635] COND FALSE !(t2_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L645] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L647] RET return (__retres1); [L1564] EXPR is_transmit2_triggered() [L1564] tmp___1 = is_transmit2_triggered() [L1566] COND FALSE !(\read(tmp___1)) [L1572] CALL, EXPR is_transmit3_triggered() [L651] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L654] COND FALSE !(t3_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L664] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L666] RET return (__retres1); [L1572] EXPR is_transmit3_triggered() [L1572] tmp___2 = is_transmit3_triggered() [L1574] COND FALSE !(\read(tmp___2)) [L1580] CALL, EXPR is_transmit4_triggered() [L670] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L673] COND FALSE !(t4_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L683] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L685] RET return (__retres1); [L1580] EXPR is_transmit4_triggered() [L1580] tmp___3 = is_transmit4_triggered() [L1582] COND FALSE !(\read(tmp___3)) [L1588] CALL, EXPR is_transmit5_triggered() [L689] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L692] COND FALSE !(t5_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L702] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L704] RET return (__retres1); [L1588] EXPR is_transmit5_triggered() [L1588] tmp___4 = is_transmit5_triggered() [L1590] COND FALSE !(\read(tmp___4)) [L1596] CALL, EXPR is_transmit6_triggered() [L708] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L711] COND FALSE !(t6_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L721] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L723] RET return (__retres1); [L1596] EXPR is_transmit6_triggered() [L1596] tmp___5 = is_transmit6_triggered() [L1598] COND FALSE !(\read(tmp___5)) [L1604] CALL, EXPR is_transmit7_triggered() [L727] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L730] COND FALSE !(t7_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L740] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L742] RET return (__retres1); [L1604] EXPR is_transmit7_triggered() [L1604] tmp___6 = is_transmit7_triggered() [L1606] COND FALSE !(\read(tmp___6)) [L1612] CALL, EXPR is_transmit8_triggered() [L746] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L749] COND FALSE !(t8_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L759] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L761] RET return (__retres1); [L1612] EXPR is_transmit8_triggered() [L1612] tmp___7 = is_transmit8_triggered() [L1614] COND FALSE !(\read(tmp___7)) [L1620] CALL, EXPR is_transmit9_triggered() [L765] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L768] COND FALSE !(t9_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L778] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L780] RET return (__retres1); [L1620] EXPR is_transmit9_triggered() [L1620] tmp___8 = is_transmit9_triggered() [L1622] COND FALSE !(\read(tmp___8)) [L1628] CALL, EXPR is_transmit10_triggered() [L784] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L787] COND FALSE !(t10_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L797] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L799] RET return (__retres1); [L1628] EXPR is_transmit10_triggered() [L1628] tmp___9 = is_transmit10_triggered() [L1630] COND FALSE !(\read(tmp___9)) [L1636] CALL, EXPR is_transmit11_triggered() [L803] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L806] COND FALSE !(t11_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L816] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L818] RET return (__retres1); [L1636] EXPR is_transmit11_triggered() [L1636] tmp___10 = is_transmit11_triggered() [L1638] COND FALSE !(\read(tmp___10)) [L1644] CALL, EXPR is_transmit12_triggered() [L822] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L825] COND FALSE !(t12_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L835] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L837] RET return (__retres1); [L1644] EXPR is_transmit12_triggered() [L1644] tmp___11 = is_transmit12_triggered() [L1646] COND FALSE !(\read(tmp___11)) [L1652] CALL, EXPR is_transmit13_triggered() [L841] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L844] COND FALSE !(t13_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L854] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L856] RET return (__retres1); [L1652] EXPR is_transmit13_triggered() [L1652] tmp___12 = is_transmit13_triggered() [L1654] COND FALSE, RET !(\read(tmp___12)) [L1878] activate_threads() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1879] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1391] COND FALSE !(M_E == 1) [L1396] COND FALSE !(T1_E == 1) [L1401] COND FALSE !(T2_E == 1) [L1406] COND FALSE !(T3_E == 1) [L1411] COND FALSE !(T4_E == 1) [L1416] COND FALSE !(T5_E == 1) [L1421] COND FALSE !(T6_E == 1) [L1426] COND FALSE !(T7_E == 1) [L1431] COND FALSE !(T8_E == 1) [L1436] COND FALSE !(T9_E == 1) [L1441] COND FALSE !(T10_E == 1) [L1446] COND FALSE !(T11_E == 1) [L1451] COND FALSE !(T12_E == 1) [L1456] COND FALSE !(T13_E == 1) [L1461] COND FALSE !(E_1 == 1) [L1466] COND FALSE !(E_2 == 1) [L1471] COND FALSE !(E_3 == 1) [L1476] COND FALSE !(E_4 == 1) [L1481] COND FALSE !(E_5 == 1) [L1486] COND FALSE !(E_6 == 1) [L1491] COND FALSE !(E_7 == 1) [L1496] COND FALSE !(E_8 == 1) [L1501] COND FALSE !(E_9 == 1) [L1506] COND FALSE !(E_10 == 1) [L1511] COND FALSE !(E_11 == 1) [L1516] COND FALSE !(E_12 == 1) [L1521] COND FALSE, RET !(E_13 == 1) [L1879] reset_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1882] COND TRUE 1 [L1885] kernel_st = 1 [L1886] CALL eval() [L1027] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1031] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1034] CALL, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L946] int __retres1 ; [L949] COND TRUE m_st == 0 [L950] __retres1 = 1 [L1022] RET return (__retres1); [L1034] EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1034] tmp = exists_runnable_thread() [L1036] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE m_st == 0 [L1042] int tmp_ndt_1; [L1043] tmp_ndt_1 = __VERIFIER_nondet_int() [L1044] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1055] COND TRUE t1_st == 0 [L1056] int tmp_ndt_2; [L1057] tmp_ndt_2 = __VERIFIER_nondet_int() [L1058] COND FALSE !(\read(tmp_ndt_2)) [L1064] CALL error() [L11] __VERIFIER_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 341.75 ms. Allocated memory is still 1.0 GB. Free memory was 956.5 MB in the beginning and 929.5 MB in the end (delta: 26.9 MB). Peak memory consumption was 26.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 107.02 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 152.6 MB). Free memory was 929.5 MB in the beginning and 1.1 GB in the end (delta: -216.1 MB). Peak memory consumption was 19.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 44.92 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.5 MB). Peak memory consumption was 3.5 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1961.99 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 813.7 MB in the end (delta: 328.4 MB). Peak memory consumption was 328.4 MB. Max. memory is 11.5 GB. * CodeCheck took 49856.27 ms. Allocated memory was 1.2 GB in the beginning and 2.1 GB in the end (delta: 895.5 MB). Free memory was 813.7 MB in the beginning and 1.5 GB in the end (delta: -719.4 MB). Peak memory consumption was 176.0 MB. Max. memory is 11.5 GB. * Witness Printer took 126.48 ms. Allocated memory is still 2.1 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 24.4 MB). Peak memory consumption was 24.4 MB. Max. memory is 11.5 GB. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...