./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/transmitter.16_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 1dbac8bc Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.16_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05a526ca9d0710db502cdfc74677e2807f071449 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-1dbac8b [2018-11-10 07:06:51,702 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-10 07:06:51,704 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-10 07:06:51,712 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-10 07:06:51,712 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-10 07:06:51,713 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-10 07:06:51,714 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-10 07:06:51,715 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-10 07:06:51,716 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-10 07:06:51,716 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-10 07:06:51,717 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-10 07:06:51,717 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-10 07:06:51,718 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-10 07:06:51,719 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-10 07:06:51,719 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-10 07:06:51,720 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-10 07:06:51,720 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-10 07:06:51,722 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-10 07:06:51,724 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-10 07:06:51,724 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-10 07:06:51,725 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-10 07:06:51,725 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-10 07:06:51,727 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-10 07:06:51,727 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-10 07:06:51,727 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-10 07:06:51,728 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-10 07:06:51,729 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-10 07:06:51,729 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-10 07:06:51,730 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-10 07:06:51,731 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-10 07:06:51,731 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-10 07:06:51,731 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-10 07:06:51,731 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-10 07:06:51,732 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-10 07:06:51,732 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-10 07:06:51,733 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-10 07:06:51,733 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf [2018-11-10 07:06:51,741 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-10 07:06:51,741 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-10 07:06:51,742 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-10 07:06:51,742 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-10 07:06:51,742 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-10 07:06:51,743 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-10 07:06:51,743 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-10 07:06:51,743 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-10 07:06:51,743 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-10 07:06:51,743 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-10 07:06:51,743 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-10 07:06:51,743 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-10 07:06:51,744 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-10 07:06:51,744 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-10 07:06:51,744 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-10 07:06:51,744 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-10 07:06:51,744 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-10 07:06:51,744 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-11-10 07:06:51,744 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-11-10 07:06:51,745 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-10 07:06:51,745 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-10 07:06:51,745 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-10 07:06:51,745 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-10 07:06:51,745 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-10 07:06:51,745 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-10 07:06:51,745 INFO L133 SettingsManager]: * Trace refinement strategy=PENGUIN [2018-11-10 07:06:51,746 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-10 07:06:51,746 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-10 07:06:51,746 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05a526ca9d0710db502cdfc74677e2807f071449 [2018-11-10 07:06:51,770 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-10 07:06:51,779 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-10 07:06:51,782 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-10 07:06:51,783 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-10 07:06:51,783 INFO L276 PluginConnector]: CDTParser initialized [2018-11-10 07:06:51,784 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/../../sv-benchmarks/c/systemc/transmitter.16_false-unreach-call_false-termination.cil.c [2018-11-10 07:06:51,829 INFO L218 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/data/543801df9/d19fb7100de24bf7b7d95d937e2f0ff1/FLAG574d7411a [2018-11-10 07:06:52,159 INFO L298 CDTParser]: Found 1 translation units. [2018-11-10 07:06:52,159 INFO L158 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/sv-benchmarks/c/systemc/transmitter.16_false-unreach-call_false-termination.cil.c [2018-11-10 07:06:52,171 INFO L346 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/data/543801df9/d19fb7100de24bf7b7d95d937e2f0ff1/FLAG574d7411a [2018-11-10 07:06:52,180 INFO L354 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/data/543801df9/d19fb7100de24bf7b7d95d937e2f0ff1 [2018-11-10 07:06:52,182 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-10 07:06:52,183 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-10 07:06:52,184 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-10 07:06:52,184 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-10 07:06:52,186 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-10 07:06:52,186 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,188 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@43862a89 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52, skipping insertion in model container [2018-11-10 07:06:52,188 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,194 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-10 07:06:52,231 INFO L174 MainTranslator]: Built tables and reachable declarations [2018-11-10 07:06:52,416 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 07:06:52,420 INFO L189 MainTranslator]: Completed pre-run [2018-11-10 07:06:52,478 INFO L202 PostProcessor]: Analyzing one entry point: main [2018-11-10 07:06:52,494 INFO L193 MainTranslator]: Completed translation [2018-11-10 07:06:52,494 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52 WrapperNode [2018-11-10 07:06:52,494 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-10 07:06:52,495 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-10 07:06:52,495 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-10 07:06:52,495 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-10 07:06:52,501 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,551 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,586 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-10 07:06:52,586 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-10 07:06:52,586 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-10 07:06:52,586 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-10 07:06:52,595 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,595 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,598 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,598 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,606 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,621 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,624 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... [2018-11-10 07:06:52,629 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-10 07:06:52,629 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-10 07:06:52,629 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-10 07:06:52,629 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-10 07:06:52,630 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 07:06:52" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-10 07:06:52,678 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-10 07:06:52,678 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-10 07:06:52,679 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-10 07:06:52,679 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-10 07:06:52,679 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-10 07:06:52,679 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-10 07:06:52,679 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-10 07:06:52,679 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-10 07:06:52,679 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-10 07:06:52,679 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-10 07:06:52,680 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-10 07:06:52,680 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-10 07:06:52,680 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-10 07:06:52,680 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-10 07:06:54,499 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-10 07:06:54,500 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 07:06:54 BoogieIcfgContainer [2018-11-10 07:06:54,500 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-10 07:06:54,500 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-11-10 07:06:54,501 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-11-10 07:06:54,507 INFO L276 PluginConnector]: CodeCheck initialized [2018-11-10 07:06:54,507 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 07:06:54" (1/1) ... [2018-11-10 07:06:54,515 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-10 07:06:54,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:54,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 313 states to 201 states and 313 transitions. [2018-11-10 07:06:54,544 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 313 transitions. [2018-11-10 07:06:54,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:54,550 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:54,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:54,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:55,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:55,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 245 states and 397 transitions. [2018-11-10 07:06:55,288 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 397 transitions. [2018-11-10 07:06:55,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:55,290 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:55,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:55,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:55,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:55,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 246 states and 397 transitions. [2018-11-10 07:06:55,646 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 397 transitions. [2018-11-10 07:06:55,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:55,648 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:55,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:55,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:56,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:56,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 247 states and 397 transitions. [2018-11-10 07:06:56,031 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 397 transitions. [2018-11-10 07:06:56,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:56,033 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:56,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:56,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:56,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:56,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 248 states and 397 transitions. [2018-11-10 07:06:56,436 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 397 transitions. [2018-11-10 07:06:56,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:56,438 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:56,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:56,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:56,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:56,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 249 states and 397 transitions. [2018-11-10 07:06:56,817 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 397 transitions. [2018-11-10 07:06:56,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:56,818 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:56,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:56,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:57,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:57,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 250 states and 397 transitions. [2018-11-10 07:06:57,145 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 397 transitions. [2018-11-10 07:06:57,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:57,146 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:57,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:57,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:57,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:57,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 251 states and 397 transitions. [2018-11-10 07:06:57,502 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 397 transitions. [2018-11-10 07:06:57,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:57,503 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:57,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:57,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:57,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:57,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 252 states and 397 transitions. [2018-11-10 07:06:57,887 INFO L276 IsEmpty]: Start isEmpty. Operand 252 states and 397 transitions. [2018-11-10 07:06:57,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:57,888 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:57,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:57,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:58,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:58,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 253 states and 397 transitions. [2018-11-10 07:06:58,251 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 397 transitions. [2018-11-10 07:06:58,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:58,251 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:58,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:58,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:58,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:58,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 254 states and 397 transitions. [2018-11-10 07:06:58,637 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 397 transitions. [2018-11-10 07:06:58,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:58,638 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:58,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:58,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:59,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:59,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 255 states and 397 transitions. [2018-11-10 07:06:59,039 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 397 transitions. [2018-11-10 07:06:59,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:59,040 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:59,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:59,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:59,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:59,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 256 states and 397 transitions. [2018-11-10 07:06:59,401 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 397 transitions. [2018-11-10 07:06:59,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:59,401 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:59,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:59,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:06:59,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:06:59,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 257 states and 397 transitions. [2018-11-10 07:06:59,774 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 397 transitions. [2018-11-10 07:06:59,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:06:59,775 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:06:59,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:06:59,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:00,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:00,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 258 states and 397 transitions. [2018-11-10 07:07:00,189 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 397 transitions. [2018-11-10 07:07:00,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:00,189 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:00,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:00,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:00,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:00,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 259 states and 397 transitions. [2018-11-10 07:07:00,644 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 397 transitions. [2018-11-10 07:07:00,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:00,644 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:00,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:00,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:01,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:01,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 297 states and 474 transitions. [2018-11-10 07:07:01,178 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 474 transitions. [2018-11-10 07:07:01,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:01,179 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:01,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:01,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:01,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:01,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 298 states and 474 transitions. [2018-11-10 07:07:01,494 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 474 transitions. [2018-11-10 07:07:01,495 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:01,495 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:01,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:01,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:01,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:01,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 299 states and 474 transitions. [2018-11-10 07:07:01,697 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 474 transitions. [2018-11-10 07:07:01,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:01,698 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:01,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:01,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:01,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:01,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 300 states and 474 transitions. [2018-11-10 07:07:01,976 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 474 transitions. [2018-11-10 07:07:01,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:01,977 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:01,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:02,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:02,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:02,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 301 states and 474 transitions. [2018-11-10 07:07:02,220 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 474 transitions. [2018-11-10 07:07:02,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:02,221 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:02,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:02,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:02,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:02,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 302 states and 474 transitions. [2018-11-10 07:07:02,468 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 474 transitions. [2018-11-10 07:07:02,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:02,469 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:02,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:02,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:02,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:02,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 303 states and 474 transitions. [2018-11-10 07:07:02,669 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 474 transitions. [2018-11-10 07:07:02,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:02,670 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:02,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:02,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:02,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:02,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 304 states and 474 transitions. [2018-11-10 07:07:02,875 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 474 transitions. [2018-11-10 07:07:02,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:02,875 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:02,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:02,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:03,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:03,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 305 states and 474 transitions. [2018-11-10 07:07:03,048 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 474 transitions. [2018-11-10 07:07:03,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:03,049 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:03,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:03,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:03,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:03,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 306 states and 474 transitions. [2018-11-10 07:07:03,257 INFO L276 IsEmpty]: Start isEmpty. Operand 306 states and 474 transitions. [2018-11-10 07:07:03,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:03,257 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:03,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:03,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:03,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:03,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 307 states and 474 transitions. [2018-11-10 07:07:03,453 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 474 transitions. [2018-11-10 07:07:03,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:03,453 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:03,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:03,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:03,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:03,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 308 states and 474 transitions. [2018-11-10 07:07:03,618 INFO L276 IsEmpty]: Start isEmpty. Operand 308 states and 474 transitions. [2018-11-10 07:07:03,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:03,618 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:03,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:03,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:03,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:03,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 309 states and 474 transitions. [2018-11-10 07:07:03,821 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 474 transitions. [2018-11-10 07:07:03,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:03,822 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:03,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:03,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:04,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:04,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 341 states and 539 transitions. [2018-11-10 07:07:04,151 INFO L276 IsEmpty]: Start isEmpty. Operand 341 states and 539 transitions. [2018-11-10 07:07:04,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:04,152 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:04,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:04,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:04,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:04,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 342 states and 539 transitions. [2018-11-10 07:07:04,535 INFO L276 IsEmpty]: Start isEmpty. Operand 342 states and 539 transitions. [2018-11-10 07:07:04,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:04,536 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:04,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:04,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:04,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:04,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 343 states and 539 transitions. [2018-11-10 07:07:04,758 INFO L276 IsEmpty]: Start isEmpty. Operand 343 states and 539 transitions. [2018-11-10 07:07:04,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:04,759 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:04,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:04,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:04,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:04,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 344 states and 539 transitions. [2018-11-10 07:07:04,974 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 539 transitions. [2018-11-10 07:07:04,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:04,975 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:04,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:04,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:05,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:05,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 345 states and 539 transitions. [2018-11-10 07:07:05,185 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 539 transitions. [2018-11-10 07:07:05,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:05,185 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:05,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:05,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:05,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:05,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 346 states and 539 transitions. [2018-11-10 07:07:05,393 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 539 transitions. [2018-11-10 07:07:05,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:05,393 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:05,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:05,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:05,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:05,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 347 states and 539 transitions. [2018-11-10 07:07:05,617 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 539 transitions. [2018-11-10 07:07:05,617 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:05,617 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:05,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:05,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:05,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:05,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 348 states and 539 transitions. [2018-11-10 07:07:05,843 INFO L276 IsEmpty]: Start isEmpty. Operand 348 states and 539 transitions. [2018-11-10 07:07:05,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:05,844 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:05,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:05,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:06,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:06,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 349 states and 539 transitions. [2018-11-10 07:07:06,061 INFO L276 IsEmpty]: Start isEmpty. Operand 349 states and 539 transitions. [2018-11-10 07:07:06,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:06,061 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:06,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:06,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:06,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:06,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 350 states and 539 transitions. [2018-11-10 07:07:06,283 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 539 transitions. [2018-11-10 07:07:06,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:06,284 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:06,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:06,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:06,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:06,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 351 states and 539 transitions. [2018-11-10 07:07:06,540 INFO L276 IsEmpty]: Start isEmpty. Operand 351 states and 539 transitions. [2018-11-10 07:07:06,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:06,540 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:06,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:06,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:06,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:06,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 380 states and 598 transitions. [2018-11-10 07:07:06,890 INFO L276 IsEmpty]: Start isEmpty. Operand 380 states and 598 transitions. [2018-11-10 07:07:06,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:06,890 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:06,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:06,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:07,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:07,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 381 states and 598 transitions. [2018-11-10 07:07:07,216 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 598 transitions. [2018-11-10 07:07:07,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:07,217 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:07,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:07,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:07,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:07,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 382 states and 598 transitions. [2018-11-10 07:07:07,498 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 598 transitions. [2018-11-10 07:07:07,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:07,498 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:07,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:07,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:07,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:07,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 383 states and 598 transitions. [2018-11-10 07:07:07,758 INFO L276 IsEmpty]: Start isEmpty. Operand 383 states and 598 transitions. [2018-11-10 07:07:07,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:07,759 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:07,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:07,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:08,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:08,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 384 states and 598 transitions. [2018-11-10 07:07:08,014 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 598 transitions. [2018-11-10 07:07:08,014 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:08,014 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:08,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:08,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:08,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:08,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 385 states and 598 transitions. [2018-11-10 07:07:08,304 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 598 transitions. [2018-11-10 07:07:08,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:08,304 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:08,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:08,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:08,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:08,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 386 states and 598 transitions. [2018-11-10 07:07:08,566 INFO L276 IsEmpty]: Start isEmpty. Operand 386 states and 598 transitions. [2018-11-10 07:07:08,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:08,566 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:08,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:08,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:08,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:08,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 387 states and 598 transitions. [2018-11-10 07:07:08,823 INFO L276 IsEmpty]: Start isEmpty. Operand 387 states and 598 transitions. [2018-11-10 07:07:08,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:08,823 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:08,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:08,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:09,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:09,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 388 states and 598 transitions. [2018-11-10 07:07:09,091 INFO L276 IsEmpty]: Start isEmpty. Operand 388 states and 598 transitions. [2018-11-10 07:07:09,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:09,092 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:09,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:09,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:09,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:09,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 389 states and 598 transitions. [2018-11-10 07:07:09,355 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 598 transitions. [2018-11-10 07:07:09,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:09,356 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:09,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:09,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:09,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:09,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 675 states to 412 states and 645 transitions. [2018-11-10 07:07:09,706 INFO L276 IsEmpty]: Start isEmpty. Operand 412 states and 645 transitions. [2018-11-10 07:07:09,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:09,706 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:09,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:09,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:09,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:09,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 675 states to 413 states and 645 transitions. [2018-11-10 07:07:09,990 INFO L276 IsEmpty]: Start isEmpty. Operand 413 states and 645 transitions. [2018-11-10 07:07:09,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:09,991 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:09,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:10,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:10,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:10,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 675 states to 414 states and 645 transitions. [2018-11-10 07:07:10,277 INFO L276 IsEmpty]: Start isEmpty. Operand 414 states and 645 transitions. [2018-11-10 07:07:10,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:10,277 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:10,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:10,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:10,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:10,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 675 states to 415 states and 645 transitions. [2018-11-10 07:07:10,552 INFO L276 IsEmpty]: Start isEmpty. Operand 415 states and 645 transitions. [2018-11-10 07:07:10,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:10,552 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:10,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:10,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:10,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:10,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 675 states to 416 states and 645 transitions. [2018-11-10 07:07:10,828 INFO L276 IsEmpty]: Start isEmpty. Operand 416 states and 645 transitions. [2018-11-10 07:07:10,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:10,828 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:10,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:10,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:11,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:11,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 675 states to 417 states and 645 transitions. [2018-11-10 07:07:11,101 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 645 transitions. [2018-11-10 07:07:11,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:11,101 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:11,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:11,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:11,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:11,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 675 states to 418 states and 645 transitions. [2018-11-10 07:07:11,374 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 645 transitions. [2018-11-10 07:07:11,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:11,374 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:11,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:11,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:11,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:11,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 675 states to 419 states and 645 transitions. [2018-11-10 07:07:11,649 INFO L276 IsEmpty]: Start isEmpty. Operand 419 states and 645 transitions. [2018-11-10 07:07:11,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:11,649 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:11,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:11,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:12,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:12,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 436 states and 680 transitions. [2018-11-10 07:07:12,001 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 680 transitions. [2018-11-10 07:07:12,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:12,001 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:12,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:12,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:12,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:12,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 437 states and 680 transitions. [2018-11-10 07:07:12,288 INFO L276 IsEmpty]: Start isEmpty. Operand 437 states and 680 transitions. [2018-11-10 07:07:12,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:12,289 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:12,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:12,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:12,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:12,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 438 states and 680 transitions. [2018-11-10 07:07:12,574 INFO L276 IsEmpty]: Start isEmpty. Operand 438 states and 680 transitions. [2018-11-10 07:07:12,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:12,574 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:12,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:12,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:12,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:12,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 439 states and 680 transitions. [2018-11-10 07:07:12,842 INFO L276 IsEmpty]: Start isEmpty. Operand 439 states and 680 transitions. [2018-11-10 07:07:12,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:12,842 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:12,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:12,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:13,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:13,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 440 states and 680 transitions. [2018-11-10 07:07:13,117 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 680 transitions. [2018-11-10 07:07:13,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:13,118 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:13,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:13,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:13,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:13,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 716 states to 441 states and 680 transitions. [2018-11-10 07:07:13,410 INFO L276 IsEmpty]: Start isEmpty. Operand 441 states and 680 transitions. [2018-11-10 07:07:13,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:13,410 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:13,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:13,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:13,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:13,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 745 states to 452 states and 703 transitions. [2018-11-10 07:07:13,773 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 703 transitions. [2018-11-10 07:07:13,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:13,773 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:13,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:13,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:14,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:14,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 745 states to 453 states and 703 transitions. [2018-11-10 07:07:14,018 INFO L276 IsEmpty]: Start isEmpty. Operand 453 states and 703 transitions. [2018-11-10 07:07:14,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:14,019 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:14,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:14,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:14,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:14,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 745 states to 454 states and 703 transitions. [2018-11-10 07:07:14,262 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 703 transitions. [2018-11-10 07:07:14,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:14,263 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:14,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:14,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:14,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:14,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 745 states to 455 states and 703 transitions. [2018-11-10 07:07:14,521 INFO L276 IsEmpty]: Start isEmpty. Operand 455 states and 703 transitions. [2018-11-10 07:07:14,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:14,522 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:14,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:14,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:14,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:14,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 762 states to 460 states and 714 transitions. [2018-11-10 07:07:14,833 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 714 transitions. [2018-11-10 07:07:14,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:14,833 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:14,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:14,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:15,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:15,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 762 states to 461 states and 714 transitions. [2018-11-10 07:07:15,039 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 714 transitions. [2018-11-10 07:07:15,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:15,039 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:15,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:15,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:15,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:15,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 773 states to 463 states and 719 transitions. [2018-11-10 07:07:15,340 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 719 transitions. [2018-11-10 07:07:15,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:15,340 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:15,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:15,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:17,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:17,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 896 states to 517 states and 825 transitions. [2018-11-10 07:07:17,274 INFO L276 IsEmpty]: Start isEmpty. Operand 517 states and 825 transitions. [2018-11-10 07:07:17,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:17,275 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:17,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:17,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:18,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:18,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 921 states to 525 states and 842 transitions. [2018-11-10 07:07:18,696 INFO L276 IsEmpty]: Start isEmpty. Operand 525 states and 842 transitions. [2018-11-10 07:07:18,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:18,697 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:18,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:18,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:21,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:21,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 958 states to 539 states and 871 transitions. [2018-11-10 07:07:21,040 INFO L276 IsEmpty]: Start isEmpty. Operand 539 states and 871 transitions. [2018-11-10 07:07:21,041 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:21,041 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:21,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:21,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:24,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:24,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 559 states and 912 transitions. [2018-11-10 07:07:24,580 INFO L276 IsEmpty]: Start isEmpty. Operand 559 states and 912 transitions. [2018-11-10 07:07:24,581 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:24,581 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:24,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:24,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:29,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:29,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1068 states to 585 states and 965 transitions. [2018-11-10 07:07:29,651 INFO L276 IsEmpty]: Start isEmpty. Operand 585 states and 965 transitions. [2018-11-10 07:07:29,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:29,652 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:29,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:29,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:37,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:37,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1147 states to 620 states and 1036 transitions. [2018-11-10 07:07:37,630 INFO L276 IsEmpty]: Start isEmpty. Operand 620 states and 1036 transitions. [2018-11-10 07:07:37,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-10 07:07:37,631 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:37,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:37,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:48,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:48,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1238 states to 661 states and 1119 transitions. [2018-11-10 07:07:48,423 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 1119 transitions. [2018-11-10 07:07:48,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:48,423 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:48,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:48,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:48,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:48,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1233 states to 659 states and 1114 transitions. [2018-11-10 07:07:48,816 INFO L276 IsEmpty]: Start isEmpty. Operand 659 states and 1114 transitions. [2018-11-10 07:07:48,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:48,816 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:48,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:48,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:49,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:49,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1234 states to 660 states and 1115 transitions. [2018-11-10 07:07:49,064 INFO L276 IsEmpty]: Start isEmpty. Operand 660 states and 1115 transitions. [2018-11-10 07:07:49,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:49,064 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:49,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:49,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:49,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:49,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1235 states to 661 states and 1116 transitions. [2018-11-10 07:07:49,388 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 1116 transitions. [2018-11-10 07:07:49,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:49,388 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:49,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:49,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:49,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:49,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1236 states to 662 states and 1117 transitions. [2018-11-10 07:07:49,783 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 1117 transitions. [2018-11-10 07:07:49,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:49,784 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:49,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:49,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:50,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:50,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1237 states to 663 states and 1118 transitions. [2018-11-10 07:07:50,192 INFO L276 IsEmpty]: Start isEmpty. Operand 663 states and 1118 transitions. [2018-11-10 07:07:50,193 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:50,193 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:50,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:50,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:50,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:50,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1238 states to 664 states and 1119 transitions. [2018-11-10 07:07:50,622 INFO L276 IsEmpty]: Start isEmpty. Operand 664 states and 1119 transitions. [2018-11-10 07:07:50,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:50,622 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:50,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:50,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:51,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:51,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1239 states to 665 states and 1120 transitions. [2018-11-10 07:07:51,102 INFO L276 IsEmpty]: Start isEmpty. Operand 665 states and 1120 transitions. [2018-11-10 07:07:51,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:51,103 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:51,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:51,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:51,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:51,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1240 states to 666 states and 1121 transitions. [2018-11-10 07:07:51,484 INFO L276 IsEmpty]: Start isEmpty. Operand 666 states and 1121 transitions. [2018-11-10 07:07:51,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:51,484 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:51,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-10 07:07:51,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-10 07:07:51,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-10 07:07:51,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1241 states to 667 states and 1122 transitions. [2018-11-10 07:07:51,890 INFO L276 IsEmpty]: Start isEmpty. Operand 667 states and 1122 transitions. [2018-11-10 07:07:51,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-10 07:07:51,891 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-11-10 07:07:51,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 07:07:51,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 07:07:52,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 07:07:52,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-10 07:07:52,274 WARN L496 CodeCheckObserver]: This program is UNSAFE, Check terminated with 87 iterations. [2018-11-10 07:07:52,389 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 10.11 07:07:52 ImpRootNode [2018-11-10 07:07:52,389 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2018-11-10 07:07:52,390 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-10 07:07:52,390 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-10 07:07:52,390 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-10 07:07:52,390 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.11 07:06:54" (3/4) ... [2018-11-10 07:07:52,392 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-10 07:07:52,484 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_bb622b70-bbb0-4583-8ddf-1a7cb6719067/bin-2019/ukojak/witness.graphml [2018-11-10 07:07:52,484 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-10 07:07:52,484 INFO L168 Benchmark]: Toolchain (without parser) took 60301.77 ms. Allocated memory was 1.0 GB in the beginning and 2.2 GB in the end (delta: 1.1 GB). Free memory was 960.3 MB in the beginning and 1.6 GB in the end (delta: -663.2 MB). Peak memory consumption was 472.9 MB. Max. memory is 11.5 GB. [2018-11-10 07:07:52,485 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-10 07:07:52,485 INFO L168 Benchmark]: CACSL2BoogieTranslator took 310.85 ms. Allocated memory is still 1.0 GB. Free memory was 957.6 MB in the beginning and 927.0 MB in the end (delta: 30.6 MB). Peak memory consumption was 30.6 MB. Max. memory is 11.5 GB. [2018-11-10 07:07:52,485 INFO L168 Benchmark]: Boogie Procedure Inliner took 91.27 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 173.5 MB). Free memory was 927.0 MB in the beginning and 1.2 GB in the end (delta: -237.1 MB). Peak memory consumption was 16.7 MB. Max. memory is 11.5 GB. [2018-11-10 07:07:52,486 INFO L168 Benchmark]: Boogie Preprocessor took 42.59 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-10 07:07:52,486 INFO L168 Benchmark]: RCFGBuilder took 1871.16 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 79.2 MB). Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: -34.9 MB). Peak memory consumption was 321.8 MB. Max. memory is 11.5 GB. [2018-11-10 07:07:52,486 INFO L168 Benchmark]: CodeCheck took 57888.90 ms. Allocated memory was 1.3 GB in the beginning and 2.2 GB in the end (delta: 883.4 MB). Free memory was 1.2 GB in the beginning and 1.7 GB in the end (delta: -478.5 MB). Peak memory consumption was 405.0 MB. Max. memory is 11.5 GB. [2018-11-10 07:07:52,486 INFO L168 Benchmark]: Witness Printer took 94.15 ms. Allocated memory is still 2.2 GB. Free memory was 1.7 GB in the beginning and 1.6 GB in the end (delta: 50.7 MB). Peak memory consumption was 50.7 MB. Max. memory is 11.5 GB. [2018-11-10 07:07:52,488 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 442 locations, 1 error locations. UNSAFE Result, 57.7s OverallTime, 87 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: -943990784 SDtfs, -911884296 SDslu, -1568817672 SDs, 0 SdLazy, -2032255492 SolverSat, 74832896 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 11.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 56160 GetRequests, 45002 SyntacticMatches, 10746 SemanticMatches, 412 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 283708 ImplicationChecksByTransitivity, 53.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, traceCheckStatistics: 0.2s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 2.5s InterpolantComputationTime, 6274 NumberOfCodeBlocks, 6274 NumberOfCodeBlocksAsserted, 87 NumberOfCheckSat, 6115 ConstructedInterpolants, 0 QuantifiedInterpolants, 870553 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 86 InterpolantComputations, 86 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int t9_pc = 0; [L25] int t10_pc = 0; [L26] int t11_pc = 0; [L27] int t12_pc = 0; [L28] int t13_pc = 0; [L29] int t14_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int t6_st ; [L37] int t7_st ; [L38] int t8_st ; [L39] int t9_st ; [L40] int t10_st ; [L41] int t11_st ; [L42] int t12_st ; [L43] int t13_st ; [L44] int t14_st ; [L45] int m_i ; [L46] int t1_i ; [L47] int t2_i ; [L48] int t3_i ; [L49] int t4_i ; [L50] int t5_i ; [L51] int t6_i ; [L52] int t7_i ; [L53] int t8_i ; [L54] int t9_i ; [L55] int t10_i ; [L56] int t11_i ; [L57] int t12_i ; [L58] int t13_i ; [L59] int t14_i ; [L60] int M_E = 2; [L61] int T1_E = 2; [L62] int T2_E = 2; [L63] int T3_E = 2; [L64] int T4_E = 2; [L65] int T5_E = 2; [L66] int T6_E = 2; [L67] int T7_E = 2; [L68] int T8_E = 2; [L69] int T9_E = 2; [L70] int T10_E = 2; [L71] int T11_E = 2; [L72] int T12_E = 2; [L73] int T13_E = 2; [L74] int T14_E = 2; [L75] int E_1 = 2; [L76] int E_2 = 2; [L77] int E_3 = 2; [L78] int E_4 = 2; [L79] int E_5 = 2; [L80] int E_6 = 2; [L81] int E_7 = 2; [L82] int E_8 = 2; [L83] int E_9 = 2; [L84] int E_10 = 2; [L85] int E_11 = 2; [L86] int E_12 = 2; [L87] int E_13 = 2; [L88] int E_14 = 2; [L2052] int __retres1 ; [L2056] CALL init_model() [L1954] m_i = 1 [L1955] t1_i = 1 [L1956] t2_i = 1 [L1957] t3_i = 1 [L1958] t4_i = 1 [L1959] t5_i = 1 [L1960] t6_i = 1 [L1961] t7_i = 1 [L1962] t8_i = 1 [L1963] t9_i = 1 [L1964] t10_i = 1 [L1965] t11_i = 1 [L1966] t12_i = 1 [L1967] t13_i = 1 [L1968] RET t14_i = 1 [L2056] init_model() [L2057] CALL start_simulation() [L1993] int kernel_st ; [L1994] int tmp ; [L1995] int tmp___0 ; [L1999] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2000] FCALL update_channels() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2001] CALL init_threads() [L929] COND TRUE m_i == 1 [L930] m_st = 0 [L934] COND TRUE t1_i == 1 [L935] t1_st = 0 [L939] COND TRUE t2_i == 1 [L940] t2_st = 0 [L944] COND TRUE t3_i == 1 [L945] t3_st = 0 [L949] COND TRUE t4_i == 1 [L950] t4_st = 0 [L954] COND TRUE t5_i == 1 [L955] t5_st = 0 [L959] COND TRUE t6_i == 1 [L960] t6_st = 0 [L964] COND TRUE t7_i == 1 [L965] t7_st = 0 [L969] COND TRUE t8_i == 1 [L970] t8_st = 0 [L974] COND TRUE t9_i == 1 [L975] t9_st = 0 [L979] COND TRUE t10_i == 1 [L980] t10_st = 0 [L984] COND TRUE t11_i == 1 [L985] t11_st = 0 [L989] COND TRUE t12_i == 1 [L990] t12_st = 0 [L994] COND TRUE t13_i == 1 [L995] t13_st = 0 [L999] COND TRUE t14_i == 1 [L1000] RET t14_st = 0 [L2001] init_threads() [L2002] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1332] COND FALSE !(M_E == 0) [L1337] COND FALSE !(T1_E == 0) [L1342] COND FALSE !(T2_E == 0) [L1347] COND FALSE !(T3_E == 0) [L1352] COND FALSE !(T4_E == 0) [L1357] COND FALSE !(T5_E == 0) [L1362] COND FALSE !(T6_E == 0) [L1367] COND FALSE !(T7_E == 0) [L1372] COND FALSE !(T8_E == 0) [L1377] COND FALSE !(T9_E == 0) [L1382] COND FALSE !(T10_E == 0) [L1387] COND FALSE !(T11_E == 0) [L1392] COND FALSE !(T12_E == 0) [L1397] COND FALSE !(T13_E == 0) [L1402] COND FALSE !(T14_E == 0) [L1407] COND FALSE !(E_1 == 0) [L1412] COND FALSE !(E_2 == 0) [L1417] COND FALSE !(E_3 == 0) [L1422] COND FALSE !(E_4 == 0) [L1427] COND FALSE !(E_5 == 0) [L1432] COND FALSE !(E_6 == 0) [L1437] COND FALSE !(E_7 == 0) [L1442] COND FALSE !(E_8 == 0) [L1447] COND FALSE !(E_9 == 0) [L1452] COND FALSE !(E_10 == 0) [L1457] COND FALSE !(E_11 == 0) [L1462] COND FALSE !(E_12 == 0) [L1467] COND FALSE !(E_13 == 0) [L1472] COND FALSE, RET !(E_14 == 0) [L2002] fire_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2003] CALL activate_threads() VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1635] int tmp ; [L1636] int tmp___0 ; [L1637] int tmp___1 ; [L1638] int tmp___2 ; [L1639] int tmp___3 ; [L1640] int tmp___4 ; [L1641] int tmp___5 ; [L1642] int tmp___6 ; [L1643] int tmp___7 ; [L1644] int tmp___8 ; [L1645] int tmp___9 ; [L1646] int tmp___10 ; [L1647] int tmp___11 ; [L1648] int tmp___12 ; [L1649] int tmp___13 ; [L1654] CALL, EXPR is_master_triggered() [L633] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L636] COND FALSE !(m_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L646] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L648] RET return (__retres1); [L1654] EXPR is_master_triggered() [L1654] tmp = is_master_triggered() [L1656] COND FALSE !(\read(tmp)) [L1662] CALL, EXPR is_transmit1_triggered() [L652] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L655] COND FALSE !(t1_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L665] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L667] RET return (__retres1); [L1662] EXPR is_transmit1_triggered() [L1662] tmp___0 = is_transmit1_triggered() [L1664] COND FALSE !(\read(tmp___0)) [L1670] CALL, EXPR is_transmit2_triggered() [L671] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L674] COND FALSE !(t2_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L684] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L686] RET return (__retres1); [L1670] EXPR is_transmit2_triggered() [L1670] tmp___1 = is_transmit2_triggered() [L1672] COND FALSE !(\read(tmp___1)) [L1678] CALL, EXPR is_transmit3_triggered() [L690] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L693] COND FALSE !(t3_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L703] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L705] RET return (__retres1); [L1678] EXPR is_transmit3_triggered() [L1678] tmp___2 = is_transmit3_triggered() [L1680] COND FALSE !(\read(tmp___2)) [L1686] CALL, EXPR is_transmit4_triggered() [L709] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L712] COND FALSE !(t4_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L722] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L724] RET return (__retres1); [L1686] EXPR is_transmit4_triggered() [L1686] tmp___3 = is_transmit4_triggered() [L1688] COND FALSE !(\read(tmp___3)) [L1694] CALL, EXPR is_transmit5_triggered() [L728] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L731] COND FALSE !(t5_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L741] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L743] RET return (__retres1); [L1694] EXPR is_transmit5_triggered() [L1694] tmp___4 = is_transmit5_triggered() [L1696] COND FALSE !(\read(tmp___4)) [L1702] CALL, EXPR is_transmit6_triggered() [L747] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L750] COND FALSE !(t6_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L760] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L762] RET return (__retres1); [L1702] EXPR is_transmit6_triggered() [L1702] tmp___5 = is_transmit6_triggered() [L1704] COND FALSE !(\read(tmp___5)) [L1710] CALL, EXPR is_transmit7_triggered() [L766] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L769] COND FALSE !(t7_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L779] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L781] RET return (__retres1); [L1710] EXPR is_transmit7_triggered() [L1710] tmp___6 = is_transmit7_triggered() [L1712] COND FALSE !(\read(tmp___6)) [L1718] CALL, EXPR is_transmit8_triggered() [L785] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L788] COND FALSE !(t8_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L798] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L800] RET return (__retres1); [L1718] EXPR is_transmit8_triggered() [L1718] tmp___7 = is_transmit8_triggered() [L1720] COND FALSE !(\read(tmp___7)) [L1726] CALL, EXPR is_transmit9_triggered() [L804] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L807] COND FALSE !(t9_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L817] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L819] RET return (__retres1); [L1726] EXPR is_transmit9_triggered() [L1726] tmp___8 = is_transmit9_triggered() [L1728] COND FALSE !(\read(tmp___8)) [L1734] CALL, EXPR is_transmit10_triggered() [L823] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L826] COND FALSE !(t10_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L836] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L838] RET return (__retres1); [L1734] EXPR is_transmit10_triggered() [L1734] tmp___9 = is_transmit10_triggered() [L1736] COND FALSE !(\read(tmp___9)) [L1742] CALL, EXPR is_transmit11_triggered() [L842] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L845] COND FALSE !(t11_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L855] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L857] RET return (__retres1); [L1742] EXPR is_transmit11_triggered() [L1742] tmp___10 = is_transmit11_triggered() [L1744] COND FALSE !(\read(tmp___10)) [L1750] CALL, EXPR is_transmit12_triggered() [L861] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L864] COND FALSE !(t12_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L874] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L876] RET return (__retres1); [L1750] EXPR is_transmit12_triggered() [L1750] tmp___11 = is_transmit12_triggered() [L1752] COND FALSE !(\read(tmp___11)) [L1758] CALL, EXPR is_transmit13_triggered() [L880] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L883] COND FALSE !(t13_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L893] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L895] RET return (__retres1); [L1758] EXPR is_transmit13_triggered() [L1758] tmp___12 = is_transmit13_triggered() [L1760] COND FALSE !(\read(tmp___12)) [L1766] CALL, EXPR is_transmit14_triggered() [L899] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L902] COND FALSE !(t14_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L912] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L914] RET return (__retres1); [L1766] EXPR is_transmit14_triggered() [L1766] tmp___13 = is_transmit14_triggered() [L1768] COND FALSE, RET !(\read(tmp___13)) [L2003] activate_threads() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2004] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1485] COND FALSE !(M_E == 1) [L1490] COND FALSE !(T1_E == 1) [L1495] COND FALSE !(T2_E == 1) [L1500] COND FALSE !(T3_E == 1) [L1505] COND FALSE !(T4_E == 1) [L1510] COND FALSE !(T5_E == 1) [L1515] COND FALSE !(T6_E == 1) [L1520] COND FALSE !(T7_E == 1) [L1525] COND FALSE !(T8_E == 1) [L1530] COND FALSE !(T9_E == 1) [L1535] COND FALSE !(T10_E == 1) [L1540] COND FALSE !(T11_E == 1) [L1545] COND FALSE !(T12_E == 1) [L1550] COND FALSE !(T13_E == 1) [L1555] COND FALSE !(T14_E == 1) [L1560] COND FALSE !(E_1 == 1) [L1565] COND FALSE !(E_2 == 1) [L1570] COND FALSE !(E_3 == 1) [L1575] COND FALSE !(E_4 == 1) [L1580] COND FALSE !(E_5 == 1) [L1585] COND FALSE !(E_6 == 1) [L1590] COND FALSE !(E_7 == 1) [L1595] COND FALSE !(E_8 == 1) [L1600] COND FALSE !(E_9 == 1) [L1605] COND FALSE !(E_10 == 1) [L1610] COND FALSE !(E_11 == 1) [L1615] COND FALSE !(E_12 == 1) [L1620] COND FALSE !(E_13 == 1) [L1625] COND FALSE, RET !(E_14 == 1) [L2004] reset_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2007] COND TRUE 1 [L2010] kernel_st = 1 [L2011] CALL eval() [L1096] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1100] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1103] CALL, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1009] int __retres1 ; [L1012] COND TRUE m_st == 0 [L1013] __retres1 = 1 [L1091] RET return (__retres1); [L1103] EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1103] tmp = exists_runnable_thread() [L1105] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1110] COND TRUE m_st == 0 [L1111] int tmp_ndt_1; [L1112] tmp_ndt_1 = __VERIFIER_nondet_int() [L1113] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1124] COND TRUE t1_st == 0 [L1125] int tmp_ndt_2; [L1126] tmp_ndt_2 = __VERIFIER_nondet_int() [L1127] COND FALSE !(\read(tmp_ndt_2)) [L1133] CALL error() [L11] __VERIFIER_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 310.85 ms. Allocated memory is still 1.0 GB. Free memory was 957.6 MB in the beginning and 927.0 MB in the end (delta: 30.6 MB). Peak memory consumption was 30.6 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 91.27 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 173.5 MB). Free memory was 927.0 MB in the beginning and 1.2 GB in the end (delta: -237.1 MB). Peak memory consumption was 16.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 42.59 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1871.16 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 79.2 MB). Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: -34.9 MB). Peak memory consumption was 321.8 MB. Max. memory is 11.5 GB. * CodeCheck took 57888.90 ms. Allocated memory was 1.3 GB in the beginning and 2.2 GB in the end (delta: 883.4 MB). Free memory was 1.2 GB in the beginning and 1.7 GB in the end (delta: -478.5 MB). Peak memory consumption was 405.0 MB. Max. memory is 11.5 GB. * Witness Printer took 94.15 ms. Allocated memory is still 2.2 GB. Free memory was 1.7 GB in the beginning and 1.6 GB in the end (delta: 50.7 MB). Peak memory consumption was 50.7 MB. Max. memory is 11.5 GB. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...