./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/transmitter.15_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0e3598d1a4e9129bf22e72269576449e67f0febd ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 13:08:49,462 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 13:08:49,464 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 13:08:49,471 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 13:08:49,471 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 13:08:49,472 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 13:08:49,473 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 13:08:49,474 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 13:08:49,475 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 13:08:49,476 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 13:08:49,476 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 13:08:49,476 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 13:08:49,477 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 13:08:49,478 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 13:08:49,478 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 13:08:49,479 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 13:08:49,479 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 13:08:49,480 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 13:08:49,482 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 13:08:49,483 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 13:08:49,483 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 13:08:49,484 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 13:08:49,486 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 13:08:49,486 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 13:08:49,487 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 13:08:49,487 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 13:08:49,488 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 13:08:49,488 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 13:08:49,489 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 13:08:49,490 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 13:08:49,490 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 13:08:49,491 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 13:08:49,491 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 13:08:49,491 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 13:08:49,491 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 13:08:49,492 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 13:08:49,492 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf [2018-11-18 13:08:49,501 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 13:08:49,501 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 13:08:49,502 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 13:08:49,502 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-18 13:08:49,502 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 13:08:49,502 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 13:08:49,503 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 13:08:49,503 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 13:08:49,503 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 13:08:49,503 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 13:08:49,503 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 13:08:49,503 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 13:08:49,504 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 13:08:49,504 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 13:08:49,504 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 13:08:49,504 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 13:08:49,504 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 13:08:49,504 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 13:08:49,504 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-11-18 13:08:49,505 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-11-18 13:08:49,505 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 13:08:49,505 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 13:08:49,505 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-18 13:08:49,505 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 13:08:49,505 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 13:08:49,505 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 13:08:49,508 INFO L133 SettingsManager]: * Trace refinement strategy=PENGUIN [2018-11-18 13:08:49,508 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 13:08:49,508 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 13:08:49,508 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0e3598d1a4e9129bf22e72269576449e67f0febd [2018-11-18 13:08:49,530 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 13:08:49,538 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 13:08:49,540 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 13:08:49,541 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 13:08:49,541 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 13:08:49,542 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/../../sv-benchmarks/c/systemc/transmitter.15_false-unreach-call_false-termination.cil.c [2018-11-18 13:08:49,581 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/data/963886058/e62c814fbf8a49229560e0ed4edcb27d/FLAGba83a05f5 [2018-11-18 13:08:50,004 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 13:08:50,004 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/sv-benchmarks/c/systemc/transmitter.15_false-unreach-call_false-termination.cil.c [2018-11-18 13:08:50,014 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/data/963886058/e62c814fbf8a49229560e0ed4edcb27d/FLAGba83a05f5 [2018-11-18 13:08:50,026 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/data/963886058/e62c814fbf8a49229560e0ed4edcb27d [2018-11-18 13:08:50,028 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 13:08:50,029 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 13:08:50,030 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 13:08:50,030 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 13:08:50,033 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 13:08:50,033 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,035 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5ff47436 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50, skipping insertion in model container [2018-11-18 13:08:50,035 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,041 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 13:08:50,073 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 13:08:50,264 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 13:08:50,268 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 13:08:50,320 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 13:08:50,337 INFO L195 MainTranslator]: Completed translation [2018-11-18 13:08:50,337 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50 WrapperNode [2018-11-18 13:08:50,337 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 13:08:50,338 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 13:08:50,338 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 13:08:50,338 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 13:08:50,387 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,397 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,433 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 13:08:50,433 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 13:08:50,433 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 13:08:50,433 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 13:08:50,442 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,442 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,444 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,445 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,453 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,466 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,468 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... [2018-11-18 13:08:50,472 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 13:08:50,473 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 13:08:50,473 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 13:08:50,473 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 13:08:50,473 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 01:08:50" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-18 13:08:50,528 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-18 13:08:50,528 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-18 13:08:50,528 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-18 13:08:50,528 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-18 13:08:50,528 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-18 13:08:50,528 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-18 13:08:50,529 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-18 13:08:50,529 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-18 13:08:50,529 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-18 13:08:50,529 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-18 13:08:50,529 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-18 13:08:50,529 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-18 13:08:50,529 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 13:08:50,529 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 13:08:52,142 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 13:08:52,143 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 01:08:52 BoogieIcfgContainer [2018-11-18 13:08:52,143 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 13:08:52,143 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-11-18 13:08:52,143 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-11-18 13:08:52,150 INFO L276 PluginConnector]: CodeCheck initialized [2018-11-18 13:08:52,150 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 01:08:52" (1/1) ... [2018-11-18 13:08:52,158 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 13:08:52,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:52,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 197 states and 307 transitions. [2018-11-18 13:08:52,186 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 307 transitions. [2018-11-18 13:08:52,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:52,192 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:52,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:52,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:52,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:52,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 238 states and 385 transitions. [2018-11-18 13:08:52,891 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 385 transitions. [2018-11-18 13:08:52,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:52,893 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:52,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:52,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:53,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:53,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 239 states and 385 transitions. [2018-11-18 13:08:53,258 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 385 transitions. [2018-11-18 13:08:53,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:53,259 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:53,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:53,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:53,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:53,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 240 states and 385 transitions. [2018-11-18 13:08:53,571 INFO L276 IsEmpty]: Start isEmpty. Operand 240 states and 385 transitions. [2018-11-18 13:08:53,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:53,572 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:53,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:53,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:53,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:53,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 241 states and 385 transitions. [2018-11-18 13:08:53,921 INFO L276 IsEmpty]: Start isEmpty. Operand 241 states and 385 transitions. [2018-11-18 13:08:53,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:53,926 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:53,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:53,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:54,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:54,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 242 states and 385 transitions. [2018-11-18 13:08:54,225 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 385 transitions. [2018-11-18 13:08:54,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:54,226 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:54,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:54,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:54,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:54,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 243 states and 385 transitions. [2018-11-18 13:08:54,548 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 385 transitions. [2018-11-18 13:08:54,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:54,549 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:54,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:54,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:54,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:54,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 244 states and 385 transitions. [2018-11-18 13:08:54,863 INFO L276 IsEmpty]: Start isEmpty. Operand 244 states and 385 transitions. [2018-11-18 13:08:54,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:54,864 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:54,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:54,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:55,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:55,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 245 states and 385 transitions. [2018-11-18 13:08:55,249 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 385 transitions. [2018-11-18 13:08:55,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:55,250 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:55,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:55,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:55,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:55,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 246 states and 385 transitions. [2018-11-18 13:08:55,601 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 385 transitions. [2018-11-18 13:08:55,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:55,602 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:55,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:55,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:55,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:55,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 247 states and 385 transitions. [2018-11-18 13:08:55,974 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 385 transitions. [2018-11-18 13:08:55,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:55,974 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:55,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:56,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:56,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:56,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 248 states and 385 transitions. [2018-11-18 13:08:56,333 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 385 transitions. [2018-11-18 13:08:56,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:56,334 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:56,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:56,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:56,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:56,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 249 states and 385 transitions. [2018-11-18 13:08:56,760 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 385 transitions. [2018-11-18 13:08:56,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:56,761 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:56,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:56,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:57,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:57,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 250 states and 385 transitions. [2018-11-18 13:08:57,189 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 385 transitions. [2018-11-18 13:08:57,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:57,189 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:57,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:57,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:57,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:57,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 251 states and 385 transitions. [2018-11-18 13:08:57,573 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 385 transitions. [2018-11-18 13:08:57,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:57,573 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:57,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:57,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:57,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:57,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 286 states and 456 transitions. [2018-11-18 13:08:57,966 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 456 transitions. [2018-11-18 13:08:57,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:57,967 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:57,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:58,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:58,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:58,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 287 states and 456 transitions. [2018-11-18 13:08:58,219 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 456 transitions. [2018-11-18 13:08:58,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:58,219 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:58,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:58,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:58,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:58,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 288 states and 456 transitions. [2018-11-18 13:08:58,486 INFO L276 IsEmpty]: Start isEmpty. Operand 288 states and 456 transitions. [2018-11-18 13:08:58,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:58,486 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:58,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:58,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:58,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:58,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 289 states and 456 transitions. [2018-11-18 13:08:58,692 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 456 transitions. [2018-11-18 13:08:58,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:58,692 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:58,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:58,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:58,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:58,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 290 states and 456 transitions. [2018-11-18 13:08:58,948 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 456 transitions. [2018-11-18 13:08:58,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:58,949 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:58,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:58,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:59,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:59,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 291 states and 456 transitions. [2018-11-18 13:08:59,199 INFO L276 IsEmpty]: Start isEmpty. Operand 291 states and 456 transitions. [2018-11-18 13:08:59,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:59,200 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:59,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:59,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:59,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:59,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 292 states and 456 transitions. [2018-11-18 13:08:59,389 INFO L276 IsEmpty]: Start isEmpty. Operand 292 states and 456 transitions. [2018-11-18 13:08:59,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:59,390 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:59,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:59,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:59,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:59,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 293 states and 456 transitions. [2018-11-18 13:08:59,572 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states and 456 transitions. [2018-11-18 13:08:59,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:59,572 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:59,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:59,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:59,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:59,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 294 states and 456 transitions. [2018-11-18 13:08:59,761 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 456 transitions. [2018-11-18 13:08:59,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:59,761 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:59,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:59,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:08:59,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:08:59,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 295 states and 456 transitions. [2018-11-18 13:08:59,935 INFO L276 IsEmpty]: Start isEmpty. Operand 295 states and 456 transitions. [2018-11-18 13:08:59,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:08:59,935 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:08:59,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:08:59,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:00,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:00,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 296 states and 456 transitions. [2018-11-18 13:09:00,110 INFO L276 IsEmpty]: Start isEmpty. Operand 296 states and 456 transitions. [2018-11-18 13:09:00,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:00,111 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:00,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:00,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:00,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:00,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 468 states to 297 states and 456 transitions. [2018-11-18 13:09:00,271 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 456 transitions. [2018-11-18 13:09:00,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:00,271 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:00,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:00,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:00,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:00,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 329 states and 521 transitions. [2018-11-18 13:09:00,596 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 521 transitions. [2018-11-18 13:09:00,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:00,597 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:00,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:00,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:00,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:00,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 330 states and 521 transitions. [2018-11-18 13:09:00,831 INFO L276 IsEmpty]: Start isEmpty. Operand 330 states and 521 transitions. [2018-11-18 13:09:00,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:00,832 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:00,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:00,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:01,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:01,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 331 states and 521 transitions. [2018-11-18 13:09:01,089 INFO L276 IsEmpty]: Start isEmpty. Operand 331 states and 521 transitions. [2018-11-18 13:09:01,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:01,089 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:01,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:01,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:01,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:01,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 332 states and 521 transitions. [2018-11-18 13:09:01,305 INFO L276 IsEmpty]: Start isEmpty. Operand 332 states and 521 transitions. [2018-11-18 13:09:01,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:01,306 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:01,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:01,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:01,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:01,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 333 states and 521 transitions. [2018-11-18 13:09:01,583 INFO L276 IsEmpty]: Start isEmpty. Operand 333 states and 521 transitions. [2018-11-18 13:09:01,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:01,584 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:01,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:01,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:01,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:01,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 334 states and 521 transitions. [2018-11-18 13:09:01,873 INFO L276 IsEmpty]: Start isEmpty. Operand 334 states and 521 transitions. [2018-11-18 13:09:01,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:01,874 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:01,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:01,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:02,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:02,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 335 states and 521 transitions. [2018-11-18 13:09:02,084 INFO L276 IsEmpty]: Start isEmpty. Operand 335 states and 521 transitions. [2018-11-18 13:09:02,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:02,085 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:02,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:02,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:02,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:02,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 336 states and 521 transitions. [2018-11-18 13:09:02,310 INFO L276 IsEmpty]: Start isEmpty. Operand 336 states and 521 transitions. [2018-11-18 13:09:02,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:02,311 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:02,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:02,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:02,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:02,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 337 states and 521 transitions. [2018-11-18 13:09:02,534 INFO L276 IsEmpty]: Start isEmpty. Operand 337 states and 521 transitions. [2018-11-18 13:09:02,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:02,535 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:02,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:02,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:02,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:02,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 338 states and 521 transitions. [2018-11-18 13:09:02,783 INFO L276 IsEmpty]: Start isEmpty. Operand 338 states and 521 transitions. [2018-11-18 13:09:02,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:02,783 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:02,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:02,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:03,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:03,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 539 states to 339 states and 521 transitions. [2018-11-18 13:09:03,016 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 521 transitions. [2018-11-18 13:09:03,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:03,017 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:03,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:03,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:03,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:03,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 365 states and 574 transitions. [2018-11-18 13:09:03,324 INFO L276 IsEmpty]: Start isEmpty. Operand 365 states and 574 transitions. [2018-11-18 13:09:03,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:03,325 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:03,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:03,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:03,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:03,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 366 states and 574 transitions. [2018-11-18 13:09:03,572 INFO L276 IsEmpty]: Start isEmpty. Operand 366 states and 574 transitions. [2018-11-18 13:09:03,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:03,573 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:03,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:03,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:03,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:03,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 367 states and 574 transitions. [2018-11-18 13:09:03,817 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 574 transitions. [2018-11-18 13:09:03,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:03,817 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:03,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:03,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:04,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:04,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 368 states and 574 transitions. [2018-11-18 13:09:04,065 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 574 transitions. [2018-11-18 13:09:04,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:04,065 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:04,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:04,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:04,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:04,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 369 states and 574 transitions. [2018-11-18 13:09:04,303 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 574 transitions. [2018-11-18 13:09:04,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:04,303 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:04,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:04,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:04,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:04,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 370 states and 574 transitions. [2018-11-18 13:09:04,546 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 574 transitions. [2018-11-18 13:09:04,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:04,546 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:04,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:04,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:04,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:04,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 371 states and 574 transitions. [2018-11-18 13:09:04,832 INFO L276 IsEmpty]: Start isEmpty. Operand 371 states and 574 transitions. [2018-11-18 13:09:04,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:04,833 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:04,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:04,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:05,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:05,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 372 states and 574 transitions. [2018-11-18 13:09:05,068 INFO L276 IsEmpty]: Start isEmpty. Operand 372 states and 574 transitions. [2018-11-18 13:09:05,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:05,069 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:05,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:05,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:05,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:05,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 373 states and 574 transitions. [2018-11-18 13:09:05,332 INFO L276 IsEmpty]: Start isEmpty. Operand 373 states and 574 transitions. [2018-11-18 13:09:05,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:05,332 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:05,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:05,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:05,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:05,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 393 states and 615 transitions. [2018-11-18 13:09:05,658 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 615 transitions. [2018-11-18 13:09:05,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:05,659 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:05,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:05,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:05,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:05,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 394 states and 615 transitions. [2018-11-18 13:09:05,910 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 615 transitions. [2018-11-18 13:09:05,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:05,910 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:05,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:05,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:06,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:06,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 395 states and 615 transitions. [2018-11-18 13:09:06,159 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 615 transitions. [2018-11-18 13:09:06,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:06,160 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:06,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:06,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:06,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:06,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 396 states and 615 transitions. [2018-11-18 13:09:06,407 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 615 transitions. [2018-11-18 13:09:06,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:06,408 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:06,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:06,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:06,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:06,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 397 states and 615 transitions. [2018-11-18 13:09:06,659 INFO L276 IsEmpty]: Start isEmpty. Operand 397 states and 615 transitions. [2018-11-18 13:09:06,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:06,660 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:06,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:06,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:06,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:06,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 398 states and 615 transitions. [2018-11-18 13:09:06,924 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states and 615 transitions. [2018-11-18 13:09:06,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:06,924 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:06,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:06,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:07,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:07,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 399 states and 615 transitions. [2018-11-18 13:09:07,187 INFO L276 IsEmpty]: Start isEmpty. Operand 399 states and 615 transitions. [2018-11-18 13:09:07,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:07,188 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:07,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:07,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:07,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:07,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 413 states and 644 transitions. [2018-11-18 13:09:07,533 INFO L276 IsEmpty]: Start isEmpty. Operand 413 states and 644 transitions. [2018-11-18 13:09:07,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:07,534 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:07,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:07,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:07,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:07,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 414 states and 644 transitions. [2018-11-18 13:09:07,774 INFO L276 IsEmpty]: Start isEmpty. Operand 414 states and 644 transitions. [2018-11-18 13:09:07,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:07,774 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:07,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:07,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:08,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:08,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 415 states and 644 transitions. [2018-11-18 13:09:08,016 INFO L276 IsEmpty]: Start isEmpty. Operand 415 states and 644 transitions. [2018-11-18 13:09:08,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:08,017 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:08,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:08,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:08,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:08,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 416 states and 644 transitions. [2018-11-18 13:09:08,260 INFO L276 IsEmpty]: Start isEmpty. Operand 416 states and 644 transitions. [2018-11-18 13:09:08,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:08,260 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:08,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:08,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:08,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:08,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 417 states and 644 transitions. [2018-11-18 13:09:08,506 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 644 transitions. [2018-11-18 13:09:08,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:08,506 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:08,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:08,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:08,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:08,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 703 states to 425 states and 661 transitions. [2018-11-18 13:09:08,823 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 661 transitions. [2018-11-18 13:09:08,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:08,823 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:08,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:08,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:09,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:09,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 703 states to 426 states and 661 transitions. [2018-11-18 13:09:09,038 INFO L276 IsEmpty]: Start isEmpty. Operand 426 states and 661 transitions. [2018-11-18 13:09:09,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:09,038 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:09,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:09,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:09,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:09,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 703 states to 427 states and 661 transitions. [2018-11-18 13:09:09,269 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 661 transitions. [2018-11-18 13:09:09,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:09,269 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:09,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:09,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:09,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:09,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 720 states to 432 states and 672 transitions. [2018-11-18 13:09:09,572 INFO L276 IsEmpty]: Start isEmpty. Operand 432 states and 672 transitions. [2018-11-18 13:09:09,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:09,573 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:09,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:09,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:09,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:09,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 720 states to 433 states and 672 transitions. [2018-11-18 13:09:09,766 INFO L276 IsEmpty]: Start isEmpty. Operand 433 states and 672 transitions. [2018-11-18 13:09:09,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:09,767 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:09,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:09,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:11,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:11,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 836 states to 484 states and 772 transitions. [2018-11-18 13:09:11,231 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 772 transitions. [2018-11-18 13:09:11,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:11,232 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:11,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:11,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:12,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:12,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 849 states to 486 states and 777 transitions. [2018-11-18 13:09:12,118 INFO L276 IsEmpty]: Start isEmpty. Operand 486 states and 777 transitions. [2018-11-18 13:09:12,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:12,119 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:12,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:12,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:13,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:13,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 880 states to 497 states and 800 transitions. [2018-11-18 13:09:13,810 INFO L276 IsEmpty]: Start isEmpty. Operand 497 states and 800 transitions. [2018-11-18 13:09:13,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:13,810 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:13,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:13,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:16,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:16,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 923 states to 514 states and 835 transitions. [2018-11-18 13:09:16,508 INFO L276 IsEmpty]: Start isEmpty. Operand 514 states and 835 transitions. [2018-11-18 13:09:16,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:16,508 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:16,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:16,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:20,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:20,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 978 states to 537 states and 882 transitions. [2018-11-18 13:09:20,597 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 882 transitions. [2018-11-18 13:09:20,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:20,598 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:20,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:20,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:26,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:26,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1045 states to 566 states and 941 transitions. [2018-11-18 13:09:26,467 INFO L276 IsEmpty]: Start isEmpty. Operand 566 states and 941 transitions. [2018-11-18 13:09:26,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-11-18 13:09:26,468 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:26,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:26,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:35,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:35,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1130 states to 604 states and 1018 transitions. [2018-11-18 13:09:35,265 INFO L276 IsEmpty]: Start isEmpty. Operand 604 states and 1018 transitions. [2018-11-18 13:09:35,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-18 13:09:35,266 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:35,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:35,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:35,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:35,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1125 states to 602 states and 1013 transitions. [2018-11-18 13:09:35,441 INFO L276 IsEmpty]: Start isEmpty. Operand 602 states and 1013 transitions. [2018-11-18 13:09:35,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-18 13:09:35,442 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:35,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:35,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:35,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:35,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1126 states to 603 states and 1014 transitions. [2018-11-18 13:09:35,702 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 1014 transitions. [2018-11-18 13:09:35,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-18 13:09:35,703 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:35,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:35,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:36,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:36,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1127 states to 604 states and 1015 transitions. [2018-11-18 13:09:36,027 INFO L276 IsEmpty]: Start isEmpty. Operand 604 states and 1015 transitions. [2018-11-18 13:09:36,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-18 13:09:36,028 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:36,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:36,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:36,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:36,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1128 states to 605 states and 1016 transitions. [2018-11-18 13:09:36,366 INFO L276 IsEmpty]: Start isEmpty. Operand 605 states and 1016 transitions. [2018-11-18 13:09:36,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-18 13:09:36,366 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:36,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:36,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:36,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:36,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 606 states and 1017 transitions. [2018-11-18 13:09:36,736 INFO L276 IsEmpty]: Start isEmpty. Operand 606 states and 1017 transitions. [2018-11-18 13:09:36,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-18 13:09:36,737 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:36,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:36,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:37,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:37,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1130 states to 607 states and 1018 transitions. [2018-11-18 13:09:37,120 INFO L276 IsEmpty]: Start isEmpty. Operand 607 states and 1018 transitions. [2018-11-18 13:09:37,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-18 13:09:37,120 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:37,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:37,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:37,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:37,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1131 states to 608 states and 1019 transitions. [2018-11-18 13:09:37,471 INFO L276 IsEmpty]: Start isEmpty. Operand 608 states and 1019 transitions. [2018-11-18 13:09:37,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-18 13:09:37,471 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:37,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 13:09:37,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 13:09:37,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 13:09:37,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1132 states to 609 states and 1020 transitions. [2018-11-18 13:09:37,831 INFO L276 IsEmpty]: Start isEmpty. Operand 609 states and 1020 transitions. [2018-11-18 13:09:37,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-18 13:09:37,832 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 13:09:37,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 13:09:37,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 13:09:38,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 13:09:38,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 13:09:38,208 WARN L493 CodeCheckObserver]: This program is UNSAFE, Check terminated with 79 iterations. [2018-11-18 13:09:38,322 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 18.11 01:09:38 ImpRootNode [2018-11-18 13:09:38,322 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2018-11-18 13:09:38,322 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 13:09:38,322 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 13:09:38,322 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 13:09:38,323 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 01:08:52" (3/4) ... [2018-11-18 13:09:38,326 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 13:09:38,439 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_9b09ea9a-f1ec-4351-9f04-1813daf4c499/bin-2019/ukojak/witness.graphml [2018-11-18 13:09:38,440 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 13:09:38,441 INFO L168 Benchmark]: Toolchain (without parser) took 48411.96 ms. Allocated memory was 1.0 GB in the beginning and 2.1 GB in the end (delta: 1.0 GB). Free memory was 959.2 MB in the beginning and 1.0 GB in the end (delta: -58.3 MB). Peak memory consumption was 969.3 MB. Max. memory is 11.5 GB. [2018-11-18 13:09:38,442 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 13:09:38,442 INFO L168 Benchmark]: CACSL2BoogieTranslator took 307.18 ms. Allocated memory is still 1.0 GB. Free memory was 956.6 MB in the beginning and 929.7 MB in the end (delta: 26.8 MB). Peak memory consumption was 26.8 MB. Max. memory is 11.5 GB. [2018-11-18 13:09:38,442 INFO L168 Benchmark]: Boogie Procedure Inliner took 95.27 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 169.9 MB). Free memory was 929.7 MB in the beginning and 1.2 GB in the end (delta: -230.8 MB). Peak memory consumption was 19.1 MB. Max. memory is 11.5 GB. [2018-11-18 13:09:38,442 INFO L168 Benchmark]: Boogie Preprocessor took 39.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. [2018-11-18 13:09:38,443 INFO L168 Benchmark]: RCFGBuilder took 1670.27 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 72.4 MB). Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: -62.9 MB). Peak memory consumption was 323.3 MB. Max. memory is 11.5 GB. [2018-11-18 13:09:38,443 INFO L168 Benchmark]: CodeCheck took 46178.86 ms. Allocated memory was 1.3 GB in the beginning and 2.1 GB in the end (delta: 785.4 MB). Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 179.3 MB). Peak memory consumption was 964.7 MB. Max. memory is 11.5 GB. [2018-11-18 13:09:38,443 INFO L168 Benchmark]: Witness Printer took 117.43 ms. Allocated memory is still 2.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 23.3 MB). Peak memory consumption was 23.3 MB. Max. memory is 11.5 GB. [2018-11-18 13:09:38,445 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 419 locations, 1 error locations. UNSAFE Result, 46.0s OverallTime, 79 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 487844864 SDtfs, 822072312 SDslu, -1480280072 SDs, 0 SdLazy, 419863036 SolverSat, 279014912 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 48825 GetRequests, 39087 SyntacticMatches, 9374 SemanticMatches, 364 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 225409 ImplicationChecksByTransitivity, 42.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, traceCheckStatistics: 0.2s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 2.1s InterpolantComputationTime, 5460 NumberOfCodeBlocks, 5460 NumberOfCodeBlocksAsserted, 79 NumberOfCheckSat, 5312 ConstructedInterpolants, 0 QuantifiedInterpolants, 723306 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 78 InterpolantComputations, 78 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int t9_pc = 0; [L25] int t10_pc = 0; [L26] int t11_pc = 0; [L27] int t12_pc = 0; [L28] int t13_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int t5_st ; [L35] int t6_st ; [L36] int t7_st ; [L37] int t8_st ; [L38] int t9_st ; [L39] int t10_st ; [L40] int t11_st ; [L41] int t12_st ; [L42] int t13_st ; [L43] int m_i ; [L44] int t1_i ; [L45] int t2_i ; [L46] int t3_i ; [L47] int t4_i ; [L48] int t5_i ; [L49] int t6_i ; [L50] int t7_i ; [L51] int t8_i ; [L52] int t9_i ; [L53] int t10_i ; [L54] int t11_i ; [L55] int t12_i ; [L56] int t13_i ; [L57] int M_E = 2; [L58] int T1_E = 2; [L59] int T2_E = 2; [L60] int T3_E = 2; [L61] int T4_E = 2; [L62] int T5_E = 2; [L63] int T6_E = 2; [L64] int T7_E = 2; [L65] int T8_E = 2; [L66] int T9_E = 2; [L67] int T10_E = 2; [L68] int T11_E = 2; [L69] int T12_E = 2; [L70] int T13_E = 2; [L71] int E_1 = 2; [L72] int E_2 = 2; [L73] int E_3 = 2; [L74] int E_4 = 2; [L75] int E_5 = 2; [L76] int E_6 = 2; [L77] int E_7 = 2; [L78] int E_8 = 2; [L79] int E_9 = 2; [L80] int E_10 = 2; [L81] int E_11 = 2; [L82] int E_12 = 2; [L83] int E_13 = 2; [L1927] int __retres1 ; [L1931] CALL init_model() [L1830] m_i = 1 [L1831] t1_i = 1 [L1832] t2_i = 1 [L1833] t3_i = 1 [L1834] t4_i = 1 [L1835] t5_i = 1 [L1836] t6_i = 1 [L1837] t7_i = 1 [L1838] t8_i = 1 [L1839] t9_i = 1 [L1840] t10_i = 1 [L1841] t11_i = 1 [L1842] t12_i = 1 [L1843] RET t13_i = 1 [L1931] init_model() [L1932] CALL start_simulation() [L1868] int kernel_st ; [L1869] int tmp ; [L1870] int tmp___0 ; [L1874] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1875] FCALL update_channels() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1876] CALL init_threads() [L871] COND TRUE m_i == 1 [L872] m_st = 0 [L876] COND TRUE t1_i == 1 [L877] t1_st = 0 [L881] COND TRUE t2_i == 1 [L882] t2_st = 0 [L886] COND TRUE t3_i == 1 [L887] t3_st = 0 [L891] COND TRUE t4_i == 1 [L892] t4_st = 0 [L896] COND TRUE t5_i == 1 [L897] t5_st = 0 [L901] COND TRUE t6_i == 1 [L902] t6_st = 0 [L906] COND TRUE t7_i == 1 [L907] t7_st = 0 [L911] COND TRUE t8_i == 1 [L912] t8_st = 0 [L916] COND TRUE t9_i == 1 [L917] t9_st = 0 [L921] COND TRUE t10_i == 1 [L922] t10_st = 0 [L926] COND TRUE t11_i == 1 [L927] t11_st = 0 [L931] COND TRUE t12_i == 1 [L932] t12_st = 0 [L936] COND TRUE t13_i == 1 [L937] RET t13_st = 0 [L1876] init_threads() [L1877] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1248] COND FALSE !(M_E == 0) [L1253] COND FALSE !(T1_E == 0) [L1258] COND FALSE !(T2_E == 0) [L1263] COND FALSE !(T3_E == 0) [L1268] COND FALSE !(T4_E == 0) [L1273] COND FALSE !(T5_E == 0) [L1278] COND FALSE !(T6_E == 0) [L1283] COND FALSE !(T7_E == 0) [L1288] COND FALSE !(T8_E == 0) [L1293] COND FALSE !(T9_E == 0) [L1298] COND FALSE !(T10_E == 0) [L1303] COND FALSE !(T11_E == 0) [L1308] COND FALSE !(T12_E == 0) [L1313] COND FALSE !(T13_E == 0) [L1318] COND FALSE !(E_1 == 0) [L1323] COND FALSE !(E_2 == 0) [L1328] COND FALSE !(E_3 == 0) [L1333] COND FALSE !(E_4 == 0) [L1338] COND FALSE !(E_5 == 0) [L1343] COND FALSE !(E_6 == 0) [L1348] COND FALSE !(E_7 == 0) [L1353] COND FALSE !(E_8 == 0) [L1358] COND FALSE !(E_9 == 0) [L1363] COND FALSE !(E_10 == 0) [L1368] COND FALSE !(E_11 == 0) [L1373] COND FALSE !(E_12 == 0) [L1378] COND FALSE, RET !(E_13 == 0) [L1877] fire_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1878] CALL activate_threads() VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1531] int tmp ; [L1532] int tmp___0 ; [L1533] int tmp___1 ; [L1534] int tmp___2 ; [L1535] int tmp___3 ; [L1536] int tmp___4 ; [L1537] int tmp___5 ; [L1538] int tmp___6 ; [L1539] int tmp___7 ; [L1540] int tmp___8 ; [L1541] int tmp___9 ; [L1542] int tmp___10 ; [L1543] int tmp___11 ; [L1544] int tmp___12 ; [L1548] CALL, EXPR is_master_triggered() [L594] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L597] COND FALSE !(m_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L607] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L609] RET return (__retres1); [L1548] EXPR is_master_triggered() [L1548] tmp = is_master_triggered() [L1550] COND FALSE !(\read(tmp)) [L1556] CALL, EXPR is_transmit1_triggered() [L613] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L616] COND FALSE !(t1_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L626] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L628] RET return (__retres1); [L1556] EXPR is_transmit1_triggered() [L1556] tmp___0 = is_transmit1_triggered() [L1558] COND FALSE !(\read(tmp___0)) [L1564] CALL, EXPR is_transmit2_triggered() [L632] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L635] COND FALSE !(t2_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L645] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L647] RET return (__retres1); [L1564] EXPR is_transmit2_triggered() [L1564] tmp___1 = is_transmit2_triggered() [L1566] COND FALSE !(\read(tmp___1)) [L1572] CALL, EXPR is_transmit3_triggered() [L651] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L654] COND FALSE !(t3_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L664] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L666] RET return (__retres1); [L1572] EXPR is_transmit3_triggered() [L1572] tmp___2 = is_transmit3_triggered() [L1574] COND FALSE !(\read(tmp___2)) [L1580] CALL, EXPR is_transmit4_triggered() [L670] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L673] COND FALSE !(t4_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L683] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L685] RET return (__retres1); [L1580] EXPR is_transmit4_triggered() [L1580] tmp___3 = is_transmit4_triggered() [L1582] COND FALSE !(\read(tmp___3)) [L1588] CALL, EXPR is_transmit5_triggered() [L689] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L692] COND FALSE !(t5_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L702] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L704] RET return (__retres1); [L1588] EXPR is_transmit5_triggered() [L1588] tmp___4 = is_transmit5_triggered() [L1590] COND FALSE !(\read(tmp___4)) [L1596] CALL, EXPR is_transmit6_triggered() [L708] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L711] COND FALSE !(t6_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L721] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L723] RET return (__retres1); [L1596] EXPR is_transmit6_triggered() [L1596] tmp___5 = is_transmit6_triggered() [L1598] COND FALSE !(\read(tmp___5)) [L1604] CALL, EXPR is_transmit7_triggered() [L727] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L730] COND FALSE !(t7_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L740] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L742] RET return (__retres1); [L1604] EXPR is_transmit7_triggered() [L1604] tmp___6 = is_transmit7_triggered() [L1606] COND FALSE !(\read(tmp___6)) [L1612] CALL, EXPR is_transmit8_triggered() [L746] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L749] COND FALSE !(t8_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L759] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L761] RET return (__retres1); [L1612] EXPR is_transmit8_triggered() [L1612] tmp___7 = is_transmit8_triggered() [L1614] COND FALSE !(\read(tmp___7)) [L1620] CALL, EXPR is_transmit9_triggered() [L765] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L768] COND FALSE !(t9_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L778] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L780] RET return (__retres1); [L1620] EXPR is_transmit9_triggered() [L1620] tmp___8 = is_transmit9_triggered() [L1622] COND FALSE !(\read(tmp___8)) [L1628] CALL, EXPR is_transmit10_triggered() [L784] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L787] COND FALSE !(t10_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L797] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L799] RET return (__retres1); [L1628] EXPR is_transmit10_triggered() [L1628] tmp___9 = is_transmit10_triggered() [L1630] COND FALSE !(\read(tmp___9)) [L1636] CALL, EXPR is_transmit11_triggered() [L803] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L806] COND FALSE !(t11_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L816] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L818] RET return (__retres1); [L1636] EXPR is_transmit11_triggered() [L1636] tmp___10 = is_transmit11_triggered() [L1638] COND FALSE !(\read(tmp___10)) [L1644] CALL, EXPR is_transmit12_triggered() [L822] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L825] COND FALSE !(t12_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L835] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L837] RET return (__retres1); [L1644] EXPR is_transmit12_triggered() [L1644] tmp___11 = is_transmit12_triggered() [L1646] COND FALSE !(\read(tmp___11)) [L1652] CALL, EXPR is_transmit13_triggered() [L841] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L844] COND FALSE !(t13_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L854] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L856] RET return (__retres1); [L1652] EXPR is_transmit13_triggered() [L1652] tmp___12 = is_transmit13_triggered() [L1654] COND FALSE, RET !(\read(tmp___12)) [L1878] activate_threads() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1879] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1391] COND FALSE !(M_E == 1) [L1396] COND FALSE !(T1_E == 1) [L1401] COND FALSE !(T2_E == 1) [L1406] COND FALSE !(T3_E == 1) [L1411] COND FALSE !(T4_E == 1) [L1416] COND FALSE !(T5_E == 1) [L1421] COND FALSE !(T6_E == 1) [L1426] COND FALSE !(T7_E == 1) [L1431] COND FALSE !(T8_E == 1) [L1436] COND FALSE !(T9_E == 1) [L1441] COND FALSE !(T10_E == 1) [L1446] COND FALSE !(T11_E == 1) [L1451] COND FALSE !(T12_E == 1) [L1456] COND FALSE !(T13_E == 1) [L1461] COND FALSE !(E_1 == 1) [L1466] COND FALSE !(E_2 == 1) [L1471] COND FALSE !(E_3 == 1) [L1476] COND FALSE !(E_4 == 1) [L1481] COND FALSE !(E_5 == 1) [L1486] COND FALSE !(E_6 == 1) [L1491] COND FALSE !(E_7 == 1) [L1496] COND FALSE !(E_8 == 1) [L1501] COND FALSE !(E_9 == 1) [L1506] COND FALSE !(E_10 == 1) [L1511] COND FALSE !(E_11 == 1) [L1516] COND FALSE !(E_12 == 1) [L1521] COND FALSE, RET !(E_13 == 1) [L1879] reset_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1882] COND TRUE 1 [L1885] kernel_st = 1 [L1886] CALL eval() [L1027] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1031] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1034] CALL, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L946] int __retres1 ; [L949] COND TRUE m_st == 0 [L950] __retres1 = 1 [L1022] RET return (__retres1); [L1034] EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1034] tmp = exists_runnable_thread() [L1036] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE m_st == 0 [L1042] int tmp_ndt_1; [L1043] tmp_ndt_1 = __VERIFIER_nondet_int() [L1044] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1055] COND TRUE t1_st == 0 [L1056] int tmp_ndt_2; [L1057] tmp_ndt_2 = __VERIFIER_nondet_int() [L1058] COND FALSE !(\read(tmp_ndt_2)) [L1064] CALL error() [L11] __VERIFIER_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 307.18 ms. Allocated memory is still 1.0 GB. Free memory was 956.6 MB in the beginning and 929.7 MB in the end (delta: 26.8 MB). Peak memory consumption was 26.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 95.27 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 169.9 MB). Free memory was 929.7 MB in the beginning and 1.2 GB in the end (delta: -230.8 MB). Peak memory consumption was 19.1 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 39.36 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 3.3 MB). Peak memory consumption was 3.3 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1670.27 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 72.4 MB). Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: -62.9 MB). Peak memory consumption was 323.3 MB. Max. memory is 11.5 GB. * CodeCheck took 46178.86 ms. Allocated memory was 1.3 GB in the beginning and 2.1 GB in the end (delta: 785.4 MB). Free memory was 1.2 GB in the beginning and 1.0 GB in the end (delta: 179.3 MB). Peak memory consumption was 964.7 MB. Max. memory is 11.5 GB. * Witness Printer took 117.43 ms. Allocated memory is still 2.1 GB. Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 23.3 MB). Peak memory consumption was 23.3 MB. Max. memory is 11.5 GB. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...