./Ultimate.py --spec ../../sv-benchmarks/c/ReachSafety.prp --file ../../sv-benchmarks/c/systemc/transmitter.16_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.16_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05a526ca9d0710db502cdfc74677e2807f071449 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 12:22:39,600 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 12:22:39,601 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 12:22:39,610 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 12:22:39,610 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 12:22:39,611 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 12:22:39,611 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 12:22:39,613 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 12:22:39,615 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 12:22:39,615 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 12:22:39,616 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 12:22:39,616 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 12:22:39,617 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 12:22:39,618 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 12:22:39,619 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 12:22:39,619 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 12:22:39,620 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 12:22:39,621 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 12:22:39,623 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 12:22:39,624 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 12:22:39,625 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 12:22:39,626 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 12:22:39,628 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 12:22:39,628 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 12:22:39,629 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 12:22:39,629 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 12:22:39,631 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 12:22:39,631 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 12:22:39,632 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 12:22:39,633 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 12:22:39,633 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 12:22:39,633 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 12:22:39,634 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 12:22:39,634 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 12:22:39,635 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 12:22:39,636 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 12:22:39,636 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf [2018-11-18 12:22:39,645 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 12:22:39,645 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 12:22:39,646 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-18 12:22:39,646 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-11-18 12:22:39,646 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 12:22:39,646 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 12:22:39,646 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 12:22:39,647 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 12:22:39,647 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 12:22:39,647 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 12:22:39,647 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 12:22:39,647 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-18 12:22:39,647 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-18 12:22:39,647 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-18 12:22:39,647 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 12:22:39,648 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 12:22:39,648 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 12:22:39,648 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-18 12:22:39,648 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-11-18 12:22:39,648 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-11-18 12:22:39,648 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 12:22:39,648 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-18 12:22:39,648 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-18 12:22:39,649 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 12:22:39,649 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-18 12:22:39,649 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-18 12:22:39,649 INFO L133 SettingsManager]: * Trace refinement strategy=PENGUIN [2018-11-18 12:22:39,649 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-18 12:22:39,649 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-18 12:22:39,649 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05a526ca9d0710db502cdfc74677e2807f071449 [2018-11-18 12:22:39,679 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 12:22:39,687 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 12:22:39,690 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 12:22:39,691 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 12:22:39,691 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 12:22:39,692 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/../../sv-benchmarks/c/systemc/transmitter.16_false-unreach-call_false-termination.cil.c [2018-11-18 12:22:39,736 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/data/615385af5/cd833679fcc1470f9a62308639b0d0b0/FLAG87fd94030 [2018-11-18 12:22:40,103 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 12:22:40,104 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/sv-benchmarks/c/systemc/transmitter.16_false-unreach-call_false-termination.cil.c [2018-11-18 12:22:40,116 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/data/615385af5/cd833679fcc1470f9a62308639b0d0b0/FLAG87fd94030 [2018-11-18 12:22:40,128 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/data/615385af5/cd833679fcc1470f9a62308639b0d0b0 [2018-11-18 12:22:40,135 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 12:22:40,136 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 12:22:40,136 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 12:22:40,137 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 12:22:40,140 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 12:22:40,140 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,143 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@132b5adf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40, skipping insertion in model container [2018-11-18 12:22:40,143 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,151 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 12:22:40,192 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 12:22:40,435 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 12:22:40,440 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 12:22:40,497 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 12:22:40,518 INFO L195 MainTranslator]: Completed translation [2018-11-18 12:22:40,518 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40 WrapperNode [2018-11-18 12:22:40,518 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 12:22:40,519 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 12:22:40,519 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 12:22:40,519 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 12:22:40,578 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,590 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,632 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 12:22:40,632 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 12:22:40,632 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 12:22:40,633 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 12:22:40,639 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,639 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,642 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,642 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,652 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,669 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,672 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... [2018-11-18 12:22:40,677 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 12:22:40,677 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 12:22:40,677 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 12:22:40,678 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 12:22:40,678 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 12:22:40" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-18 12:22:40,740 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-18 12:22:40,740 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-18 12:22:40,741 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2018-11-18 12:22:40,741 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2018-11-18 12:22:40,741 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-18 12:22:40,741 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-18 12:22:40,741 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-18 12:22:40,741 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-18 12:22:40,741 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-18 12:22:40,741 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-18 12:22:40,742 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-18 12:22:40,742 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-18 12:22:40,742 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 12:22:40,742 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 12:22:44,550 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 12:22:44,551 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 12:22:44 BoogieIcfgContainer [2018-11-18 12:22:44,551 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 12:22:44,551 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-11-18 12:22:44,551 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-11-18 12:22:44,558 INFO L276 PluginConnector]: CodeCheck initialized [2018-11-18 12:22:44,558 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 12:22:44" (1/1) ... [2018-11-18 12:22:44,566 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 12:22:44,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:44,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 313 states to 201 states and 313 transitions. [2018-11-18 12:22:44,597 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 313 transitions. [2018-11-18 12:22:44,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:44,602 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:44,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:44,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:45,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:45,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 245 states and 397 transitions. [2018-11-18 12:22:45,532 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 397 transitions. [2018-11-18 12:22:45,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:45,533 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:45,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:45,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:46,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:46,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 246 states and 397 transitions. [2018-11-18 12:22:46,044 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 397 transitions. [2018-11-18 12:22:46,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:46,045 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:46,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:46,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:46,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:46,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 247 states and 397 transitions. [2018-11-18 12:22:46,881 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 397 transitions. [2018-11-18 12:22:46,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:46,884 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:46,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:46,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:47,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:47,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 248 states and 397 transitions. [2018-11-18 12:22:47,272 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 397 transitions. [2018-11-18 12:22:47,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:47,275 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:47,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:47,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:47,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:47,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 249 states and 397 transitions. [2018-11-18 12:22:47,820 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 397 transitions. [2018-11-18 12:22:47,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:47,822 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:47,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:47,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:48,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:48,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 250 states and 397 transitions. [2018-11-18 12:22:48,259 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 397 transitions. [2018-11-18 12:22:48,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:48,261 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:48,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:48,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:48,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:48,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 251 states and 397 transitions. [2018-11-18 12:22:48,743 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 397 transitions. [2018-11-18 12:22:48,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:48,743 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:48,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:48,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:49,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:49,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 252 states and 397 transitions. [2018-11-18 12:22:49,579 INFO L276 IsEmpty]: Start isEmpty. Operand 252 states and 397 transitions. [2018-11-18 12:22:49,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:49,580 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:49,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:49,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:50,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:50,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 253 states and 397 transitions. [2018-11-18 12:22:50,099 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 397 transitions. [2018-11-18 12:22:50,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:50,100 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:50,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:50,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:50,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:50,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 254 states and 397 transitions. [2018-11-18 12:22:50,630 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 397 transitions. [2018-11-18 12:22:50,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:50,631 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:50,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:50,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:51,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:51,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 255 states and 397 transitions. [2018-11-18 12:22:51,082 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 397 transitions. [2018-11-18 12:22:51,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:51,083 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:51,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:51,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:51,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:51,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 256 states and 397 transitions. [2018-11-18 12:22:51,743 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 397 transitions. [2018-11-18 12:22:51,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:51,743 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:51,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:51,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:52,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:52,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 257 states and 397 transitions. [2018-11-18 12:22:52,189 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 397 transitions. [2018-11-18 12:22:52,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:52,189 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:52,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:52,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:52,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:52,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 258 states and 397 transitions. [2018-11-18 12:22:52,668 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 397 transitions. [2018-11-18 12:22:52,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:52,669 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:52,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:52,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:54,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:54,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 259 states and 397 transitions. [2018-11-18 12:22:54,166 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 397 transitions. [2018-11-18 12:22:54,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:54,167 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:54,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:54,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:54,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:54,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 297 states and 474 transitions. [2018-11-18 12:22:54,763 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 474 transitions. [2018-11-18 12:22:54,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:54,763 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:54,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:54,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:55,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:55,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 298 states and 474 transitions. [2018-11-18 12:22:55,249 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 474 transitions. [2018-11-18 12:22:55,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:55,250 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:55,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:55,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:55,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:55,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 299 states and 474 transitions. [2018-11-18 12:22:55,774 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 474 transitions. [2018-11-18 12:22:55,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:55,775 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:55,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:55,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:56,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:56,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 300 states and 474 transitions. [2018-11-18 12:22:56,224 INFO L276 IsEmpty]: Start isEmpty. Operand 300 states and 474 transitions. [2018-11-18 12:22:56,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:56,225 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:56,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:56,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:56,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:56,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 301 states and 474 transitions. [2018-11-18 12:22:56,530 INFO L276 IsEmpty]: Start isEmpty. Operand 301 states and 474 transitions. [2018-11-18 12:22:56,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:56,530 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:56,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:56,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:56,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:56,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 302 states and 474 transitions. [2018-11-18 12:22:56,794 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 474 transitions. [2018-11-18 12:22:56,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:56,794 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:56,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:56,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:57,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:57,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 303 states and 474 transitions. [2018-11-18 12:22:57,209 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 474 transitions. [2018-11-18 12:22:57,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:57,209 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:57,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:57,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:57,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:57,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 304 states and 474 transitions. [2018-11-18 12:22:57,590 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 474 transitions. [2018-11-18 12:22:57,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:57,591 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:57,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:57,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:57,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:57,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 305 states and 474 transitions. [2018-11-18 12:22:57,811 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 474 transitions. [2018-11-18 12:22:57,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:57,811 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:57,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:57,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:58,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:58,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 306 states and 474 transitions. [2018-11-18 12:22:58,032 INFO L276 IsEmpty]: Start isEmpty. Operand 306 states and 474 transitions. [2018-11-18 12:22:58,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:58,033 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:58,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:58,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:58,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:58,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 307 states and 474 transitions. [2018-11-18 12:22:58,323 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 474 transitions. [2018-11-18 12:22:58,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:58,324 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:58,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:58,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:58,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:58,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 308 states and 474 transitions. [2018-11-18 12:22:58,522 INFO L276 IsEmpty]: Start isEmpty. Operand 308 states and 474 transitions. [2018-11-18 12:22:58,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:58,523 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:58,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:58,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:58,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:58,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 486 states to 309 states and 474 transitions. [2018-11-18 12:22:58,715 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 474 transitions. [2018-11-18 12:22:58,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:58,716 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:58,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:58,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:22:59,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:22:59,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 344 states and 545 transitions. [2018-11-18 12:22:59,235 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 545 transitions. [2018-11-18 12:22:59,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:22:59,235 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:22:59,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:22:59,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:00,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:00,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 345 states and 545 transitions. [2018-11-18 12:23:00,005 INFO L276 IsEmpty]: Start isEmpty. Operand 345 states and 545 transitions. [2018-11-18 12:23:00,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:00,006 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:00,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:00,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:00,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:00,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 346 states and 545 transitions. [2018-11-18 12:23:00,350 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 545 transitions. [2018-11-18 12:23:00,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:00,352 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:00,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:00,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:00,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:00,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 347 states and 545 transitions. [2018-11-18 12:23:00,763 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 545 transitions. [2018-11-18 12:23:00,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:00,764 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:00,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:00,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:01,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:01,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 348 states and 545 transitions. [2018-11-18 12:23:01,032 INFO L276 IsEmpty]: Start isEmpty. Operand 348 states and 545 transitions. [2018-11-18 12:23:01,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:01,032 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:01,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:01,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:01,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:01,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 349 states and 545 transitions. [2018-11-18 12:23:01,287 INFO L276 IsEmpty]: Start isEmpty. Operand 349 states and 545 transitions. [2018-11-18 12:23:01,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:01,288 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:01,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:01,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:01,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:01,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 350 states and 545 transitions. [2018-11-18 12:23:01,546 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 545 transitions. [2018-11-18 12:23:01,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:01,546 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:01,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:01,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:01,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:01,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 351 states and 545 transitions. [2018-11-18 12:23:01,898 INFO L276 IsEmpty]: Start isEmpty. Operand 351 states and 545 transitions. [2018-11-18 12:23:01,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:01,899 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:01,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:01,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:02,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:02,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 352 states and 545 transitions. [2018-11-18 12:23:02,162 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 545 transitions. [2018-11-18 12:23:02,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:02,163 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:02,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:02,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:02,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:02,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 353 states and 545 transitions. [2018-11-18 12:23:02,409 INFO L276 IsEmpty]: Start isEmpty. Operand 353 states and 545 transitions. [2018-11-18 12:23:02,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:02,409 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:02,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:02,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:02,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:02,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 354 states and 545 transitions. [2018-11-18 12:23:02,679 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 545 transitions. [2018-11-18 12:23:02,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:02,680 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:02,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:02,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:02,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:02,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 563 states to 355 states and 545 transitions. [2018-11-18 12:23:02,997 INFO L276 IsEmpty]: Start isEmpty. Operand 355 states and 545 transitions. [2018-11-18 12:23:02,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:02,998 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:03,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:03,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:03,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:03,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 384 states and 604 transitions. [2018-11-18 12:23:03,985 INFO L276 IsEmpty]: Start isEmpty. Operand 384 states and 604 transitions. [2018-11-18 12:23:03,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:03,985 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:03,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:04,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:04,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:04,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 385 states and 604 transitions. [2018-11-18 12:23:04,302 INFO L276 IsEmpty]: Start isEmpty. Operand 385 states and 604 transitions. [2018-11-18 12:23:04,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:04,303 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:04,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:04,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:04,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:04,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 386 states and 604 transitions. [2018-11-18 12:23:04,632 INFO L276 IsEmpty]: Start isEmpty. Operand 386 states and 604 transitions. [2018-11-18 12:23:04,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:04,633 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:04,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:04,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:04,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:04,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 387 states and 604 transitions. [2018-11-18 12:23:04,986 INFO L276 IsEmpty]: Start isEmpty. Operand 387 states and 604 transitions. [2018-11-18 12:23:04,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:04,986 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:04,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:05,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:05,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:05,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 388 states and 604 transitions. [2018-11-18 12:23:05,335 INFO L276 IsEmpty]: Start isEmpty. Operand 388 states and 604 transitions. [2018-11-18 12:23:05,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:05,336 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:05,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:05,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:05,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:05,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 389 states and 604 transitions. [2018-11-18 12:23:05,619 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 604 transitions. [2018-11-18 12:23:05,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:05,620 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:05,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:05,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:05,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:05,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 390 states and 604 transitions. [2018-11-18 12:23:05,923 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 604 transitions. [2018-11-18 12:23:05,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:05,923 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:05,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:05,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:06,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:06,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 391 states and 604 transitions. [2018-11-18 12:23:06,241 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 604 transitions. [2018-11-18 12:23:06,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:06,241 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:06,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:06,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:06,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:06,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 392 states and 604 transitions. [2018-11-18 12:23:06,605 INFO L276 IsEmpty]: Start isEmpty. Operand 392 states and 604 transitions. [2018-11-18 12:23:06,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:06,606 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:06,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:06,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:06,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:06,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 628 states to 393 states and 604 transitions. [2018-11-18 12:23:06,929 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 604 transitions. [2018-11-18 12:23:06,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:06,931 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:06,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:06,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:07,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:07,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 416 states and 651 transitions. [2018-11-18 12:23:07,353 INFO L276 IsEmpty]: Start isEmpty. Operand 416 states and 651 transitions. [2018-11-18 12:23:07,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:07,354 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:07,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:07,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:07,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:07,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 417 states and 651 transitions. [2018-11-18 12:23:07,700 INFO L276 IsEmpty]: Start isEmpty. Operand 417 states and 651 transitions. [2018-11-18 12:23:07,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:07,701 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:07,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:07,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:08,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:08,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 418 states and 651 transitions. [2018-11-18 12:23:08,013 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 651 transitions. [2018-11-18 12:23:08,014 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:08,014 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:08,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:08,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:08,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:08,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 419 states and 651 transitions. [2018-11-18 12:23:08,389 INFO L276 IsEmpty]: Start isEmpty. Operand 419 states and 651 transitions. [2018-11-18 12:23:08,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:08,390 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:08,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:08,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:08,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:08,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 420 states and 651 transitions. [2018-11-18 12:23:08,694 INFO L276 IsEmpty]: Start isEmpty. Operand 420 states and 651 transitions. [2018-11-18 12:23:08,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:08,695 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:08,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:08,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:09,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:09,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 421 states and 651 transitions. [2018-11-18 12:23:09,066 INFO L276 IsEmpty]: Start isEmpty. Operand 421 states and 651 transitions. [2018-11-18 12:23:09,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:09,066 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:09,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:09,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:09,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:09,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 422 states and 651 transitions. [2018-11-18 12:23:09,414 INFO L276 IsEmpty]: Start isEmpty. Operand 422 states and 651 transitions. [2018-11-18 12:23:09,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:09,415 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:09,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:09,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:09,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:09,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 681 states to 423 states and 651 transitions. [2018-11-18 12:23:09,733 INFO L276 IsEmpty]: Start isEmpty. Operand 423 states and 651 transitions. [2018-11-18 12:23:09,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:09,733 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:09,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:09,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:10,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:10,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 440 states and 686 transitions. [2018-11-18 12:23:10,146 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 686 transitions. [2018-11-18 12:23:10,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:10,147 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:10,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:10,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:10,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:10,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 441 states and 686 transitions. [2018-11-18 12:23:10,461 INFO L276 IsEmpty]: Start isEmpty. Operand 441 states and 686 transitions. [2018-11-18 12:23:10,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:10,461 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:10,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:10,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:10,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:10,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 442 states and 686 transitions. [2018-11-18 12:23:10,775 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 686 transitions. [2018-11-18 12:23:10,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:10,776 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:10,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:10,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:11,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:11,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 443 states and 686 transitions. [2018-11-18 12:23:11,099 INFO L276 IsEmpty]: Start isEmpty. Operand 443 states and 686 transitions. [2018-11-18 12:23:11,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:11,099 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:11,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:11,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:11,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:11,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 444 states and 686 transitions. [2018-11-18 12:23:11,451 INFO L276 IsEmpty]: Start isEmpty. Operand 444 states and 686 transitions. [2018-11-18 12:23:11,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:11,452 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:11,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:11,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:11,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:11,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 445 states and 686 transitions. [2018-11-18 12:23:11,767 INFO L276 IsEmpty]: Start isEmpty. Operand 445 states and 686 transitions. [2018-11-18 12:23:11,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:11,768 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:11,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:11,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:12,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:12,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 751 states to 456 states and 709 transitions. [2018-11-18 12:23:12,159 INFO L276 IsEmpty]: Start isEmpty. Operand 456 states and 709 transitions. [2018-11-18 12:23:12,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:12,160 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:12,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:12,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:12,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:12,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 751 states to 457 states and 709 transitions. [2018-11-18 12:23:12,447 INFO L276 IsEmpty]: Start isEmpty. Operand 457 states and 709 transitions. [2018-11-18 12:23:12,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:12,447 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:12,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:12,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:12,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:12,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 751 states to 458 states and 709 transitions. [2018-11-18 12:23:12,736 INFO L276 IsEmpty]: Start isEmpty. Operand 458 states and 709 transitions. [2018-11-18 12:23:12,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:12,737 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:12,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:12,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:13,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:13,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 751 states to 459 states and 709 transitions. [2018-11-18 12:23:13,034 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 709 transitions. [2018-11-18 12:23:13,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:13,035 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:13,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:13,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:13,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:13,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 774 states to 467 states and 726 transitions. [2018-11-18 12:23:13,482 INFO L276 IsEmpty]: Start isEmpty. Operand 467 states and 726 transitions. [2018-11-18 12:23:13,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:13,482 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:13,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:13,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:13,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:13,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 774 states to 468 states and 726 transitions. [2018-11-18 12:23:13,802 INFO L276 IsEmpty]: Start isEmpty. Operand 468 states and 726 transitions. [2018-11-18 12:23:13,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:13,803 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:13,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:13,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:14,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:14,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 774 states to 469 states and 726 transitions. [2018-11-18 12:23:14,075 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 726 transitions. [2018-11-18 12:23:14,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:14,075 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:14,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:14,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:14,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:14,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 785 states to 471 states and 731 transitions. [2018-11-18 12:23:14,421 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 731 transitions. [2018-11-18 12:23:14,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:14,422 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:14,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:14,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:16,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:16,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 908 states to 525 states and 837 transitions. [2018-11-18 12:23:16,853 INFO L276 IsEmpty]: Start isEmpty. Operand 525 states and 837 transitions. [2018-11-18 12:23:16,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:16,854 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:16,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:16,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:18,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:18,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 927 states to 530 states and 848 transitions. [2018-11-18 12:23:18,249 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 848 transitions. [2018-11-18 12:23:18,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:18,250 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:18,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:18,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:20,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:20,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 964 states to 544 states and 877 transitions. [2018-11-18 12:23:20,914 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 877 transitions. [2018-11-18 12:23:20,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:20,914 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:20,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:21,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:25,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:25,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1013 states to 564 states and 918 transitions. [2018-11-18 12:23:25,159 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 918 transitions. [2018-11-18 12:23:25,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:25,160 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:25,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:25,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:31,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:31,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1074 states to 590 states and 971 transitions. [2018-11-18 12:23:31,601 INFO L276 IsEmpty]: Start isEmpty. Operand 590 states and 971 transitions. [2018-11-18 12:23:31,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:31,602 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:31,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:31,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:39,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:39,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1147 states to 622 states and 1036 transitions. [2018-11-18 12:23:39,958 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 1036 transitions. [2018-11-18 12:23:39,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-11-18 12:23:39,959 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:39,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:40,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:52,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:52,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1238 states to 663 states and 1119 transitions. [2018-11-18 12:23:52,590 INFO L276 IsEmpty]: Start isEmpty. Operand 663 states and 1119 transitions. [2018-11-18 12:23:52,591 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:52,591 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:52,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:52,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:53,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:53,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1233 states to 661 states and 1114 transitions. [2018-11-18 12:23:53,360 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 1114 transitions. [2018-11-18 12:23:53,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:53,360 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:53,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:53,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:53,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:53,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1234 states to 662 states and 1115 transitions. [2018-11-18 12:23:53,638 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 1115 transitions. [2018-11-18 12:23:53,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:53,638 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:53,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:53,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:53,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:53,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1235 states to 663 states and 1116 transitions. [2018-11-18 12:23:53,979 INFO L276 IsEmpty]: Start isEmpty. Operand 663 states and 1116 transitions. [2018-11-18 12:23:53,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:53,979 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:53,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:54,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:54,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:54,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1236 states to 664 states and 1117 transitions. [2018-11-18 12:23:54,458 INFO L276 IsEmpty]: Start isEmpty. Operand 664 states and 1117 transitions. [2018-11-18 12:23:54,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:54,458 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:54,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:54,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:54,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:54,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1237 states to 665 states and 1118 transitions. [2018-11-18 12:23:54,924 INFO L276 IsEmpty]: Start isEmpty. Operand 665 states and 1118 transitions. [2018-11-18 12:23:54,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:54,925 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:54,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:54,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:55,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:55,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1238 states to 666 states and 1119 transitions. [2018-11-18 12:23:55,431 INFO L276 IsEmpty]: Start isEmpty. Operand 666 states and 1119 transitions. [2018-11-18 12:23:55,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:55,432 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:55,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:55,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:56,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:56,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1239 states to 667 states and 1120 transitions. [2018-11-18 12:23:56,021 INFO L276 IsEmpty]: Start isEmpty. Operand 667 states and 1120 transitions. [2018-11-18 12:23:56,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:56,022 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:56,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:56,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:56,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:56,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1240 states to 668 states and 1121 transitions. [2018-11-18 12:23:56,595 INFO L276 IsEmpty]: Start isEmpty. Operand 668 states and 1121 transitions. [2018-11-18 12:23:56,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:56,595 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:56,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 12:23:56,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 12:23:57,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-18 12:23:57,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1241 states to 669 states and 1122 transitions. [2018-11-18 12:23:57,009 INFO L276 IsEmpty]: Start isEmpty. Operand 669 states and 1122 transitions. [2018-11-18 12:23:57,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-18 12:23:57,010 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-18 12:23:57,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 12:23:57,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 12:23:57,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 12:23:57,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 12:23:57,515 WARN L493 CodeCheckObserver]: This program is UNSAFE, Check terminated with 89 iterations. [2018-11-18 12:23:57,670 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 18.11 12:23:57 ImpRootNode [2018-11-18 12:23:57,670 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2018-11-18 12:23:57,670 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 12:23:57,670 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 12:23:57,671 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 12:23:57,672 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 12:22:44" (3/4) ... [2018-11-18 12:23:57,674 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample [2018-11-18 12:23:57,820 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_9ba423db-0109-440f-8984-2f4b5736d956/bin-2019/ukojak/witness.graphml [2018-11-18 12:23:57,820 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 12:23:57,821 INFO L168 Benchmark]: Toolchain (without parser) took 77685.74 ms. Allocated memory was 1.0 GB in the beginning and 2.1 GB in the end (delta: 1.1 GB). Free memory was 958.0 MB in the beginning and 1.5 GB in the end (delta: -582.3 MB). Peak memory consumption was 506.1 MB. Max. memory is 11.5 GB. [2018-11-18 12:23:57,823 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 982.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 12:23:57,823 INFO L168 Benchmark]: CACSL2BoogieTranslator took 381.92 ms. Allocated memory is still 1.0 GB. Free memory was 958.0 MB in the beginning and 930.1 MB in the end (delta: 27.9 MB). Peak memory consumption was 27.9 MB. Max. memory is 11.5 GB. [2018-11-18 12:23:57,823 INFO L168 Benchmark]: Boogie Procedure Inliner took 113.37 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 172.0 MB). Free memory was 930.1 MB in the beginning and 1.2 GB in the end (delta: -232.1 MB). Peak memory consumption was 16.6 MB. Max. memory is 11.5 GB. [2018-11-18 12:23:57,823 INFO L168 Benchmark]: Boogie Preprocessor took 44.73 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2018-11-18 12:23:57,823 INFO L168 Benchmark]: RCFGBuilder took 3873.61 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 68.2 MB). Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: -38.6 MB). Peak memory consumption was 326.8 MB. Max. memory is 11.5 GB. [2018-11-18 12:23:57,824 INFO L168 Benchmark]: CodeCheck took 73118.75 ms. Allocated memory was 1.3 GB in the beginning and 2.1 GB in the end (delta: 848.3 MB). Free memory was 1.2 GB in the beginning and 1.6 GB in the end (delta: -371.0 MB). Peak memory consumption was 477.3 MB. Max. memory is 11.5 GB. [2018-11-18 12:23:57,824 INFO L168 Benchmark]: Witness Printer took 149.93 ms. Allocated memory is still 2.1 GB. Free memory was 1.6 GB in the beginning and 1.5 GB in the end (delta: 24.6 MB). Peak memory consumption was 24.6 MB. Max. memory is 11.5 GB. [2018-11-18 12:23:57,825 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 442 locations, 1 error locations. UNSAFE Result, 72.9s OverallTime, 89 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: -1892952064 SDtfs, -1825402888 SDslu, 1148395000 SDs, 0 SdLazy, 222113276 SolverSat, 146136064 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 16.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 57440 GetRequests, 46042 SyntacticMatches, 10994 SemanticMatches, 404 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 281765 ImplicationChecksByTransitivity, 68.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, traceCheckStatistics: 0.2s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 3.3s InterpolantComputationTime, 6418 NumberOfCodeBlocks, 6418 NumberOfCodeBlocksAsserted, 89 NumberOfCheckSat, 6257 ConstructedInterpolants, 0 QuantifiedInterpolants, 893711 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 88 InterpolantComputations, 88 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int t9_pc = 0; [L25] int t10_pc = 0; [L26] int t11_pc = 0; [L27] int t12_pc = 0; [L28] int t13_pc = 0; [L29] int t14_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int t6_st ; [L37] int t7_st ; [L38] int t8_st ; [L39] int t9_st ; [L40] int t10_st ; [L41] int t11_st ; [L42] int t12_st ; [L43] int t13_st ; [L44] int t14_st ; [L45] int m_i ; [L46] int t1_i ; [L47] int t2_i ; [L48] int t3_i ; [L49] int t4_i ; [L50] int t5_i ; [L51] int t6_i ; [L52] int t7_i ; [L53] int t8_i ; [L54] int t9_i ; [L55] int t10_i ; [L56] int t11_i ; [L57] int t12_i ; [L58] int t13_i ; [L59] int t14_i ; [L60] int M_E = 2; [L61] int T1_E = 2; [L62] int T2_E = 2; [L63] int T3_E = 2; [L64] int T4_E = 2; [L65] int T5_E = 2; [L66] int T6_E = 2; [L67] int T7_E = 2; [L68] int T8_E = 2; [L69] int T9_E = 2; [L70] int T10_E = 2; [L71] int T11_E = 2; [L72] int T12_E = 2; [L73] int T13_E = 2; [L74] int T14_E = 2; [L75] int E_1 = 2; [L76] int E_2 = 2; [L77] int E_3 = 2; [L78] int E_4 = 2; [L79] int E_5 = 2; [L80] int E_6 = 2; [L81] int E_7 = 2; [L82] int E_8 = 2; [L83] int E_9 = 2; [L84] int E_10 = 2; [L85] int E_11 = 2; [L86] int E_12 = 2; [L87] int E_13 = 2; [L88] int E_14 = 2; [L2052] int __retres1 ; [L2056] CALL init_model() [L1954] m_i = 1 [L1955] t1_i = 1 [L1956] t2_i = 1 [L1957] t3_i = 1 [L1958] t4_i = 1 [L1959] t5_i = 1 [L1960] t6_i = 1 [L1961] t7_i = 1 [L1962] t8_i = 1 [L1963] t9_i = 1 [L1964] t10_i = 1 [L1965] t11_i = 1 [L1966] t12_i = 1 [L1967] t13_i = 1 [L1968] RET t14_i = 1 [L2056] init_model() [L2057] CALL start_simulation() [L1993] int kernel_st ; [L1994] int tmp ; [L1995] int tmp___0 ; [L1999] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2000] FCALL update_channels() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2001] CALL init_threads() [L929] COND TRUE m_i == 1 [L930] m_st = 0 [L934] COND TRUE t1_i == 1 [L935] t1_st = 0 [L939] COND TRUE t2_i == 1 [L940] t2_st = 0 [L944] COND TRUE t3_i == 1 [L945] t3_st = 0 [L949] COND TRUE t4_i == 1 [L950] t4_st = 0 [L954] COND TRUE t5_i == 1 [L955] t5_st = 0 [L959] COND TRUE t6_i == 1 [L960] t6_st = 0 [L964] COND TRUE t7_i == 1 [L965] t7_st = 0 [L969] COND TRUE t8_i == 1 [L970] t8_st = 0 [L974] COND TRUE t9_i == 1 [L975] t9_st = 0 [L979] COND TRUE t10_i == 1 [L980] t10_st = 0 [L984] COND TRUE t11_i == 1 [L985] t11_st = 0 [L989] COND TRUE t12_i == 1 [L990] t12_st = 0 [L994] COND TRUE t13_i == 1 [L995] t13_st = 0 [L999] COND TRUE t14_i == 1 [L1000] RET t14_st = 0 [L2001] init_threads() [L2002] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1332] COND FALSE !(M_E == 0) [L1337] COND FALSE !(T1_E == 0) [L1342] COND FALSE !(T2_E == 0) [L1347] COND FALSE !(T3_E == 0) [L1352] COND FALSE !(T4_E == 0) [L1357] COND FALSE !(T5_E == 0) [L1362] COND FALSE !(T6_E == 0) [L1367] COND FALSE !(T7_E == 0) [L1372] COND FALSE !(T8_E == 0) [L1377] COND FALSE !(T9_E == 0) [L1382] COND FALSE !(T10_E == 0) [L1387] COND FALSE !(T11_E == 0) [L1392] COND FALSE !(T12_E == 0) [L1397] COND FALSE !(T13_E == 0) [L1402] COND FALSE !(T14_E == 0) [L1407] COND FALSE !(E_1 == 0) [L1412] COND FALSE !(E_2 == 0) [L1417] COND FALSE !(E_3 == 0) [L1422] COND FALSE !(E_4 == 0) [L1427] COND FALSE !(E_5 == 0) [L1432] COND FALSE !(E_6 == 0) [L1437] COND FALSE !(E_7 == 0) [L1442] COND FALSE !(E_8 == 0) [L1447] COND FALSE !(E_9 == 0) [L1452] COND FALSE !(E_10 == 0) [L1457] COND FALSE !(E_11 == 0) [L1462] COND FALSE !(E_12 == 0) [L1467] COND FALSE !(E_13 == 0) [L1472] COND FALSE, RET !(E_14 == 0) [L2002] fire_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2003] CALL activate_threads() VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1635] int tmp ; [L1636] int tmp___0 ; [L1637] int tmp___1 ; [L1638] int tmp___2 ; [L1639] int tmp___3 ; [L1640] int tmp___4 ; [L1641] int tmp___5 ; [L1642] int tmp___6 ; [L1643] int tmp___7 ; [L1644] int tmp___8 ; [L1645] int tmp___9 ; [L1646] int tmp___10 ; [L1647] int tmp___11 ; [L1648] int tmp___12 ; [L1649] int tmp___13 ; [L1654] CALL, EXPR is_master_triggered() [L633] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L636] COND FALSE !(m_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L646] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L648] RET return (__retres1); [L1654] EXPR is_master_triggered() [L1654] tmp = is_master_triggered() [L1656] COND FALSE !(\read(tmp)) [L1662] CALL, EXPR is_transmit1_triggered() [L652] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L655] COND FALSE !(t1_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L665] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L667] RET return (__retres1); [L1662] EXPR is_transmit1_triggered() [L1662] tmp___0 = is_transmit1_triggered() [L1664] COND FALSE !(\read(tmp___0)) [L1670] CALL, EXPR is_transmit2_triggered() [L671] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L674] COND FALSE !(t2_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L684] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L686] RET return (__retres1); [L1670] EXPR is_transmit2_triggered() [L1670] tmp___1 = is_transmit2_triggered() [L1672] COND FALSE !(\read(tmp___1)) [L1678] CALL, EXPR is_transmit3_triggered() [L690] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L693] COND FALSE !(t3_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L703] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L705] RET return (__retres1); [L1678] EXPR is_transmit3_triggered() [L1678] tmp___2 = is_transmit3_triggered() [L1680] COND FALSE !(\read(tmp___2)) [L1686] CALL, EXPR is_transmit4_triggered() [L709] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L712] COND FALSE !(t4_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L722] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L724] RET return (__retres1); [L1686] EXPR is_transmit4_triggered() [L1686] tmp___3 = is_transmit4_triggered() [L1688] COND FALSE !(\read(tmp___3)) [L1694] CALL, EXPR is_transmit5_triggered() [L728] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L731] COND FALSE !(t5_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L741] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L743] RET return (__retres1); [L1694] EXPR is_transmit5_triggered() [L1694] tmp___4 = is_transmit5_triggered() [L1696] COND FALSE !(\read(tmp___4)) [L1702] CALL, EXPR is_transmit6_triggered() [L747] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L750] COND FALSE !(t6_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L760] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L762] RET return (__retres1); [L1702] EXPR is_transmit6_triggered() [L1702] tmp___5 = is_transmit6_triggered() [L1704] COND FALSE !(\read(tmp___5)) [L1710] CALL, EXPR is_transmit7_triggered() [L766] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L769] COND FALSE !(t7_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L779] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L781] RET return (__retres1); [L1710] EXPR is_transmit7_triggered() [L1710] tmp___6 = is_transmit7_triggered() [L1712] COND FALSE !(\read(tmp___6)) [L1718] CALL, EXPR is_transmit8_triggered() [L785] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L788] COND FALSE !(t8_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L798] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L800] RET return (__retres1); [L1718] EXPR is_transmit8_triggered() [L1718] tmp___7 = is_transmit8_triggered() [L1720] COND FALSE !(\read(tmp___7)) [L1726] CALL, EXPR is_transmit9_triggered() [L804] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L807] COND FALSE !(t9_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L817] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L819] RET return (__retres1); [L1726] EXPR is_transmit9_triggered() [L1726] tmp___8 = is_transmit9_triggered() [L1728] COND FALSE !(\read(tmp___8)) [L1734] CALL, EXPR is_transmit10_triggered() [L823] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L826] COND FALSE !(t10_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L836] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L838] RET return (__retres1); [L1734] EXPR is_transmit10_triggered() [L1734] tmp___9 = is_transmit10_triggered() [L1736] COND FALSE !(\read(tmp___9)) [L1742] CALL, EXPR is_transmit11_triggered() [L842] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L845] COND FALSE !(t11_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L855] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L857] RET return (__retres1); [L1742] EXPR is_transmit11_triggered() [L1742] tmp___10 = is_transmit11_triggered() [L1744] COND FALSE !(\read(tmp___10)) [L1750] CALL, EXPR is_transmit12_triggered() [L861] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L864] COND FALSE !(t12_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L874] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L876] RET return (__retres1); [L1750] EXPR is_transmit12_triggered() [L1750] tmp___11 = is_transmit12_triggered() [L1752] COND FALSE !(\read(tmp___11)) [L1758] CALL, EXPR is_transmit13_triggered() [L880] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L883] COND FALSE !(t13_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L893] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L895] RET return (__retres1); [L1758] EXPR is_transmit13_triggered() [L1758] tmp___12 = is_transmit13_triggered() [L1760] COND FALSE !(\read(tmp___12)) [L1766] CALL, EXPR is_transmit14_triggered() [L899] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L902] COND FALSE !(t14_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L912] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L914] RET return (__retres1); [L1766] EXPR is_transmit14_triggered() [L1766] tmp___13 = is_transmit14_triggered() [L1768] COND FALSE, RET !(\read(tmp___13)) [L2003] activate_threads() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2004] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1485] COND FALSE !(M_E == 1) [L1490] COND FALSE !(T1_E == 1) [L1495] COND FALSE !(T2_E == 1) [L1500] COND FALSE !(T3_E == 1) [L1505] COND FALSE !(T4_E == 1) [L1510] COND FALSE !(T5_E == 1) [L1515] COND FALSE !(T6_E == 1) [L1520] COND FALSE !(T7_E == 1) [L1525] COND FALSE !(T8_E == 1) [L1530] COND FALSE !(T9_E == 1) [L1535] COND FALSE !(T10_E == 1) [L1540] COND FALSE !(T11_E == 1) [L1545] COND FALSE !(T12_E == 1) [L1550] COND FALSE !(T13_E == 1) [L1555] COND FALSE !(T14_E == 1) [L1560] COND FALSE !(E_1 == 1) [L1565] COND FALSE !(E_2 == 1) [L1570] COND FALSE !(E_3 == 1) [L1575] COND FALSE !(E_4 == 1) [L1580] COND FALSE !(E_5 == 1) [L1585] COND FALSE !(E_6 == 1) [L1590] COND FALSE !(E_7 == 1) [L1595] COND FALSE !(E_8 == 1) [L1600] COND FALSE !(E_9 == 1) [L1605] COND FALSE !(E_10 == 1) [L1610] COND FALSE !(E_11 == 1) [L1615] COND FALSE !(E_12 == 1) [L1620] COND FALSE !(E_13 == 1) [L1625] COND FALSE, RET !(E_14 == 1) [L2004] reset_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2007] COND TRUE 1 [L2010] kernel_st = 1 [L2011] CALL eval() [L1096] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1100] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1103] CALL, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1009] int __retres1 ; [L1012] COND TRUE m_st == 0 [L1013] __retres1 = 1 [L1091] RET return (__retres1); [L1103] EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1103] tmp = exists_runnable_thread() [L1105] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1110] COND TRUE m_st == 0 [L1111] int tmp_ndt_1; [L1112] tmp_ndt_1 = __VERIFIER_nondet_int() [L1113] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1124] COND TRUE t1_st == 0 [L1125] int tmp_ndt_2; [L1126] tmp_ndt_2 = __VERIFIER_nondet_int() [L1127] COND FALSE !(\read(tmp_ndt_2)) [L1133] CALL error() [L11] __VERIFIER_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 982.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 381.92 ms. Allocated memory is still 1.0 GB. Free memory was 958.0 MB in the beginning and 930.1 MB in the end (delta: 27.9 MB). Peak memory consumption was 27.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 113.37 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 172.0 MB). Free memory was 930.1 MB in the beginning and 1.2 GB in the end (delta: -232.1 MB). Peak memory consumption was 16.6 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 44.73 ms. Allocated memory is still 1.2 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 3873.61 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 68.2 MB). Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: -38.6 MB). Peak memory consumption was 326.8 MB. Max. memory is 11.5 GB. * CodeCheck took 73118.75 ms. Allocated memory was 1.3 GB in the beginning and 2.1 GB in the end (delta: 848.3 MB). Free memory was 1.2 GB in the beginning and 1.6 GB in the end (delta: -371.0 MB). Peak memory consumption was 477.3 MB. Max. memory is 11.5 GB. * Witness Printer took 149.93 ms. Allocated memory is still 2.1 GB. Free memory was 1.6 GB in the beginning and 1.5 GB in the end (delta: 24.6 MB). Peak memory consumption was 24.6 MB. Max. memory is 11.5 GB. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...