./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/pc_sfifo_2_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/pc_sfifo_2_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash df684da5e5a56662a7be6091ec5bb0a21e1453c5 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 05:00:25,752 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 05:00:25,753 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 05:00:25,759 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 05:00:25,759 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 05:00:25,760 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 05:00:25,760 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 05:00:25,761 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 05:00:25,762 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 05:00:25,762 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 05:00:25,763 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 05:00:25,763 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 05:00:25,764 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 05:00:25,764 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 05:00:25,766 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 05:00:25,766 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 05:00:25,767 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 05:00:25,768 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 05:00:25,769 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 05:00:25,770 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 05:00:25,771 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 05:00:25,771 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 05:00:25,773 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 05:00:25,773 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 05:00:25,773 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 05:00:25,774 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 05:00:25,774 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 05:00:25,775 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 05:00:25,775 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 05:00:25,776 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 05:00:25,776 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 05:00:25,777 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 05:00:25,777 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 05:00:25,777 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 05:00:25,778 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 05:00:25,778 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 05:00:25,778 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/config/svcomp-Reach-32bit-Kojak_Default.epf [2018-11-23 05:00:25,785 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 05:00:25,786 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 05:00:25,786 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 05:00:25,786 INFO L133 SettingsManager]: * ... to procedures called more than once=ALWAYS [2018-11-23 05:00:25,787 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 05:00:25,787 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 05:00:25,787 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 05:00:25,787 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 05:00:25,787 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 05:00:25,788 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 05:00:25,788 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 05:00:25,788 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 05:00:25,788 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 05:00:25,788 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 05:00:25,788 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 05:00:25,788 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 05:00:25,789 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 05:00:25,789 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 05:00:25,789 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-11-23 05:00:25,789 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-11-23 05:00:25,789 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 05:00:25,789 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 05:00:25,789 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-23 05:00:25,789 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 05:00:25,790 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 05:00:25,790 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 05:00:25,790 INFO L133 SettingsManager]: * Trace refinement strategy=PENGUIN [2018-11-23 05:00:25,790 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 05:00:25,790 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 05:00:25,790 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> df684da5e5a56662a7be6091ec5bb0a21e1453c5 [2018-11-23 05:00:25,809 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 05:00:25,819 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 05:00:25,822 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 05:00:25,823 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 05:00:25,823 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 05:00:25,824 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/../../sv-benchmarks/c/systemc/pc_sfifo_2_false-unreach-call_false-termination.cil.c [2018-11-23 05:00:25,863 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/data/c655aa3f1/7ed476221b044e9eb1901349a7f56d4a/FLAG87b527f5a [2018-11-23 05:00:26,299 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 05:00:26,300 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/sv-benchmarks/c/systemc/pc_sfifo_2_false-unreach-call_false-termination.cil.c [2018-11-23 05:00:26,307 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/data/c655aa3f1/7ed476221b044e9eb1901349a7f56d4a/FLAG87b527f5a [2018-11-23 05:00:26,319 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/data/c655aa3f1/7ed476221b044e9eb1901349a7f56d4a [2018-11-23 05:00:26,321 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 05:00:26,322 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 05:00:26,322 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 05:00:26,322 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 05:00:26,325 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 05:00:26,325 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,327 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@15a4b09f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26, skipping insertion in model container [2018-11-23 05:00:26,327 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,333 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 05:00:26,354 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 05:00:26,488 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:00:26,491 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 05:00:26,519 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:00:26,531 INFO L195 MainTranslator]: Completed translation [2018-11-23 05:00:26,531 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26 WrapperNode [2018-11-23 05:00:26,531 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 05:00:26,531 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 05:00:26,532 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 05:00:26,532 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 05:00:26,537 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,541 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,595 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 05:00:26,595 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 05:00:26,596 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 05:00:26,596 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 05:00:26,603 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,603 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,604 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,604 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,608 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,612 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,613 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... [2018-11-23 05:00:26,614 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 05:00:26,615 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 05:00:26,615 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 05:00:26,615 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 05:00:26,615 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:00:26" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-11-23 05:00:26,647 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2018-11-23 05:00:26,647 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2018-11-23 05:00:26,647 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2018-11-23 05:00:26,647 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2018-11-23 05:00:26,647 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2018-11-23 05:00:26,648 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2018-11-23 05:00:26,648 INFO L130 BoogieDeclarations]: Found specification of procedure error [2018-11-23 05:00:26,648 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2018-11-23 05:00:26,648 INFO L130 BoogieDeclarations]: Found specification of procedure is_do_read_c_triggered [2018-11-23 05:00:26,648 INFO L138 BoogieDeclarations]: Found implementation of procedure is_do_read_c_triggered [2018-11-23 05:00:26,648 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2018-11-23 05:00:26,648 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2018-11-23 05:00:26,648 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2018-11-23 05:00:26,648 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2018-11-23 05:00:26,649 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 05:00:26,649 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 05:00:26,649 INFO L130 BoogieDeclarations]: Found specification of procedure is_do_write_p_triggered [2018-11-23 05:00:26,649 INFO L138 BoogieDeclarations]: Found implementation of procedure is_do_write_p_triggered [2018-11-23 05:00:27,093 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 05:00:27,093 INFO L280 CfgBuilder]: Removed 24 assue(true) statements. [2018-11-23 05:00:27,094 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:00:27 BoogieIcfgContainer [2018-11-23 05:00:27,094 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 05:00:27,094 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-11-23 05:00:27,094 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-11-23 05:00:27,101 INFO L276 PluginConnector]: CodeCheck initialized [2018-11-23 05:00:27,101 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:00:27" (1/1) ... [2018-11-23 05:00:27,108 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:00:27,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-23 05:00:27,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 71 states and 99 transitions. [2018-11-23 05:00:27,134 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 99 transitions. [2018-11-23 05:00:27,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-11-23 05:00:27,139 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-23 05:00:27,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:00:27,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:00:27,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-23 05:00:27,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 76 states and 100 transitions. [2018-11-23 05:00:27,484 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 100 transitions. [2018-11-23 05:00:27,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-11-23 05:00:27,485 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-23 05:00:27,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:00:27,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:00:27,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-11-23 05:00:27,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 80 states and 106 transitions. [2018-11-23 05:00:27,783 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 106 transitions. [2018-11-23 05:00:27,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-11-23 05:00:27,785 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2018-11-23 05:00:27,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:00:27,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:00:27,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:00:27,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:00:27,931 WARN L493 CodeCheckObserver]: This program is UNSAFE, Check terminated with 3 iterations. ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call update_channels(); VAL [|old(~q_ev~0)|=0, |old(~q_read_ev~0)|=2, |old(~q_req_up~0)|=0, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] BeginParallelComposition{ParallelCodeBlock0: assume !(1 == ~q_req_up~0);ParallelCodeBlock1: assume 1 == ~q_req_up~0;BeginParallelComposition{ParallelCodeBlock0: assume 0 == ~q_free~0;~q_write_ev~0 := 0;ParallelCodeBlock1: assume !(0 == ~q_free~0);}EndParallelCompositionBeginParallelComposition{ParallelCodeBlock0: assume 1 == ~q_free~0;~q_read_ev~0 := 0;ParallelCodeBlock1: assume !(1 == ~q_free~0);}EndParallelComposition~q_ev~0 := 0;~q_req_up~0 := 0;}EndParallelCompositionassume true; VAL [|old(~q_ev~0)|=0, |old(~q_read_ev~0)|=2, |old(~q_req_up~0)|=0, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #309#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] BeginParallelComposition{ParallelCodeBlock0: assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;ParallelCodeBlock1: assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2;}EndParallelCompositionBeginParallelComposition{ParallelCodeBlock0: assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;ParallelCodeBlock1: assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;}EndParallelComposition VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call fire_delta_events(); VAL [|old(~q_read_ev~0)|=2, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] BeginParallelComposition{ParallelCodeBlock0: assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;ParallelCodeBlock1: assume !(0 == ~q_read_ev~0);}EndParallelCompositionBeginParallelComposition{ParallelCodeBlock0: assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;ParallelCodeBlock1: assume !(0 == ~q_write_ev~0);}EndParallelCompositionassume true; VAL [|old(~q_read_ev~0)|=2, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #311#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call activate_threads(); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~1; VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] havoc ~__retres1~0; VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !(1 == ~p_dw_pc~0); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] ~__retres1~0 := 0; VAL [is_do_write_p_triggered_~__retres1~0=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] #res := ~__retres1~0;assume true; VAL [is_do_write_p_triggered_~__retres1~0=0, |is_do_write_p_triggered_#res|=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #305#return; VAL [|activate_threads_#t~ret3|=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647;~tmp~1 := #t~ret3;havoc #t~ret3;BeginParallelComposition{ParallelCodeBlock0: assume 0 != ~tmp~1;~p_dw_st~0 := 0;ParallelCodeBlock1: assume !(0 != ~tmp~1);}EndParallelComposition VAL [activate_threads_~tmp~1=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] havoc ~__retres1~1; VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !(1 == ~c_dr_pc~0); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] ~__retres1~1 := 0; VAL [is_do_read_c_triggered_~__retres1~1=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] #res := ~__retres1~1;assume true; VAL [is_do_read_c_triggered_~__retres1~1=0, |is_do_read_c_triggered_#res|=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #307#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret4|=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647;~tmp___0~1 := #t~ret4;havoc #t~ret4;BeginParallelComposition{ParallelCodeBlock0: assume 0 != ~tmp___0~1;~c_dr_st~0 := 0;ParallelCodeBlock1: assume !(0 != ~tmp___0~1);}EndParallelCompositionassume true; VAL [activate_threads_~tmp___0~1=0, activate_threads_~tmp~1=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #313#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call reset_delta_events(); VAL [|old(~q_read_ev~0)|=2, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] BeginParallelComposition{ParallelCodeBlock0: assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;ParallelCodeBlock1: assume !(1 == ~q_read_ev~0);}EndParallelCompositionBeginParallelComposition{ParallelCodeBlock0: assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;ParallelCodeBlock1: assume !(1 == ~q_write_ev~0);}EndParallelCompositionassume true; VAL [|old(~q_read_ev~0)|=2, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #315#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !false;start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !false; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] havoc ~__retres1~2;BeginParallelComposition{ParallelCodeBlock0: assume 0 == ~p_dw_st~0;~__retres1~2 := 1;ParallelCodeBlock1: assume !(0 == ~p_dw_st~0);BeginParallelComposition{ParallelCodeBlock0: assume 0 == ~c_dr_st~0;~__retres1~2 := 1;ParallelCodeBlock1: assume !(0 == ~c_dr_st~0);~__retres1~2 := 0;}EndParallelComposition}EndParallelComposition#res := ~__retres1~2;assume true; VAL [exists_runnable_thread_~__retres1~2=1, |exists_runnable_thread_#res|=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #317#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=1, |ULTIMATE.start_eval_#t~ret5|=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; VAL [ULTIMATE.start_eval_~tmp___1~0=1, ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume 0 != eval_~tmp___1~0; VAL [ULTIMATE.start_eval_~tmp___1~0=1, ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume 0 == ~p_dw_st~0;assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647;eval_~tmp~2 := eval_#t~nondet6;havoc eval_#t~nondet6; VAL [ULTIMATE.start_eval_~tmp___1~0=1, ULTIMATE.start_eval_~tmp~2=0, ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !(0 != eval_~tmp~2); VAL [ULTIMATE.start_eval_~tmp___1~0=1, ULTIMATE.start_eval_~tmp~2=0, ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~3; [L456] havoc main_~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L461] havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4; [L396] havoc start_simulation_~kernel_st~0; [L397] havoc start_simulation_~tmp~4; [L401] start_simulation_~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212-L218] assume !(1 == ~q_req_up~0); [L208-L222] ensures true; VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] RET call update_channels(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227-L231] assume 1 == ~p_dw_i~0; [L228] ~p_dw_st~0 := 0; [L232-L236] assume 1 == ~c_dr_i~0; [L233] ~c_dr_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265-L269] assume !(0 == ~q_read_ev~0); [L270-L274] assume !(0 == ~q_write_ev~0); [L261-L278] ensures true; VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] RET call fire_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55-L64] assume !(1 == ~p_dw_pc~0); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L51-L69] ensures true; VAL [#res=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] assume !(0 != ~tmp~1); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74-L83] assume !(1 == ~c_dr_pc~0); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L70-L88] ensures true; VAL [#res=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] assume !(0 != ~tmp___0~1); [L297-L321] ensures true; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp___0~1=0, ~tmp~1=0] [L405] RET call activate_threads(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283-L287] assume !(1 == ~q_read_ev~0); [L288-L292] assume !(1 == ~q_write_ev~0); [L279-L296] ensures true; VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] RET call reset_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] assume !false; [L412] start_simulation_~kernel_st~0 := 1; [L413] havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0; [L323] havoc eval_~tmp~2; [L324] havoc eval_~tmp___0~2; [L325] havoc eval_~tmp___1~0; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] assume !false; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245-L255] assume 0 == ~p_dw_st~0; [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L241-L260] ensures true; VAL [#res=1, ~__retres1~2=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] RET call eval_#t~ret5 := exists_runnable_thread(); VAL [eval_#t~ret5=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647; [L332] eval_~tmp___1~0 := eval_#t~ret5; [L332] havoc eval_#t~ret5; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] assume 0 != eval_~tmp___1~0; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339-L353] assume 0 == ~p_dw_st~0; [L341] assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647; [L341] eval_~tmp~2 := eval_#t~nondet6; [L341] havoc eval_#t~nondet6; VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] assume !(0 != eval_~tmp~2); VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~3; [L456] havoc main_~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L461] havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4; [L396] havoc start_simulation_~kernel_st~0; [L397] havoc start_simulation_~tmp~4; [L401] start_simulation_~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212-L218] assume !(1 == ~q_req_up~0); [L208-L222] ensures true; VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] RET call update_channels(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227-L231] assume 1 == ~p_dw_i~0; [L228] ~p_dw_st~0 := 0; [L232-L236] assume 1 == ~c_dr_i~0; [L233] ~c_dr_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265-L269] assume !(0 == ~q_read_ev~0); [L270-L274] assume !(0 == ~q_write_ev~0); [L261-L278] ensures true; VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] RET call fire_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55-L64] assume !(1 == ~p_dw_pc~0); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L51-L69] ensures true; VAL [#res=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] assume !(0 != ~tmp~1); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74-L83] assume !(1 == ~c_dr_pc~0); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L70-L88] ensures true; VAL [#res=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] assume !(0 != ~tmp___0~1); [L297-L321] ensures true; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp___0~1=0, ~tmp~1=0] [L405] RET call activate_threads(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283-L287] assume !(1 == ~q_read_ev~0); [L288-L292] assume !(1 == ~q_write_ev~0); [L279-L296] ensures true; VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] RET call reset_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] assume !false; [L412] start_simulation_~kernel_st~0 := 1; [L413] havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0; [L323] havoc eval_~tmp~2; [L324] havoc eval_~tmp___0~2; [L325] havoc eval_~tmp___1~0; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] assume !false; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245-L255] assume 0 == ~p_dw_st~0; [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L241-L260] ensures true; VAL [#res=1, ~__retres1~2=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] RET call eval_#t~ret5 := exists_runnable_thread(); VAL [eval_#t~ret5=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647; [L332] eval_~tmp___1~0 := eval_#t~ret5; [L332] havoc eval_#t~ret5; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] assume 0 != eval_~tmp___1~0; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339-L353] assume 0 == ~p_dw_st~0; [L341] assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647; [L341] eval_~tmp~2 := eval_#t~nondet6; [L341] havoc eval_#t~nondet6; VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] assume !(0 != eval_~tmp~2); VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~3; [L456] havoc main_~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L461] havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4; [L396] havoc start_simulation_~kernel_st~0; [L397] havoc start_simulation_~tmp~4; [L401] start_simulation_~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212] COND FALSE !(1 == ~q_req_up~0) [L402] RET call update_channels(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227] COND TRUE 1 == ~p_dw_i~0 [L228] ~p_dw_st~0 := 0; [L232] COND TRUE 1 == ~c_dr_i~0 [L233] ~c_dr_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265] COND FALSE !(0 == ~q_read_ev~0) [L270] COND FALSE !(0 == ~q_write_ev~0) [L404] RET call fire_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55] COND FALSE !(1 == ~p_dw_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] COND FALSE !(0 != ~tmp~1) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74] COND FALSE !(1 == ~c_dr_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] COND FALSE !(0 != ~tmp___0~1) [L405] RET call activate_threads(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283] COND FALSE !(1 == ~q_read_ev~0) [L288] COND FALSE !(1 == ~q_write_ev~0) [L406] RET call reset_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] COND FALSE !(false) [L412] start_simulation_~kernel_st~0 := 1; [L413] havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0; [L323] havoc eval_~tmp~2; [L324] havoc eval_~tmp___0~2; [L325] havoc eval_~tmp___1~0; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] COND FALSE !(false) VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245] COND TRUE 0 == ~p_dw_st~0 [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L332] RET call eval_#t~ret5 := exists_runnable_thread(); VAL [eval_#t~ret5=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647; [L332] eval_~tmp___1~0 := eval_#t~ret5; [L332] havoc eval_#t~ret5; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] COND TRUE 0 != eval_~tmp___1~0 VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339] COND TRUE 0 == ~p_dw_st~0 [L341] assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647; [L341] eval_~tmp~2 := eval_#t~nondet6; [L341] havoc eval_#t~nondet6; VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] COND FALSE !(0 != eval_~tmp~2) VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~3; [L456] havoc main_~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L461] havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4; [L396] havoc start_simulation_~kernel_st~0; [L397] havoc start_simulation_~tmp~4; [L401] start_simulation_~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212] COND FALSE !(1 == ~q_req_up~0) [L402] RET call update_channels(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227] COND TRUE 1 == ~p_dw_i~0 [L228] ~p_dw_st~0 := 0; [L232] COND TRUE 1 == ~c_dr_i~0 [L233] ~c_dr_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265] COND FALSE !(0 == ~q_read_ev~0) [L270] COND FALSE !(0 == ~q_write_ev~0) [L404] RET call fire_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55] COND FALSE !(1 == ~p_dw_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] COND FALSE !(0 != ~tmp~1) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74] COND FALSE !(1 == ~c_dr_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] COND FALSE !(0 != ~tmp___0~1) [L405] RET call activate_threads(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283] COND FALSE !(1 == ~q_read_ev~0) [L288] COND FALSE !(1 == ~q_write_ev~0) [L406] RET call reset_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] COND FALSE !(false) [L412] start_simulation_~kernel_st~0 := 1; [L413] havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0; [L323] havoc eval_~tmp~2; [L324] havoc eval_~tmp___0~2; [L325] havoc eval_~tmp___1~0; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] COND FALSE !(false) VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245] COND TRUE 0 == ~p_dw_st~0 [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L332] RET call eval_#t~ret5 := exists_runnable_thread(); VAL [eval_#t~ret5=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647; [L332] eval_~tmp___1~0 := eval_#t~ret5; [L332] havoc eval_#t~ret5; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] COND TRUE 0 != eval_~tmp___1~0 VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339] COND TRUE 0 == ~p_dw_st~0 [L341] assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647; [L341] eval_~tmp~2 := eval_#t~nondet6; [L341] havoc eval_#t~nondet6; VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] COND FALSE !(0 != eval_~tmp~2) VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [L456] havoc ~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L396] havoc ~kernel_st~0; [L397] havoc ~tmp~4; [L401] ~kernel_st~0 := 0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212] COND FALSE !(1 == ~q_req_up~0) [L402] RET call update_channels(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227] COND TRUE 1 == ~p_dw_i~0 [L228] ~p_dw_st~0 := 0; [L232] COND TRUE 1 == ~c_dr_i~0 [L233] ~c_dr_st~0 := 0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265] COND FALSE !(0 == ~q_read_ev~0) [L270] COND FALSE !(0 == ~q_write_ev~0) [L404] RET call fire_delta_events(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55] COND FALSE !(1 == ~p_dw_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] COND FALSE !(0 != ~tmp~1) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74] COND FALSE !(1 == ~c_dr_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] COND FALSE !(0 != ~tmp___0~1) [L405] RET call activate_threads(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283] COND FALSE !(1 == ~q_read_ev~0) [L288] COND FALSE !(1 == ~q_write_ev~0) [L406] RET call reset_delta_events(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] COND FALSE !(false) [L412] ~kernel_st~0 := 1; [L323] havoc ~tmp~2; [L324] havoc ~tmp___0~2; [L325] havoc ~tmp___1~0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] COND FALSE !(false) VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call #t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245] COND TRUE 0 == ~p_dw_st~0 [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L332] RET call #t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= #t~ret5 && #t~ret5 <= 2147483647; [L332] ~tmp___1~0 := #t~ret5; [L332] havoc #t~ret5; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] COND TRUE 0 != ~tmp___1~0 VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339] COND TRUE 0 == ~p_dw_st~0 [L341] assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647; [L341] ~tmp~2 := #t~nondet6; [L341] havoc #t~nondet6; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] COND FALSE !(0 != ~tmp~2) VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [L456] havoc ~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L396] havoc ~kernel_st~0; [L397] havoc ~tmp~4; [L401] ~kernel_st~0 := 0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212] COND FALSE !(1 == ~q_req_up~0) [L402] RET call update_channels(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227] COND TRUE 1 == ~p_dw_i~0 [L228] ~p_dw_st~0 := 0; [L232] COND TRUE 1 == ~c_dr_i~0 [L233] ~c_dr_st~0 := 0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265] COND FALSE !(0 == ~q_read_ev~0) [L270] COND FALSE !(0 == ~q_write_ev~0) [L404] RET call fire_delta_events(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55] COND FALSE !(1 == ~p_dw_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] COND FALSE !(0 != ~tmp~1) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74] COND FALSE !(1 == ~c_dr_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] COND FALSE !(0 != ~tmp___0~1) [L405] RET call activate_threads(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283] COND FALSE !(1 == ~q_read_ev~0) [L288] COND FALSE !(1 == ~q_write_ev~0) [L406] RET call reset_delta_events(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] COND FALSE !(false) [L412] ~kernel_st~0 := 1; [L323] havoc ~tmp~2; [L324] havoc ~tmp___0~2; [L325] havoc ~tmp___1~0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] COND FALSE !(false) VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call #t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245] COND TRUE 0 == ~p_dw_st~0 [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L332] RET call #t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= #t~ret5 && #t~ret5 <= 2147483647; [L332] ~tmp___1~0 := #t~ret5; [L332] havoc #t~ret5; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] COND TRUE 0 != ~tmp___1~0 VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339] COND TRUE 0 == ~p_dw_st~0 [L341] assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647; [L341] ~tmp~2 := #t~nondet6; [L341] havoc #t~nondet6; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] COND FALSE !(0 != ~tmp~2) VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L15] int q_buf_0 ; [L16] int q_free ; [L17] int q_read_ev ; [L18] int q_write_ev ; [L19] int q_req_up ; [L20] int q_ev ; [L41] int p_num_write ; [L42] int p_last_write ; [L43] int p_dw_st ; [L44] int p_dw_pc ; [L45] int p_dw_i ; [L46] int c_num_read ; [L47] int c_last_read ; [L48] int c_dr_st ; [L49] int c_dr_pc ; [L50] int c_dr_i ; [L154] static int a_t ; [L456] int __retres1 ; [L442] q_free = 1 [L443] q_write_ev = 2 [L444] q_read_ev = q_write_ev [L445] p_num_write = 0 [L446] p_dw_pc = 0 [L447] p_dw_i = 1 [L448] c_num_read = 0 [L449] c_dr_pc = 0 [L450] c_dr_i = 1 [L396] int kernel_st ; [L397] int tmp ; [L401] kernel_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L402] CALL update_channels() VAL [\old(q_ev)=0, \old(q_read_ev)=2, \old(q_req_up)=0, \old(q_write_ev)=2, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L212] COND FALSE !((int )q_req_up == 1) [L402] RET update_channels() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L227] COND TRUE (int )p_dw_i == 1 [L228] p_dw_st = 0 [L232] COND TRUE (int )c_dr_i == 1 [L233] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L404] CALL fire_delta_events() VAL [\old(q_read_ev)=2, \old(q_write_ev)=2, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L265] COND FALSE !((int )q_read_ev == 0) [L270] COND FALSE !((int )q_write_ev == 0) [L404] RET fire_delta_events() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L405] CALL activate_threads() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] int tmp ; [L299] int tmp___0 ; VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L303] CALL, EXPR is_do_write_p_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L52] int __retres1 ; VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L55] COND FALSE !((int )p_dw_pc == 1) VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] __retres1 = 0 VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L67] return (__retres1); [L303] RET, EXPR is_do_write_p_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, is_do_write_p_triggered()=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L303] tmp = is_do_write_p_triggered() [L305] COND FALSE !(\read(tmp)) VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L311] CALL, EXPR is_do_read_c_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L71] int __retres1 ; VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L74] COND FALSE !((int )c_dr_pc == 1) VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] __retres1 = 0 VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L86] return (__retres1); [L311] RET, EXPR is_do_read_c_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, is_do_read_c_triggered()=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L311] tmp___0 = is_do_read_c_triggered() [L313] COND FALSE !(\read(tmp___0)) [L405] RET activate_threads() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L406] CALL reset_delta_events() VAL [\old(q_read_ev)=2, \old(q_write_ev)=2, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L283] COND FALSE !((int )q_read_ev == 1) [L288] COND FALSE !((int )q_write_ev == 1) [L406] RET reset_delta_events() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L409] COND TRUE 1 [L412] kernel_st = 1 [L323] int tmp ; [L324] int tmp___0 ; [L325] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L329] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L332] CALL, EXPR exists_runnable_thread() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] int __retres1 ; [L245] COND TRUE (int )p_dw_st == 0 [L246] __retres1 = 1 [L258] return (__retres1); [L332] RET, EXPR exists_runnable_thread() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L332] tmp___1 = exists_runnable_thread() [L334] COND TRUE \read(tmp___1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L339] COND TRUE (int )p_dw_st == 0 [L341] tmp = __VERIFIER_nondet_int() [L343] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L349] CALL error() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L10] __VERIFIER_error() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] ----- [2018-11-23 05:00:28,076 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 23.11 05:00:28 ImpRootNode [2018-11-23 05:00:28,076 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2018-11-23 05:00:28,077 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 05:00:28,077 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 05:00:28,077 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 05:00:28,078 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:00:27" (3/4) ... [2018-11-23 05:00:28,080 INFO L138 WitnessPrinter]: Generating witness for reachability counterexample ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] ~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~4;start_simulation_~kernel_st~0 := 0; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call update_channels(); VAL [|old(~q_ev~0)|=0, |old(~q_read_ev~0)|=2, |old(~q_req_up~0)|=0, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] BeginParallelComposition{ParallelCodeBlock0: assume !(1 == ~q_req_up~0);ParallelCodeBlock1: assume 1 == ~q_req_up~0;BeginParallelComposition{ParallelCodeBlock0: assume 0 == ~q_free~0;~q_write_ev~0 := 0;ParallelCodeBlock1: assume !(0 == ~q_free~0);}EndParallelCompositionBeginParallelComposition{ParallelCodeBlock0: assume 1 == ~q_free~0;~q_read_ev~0 := 0;ParallelCodeBlock1: assume !(1 == ~q_free~0);}EndParallelComposition~q_ev~0 := 0;~q_req_up~0 := 0;}EndParallelCompositionassume true; VAL [|old(~q_ev~0)|=0, |old(~q_read_ev~0)|=2, |old(~q_req_up~0)|=0, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #309#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] BeginParallelComposition{ParallelCodeBlock0: assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;ParallelCodeBlock1: assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2;}EndParallelCompositionBeginParallelComposition{ParallelCodeBlock0: assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;ParallelCodeBlock1: assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;}EndParallelComposition VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call fire_delta_events(); VAL [|old(~q_read_ev~0)|=2, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] BeginParallelComposition{ParallelCodeBlock0: assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;ParallelCodeBlock1: assume !(0 == ~q_read_ev~0);}EndParallelCompositionBeginParallelComposition{ParallelCodeBlock0: assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;ParallelCodeBlock1: assume !(0 == ~q_write_ev~0);}EndParallelCompositionassume true; VAL [|old(~q_read_ev~0)|=2, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #311#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call activate_threads(); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] havoc ~tmp~1;havoc ~tmp___0~1; VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] havoc ~__retres1~0; VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !(1 == ~p_dw_pc~0); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] ~__retres1~0 := 0; VAL [is_do_write_p_triggered_~__retres1~0=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] #res := ~__retres1~0;assume true; VAL [is_do_write_p_triggered_~__retres1~0=0, |is_do_write_p_triggered_#res|=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #305#return; VAL [|activate_threads_#t~ret3|=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647;~tmp~1 := #t~ret3;havoc #t~ret3;BeginParallelComposition{ParallelCodeBlock0: assume 0 != ~tmp~1;~p_dw_st~0 := 0;ParallelCodeBlock1: assume !(0 != ~tmp~1);}EndParallelComposition VAL [activate_threads_~tmp~1=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] havoc ~__retres1~1; VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !(1 == ~c_dr_pc~0); VAL [|old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] ~__retres1~1 := 0; VAL [is_do_read_c_triggered_~__retres1~1=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] #res := ~__retres1~1;assume true; VAL [is_do_read_c_triggered_~__retres1~1=0, |is_do_read_c_triggered_#res|=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #307#return; VAL [activate_threads_~tmp~1=0, |activate_threads_#t~ret4|=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647;~tmp___0~1 := #t~ret4;havoc #t~ret4;BeginParallelComposition{ParallelCodeBlock0: assume 0 != ~tmp___0~1;~c_dr_st~0 := 0;ParallelCodeBlock1: assume !(0 != ~tmp___0~1);}EndParallelCompositionassume true; VAL [activate_threads_~tmp___0~1=0, activate_threads_~tmp~1=0, |old(~c_dr_st~0)|=0, |old(~p_dw_st~0)|=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #313#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call reset_delta_events(); VAL [|old(~q_read_ev~0)|=2, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] BeginParallelComposition{ParallelCodeBlock0: assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;ParallelCodeBlock1: assume !(1 == ~q_read_ev~0);}EndParallelCompositionBeginParallelComposition{ParallelCodeBlock0: assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;ParallelCodeBlock1: assume !(1 == ~q_write_ev~0);}EndParallelCompositionassume true; VAL [|old(~q_read_ev~0)|=2, |old(~q_write_ev~0)|=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #315#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !false;start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0;havoc eval_~tmp~2;havoc eval_~tmp___0~2;havoc eval_~tmp___1~0; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !false; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] havoc ~__retres1~2;BeginParallelComposition{ParallelCodeBlock0: assume 0 == ~p_dw_st~0;~__retres1~2 := 1;ParallelCodeBlock1: assume !(0 == ~p_dw_st~0);BeginParallelComposition{ParallelCodeBlock0: assume 0 == ~c_dr_st~0;~__retres1~2 := 1;ParallelCodeBlock1: assume !(0 == ~c_dr_st~0);~__retres1~2 := 0;}EndParallelComposition}EndParallelComposition#res := ~__retres1~2;assume true; VAL [exists_runnable_thread_~__retres1~2=1, |exists_runnable_thread_#res|=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] RET #317#return; VAL [ULTIMATE.start_start_simulation_~kernel_st~0=1, |ULTIMATE.start_eval_#t~ret5|=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647;eval_~tmp___1~0 := eval_#t~ret5;havoc eval_#t~ret5; VAL [ULTIMATE.start_eval_~tmp___1~0=1, ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume 0 != eval_~tmp___1~0; VAL [ULTIMATE.start_eval_~tmp___1~0=1, ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume 0 == ~p_dw_st~0;assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647;eval_~tmp~2 := eval_#t~nondet6;havoc eval_#t~nondet6; VAL [ULTIMATE.start_eval_~tmp___1~0=1, ULTIMATE.start_eval_~tmp~2=0, ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !(0 != eval_~tmp~2); VAL [ULTIMATE.start_eval_~tmp___1~0=1, ULTIMATE.start_eval_~tmp~2=0, ULTIMATE.start_start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [?] assume !false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~3; [L456] havoc main_~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L461] havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4; [L396] havoc start_simulation_~kernel_st~0; [L397] havoc start_simulation_~tmp~4; [L401] start_simulation_~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212-L218] assume !(1 == ~q_req_up~0); [L208-L222] ensures true; VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] RET call update_channels(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227-L231] assume 1 == ~p_dw_i~0; [L228] ~p_dw_st~0 := 0; [L232-L236] assume 1 == ~c_dr_i~0; [L233] ~c_dr_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265-L269] assume !(0 == ~q_read_ev~0); [L270-L274] assume !(0 == ~q_write_ev~0); [L261-L278] ensures true; VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] RET call fire_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55-L64] assume !(1 == ~p_dw_pc~0); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L51-L69] ensures true; VAL [#res=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] assume !(0 != ~tmp~1); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74-L83] assume !(1 == ~c_dr_pc~0); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L70-L88] ensures true; VAL [#res=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] assume !(0 != ~tmp___0~1); [L297-L321] ensures true; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp___0~1=0, ~tmp~1=0] [L405] RET call activate_threads(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283-L287] assume !(1 == ~q_read_ev~0); [L288-L292] assume !(1 == ~q_write_ev~0); [L279-L296] ensures true; VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] RET call reset_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] assume !false; [L412] start_simulation_~kernel_st~0 := 1; [L413] havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0; [L323] havoc eval_~tmp~2; [L324] havoc eval_~tmp___0~2; [L325] havoc eval_~tmp___1~0; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] assume !false; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245-L255] assume 0 == ~p_dw_st~0; [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L241-L260] ensures true; VAL [#res=1, ~__retres1~2=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] RET call eval_#t~ret5 := exists_runnable_thread(); VAL [eval_#t~ret5=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647; [L332] eval_~tmp___1~0 := eval_#t~ret5; [L332] havoc eval_#t~ret5; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] assume 0 != eval_~tmp___1~0; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339-L353] assume 0 == ~p_dw_st~0; [L341] assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647; [L341] eval_~tmp~2 := eval_#t~nondet6; [L341] havoc eval_#t~nondet6; VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] assume !(0 != eval_~tmp~2); VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~3; [L456] havoc main_~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L461] havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4; [L396] havoc start_simulation_~kernel_st~0; [L397] havoc start_simulation_~tmp~4; [L401] start_simulation_~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212-L218] assume !(1 == ~q_req_up~0); [L208-L222] ensures true; VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] RET call update_channels(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227-L231] assume 1 == ~p_dw_i~0; [L228] ~p_dw_st~0 := 0; [L232-L236] assume 1 == ~c_dr_i~0; [L233] ~c_dr_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265-L269] assume !(0 == ~q_read_ev~0); [L270-L274] assume !(0 == ~q_write_ev~0); [L261-L278] ensures true; VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] RET call fire_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55-L64] assume !(1 == ~p_dw_pc~0); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L51-L69] ensures true; VAL [#res=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] assume !(0 != ~tmp~1); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74-L83] assume !(1 == ~c_dr_pc~0); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L70-L88] ensures true; VAL [#res=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] assume !(0 != ~tmp___0~1); [L297-L321] ensures true; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp___0~1=0, ~tmp~1=0] [L405] RET call activate_threads(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283-L287] assume !(1 == ~q_read_ev~0); [L288-L292] assume !(1 == ~q_write_ev~0); [L279-L296] ensures true; VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] RET call reset_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] assume !false; [L412] start_simulation_~kernel_st~0 := 1; [L413] havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0; [L323] havoc eval_~tmp~2; [L324] havoc eval_~tmp___0~2; [L325] havoc eval_~tmp___1~0; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] assume !false; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245-L255] assume 0 == ~p_dw_st~0; [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L241-L260] ensures true; VAL [#res=1, ~__retres1~2=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] RET call eval_#t~ret5 := exists_runnable_thread(); VAL [eval_#t~ret5=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647; [L332] eval_~tmp___1~0 := eval_#t~ret5; [L332] havoc eval_#t~ret5; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] assume 0 != eval_~tmp___1~0; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339-L353] assume 0 == ~p_dw_st~0; [L341] assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647; [L341] eval_~tmp~2 := eval_#t~nondet6; [L341] havoc eval_#t~nondet6; VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] assume !(0 != eval_~tmp~2); VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~3; [L456] havoc main_~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L461] havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4; [L396] havoc start_simulation_~kernel_st~0; [L397] havoc start_simulation_~tmp~4; [L401] start_simulation_~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212] COND FALSE !(1 == ~q_req_up~0) [L402] RET call update_channels(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227] COND TRUE 1 == ~p_dw_i~0 [L228] ~p_dw_st~0 := 0; [L232] COND TRUE 1 == ~c_dr_i~0 [L233] ~c_dr_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265] COND FALSE !(0 == ~q_read_ev~0) [L270] COND FALSE !(0 == ~q_write_ev~0) [L404] RET call fire_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55] COND FALSE !(1 == ~p_dw_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] COND FALSE !(0 != ~tmp~1) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74] COND FALSE !(1 == ~c_dr_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] COND FALSE !(0 != ~tmp___0~1) [L405] RET call activate_threads(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283] COND FALSE !(1 == ~q_read_ev~0) [L288] COND FALSE !(1 == ~q_write_ev~0) [L406] RET call reset_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] COND FALSE !(false) [L412] start_simulation_~kernel_st~0 := 1; [L413] havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0; [L323] havoc eval_~tmp~2; [L324] havoc eval_~tmp___0~2; [L325] havoc eval_~tmp___1~0; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] COND FALSE !(false) VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245] COND TRUE 0 == ~p_dw_st~0 [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L332] RET call eval_#t~ret5 := exists_runnable_thread(); VAL [eval_#t~ret5=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647; [L332] eval_~tmp___1~0 := eval_#t~ret5; [L332] havoc eval_#t~ret5; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] COND TRUE 0 != eval_~tmp___1~0 VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339] COND TRUE 0 == ~p_dw_st~0 [L341] assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647; [L341] eval_~tmp~2 := eval_#t~nondet6; [L341] havoc eval_#t~nondet6; VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] COND FALSE !(0 != eval_~tmp~2) VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [?] havoc main_#res; [?] havoc main_~__retres1~3; [L456] havoc main_~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L461] havoc start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~4; [L396] havoc start_simulation_~kernel_st~0; [L397] havoc start_simulation_~tmp~4; [L401] start_simulation_~kernel_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212] COND FALSE !(1 == ~q_req_up~0) [L402] RET call update_channels(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227] COND TRUE 1 == ~p_dw_i~0 [L228] ~p_dw_st~0 := 0; [L232] COND TRUE 1 == ~c_dr_i~0 [L233] ~c_dr_st~0 := 0; VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265] COND FALSE !(0 == ~q_read_ev~0) [L270] COND FALSE !(0 == ~q_write_ev~0) [L404] RET call fire_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55] COND FALSE !(1 == ~p_dw_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] COND FALSE !(0 != ~tmp~1) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74] COND FALSE !(1 == ~c_dr_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] COND FALSE !(0 != ~tmp___0~1) [L405] RET call activate_threads(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283] COND FALSE !(1 == ~q_read_ev~0) [L288] COND FALSE !(1 == ~q_write_ev~0) [L406] RET call reset_delta_events(); VAL [start_simulation_~kernel_st~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] COND FALSE !(false) [L412] start_simulation_~kernel_st~0 := 1; [L413] havoc eval_#t~ret5, eval_#t~nondet6, eval_#t~nondet7, eval_~tmp~2, eval_~tmp___0~2, eval_~tmp___1~0; [L323] havoc eval_~tmp~2; [L324] havoc eval_~tmp___0~2; [L325] havoc eval_~tmp___1~0; VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] COND FALSE !(false) VAL [start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call eval_#t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245] COND TRUE 0 == ~p_dw_st~0 [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L332] RET call eval_#t~ret5 := exists_runnable_thread(); VAL [eval_#t~ret5=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= eval_#t~ret5 && eval_#t~ret5 <= 2147483647; [L332] eval_~tmp___1~0 := eval_#t~ret5; [L332] havoc eval_#t~ret5; VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] COND TRUE 0 != eval_~tmp___1~0 VAL [eval_~tmp___1~0=1, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339] COND TRUE 0 == ~p_dw_st~0 [L341] assume -2147483648 <= eval_#t~nondet6 && eval_#t~nondet6 <= 2147483647; [L341] eval_~tmp~2 := eval_#t~nondet6; [L341] havoc eval_#t~nondet6; VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] COND FALSE !(0 != eval_~tmp~2) VAL [eval_~tmp___1~0=1, eval_~tmp~2=0, start_simulation_~kernel_st~0=1, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [L456] havoc ~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L396] havoc ~kernel_st~0; [L397] havoc ~tmp~4; [L401] ~kernel_st~0 := 0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212] COND FALSE !(1 == ~q_req_up~0) [L402] RET call update_channels(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227] COND TRUE 1 == ~p_dw_i~0 [L228] ~p_dw_st~0 := 0; [L232] COND TRUE 1 == ~c_dr_i~0 [L233] ~c_dr_st~0 := 0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265] COND FALSE !(0 == ~q_read_ev~0) [L270] COND FALSE !(0 == ~q_write_ev~0) [L404] RET call fire_delta_events(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55] COND FALSE !(1 == ~p_dw_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] COND FALSE !(0 != ~tmp~1) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74] COND FALSE !(1 == ~c_dr_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] COND FALSE !(0 != ~tmp___0~1) [L405] RET call activate_threads(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283] COND FALSE !(1 == ~q_read_ev~0) [L288] COND FALSE !(1 == ~q_write_ev~0) [L406] RET call reset_delta_events(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] COND FALSE !(false) [L412] ~kernel_st~0 := 1; [L323] havoc ~tmp~2; [L324] havoc ~tmp___0~2; [L325] havoc ~tmp___1~0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] COND FALSE !(false) VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call #t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245] COND TRUE 0 == ~p_dw_st~0 [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L332] RET call #t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= #t~ret5 && #t~ret5 <= 2147483647; [L332] ~tmp___1~0 := #t~ret5; [L332] havoc #t~ret5; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] COND TRUE 0 != ~tmp___1~0 VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339] COND TRUE 0 == ~p_dw_st~0 [L341] assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647; [L341] ~tmp~2 := #t~nondet6; [L341] havoc #t~nondet6; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] COND FALSE !(0 != ~tmp~2) VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [L15] ~q_buf_0~0 := 0; [L16] ~q_free~0 := 0; [L17] ~q_read_ev~0 := 0; [L18] ~q_write_ev~0 := 0; [L19] ~q_req_up~0 := 0; [L20] ~q_ev~0 := 0; [L41] ~p_num_write~0 := 0; [L42] ~p_last_write~0 := 0; [L43] ~p_dw_st~0 := 0; [L44] ~p_dw_pc~0 := 0; [L45] ~p_dw_i~0 := 0; [L46] ~c_num_read~0 := 0; [L47] ~c_last_read~0 := 0; [L48] ~c_dr_st~0 := 0; [L49] ~c_dr_pc~0 := 0; [L50] ~c_dr_i~0 := 0; [L154] ~a_t~0 := 0; [L456] havoc ~__retres1~3; [L442] ~q_free~0 := 1; [L443] ~q_write_ev~0 := 2; [L444] ~q_read_ev~0 := ~q_write_ev~0; [L445] ~p_num_write~0 := 0; [L446] ~p_dw_pc~0 := 0; [L447] ~p_dw_i~0 := 1; [L448] ~c_num_read~0 := 0; [L449] ~c_dr_pc~0 := 0; [L450] ~c_dr_i~0 := 1; [L396] havoc ~kernel_st~0; [L397] havoc ~tmp~4; [L401] ~kernel_st~0 := 0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L402] CALL call update_channels(); VAL [old(~q_ev~0)=0, old(~q_read_ev~0)=2, old(~q_req_up~0)=0, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L212] COND FALSE !(1 == ~q_req_up~0) [L402] RET call update_channels(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L227] COND TRUE 1 == ~p_dw_i~0 [L228] ~p_dw_st~0 := 0; [L232] COND TRUE 1 == ~c_dr_i~0 [L233] ~c_dr_st~0 := 0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L404] CALL call fire_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L265] COND FALSE !(0 == ~q_read_ev~0) [L270] COND FALSE !(0 == ~q_write_ev~0) [L404] RET call fire_delta_events(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L405] CALL call activate_threads(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L298] havoc ~tmp~1; [L299] havoc ~tmp___0~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] CALL call #t~ret3 := is_do_write_p_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L52] havoc ~__retres1~0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L55] COND FALSE !(1 == ~p_dw_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L65] ~__retres1~0 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~0=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L67] #res := ~__retres1~0; [L303] RET call #t~ret3 := is_do_write_p_triggered(); VAL [#t~ret3=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L303] assume -2147483648 <= #t~ret3 && #t~ret3 <= 2147483647; [L303] ~tmp~1 := #t~ret3; [L303] havoc #t~ret3; [L305-L309] COND FALSE !(0 != ~tmp~1) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] CALL call #t~ret4 := is_do_read_c_triggered(); VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L71] havoc ~__retres1~1; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L74] COND FALSE !(1 == ~c_dr_pc~0) VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L84] ~__retres1~1 := 0; VAL [old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~__retres1~1=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L86] #res := ~__retres1~1; [L311] RET call #t~ret4 := is_do_read_c_triggered(); VAL [#t~ret4=0, old(~c_dr_st~0)=0, old(~p_dw_st~0)=0, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2, ~tmp~1=0] [L311] assume -2147483648 <= #t~ret4 && #t~ret4 <= 2147483647; [L311] ~tmp___0~1 := #t~ret4; [L311] havoc #t~ret4; [L313-L317] COND FALSE !(0 != ~tmp___0~1) [L405] RET call activate_threads(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L406] CALL call reset_delta_events(); VAL [old(~q_read_ev~0)=2, old(~q_write_ev~0)=2, ~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L283] COND FALSE !(1 == ~q_read_ev~0) [L288] COND FALSE !(1 == ~q_write_ev~0) [L406] RET call reset_delta_events(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L409-L431] COND FALSE !(false) [L412] ~kernel_st~0 := 1; [L323] havoc ~tmp~2; [L324] havoc ~tmp___0~2; [L325] havoc ~tmp___1~0; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L329-L369] COND FALSE !(false) VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] CALL call #t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L242] havoc ~__retres1~2; [L245] COND TRUE 0 == ~p_dw_st~0 [L246] ~__retres1~2 := 1; [L258] #res := ~__retres1~2; [L332] RET call #t~ret5 := exists_runnable_thread(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L332] assume -2147483648 <= #t~ret5 && #t~ret5 <= 2147483647; [L332] ~tmp___1~0 := #t~ret5; [L332] havoc #t~ret5; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L334-L338] COND TRUE 0 != ~tmp___1~0 VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L339] COND TRUE 0 == ~p_dw_st~0 [L341] assume -2147483648 <= #t~nondet6 && #t~nondet6 <= 2147483647; [L341] ~tmp~2 := #t~nondet6; [L341] havoc #t~nondet6; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L343-L350] COND FALSE !(0 != ~tmp~2) VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L349] CALL call error(); VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L10] assert false; VAL [~a_t~0=0, ~c_dr_i~0=1, ~c_dr_pc~0=0, ~c_dr_st~0=0, ~c_last_read~0=0, ~c_num_read~0=0, ~p_dw_i~0=1, ~p_dw_pc~0=0, ~p_dw_st~0=0, ~p_last_write~0=0, ~p_num_write~0=0, ~q_buf_0~0=0, ~q_ev~0=0, ~q_free~0=1, ~q_read_ev~0=2, ~q_req_up~0=0, ~q_write_ev~0=2] [L15] int q_buf_0 ; [L16] int q_free ; [L17] int q_read_ev ; [L18] int q_write_ev ; [L19] int q_req_up ; [L20] int q_ev ; [L41] int p_num_write ; [L42] int p_last_write ; [L43] int p_dw_st ; [L44] int p_dw_pc ; [L45] int p_dw_i ; [L46] int c_num_read ; [L47] int c_last_read ; [L48] int c_dr_st ; [L49] int c_dr_pc ; [L50] int c_dr_i ; [L154] static int a_t ; [L456] int __retres1 ; [L442] q_free = 1 [L443] q_write_ev = 2 [L444] q_read_ev = q_write_ev [L445] p_num_write = 0 [L446] p_dw_pc = 0 [L447] p_dw_i = 1 [L448] c_num_read = 0 [L449] c_dr_pc = 0 [L450] c_dr_i = 1 [L396] int kernel_st ; [L397] int tmp ; [L401] kernel_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L402] CALL update_channels() VAL [\old(q_ev)=0, \old(q_read_ev)=2, \old(q_req_up)=0, \old(q_write_ev)=2, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L212] COND FALSE !((int )q_req_up == 1) [L402] RET update_channels() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L227] COND TRUE (int )p_dw_i == 1 [L228] p_dw_st = 0 [L232] COND TRUE (int )c_dr_i == 1 [L233] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L404] CALL fire_delta_events() VAL [\old(q_read_ev)=2, \old(q_write_ev)=2, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L265] COND FALSE !((int )q_read_ev == 0) [L270] COND FALSE !((int )q_write_ev == 0) [L404] RET fire_delta_events() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L405] CALL activate_threads() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] int tmp ; [L299] int tmp___0 ; VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L303] CALL, EXPR is_do_write_p_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L52] int __retres1 ; VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L55] COND FALSE !((int )p_dw_pc == 1) VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] __retres1 = 0 VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L67] return (__retres1); [L303] RET, EXPR is_do_write_p_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, is_do_write_p_triggered()=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L303] tmp = is_do_write_p_triggered() [L305] COND FALSE !(\read(tmp)) VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L311] CALL, EXPR is_do_read_c_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L71] int __retres1 ; VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L74] COND FALSE !((int )c_dr_pc == 1) VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] __retres1 = 0 VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L86] return (__retres1); [L311] RET, EXPR is_do_read_c_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, is_do_read_c_triggered()=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L311] tmp___0 = is_do_read_c_triggered() [L313] COND FALSE !(\read(tmp___0)) [L405] RET activate_threads() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L406] CALL reset_delta_events() VAL [\old(q_read_ev)=2, \old(q_write_ev)=2, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L283] COND FALSE !((int )q_read_ev == 1) [L288] COND FALSE !((int )q_write_ev == 1) [L406] RET reset_delta_events() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L409] COND TRUE 1 [L412] kernel_st = 1 [L323] int tmp ; [L324] int tmp___0 ; [L325] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L329] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L332] CALL, EXPR exists_runnable_thread() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] int __retres1 ; [L245] COND TRUE (int )p_dw_st == 0 [L246] __retres1 = 1 [L258] return (__retres1); [L332] RET, EXPR exists_runnable_thread() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L332] tmp___1 = exists_runnable_thread() [L334] COND TRUE \read(tmp___1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L339] COND TRUE (int )p_dw_st == 0 [L341] tmp = __VERIFIER_nondet_int() [L343] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L349] CALL error() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L10] __VERIFIER_error() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] ----- [2018-11-23 05:00:28,378 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_33750367-5c7f-4fbe-8a30-c036dbd9aea2/bin-2019/ukojak/witness.graphml [2018-11-23 05:00:28,378 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 05:00:28,379 INFO L168 Benchmark]: Toolchain (without parser) took 2057.65 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 135.3 MB). Free memory was 959.2 MB in the beginning and 931.0 MB in the end (delta: 28.3 MB). Peak memory consumption was 163.5 MB. Max. memory is 11.5 GB. [2018-11-23 05:00:28,380 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:00:28,380 INFO L168 Benchmark]: CACSL2BoogieTranslator took 209.11 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 943.1 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. [2018-11-23 05:00:28,381 INFO L168 Benchmark]: Boogie Procedure Inliner took 63.85 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 135.3 MB). Free memory was 943.1 MB in the beginning and 1.1 GB in the end (delta: -192.3 MB). Peak memory consumption was 14.5 MB. Max. memory is 11.5 GB. [2018-11-23 05:00:28,381 INFO L168 Benchmark]: Boogie Preprocessor took 19.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 05:00:28,381 INFO L168 Benchmark]: RCFGBuilder took 479.29 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 49.3 MB). Peak memory consumption was 49.3 MB. Max. memory is 11.5 GB. [2018-11-23 05:00:28,381 INFO L168 Benchmark]: CodeCheck took 982.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 947.1 MB in the end (delta: 136.3 MB). Peak memory consumption was 136.3 MB. Max. memory is 11.5 GB. [2018-11-23 05:00:28,382 INFO L168 Benchmark]: Witness Printer took 301.55 ms. Allocated memory is still 1.2 GB. Free memory was 947.1 MB in the beginning and 931.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-23 05:00:28,383 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 9 procedures, 99 locations, 1 error locations. UNSAFE Result, 0.8s OverallTime, 3 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 196 SDtfs, 40 SDslu, 52 SDs, 0 SdLazy, 56 SolverSat, 28 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 626 GetRequests, 497 SyntacticMatches, 121 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 293 ImplicationChecksByTransitivity, 0.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, traceCheckStatistics: 0.0s SsaConstructionTime, 0.0s SatisfiabilityAnalysisTime, 0.1s InterpolantComputationTime, 117 NumberOfCodeBlocks, 117 NumberOfCodeBlocksAsserted, 3 NumberOfCheckSat, 76 ConstructedInterpolants, 0 QuantifiedInterpolants, 4408 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 2 InterpolantComputations, 2 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 10]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int q_buf_0 ; [L16] int q_free ; [L17] int q_read_ev ; [L18] int q_write_ev ; [L19] int q_req_up ; [L20] int q_ev ; [L41] int p_num_write ; [L42] int p_last_write ; [L43] int p_dw_st ; [L44] int p_dw_pc ; [L45] int p_dw_i ; [L46] int c_num_read ; [L47] int c_last_read ; [L48] int c_dr_st ; [L49] int c_dr_pc ; [L50] int c_dr_i ; [L154] static int a_t ; [L456] int __retres1 ; [L442] q_free = 1 [L443] q_write_ev = 2 [L444] q_read_ev = q_write_ev [L445] p_num_write = 0 [L446] p_dw_pc = 0 [L447] p_dw_i = 1 [L448] c_num_read = 0 [L449] c_dr_pc = 0 [L450] c_dr_i = 1 [L396] int kernel_st ; [L397] int tmp ; [L401] kernel_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L402] CALL update_channels() VAL [\old(q_ev)=0, \old(q_read_ev)=2, \old(q_req_up)=0, \old(q_write_ev)=2, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L212] COND FALSE !((int )q_req_up == 1) [L402] RET update_channels() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L227] COND TRUE (int )p_dw_i == 1 [L228] p_dw_st = 0 [L232] COND TRUE (int )c_dr_i == 1 [L233] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L404] CALL fire_delta_events() VAL [\old(q_read_ev)=2, \old(q_write_ev)=2, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L265] COND FALSE !((int )q_read_ev == 0) [L270] COND FALSE !((int )q_write_ev == 0) [L404] RET fire_delta_events() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L405] CALL activate_threads() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] int tmp ; [L299] int tmp___0 ; VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L303] CALL, EXPR is_do_write_p_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L52] int __retres1 ; VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L55] COND FALSE !((int )p_dw_pc == 1) VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] __retres1 = 0 VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L67] return (__retres1); [L303] RET, EXPR is_do_write_p_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, is_do_write_p_triggered()=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L303] tmp = is_do_write_p_triggered() [L305] COND FALSE !(\read(tmp)) VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L311] CALL, EXPR is_do_read_c_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L71] int __retres1 ; VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L74] COND FALSE !((int )c_dr_pc == 1) VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] __retres1 = 0 VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, __retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L86] return (__retres1); [L311] RET, EXPR is_do_read_c_triggered() VAL [\old(c_dr_st)=0, \old(p_dw_st)=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, is_do_read_c_triggered()=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, tmp=0] [L311] tmp___0 = is_do_read_c_triggered() [L313] COND FALSE !(\read(tmp___0)) [L405] RET activate_threads() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L406] CALL reset_delta_events() VAL [\old(q_read_ev)=2, \old(q_write_ev)=2, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L283] COND FALSE !((int )q_read_ev == 1) [L288] COND FALSE !((int )q_write_ev == 1) [L406] RET reset_delta_events() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L409] COND TRUE 1 [L412] kernel_st = 1 [L323] int tmp ; [L324] int tmp___0 ; [L325] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L329] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L332] CALL, EXPR exists_runnable_thread() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] int __retres1 ; [L245] COND TRUE (int )p_dw_st == 0 [L246] __retres1 = 1 [L258] return (__retres1); [L332] RET, EXPR exists_runnable_thread() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L332] tmp___1 = exists_runnable_thread() [L334] COND TRUE \read(tmp___1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L339] COND TRUE (int )p_dw_st == 0 [L341] tmp = __VERIFIER_nondet_int() [L343] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L349] CALL error() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L10] __VERIFIER_error() VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 209.11 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 943.1 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 63.85 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 135.3 MB). Free memory was 943.1 MB in the beginning and 1.1 GB in the end (delta: -192.3 MB). Peak memory consumption was 14.5 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 19.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 479.29 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 49.3 MB). Peak memory consumption was 49.3 MB. Max. memory is 11.5 GB. * CodeCheck took 982.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 947.1 MB in the end (delta: 136.3 MB). Peak memory consumption was 136.3 MB. Max. memory is 11.5 GB. * Witness Printer took 301.55 ms. Allocated memory is still 1.2 GB. Free memory was 947.1 MB in the beginning and 931.0 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...