./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 35987657 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.2.2-?-3598765 [2022-07-22 02:41:46,585 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-22 02:41:46,587 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-22 02:41:46,625 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-22 02:41:46,627 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-22 02:41:46,628 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-22 02:41:46,629 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-22 02:41:46,630 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-22 02:41:46,638 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-22 02:41:46,641 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-22 02:41:46,642 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-22 02:41:46,644 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-22 02:41:46,646 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-22 02:41:46,649 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-22 02:41:46,650 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-22 02:41:46,654 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-22 02:41:46,656 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-22 02:41:46,657 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-22 02:41:46,663 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-22 02:41:46,665 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-22 02:41:46,666 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-22 02:41:46,671 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-22 02:41:46,672 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-22 02:41:46,673 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-22 02:41:46,674 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-22 02:41:46,676 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-22 02:41:46,677 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-22 02:41:46,677 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-22 02:41:46,678 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-22 02:41:46,678 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-22 02:41:46,679 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-22 02:41:46,679 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-22 02:41:46,680 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-22 02:41:46,681 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-22 02:41:46,681 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-22 02:41:46,682 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-22 02:41:46,682 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-22 02:41:46,683 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-22 02:41:46,683 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-22 02:41:46,684 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-22 02:41:46,684 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-22 02:41:46,685 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-22 02:41:46,686 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-22 02:41:46,713 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-22 02:41:46,714 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-22 02:41:46,715 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-22 02:41:46,715 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-22 02:41:46,717 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-22 02:41:46,717 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-22 02:41:46,717 INFO L138 SettingsManager]: * Use SBE=true [2022-07-22 02:41:46,718 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-22 02:41:46,718 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-22 02:41:46,718 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-22 02:41:46,719 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-22 02:41:46,719 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-22 02:41:46,719 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-22 02:41:46,719 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-22 02:41:46,719 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-22 02:41:46,720 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-22 02:41:46,720 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-22 02:41:46,720 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-22 02:41:46,720 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-22 02:41:46,720 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-22 02:41:46,721 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-22 02:41:46,721 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-22 02:41:46,721 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-22 02:41:46,721 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-22 02:41:46,721 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-22 02:41:46,722 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-22 02:41:46,722 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-22 02:41:46,722 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-22 02:41:46,722 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-22 02:41:46,723 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-22 02:41:46,723 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-22 02:41:46,724 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-22 02:41:46,724 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2022-07-22 02:41:47,066 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-22 02:41:47,096 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-22 02:41:47,099 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-22 02:41:47,100 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-22 02:41:47,100 INFO L275 PluginConnector]: CDTParser initialized [2022-07-22 02:41:47,103 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2022-07-22 02:41:47,159 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/588299cab/6050ac7b97d8443382fee84c2c7cc4bd/FLAG99504eb17 [2022-07-22 02:41:47,642 INFO L306 CDTParser]: Found 1 translation units. [2022-07-22 02:41:47,643 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2022-07-22 02:41:47,651 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/588299cab/6050ac7b97d8443382fee84c2c7cc4bd/FLAG99504eb17 [2022-07-22 02:41:48,007 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/588299cab/6050ac7b97d8443382fee84c2c7cc4bd [2022-07-22 02:41:48,010 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-22 02:41:48,012 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-22 02:41:48,013 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-22 02:41:48,013 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-22 02:41:48,016 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-22 02:41:48,017 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,018 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@59d92602 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48, skipping insertion in model container [2022-07-22 02:41:48,019 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,025 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-22 02:41:48,067 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-22 02:41:48,195 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2022-07-22 02:41:48,242 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:41:48,261 INFO L203 MainTranslator]: Completed pre-run [2022-07-22 02:41:48,271 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2022-07-22 02:41:48,312 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:41:48,342 INFO L208 MainTranslator]: Completed translation [2022-07-22 02:41:48,343 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48 WrapperNode [2022-07-22 02:41:48,343 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-22 02:41:48,344 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-22 02:41:48,344 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-22 02:41:48,344 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-22 02:41:48,350 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,374 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,418 INFO L137 Inliner]: procedures = 31, calls = 35, calls flagged for inlining = 30, calls inlined = 33, statements flattened = 406 [2022-07-22 02:41:48,419 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-22 02:41:48,419 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-22 02:41:48,419 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-22 02:41:48,420 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-22 02:41:48,426 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,426 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,438 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,438 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,451 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,461 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,469 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,473 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-22 02:41:48,476 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-22 02:41:48,477 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-22 02:41:48,478 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-22 02:41:48,479 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (1/1) ... [2022-07-22 02:41:48,484 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-22 02:41:48,494 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-22 02:41:48,508 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-22 02:41:48,524 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-22 02:41:48,553 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-22 02:41:48,553 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-22 02:41:48,553 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-22 02:41:48,554 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-22 02:41:48,647 INFO L234 CfgBuilder]: Building ICFG [2022-07-22 02:41:48,648 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-22 02:41:49,071 INFO L764 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2022-07-22 02:41:49,071 INFO L764 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2022-07-22 02:41:49,072 INFO L275 CfgBuilder]: Performing block encoding [2022-07-22 02:41:49,078 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-22 02:41:49,079 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-07-22 02:41:49,081 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:41:49 BoogieIcfgContainer [2022-07-22 02:41:49,081 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-22 02:41:49,082 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-22 02:41:49,082 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-22 02:41:49,085 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-22 02:41:49,085 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:41:49,086 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.07 02:41:48" (1/3) ... [2022-07-22 02:41:49,087 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@163ad5eb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:41:49, skipping insertion in model container [2022-07-22 02:41:49,087 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:41:49,087 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:41:48" (2/3) ... [2022-07-22 02:41:49,087 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@163ad5eb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:41:49, skipping insertion in model container [2022-07-22 02:41:49,087 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:41:49,088 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:41:49" (3/3) ... [2022-07-22 02:41:49,089 INFO L354 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2022-07-22 02:41:49,136 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-22 02:41:49,137 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-22 02:41:49,137 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-22 02:41:49,137 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-22 02:41:49,137 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-22 02:41:49,138 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-22 02:41:49,138 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-22 02:41:49,138 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-22 02:41:49,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:49,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2022-07-22 02:41:49,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:49,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:49,181 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:49,182 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:49,182 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-22 02:41:49,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:49,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2022-07-22 02:41:49,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:49,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:49,206 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:49,206 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:49,212 INFO L752 eck$LassoCheckResult]: Stem: 130#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 38#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 28#L551true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30#L258true assume !(1 == ~q_req_up~0); 67#L258-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59#L273true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 108#L273-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 96#L278-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47#L311true assume !(0 == ~q_read_ev~0); 97#L311-2true assume !(0 == ~q_write_ev~0); 75#L316-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 34#L66true assume 1 == ~p_dw_pc~0; 129#L67true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 54#L87true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 89#L88true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 52#L387true assume !(0 != activate_threads_~tmp~1#1); 102#L387-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 81#L95true assume 1 == ~c_dr_pc~0; 115#L96true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 26#L116true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6#L117true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 76#L395true assume !(0 != activate_threads_~tmp___0~1#1); 13#L395-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32#L329true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 55#L329-2true assume !(1 == ~q_write_ev~0); 36#L334-1true assume { :end_inline_reset_delta_events } true; 126#L491-2true [2022-07-22 02:41:49,214 INFO L754 eck$LassoCheckResult]: Loop: 126#L491-2true assume !false; 127#L492true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 93#L435true assume !true; 143#L451true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58#L258-3true assume !(1 == ~q_req_up~0); 105#L258-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 131#L311-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 109#L311-5true assume !(0 == ~q_write_ev~0); 68#L316-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 107#L66-3true assume 1 == ~p_dw_pc~0; 90#L67-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 10#L87-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 125#L88-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 120#L387-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 35#L387-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 123#L95-3true assume 1 == ~c_dr_pc~0; 63#L96-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 99#L116-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 94#L117-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 132#L395-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 19#L395-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43#L329-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 84#L329-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 139#L334-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 50#L291-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 100#L303-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 101#L304-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 77#L510true assume !(0 == start_simulation_~tmp~4#1); 7#L510-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 72#L291-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 88#L303-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 92#L304-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 140#L465true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 33#L472true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 136#L473true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 74#L523true assume !(0 != start_simulation_~tmp___0~3#1); 126#L491-2true [2022-07-22 02:41:49,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:49,229 INFO L85 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2022-07-22 02:41:49,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:49,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564044508] [2022-07-22 02:41:49,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:49,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:49,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:49,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:49,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:49,396 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564044508] [2022-07-22 02:41:49,397 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564044508] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:49,397 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:49,398 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:41:49,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826610099] [2022-07-22 02:41:49,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:49,405 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:41:49,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:49,407 INFO L85 PathProgramCache]: Analyzing trace with hash 784504738, now seen corresponding path program 1 times [2022-07-22 02:41:49,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:49,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877784851] [2022-07-22 02:41:49,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:49,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:49,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:49,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:49,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:49,452 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877784851] [2022-07-22 02:41:49,452 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1877784851] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:49,452 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:49,452 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:41:49,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731853442] [2022-07-22 02:41:49,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:49,453 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:41:49,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:41:49,493 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:41:49,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:41:49,497 INFO L87 Difference]: Start difference. First operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:49,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:41:49,538 INFO L93 Difference]: Finished difference Result 140 states and 207 transitions. [2022-07-22 02:41:49,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:41:49,547 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 207 transitions. [2022-07-22 02:41:49,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2022-07-22 02:41:49,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 134 states and 201 transitions. [2022-07-22 02:41:49,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134 [2022-07-22 02:41:49,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134 [2022-07-22 02:41:49,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134 states and 201 transitions. [2022-07-22 02:41:49,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:41:49,566 INFO L369 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2022-07-22 02:41:49,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states and 201 transitions. [2022-07-22 02:41:49,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2022-07-22 02:41:49,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:49,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 201 transitions. [2022-07-22 02:41:49,603 INFO L392 hiAutomatonCegarLoop]: Abstraction has 134 states and 201 transitions. [2022-07-22 02:41:49,604 INFO L374 stractBuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2022-07-22 02:41:49,604 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-22 02:41:49,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 201 transitions. [2022-07-22 02:41:49,606 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2022-07-22 02:41:49,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:49,607 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:49,609 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:49,609 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:49,611 INFO L752 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 336#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337#L258 assume !(1 == ~q_req_up~0); 341#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 386#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 387#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 410#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 365#L311 assume !(0 == ~q_read_ev~0); 366#L311-2 assume !(0 == ~q_write_ev~0); 396#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 345#L66 assume 1 == ~p_dw_pc~0; 347#L67 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 379#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 380#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 375#L387 assume !(0 != activate_threads_~tmp~1#1); 376#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 400#L95 assume 1 == ~c_dr_pc~0; 402#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 333#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 298#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 299#L395 assume !(0 != activate_threads_~tmp___0~1#1); 311#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 344#L329-2 assume !(1 == ~q_write_ev~0); 350#L334-1 assume { :end_inline_reset_delta_events } true; 351#L491-2 [2022-07-22 02:41:49,615 INFO L754 eck$LassoCheckResult]: Loop: 351#L491-2 assume !false; 423#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 352#L435 assume !false; 381#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 382#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 297#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 411#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 412#L415 assume !(0 != eval_~tmp___1~0#1); 420#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383#L258-3 assume !(1 == ~q_req_up~0); 385#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 415#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 418#L311-5 assume !(0 == ~q_write_ev~0); 393#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 394#L66-3 assume 1 == ~p_dw_pc~0; 406#L67-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 303#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 308#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 422#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 348#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 349#L95-3 assume 1 == ~c_dr_pc~0; 389#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 390#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 408#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 409#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 318#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 361#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 403#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 372#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 373#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 413#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 397#L510 assume !(0 == start_simulation_~tmp~4#1); 300#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 301#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 335#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 405#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 407#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 342#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 343#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 395#L523 assume !(0 != start_simulation_~tmp___0~3#1); 351#L491-2 [2022-07-22 02:41:49,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:49,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2022-07-22 02:41:49,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:49,618 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205401327] [2022-07-22 02:41:49,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:49,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:49,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:49,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:49,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:49,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205401327] [2022-07-22 02:41:49,720 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1205401327] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:49,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:49,722 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-22 02:41:49,722 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101058641] [2022-07-22 02:41:49,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:49,724 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:41:49,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:49,731 INFO L85 PathProgramCache]: Analyzing trace with hash 2119142840, now seen corresponding path program 1 times [2022-07-22 02:41:49,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:49,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589899245] [2022-07-22 02:41:49,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:49,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:49,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:49,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:49,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:49,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [589899245] [2022-07-22 02:41:49,805 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [589899245] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:49,805 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:49,805 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:41:49,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508789565] [2022-07-22 02:41:49,805 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:49,806 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:41:49,806 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:41:49,806 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-22 02:41:49,807 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-22 02:41:49,807 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. cyclomatic complexity: 68 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:50,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:41:50,002 INFO L93 Difference]: Finished difference Result 479 states and 696 transitions. [2022-07-22 02:41:50,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-22 02:41:50,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 696 transitions. [2022-07-22 02:41:50,007 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 446 [2022-07-22 02:41:50,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 479 states and 696 transitions. [2022-07-22 02:41:50,013 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 479 [2022-07-22 02:41:50,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 479 [2022-07-22 02:41:50,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 479 states and 696 transitions. [2022-07-22 02:41:50,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:41:50,021 INFO L369 hiAutomatonCegarLoop]: Abstraction has 479 states and 696 transitions. [2022-07-22 02:41:50,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states and 696 transitions. [2022-07-22 02:41:50,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 466. [2022-07-22 02:41:50,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:50,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 683 transitions. [2022-07-22 02:41:50,050 INFO L392 hiAutomatonCegarLoop]: Abstraction has 466 states and 683 transitions. [2022-07-22 02:41:50,050 INFO L374 stractBuchiCegarLoop]: Abstraction has 466 states and 683 transitions. [2022-07-22 02:41:50,050 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-22 02:41:50,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 466 states and 683 transitions. [2022-07-22 02:41:50,053 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 435 [2022-07-22 02:41:50,053 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:50,053 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:50,054 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:50,054 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:50,055 INFO L752 eck$LassoCheckResult]: Stem: 1065#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 983#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 967#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 968#L258 assume !(1 == ~q_req_up~0); 971#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1014#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1015#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1046#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 994#L311 assume !(0 == ~q_read_ev~0); 995#L311-2 assume !(0 == ~q_write_ev~0); 1026#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 975#L66 assume !(1 == ~p_dw_pc~0); 976#L66-2 assume !(2 == ~p_dw_pc~0); 987#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 1007#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1008#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1003#L387 assume !(0 != activate_threads_~tmp~1#1); 1004#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1031#L95 assume 1 == ~c_dr_pc~0; 1033#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 964#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 926#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 927#L395 assume !(0 != activate_threads_~tmp___0~1#1); 939#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 940#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 972#L329-2 assume !(1 == ~q_write_ev~0); 979#L334-1 assume { :end_inline_reset_delta_events } true; 980#L491-2 [2022-07-22 02:41:50,055 INFO L754 eck$LassoCheckResult]: Loop: 980#L491-2 assume !false; 1064#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 981#L435 assume !false; 1009#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1010#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 925#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1047#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1048#L415 assume !(0 != eval_~tmp___1~0#1); 1056#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1012#L258-3 assume !(1 == ~q_req_up~0); 1013#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1051#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1054#L311-5 assume !(0 == ~q_write_ev~0); 1021#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1022#L66-3 assume !(1 == ~p_dw_pc~0); 999#L66-5 assume !(2 == ~p_dw_pc~0); 930#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 931#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 935#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1061#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 977#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 978#L95-3 assume 1 == ~c_dr_pc~0; 1017#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1018#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1044#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1045#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1066#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1328#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1327#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1326#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1325#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1323#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1322#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1321#L510 assume !(0 == start_simulation_~tmp~4#1); 928#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 929#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 966#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1039#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1043#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 973#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 974#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1025#L523 assume !(0 != start_simulation_~tmp___0~3#1); 980#L491-2 [2022-07-22 02:41:50,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:50,056 INFO L85 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2022-07-22 02:41:50,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:50,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247710764] [2022-07-22 02:41:50,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:50,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:50,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:50,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:50,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:50,125 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1247710764] [2022-07-22 02:41:50,125 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1247710764] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:50,126 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:50,126 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-22 02:41:50,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515460295] [2022-07-22 02:41:50,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:50,127 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:41:50,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:50,127 INFO L85 PathProgramCache]: Analyzing trace with hash 1851475893, now seen corresponding path program 1 times [2022-07-22 02:41:50,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:50,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688986709] [2022-07-22 02:41:50,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:50,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:50,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:50,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:50,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:50,160 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [688986709] [2022-07-22 02:41:50,160 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [688986709] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:50,160 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:50,160 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:41:50,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083570448] [2022-07-22 02:41:50,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:50,161 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:41:50,161 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:41:50,162 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-22 02:41:50,162 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-22 02:41:50,162 INFO L87 Difference]: Start difference. First operand 466 states and 683 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 5.4) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:50,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:41:50,272 INFO L93 Difference]: Finished difference Result 1105 states and 1581 transitions. [2022-07-22 02:41:50,273 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-22 02:41:50,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1105 states and 1581 transitions. [2022-07-22 02:41:50,281 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1070 [2022-07-22 02:41:50,286 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1105 states to 1105 states and 1581 transitions. [2022-07-22 02:41:50,287 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1105 [2022-07-22 02:41:50,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1105 [2022-07-22 02:41:50,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1105 states and 1581 transitions. [2022-07-22 02:41:50,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:41:50,289 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1105 states and 1581 transitions. [2022-07-22 02:41:50,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1105 states and 1581 transitions. [2022-07-22 02:41:50,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1105 to 1072. [2022-07-22 02:41:50,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:50,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1072 states to 1072 states and 1538 transitions. [2022-07-22 02:41:50,315 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2022-07-22 02:41:50,315 INFO L374 stractBuchiCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2022-07-22 02:41:50,315 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-22 02:41:50,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1072 states and 1538 transitions. [2022-07-22 02:41:50,322 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1038 [2022-07-22 02:41:50,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:50,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:50,324 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:50,324 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:50,324 INFO L752 eck$LassoCheckResult]: Stem: 2664#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 2569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2555#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2556#L258 assume !(1 == ~q_req_up~0); 2557#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2603#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2604#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2642#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2581#L311 assume !(0 == ~q_read_ev~0); 2582#L311-2 assume !(0 == ~q_write_ev~0); 2618#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2563#L66 assume !(1 == ~p_dw_pc~0); 2564#L66-2 assume !(2 == ~p_dw_pc~0); 2574#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 2599#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2600#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2593#L387 assume !(0 != activate_threads_~tmp~1#1); 2594#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2626#L95 assume !(1 == ~c_dr_pc~0); 2627#L95-2 assume !(2 == ~c_dr_pc~0); 2605#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 2550#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2511#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2512#L395 assume !(0 != activate_threads_~tmp___0~1#1); 2526#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2527#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2560#L329-2 assume !(1 == ~q_write_ev~0); 2567#L334-1 assume { :end_inline_reset_delta_events } true; 2568#L491-2 [2022-07-22 02:41:50,325 INFO L754 eck$LassoCheckResult]: Loop: 2568#L491-2 assume !false; 2663#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2565#L435 assume !false; 2597#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2598#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2510#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2647#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2648#L415 assume !(0 != eval_~tmp___1~0#1); 2655#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3311#L258-3 assume !(1 == ~q_req_up~0); 3312#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3532#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 3531#L311-5 assume !(0 == ~q_write_ev~0); 3530#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3529#L66-3 assume !(1 == ~p_dw_pc~0); 2585#L66-5 assume !(2 == ~p_dw_pc~0); 2586#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 3576#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3575#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3574#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3573#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3571#L95-3 assume !(1 == ~c_dr_pc~0); 3570#L95-5 assume !(2 == ~c_dr_pc~0); 3569#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 3568#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2640#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2641#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2534#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2535#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2573#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2666#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2590#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2591#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3365#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3363#L510 assume !(0 == start_simulation_~tmp~4#1); 3361#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3360#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3358#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3356#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3354#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3353#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3352#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3351#L523 assume !(0 != start_simulation_~tmp___0~3#1); 2568#L491-2 [2022-07-22 02:41:50,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:50,326 INFO L85 PathProgramCache]: Analyzing trace with hash 156116973, now seen corresponding path program 1 times [2022-07-22 02:41:50,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:50,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880572475] [2022-07-22 02:41:50,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:50,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:50,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:50,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:50,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:50,371 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880572475] [2022-07-22 02:41:50,371 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [880572475] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:50,371 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:50,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:41:50,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7762257] [2022-07-22 02:41:50,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:50,379 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:41:50,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:50,380 INFO L85 PathProgramCache]: Analyzing trace with hash 1021819368, now seen corresponding path program 1 times [2022-07-22 02:41:50,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:50,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189586968] [2022-07-22 02:41:50,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:50,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:50,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:50,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:50,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:50,421 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189586968] [2022-07-22 02:41:50,421 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [189586968] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:50,421 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:50,421 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:41:50,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1573723912] [2022-07-22 02:41:50,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:50,422 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:41:50,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:41:50,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:41:50,424 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:41:50,424 INFO L87 Difference]: Start difference. First operand 1072 states and 1538 transitions. cyclomatic complexity: 470 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:50,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:41:50,454 INFO L93 Difference]: Finished difference Result 1742 states and 2482 transitions. [2022-07-22 02:41:50,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:41:50,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1742 states and 2482 transitions. [2022-07-22 02:41:50,466 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2022-07-22 02:41:50,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1742 states to 1742 states and 2482 transitions. [2022-07-22 02:41:50,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1742 [2022-07-22 02:41:50,477 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1742 [2022-07-22 02:41:50,477 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1742 states and 2482 transitions. [2022-07-22 02:41:50,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:41:50,479 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2022-07-22 02:41:50,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1742 states and 2482 transitions. [2022-07-22 02:41:50,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1742 to 1742. [2022-07-22 02:41:50,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:50,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1742 states to 1742 states and 2482 transitions. [2022-07-22 02:41:50,515 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2022-07-22 02:41:50,515 INFO L374 stractBuchiCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2022-07-22 02:41:50,515 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-22 02:41:50,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1742 states and 2482 transitions. [2022-07-22 02:41:50,522 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2022-07-22 02:41:50,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:50,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:50,523 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:50,523 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:50,523 INFO L752 eck$LassoCheckResult]: Stem: 5488#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 5394#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5380#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5381#L258 assume !(1 == ~q_req_up~0); 5382#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5429#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5430#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5468#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5407#L311 assume !(0 == ~q_read_ev~0); 5408#L311-2 assume !(0 == ~q_write_ev~0); 5445#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5388#L66 assume !(1 == ~p_dw_pc~0); 5389#L66-2 assume !(2 == ~p_dw_pc~0); 5399#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 5422#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5423#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5416#L387 assume !(0 != activate_threads_~tmp~1#1); 5417#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5455#L95 assume !(1 == ~c_dr_pc~0); 5456#L95-2 assume !(2 == ~c_dr_pc~0); 5431#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 5375#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5335#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5336#L395 assume !(0 != activate_threads_~tmp___0~1#1); 5350#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5351#L329 assume !(1 == ~q_read_ev~0); 5385#L329-2 assume !(1 == ~q_write_ev~0); 5392#L334-1 assume { :end_inline_reset_delta_events } true; 5393#L491-2 [2022-07-22 02:41:50,524 INFO L754 eck$LassoCheckResult]: Loop: 5393#L491-2 assume !false; 5623#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5619#L435 assume !false; 5616#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5611#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5607#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5604#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5599#L415 assume !(0 != eval_~tmp___1~0#1); 5600#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5723#L258-3 assume !(1 == ~q_req_up~0); 5721#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5719#L311-3 assume !(0 == ~q_read_ev~0); 5717#L311-5 assume !(0 == ~q_write_ev~0); 5715#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5713#L66-3 assume !(1 == ~p_dw_pc~0); 5711#L66-5 assume !(2 == ~p_dw_pc~0); 5708#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 5706#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5703#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5701#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5699#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5697#L95-3 assume !(1 == ~c_dr_pc~0); 5695#L95-5 assume !(2 == ~c_dr_pc~0); 5693#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 5691#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5689#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5687#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5685#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5683#L329-3 assume !(1 == ~q_read_ev~0); 5681#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5679#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5677#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5670#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5663#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5656#L510 assume !(0 == start_simulation_~tmp~4#1); 5651#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5647#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5643#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5640#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5637#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5634#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5630#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5627#L523 assume !(0 != start_simulation_~tmp___0~3#1); 5393#L491-2 [2022-07-22 02:41:50,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:50,524 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2022-07-22 02:41:50,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:50,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193277080] [2022-07-22 02:41:50,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:50,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:50,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:50,532 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-22 02:41:50,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:50,561 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-22 02:41:50,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:50,562 INFO L85 PathProgramCache]: Analyzing trace with hash 16715304, now seen corresponding path program 1 times [2022-07-22 02:41:50,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:50,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565145295] [2022-07-22 02:41:50,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:50,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:50,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:50,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:50,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:50,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565145295] [2022-07-22 02:41:50,592 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565145295] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:50,592 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:50,592 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:41:50,592 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883647643] [2022-07-22 02:41:50,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:50,593 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:41:50,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:41:50,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-22 02:41:50,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-22 02:41:50,594 INFO L87 Difference]: Start difference. First operand 1742 states and 2482 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:50,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:41:50,681 INFO L93 Difference]: Finished difference Result 2947 states and 4108 transitions. [2022-07-22 02:41:50,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-22 02:41:50,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2947 states and 4108 transitions. [2022-07-22 02:41:50,717 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2907 [2022-07-22 02:41:50,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2947 states to 2947 states and 4108 transitions. [2022-07-22 02:41:50,733 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2947 [2022-07-22 02:41:50,735 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2947 [2022-07-22 02:41:50,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2947 states and 4108 transitions. [2022-07-22 02:41:50,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:41:50,740 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2947 states and 4108 transitions. [2022-07-22 02:41:50,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2947 states and 4108 transitions. [2022-07-22 02:41:50,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2947 to 1805. [2022-07-22 02:41:50,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:50,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2545 transitions. [2022-07-22 02:41:50,773 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2022-07-22 02:41:50,774 INFO L374 stractBuchiCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2022-07-22 02:41:50,774 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-22 02:41:50,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2545 transitions. [2022-07-22 02:41:50,781 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1771 [2022-07-22 02:41:50,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:50,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:50,782 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:50,782 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:50,782 INFO L752 eck$LassoCheckResult]: Stem: 10196#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 10102#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10087#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10088#L258 assume !(1 == ~q_req_up~0); 10089#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10136#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 10137#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10173#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10114#L311 assume !(0 == ~q_read_ev~0); 10115#L311-2 assume !(0 == ~q_write_ev~0); 10151#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10095#L66 assume !(1 == ~p_dw_pc~0); 10096#L66-2 assume !(2 == ~p_dw_pc~0); 10107#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 10129#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10130#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10123#L387 assume !(0 != activate_threads_~tmp~1#1); 10124#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10159#L95 assume !(1 == ~c_dr_pc~0); 10160#L95-2 assume !(2 == ~c_dr_pc~0); 10138#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 10082#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10040#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10041#L395 assume !(0 != activate_threads_~tmp___0~1#1); 10055#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10056#L329 assume !(1 == ~q_read_ev~0); 10092#L329-2 assume !(1 == ~q_write_ev~0); 10100#L334-1 assume { :end_inline_reset_delta_events } true; 10101#L491-2 [2022-07-22 02:41:50,782 INFO L754 eck$LassoCheckResult]: Loop: 10101#L491-2 assume !false; 10436#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10369#L435 assume !false; 10366#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10364#L291 assume !(0 == ~p_dw_st~0); 10360#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10358#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10347#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10345#L415 assume !(0 != eval_~tmp___1~0#1); 10344#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10343#L258-3 assume !(1 == ~q_req_up~0); 10342#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10341#L311-3 assume !(0 == ~q_read_ev~0); 10340#L311-5 assume !(0 == ~q_write_ev~0); 10339#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10338#L66-3 assume !(1 == ~p_dw_pc~0); 10336#L66-5 assume !(2 == ~p_dw_pc~0); 10337#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 10312#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10313#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10306#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 10307#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10297#L95-3 assume !(1 == ~c_dr_pc~0); 10298#L95-5 assume !(2 == ~c_dr_pc~0); 10468#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 10467#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10466#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10465#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 10464#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10463#L329-3 assume !(1 == ~q_read_ev~0); 10462#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 10461#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10460#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10457#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10455#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10452#L510 assume !(0 == start_simulation_~tmp~4#1); 10450#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10449#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10447#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10446#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10445#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 10444#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10443#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10440#L523 assume !(0 != start_simulation_~tmp___0~3#1); 10101#L491-2 [2022-07-22 02:41:50,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:50,783 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2022-07-22 02:41:50,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:50,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131574716] [2022-07-22 02:41:50,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:50,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:50,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:50,790 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-22 02:41:50,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:50,800 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-22 02:41:50,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:50,801 INFO L85 PathProgramCache]: Analyzing trace with hash 526545300, now seen corresponding path program 1 times [2022-07-22 02:41:50,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:50,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715746557] [2022-07-22 02:41:50,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:50,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:50,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:50,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:50,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:50,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715746557] [2022-07-22 02:41:50,870 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715746557] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:50,870 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:50,870 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:41:50,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719397823] [2022-07-22 02:41:50,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:50,871 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:41:50,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:41:50,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-22 02:41:50,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-22 02:41:50,871 INFO L87 Difference]: Start difference. First operand 1805 states and 2545 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:50,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:41:50,943 INFO L93 Difference]: Finished difference Result 4219 states and 5928 transitions. [2022-07-22 02:41:50,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-22 02:41:50,944 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4219 states and 5928 transitions. [2022-07-22 02:41:50,984 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4181 [2022-07-22 02:41:51,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4219 states to 4219 states and 5928 transitions. [2022-07-22 02:41:51,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4219 [2022-07-22 02:41:51,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4219 [2022-07-22 02:41:51,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4219 states and 5928 transitions. [2022-07-22 02:41:51,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:41:51,015 INFO L369 hiAutomatonCegarLoop]: Abstraction has 4219 states and 5928 transitions. [2022-07-22 02:41:51,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4219 states and 5928 transitions. [2022-07-22 02:41:51,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4219 to 1883. [2022-07-22 02:41:51,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:51,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1883 states to 1883 states and 2606 transitions. [2022-07-22 02:41:51,068 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2022-07-22 02:41:51,068 INFO L374 stractBuchiCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2022-07-22 02:41:51,069 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-22 02:41:51,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1883 states and 2606 transitions. [2022-07-22 02:41:51,080 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1849 [2022-07-22 02:41:51,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:51,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:51,081 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:51,081 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:51,083 INFO L752 eck$LassoCheckResult]: Stem: 16230#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 16136#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 16120#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16121#L258 assume !(1 == ~q_req_up~0); 16124#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16171#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 16172#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 16210#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16149#L311 assume !(0 == ~q_read_ev~0); 16150#L311-2 assume !(0 == ~q_write_ev~0); 16186#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 16128#L66 assume !(1 == ~p_dw_pc~0); 16129#L66-2 assume !(2 == ~p_dw_pc~0); 16140#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 16165#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 16166#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 16161#L387 assume !(0 != activate_threads_~tmp~1#1); 16162#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 16195#L95 assume !(1 == ~c_dr_pc~0); 16196#L95-2 assume !(2 == ~c_dr_pc~0); 16173#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 16117#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 16078#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16079#L395 assume !(0 != activate_threads_~tmp___0~1#1); 16092#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16093#L329 assume !(1 == ~q_read_ev~0); 16125#L329-2 assume !(1 == ~q_write_ev~0); 16132#L334-1 assume { :end_inline_reset_delta_events } true; 16133#L491-2 [2022-07-22 02:41:51,084 INFO L754 eck$LassoCheckResult]: Loop: 16133#L491-2 assume !false; 16431#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 16324#L435 assume !false; 16429#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16418#L291 assume !(0 == ~p_dw_st~0); 16419#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 16420#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16414#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 16415#L415 assume !(0 != eval_~tmp___1~0#1); 16475#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16474#L258-3 assume !(1 == ~q_req_up~0); 16473#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16472#L311-3 assume !(0 == ~q_read_ev~0); 16471#L311-5 assume !(0 == ~q_write_ev~0); 16470#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 16469#L66-3 assume !(1 == ~p_dw_pc~0); 16153#L66-5 assume !(2 == ~p_dw_pc~0); 16154#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 16444#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 16443#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 16440#L387-3 assume !(0 != activate_threads_~tmp~1#1); 16438#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 16436#L95-3 assume !(1 == ~c_dr_pc~0); 16421#L95-5 assume !(2 == ~c_dr_pc~0); 16279#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 16272#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 16271#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16270#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 16269#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16268#L329-3 assume !(1 == ~q_read_ev~0); 16267#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 16265#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16266#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 16261#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16260#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 16257#L510 assume !(0 == start_simulation_~tmp~4#1); 16258#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16442#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 16439#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16437#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 16435#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 16434#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16433#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 16432#L523 assume !(0 != start_simulation_~tmp___0~3#1); 16133#L491-2 [2022-07-22 02:41:51,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:51,085 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2022-07-22 02:41:51,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:51,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081300949] [2022-07-22 02:41:51,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:51,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:51,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:51,097 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-22 02:41:51,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:51,124 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-22 02:41:51,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:51,125 INFO L85 PathProgramCache]: Analyzing trace with hash 392531794, now seen corresponding path program 1 times [2022-07-22 02:41:51,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:51,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508101696] [2022-07-22 02:41:51,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:51,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:51,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:51,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:51,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:51,194 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508101696] [2022-07-22 02:41:51,194 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508101696] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:51,195 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:51,195 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:41:51,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858251071] [2022-07-22 02:41:51,195 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:51,195 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:41:51,196 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:41:51,196 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:41:51,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:41:51,196 INFO L87 Difference]: Start difference. First operand 1883 states and 2606 transitions. cyclomatic complexity: 727 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:51,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:41:51,263 INFO L93 Difference]: Finished difference Result 2972 states and 4013 transitions. [2022-07-22 02:41:51,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:41:51,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2972 states and 4013 transitions. [2022-07-22 02:41:51,294 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-07-22 02:41:51,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2972 states to 2972 states and 4013 transitions. [2022-07-22 02:41:51,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2972 [2022-07-22 02:41:51,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2972 [2022-07-22 02:41:51,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2972 states and 4013 transitions. [2022-07-22 02:41:51,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:41:51,347 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2022-07-22 02:41:51,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states and 4013 transitions. [2022-07-22 02:41:51,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 2972. [2022-07-22 02:41:51,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:51,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2972 states to 2972 states and 4013 transitions. [2022-07-22 02:41:51,402 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2022-07-22 02:41:51,402 INFO L374 stractBuchiCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2022-07-22 02:41:51,402 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-22 02:41:51,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2972 states and 4013 transitions. [2022-07-22 02:41:51,418 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-07-22 02:41:51,419 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:51,419 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:51,419 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:51,420 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:51,420 INFO L752 eck$LassoCheckResult]: Stem: 21114#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 20997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 20982#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20983#L258 assume !(1 == ~q_req_up~0); 20984#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21032#L273 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 21033#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 21077#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21078#L311 assume !(0 == ~q_read_ev~0); 21084#L311-2 assume !(0 == ~q_write_ev~0); 21085#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 20989#L66 assume !(1 == ~p_dw_pc~0); 20990#L66-2 assume !(2 == ~p_dw_pc~0); 21111#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 21112#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 21068#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 21069#L387 assume !(0 != activate_threads_~tmp~1#1); 21087#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 21088#L95 assume !(1 == ~c_dr_pc~0); 21089#L95-2 assume !(2 == ~c_dr_pc~0); 21090#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 20976#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 20977#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21052#L395 assume !(0 != activate_threads_~tmp___0~1#1); 21053#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20987#L329 assume !(1 == ~q_read_ev~0); 20988#L329-2 assume !(1 == ~q_write_ev~0); 20995#L334-1 assume { :end_inline_reset_delta_events } true; 20996#L491-2 [2022-07-22 02:41:51,420 INFO L754 eck$LassoCheckResult]: Loop: 20996#L491-2 assume !false; 21205#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 21180#L435 assume !false; 21200#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21198#L291 assume !(0 == ~p_dw_st~0); 21196#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21194#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21191#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 21187#L415 assume !(0 != eval_~tmp___1~0#1); 21188#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21261#L258-3 assume !(1 == ~q_req_up~0); 21260#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21259#L311-3 assume !(0 == ~q_read_ev~0); 21258#L311-5 assume !(0 == ~q_write_ev~0); 21257#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 21256#L66-3 assume !(1 == ~p_dw_pc~0); 21255#L66-5 assume !(2 == ~p_dw_pc~0); 21254#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 21253#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 21252#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 21250#L387-3 assume !(0 != activate_threads_~tmp~1#1); 21248#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 21246#L95-3 assume !(1 == ~c_dr_pc~0); 21244#L95-5 assume !(2 == ~c_dr_pc~0); 21242#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 21240#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21238#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21236#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 21234#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21232#L329-3 assume !(1 == ~q_read_ev~0); 21230#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 21228#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21226#L291-1 assume !(0 == ~p_dw_st~0); 21224#L295-1 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21222#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21220#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 21217#L510 assume !(0 == start_simulation_~tmp~4#1); 21215#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21214#L291-2 assume !(0 == ~p_dw_st~0); 21213#L295-2 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21212#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21211#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 21210#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 21209#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21208#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21207#L523 assume !(0 != start_simulation_~tmp___0~3#1); 20996#L491-2 [2022-07-22 02:41:51,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:51,421 INFO L85 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2022-07-22 02:41:51,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:51,421 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007766743] [2022-07-22 02:41:51,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:51,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:51,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:51,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:51,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:51,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007766743] [2022-07-22 02:41:51,460 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007766743] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:51,460 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:51,460 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:41:51,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [274656822] [2022-07-22 02:41:51,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:51,460 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:41:51,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:51,461 INFO L85 PathProgramCache]: Analyzing trace with hash 2092921140, now seen corresponding path program 1 times [2022-07-22 02:41:51,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:51,461 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698103792] [2022-07-22 02:41:51,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:51,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:51,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:51,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:51,485 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:51,485 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698103792] [2022-07-22 02:41:51,485 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698103792] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:51,485 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:51,486 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:41:51,486 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123609211] [2022-07-22 02:41:51,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:51,488 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:41:51,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:41:51,488 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:41:51,488 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:41:51,489 INFO L87 Difference]: Start difference. First operand 2972 states and 4013 transitions. cyclomatic complexity: 1048 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:51,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:41:51,505 INFO L93 Difference]: Finished difference Result 2950 states and 3987 transitions. [2022-07-22 02:41:51,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:41:51,508 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2950 states and 3987 transitions. [2022-07-22 02:41:51,526 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-07-22 02:41:51,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2950 states to 2950 states and 3987 transitions. [2022-07-22 02:41:51,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2950 [2022-07-22 02:41:51,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2950 [2022-07-22 02:41:51,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2950 states and 3987 transitions. [2022-07-22 02:41:51,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:41:51,547 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2022-07-22 02:41:51,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2950 states and 3987 transitions. [2022-07-22 02:41:51,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2950 to 2950. [2022-07-22 02:41:51,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:51,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2950 states to 2950 states and 3987 transitions. [2022-07-22 02:41:51,611 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2022-07-22 02:41:51,611 INFO L374 stractBuchiCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2022-07-22 02:41:51,611 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-22 02:41:51,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2950 states and 3987 transitions. [2022-07-22 02:41:51,623 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-07-22 02:41:51,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:51,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:51,624 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:51,624 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:51,624 INFO L752 eck$LassoCheckResult]: Stem: 27027#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 26926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 26911#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26912#L258 assume !(1 == ~q_req_up~0); 26913#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26961#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 26962#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 27000#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26937#L311 assume !(0 == ~q_read_ev~0); 26938#L311-2 assume !(0 == ~q_write_ev~0); 26978#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 26919#L66 assume !(1 == ~p_dw_pc~0); 26920#L66-2 assume !(2 == ~p_dw_pc~0); 26930#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 26954#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 26955#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 26948#L387 assume !(0 != activate_threads_~tmp~1#1); 26949#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 26985#L95 assume !(1 == ~c_dr_pc~0); 26986#L95-2 assume !(2 == ~c_dr_pc~0); 26963#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 26906#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 26867#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 26868#L395 assume !(0 != activate_threads_~tmp___0~1#1); 26883#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26884#L329 assume !(1 == ~q_read_ev~0); 26916#L329-2 assume !(1 == ~q_write_ev~0); 26924#L334-1 assume { :end_inline_reset_delta_events } true; 26925#L491-2 assume !false; 27122#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 27121#L435 [2022-07-22 02:41:51,624 INFO L754 eck$LassoCheckResult]: Loop: 27121#L435 assume !false; 27119#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 27117#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 27115#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 27112#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 27109#L415 assume 0 != eval_~tmp___1~0#1; 27105#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 27101#L424 assume !(0 != eval_~tmp~2#1); 27102#L420 assume !(0 == ~c_dr_st~0); 27121#L435 [2022-07-22 02:41:51,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:51,625 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 1 times [2022-07-22 02:41:51,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:51,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847910162] [2022-07-22 02:41:51,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:51,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:51,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:51,632 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-22 02:41:51,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:51,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-22 02:41:51,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:51,641 INFO L85 PathProgramCache]: Analyzing trace with hash 1094877037, now seen corresponding path program 1 times [2022-07-22 02:41:51,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:51,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778845600] [2022-07-22 02:41:51,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:51,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:51,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:51,645 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-22 02:41:51,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:51,648 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-22 02:41:51,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:51,648 INFO L85 PathProgramCache]: Analyzing trace with hash -1470124195, now seen corresponding path program 1 times [2022-07-22 02:41:51,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:51,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975352522] [2022-07-22 02:41:51,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:51,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:51,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:41:51,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:41:51,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:41:51,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [975352522] [2022-07-22 02:41:51,688 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [975352522] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:41:51,688 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:41:51,688 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:41:51,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766128404] [2022-07-22 02:41:51,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:41:51,749 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:41:51,749 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:41:51,749 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:41:51,750 INFO L87 Difference]: Start difference. First operand 2950 states and 3987 transitions. cyclomatic complexity: 1044 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:51,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:41:51,815 INFO L93 Difference]: Finished difference Result 4412 states and 5918 transitions. [2022-07-22 02:41:51,815 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:41:51,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4412 states and 5918 transitions. [2022-07-22 02:41:51,847 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4373 [2022-07-22 02:41:51,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4412 states to 4412 states and 5918 transitions. [2022-07-22 02:41:51,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4412 [2022-07-22 02:41:51,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4412 [2022-07-22 02:41:51,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4412 states and 5918 transitions. [2022-07-22 02:41:51,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:41:51,909 INFO L369 hiAutomatonCegarLoop]: Abstraction has 4412 states and 5918 transitions. [2022-07-22 02:41:51,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4412 states and 5918 transitions. [2022-07-22 02:41:51,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4412 to 3868. [2022-07-22 02:41:51,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:41:51,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3868 states to 3868 states and 5220 transitions. [2022-07-22 02:41:51,984 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2022-07-22 02:41:51,984 INFO L374 stractBuchiCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2022-07-22 02:41:51,984 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-22 02:41:51,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3868 states and 5220 transitions. [2022-07-22 02:41:52,000 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3829 [2022-07-22 02:41:52,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:41:52,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:41:52,002 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:52,002 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:41:52,002 INFO L752 eck$LassoCheckResult]: Stem: 34395#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 34295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 34281#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34282#L258 assume !(1 == ~q_req_up~0); 34283#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34328#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 34329#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 34367#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34306#L311 assume !(0 == ~q_read_ev~0); 34307#L311-2 assume !(0 == ~q_write_ev~0); 34343#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 34289#L66 assume !(1 == ~p_dw_pc~0); 34290#L66-2 assume !(2 == ~p_dw_pc~0); 34301#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 34322#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 34323#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 34316#L387 assume !(0 != activate_threads_~tmp~1#1); 34317#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 34352#L95 assume !(1 == ~c_dr_pc~0); 34353#L95-2 assume !(2 == ~c_dr_pc~0); 34330#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 34276#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 34237#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 34238#L395 assume !(0 != activate_threads_~tmp___0~1#1); 34252#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34253#L329 assume !(1 == ~q_read_ev~0); 34286#L329-2 assume !(1 == ~q_write_ev~0); 34293#L334-1 assume { :end_inline_reset_delta_events } true; 34294#L491-2 assume !false; 35647#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 35638#L435 [2022-07-22 02:41:52,002 INFO L754 eck$LassoCheckResult]: Loop: 35638#L435 assume !false; 35631#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 35623#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 35617#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 35616#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 35615#L415 assume 0 != eval_~tmp___1~0#1; 35612#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 35608#L424 assume !(0 != eval_~tmp~2#1); 35609#L420 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 35648#L439 assume !(0 != eval_~tmp___0~2#1); 35638#L435 [2022-07-22 02:41:52,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:52,003 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 2 times [2022-07-22 02:41:52,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:52,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819573169] [2022-07-22 02:41:52,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:52,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:52,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:52,012 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-22 02:41:52,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:52,022 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-22 02:41:52,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:52,023 INFO L85 PathProgramCache]: Analyzing trace with hash -418551849, now seen corresponding path program 1 times [2022-07-22 02:41:52,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:52,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247605464] [2022-07-22 02:41:52,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:52,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:52,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:52,028 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-22 02:41:52,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:52,032 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-22 02:41:52,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:41:52,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1670788583, now seen corresponding path program 1 times [2022-07-22 02:41:52,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:41:52,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142098922] [2022-07-22 02:41:52,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:41:52,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:41:52,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:52,042 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-22 02:41:52,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-22 02:41:52,057 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-22 02:41:52,911 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 22.07 02:41:52 BoogieIcfgContainer [2022-07-22 02:41:52,911 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-22 02:41:52,912 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-07-22 02:41:52,912 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-07-22 02:41:52,912 INFO L275 PluginConnector]: Witness Printer initialized [2022-07-22 02:41:52,912 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:41:49" (3/4) ... [2022-07-22 02:41:52,914 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-07-22 02:41:52,967 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-07-22 02:41:52,967 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-07-22 02:41:52,968 INFO L158 Benchmark]: Toolchain (without parser) took 4956.01ms. Allocated memory was 56.6MB in the beginning and 203.4MB in the end (delta: 146.8MB). Free memory was 34.7MB in the beginning and 122.5MB in the end (delta: -87.8MB). Peak memory consumption was 115.2MB. Max. memory is 16.1GB. [2022-07-22 02:41:52,968 INFO L158 Benchmark]: CDTParser took 0.27ms. Allocated memory is still 56.6MB. Free memory was 38.2MB in the beginning and 38.2MB in the end (delta: 25.7kB). There was no memory consumed. Max. memory is 16.1GB. [2022-07-22 02:41:52,969 INFO L158 Benchmark]: CACSL2BoogieTranslator took 330.31ms. Allocated memory is still 56.6MB. Free memory was 34.6MB in the beginning and 21.5MB in the end (delta: 13.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-07-22 02:41:52,969 INFO L158 Benchmark]: Boogie Procedure Inliner took 74.74ms. Allocated memory is still 56.6MB. Free memory was 21.5MB in the beginning and 38.6MB in the end (delta: -17.1MB). Peak memory consumption was 5.4MB. Max. memory is 16.1GB. [2022-07-22 02:41:52,969 INFO L158 Benchmark]: Boogie Preprocessor took 55.93ms. Allocated memory is still 56.6MB. Free memory was 38.6MB in the beginning and 36.7MB in the end (delta: 1.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-22 02:41:52,970 INFO L158 Benchmark]: RCFGBuilder took 605.29ms. Allocated memory was 56.6MB in the beginning and 69.2MB in the end (delta: 12.6MB). Free memory was 36.7MB in the beginning and 47.0MB in the end (delta: -10.3MB). Peak memory consumption was 19.2MB. Max. memory is 16.1GB. [2022-07-22 02:41:52,970 INFO L158 Benchmark]: BuchiAutomizer took 3828.99ms. Allocated memory was 69.2MB in the beginning and 203.4MB in the end (delta: 134.2MB). Free memory was 47.0MB in the beginning and 79.1MB in the end (delta: -32.1MB). Peak memory consumption was 107.9MB. Max. memory is 16.1GB. [2022-07-22 02:41:52,970 INFO L158 Benchmark]: Witness Printer took 55.51ms. Allocated memory is still 203.4MB. Free memory was 79.1MB in the beginning and 122.5MB in the end (delta: -43.4MB). Peak memory consumption was 12.1MB. Max. memory is 16.1GB. [2022-07-22 02:41:52,972 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27ms. Allocated memory is still 56.6MB. Free memory was 38.2MB in the beginning and 38.2MB in the end (delta: 25.7kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 330.31ms. Allocated memory is still 56.6MB. Free memory was 34.6MB in the beginning and 21.5MB in the end (delta: 13.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 74.74ms. Allocated memory is still 56.6MB. Free memory was 21.5MB in the beginning and 38.6MB in the end (delta: -17.1MB). Peak memory consumption was 5.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 55.93ms. Allocated memory is still 56.6MB. Free memory was 38.6MB in the beginning and 36.7MB in the end (delta: 1.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 605.29ms. Allocated memory was 56.6MB in the beginning and 69.2MB in the end (delta: 12.6MB). Free memory was 36.7MB in the beginning and 47.0MB in the end (delta: -10.3MB). Peak memory consumption was 19.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 3828.99ms. Allocated memory was 69.2MB in the beginning and 203.4MB in the end (delta: 134.2MB). Free memory was 47.0MB in the beginning and 79.1MB in the end (delta: -32.1MB). Peak memory consumption was 107.9MB. Max. memory is 16.1GB. * Witness Printer took 55.51ms. Allocated memory is still 203.4MB. Free memory was 79.1MB in the beginning and 122.5MB in the end (delta: -43.4MB). Peak memory consumption was 12.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 3868 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.7s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 1.9s. Construction of modules took 0.3s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 9 MinimizatonAttempts, 4068 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3109 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3109 mSDsluCounter, 4252 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2626 mSDsCounter, 105 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 261 IncrementalHoareTripleChecker+Invalid, 366 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 105 mSolverCounterUnsat, 1626 mSDtfsCounter, 261 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {p_last_write=0, c_dr_i=1, c_dr_pc=0, a_t=0, NULL=0, \result=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7baaff1e=0, __retres1=0, c_num_read=0, c_dr_st=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@68d89ff1=0, q_read_ev=2, p_dw_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@679d7cf3=0, q_req_up=0, q_write_ev=2, tmp___0=0, tmp___1=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1cd37263=0, t=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1ab617e0=0, p_dw_pc=0, q_free=1, __retres1=1, fast_clk_edge=2, \result=0, p_dw_st=0, __retres1=0, q_ev=0, tmp___0=0, slow_clk_edge=2, tmp=0, c_last_read=0, NULL=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@366307f3=0, kernel_st=1, p_num_write=0, q_buf_0=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@774471dd=0, __retres1=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) [L316] COND FALSE !((int )q_write_ev == 0) [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; [L66] COND FALSE !((int )p_dw_pc == 1) [L76] COND FALSE !((int )p_dw_pc == 2) [L86] __retres1 = 0 [L88] return (__retres1); [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; [L95] COND FALSE !((int )c_dr_pc == 1) [L105] COND FALSE !((int )c_dr_pc == 2) [L115] __retres1 = 0 [L117] return (__retres1); [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) [L334] COND FALSE !((int )q_write_ev == 1) [L488] RET reset_delta_events() [L491] COND TRUE 1 [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-22 02:41:53,011 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)