./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.10.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 35987657 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.10.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 --- Real Ultimate output --- This is Ultimate 0.2.2-?-3598765 [2022-07-22 02:42:26,092 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-22 02:42:26,095 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-22 02:42:26,129 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-22 02:42:26,130 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-22 02:42:26,132 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-22 02:42:26,137 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-22 02:42:26,140 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-22 02:42:26,142 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-22 02:42:26,147 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-22 02:42:26,148 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-22 02:42:26,150 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-22 02:42:26,150 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-22 02:42:26,153 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-22 02:42:26,154 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-22 02:42:26,158 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-22 02:42:26,158 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-22 02:42:26,160 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-22 02:42:26,163 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-22 02:42:26,167 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-22 02:42:26,170 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-22 02:42:26,171 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-22 02:42:26,173 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-22 02:42:26,174 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-22 02:42:26,175 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-22 02:42:26,179 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-22 02:42:26,182 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-22 02:42:26,182 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-22 02:42:26,184 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-22 02:42:26,184 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-22 02:42:26,185 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-22 02:42:26,185 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-22 02:42:26,187 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-22 02:42:26,187 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-22 02:42:26,188 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-22 02:42:26,189 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-22 02:42:26,189 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-22 02:42:26,190 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-22 02:42:26,190 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-22 02:42:26,190 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-22 02:42:26,191 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-22 02:42:26,192 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-22 02:42:26,199 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-22 02:42:26,230 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-22 02:42:26,231 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-22 02:42:26,231 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-22 02:42:26,231 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-22 02:42:26,233 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-22 02:42:26,233 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-22 02:42:26,233 INFO L138 SettingsManager]: * Use SBE=true [2022-07-22 02:42:26,233 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-22 02:42:26,233 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-22 02:42:26,234 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-22 02:42:26,234 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-22 02:42:26,235 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-22 02:42:26,235 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-22 02:42:26,235 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-22 02:42:26,235 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-22 02:42:26,235 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-22 02:42:26,235 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-22 02:42:26,236 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-22 02:42:26,236 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-22 02:42:26,236 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-22 02:42:26,236 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-22 02:42:26,236 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-22 02:42:26,236 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-22 02:42:26,237 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-22 02:42:26,237 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-22 02:42:26,237 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-22 02:42:26,237 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-22 02:42:26,237 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-22 02:42:26,238 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-22 02:42:26,238 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-22 02:42:26,238 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-22 02:42:26,239 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-22 02:42:26,240 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 [2022-07-22 02:42:26,567 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-22 02:42:26,593 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-22 02:42:26,596 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-22 02:42:26,597 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-22 02:42:26,598 INFO L275 PluginConnector]: CDTParser initialized [2022-07-22 02:42:26,600 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2022-07-22 02:42:26,673 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/56ba7a322/2fd8068b7b3441a99618928db40180bb/FLAG368202467 [2022-07-22 02:42:27,235 INFO L306 CDTParser]: Found 1 translation units. [2022-07-22 02:42:27,236 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2022-07-22 02:42:27,252 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/56ba7a322/2fd8068b7b3441a99618928db40180bb/FLAG368202467 [2022-07-22 02:42:27,651 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/56ba7a322/2fd8068b7b3441a99618928db40180bb [2022-07-22 02:42:27,656 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-22 02:42:27,658 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-22 02:42:27,659 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-22 02:42:27,659 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-22 02:42:27,664 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-22 02:42:27,664 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:42:27" (1/1) ... [2022-07-22 02:42:27,665 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@674aed22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:27, skipping insertion in model container [2022-07-22 02:42:27,666 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:42:27" (1/1) ... [2022-07-22 02:42:27,672 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-22 02:42:27,712 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-22 02:42:27,877 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c[671,684] [2022-07-22 02:42:28,032 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:42:28,041 INFO L203 MainTranslator]: Completed pre-run [2022-07-22 02:42:28,058 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-2.c[671,684] [2022-07-22 02:42:28,129 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:42:28,146 INFO L208 MainTranslator]: Completed translation [2022-07-22 02:42:28,148 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28 WrapperNode [2022-07-22 02:42:28,148 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-22 02:42:28,150 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-22 02:42:28,150 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-22 02:42:28,150 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-22 02:42:28,157 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,188 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,294 INFO L137 Inliner]: procedures = 48, calls = 61, calls flagged for inlining = 56, calls inlined = 209, statements flattened = 3186 [2022-07-22 02:42:28,294 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-22 02:42:28,296 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-22 02:42:28,296 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-22 02:42:28,296 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-22 02:42:28,303 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,304 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,315 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,315 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,358 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,391 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,399 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,413 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-22 02:42:28,415 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-22 02:42:28,416 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-22 02:42:28,416 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-22 02:42:28,417 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (1/1) ... [2022-07-22 02:42:28,423 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-22 02:42:28,432 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-22 02:42:28,453 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-22 02:42:28,480 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-22 02:42:28,498 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-22 02:42:28,498 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-22 02:42:28,498 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-22 02:42:28,499 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-22 02:42:28,596 INFO L234 CfgBuilder]: Building ICFG [2022-07-22 02:42:28,598 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-22 02:42:30,246 INFO L275 CfgBuilder]: Performing block encoding [2022-07-22 02:42:30,260 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-22 02:42:30,260 INFO L299 CfgBuilder]: Removed 13 assume(true) statements. [2022-07-22 02:42:30,263 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:42:30 BoogieIcfgContainer [2022-07-22 02:42:30,264 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-22 02:42:30,265 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-22 02:42:30,265 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-22 02:42:30,267 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-22 02:42:30,268 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:42:30,268 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.07 02:42:27" (1/3) ... [2022-07-22 02:42:30,269 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@ee2ccbd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:42:30, skipping insertion in model container [2022-07-22 02:42:30,269 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:42:30,270 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:28" (2/3) ... [2022-07-22 02:42:30,270 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@ee2ccbd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:42:30, skipping insertion in model container [2022-07-22 02:42:30,270 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:42:30,270 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:42:30" (3/3) ... [2022-07-22 02:42:30,271 INFO L354 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-2.c [2022-07-22 02:42:30,352 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-22 02:42:30,352 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-22 02:42:30,352 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-22 02:42:30,352 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-22 02:42:30,353 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-22 02:42:30,353 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-22 02:42:30,353 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-22 02:42:30,353 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-22 02:42:30,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:30,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1224 [2022-07-22 02:42:30,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:30,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:30,453 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:30,453 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:30,454 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-22 02:42:30,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:30,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1224 [2022-07-22 02:42:30,474 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:30,474 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:30,478 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:30,479 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:30,487 INFO L752 eck$LassoCheckResult]: Stem: 629#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1245#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 22#L1516true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 561#L712true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 569#L719true assume !(1 == ~m_i~0);~m_st~0 := 2; 346#L719-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 542#L724-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 705#L729-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1235#L734-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 459#L739-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 826#L744-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 378#L749-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 662#L754-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 845#L759-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 618#L764-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 549#L769-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 833#L1024true assume !(0 == ~M_E~0); 935#L1024-2true assume !(0 == ~T1_E~0); 185#L1029-1true assume !(0 == ~T2_E~0); 245#L1034-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1312#L1039-1true assume !(0 == ~T4_E~0); 1006#L1044-1true assume !(0 == ~T5_E~0); 393#L1049-1true assume !(0 == ~T6_E~0); 1324#L1054-1true assume !(0 == ~T7_E~0); 568#L1059-1true assume !(0 == ~T8_E~0); 212#L1064-1true assume !(0 == ~T9_E~0); 792#L1069-1true assume !(0 == ~T10_E~0); 1228#L1074-1true assume 0 == ~E_M~0;~E_M~0 := 1; 874#L1079-1true assume !(0 == ~E_1~0); 836#L1084-1true assume !(0 == ~E_2~0); 1033#L1089-1true assume !(0 == ~E_3~0); 906#L1094-1true assume !(0 == ~E_4~0); 452#L1099-1true assume !(0 == ~E_5~0); 1048#L1104-1true assume !(0 == ~E_6~0); 681#L1109-1true assume !(0 == ~E_7~0); 317#L1114-1true assume 0 == ~E_8~0;~E_8~0 := 1; 1274#L1119-1true assume !(0 == ~E_9~0); 352#L1124-1true assume !(0 == ~E_10~0); 39#L1129-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 697#L502true assume 1 == ~m_pc~0; 566#L503true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 99#L513true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 741#L514true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 615#L1273true assume !(0 != activate_threads_~tmp~1#1); 1366#L1273-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1122#L521true assume !(1 == ~t1_pc~0); 1043#L521-2true is_transmit1_triggered_~__retres1~1#1 := 0; 67#L532true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135#L533true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 632#L1281true assume !(0 != activate_threads_~tmp___0~0#1); 58#L1281-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 852#L540true assume 1 == ~t2_pc~0; 1103#L541true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 856#L551true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 872#L552true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1229#L1289true assume !(0 != activate_threads_~tmp___1~0#1); 944#L1289-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 199#L559true assume 1 == ~t3_pc~0; 1014#L560true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 365#L570true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 471#L571true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 643#L1297true assume !(0 != activate_threads_~tmp___2~0#1); 107#L1297-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1252#L578true assume !(1 == ~t4_pc~0); 799#L578-2true is_transmit4_triggered_~__retres1~4#1 := 0; 832#L589true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55#L590true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1089#L1305true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 598#L1305-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1161#L597true assume 1 == ~t5_pc~0; 1330#L598true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77#L608true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 426#L609true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1350#L1313true assume !(0 != activate_threads_~tmp___4~0#1); 550#L1313-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 612#L616true assume !(1 == ~t6_pc~0); 1174#L616-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1063#L627true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1255#L628true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 492#L1321true assume !(0 != activate_threads_~tmp___5~0#1); 445#L1321-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 676#L635true assume 1 == ~t7_pc~0; 601#L636true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 257#L646true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 806#L647true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 902#L1329true assume !(0 != activate_threads_~tmp___6~0#1); 545#L1329-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 786#L654true assume !(1 == ~t8_pc~0); 410#L654-2true is_transmit8_triggered_~__retres1~8#1 := 0; 945#L665true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1209#L666true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 788#L1337true assume !(0 != activate_threads_~tmp___7~0#1); 992#L1337-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 184#L673true assume 1 == ~t9_pc~0; 1008#L674true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1202#L684true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1111#L685true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 744#L1345true assume !(0 != activate_threads_~tmp___8~0#1); 692#L1345-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 864#L692true assume !(1 == ~t10_pc~0); 679#L692-2true is_transmit10_triggered_~__retres1~10#1 := 0; 998#L703true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 552#L704true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 455#L1353true assume !(0 != activate_threads_~tmp___9~0#1); 767#L1353-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1309#L1142true assume !(1 == ~M_E~0); 138#L1142-2true assume !(1 == ~T1_E~0); 745#L1147-1true assume !(1 == ~T2_E~0); 1308#L1152-1true assume !(1 == ~T3_E~0); 370#L1157-1true assume !(1 == ~T4_E~0); 844#L1162-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 474#L1167-1true assume !(1 == ~T6_E~0); 928#L1172-1true assume !(1 == ~T7_E~0); 961#L1177-1true assume !(1 == ~T8_E~0); 583#L1182-1true assume !(1 == ~T9_E~0); 686#L1187-1true assume !(1 == ~T10_E~0); 734#L1192-1true assume !(1 == ~E_M~0); 287#L1197-1true assume !(1 == ~E_1~0); 749#L1202-1true assume 1 == ~E_2~0;~E_2~0 := 2; 534#L1207-1true assume !(1 == ~E_3~0); 520#L1212-1true assume !(1 == ~E_4~0); 70#L1217-1true assume !(1 == ~E_5~0); 1368#L1222-1true assume !(1 == ~E_6~0); 516#L1227-1true assume !(1 == ~E_7~0); 579#L1232-1true assume !(1 == ~E_8~0); 8#L1237-1true assume !(1 == ~E_9~0); 1055#L1242-1true assume 1 == ~E_10~0;~E_10~0 := 2; 567#L1247-1true assume { :end_inline_reset_delta_events } true; 89#L1553-2true [2022-07-22 02:42:30,489 INFO L754 eck$LassoCheckResult]: Loop: 89#L1553-2true assume !false; 731#L1554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1335#L999true assume false; 807#L1014true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 233#L712-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1288#L1024-3true assume 0 == ~M_E~0;~M_E~0 := 1; 996#L1024-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 443#L1029-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 419#L1034-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 710#L1039-3true assume !(0 == ~T4_E~0); 764#L1044-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 181#L1049-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 642#L1054-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 68#L1059-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1334#L1064-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 400#L1069-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 688#L1074-3true assume 0 == ~E_M~0;~E_M~0 := 1; 974#L1079-3true assume !(0 == ~E_1~0); 575#L1084-3true assume 0 == ~E_2~0;~E_2~0 := 1; 485#L1089-3true assume 0 == ~E_3~0;~E_3~0 := 1; 640#L1094-3true assume 0 == ~E_4~0;~E_4~0 := 1; 433#L1099-3true assume 0 == ~E_5~0;~E_5~0 := 1; 708#L1104-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1061#L1109-3true assume 0 == ~E_7~0;~E_7~0 := 1; 695#L1114-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1189#L1119-3true assume !(0 == ~E_9~0); 1327#L1124-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1226#L1129-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1095#L502-36true assume !(1 == ~m_pc~0); 266#L502-38true is_master_triggered_~__retres1~0#1 := 0; 2#L513-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1220#L514-12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 213#L1273-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 682#L1273-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 380#L521-36true assume !(1 == ~t1_pc~0); 1075#L521-38true is_transmit1_triggered_~__retres1~1#1 := 0; 510#L532-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 540#L533-12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1195#L1281-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 798#L1281-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1106#L540-36true assume 1 == ~t2_pc~0; 1257#L541-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 258#L551-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1247#L552-12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1336#L1289-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 470#L1289-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7#L559-36true assume 1 == ~t3_pc~0; 701#L560-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 733#L570-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152#L571-12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 585#L1297-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 870#L1297-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1239#L578-36true assume !(1 == ~t4_pc~0); 525#L578-38true is_transmit4_triggered_~__retres1~4#1 := 0; 1244#L589-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 913#L590-12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1307#L1305-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 403#L1305-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 574#L597-36true assume !(1 == ~t5_pc~0); 1119#L597-38true is_transmit5_triggered_~__retres1~5#1 := 0; 1053#L608-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 509#L609-12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 535#L1313-36true assume !(0 != activate_threads_~tmp___4~0#1); 288#L1313-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1108#L616-36true assume !(1 == ~t6_pc~0); 988#L616-38true is_transmit6_triggered_~__retres1~6#1 := 0; 37#L627-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 368#L628-12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 439#L1321-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 729#L1321-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1347#L635-36true assume !(1 == ~t7_pc~0); 1233#L635-38true is_transmit7_triggered_~__retres1~7#1 := 0; 813#L646-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 475#L647-12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1267#L1329-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 431#L1329-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1281#L654-36true assume 1 == ~t8_pc~0; 1205#L655-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1329#L665-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1279#L666-12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1173#L1337-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1124#L1337-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 229#L673-36true assume 1 == ~t9_pc~0; 841#L674-12true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 460#L684-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 821#L685-12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1022#L1345-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11#L1345-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1185#L692-36true assume !(1 == ~t10_pc~0); 111#L692-38true is_transmit10_triggered_~__retres1~10#1 := 0; 438#L703-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 886#L704-12true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 209#L1353-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 437#L1353-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 551#L1142-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1169#L1142-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1005#L1147-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1067#L1152-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 496#L1157-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 808#L1162-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1065#L1167-3true assume !(1 == ~T6_E~0); 984#L1172-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 429#L1177-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 363#L1182-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 843#L1187-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 372#L1192-3true assume 1 == ~E_M~0;~E_M~0 := 2; 264#L1197-3true assume 1 == ~E_1~0;~E_1~0 := 2; 417#L1202-3true assume 1 == ~E_2~0;~E_2~0 := 2; 502#L1207-3true assume !(1 == ~E_3~0); 1104#L1212-3true assume 1 == ~E_4~0;~E_4~0 := 2; 706#L1217-3true assume 1 == ~E_5~0;~E_5~0 := 2; 204#L1222-3true assume 1 == ~E_6~0;~E_6~0 := 2; 49#L1227-3true assume 1 == ~E_7~0;~E_7~0 := 2; 875#L1232-3true assume 1 == ~E_8~0;~E_8~0 := 2; 847#L1237-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1292#L1242-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1250#L1247-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 918#L782-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 119#L839-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1227#L840-1true start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 560#L1572true assume !(0 == start_simulation_~tmp~3#1); 382#L1572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1217#L782-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1080#L839-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1084#L840-2true stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1284#L1527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4#L1534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 818#L1535true start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1357#L1585true assume !(0 != start_simulation_~tmp___0~1#1); 89#L1553-2true [2022-07-22 02:42:30,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:30,496 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2022-07-22 02:42:30,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:30,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076237986] [2022-07-22 02:42:30,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:30,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:30,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:30,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:30,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:30,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076237986] [2022-07-22 02:42:30,729 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076237986] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:30,729 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:30,730 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:30,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428581447] [2022-07-22 02:42:30,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:30,736 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:30,737 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:30,737 INFO L85 PathProgramCache]: Analyzing trace with hash -809833669, now seen corresponding path program 1 times [2022-07-22 02:42:30,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:30,738 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882273521] [2022-07-22 02:42:30,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:30,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:30,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:30,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:30,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:30,787 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882273521] [2022-07-22 02:42:30,787 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1882273521] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:30,787 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:30,787 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:42:30,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529481051] [2022-07-22 02:42:30,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:30,789 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:30,790 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:30,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:30,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:30,822 INFO L87 Difference]: Start difference. First operand has 1367 states, 1366 states have (on average 1.5058565153733527) internal successors, (2057), 1366 states have internal predecessors, (2057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:30,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:30,891 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2022-07-22 02:42:30,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:30,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2028 transitions. [2022-07-22 02:42:30,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:30,935 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1361 states and 2023 transitions. [2022-07-22 02:42:30,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-07-22 02:42:30,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-07-22 02:42:30,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2023 transitions. [2022-07-22 02:42:30,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:30,945 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2022-07-22 02:42:30,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2023 transitions. [2022-07-22 02:42:31,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-07-22 02:42:31,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4864070536370315) internal successors, (2023), 1360 states have internal predecessors, (2023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:31,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2023 transitions. [2022-07-22 02:42:31,019 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2022-07-22 02:42:31,020 INFO L374 stractBuchiCegarLoop]: Abstraction has 1361 states and 2023 transitions. [2022-07-22 02:42:31,020 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-22 02:42:31,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2023 transitions. [2022-07-22 02:42:31,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:31,040 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:31,040 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:31,044 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,044 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,045 INFO L752 eck$LassoCheckResult]: Stem: 3750#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3751#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2791#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2792#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3680#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3384#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3385#L724-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3662#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3818#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3550#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3551#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3440#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3441#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3778#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3740#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3668#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3669#L1024 assume !(0 == ~M_E~0); 3914#L1024-2 assume !(0 == ~T1_E~0); 3118#L1029-1 assume !(0 == ~T2_E~0); 3119#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3225#L1039-1 assume !(0 == ~T4_E~0); 4031#L1044-1 assume !(0 == ~T5_E~0); 3462#L1049-1 assume !(0 == ~T6_E~0); 3463#L1054-1 assume !(0 == ~T7_E~0); 3688#L1059-1 assume !(0 == ~T8_E~0); 3165#L1064-1 assume !(0 == ~T9_E~0); 3166#L1069-1 assume !(0 == ~T10_E~0); 3882#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3948#L1079-1 assume !(0 == ~E_1~0); 3916#L1084-1 assume !(0 == ~E_2~0); 3917#L1089-1 assume !(0 == ~E_3~0); 3967#L1094-1 assume !(0 == ~E_4~0); 3538#L1099-1 assume !(0 == ~E_5~0); 3539#L1104-1 assume !(0 == ~E_6~0); 3796#L1109-1 assume !(0 == ~E_7~0); 3339#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3340#L1119-1 assume !(0 == ~E_9~0); 3396#L1124-1 assume !(0 == ~E_10~0); 2824#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2825#L502 assume 1 == ~m_pc~0; 3686#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2953#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2954#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3736#L1273 assume !(0 != activate_threads_~tmp~1#1); 3737#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4066#L521 assume !(1 == ~t1_pc~0); 3999#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2884#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2885#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3028#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2868#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2869#L540 assume 1 == ~t2_pc~0; 3930#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3651#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3933#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3946#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3993#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3140#L559 assume 1 == ~t3_pc~0; 3141#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3420#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3421#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3563#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2971#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2972#L578 assume !(1 == ~t4_pc~0); 3092#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3091#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2860#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2861#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3720#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3721#L597 assume 1 == ~t5_pc~0; 4083#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2905#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2906#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3511#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3670#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3671#L616 assume !(1 == ~t6_pc~0); 3685#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3684#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4048#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3593#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3530#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3531#L635 assume 1 == ~t7_pc~0; 3725#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2874#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3245#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3891#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3663#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3664#L654 assume !(1 == ~t8_pc~0); 3486#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3487#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3994#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3879#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3880#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3116#L673 assume 1 == ~t9_pc~0; 3117#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2815#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4063#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3849#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3805#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3806#L692 assume !(1 == ~t10_pc~0); 3754#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3753#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3672#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3542#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3543#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3860#L1142 assume !(1 == ~M_E~0); 3031#L1142-2 assume !(1 == ~T1_E~0); 3032#L1147-1 assume !(1 == ~T2_E~0); 3850#L1152-1 assume !(1 == ~T3_E~0); 3426#L1157-1 assume !(1 == ~T4_E~0); 3427#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3567#L1167-1 assume !(1 == ~T6_E~0); 3568#L1172-1 assume !(1 == ~T7_E~0); 3987#L1177-1 assume !(1 == ~T8_E~0); 3705#L1182-1 assume !(1 == ~T9_E~0); 3706#L1187-1 assume !(1 == ~T10_E~0); 3799#L1192-1 assume !(1 == ~E_M~0); 3292#L1197-1 assume !(1 == ~E_1~0); 3293#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3654#L1207-1 assume !(1 == ~E_3~0); 3633#L1212-1 assume !(1 == ~E_4~0); 2890#L1217-1 assume !(1 == ~E_5~0); 2891#L1222-1 assume !(1 == ~E_6~0); 3629#L1227-1 assume !(1 == ~E_7~0); 3630#L1232-1 assume !(1 == ~E_8~0); 2756#L1237-1 assume !(1 == ~E_9~0); 2757#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3687#L1247-1 assume { :end_inline_reset_delta_events } true; 2930#L1553-2 [2022-07-22 02:42:31,045 INFO L754 eck$LassoCheckResult]: Loop: 2930#L1553-2 assume !false; 2931#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3840#L999 assume !false; 3888#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3015#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2908#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3403#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3757#L854 assume !(0 != eval_~tmp~0#1); 3758#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3202#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3203#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4020#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3529#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3499#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3500#L1039-3 assume !(0 == ~T4_E~0); 3823#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3110#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3111#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2886#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2887#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3471#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3472#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3801#L1079-3 assume !(0 == ~E_1~0); 3699#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3586#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3587#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3516#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3517#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3821#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3809#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3810#L1119-3 assume !(0 == ~E_9~0); 4090#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4097#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4057#L502-36 assume 1 == ~m_pc~0; 3824#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2742#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2743#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3167#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3168#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3445#L521-36 assume 1 == ~t1_pc~0; 3446#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3455#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3622#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3659#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3884#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3885#L540-36 assume !(1 == ~t2_pc~0); 2833#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2834#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3246#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4098#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3561#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2750#L559-36 assume !(1 == ~t3_pc~0); 2752#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3204#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3060#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3061#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3707#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3943#L578-36 assume !(1 == ~t4_pc~0); 3636#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3637#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3973#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3974#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3475#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3476#L597-36 assume !(1 == ~t5_pc~0); 3696#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4046#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3620#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3621#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 3290#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3291#L616-36 assume !(1 == ~t6_pc~0); 4018#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2820#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2821#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3423#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3524#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3839#L635-36 assume 1 == ~t7_pc~0; 4023#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3896#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3569#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3570#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3512#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3513#L654-36 assume !(1 == ~t8_pc~0); 4027#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4028#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4100#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4085#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4067#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3195#L673-36 assume !(1 == ~t9_pc~0); 3196#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3548#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3549#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3903#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2763#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2764#L692-36 assume 1 == ~t10_pc~0; 3698#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2980#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3523#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3158#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3159#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3522#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3667#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4029#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4030#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3600#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3601#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3892#L1167-3 assume !(1 == ~T6_E~0); 4014#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3510#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3415#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3416#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3429#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3254#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3255#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3496#L1207-3 assume !(1 == ~E_3~0); 3611#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3819#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3149#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2847#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2848#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3923#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3924#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4099#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3977#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2999#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3000#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3679#L1572 assume !(0 == start_simulation_~tmp~3#1); 3295#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3448#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2777#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4051#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 4052#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2746#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2747#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3901#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2930#L1553-2 [2022-07-22 02:42:31,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,056 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2022-07-22 02:42:31,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553856914] [2022-07-22 02:42:31,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:31,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:31,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:31,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553856914] [2022-07-22 02:42:31,140 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1553856914] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:31,140 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:31,140 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:31,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701433407] [2022-07-22 02:42:31,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:31,141 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:31,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,142 INFO L85 PathProgramCache]: Analyzing trace with hash -2058537928, now seen corresponding path program 1 times [2022-07-22 02:42:31,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438150103] [2022-07-22 02:42:31,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:31,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:31,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:31,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438150103] [2022-07-22 02:42:31,229 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438150103] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:31,229 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:31,230 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:31,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81401160] [2022-07-22 02:42:31,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:31,231 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:31,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:31,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:31,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:31,232 INFO L87 Difference]: Start difference. First operand 1361 states and 2023 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:31,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:31,255 INFO L93 Difference]: Finished difference Result 1361 states and 2022 transitions. [2022-07-22 02:42:31,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:31,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2022 transitions. [2022-07-22 02:42:31,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:31,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2022 transitions. [2022-07-22 02:42:31,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-07-22 02:42:31,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-07-22 02:42:31,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2022 transitions. [2022-07-22 02:42:31,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:31,275 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2022-07-22 02:42:31,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2022 transitions. [2022-07-22 02:42:31,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-07-22 02:42:31,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.485672299779574) internal successors, (2022), 1360 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:31,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2022 transitions. [2022-07-22 02:42:31,320 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2022-07-22 02:42:31,320 INFO L374 stractBuchiCegarLoop]: Abstraction has 1361 states and 2022 transitions. [2022-07-22 02:42:31,320 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-22 02:42:31,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2022 transitions. [2022-07-22 02:42:31,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:31,327 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:31,327 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:31,329 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,329 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,330 INFO L752 eck$LassoCheckResult]: Stem: 6479#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 6480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5520#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5521#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6409#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 6112#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6113#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6391#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6547#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6277#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6278#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6167#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6168#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6507#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6469#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6396#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6397#L1024 assume !(0 == ~M_E~0); 6643#L1024-2 assume !(0 == ~T1_E~0); 5847#L1029-1 assume !(0 == ~T2_E~0); 5848#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5954#L1039-1 assume !(0 == ~T4_E~0); 6760#L1044-1 assume !(0 == ~T5_E~0); 6189#L1049-1 assume !(0 == ~T6_E~0); 6190#L1054-1 assume !(0 == ~T7_E~0); 6417#L1059-1 assume !(0 == ~T8_E~0); 5894#L1064-1 assume !(0 == ~T9_E~0); 5895#L1069-1 assume !(0 == ~T10_E~0); 6611#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6677#L1079-1 assume !(0 == ~E_1~0); 6645#L1084-1 assume !(0 == ~E_2~0); 6646#L1089-1 assume !(0 == ~E_3~0); 6696#L1094-1 assume !(0 == ~E_4~0); 6267#L1099-1 assume !(0 == ~E_5~0); 6268#L1104-1 assume !(0 == ~E_6~0); 6525#L1109-1 assume !(0 == ~E_7~0); 6068#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6069#L1119-1 assume !(0 == ~E_9~0); 6123#L1124-1 assume !(0 == ~E_10~0); 5553#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5554#L502 assume 1 == ~m_pc~0; 6415#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5682#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5683#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6464#L1273 assume !(0 != activate_threads_~tmp~1#1); 6465#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6795#L521 assume !(1 == ~t1_pc~0); 6728#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5613#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5614#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5756#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 5595#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5596#L540 assume 1 == ~t2_pc~0; 6659#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6380#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6662#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6675#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 6722#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5869#L559 assume 1 == ~t3_pc~0; 5870#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6148#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6149#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6292#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 5700#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5701#L578 assume !(1 == ~t4_pc~0); 5819#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5818#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5589#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5590#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6447#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6448#L597 assume 1 == ~t5_pc~0; 6810#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5634#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5635#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6235#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 6398#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6399#L616 assume !(1 == ~t6_pc~0); 6413#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6412#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6777#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6322#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 6259#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6260#L635 assume 1 == ~t7_pc~0; 6452#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5603#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5974#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6620#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 6392#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6393#L654 assume !(1 == ~t8_pc~0); 6215#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6216#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6723#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6608#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 6609#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5845#L673 assume 1 == ~t9_pc~0; 5846#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5544#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6792#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6578#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 6534#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6535#L692 assume !(1 == ~t10_pc~0); 6483#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6482#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6401#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6271#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 6272#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6589#L1142 assume !(1 == ~M_E~0); 5760#L1142-2 assume !(1 == ~T1_E~0); 5761#L1147-1 assume !(1 == ~T2_E~0); 6579#L1152-1 assume !(1 == ~T3_E~0); 6155#L1157-1 assume !(1 == ~T4_E~0); 6156#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6296#L1167-1 assume !(1 == ~T6_E~0); 6297#L1172-1 assume !(1 == ~T7_E~0); 6716#L1177-1 assume !(1 == ~T8_E~0); 6434#L1182-1 assume !(1 == ~T9_E~0); 6435#L1187-1 assume !(1 == ~T10_E~0); 6528#L1192-1 assume !(1 == ~E_M~0); 6019#L1197-1 assume !(1 == ~E_1~0); 6020#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6383#L1207-1 assume !(1 == ~E_3~0); 6362#L1212-1 assume !(1 == ~E_4~0); 5619#L1217-1 assume !(1 == ~E_5~0); 5620#L1222-1 assume !(1 == ~E_6~0); 6358#L1227-1 assume !(1 == ~E_7~0); 6359#L1232-1 assume !(1 == ~E_8~0); 5485#L1237-1 assume !(1 == ~E_9~0); 5486#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 6416#L1247-1 assume { :end_inline_reset_delta_events } true; 5659#L1553-2 [2022-07-22 02:42:31,330 INFO L754 eck$LassoCheckResult]: Loop: 5659#L1553-2 assume !false; 5660#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6569#L999 assume !false; 6615#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5744#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5637#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6132#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6486#L854 assume !(0 != eval_~tmp~0#1); 6487#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5931#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5932#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6749#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6258#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6228#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6229#L1039-3 assume !(0 == ~T4_E~0); 6552#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5839#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5840#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5615#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5616#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6200#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6201#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6530#L1079-3 assume !(0 == ~E_1~0); 6427#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6315#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6316#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6245#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6246#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6550#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6538#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6539#L1119-3 assume !(0 == ~E_9~0); 6819#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6826#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6786#L502-36 assume !(1 == ~m_pc~0); 5986#L502-38 is_master_triggered_~__retres1~0#1 := 0; 5471#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5472#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5896#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5897#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6172#L521-36 assume 1 == ~t1_pc~0; 6173#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6184#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6351#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6388#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6613#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6614#L540-36 assume 1 == ~t2_pc~0; 6788#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5561#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5975#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6827#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6291#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5482#L559-36 assume 1 == ~t3_pc~0; 5483#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5939#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5789#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5790#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6436#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6672#L578-36 assume !(1 == ~t4_pc~0); 6368#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 6369#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6702#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6703#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6206#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6207#L597-36 assume !(1 == ~t5_pc~0); 6425#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 6775#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6349#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6350#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 6021#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6022#L616-36 assume 1 == ~t6_pc~0; 6789#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5549#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5550#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6152#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6253#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6568#L635-36 assume 1 == ~t7_pc~0; 6752#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6625#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6298#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6299#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6241#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6242#L654-36 assume !(1 == ~t8_pc~0); 6756#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6757#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6829#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6814#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6796#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5924#L673-36 assume !(1 == ~t9_pc~0); 5925#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 6279#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6280#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6632#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5492#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5493#L692-36 assume 1 == ~t10_pc~0; 6428#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5709#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6252#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5887#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5888#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6251#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6400#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6758#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6759#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6329#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6330#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6621#L1167-3 assume !(1 == ~T6_E~0); 6743#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6240#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6144#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6145#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6158#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5983#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5984#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6225#L1207-3 assume !(1 == ~E_3~0); 6340#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6548#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5879#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5576#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5577#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6653#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6654#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6828#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6706#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5728#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5729#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6408#L1572 assume !(0 == start_simulation_~tmp~3#1); 6026#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6177#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5506#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6780#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 6781#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5475#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5476#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6630#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 5659#L1553-2 [2022-07-22 02:42:31,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,331 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2022-07-22 02:42:31,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,332 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478024622] [2022-07-22 02:42:31,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:31,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:31,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:31,385 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1478024622] [2022-07-22 02:42:31,385 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1478024622] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:31,386 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:31,386 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:31,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047070330] [2022-07-22 02:42:31,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:31,387 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:31,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,387 INFO L85 PathProgramCache]: Analyzing trace with hash -679343498, now seen corresponding path program 1 times [2022-07-22 02:42:31,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627379949] [2022-07-22 02:42:31,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:31,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:31,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:31,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627379949] [2022-07-22 02:42:31,500 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627379949] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:31,500 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:31,500 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:31,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288184678] [2022-07-22 02:42:31,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:31,502 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:31,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:31,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:31,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:31,503 INFO L87 Difference]: Start difference. First operand 1361 states and 2022 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:31,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:31,527 INFO L93 Difference]: Finished difference Result 1361 states and 2021 transitions. [2022-07-22 02:42:31,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:31,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2021 transitions. [2022-07-22 02:42:31,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:31,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2021 transitions. [2022-07-22 02:42:31,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-07-22 02:42:31,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-07-22 02:42:31,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2021 transitions. [2022-07-22 02:42:31,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:31,578 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2022-07-22 02:42:31,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2021 transitions. [2022-07-22 02:42:31,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-07-22 02:42:31,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4849375459221161) internal successors, (2021), 1360 states have internal predecessors, (2021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:31,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2021 transitions. [2022-07-22 02:42:31,601 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2022-07-22 02:42:31,601 INFO L374 stractBuchiCegarLoop]: Abstraction has 1361 states and 2021 transitions. [2022-07-22 02:42:31,602 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-22 02:42:31,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2021 transitions. [2022-07-22 02:42:31,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:31,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:31,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:31,611 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,611 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,612 INFO L752 eck$LassoCheckResult]: Stem: 9208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 9209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8249#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8250#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9138#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 8841#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8842#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9120#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9276#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9006#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9007#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8896#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8897#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9236#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9198#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9125#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9126#L1024 assume !(0 == ~M_E~0); 9372#L1024-2 assume !(0 == ~T1_E~0); 8576#L1029-1 assume !(0 == ~T2_E~0); 8577#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8683#L1039-1 assume !(0 == ~T4_E~0); 9489#L1044-1 assume !(0 == ~T5_E~0); 8918#L1049-1 assume !(0 == ~T6_E~0); 8919#L1054-1 assume !(0 == ~T7_E~0); 9146#L1059-1 assume !(0 == ~T8_E~0); 8623#L1064-1 assume !(0 == ~T9_E~0); 8624#L1069-1 assume !(0 == ~T10_E~0); 9340#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 9406#L1079-1 assume !(0 == ~E_1~0); 9374#L1084-1 assume !(0 == ~E_2~0); 9375#L1089-1 assume !(0 == ~E_3~0); 9425#L1094-1 assume !(0 == ~E_4~0); 8996#L1099-1 assume !(0 == ~E_5~0); 8997#L1104-1 assume !(0 == ~E_6~0); 9254#L1109-1 assume !(0 == ~E_7~0); 8797#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8798#L1119-1 assume !(0 == ~E_9~0); 8852#L1124-1 assume !(0 == ~E_10~0); 8282#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8283#L502 assume 1 == ~m_pc~0; 9144#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8411#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8412#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9193#L1273 assume !(0 != activate_threads_~tmp~1#1); 9194#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9524#L521 assume !(1 == ~t1_pc~0); 9457#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8342#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8343#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8485#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 8324#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8325#L540 assume 1 == ~t2_pc~0; 9388#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9109#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9391#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9404#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 9451#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8598#L559 assume 1 == ~t3_pc~0; 8599#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8877#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8878#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9021#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 8429#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8430#L578 assume !(1 == ~t4_pc~0); 8550#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8549#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8318#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8319#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9178#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9179#L597 assume 1 == ~t5_pc~0; 9539#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8363#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8364#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8964#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 9127#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9128#L616 assume !(1 == ~t6_pc~0); 9142#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9141#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9506#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9051#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 8988#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8989#L635 assume 1 == ~t7_pc~0; 9181#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8332#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8703#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9349#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 9121#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9122#L654 assume !(1 == ~t8_pc~0); 8944#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8945#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9452#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9337#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 9338#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8574#L673 assume 1 == ~t9_pc~0; 8575#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8273#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9521#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9307#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 9263#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9264#L692 assume !(1 == ~t10_pc~0); 9212#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9211#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9130#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9000#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 9001#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9318#L1142 assume !(1 == ~M_E~0); 8489#L1142-2 assume !(1 == ~T1_E~0); 8490#L1147-1 assume !(1 == ~T2_E~0); 9308#L1152-1 assume !(1 == ~T3_E~0); 8884#L1157-1 assume !(1 == ~T4_E~0); 8885#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9025#L1167-1 assume !(1 == ~T6_E~0); 9026#L1172-1 assume !(1 == ~T7_E~0); 9445#L1177-1 assume !(1 == ~T8_E~0); 9163#L1182-1 assume !(1 == ~T9_E~0); 9164#L1187-1 assume !(1 == ~T10_E~0); 9257#L1192-1 assume !(1 == ~E_M~0); 8748#L1197-1 assume !(1 == ~E_1~0); 8749#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9112#L1207-1 assume !(1 == ~E_3~0); 9091#L1212-1 assume !(1 == ~E_4~0); 8348#L1217-1 assume !(1 == ~E_5~0); 8349#L1222-1 assume !(1 == ~E_6~0); 9087#L1227-1 assume !(1 == ~E_7~0); 9088#L1232-1 assume !(1 == ~E_8~0); 8214#L1237-1 assume !(1 == ~E_9~0); 8215#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9145#L1247-1 assume { :end_inline_reset_delta_events } true; 8388#L1553-2 [2022-07-22 02:42:31,612 INFO L754 eck$LassoCheckResult]: Loop: 8388#L1553-2 assume !false; 8389#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9298#L999 assume !false; 9344#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8473#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8366#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8861#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9215#L854 assume !(0 != eval_~tmp~0#1); 9216#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8660#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8661#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9478#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8987#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8957#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8958#L1039-3 assume !(0 == ~T4_E~0); 9281#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8568#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8569#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8344#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8345#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8929#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8930#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9259#L1079-3 assume !(0 == ~E_1~0); 9156#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9044#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9045#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8974#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8975#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9279#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9267#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9268#L1119-3 assume !(0 == ~E_9~0); 9548#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9555#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9515#L502-36 assume 1 == ~m_pc~0; 9282#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8200#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8201#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8625#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8626#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8901#L521-36 assume 1 == ~t1_pc~0; 8902#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8913#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9080#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9117#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9342#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9343#L540-36 assume !(1 == ~t2_pc~0); 8289#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 8290#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8704#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9556#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9020#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8211#L559-36 assume 1 == ~t3_pc~0; 8212#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8668#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8518#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8519#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9165#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9401#L578-36 assume 1 == ~t4_pc~0; 9136#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9098#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9431#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9432#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8935#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8936#L597-36 assume !(1 == ~t5_pc~0); 9154#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9504#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9078#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9079#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 8750#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8751#L616-36 assume !(1 == ~t6_pc~0); 9476#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 8278#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8279#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8881#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8982#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9297#L635-36 assume 1 == ~t7_pc~0; 9481#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9354#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9027#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9028#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8970#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8971#L654-36 assume !(1 == ~t8_pc~0); 9485#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9486#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9558#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9543#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9525#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8653#L673-36 assume !(1 == ~t9_pc~0); 8654#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 9008#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9009#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9361#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8221#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8222#L692-36 assume 1 == ~t10_pc~0; 9157#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8438#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8981#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8616#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8617#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8980#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9129#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9487#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9488#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9058#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9059#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9350#L1167-3 assume !(1 == ~T6_E~0); 9472#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8969#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8873#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8874#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8887#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8712#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8713#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8954#L1207-3 assume !(1 == ~E_3~0); 9069#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9277#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8608#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8305#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8306#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9382#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9383#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9557#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9435#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8457#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8458#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 9137#L1572 assume !(0 == start_simulation_~tmp~3#1); 8753#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8906#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8235#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9509#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 9510#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8204#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8205#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9359#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 8388#L1553-2 [2022-07-22 02:42:31,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,614 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2022-07-22 02:42:31,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15433420] [2022-07-22 02:42:31,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:31,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:31,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:31,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15433420] [2022-07-22 02:42:31,664 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15433420] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:31,664 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:31,665 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:31,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [542951337] [2022-07-22 02:42:31,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:31,665 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:31,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,666 INFO L85 PathProgramCache]: Analyzing trace with hash 1183923574, now seen corresponding path program 1 times [2022-07-22 02:42:31,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009106103] [2022-07-22 02:42:31,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:31,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:31,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:31,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009106103] [2022-07-22 02:42:31,724 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1009106103] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:31,724 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:31,724 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:31,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29313019] [2022-07-22 02:42:31,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:31,725 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:31,725 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:31,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:31,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:31,726 INFO L87 Difference]: Start difference. First operand 1361 states and 2021 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:31,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:31,749 INFO L93 Difference]: Finished difference Result 1361 states and 2020 transitions. [2022-07-22 02:42:31,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:31,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2020 transitions. [2022-07-22 02:42:31,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:31,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2020 transitions. [2022-07-22 02:42:31,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-07-22 02:42:31,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-07-22 02:42:31,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2020 transitions. [2022-07-22 02:42:31,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:31,767 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2022-07-22 02:42:31,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2020 transitions. [2022-07-22 02:42:31,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-07-22 02:42:31,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4842027920646583) internal successors, (2020), 1360 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:31,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2020 transitions. [2022-07-22 02:42:31,786 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2022-07-22 02:42:31,786 INFO L374 stractBuchiCegarLoop]: Abstraction has 1361 states and 2020 transitions. [2022-07-22 02:42:31,786 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-22 02:42:31,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2020 transitions. [2022-07-22 02:42:31,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:31,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:31,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:31,794 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,794 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,795 INFO L752 eck$LassoCheckResult]: Stem: 11937#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11938#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 10978#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10979#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11867#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 11571#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11572#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11849#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12005#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11737#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11738#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11627#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11628#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11965#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11927#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11855#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11856#L1024 assume !(0 == ~M_E~0); 12101#L1024-2 assume !(0 == ~T1_E~0); 11305#L1029-1 assume !(0 == ~T2_E~0); 11306#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11412#L1039-1 assume !(0 == ~T4_E~0); 12218#L1044-1 assume !(0 == ~T5_E~0); 11649#L1049-1 assume !(0 == ~T6_E~0); 11650#L1054-1 assume !(0 == ~T7_E~0); 11875#L1059-1 assume !(0 == ~T8_E~0); 11352#L1064-1 assume !(0 == ~T9_E~0); 11353#L1069-1 assume !(0 == ~T10_E~0); 12069#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 12135#L1079-1 assume !(0 == ~E_1~0); 12103#L1084-1 assume !(0 == ~E_2~0); 12104#L1089-1 assume !(0 == ~E_3~0); 12154#L1094-1 assume !(0 == ~E_4~0); 11725#L1099-1 assume !(0 == ~E_5~0); 11726#L1104-1 assume !(0 == ~E_6~0); 11983#L1109-1 assume !(0 == ~E_7~0); 11526#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11527#L1119-1 assume !(0 == ~E_9~0); 11583#L1124-1 assume !(0 == ~E_10~0); 11011#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11012#L502 assume 1 == ~m_pc~0; 11873#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11140#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11141#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11923#L1273 assume !(0 != activate_threads_~tmp~1#1); 11924#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12253#L521 assume !(1 == ~t1_pc~0); 12186#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11071#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11072#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11215#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 11055#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11056#L540 assume 1 == ~t2_pc~0; 12117#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11838#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12120#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12133#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 12180#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11327#L559 assume 1 == ~t3_pc~0; 11328#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11607#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11608#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11750#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 11158#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11159#L578 assume !(1 == ~t4_pc~0); 11279#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11278#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11047#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11048#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11907#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11908#L597 assume 1 == ~t5_pc~0; 12270#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11092#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11093#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11698#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 11857#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11858#L616 assume !(1 == ~t6_pc~0); 11872#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11871#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12235#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11780#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 11717#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11718#L635 assume 1 == ~t7_pc~0; 11912#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11061#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11432#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12078#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 11850#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11851#L654 assume !(1 == ~t8_pc~0); 11673#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11674#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12181#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12066#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 12067#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11303#L673 assume 1 == ~t9_pc~0; 11304#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11002#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12250#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12036#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 11992#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11993#L692 assume !(1 == ~t10_pc~0); 11941#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11940#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11859#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11729#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 11730#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12047#L1142 assume !(1 == ~M_E~0); 11218#L1142-2 assume !(1 == ~T1_E~0); 11219#L1147-1 assume !(1 == ~T2_E~0); 12037#L1152-1 assume !(1 == ~T3_E~0); 11613#L1157-1 assume !(1 == ~T4_E~0); 11614#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11754#L1167-1 assume !(1 == ~T6_E~0); 11755#L1172-1 assume !(1 == ~T7_E~0); 12174#L1177-1 assume !(1 == ~T8_E~0); 11892#L1182-1 assume !(1 == ~T9_E~0); 11893#L1187-1 assume !(1 == ~T10_E~0); 11986#L1192-1 assume !(1 == ~E_M~0); 11479#L1197-1 assume !(1 == ~E_1~0); 11480#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11841#L1207-1 assume !(1 == ~E_3~0); 11820#L1212-1 assume !(1 == ~E_4~0); 11077#L1217-1 assume !(1 == ~E_5~0); 11078#L1222-1 assume !(1 == ~E_6~0); 11816#L1227-1 assume !(1 == ~E_7~0); 11817#L1232-1 assume !(1 == ~E_8~0); 10943#L1237-1 assume !(1 == ~E_9~0); 10944#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11874#L1247-1 assume { :end_inline_reset_delta_events } true; 11117#L1553-2 [2022-07-22 02:42:31,795 INFO L754 eck$LassoCheckResult]: Loop: 11117#L1553-2 assume !false; 11118#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12027#L999 assume !false; 12075#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11202#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11095#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11590#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11944#L854 assume !(0 != eval_~tmp~0#1); 11945#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11389#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11390#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12207#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11716#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11686#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11687#L1039-3 assume !(0 == ~T4_E~0); 12010#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11297#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11298#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11073#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11074#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11658#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11659#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11988#L1079-3 assume !(0 == ~E_1~0); 11886#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11773#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11774#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11703#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11704#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12008#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11996#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11997#L1119-3 assume !(0 == ~E_9~0); 12277#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12284#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12244#L502-36 assume !(1 == ~m_pc~0); 11444#L502-38 is_master_triggered_~__retres1~0#1 := 0; 10929#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10930#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11354#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11355#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11632#L521-36 assume 1 == ~t1_pc~0; 11633#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11642#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11809#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11846#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12071#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12072#L540-36 assume 1 == ~t2_pc~0; 12246#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11021#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11433#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12285#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11748#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10937#L559-36 assume 1 == ~t3_pc~0; 10938#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11391#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11247#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11248#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11894#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12130#L578-36 assume 1 == ~t4_pc~0; 11865#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11824#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12160#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12161#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11662#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11663#L597-36 assume !(1 == ~t5_pc~0); 11883#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 12233#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11807#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11808#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 11477#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11478#L616-36 assume 1 == ~t6_pc~0; 12247#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11007#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11008#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11610#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11711#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12026#L635-36 assume 1 == ~t7_pc~0; 12210#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12083#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11756#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11757#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11699#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11700#L654-36 assume !(1 == ~t8_pc~0); 12214#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12215#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12287#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12272#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12254#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11382#L673-36 assume !(1 == ~t9_pc~0); 11383#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 11735#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11736#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12090#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10950#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10951#L692-36 assume 1 == ~t10_pc~0; 11885#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11167#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11710#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11345#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11346#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11709#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11854#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12216#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12217#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11787#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11788#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12079#L1167-3 assume !(1 == ~T6_E~0); 12201#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11697#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11602#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11603#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11616#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11441#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11442#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11683#L1207-3 assume !(1 == ~E_3~0); 11798#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12006#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11336#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11034#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11035#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12110#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12111#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12286#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12164#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11186#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11187#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 11866#L1572 assume !(0 == start_simulation_~tmp~3#1); 11482#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11635#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10964#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12238#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 12239#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10933#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10934#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 12088#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 11117#L1553-2 [2022-07-22 02:42:31,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,796 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2022-07-22 02:42:31,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,796 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940064974] [2022-07-22 02:42:31,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:31,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:31,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:31,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [940064974] [2022-07-22 02:42:31,837 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [940064974] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:31,837 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:31,837 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:31,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [240799064] [2022-07-22 02:42:31,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:31,838 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:31,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,839 INFO L85 PathProgramCache]: Analyzing trace with hash 1162970293, now seen corresponding path program 1 times [2022-07-22 02:42:31,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957445814] [2022-07-22 02:42:31,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:31,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:31,877 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:31,878 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957445814] [2022-07-22 02:42:31,878 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1957445814] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:31,878 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:31,878 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:31,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707074728] [2022-07-22 02:42:31,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:31,879 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:31,879 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:31,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:31,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:31,880 INFO L87 Difference]: Start difference. First operand 1361 states and 2020 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:31,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:31,903 INFO L93 Difference]: Finished difference Result 1361 states and 2019 transitions. [2022-07-22 02:42:31,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:31,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2019 transitions. [2022-07-22 02:42:31,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:31,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2019 transitions. [2022-07-22 02:42:31,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-07-22 02:42:31,920 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-07-22 02:42:31,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2019 transitions. [2022-07-22 02:42:31,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:31,922 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2022-07-22 02:42:31,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2019 transitions. [2022-07-22 02:42:31,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-07-22 02:42:31,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4834680382072005) internal successors, (2019), 1360 states have internal predecessors, (2019), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:31,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2019 transitions. [2022-07-22 02:42:31,940 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2022-07-22 02:42:31,940 INFO L374 stractBuchiCegarLoop]: Abstraction has 1361 states and 2019 transitions. [2022-07-22 02:42:31,941 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-22 02:42:31,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2019 transitions. [2022-07-22 02:42:31,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:31,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:31,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:31,948 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,948 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:31,949 INFO L752 eck$LassoCheckResult]: Stem: 14666#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14667#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 13707#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13708#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14596#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 14299#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14300#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14578#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14734#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14464#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14465#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14354#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14355#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14694#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14656#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14583#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14584#L1024 assume !(0 == ~M_E~0); 14830#L1024-2 assume !(0 == ~T1_E~0); 14034#L1029-1 assume !(0 == ~T2_E~0); 14035#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14141#L1039-1 assume !(0 == ~T4_E~0); 14947#L1044-1 assume !(0 == ~T5_E~0); 14376#L1049-1 assume !(0 == ~T6_E~0); 14377#L1054-1 assume !(0 == ~T7_E~0); 14604#L1059-1 assume !(0 == ~T8_E~0); 14081#L1064-1 assume !(0 == ~T9_E~0); 14082#L1069-1 assume !(0 == ~T10_E~0); 14798#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14864#L1079-1 assume !(0 == ~E_1~0); 14832#L1084-1 assume !(0 == ~E_2~0); 14833#L1089-1 assume !(0 == ~E_3~0); 14883#L1094-1 assume !(0 == ~E_4~0); 14454#L1099-1 assume !(0 == ~E_5~0); 14455#L1104-1 assume !(0 == ~E_6~0); 14712#L1109-1 assume !(0 == ~E_7~0); 14255#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14256#L1119-1 assume !(0 == ~E_9~0); 14310#L1124-1 assume !(0 == ~E_10~0); 13740#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13741#L502 assume 1 == ~m_pc~0; 14602#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13869#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13870#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14651#L1273 assume !(0 != activate_threads_~tmp~1#1); 14652#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14982#L521 assume !(1 == ~t1_pc~0); 14915#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13800#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13801#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13943#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 13782#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13783#L540 assume 1 == ~t2_pc~0; 14846#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14567#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14849#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14862#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 14909#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14056#L559 assume 1 == ~t3_pc~0; 14057#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14335#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14336#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14479#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 13887#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13888#L578 assume !(1 == ~t4_pc~0); 14006#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14005#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13776#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13777#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14634#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14635#L597 assume 1 == ~t5_pc~0; 14997#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13821#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13822#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14422#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 14585#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14586#L616 assume !(1 == ~t6_pc~0); 14600#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14599#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14964#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14509#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 14446#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14447#L635 assume 1 == ~t7_pc~0; 14639#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13790#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14161#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14807#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 14579#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14580#L654 assume !(1 == ~t8_pc~0); 14402#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14403#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14910#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14795#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 14796#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14032#L673 assume 1 == ~t9_pc~0; 14033#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13731#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14979#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14765#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 14721#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14722#L692 assume !(1 == ~t10_pc~0); 14670#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14669#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14588#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14458#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 14459#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14776#L1142 assume !(1 == ~M_E~0); 13947#L1142-2 assume !(1 == ~T1_E~0); 13948#L1147-1 assume !(1 == ~T2_E~0); 14766#L1152-1 assume !(1 == ~T3_E~0); 14342#L1157-1 assume !(1 == ~T4_E~0); 14343#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14483#L1167-1 assume !(1 == ~T6_E~0); 14484#L1172-1 assume !(1 == ~T7_E~0); 14903#L1177-1 assume !(1 == ~T8_E~0); 14621#L1182-1 assume !(1 == ~T9_E~0); 14622#L1187-1 assume !(1 == ~T10_E~0); 14715#L1192-1 assume !(1 == ~E_M~0); 14206#L1197-1 assume !(1 == ~E_1~0); 14207#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14570#L1207-1 assume !(1 == ~E_3~0); 14549#L1212-1 assume !(1 == ~E_4~0); 13806#L1217-1 assume !(1 == ~E_5~0); 13807#L1222-1 assume !(1 == ~E_6~0); 14545#L1227-1 assume !(1 == ~E_7~0); 14546#L1232-1 assume !(1 == ~E_8~0); 13672#L1237-1 assume !(1 == ~E_9~0); 13673#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14603#L1247-1 assume { :end_inline_reset_delta_events } true; 13846#L1553-2 [2022-07-22 02:42:31,949 INFO L754 eck$LassoCheckResult]: Loop: 13846#L1553-2 assume !false; 13847#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14756#L999 assume !false; 14802#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13931#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13824#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14319#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14673#L854 assume !(0 != eval_~tmp~0#1); 14674#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14118#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14119#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14936#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14445#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14415#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14416#L1039-3 assume !(0 == ~T4_E~0); 14739#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14026#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14027#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13802#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13803#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14387#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14388#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14717#L1079-3 assume !(0 == ~E_1~0); 14614#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14502#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14503#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14432#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14433#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14737#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14725#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14726#L1119-3 assume !(0 == ~E_9~0); 15006#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15013#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14973#L502-36 assume 1 == ~m_pc~0; 14740#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13658#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13659#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14083#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14084#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14359#L521-36 assume 1 == ~t1_pc~0; 14360#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14371#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14538#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14575#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14800#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14801#L540-36 assume !(1 == ~t2_pc~0); 13747#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 13748#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14162#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15014#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14478#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13669#L559-36 assume 1 == ~t3_pc~0; 13670#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14126#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13976#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13977#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14623#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14859#L578-36 assume 1 == ~t4_pc~0; 14594#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14556#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14889#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14890#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14393#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14394#L597-36 assume !(1 == ~t5_pc~0); 14612#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 14962#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14536#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14537#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 14208#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14209#L616-36 assume 1 == ~t6_pc~0; 14976#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13736#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13737#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14339#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14440#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14755#L635-36 assume 1 == ~t7_pc~0; 14939#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14812#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14485#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14486#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14428#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14429#L654-36 assume 1 == ~t8_pc~0; 15009#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14944#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15016#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15001#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14983#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14111#L673-36 assume !(1 == ~t9_pc~0); 14112#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 14466#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14467#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14819#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13679#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13680#L692-36 assume 1 == ~t10_pc~0; 14615#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13896#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14439#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14074#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14075#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14438#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14587#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14945#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14946#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14516#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14517#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14808#L1167-3 assume !(1 == ~T6_E~0); 14930#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14427#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14331#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14332#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14345#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14170#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14171#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14412#L1207-3 assume !(1 == ~E_3~0); 14527#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14735#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14066#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13763#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13764#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14840#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14841#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15015#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14893#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13915#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13916#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14595#L1572 assume !(0 == start_simulation_~tmp~3#1); 14213#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14364#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13693#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14967#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 14968#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13662#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13663#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14817#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 13846#L1553-2 [2022-07-22 02:42:31,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2022-07-22 02:42:31,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476552581] [2022-07-22 02:42:31,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:31,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:31,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:31,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476552581] [2022-07-22 02:42:31,977 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476552581] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:31,977 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:31,977 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:31,978 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317369794] [2022-07-22 02:42:31,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:31,978 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:31,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:31,979 INFO L85 PathProgramCache]: Analyzing trace with hash 1080059252, now seen corresponding path program 1 times [2022-07-22 02:42:31,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:31,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958641477] [2022-07-22 02:42:31,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:31,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:31,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:32,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:32,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:32,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1958641477] [2022-07-22 02:42:32,023 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1958641477] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:32,023 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:32,023 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:32,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502373025] [2022-07-22 02:42:32,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:32,024 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:32,025 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:32,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:32,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:32,026 INFO L87 Difference]: Start difference. First operand 1361 states and 2019 transitions. cyclomatic complexity: 659 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:32,072 INFO L93 Difference]: Finished difference Result 1361 states and 2018 transitions. [2022-07-22 02:42:32,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:32,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2018 transitions. [2022-07-22 02:42:32,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:32,089 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2018 transitions. [2022-07-22 02:42:32,089 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-07-22 02:42:32,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-07-22 02:42:32,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2018 transitions. [2022-07-22 02:42:32,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:32,092 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2022-07-22 02:42:32,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2018 transitions. [2022-07-22 02:42:32,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-07-22 02:42:32,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.482733284349743) internal successors, (2018), 1360 states have internal predecessors, (2018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2018 transitions. [2022-07-22 02:42:32,118 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2022-07-22 02:42:32,118 INFO L374 stractBuchiCegarLoop]: Abstraction has 1361 states and 2018 transitions. [2022-07-22 02:42:32,118 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-22 02:42:32,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2018 transitions. [2022-07-22 02:42:32,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:32,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:32,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:32,129 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,129 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,130 INFO L752 eck$LassoCheckResult]: Stem: 17395#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 17396#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 16436#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16437#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17325#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 17028#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17029#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17307#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17463#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17193#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17194#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17083#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17084#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17423#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17385#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17312#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17313#L1024 assume !(0 == ~M_E~0); 17559#L1024-2 assume !(0 == ~T1_E~0); 16763#L1029-1 assume !(0 == ~T2_E~0); 16764#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16870#L1039-1 assume !(0 == ~T4_E~0); 17676#L1044-1 assume !(0 == ~T5_E~0); 17105#L1049-1 assume !(0 == ~T6_E~0); 17106#L1054-1 assume !(0 == ~T7_E~0); 17333#L1059-1 assume !(0 == ~T8_E~0); 16810#L1064-1 assume !(0 == ~T9_E~0); 16811#L1069-1 assume !(0 == ~T10_E~0); 17527#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17593#L1079-1 assume !(0 == ~E_1~0); 17561#L1084-1 assume !(0 == ~E_2~0); 17562#L1089-1 assume !(0 == ~E_3~0); 17612#L1094-1 assume !(0 == ~E_4~0); 17183#L1099-1 assume !(0 == ~E_5~0); 17184#L1104-1 assume !(0 == ~E_6~0); 17441#L1109-1 assume !(0 == ~E_7~0); 16984#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 16985#L1119-1 assume !(0 == ~E_9~0); 17039#L1124-1 assume !(0 == ~E_10~0); 16469#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16470#L502 assume 1 == ~m_pc~0; 17331#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16598#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16599#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17380#L1273 assume !(0 != activate_threads_~tmp~1#1); 17381#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17711#L521 assume !(1 == ~t1_pc~0); 17644#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16529#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16530#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16672#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 16511#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16512#L540 assume 1 == ~t2_pc~0; 17575#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17296#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17578#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17591#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 17638#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16785#L559 assume 1 == ~t3_pc~0; 16786#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17064#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17065#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17208#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 16616#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16617#L578 assume !(1 == ~t4_pc~0); 16735#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16734#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16505#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16506#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17363#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17364#L597 assume 1 == ~t5_pc~0; 17726#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16550#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16551#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17151#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 17314#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17315#L616 assume !(1 == ~t6_pc~0); 17329#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17328#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17693#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17238#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 17175#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17176#L635 assume 1 == ~t7_pc~0; 17368#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16519#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16890#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17536#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 17308#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17309#L654 assume !(1 == ~t8_pc~0); 17131#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17132#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17639#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17524#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 17525#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16761#L673 assume 1 == ~t9_pc~0; 16762#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16460#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17708#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17494#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 17450#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17451#L692 assume !(1 == ~t10_pc~0); 17399#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17398#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17317#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17187#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 17188#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17505#L1142 assume !(1 == ~M_E~0); 16676#L1142-2 assume !(1 == ~T1_E~0); 16677#L1147-1 assume !(1 == ~T2_E~0); 17495#L1152-1 assume !(1 == ~T3_E~0); 17071#L1157-1 assume !(1 == ~T4_E~0); 17072#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17212#L1167-1 assume !(1 == ~T6_E~0); 17213#L1172-1 assume !(1 == ~T7_E~0); 17632#L1177-1 assume !(1 == ~T8_E~0); 17350#L1182-1 assume !(1 == ~T9_E~0); 17351#L1187-1 assume !(1 == ~T10_E~0); 17444#L1192-1 assume !(1 == ~E_M~0); 16935#L1197-1 assume !(1 == ~E_1~0); 16936#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17299#L1207-1 assume !(1 == ~E_3~0); 17278#L1212-1 assume !(1 == ~E_4~0); 16535#L1217-1 assume !(1 == ~E_5~0); 16536#L1222-1 assume !(1 == ~E_6~0); 17274#L1227-1 assume !(1 == ~E_7~0); 17275#L1232-1 assume !(1 == ~E_8~0); 16401#L1237-1 assume !(1 == ~E_9~0); 16402#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 17332#L1247-1 assume { :end_inline_reset_delta_events } true; 16575#L1553-2 [2022-07-22 02:42:32,130 INFO L754 eck$LassoCheckResult]: Loop: 16575#L1553-2 assume !false; 16576#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17485#L999 assume !false; 17531#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16660#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16553#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17048#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17402#L854 assume !(0 != eval_~tmp~0#1); 17403#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16847#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16848#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17665#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17174#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17144#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17145#L1039-3 assume !(0 == ~T4_E~0); 17468#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16755#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16756#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16531#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16532#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17116#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17117#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17446#L1079-3 assume !(0 == ~E_1~0); 17343#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17231#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17232#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17161#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17162#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17466#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17454#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17455#L1119-3 assume !(0 == ~E_9~0); 17735#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17742#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17702#L502-36 assume !(1 == ~m_pc~0); 16902#L502-38 is_master_triggered_~__retres1~0#1 := 0; 16387#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16388#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16812#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16813#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17088#L521-36 assume 1 == ~t1_pc~0; 17089#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17100#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17267#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17304#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17529#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17530#L540-36 assume 1 == ~t2_pc~0; 17704#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16477#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16891#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17743#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17207#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16398#L559-36 assume !(1 == ~t3_pc~0); 16400#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 16855#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16705#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16706#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17352#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17588#L578-36 assume !(1 == ~t4_pc~0); 17284#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 17285#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17618#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17619#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17122#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17123#L597-36 assume !(1 == ~t5_pc~0); 17341#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 17691#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17265#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17266#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 16937#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16938#L616-36 assume 1 == ~t6_pc~0; 17705#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16465#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16466#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17068#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17169#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17484#L635-36 assume 1 == ~t7_pc~0; 17668#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17541#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17214#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17215#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17157#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17158#L654-36 assume !(1 == ~t8_pc~0); 17672#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 17673#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17745#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17730#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17712#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16840#L673-36 assume !(1 == ~t9_pc~0); 16841#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 17195#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17196#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17548#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16408#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16409#L692-36 assume 1 == ~t10_pc~0; 17344#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16625#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17168#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16803#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16804#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17167#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17316#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17674#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17675#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17245#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17246#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17537#L1167-3 assume !(1 == ~T6_E~0); 17659#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17156#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17060#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17061#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17074#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16899#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16900#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17141#L1207-3 assume !(1 == ~E_3~0); 17256#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17464#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16795#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16492#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16493#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17569#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17570#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17744#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17622#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16644#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16645#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17324#L1572 assume !(0 == start_simulation_~tmp~3#1); 16940#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17093#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16422#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17696#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 17697#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16391#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16392#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17546#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 16575#L1553-2 [2022-07-22 02:42:32,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:32,131 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2022-07-22 02:42:32,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:32,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123344669] [2022-07-22 02:42:32,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:32,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:32,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:32,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:32,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:32,162 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123344669] [2022-07-22 02:42:32,162 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123344669] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:32,162 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:32,162 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:32,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724743592] [2022-07-22 02:42:32,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:32,163 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:32,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:32,164 INFO L85 PathProgramCache]: Analyzing trace with hash -2079491209, now seen corresponding path program 1 times [2022-07-22 02:42:32,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:32,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127316154] [2022-07-22 02:42:32,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:32,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:32,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:32,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:32,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:32,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127316154] [2022-07-22 02:42:32,214 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127316154] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:32,214 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:32,214 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:32,214 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1294590393] [2022-07-22 02:42:32,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:32,215 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:32,215 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:32,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:32,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:32,216 INFO L87 Difference]: Start difference. First operand 1361 states and 2018 transitions. cyclomatic complexity: 658 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:32,241 INFO L93 Difference]: Finished difference Result 1361 states and 2017 transitions. [2022-07-22 02:42:32,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:32,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2017 transitions. [2022-07-22 02:42:32,251 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:32,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2017 transitions. [2022-07-22 02:42:32,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-07-22 02:42:32,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-07-22 02:42:32,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2017 transitions. [2022-07-22 02:42:32,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:32,264 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2022-07-22 02:42:32,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2017 transitions. [2022-07-22 02:42:32,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-07-22 02:42:32,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4819985304922851) internal successors, (2017), 1360 states have internal predecessors, (2017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2017 transitions. [2022-07-22 02:42:32,291 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2022-07-22 02:42:32,291 INFO L374 stractBuchiCegarLoop]: Abstraction has 1361 states and 2017 transitions. [2022-07-22 02:42:32,291 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-22 02:42:32,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2017 transitions. [2022-07-22 02:42:32,296 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:32,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:32,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:32,298 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,298 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,299 INFO L752 eck$LassoCheckResult]: Stem: 20124#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 20125#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19165#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19166#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20054#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 19758#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19759#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20036#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20192#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19924#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19925#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19814#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19815#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20152#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20114#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20042#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20043#L1024 assume !(0 == ~M_E~0); 20288#L1024-2 assume !(0 == ~T1_E~0); 19492#L1029-1 assume !(0 == ~T2_E~0); 19493#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19599#L1039-1 assume !(0 == ~T4_E~0); 20405#L1044-1 assume !(0 == ~T5_E~0); 19836#L1049-1 assume !(0 == ~T6_E~0); 19837#L1054-1 assume !(0 == ~T7_E~0); 20062#L1059-1 assume !(0 == ~T8_E~0); 19539#L1064-1 assume !(0 == ~T9_E~0); 19540#L1069-1 assume !(0 == ~T10_E~0); 20256#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 20322#L1079-1 assume !(0 == ~E_1~0); 20290#L1084-1 assume !(0 == ~E_2~0); 20291#L1089-1 assume !(0 == ~E_3~0); 20341#L1094-1 assume !(0 == ~E_4~0); 19912#L1099-1 assume !(0 == ~E_5~0); 19913#L1104-1 assume !(0 == ~E_6~0); 20170#L1109-1 assume !(0 == ~E_7~0); 19713#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19714#L1119-1 assume !(0 == ~E_9~0); 19770#L1124-1 assume !(0 == ~E_10~0); 19198#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19199#L502 assume 1 == ~m_pc~0; 20060#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19327#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19328#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20110#L1273 assume !(0 != activate_threads_~tmp~1#1); 20111#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20440#L521 assume !(1 == ~t1_pc~0); 20373#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19258#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19259#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19402#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 19242#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19243#L540 assume 1 == ~t2_pc~0; 20304#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20025#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20307#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20320#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 20367#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19514#L559 assume 1 == ~t3_pc~0; 19515#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19794#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19795#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19937#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 19345#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19346#L578 assume !(1 == ~t4_pc~0); 19466#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19465#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19234#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19235#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20094#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20095#L597 assume 1 == ~t5_pc~0; 20457#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19279#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19280#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19885#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 20044#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20045#L616 assume !(1 == ~t6_pc~0); 20059#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20058#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20422#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19967#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 19904#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19905#L635 assume 1 == ~t7_pc~0; 20099#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19248#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19619#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20265#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 20037#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20038#L654 assume !(1 == ~t8_pc~0); 19860#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19861#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20368#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20253#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 20254#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19490#L673 assume 1 == ~t9_pc~0; 19491#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19189#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20437#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20223#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 20179#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20180#L692 assume !(1 == ~t10_pc~0); 20128#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20127#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20046#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19916#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 19917#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20234#L1142 assume !(1 == ~M_E~0); 19405#L1142-2 assume !(1 == ~T1_E~0); 19406#L1147-1 assume !(1 == ~T2_E~0); 20224#L1152-1 assume !(1 == ~T3_E~0); 19800#L1157-1 assume !(1 == ~T4_E~0); 19801#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19941#L1167-1 assume !(1 == ~T6_E~0); 19942#L1172-1 assume !(1 == ~T7_E~0); 20361#L1177-1 assume !(1 == ~T8_E~0); 20079#L1182-1 assume !(1 == ~T9_E~0); 20080#L1187-1 assume !(1 == ~T10_E~0); 20173#L1192-1 assume !(1 == ~E_M~0); 19666#L1197-1 assume !(1 == ~E_1~0); 19667#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20028#L1207-1 assume !(1 == ~E_3~0); 20007#L1212-1 assume !(1 == ~E_4~0); 19264#L1217-1 assume !(1 == ~E_5~0); 19265#L1222-1 assume !(1 == ~E_6~0); 20003#L1227-1 assume !(1 == ~E_7~0); 20004#L1232-1 assume !(1 == ~E_8~0); 19130#L1237-1 assume !(1 == ~E_9~0); 19131#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20061#L1247-1 assume { :end_inline_reset_delta_events } true; 19304#L1553-2 [2022-07-22 02:42:32,299 INFO L754 eck$LassoCheckResult]: Loop: 19304#L1553-2 assume !false; 19305#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20214#L999 assume !false; 20262#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19389#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19282#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19777#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20131#L854 assume !(0 != eval_~tmp~0#1); 20132#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19576#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19577#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20394#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19903#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19873#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19874#L1039-3 assume !(0 == ~T4_E~0); 20197#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19484#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19485#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19260#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19261#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19845#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19846#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20175#L1079-3 assume !(0 == ~E_1~0); 20073#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19960#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19961#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19890#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19891#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20195#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20183#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20184#L1119-3 assume !(0 == ~E_9~0); 20464#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20471#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20431#L502-36 assume 1 == ~m_pc~0; 20198#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19116#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19117#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19541#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19542#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19819#L521-36 assume 1 == ~t1_pc~0; 19820#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19829#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19996#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20033#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20258#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20259#L540-36 assume 1 == ~t2_pc~0; 20433#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19208#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19620#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20472#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19935#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19124#L559-36 assume 1 == ~t3_pc~0; 19125#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19578#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19434#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19435#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20081#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20317#L578-36 assume 1 == ~t4_pc~0; 20052#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20011#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20347#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20348#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19849#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19850#L597-36 assume !(1 == ~t5_pc~0); 20067#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 20420#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19994#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19995#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 19664#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19665#L616-36 assume 1 == ~t6_pc~0; 20434#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19194#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19195#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19797#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19898#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20213#L635-36 assume 1 == ~t7_pc~0; 20397#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20270#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19943#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19944#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19886#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19887#L654-36 assume !(1 == ~t8_pc~0); 20401#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 20402#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20474#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20459#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20441#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19569#L673-36 assume !(1 == ~t9_pc~0); 19570#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 19922#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19923#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20277#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19137#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19138#L692-36 assume 1 == ~t10_pc~0; 20072#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19354#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19897#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19532#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19533#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19896#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20041#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20403#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20404#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19974#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19975#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20266#L1167-3 assume !(1 == ~T6_E~0); 20388#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19884#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19789#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19790#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19803#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19628#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19629#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19870#L1207-3 assume !(1 == ~E_3~0); 19985#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20193#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19523#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19221#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19222#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20297#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20298#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20473#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20351#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19373#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19374#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 20053#L1572 assume !(0 == start_simulation_~tmp~3#1); 19669#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19822#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19151#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20425#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 20426#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19120#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19121#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20275#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 19304#L1553-2 [2022-07-22 02:42:32,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:32,300 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2022-07-22 02:42:32,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:32,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905619419] [2022-07-22 02:42:32,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:32,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:32,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:32,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:32,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:32,341 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905619419] [2022-07-22 02:42:32,341 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1905619419] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:32,344 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:32,345 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:32,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1088242276] [2022-07-22 02:42:32,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:32,347 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:32,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:32,347 INFO L85 PathProgramCache]: Analyzing trace with hash -2102005260, now seen corresponding path program 1 times [2022-07-22 02:42:32,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:32,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067352919] [2022-07-22 02:42:32,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:32,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:32,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:32,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:32,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:32,407 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067352919] [2022-07-22 02:42:32,409 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067352919] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:32,410 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:32,410 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:32,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17895202] [2022-07-22 02:42:32,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:32,411 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:32,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:32,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:32,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:32,413 INFO L87 Difference]: Start difference. First operand 1361 states and 2017 transitions. cyclomatic complexity: 657 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:32,455 INFO L93 Difference]: Finished difference Result 1361 states and 2016 transitions. [2022-07-22 02:42:32,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:32,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2016 transitions. [2022-07-22 02:42:32,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:32,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2016 transitions. [2022-07-22 02:42:32,473 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-07-22 02:42:32,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-07-22 02:42:32,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2016 transitions. [2022-07-22 02:42:32,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:32,476 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2022-07-22 02:42:32,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2016 transitions. [2022-07-22 02:42:32,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-07-22 02:42:32,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4812637766348273) internal successors, (2016), 1360 states have internal predecessors, (2016), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2016 transitions. [2022-07-22 02:42:32,499 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2022-07-22 02:42:32,499 INFO L374 stractBuchiCegarLoop]: Abstraction has 1361 states and 2016 transitions. [2022-07-22 02:42:32,499 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-22 02:42:32,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2016 transitions. [2022-07-22 02:42:32,504 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:32,504 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:32,504 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:32,506 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,506 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,506 INFO L752 eck$LassoCheckResult]: Stem: 22853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 21894#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21895#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22783#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 22486#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22487#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22765#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22921#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22651#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22652#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22541#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22542#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22881#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22843#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22770#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22771#L1024 assume !(0 == ~M_E~0); 23017#L1024-2 assume !(0 == ~T1_E~0); 22221#L1029-1 assume !(0 == ~T2_E~0); 22222#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22328#L1039-1 assume !(0 == ~T4_E~0); 23134#L1044-1 assume !(0 == ~T5_E~0); 22563#L1049-1 assume !(0 == ~T6_E~0); 22564#L1054-1 assume !(0 == ~T7_E~0); 22791#L1059-1 assume !(0 == ~T8_E~0); 22268#L1064-1 assume !(0 == ~T9_E~0); 22269#L1069-1 assume !(0 == ~T10_E~0); 22985#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 23051#L1079-1 assume !(0 == ~E_1~0); 23019#L1084-1 assume !(0 == ~E_2~0); 23020#L1089-1 assume !(0 == ~E_3~0); 23070#L1094-1 assume !(0 == ~E_4~0); 22641#L1099-1 assume !(0 == ~E_5~0); 22642#L1104-1 assume !(0 == ~E_6~0); 22899#L1109-1 assume !(0 == ~E_7~0); 22442#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22443#L1119-1 assume !(0 == ~E_9~0); 22497#L1124-1 assume !(0 == ~E_10~0); 21927#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21928#L502 assume 1 == ~m_pc~0; 22789#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22056#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22057#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22838#L1273 assume !(0 != activate_threads_~tmp~1#1); 22839#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23169#L521 assume !(1 == ~t1_pc~0); 23102#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21987#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21988#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22130#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 21969#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21970#L540 assume 1 == ~t2_pc~0; 23033#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22754#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23036#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23049#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 23096#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22243#L559 assume 1 == ~t3_pc~0; 22244#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22522#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22523#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22666#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 22074#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22075#L578 assume !(1 == ~t4_pc~0); 22193#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22192#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21963#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21964#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22821#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22822#L597 assume 1 == ~t5_pc~0; 23184#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22008#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22009#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22609#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 22772#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22773#L616 assume !(1 == ~t6_pc~0); 22787#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22786#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23151#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22696#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 22633#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22634#L635 assume 1 == ~t7_pc~0; 22826#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21977#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22348#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22994#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 22766#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22767#L654 assume !(1 == ~t8_pc~0); 22589#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22590#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23097#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22982#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 22983#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22219#L673 assume 1 == ~t9_pc~0; 22220#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21918#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23166#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22952#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 22908#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22909#L692 assume !(1 == ~t10_pc~0); 22857#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22856#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22775#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22645#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 22646#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22963#L1142 assume !(1 == ~M_E~0); 22134#L1142-2 assume !(1 == ~T1_E~0); 22135#L1147-1 assume !(1 == ~T2_E~0); 22953#L1152-1 assume !(1 == ~T3_E~0); 22529#L1157-1 assume !(1 == ~T4_E~0); 22530#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22670#L1167-1 assume !(1 == ~T6_E~0); 22671#L1172-1 assume !(1 == ~T7_E~0); 23090#L1177-1 assume !(1 == ~T8_E~0); 22808#L1182-1 assume !(1 == ~T9_E~0); 22809#L1187-1 assume !(1 == ~T10_E~0); 22902#L1192-1 assume !(1 == ~E_M~0); 22393#L1197-1 assume !(1 == ~E_1~0); 22394#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22757#L1207-1 assume !(1 == ~E_3~0); 22736#L1212-1 assume !(1 == ~E_4~0); 21993#L1217-1 assume !(1 == ~E_5~0); 21994#L1222-1 assume !(1 == ~E_6~0); 22732#L1227-1 assume !(1 == ~E_7~0); 22733#L1232-1 assume !(1 == ~E_8~0); 21859#L1237-1 assume !(1 == ~E_9~0); 21860#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22790#L1247-1 assume { :end_inline_reset_delta_events } true; 22033#L1553-2 [2022-07-22 02:42:32,507 INFO L754 eck$LassoCheckResult]: Loop: 22033#L1553-2 assume !false; 22034#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22943#L999 assume !false; 22989#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22118#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22011#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22506#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22860#L854 assume !(0 != eval_~tmp~0#1); 22861#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22305#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22306#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23123#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22632#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22602#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22603#L1039-3 assume !(0 == ~T4_E~0); 22926#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22213#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22214#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21989#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21990#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22574#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22575#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22904#L1079-3 assume !(0 == ~E_1~0); 22801#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22689#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22690#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22619#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22620#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22924#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22912#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22913#L1119-3 assume !(0 == ~E_9~0); 23193#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23200#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23160#L502-36 assume !(1 == ~m_pc~0); 22360#L502-38 is_master_triggered_~__retres1~0#1 := 0; 21845#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21846#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22270#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22271#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22546#L521-36 assume 1 == ~t1_pc~0; 22547#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22558#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22725#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22762#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22987#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22988#L540-36 assume 1 == ~t2_pc~0; 23162#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21935#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22349#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23201#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22665#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21856#L559-36 assume 1 == ~t3_pc~0; 21857#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22313#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22163#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22164#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22810#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23046#L578-36 assume !(1 == ~t4_pc~0); 22742#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 22743#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23076#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23077#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22580#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22581#L597-36 assume 1 == ~t5_pc~0; 22800#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23149#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22723#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22724#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 22395#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22396#L616-36 assume !(1 == ~t6_pc~0); 23121#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 21923#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21924#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22526#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22627#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22942#L635-36 assume 1 == ~t7_pc~0; 23126#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22999#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22672#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22673#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22615#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22616#L654-36 assume !(1 == ~t8_pc~0); 23130#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 23131#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23203#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23188#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23170#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22298#L673-36 assume !(1 == ~t9_pc~0); 22299#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 22653#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22654#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23006#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21866#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21867#L692-36 assume 1 == ~t10_pc~0; 22802#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22083#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22626#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22261#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22262#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22625#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22774#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23132#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23133#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22703#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22704#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22995#L1167-3 assume !(1 == ~T6_E~0); 23117#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22614#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22518#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22519#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22532#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22357#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22358#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22599#L1207-3 assume !(1 == ~E_3~0); 22714#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22922#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22253#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21950#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21951#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23027#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23028#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23202#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23080#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22102#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22103#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 22782#L1572 assume !(0 == start_simulation_~tmp~3#1); 22400#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22551#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21880#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23154#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 23155#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21849#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21850#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 23004#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 22033#L1553-2 [2022-07-22 02:42:32,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:32,508 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2022-07-22 02:42:32,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:32,508 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235142858] [2022-07-22 02:42:32,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:32,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:32,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:32,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:32,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:32,542 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1235142858] [2022-07-22 02:42:32,542 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1235142858] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:32,543 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:32,543 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:32,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283599294] [2022-07-22 02:42:32,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:32,543 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:32,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:32,544 INFO L85 PathProgramCache]: Analyzing trace with hash 1653620534, now seen corresponding path program 1 times [2022-07-22 02:42:32,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:32,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944697574] [2022-07-22 02:42:32,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:32,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:32,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:32,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:32,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:32,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944697574] [2022-07-22 02:42:32,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944697574] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:32,580 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:32,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:32,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96506243] [2022-07-22 02:42:32,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:32,581 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:32,581 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:32,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:32,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:32,582 INFO L87 Difference]: Start difference. First operand 1361 states and 2016 transitions. cyclomatic complexity: 656 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:32,607 INFO L93 Difference]: Finished difference Result 1361 states and 2015 transitions. [2022-07-22 02:42:32,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:32,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1361 states and 2015 transitions. [2022-07-22 02:42:32,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:32,622 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1361 states to 1361 states and 2015 transitions. [2022-07-22 02:42:32,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1361 [2022-07-22 02:42:32,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1361 [2022-07-22 02:42:32,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1361 states and 2015 transitions. [2022-07-22 02:42:32,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:32,626 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2022-07-22 02:42:32,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1361 states and 2015 transitions. [2022-07-22 02:42:32,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1361 to 1361. [2022-07-22 02:42:32,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1361 states have (on average 1.4805290227773695) internal successors, (2015), 1360 states have internal predecessors, (2015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 2015 transitions. [2022-07-22 02:42:32,647 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2022-07-22 02:42:32,647 INFO L374 stractBuchiCegarLoop]: Abstraction has 1361 states and 2015 transitions. [2022-07-22 02:42:32,647 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-22 02:42:32,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1361 states and 2015 transitions. [2022-07-22 02:42:32,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1222 [2022-07-22 02:42:32,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:32,652 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:32,654 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,654 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,654 INFO L752 eck$LassoCheckResult]: Stem: 25582#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24623#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24624#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25512#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 25215#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25216#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25494#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25650#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25380#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25381#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25270#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25271#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25610#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25572#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 25499#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25500#L1024 assume !(0 == ~M_E~0); 25746#L1024-2 assume !(0 == ~T1_E~0); 24950#L1029-1 assume !(0 == ~T2_E~0); 24951#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25057#L1039-1 assume !(0 == ~T4_E~0); 25863#L1044-1 assume !(0 == ~T5_E~0); 25292#L1049-1 assume !(0 == ~T6_E~0); 25293#L1054-1 assume !(0 == ~T7_E~0); 25520#L1059-1 assume !(0 == ~T8_E~0); 24997#L1064-1 assume !(0 == ~T9_E~0); 24998#L1069-1 assume !(0 == ~T10_E~0); 25714#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25780#L1079-1 assume !(0 == ~E_1~0); 25748#L1084-1 assume !(0 == ~E_2~0); 25749#L1089-1 assume !(0 == ~E_3~0); 25799#L1094-1 assume !(0 == ~E_4~0); 25370#L1099-1 assume !(0 == ~E_5~0); 25371#L1104-1 assume !(0 == ~E_6~0); 25628#L1109-1 assume !(0 == ~E_7~0); 25171#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25172#L1119-1 assume !(0 == ~E_9~0); 25226#L1124-1 assume !(0 == ~E_10~0); 24656#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24657#L502 assume 1 == ~m_pc~0; 25518#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24785#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24786#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25567#L1273 assume !(0 != activate_threads_~tmp~1#1); 25568#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25898#L521 assume !(1 == ~t1_pc~0); 25831#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24716#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24717#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24859#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 24698#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24699#L540 assume 1 == ~t2_pc~0; 25762#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25483#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25765#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25778#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 25825#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24972#L559 assume 1 == ~t3_pc~0; 24973#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25251#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25252#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25395#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 24803#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24804#L578 assume !(1 == ~t4_pc~0); 24922#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24921#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24692#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24693#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25550#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25551#L597 assume 1 == ~t5_pc~0; 25913#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24737#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24738#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25338#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 25501#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25502#L616 assume !(1 == ~t6_pc~0); 25516#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25515#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25880#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25425#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 25362#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25363#L635 assume 1 == ~t7_pc~0; 25555#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24706#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25077#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25723#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 25495#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25496#L654 assume !(1 == ~t8_pc~0); 25318#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25319#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25826#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25711#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 25712#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24948#L673 assume 1 == ~t9_pc~0; 24949#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24647#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25895#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25681#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 25637#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25638#L692 assume !(1 == ~t10_pc~0); 25586#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25585#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25504#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25374#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 25375#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25692#L1142 assume !(1 == ~M_E~0); 24863#L1142-2 assume !(1 == ~T1_E~0); 24864#L1147-1 assume !(1 == ~T2_E~0); 25682#L1152-1 assume !(1 == ~T3_E~0); 25258#L1157-1 assume !(1 == ~T4_E~0); 25259#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25399#L1167-1 assume !(1 == ~T6_E~0); 25400#L1172-1 assume !(1 == ~T7_E~0); 25819#L1177-1 assume !(1 == ~T8_E~0); 25537#L1182-1 assume !(1 == ~T9_E~0); 25538#L1187-1 assume !(1 == ~T10_E~0); 25631#L1192-1 assume !(1 == ~E_M~0); 25122#L1197-1 assume !(1 == ~E_1~0); 25123#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25486#L1207-1 assume !(1 == ~E_3~0); 25465#L1212-1 assume !(1 == ~E_4~0); 24722#L1217-1 assume !(1 == ~E_5~0); 24723#L1222-1 assume !(1 == ~E_6~0); 25461#L1227-1 assume !(1 == ~E_7~0); 25462#L1232-1 assume !(1 == ~E_8~0); 24588#L1237-1 assume !(1 == ~E_9~0); 24589#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25519#L1247-1 assume { :end_inline_reset_delta_events } true; 24762#L1553-2 [2022-07-22 02:42:32,655 INFO L754 eck$LassoCheckResult]: Loop: 24762#L1553-2 assume !false; 24763#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25672#L999 assume !false; 25718#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24847#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24740#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25235#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25589#L854 assume !(0 != eval_~tmp~0#1); 25590#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25034#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25035#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25852#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25361#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25331#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25332#L1039-3 assume !(0 == ~T4_E~0); 25655#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24942#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24943#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24718#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24719#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25303#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25304#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25633#L1079-3 assume !(0 == ~E_1~0); 25530#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25418#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25419#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25348#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25349#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25653#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25641#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25642#L1119-3 assume !(0 == ~E_9~0); 25922#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25929#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25889#L502-36 assume !(1 == ~m_pc~0); 25089#L502-38 is_master_triggered_~__retres1~0#1 := 0; 24574#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24575#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24999#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25000#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25275#L521-36 assume 1 == ~t1_pc~0; 25276#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25287#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25454#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25491#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25716#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25717#L540-36 assume 1 == ~t2_pc~0; 25891#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24664#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25078#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25930#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25394#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24585#L559-36 assume 1 == ~t3_pc~0; 24586#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25042#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24892#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24893#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25539#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25775#L578-36 assume 1 == ~t4_pc~0; 25510#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25472#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25805#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25806#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25309#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25310#L597-36 assume !(1 == ~t5_pc~0); 25528#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 25878#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25452#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25453#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 25124#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25125#L616-36 assume 1 == ~t6_pc~0; 25892#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24652#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24653#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25255#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25356#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25671#L635-36 assume !(1 == ~t7_pc~0); 25856#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 25728#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25401#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25402#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25344#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25345#L654-36 assume !(1 == ~t8_pc~0); 25859#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 25860#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25932#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25917#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25899#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25027#L673-36 assume !(1 == ~t9_pc~0); 25028#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 25382#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25383#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25735#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24595#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24596#L692-36 assume 1 == ~t10_pc~0; 25531#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24812#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25355#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24990#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24991#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25354#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25503#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25861#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25862#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25432#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25433#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25724#L1167-3 assume !(1 == ~T6_E~0); 25846#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25343#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25247#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25248#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25261#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25086#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25087#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25328#L1207-3 assume !(1 == ~E_3~0); 25443#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25651#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24982#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24679#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24680#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25756#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25757#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25931#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25809#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24831#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24832#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 25511#L1572 assume !(0 == start_simulation_~tmp~3#1); 25129#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25280#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24609#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25883#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 25884#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24578#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24579#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25733#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 24762#L1553-2 [2022-07-22 02:42:32,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:32,656 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2022-07-22 02:42:32,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:32,656 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322279803] [2022-07-22 02:42:32,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:32,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:32,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:32,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:32,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:32,693 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322279803] [2022-07-22 02:42:32,693 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322279803] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:32,693 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:32,693 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:32,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1408598780] [2022-07-22 02:42:32,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:32,694 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:32,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:32,694 INFO L85 PathProgramCache]: Analyzing trace with hash 131639478, now seen corresponding path program 1 times [2022-07-22 02:42:32,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:32,695 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537181429] [2022-07-22 02:42:32,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:32,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:32,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:32,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:32,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:32,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537181429] [2022-07-22 02:42:32,743 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [537181429] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:32,743 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:32,743 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:32,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631348293] [2022-07-22 02:42:32,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:32,744 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:32,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:32,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:32,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:32,745 INFO L87 Difference]: Start difference. First operand 1361 states and 2015 transitions. cyclomatic complexity: 655 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:32,899 INFO L93 Difference]: Finished difference Result 2504 states and 3694 transitions. [2022-07-22 02:42:32,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:32,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2504 states and 3694 transitions. [2022-07-22 02:42:32,913 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2343 [2022-07-22 02:42:32,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2504 states to 2504 states and 3694 transitions. [2022-07-22 02:42:32,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2504 [2022-07-22 02:42:32,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2504 [2022-07-22 02:42:32,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2504 states and 3694 transitions. [2022-07-22 02:42:32,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:32,932 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2022-07-22 02:42:32,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2504 states and 3694 transitions. [2022-07-22 02:42:32,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2504 to 2504. [2022-07-22 02:42:32,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2504 states, 2504 states have (on average 1.4752396166134185) internal successors, (3694), 2503 states have internal predecessors, (3694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:32,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2504 states to 2504 states and 3694 transitions. [2022-07-22 02:42:32,976 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2022-07-22 02:42:32,976 INFO L374 stractBuchiCegarLoop]: Abstraction has 2504 states and 3694 transitions. [2022-07-22 02:42:32,976 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-22 02:42:32,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2504 states and 3694 transitions. [2022-07-22 02:42:32,984 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2343 [2022-07-22 02:42:32,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:32,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:32,986 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,986 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:32,986 INFO L752 eck$LassoCheckResult]: Stem: 29462#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29463#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 28498#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28499#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29392#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 29092#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29093#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29373#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29530#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29259#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29260#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29147#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29148#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29490#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29452#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 29378#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29379#L1024 assume !(0 == ~M_E~0); 29631#L1024-2 assume !(0 == ~T1_E~0); 28827#L1029-1 assume !(0 == ~T2_E~0); 28828#L1034-1 assume !(0 == ~T3_E~0); 28934#L1039-1 assume !(0 == ~T4_E~0); 29752#L1044-1 assume !(0 == ~T5_E~0); 29170#L1049-1 assume !(0 == ~T6_E~0); 29171#L1054-1 assume !(0 == ~T7_E~0); 29400#L1059-1 assume !(0 == ~T8_E~0); 28874#L1064-1 assume !(0 == ~T9_E~0); 28875#L1069-1 assume !(0 == ~T10_E~0); 29597#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29666#L1079-1 assume !(0 == ~E_1~0); 29633#L1084-1 assume !(0 == ~E_2~0); 29634#L1089-1 assume !(0 == ~E_3~0); 29685#L1094-1 assume !(0 == ~E_4~0); 29249#L1099-1 assume !(0 == ~E_5~0); 29250#L1104-1 assume !(0 == ~E_6~0); 29508#L1109-1 assume !(0 == ~E_7~0); 29048#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29049#L1119-1 assume !(0 == ~E_9~0); 29103#L1124-1 assume !(0 == ~E_10~0); 28531#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28532#L502 assume 1 == ~m_pc~0; 29398#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28660#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28661#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29447#L1273 assume !(0 != activate_threads_~tmp~1#1); 29448#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29798#L521 assume !(1 == ~t1_pc~0); 29718#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28591#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28592#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28734#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 28573#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28574#L540 assume 1 == ~t2_pc~0; 29648#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29362#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29651#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29664#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 29712#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28849#L559 assume 1 == ~t3_pc~0; 28850#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29128#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29129#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29274#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 28678#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28679#L578 assume !(1 == ~t4_pc~0); 28799#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28798#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28567#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28568#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29430#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29431#L597 assume 1 == ~t5_pc~0; 29822#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28612#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28613#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29216#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 29380#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29381#L616 assume !(1 == ~t6_pc~0); 29396#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29395#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29774#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29304#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 29241#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29242#L635 assume 1 == ~t7_pc~0; 29435#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28581#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28954#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29606#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 29374#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29375#L654 assume !(1 == ~t8_pc~0); 29196#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29197#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29713#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29594#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 29595#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28825#L673 assume 1 == ~t9_pc~0; 28826#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28522#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29794#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29562#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 29517#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29518#L692 assume !(1 == ~t10_pc~0); 29466#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29465#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29384#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29253#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 29254#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29574#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 28738#L1142-2 assume !(1 == ~T1_E~0); 28739#L1147-1 assume !(1 == ~T2_E~0); 29563#L1152-1 assume !(1 == ~T3_E~0); 29135#L1157-1 assume !(1 == ~T4_E~0); 29136#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29978#L1167-1 assume !(1 == ~T6_E~0); 29967#L1172-1 assume !(1 == ~T7_E~0); 29965#L1177-1 assume !(1 == ~T8_E~0); 29963#L1182-1 assume !(1 == ~T9_E~0); 29961#L1187-1 assume !(1 == ~T10_E~0); 29927#L1192-1 assume !(1 == ~E_M~0); 29926#L1197-1 assume !(1 == ~E_1~0); 29925#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29365#L1207-1 assume !(1 == ~E_3~0); 29344#L1212-1 assume !(1 == ~E_4~0); 28597#L1217-1 assume !(1 == ~E_5~0); 28598#L1222-1 assume !(1 == ~E_6~0); 29340#L1227-1 assume !(1 == ~E_7~0); 29341#L1232-1 assume !(1 == ~E_8~0); 28463#L1237-1 assume !(1 == ~E_9~0); 28464#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29399#L1247-1 assume { :end_inline_reset_delta_events } true; 28637#L1553-2 [2022-07-22 02:42:32,987 INFO L754 eck$LassoCheckResult]: Loop: 28637#L1553-2 assume !false; 28638#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29552#L999 assume !false; 29601#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28722#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28615#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29112#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29856#L854 assume !(0 != eval_~tmp~0#1); 29855#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29854#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29853#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29741#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29240#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29209#L1034-3 assume !(0 == ~T3_E~0); 29210#L1039-3 assume !(0 == ~T4_E~0); 29535#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28819#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28820#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28593#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28594#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29181#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29182#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29513#L1079-3 assume !(0 == ~E_1~0); 29410#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29297#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29298#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29226#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29227#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29533#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29521#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29522#L1119-3 assume !(0 == ~E_9~0); 29833#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29843#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29787#L502-36 assume 1 == ~m_pc~0; 29536#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28449#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28450#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28876#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28877#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29152#L521-36 assume 1 == ~t1_pc~0; 29153#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29165#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29333#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29370#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29599#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29600#L540-36 assume !(1 == ~t2_pc~0); 28538#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 28539#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28955#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29844#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29273#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28460#L559-36 assume 1 == ~t3_pc~0; 28461#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28919#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28767#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28768#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29419#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29661#L578-36 assume !(1 == ~t4_pc~0); 29350#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 29351#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29691#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29692#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29187#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29188#L597-36 assume !(1 == ~t5_pc~0); 29408#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 29772#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29331#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29332#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 29001#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29002#L616-36 assume !(1 == ~t6_pc~0); 29739#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 28527#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28528#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29132#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29235#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29551#L635-36 assume 1 == ~t7_pc~0; 29744#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29612#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29280#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29281#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29222#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29223#L654-36 assume !(1 == ~t8_pc~0); 29748#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 29749#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29847#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29826#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29800#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28904#L673-36 assume !(1 == ~t9_pc~0); 28905#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 29261#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29262#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30844#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30843#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30842#L692-36 assume 1 == ~t10_pc~0; 30840#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30839#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30838#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30837#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30836#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30835#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29382#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30834#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30833#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29776#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30832#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30831#L1167-3 assume !(1 == ~T6_E~0); 30830#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30829#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30828#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30827#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30826#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30825#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30824#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30823#L1207-3 assume !(1 == ~E_3~0); 30822#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30821#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30820#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30819#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30818#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30817#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30816#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30815#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30804#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30604#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30603#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 30602#L1572 assume !(0 == start_simulation_~tmp~3#1); 29006#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29842#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28484#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29780#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 29782#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28453#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28454#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 29617#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 28637#L1553-2 [2022-07-22 02:42:32,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:32,988 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2022-07-22 02:42:32,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:32,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508620316] [2022-07-22 02:42:32,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:32,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:32,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:33,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:33,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:33,019 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508620316] [2022-07-22 02:42:33,019 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508620316] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:33,019 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:33,019 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:33,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030919743] [2022-07-22 02:42:33,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:33,020 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:33,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:33,021 INFO L85 PathProgramCache]: Analyzing trace with hash -170343111, now seen corresponding path program 1 times [2022-07-22 02:42:33,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:33,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620264101] [2022-07-22 02:42:33,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:33,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:33,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:33,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:33,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:33,055 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620264101] [2022-07-22 02:42:33,056 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [620264101] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:33,056 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:33,056 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:33,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419789028] [2022-07-22 02:42:33,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:33,057 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:33,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:33,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:33,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:33,058 INFO L87 Difference]: Start difference. First operand 2504 states and 3694 transitions. cyclomatic complexity: 1192 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:33,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:33,231 INFO L93 Difference]: Finished difference Result 4620 states and 6803 transitions. [2022-07-22 02:42:33,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:33,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4620 states and 6803 transitions. [2022-07-22 02:42:33,254 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4427 [2022-07-22 02:42:33,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4620 states to 4620 states and 6803 transitions. [2022-07-22 02:42:33,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4620 [2022-07-22 02:42:33,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4620 [2022-07-22 02:42:33,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4620 states and 6803 transitions. [2022-07-22 02:42:33,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:33,294 INFO L369 hiAutomatonCegarLoop]: Abstraction has 4620 states and 6803 transitions. [2022-07-22 02:42:33,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4620 states and 6803 transitions. [2022-07-22 02:42:33,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4620 to 4618. [2022-07-22 02:42:33,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4618 states, 4618 states have (on average 1.4727154612386315) internal successors, (6801), 4617 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:33,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4618 states to 4618 states and 6801 transitions. [2022-07-22 02:42:33,382 INFO L392 hiAutomatonCegarLoop]: Abstraction has 4618 states and 6801 transitions. [2022-07-22 02:42:33,383 INFO L374 stractBuchiCegarLoop]: Abstraction has 4618 states and 6801 transitions. [2022-07-22 02:42:33,383 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-22 02:42:33,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4618 states and 6801 transitions. [2022-07-22 02:42:33,402 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4427 [2022-07-22 02:42:33,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:33,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:33,404 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:33,404 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:33,405 INFO L752 eck$LassoCheckResult]: Stem: 36620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 35632#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35633#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36545#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 36232#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36233#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36523#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36695#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36405#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36406#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36293#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36294#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36648#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36609#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36533#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36534#L1024 assume !(0 == ~M_E~0); 36810#L1024-2 assume !(0 == ~T1_E~0); 35961#L1029-1 assume !(0 == ~T2_E~0); 35962#L1034-1 assume !(0 == ~T3_E~0); 36070#L1039-1 assume !(0 == ~T4_E~0); 36945#L1044-1 assume !(0 == ~T5_E~0); 36314#L1049-1 assume !(0 == ~T6_E~0); 36315#L1054-1 assume !(0 == ~T7_E~0); 36555#L1059-1 assume !(0 == ~T8_E~0); 36008#L1064-1 assume !(0 == ~T9_E~0); 36009#L1069-1 assume !(0 == ~T10_E~0); 36775#L1074-1 assume !(0 == ~E_M~0); 36851#L1079-1 assume !(0 == ~E_1~0); 36812#L1084-1 assume !(0 == ~E_2~0); 36813#L1089-1 assume !(0 == ~E_3~0); 36872#L1094-1 assume !(0 == ~E_4~0); 36393#L1099-1 assume !(0 == ~E_5~0); 36394#L1104-1 assume !(0 == ~E_6~0); 36668#L1109-1 assume !(0 == ~E_7~0); 36184#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36185#L1119-1 assume !(0 == ~E_9~0); 36246#L1124-1 assume !(0 == ~E_10~0); 35665#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35666#L502 assume 1 == ~m_pc~0; 36553#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35794#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35795#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36605#L1273 assume !(0 != activate_threads_~tmp~1#1); 36606#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36990#L521 assume !(1 == ~t1_pc~0); 36907#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35725#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35726#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35869#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 35709#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35710#L540 assume 1 == ~t2_pc~0; 36833#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36512#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36836#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36849#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 36900#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35983#L559 assume 1 == ~t3_pc~0; 35984#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36268#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36269#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36421#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 35812#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35813#L578 assume !(1 == ~t4_pc~0); 35935#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35934#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35701#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35702#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36587#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36588#L597 assume 1 == ~t5_pc~0; 37015#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35746#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35747#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36364#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 36535#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36536#L616 assume !(1 == ~t6_pc~0); 36552#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36551#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36964#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36451#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 36383#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36384#L635 assume 1 == ~t7_pc~0; 36592#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35715#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36090#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36786#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 36524#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36525#L654 assume !(1 == ~t8_pc~0); 36339#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36340#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36901#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36772#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 36773#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35959#L673 assume 1 == ~t9_pc~0; 35960#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35656#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36986#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36735#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 36679#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36680#L692 assume !(1 == ~t10_pc~0); 36624#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36623#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36537#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36397#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 36398#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36749#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 35872#L1142-2 assume !(1 == ~T1_E~0); 35873#L1147-1 assume !(1 == ~T2_E~0); 37049#L1152-1 assume !(1 == ~T3_E~0); 36274#L1157-1 assume !(1 == ~T4_E~0); 36275#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36425#L1167-1 assume !(1 == ~T6_E~0); 36426#L1172-1 assume !(1 == ~T7_E~0); 36908#L1177-1 assume !(1 == ~T8_E~0); 36909#L1182-1 assume !(1 == ~T9_E~0); 36671#L1187-1 assume !(1 == ~T10_E~0); 36672#L1192-1 assume !(1 == ~E_M~0); 37310#L1197-1 assume !(1 == ~E_1~0); 37309#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37308#L1207-1 assume !(1 == ~E_3~0); 37307#L1212-1 assume !(1 == ~E_4~0); 37306#L1217-1 assume !(1 == ~E_5~0); 37305#L1222-1 assume !(1 == ~E_6~0); 37304#L1227-1 assume !(1 == ~E_7~0); 37303#L1232-1 assume !(1 == ~E_8~0); 37301#L1237-1 assume !(1 == ~E_9~0); 37113#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37096#L1247-1 assume { :end_inline_reset_delta_events } true; 37089#L1553-2 [2022-07-22 02:42:33,405 INFO L754 eck$LassoCheckResult]: Loop: 37089#L1553-2 assume !false; 37083#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37078#L999 assume !false; 37077#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37076#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37065#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37064#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37062#L854 assume !(0 != eval_~tmp~0#1); 37061#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37060#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37058#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37059#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38335#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38332#L1034-3 assume !(0 == ~T3_E~0); 38329#L1039-3 assume !(0 == ~T4_E~0); 38326#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38323#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38320#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38317#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38314#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38311#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38308#L1074-3 assume !(0 == ~E_M~0); 38305#L1079-3 assume !(0 == ~E_1~0); 38302#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38299#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38296#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38293#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38290#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38287#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38284#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38281#L1119-3 assume !(0 == ~E_9~0); 38278#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38275#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38272#L502-36 assume !(1 == ~m_pc~0); 38268#L502-38 is_master_triggered_~__retres1~0#1 := 0; 38263#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38260#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38257#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38254#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38251#L521-36 assume 1 == ~t1_pc~0; 38247#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38242#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38239#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38236#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38233#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38230#L540-36 assume !(1 == ~t2_pc~0); 38226#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 38221#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38218#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38215#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38212#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38209#L559-36 assume 1 == ~t3_pc~0; 38205#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38200#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38197#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38194#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38191#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38188#L578-36 assume !(1 == ~t4_pc~0); 38184#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 38179#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38176#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38173#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38170#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38167#L597-36 assume 1 == ~t5_pc~0; 38163#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38158#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38155#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38152#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 38149#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38146#L616-36 assume 1 == ~t6_pc~0; 38142#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38137#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38134#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38131#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38128#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38125#L635-36 assume 1 == ~t7_pc~0; 38121#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38116#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38113#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38110#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38107#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38104#L654-36 assume 1 == ~t8_pc~0; 38100#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38095#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38092#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38089#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38086#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38083#L673-36 assume 1 == ~t9_pc~0; 38080#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38074#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38071#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38068#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38065#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38062#L692-36 assume 1 == ~t10_pc~0; 38058#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38053#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38050#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38047#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38044#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38041#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36531#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38036#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38033#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36965#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38028#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38026#L1167-3 assume !(1 == ~T6_E~0); 38024#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38022#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38020#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38018#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38015#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38012#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38011#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38010#L1207-3 assume !(1 == ~E_3~0); 38009#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38008#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38007#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38006#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38005#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38004#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38003#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 38002#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37340#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37338#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37337#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 37326#L1572 assume !(0 == start_simulation_~tmp~3#1); 36140#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37130#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37120#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37118#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 37116#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37115#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37114#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37097#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 37089#L1553-2 [2022-07-22 02:42:33,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:33,406 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2022-07-22 02:42:33,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:33,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [365237567] [2022-07-22 02:42:33,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:33,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:33,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:33,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:33,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:33,440 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [365237567] [2022-07-22 02:42:33,440 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [365237567] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:33,440 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:33,440 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:33,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000648158] [2022-07-22 02:42:33,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:33,442 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:33,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:33,443 INFO L85 PathProgramCache]: Analyzing trace with hash -23258120, now seen corresponding path program 1 times [2022-07-22 02:42:33,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:33,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046407953] [2022-07-22 02:42:33,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:33,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:33,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:33,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:33,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:33,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046407953] [2022-07-22 02:42:33,477 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046407953] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:33,478 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:33,478 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:33,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97975253] [2022-07-22 02:42:33,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:33,478 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:33,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:33,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:33,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:33,479 INFO L87 Difference]: Start difference. First operand 4618 states and 6801 transitions. cyclomatic complexity: 2187 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:33,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:33,652 INFO L93 Difference]: Finished difference Result 8652 states and 12712 transitions. [2022-07-22 02:42:33,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:33,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8652 states and 12712 transitions. [2022-07-22 02:42:33,709 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8437 [2022-07-22 02:42:33,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8652 states to 8652 states and 12712 transitions. [2022-07-22 02:42:33,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8652 [2022-07-22 02:42:33,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8652 [2022-07-22 02:42:33,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8652 states and 12712 transitions. [2022-07-22 02:42:33,813 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:33,813 INFO L369 hiAutomatonCegarLoop]: Abstraction has 8652 states and 12712 transitions. [2022-07-22 02:42:33,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8652 states and 12712 transitions. [2022-07-22 02:42:33,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8652 to 8648. [2022-07-22 02:42:33,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8648 states, 8648 states have (on average 1.469472710453284) internal successors, (12708), 8647 states have internal predecessors, (12708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:33,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8648 states to 8648 states and 12708 transitions. [2022-07-22 02:42:34,000 INFO L392 hiAutomatonCegarLoop]: Abstraction has 8648 states and 12708 transitions. [2022-07-22 02:42:34,000 INFO L374 stractBuchiCegarLoop]: Abstraction has 8648 states and 12708 transitions. [2022-07-22 02:42:34,000 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-22 02:42:34,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8648 states and 12708 transitions. [2022-07-22 02:42:34,039 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8437 [2022-07-22 02:42:34,040 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:34,040 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:34,042 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:34,042 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:34,043 INFO L752 eck$LassoCheckResult]: Stem: 49883#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49884#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 48912#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48913#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49811#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 49505#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49506#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49792#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49953#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49676#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49677#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49564#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49565#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49911#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49873#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49797#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49798#L1024 assume !(0 == ~M_E~0); 50056#L1024-2 assume !(0 == ~T1_E~0); 49239#L1029-1 assume !(0 == ~T2_E~0); 49240#L1034-1 assume !(0 == ~T3_E~0); 49346#L1039-1 assume !(0 == ~T4_E~0); 50181#L1044-1 assume !(0 == ~T5_E~0); 49588#L1049-1 assume !(0 == ~T6_E~0); 49589#L1054-1 assume !(0 == ~T7_E~0); 49819#L1059-1 assume !(0 == ~T8_E~0); 49286#L1064-1 assume !(0 == ~T9_E~0); 49287#L1069-1 assume !(0 == ~T10_E~0); 50022#L1074-1 assume !(0 == ~E_M~0); 50090#L1079-1 assume !(0 == ~E_1~0); 50058#L1084-1 assume !(0 == ~E_2~0); 50059#L1089-1 assume !(0 == ~E_3~0); 50110#L1094-1 assume !(0 == ~E_4~0); 49666#L1099-1 assume !(0 == ~E_5~0); 49667#L1104-1 assume !(0 == ~E_6~0); 49930#L1109-1 assume !(0 == ~E_7~0); 49460#L1114-1 assume !(0 == ~E_8~0); 49461#L1119-1 assume !(0 == ~E_9~0); 49516#L1124-1 assume !(0 == ~E_10~0); 48945#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48946#L502 assume 1 == ~m_pc~0; 49817#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49074#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49075#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49868#L1273 assume !(0 != activate_threads_~tmp~1#1); 49869#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50221#L521 assume !(1 == ~t1_pc~0); 50145#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49005#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49006#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49148#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 48987#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48988#L540 assume 1 == ~t2_pc~0; 50072#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49781#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50075#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50088#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 50138#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49261#L559 assume 1 == ~t3_pc~0; 49262#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49541#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49542#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49691#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 49092#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49093#L578 assume !(1 == ~t4_pc~0); 49211#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49210#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48981#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48982#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49850#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49851#L597 assume 1 == ~t5_pc~0; 50238#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49026#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49027#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49634#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 49799#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49800#L616 assume !(1 == ~t6_pc~0); 49815#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49814#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50199#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49723#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 49658#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49659#L635 assume 1 == ~t7_pc~0; 49855#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48995#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49366#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50032#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 49793#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49794#L654 assume !(1 == ~t8_pc~0); 49614#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49615#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50139#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50019#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 50020#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49237#L673 assume 1 == ~t9_pc~0; 49238#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48936#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50216#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49986#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 49940#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49941#L692 assume !(1 == ~t10_pc~0); 49887#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49886#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49803#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49670#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 49671#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50000#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 50272#L1142-2 assume !(1 == ~T1_E~0); 49987#L1147-1 assume !(1 == ~T2_E~0); 49988#L1152-1 assume !(1 == ~T3_E~0); 50408#L1157-1 assume !(1 == ~T4_E~0); 50406#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50404#L1167-1 assume !(1 == ~T6_E~0); 50401#L1172-1 assume !(1 == ~T7_E~0); 50399#L1177-1 assume !(1 == ~T8_E~0); 50397#L1182-1 assume !(1 == ~T9_E~0); 50395#L1187-1 assume !(1 == ~T10_E~0); 50393#L1192-1 assume !(1 == ~E_M~0); 50391#L1197-1 assume !(1 == ~E_1~0); 50388#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50386#L1207-1 assume !(1 == ~E_3~0); 50384#L1212-1 assume !(1 == ~E_4~0); 50378#L1217-1 assume !(1 == ~E_5~0); 50376#L1222-1 assume !(1 == ~E_6~0); 50374#L1227-1 assume !(1 == ~E_7~0); 50369#L1232-1 assume !(1 == ~E_8~0); 50363#L1237-1 assume !(1 == ~E_9~0); 50358#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50314#L1247-1 assume { :end_inline_reset_delta_events } true; 50307#L1553-2 [2022-07-22 02:42:34,043 INFO L754 eck$LassoCheckResult]: Loop: 50307#L1553-2 assume !false; 50301#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50296#L999 assume !false; 50295#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50294#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50283#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50282#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50280#L854 assume !(0 != eval_~tmp~0#1); 50279#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50278#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50276#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50277#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51118#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51116#L1034-3 assume !(0 == ~T3_E~0); 51114#L1039-3 assume !(0 == ~T4_E~0); 51111#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51109#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51000#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50997#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50995#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50993#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50991#L1074-3 assume !(0 == ~E_M~0); 50989#L1079-3 assume !(0 == ~E_1~0); 50987#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50984#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50982#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50980#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50978#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50976#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50974#L1114-3 assume !(0 == ~E_8~0); 50971#L1119-3 assume !(0 == ~E_9~0); 50969#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50967#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50965#L502-36 assume !(1 == ~m_pc~0); 50962#L502-38 is_master_triggered_~__retres1~0#1 := 0; 50960#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50957#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50955#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50953#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50951#L521-36 assume 1 == ~t1_pc~0; 50948#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50946#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50945#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50944#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50942#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50940#L540-36 assume !(1 == ~t2_pc~0); 50937#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 50935#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50934#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50932#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50930#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50928#L559-36 assume 1 == ~t3_pc~0; 50925#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50923#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50922#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50921#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50920#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50919#L578-36 assume !(1 == ~t4_pc~0); 50917#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 50905#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50903#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50901#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50899#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50897#L597-36 assume 1 == ~t5_pc~0; 50878#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50876#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50866#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50858#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 50851#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50848#L616-36 assume 1 == ~t6_pc~0; 50843#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50830#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50827#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50824#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50820#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50817#L635-36 assume 1 == ~t7_pc~0; 50812#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50809#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50806#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50803#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50800#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50797#L654-36 assume 1 == ~t8_pc~0; 50792#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50789#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50786#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50783#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50780#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50777#L673-36 assume !(1 == ~t9_pc~0); 50772#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 50769#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50766#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50763#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50760#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50758#L692-36 assume 1 == ~t10_pc~0; 50755#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50752#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50748#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50581#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50578#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50548#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49801#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50545#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50543#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50200#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50538#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50536#L1167-3 assume !(1 == ~T6_E~0); 50534#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50527#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50519#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50514#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50508#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50503#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50499#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50495#L1207-3 assume !(1 == ~E_3~0); 50491#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50487#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50481#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50478#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50470#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50468#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50467#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50466#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50453#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50450#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50447#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 50444#L1572 assume !(0 == start_simulation_~tmp~3#1); 49418#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50440#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50382#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50375#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 50370#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50364#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50359#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50315#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 50307#L1553-2 [2022-07-22 02:42:34,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:34,044 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2022-07-22 02:42:34,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:34,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510845160] [2022-07-22 02:42:34,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:34,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:34,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:34,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:34,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:34,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [510845160] [2022-07-22 02:42:34,076 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [510845160] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:34,076 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:34,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:42:34,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858974542] [2022-07-22 02:42:34,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:34,078 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:34,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:34,078 INFO L85 PathProgramCache]: Analyzing trace with hash -1798258821, now seen corresponding path program 1 times [2022-07-22 02:42:34,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:34,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371617263] [2022-07-22 02:42:34,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:34,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:34,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:34,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:34,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:34,131 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [371617263] [2022-07-22 02:42:34,131 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [371617263] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:34,131 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:34,131 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:34,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [163751414] [2022-07-22 02:42:34,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:34,133 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:34,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:34,133 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:34,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:34,134 INFO L87 Difference]: Start difference. First operand 8648 states and 12708 transitions. cyclomatic complexity: 4068 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:34,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:34,381 INFO L93 Difference]: Finished difference Result 16971 states and 24755 transitions. [2022-07-22 02:42:34,382 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:34,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16971 states and 24755 transitions. [2022-07-22 02:42:34,484 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16753 [2022-07-22 02:42:34,549 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16971 states to 16971 states and 24755 transitions. [2022-07-22 02:42:34,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16971 [2022-07-22 02:42:34,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16971 [2022-07-22 02:42:34,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16971 states and 24755 transitions. [2022-07-22 02:42:34,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:34,588 INFO L369 hiAutomatonCegarLoop]: Abstraction has 16971 states and 24755 transitions. [2022-07-22 02:42:34,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16971 states and 24755 transitions. [2022-07-22 02:42:34,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16971 to 16363. [2022-07-22 02:42:34,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16363 states, 16363 states have (on average 1.4605512436594756) internal successors, (23899), 16362 states have internal predecessors, (23899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:34,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16363 states to 16363 states and 23899 transitions. [2022-07-22 02:42:34,945 INFO L392 hiAutomatonCegarLoop]: Abstraction has 16363 states and 23899 transitions. [2022-07-22 02:42:34,945 INFO L374 stractBuchiCegarLoop]: Abstraction has 16363 states and 23899 transitions. [2022-07-22 02:42:34,946 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-22 02:42:34,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16363 states and 23899 transitions. [2022-07-22 02:42:35,075 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16145 [2022-07-22 02:42:35,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:35,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:35,078 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:35,078 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:35,079 INFO L752 eck$LassoCheckResult]: Stem: 75568#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 74538#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74539#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75488#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 75153#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75154#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75459#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75653#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75338#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75339#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75220#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75221#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75605#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75557#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75470#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75471#L1024 assume !(0 == ~M_E~0); 75781#L1024-2 assume !(0 == ~T1_E~0); 74876#L1029-1 assume !(0 == ~T2_E~0); 74877#L1034-1 assume !(0 == ~T3_E~0); 74988#L1039-1 assume !(0 == ~T4_E~0); 75935#L1044-1 assume !(0 == ~T5_E~0); 75238#L1049-1 assume !(0 == ~T6_E~0); 75239#L1054-1 assume !(0 == ~T7_E~0); 75495#L1059-1 assume !(0 == ~T8_E~0); 74926#L1064-1 assume !(0 == ~T9_E~0); 74927#L1069-1 assume !(0 == ~T10_E~0); 75739#L1074-1 assume !(0 == ~E_M~0); 75823#L1079-1 assume !(0 == ~E_1~0); 75784#L1084-1 assume !(0 == ~E_2~0); 75785#L1089-1 assume !(0 == ~E_3~0); 75850#L1094-1 assume !(0 == ~E_4~0); 75325#L1099-1 assume !(0 == ~E_5~0); 75326#L1104-1 assume !(0 == ~E_6~0); 75627#L1109-1 assume !(0 == ~E_7~0); 75105#L1114-1 assume !(0 == ~E_8~0); 75106#L1119-1 assume !(0 == ~E_9~0); 75169#L1124-1 assume !(0 == ~E_10~0); 74571#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74572#L502 assume !(1 == ~m_pc~0); 74773#L502-2 is_master_triggered_~__retres1~0#1 := 0; 74704#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74705#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75553#L1273 assume !(0 != activate_threads_~tmp~1#1); 75554#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76013#L521 assume !(1 == ~t1_pc~0); 75894#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74633#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74634#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 74778#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 74615#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74616#L540 assume 1 == ~t2_pc~0; 75801#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75445#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75807#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75822#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 75884#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74901#L559 assume 1 == ~t3_pc~0; 74902#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75189#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75190#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75353#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 74720#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74721#L578 assume !(1 == ~t4_pc~0); 74848#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74847#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74607#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74608#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75534#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75535#L597 assume 1 == ~t5_pc~0; 76045#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 74652#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74653#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75294#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 75472#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75473#L616 assume !(1 == ~t6_pc~0); 75492#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75491#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75970#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75384#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 75314#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75315#L635 assume 1 == ~t7_pc~0; 75538#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 74621#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75007#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75751#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 75461#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75462#L654 assume !(1 == ~t8_pc~0); 75265#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75266#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75885#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75735#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 75736#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74874#L673 assume 1 == ~t9_pc~0; 74875#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 74564#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76008#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75695#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 75636#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75637#L692 assume !(1 == ~t10_pc~0); 75574#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75573#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75474#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75329#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 75330#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75715#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 76100#L1142-2 assume !(1 == ~T1_E~0); 75697#L1147-1 assume !(1 == ~T2_E~0); 75698#L1152-1 assume !(1 == ~T3_E~0); 77180#L1157-1 assume !(1 == ~T4_E~0); 77178#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77176#L1167-1 assume !(1 == ~T6_E~0); 77174#L1172-1 assume !(1 == ~T7_E~0); 77172#L1177-1 assume !(1 == ~T8_E~0); 77170#L1182-1 assume !(1 == ~T9_E~0); 77169#L1187-1 assume !(1 == ~T10_E~0); 77138#L1192-1 assume !(1 == ~E_M~0); 77136#L1197-1 assume !(1 == ~E_1~0); 77115#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 77113#L1207-1 assume !(1 == ~E_3~0); 77090#L1212-1 assume !(1 == ~E_4~0); 77064#L1217-1 assume !(1 == ~E_5~0); 77045#L1222-1 assume !(1 == ~E_6~0); 77043#L1227-1 assume !(1 == ~E_7~0); 77041#L1232-1 assume !(1 == ~E_8~0); 77027#L1237-1 assume !(1 == ~E_9~0); 77014#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77003#L1247-1 assume { :end_inline_reset_delta_events } true; 76996#L1553-2 [2022-07-22 02:42:35,079 INFO L754 eck$LassoCheckResult]: Loop: 76996#L1553-2 assume !false; 76990#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76985#L999 assume !false; 76984#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 76983#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 76972#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 76971#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 76969#L854 assume !(0 != eval_~tmp~0#1); 76968#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76967#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76964#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 76963#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76961#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 76959#L1034-3 assume !(0 == ~T3_E~0); 76957#L1039-3 assume !(0 == ~T4_E~0); 76955#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76952#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76950#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 76948#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 76112#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 75247#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 75248#L1074-3 assume !(0 == ~E_M~0); 75632#L1079-3 assume !(0 == ~E_1~0); 75507#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 75376#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 75377#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 75299#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 75300#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 75656#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 75642#L1114-3 assume !(0 == ~E_8~0); 75643#L1119-3 assume !(0 == ~E_9~0); 76057#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76068#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75996#L502-36 assume !(1 == ~m_pc~0); 75997#L502-38 is_master_triggered_~__retres1~0#1 := 0; 83586#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83584#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 83582#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 83579#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83577#L521-36 assume 1 == ~t1_pc~0; 83573#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 83571#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83569#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 83566#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 83447#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83446#L540-36 assume 1 == ~t2_pc~0; 83445#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75008#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75009#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76071#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75352#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74500#L559-36 assume 1 == ~t3_pc~0; 74501#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 74975#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74812#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 74813#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 75517#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75818#L578-36 assume !(1 == ~t4_pc~0); 75433#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 75434#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75858#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75859#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75253#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75254#L597-36 assume 1 == ~t5_pc~0; 75505#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75965#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75412#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75413#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 75055#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75056#L616-36 assume 1 == ~t6_pc~0; 76005#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74567#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74568#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75192#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 75308#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75678#L635-36 assume !(1 == ~t7_pc~0); 75925#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 75757#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75359#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75360#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75295#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75296#L654-36 assume !(1 == ~t8_pc~0); 75930#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 75931#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76080#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76048#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 76049#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81637#L673-36 assume 1 == ~t9_pc~0; 81631#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81626#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81622#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81618#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 81614#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81609#L692-36 assume !(1 == ~t10_pc~0); 81603#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 81598#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81594#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81589#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 81584#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81578#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76703#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81568#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81564#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76695#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81557#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81551#L1167-3 assume !(1 == ~T6_E~0); 81546#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81542#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 81537#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81533#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81528#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77858#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81518#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81513#L1207-3 assume !(1 == ~E_3~0); 81504#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81472#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81464#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81455#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81445#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 81438#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 81433#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 81418#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77158#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77137#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77135#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 77133#L1572 assume !(0 == start_simulation_~tmp~3#1); 76612#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77085#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77061#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77044#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 77029#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77017#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77015#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 77004#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 76996#L1553-2 [2022-07-22 02:42:35,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:35,080 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2022-07-22 02:42:35,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:35,080 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21575955] [2022-07-22 02:42:35,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:35,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:35,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:35,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:35,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:35,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21575955] [2022-07-22 02:42:35,114 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21575955] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:35,114 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:35,115 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:35,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863991119] [2022-07-22 02:42:35,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:35,115 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:35,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:35,116 INFO L85 PathProgramCache]: Analyzing trace with hash -308419396, now seen corresponding path program 1 times [2022-07-22 02:42:35,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:35,116 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527799910] [2022-07-22 02:42:35,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:35,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:35,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:35,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:35,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:35,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [527799910] [2022-07-22 02:42:35,150 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [527799910] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:35,150 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:35,150 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:35,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096885162] [2022-07-22 02:42:35,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:35,151 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:35,152 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:35,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:35,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:35,153 INFO L87 Difference]: Start difference. First operand 16363 states and 23899 transitions. cyclomatic complexity: 7552 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:35,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:35,505 INFO L93 Difference]: Finished difference Result 39692 states and 57496 transitions. [2022-07-22 02:42:35,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:35,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39692 states and 57496 transitions. [2022-07-22 02:42:35,836 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 38803 [2022-07-22 02:42:36,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39692 states to 39692 states and 57496 transitions. [2022-07-22 02:42:36,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39692 [2022-07-22 02:42:36,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39692 [2022-07-22 02:42:36,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39692 states and 57496 transitions. [2022-07-22 02:42:36,180 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:36,180 INFO L369 hiAutomatonCegarLoop]: Abstraction has 39692 states and 57496 transitions. [2022-07-22 02:42:36,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39692 states and 57496 transitions. [2022-07-22 02:42:36,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39692 to 31057. [2022-07-22 02:42:36,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31057 states, 31057 states have (on average 1.4538751328202981) internal successors, (45153), 31056 states have internal predecessors, (45153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:36,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31057 states to 31057 states and 45153 transitions. [2022-07-22 02:42:36,810 INFO L392 hiAutomatonCegarLoop]: Abstraction has 31057 states and 45153 transitions. [2022-07-22 02:42:36,810 INFO L374 stractBuchiCegarLoop]: Abstraction has 31057 states and 45153 transitions. [2022-07-22 02:42:36,810 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-22 02:42:36,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31057 states and 45153 transitions. [2022-07-22 02:42:37,061 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30832 [2022-07-22 02:42:37,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:37,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:37,064 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:37,064 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:37,064 INFO L752 eck$LassoCheckResult]: Stem: 131591#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 131592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 130603#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 130604#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131518#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 131204#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131205#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131495#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131662#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131376#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131377#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131260#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 131261#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 131619#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 131580#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 131503#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131504#L1024 assume !(0 == ~M_E~0); 131772#L1024-2 assume !(0 == ~T1_E~0); 130932#L1029-1 assume !(0 == ~T2_E~0); 130933#L1034-1 assume !(0 == ~T3_E~0); 131044#L1039-1 assume !(0 == ~T4_E~0); 131899#L1044-1 assume !(0 == ~T5_E~0); 131283#L1049-1 assume !(0 == ~T6_E~0); 131284#L1054-1 assume !(0 == ~T7_E~0); 131525#L1059-1 assume !(0 == ~T8_E~0); 130983#L1064-1 assume !(0 == ~T9_E~0); 130984#L1069-1 assume !(0 == ~T10_E~0); 131736#L1074-1 assume !(0 == ~E_M~0); 131808#L1079-1 assume !(0 == ~E_1~0); 131774#L1084-1 assume !(0 == ~E_2~0); 131775#L1089-1 assume !(0 == ~E_3~0); 131827#L1094-1 assume !(0 == ~E_4~0); 131366#L1099-1 assume !(0 == ~E_5~0); 131367#L1104-1 assume !(0 == ~E_6~0); 131638#L1109-1 assume !(0 == ~E_7~0); 131160#L1114-1 assume !(0 == ~E_8~0); 131161#L1119-1 assume !(0 == ~E_9~0); 131215#L1124-1 assume !(0 == ~E_10~0); 130636#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130637#L502 assume !(1 == ~m_pc~0); 130834#L502-2 is_master_triggered_~__retres1~0#1 := 0; 130766#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130767#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 131575#L1273 assume !(0 != activate_threads_~tmp~1#1); 131576#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131949#L521 assume !(1 == ~t1_pc~0); 131862#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 130696#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 130697#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130840#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 130678#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130679#L540 assume !(1 == ~t2_pc~0); 131481#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131482#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131791#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131804#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 131854#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130958#L559 assume 1 == ~t3_pc~0; 130959#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 131239#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131240#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131391#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 130784#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130785#L578 assume !(1 == ~t4_pc~0); 130903#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 130902#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130672#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130673#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 131559#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131560#L597 assume 1 == ~t5_pc~0; 131967#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 130718#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130719#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131332#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 131505#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131506#L616 assume !(1 == ~t6_pc~0); 131522#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 131521#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131920#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131423#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 131357#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131358#L635 assume 1 == ~t7_pc~0; 131564#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 130686#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131064#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131745#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 131499#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 131500#L654 assume !(1 == ~t8_pc~0); 131310#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 131311#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131855#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 131732#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 131733#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130930#L673 assume 1 == ~t9_pc~0; 130931#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 130627#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131945#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131695#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 131648#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131649#L692 assume !(1 == ~t10_pc~0); 131595#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 131594#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 131509#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 131370#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 131371#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131713#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 130844#L1142-2 assume !(1 == ~T1_E~0); 130845#L1147-1 assume !(1 == ~T2_E~0); 132003#L1152-1 assume !(1 == ~T3_E~0); 132004#L1157-1 assume !(1 == ~T4_E~0); 131780#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131781#L1167-1 assume !(1 == ~T6_E~0); 131847#L1172-1 assume !(1 == ~T7_E~0); 131848#L1177-1 assume !(1 == ~T8_E~0); 131544#L1182-1 assume !(1 == ~T9_E~0); 131545#L1187-1 assume !(1 == ~T10_E~0); 131687#L1192-1 assume !(1 == ~E_M~0); 131109#L1197-1 assume !(1 == ~E_1~0); 131110#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 131486#L1207-1 assume !(1 == ~E_3~0); 131487#L1212-1 assume !(1 == ~E_4~0); 130702#L1217-1 assume !(1 == ~E_5~0); 130703#L1222-1 assume !(1 == ~E_6~0); 143061#L1227-1 assume !(1 == ~E_7~0); 131540#L1232-1 assume !(1 == ~E_8~0); 131541#L1237-1 assume !(1 == ~E_9~0); 146287#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 146285#L1247-1 assume { :end_inline_reset_delta_events } true; 146283#L1553-2 [2022-07-22 02:42:37,065 INFO L754 eck$LassoCheckResult]: Loop: 146283#L1553-2 assume !false; 146280#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 146274#L999 assume !false; 146272#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 146270#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 146258#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 146257#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 146252#L854 assume !(0 != eval_~tmp~0#1); 146253#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 147411#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 147409#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 147406#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 147404#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 147402#L1034-3 assume !(0 == ~T3_E~0); 147400#L1039-3 assume !(0 == ~T4_E~0); 147398#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 147396#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 147393#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 147391#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 147389#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 147387#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 147385#L1074-3 assume !(0 == ~E_M~0); 147383#L1079-3 assume !(0 == ~E_1~0); 147380#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 147378#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 147376#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 147374#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 147372#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 147370#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 147367#L1114-3 assume !(0 == ~E_8~0); 147365#L1119-3 assume !(0 == ~E_9~0); 147363#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 147361#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 147359#L502-36 assume !(1 == ~m_pc~0); 147357#L502-38 is_master_triggered_~__retres1~0#1 := 0; 147354#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 147352#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 147350#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 147348#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 147346#L521-36 assume 1 == ~t1_pc~0; 147342#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 147338#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 147335#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 147332#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 147330#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 147319#L540-36 assume !(1 == ~t2_pc~0); 136343#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 147082#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 147081#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 147080#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 147079#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 147078#L559-36 assume 1 == ~t3_pc~0; 147074#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 147072#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 147069#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 147067#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 147065#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 147063#L578-36 assume !(1 == ~t4_pc~0); 147060#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 147058#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 147055#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 147053#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 147051#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 147046#L597-36 assume 1 == ~t5_pc~0; 147036#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 147035#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 147034#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 147033#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 147032#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 147031#L616-36 assume !(1 == ~t6_pc~0); 147030#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 147028#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 147027#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 147026#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 147025#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 147024#L635-36 assume 1 == ~t7_pc~0; 147022#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 147021#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 147020#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 147018#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 147016#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 147014#L654-36 assume 1 == ~t8_pc~0; 147011#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 147009#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 147007#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 147005#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 147002#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 147000#L673-36 assume 1 == ~t9_pc~0; 146998#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 146995#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 146993#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 146991#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 146990#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 146988#L692-36 assume !(1 == ~t10_pc~0); 146986#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 146983#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 146981#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 146979#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 146976#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 146974#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 131507#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 146971#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 146969#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 146638#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 146967#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 146966#L1167-3 assume !(1 == ~T6_E~0); 146965#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 146964#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 146952#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 146950#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 146948#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 131250#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 146945#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 146943#L1207-3 assume !(1 == ~E_3~0); 146940#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 146938#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 146936#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 146934#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 146932#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 141510#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 146928#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 146926#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 146900#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 146898#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 146896#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 146894#L1572 assume !(0 == start_simulation_~tmp~3#1); 131116#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 146476#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 146312#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 146300#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 146296#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 146294#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 146292#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 146286#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 146283#L1553-2 [2022-07-22 02:42:37,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:37,066 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2022-07-22 02:42:37,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:37,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971014113] [2022-07-22 02:42:37,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:37,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:37,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:37,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:37,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:37,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [971014113] [2022-07-22 02:42:37,107 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [971014113] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:37,107 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:37,107 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:37,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345600761] [2022-07-22 02:42:37,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:37,108 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:37,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:37,108 INFO L85 PathProgramCache]: Analyzing trace with hash -12348548, now seen corresponding path program 1 times [2022-07-22 02:42:37,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:37,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127299403] [2022-07-22 02:42:37,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:37,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:37,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:37,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:37,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:37,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127299403] [2022-07-22 02:42:37,141 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127299403] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:37,141 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:37,142 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:37,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [739938029] [2022-07-22 02:42:37,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:37,142 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:37,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:37,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:37,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:37,143 INFO L87 Difference]: Start difference. First operand 31057 states and 45153 transitions. cyclomatic complexity: 14112 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:37,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:37,681 INFO L93 Difference]: Finished difference Result 75353 states and 108733 transitions. [2022-07-22 02:42:37,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:37,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75353 states and 108733 transitions. [2022-07-22 02:42:38,211 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 73793 [2022-07-22 02:42:38,501 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75353 states to 75353 states and 108733 transitions. [2022-07-22 02:42:38,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75353 [2022-07-22 02:42:38,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75353 [2022-07-22 02:42:38,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75353 states and 108733 transitions. [2022-07-22 02:42:38,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:38,762 INFO L369 hiAutomatonCegarLoop]: Abstraction has 75353 states and 108733 transitions. [2022-07-22 02:42:38,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75353 states and 108733 transitions. [2022-07-22 02:42:39,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75353 to 59020. [2022-07-22 02:42:39,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59020 states, 59020 states have (on average 1.44808539478143) internal successors, (85466), 59019 states have internal predecessors, (85466), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:39,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59020 states to 59020 states and 85466 transitions. [2022-07-22 02:42:39,918 INFO L392 hiAutomatonCegarLoop]: Abstraction has 59020 states and 85466 transitions. [2022-07-22 02:42:39,918 INFO L374 stractBuchiCegarLoop]: Abstraction has 59020 states and 85466 transitions. [2022-07-22 02:42:39,918 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-22 02:42:39,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59020 states and 85466 transitions. [2022-07-22 02:42:40,103 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 58780 [2022-07-22 02:42:40,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:40,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:40,106 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:40,106 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:40,107 INFO L752 eck$LassoCheckResult]: Stem: 238021#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 238022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 237022#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 237023#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 237945#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 237633#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 237634#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 237922#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 238100#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 237803#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 237804#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 237690#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 237691#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 238052#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 238010#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 237930#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 237931#L1024 assume !(0 == ~M_E~0); 238218#L1024-2 assume !(0 == ~T1_E~0); 237354#L1029-1 assume !(0 == ~T2_E~0); 237355#L1034-1 assume !(0 == ~T3_E~0); 237466#L1039-1 assume !(0 == ~T4_E~0); 238347#L1044-1 assume !(0 == ~T5_E~0); 237713#L1049-1 assume !(0 == ~T6_E~0); 237714#L1054-1 assume !(0 == ~T7_E~0); 237953#L1059-1 assume !(0 == ~T8_E~0); 237404#L1064-1 assume !(0 == ~T9_E~0); 237405#L1069-1 assume !(0 == ~T10_E~0); 238180#L1074-1 assume !(0 == ~E_M~0); 238256#L1079-1 assume !(0 == ~E_1~0); 238220#L1084-1 assume !(0 == ~E_2~0); 238221#L1089-1 assume !(0 == ~E_3~0); 238275#L1094-1 assume !(0 == ~E_4~0); 237793#L1099-1 assume !(0 == ~E_5~0); 237794#L1104-1 assume !(0 == ~E_6~0); 238072#L1109-1 assume !(0 == ~E_7~0); 237587#L1114-1 assume !(0 == ~E_8~0); 237588#L1119-1 assume !(0 == ~E_9~0); 237644#L1124-1 assume !(0 == ~E_10~0); 237055#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 237056#L502 assume !(1 == ~m_pc~0); 237253#L502-2 is_master_triggered_~__retres1~0#1 := 0; 237184#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 237185#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 238005#L1273 assume !(0 != activate_threads_~tmp~1#1); 238006#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 238398#L521 assume !(1 == ~t1_pc~0); 238311#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 237114#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 237115#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 237261#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 237096#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 237097#L540 assume !(1 == ~t2_pc~0); 237906#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 237907#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238238#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 238252#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 238302#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 237380#L559 assume !(1 == ~t3_pc~0); 237381#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 237670#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 237671#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 237818#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 237202#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237203#L578 assume !(1 == ~t4_pc~0); 237325#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 237324#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 237090#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 237091#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 237985#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 237986#L597 assume 1 == ~t5_pc~0; 238417#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 237136#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 237137#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 237760#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 237932#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 237933#L616 assume !(1 == ~t6_pc~0); 237949#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 237948#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 238371#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 237848#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 237784#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 237785#L635 assume 1 == ~t7_pc~0; 237990#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 237104#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 237485#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 238192#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 237926#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 237927#L654 assume !(1 == ~t8_pc~0); 237739#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 237740#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 238303#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 238177#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 238178#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 237352#L673 assume 1 == ~t9_pc~0; 237353#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 237046#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 238395#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 238142#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 238084#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 238085#L692 assume !(1 == ~t10_pc~0); 238025#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 238024#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 237936#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 237797#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 237798#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 238157#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 237265#L1142-2 assume !(1 == ~T1_E~0); 237266#L1147-1 assume !(1 == ~T2_E~0); 238143#L1152-1 assume !(1 == ~T3_E~0); 282051#L1157-1 assume !(1 == ~T4_E~0); 238227#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 238228#L1167-1 assume !(1 == ~T6_E~0); 238295#L1172-1 assume !(1 == ~T7_E~0); 238296#L1177-1 assume !(1 == ~T8_E~0); 237971#L1182-1 assume !(1 == ~T9_E~0); 237972#L1187-1 assume !(1 == ~T10_E~0); 238131#L1192-1 assume !(1 == ~E_M~0); 238132#L1197-1 assume !(1 == ~E_1~0); 238148#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 238149#L1207-1 assume !(1 == ~E_3~0); 237889#L1212-1 assume !(1 == ~E_4~0); 237890#L1217-1 assume !(1 == ~E_5~0); 238480#L1222-1 assume !(1 == ~E_6~0); 237885#L1227-1 assume !(1 == ~E_7~0); 237886#L1232-1 assume !(1 == ~E_8~0); 237968#L1237-1 assume !(1 == ~E_9~0); 288981#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 288979#L1247-1 assume { :end_inline_reset_delta_events } true; 288977#L1553-2 [2022-07-22 02:42:40,107 INFO L754 eck$LassoCheckResult]: Loop: 288977#L1553-2 assume !false; 288975#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 288969#L999 assume !false; 288967#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 288964#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 288952#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 288950#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 288947#L854 assume !(0 != eval_~tmp~0#1); 288948#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 295477#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 295474#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 295471#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 295468#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 295464#L1034-3 assume !(0 == ~T3_E~0); 295461#L1039-3 assume !(0 == ~T4_E~0); 295458#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 295455#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 295452#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 295449#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 295445#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 295442#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 295439#L1074-3 assume !(0 == ~E_M~0); 295436#L1079-3 assume !(0 == ~E_1~0); 295434#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 295432#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 295417#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 295416#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 295392#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 295389#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 295377#L1114-3 assume !(0 == ~E_8~0); 295375#L1119-3 assume !(0 == ~E_9~0); 295373#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 295370#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295364#L502-36 assume !(1 == ~m_pc~0); 295183#L502-38 is_master_triggered_~__retres1~0#1 := 0; 295182#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 295179#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 295175#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 295172#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 237695#L521-36 assume !(1 == ~t1_pc~0); 237697#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 237708#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 237878#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 237919#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 238184#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238185#L540-36 assume !(1 == ~t2_pc~0); 291259#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 291257#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 291256#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 291254#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 291252#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 291250#L559-36 assume !(1 == ~t3_pc~0); 245632#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 291247#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 291244#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 291242#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 291240#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 291238#L578-36 assume 1 == ~t4_pc~0; 291236#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 291233#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 291230#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 291228#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 291226#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 291224#L597-36 assume 1 == ~t5_pc~0; 291221#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 291219#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 291216#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 291214#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 291212#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 291210#L616-36 assume 1 == ~t6_pc~0; 291207#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 291205#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 291202#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 291200#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 291198#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 291196#L635-36 assume 1 == ~t7_pc~0; 291193#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 291191#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 291188#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 291186#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 291184#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 291182#L654-36 assume 1 == ~t8_pc~0; 290966#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 290962#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 290960#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 290958#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 290954#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 290950#L673-36 assume !(1 == ~t9_pc~0); 290944#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 290942#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 290940#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 290938#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 290936#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 290934#L692-36 assume !(1 == ~t10_pc~0); 290932#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 290929#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 290927#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 290926#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 290924#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 290922#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 284407#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 290824#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 290641#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 290632#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 290628#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 290623#L1167-3 assume !(1 == ~T6_E~0); 290618#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 290613#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 290607#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 290601#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 290596#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 285553#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 290587#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 290582#L1207-3 assume !(1 == ~E_3~0); 290576#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 290571#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 290566#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 290561#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 290556#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 290374#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 290547#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 290545#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 290508#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 290501#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 290494#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 290488#L1572 assume !(0 == start_simulation_~tmp~3#1); 290485#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 290474#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 290460#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 290456#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 290451#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 290445#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 290440#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 288980#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 288977#L1553-2 [2022-07-22 02:42:40,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:40,108 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2022-07-22 02:42:40,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:40,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935112033] [2022-07-22 02:42:40,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:40,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:40,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:40,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:40,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:40,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935112033] [2022-07-22 02:42:40,148 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1935112033] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:40,149 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:40,149 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:42:40,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294129857] [2022-07-22 02:42:40,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:40,149 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:40,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:40,150 INFO L85 PathProgramCache]: Analyzing trace with hash -1968343939, now seen corresponding path program 1 times [2022-07-22 02:42:40,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:40,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581051616] [2022-07-22 02:42:40,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:40,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:40,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:40,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:40,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:40,180 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581051616] [2022-07-22 02:42:40,180 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581051616] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:40,180 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:40,181 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:40,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689666248] [2022-07-22 02:42:40,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:40,181 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:40,181 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:40,182 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-22 02:42:40,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-22 02:42:40,182 INFO L87 Difference]: Start difference. First operand 59020 states and 85466 transitions. cyclomatic complexity: 26462 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:41,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:41,128 INFO L93 Difference]: Finished difference Result 154975 states and 224919 transitions. [2022-07-22 02:42:41,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-22 02:42:41,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154975 states and 224919 transitions. [2022-07-22 02:42:41,973 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 154392 [2022-07-22 02:42:42,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154975 states to 154975 states and 224919 transitions. [2022-07-22 02:42:42,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 154975 [2022-07-22 02:42:42,577 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 154975 [2022-07-22 02:42:42,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154975 states and 224919 transitions. [2022-07-22 02:42:42,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:42,661 INFO L369 hiAutomatonCegarLoop]: Abstraction has 154975 states and 224919 transitions. [2022-07-22 02:42:42,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154975 states and 224919 transitions. [2022-07-22 02:42:43,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154975 to 60871. [2022-07-22 02:42:43,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60871 states, 60871 states have (on average 1.4344597591628196) internal successors, (87317), 60870 states have internal predecessors, (87317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:43,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60871 states to 60871 states and 87317 transitions. [2022-07-22 02:42:43,946 INFO L392 hiAutomatonCegarLoop]: Abstraction has 60871 states and 87317 transitions. [2022-07-22 02:42:43,946 INFO L374 stractBuchiCegarLoop]: Abstraction has 60871 states and 87317 transitions. [2022-07-22 02:42:43,947 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-22 02:42:43,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60871 states and 87317 transitions. [2022-07-22 02:42:44,392 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 60628 [2022-07-22 02:42:44,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:44,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:44,394 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,394 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,395 INFO L752 eck$LassoCheckResult]: Stem: 452045#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 452046#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 451030#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 451031#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 451971#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 451648#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 451649#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 451945#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 452125#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 451821#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 451822#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 451705#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 451706#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 452074#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 452033#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 451954#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 451955#L1024 assume !(0 == ~M_E~0); 452241#L1024-2 assume !(0 == ~T1_E~0); 451363#L1029-1 assume !(0 == ~T2_E~0); 451364#L1034-1 assume !(0 == ~T3_E~0); 451476#L1039-1 assume !(0 == ~T4_E~0); 452377#L1044-1 assume !(0 == ~T5_E~0); 451728#L1049-1 assume !(0 == ~T6_E~0); 451729#L1054-1 assume !(0 == ~T7_E~0); 451979#L1059-1 assume !(0 == ~T8_E~0); 451414#L1064-1 assume !(0 == ~T9_E~0); 451415#L1069-1 assume !(0 == ~T10_E~0); 452205#L1074-1 assume !(0 == ~E_M~0); 452281#L1079-1 assume !(0 == ~E_1~0); 452246#L1084-1 assume !(0 == ~E_2~0); 452247#L1089-1 assume !(0 == ~E_3~0); 452304#L1094-1 assume !(0 == ~E_4~0); 451810#L1099-1 assume !(0 == ~E_5~0); 451811#L1104-1 assume !(0 == ~E_6~0); 452096#L1109-1 assume !(0 == ~E_7~0); 451596#L1114-1 assume !(0 == ~E_8~0); 451597#L1119-1 assume !(0 == ~E_9~0); 451659#L1124-1 assume !(0 == ~E_10~0); 451063#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 451064#L502 assume !(1 == ~m_pc~0); 451262#L502-2 is_master_triggered_~__retres1~0#1 := 0; 451192#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 451193#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 452028#L1273 assume !(0 != activate_threads_~tmp~1#1); 452029#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 452442#L521 assume !(1 == ~t1_pc~0); 452338#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 451122#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 451123#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 451270#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 451104#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 451105#L540 assume !(1 == ~t2_pc~0); 451929#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 451930#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 452264#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 452277#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 452331#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 451390#L559 assume !(1 == ~t3_pc~0); 451391#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 451684#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 451685#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 451839#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 451210#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 451211#L578 assume !(1 == ~t4_pc~0); 451334#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 452209#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 452240#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 452423#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 452011#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 452012#L597 assume 1 == ~t5_pc~0; 452467#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 451144#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 451145#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 451778#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 451956#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 451957#L616 assume !(1 == ~t6_pc~0); 451975#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 451974#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 452411#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 451868#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 451802#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 451803#L635 assume 1 == ~t7_pc~0; 452016#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 451112#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 451497#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 452215#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 451950#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 451951#L654 assume !(1 == ~t8_pc~0); 451755#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 451756#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 452332#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 452202#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 452203#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 451361#L673 assume 1 == ~t9_pc~0; 451362#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 451054#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 452438#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 452166#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 452107#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 452108#L692 assume !(1 == ~t10_pc~0); 452049#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 452048#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 451960#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 451814#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 451815#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 452180#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 451274#L1142-2 assume !(1 == ~T1_E~0); 451275#L1147-1 assume !(1 == ~T2_E~0); 452167#L1152-1 assume !(1 == ~T3_E~0); 456851#L1157-1 assume !(1 == ~T4_E~0); 456849#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 456847#L1167-1 assume !(1 == ~T6_E~0); 456845#L1172-1 assume !(1 == ~T7_E~0); 456801#L1177-1 assume !(1 == ~T8_E~0); 456799#L1182-1 assume !(1 == ~T9_E~0); 456797#L1187-1 assume !(1 == ~T10_E~0); 456794#L1192-1 assume !(1 == ~E_M~0); 456792#L1197-1 assume !(1 == ~E_1~0); 456790#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 456788#L1207-1 assume !(1 == ~E_3~0); 456786#L1212-1 assume !(1 == ~E_4~0); 456784#L1217-1 assume !(1 == ~E_5~0); 456781#L1222-1 assume !(1 == ~E_6~0); 456779#L1227-1 assume !(1 == ~E_7~0); 456777#L1232-1 assume !(1 == ~E_8~0); 456773#L1237-1 assume !(1 == ~E_9~0); 456771#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 456539#L1247-1 assume { :end_inline_reset_delta_events } true; 456538#L1553-2 [2022-07-22 02:42:44,395 INFO L754 eck$LassoCheckResult]: Loop: 456538#L1553-2 assume !false; 456535#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 456529#L999 assume !false; 456527#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 456525#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 456513#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 456511#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 456507#L854 assume !(0 != eval_~tmp~0#1); 456508#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 478837#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 478834#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 478832#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 478830#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 478828#L1034-3 assume !(0 == ~T3_E~0); 478826#L1039-3 assume !(0 == ~T4_E~0); 478824#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 478821#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 478819#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 478817#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 478815#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 478813#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 478811#L1074-3 assume !(0 == ~E_M~0); 478808#L1079-3 assume !(0 == ~E_1~0); 478806#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 478804#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 478802#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 478800#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 478798#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 478795#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 478793#L1114-3 assume !(0 == ~E_8~0); 478791#L1119-3 assume !(0 == ~E_9~0); 475757#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 470670#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 470669#L502-36 assume !(1 == ~m_pc~0); 470667#L502-38 is_master_triggered_~__retres1~0#1 := 0; 470665#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 470663#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 470661#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 470659#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 470657#L521-36 assume !(1 == ~t1_pc~0); 470655#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 470651#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 470649#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 470647#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 470645#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 470643#L540-36 assume !(1 == ~t2_pc~0); 464741#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 470638#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 470636#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 470634#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 470632#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 458565#L559-36 assume !(1 == ~t3_pc~0); 458564#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 458563#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 458562#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 458561#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 458560#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 458559#L578-36 assume !(1 == ~t4_pc~0); 458558#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 458556#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 458554#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 458552#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 458549#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 458547#L597-36 assume !(1 == ~t5_pc~0); 458544#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 458541#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 458539#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 458537#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 458535#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 458533#L616-36 assume !(1 == ~t6_pc~0); 458530#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 458527#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 458525#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 458523#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 458521#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 458519#L635-36 assume !(1 == ~t7_pc~0); 458516#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 458513#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 458511#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 458509#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 458507#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 458505#L654-36 assume !(1 == ~t8_pc~0); 458502#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 458499#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 458497#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 458495#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 458493#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 458491#L673-36 assume !(1 == ~t9_pc~0); 458487#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 458485#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 458483#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 458481#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 458479#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 458477#L692-36 assume !(1 == ~t10_pc~0); 458474#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 458471#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 458469#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 458467#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 458465#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 458463#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 458459#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 458457#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 458455#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 458451#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 458449#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 458447#L1167-3 assume !(1 == ~T6_E~0); 458445#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 458443#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 458441#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 458439#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 458437#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 458433#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 458431#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 458429#L1207-3 assume !(1 == ~E_3~0); 458427#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 458425#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 458423#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 458421#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 458419#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 458415#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 458413#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 458412#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 458361#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 458359#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 458356#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 458354#L1572 assume !(0 == start_simulation_~tmp~3#1); 458351#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 456562#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 456550#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 456548#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 456546#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 456544#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 456542#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 456540#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 456538#L1553-2 [2022-07-22 02:42:44,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,396 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2022-07-22 02:42:44,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313121719] [2022-07-22 02:42:44,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,427 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313121719] [2022-07-22 02:42:44,427 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [313121719] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,427 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:42:44,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867659973] [2022-07-22 02:42:44,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,428 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:44,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,429 INFO L85 PathProgramCache]: Analyzing trace with hash -14553404, now seen corresponding path program 1 times [2022-07-22 02:42:44,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618733704] [2022-07-22 02:42:44,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618733704] [2022-07-22 02:42:44,457 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1618733704] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,458 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:44,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789448470] [2022-07-22 02:42:44,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,458 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:44,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:44,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:44,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:44,459 INFO L87 Difference]: Start difference. First operand 60871 states and 87317 transitions. cyclomatic complexity: 26462 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:44,871 INFO L93 Difference]: Finished difference Result 115762 states and 165430 transitions. [2022-07-22 02:42:44,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:44,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115762 states and 165430 transitions. [2022-07-22 02:42:45,712 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 115360 [2022-07-22 02:42:46,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115762 states to 115762 states and 165430 transitions. [2022-07-22 02:42:46,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115762 [2022-07-22 02:42:46,085 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115762 [2022-07-22 02:42:46,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115762 states and 165430 transitions. [2022-07-22 02:42:46,150 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:46,150 INFO L369 hiAutomatonCegarLoop]: Abstraction has 115762 states and 165430 transitions. [2022-07-22 02:42:46,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115762 states and 165430 transitions. [2022-07-22 02:42:47,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115762 to 115634. [2022-07-22 02:42:47,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115634 states, 115634 states have (on average 1.4295276475777021) internal successors, (165302), 115633 states have internal predecessors, (165302), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:47,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115634 states to 115634 states and 165302 transitions. [2022-07-22 02:42:47,666 INFO L392 hiAutomatonCegarLoop]: Abstraction has 115634 states and 165302 transitions. [2022-07-22 02:42:47,666 INFO L374 stractBuchiCegarLoop]: Abstraction has 115634 states and 165302 transitions. [2022-07-22 02:42:47,666 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-22 02:42:47,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115634 states and 165302 transitions. [2022-07-22 02:42:48,377 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 115232 [2022-07-22 02:42:48,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:48,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:48,379 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:48,379 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:48,379 INFO L752 eck$LassoCheckResult]: Stem: 628688#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 628689#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 627669#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 627670#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 628613#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 628275#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 628276#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 628588#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 628780#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 628460#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 628461#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 628339#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 628340#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 628730#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 628674#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 628595#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 628596#L1024 assume !(0 == ~M_E~0); 628913#L1024-2 assume !(0 == ~T1_E~0); 627999#L1029-1 assume !(0 == ~T2_E~0); 628000#L1034-1 assume !(0 == ~T3_E~0); 628112#L1039-1 assume !(0 == ~T4_E~0); 629064#L1044-1 assume !(0 == ~T5_E~0); 628358#L1049-1 assume !(0 == ~T6_E~0); 628359#L1054-1 assume !(0 == ~T7_E~0); 628620#L1059-1 assume !(0 == ~T8_E~0); 628050#L1064-1 assume !(0 == ~T9_E~0); 628051#L1069-1 assume !(0 == ~T10_E~0); 628872#L1074-1 assume !(0 == ~E_M~0); 628952#L1079-1 assume !(0 == ~E_1~0); 628915#L1084-1 assume !(0 == ~E_2~0); 628916#L1089-1 assume !(0 == ~E_3~0); 628975#L1094-1 assume !(0 == ~E_4~0); 628448#L1099-1 assume !(0 == ~E_5~0); 628449#L1104-1 assume !(0 == ~E_6~0); 628752#L1109-1 assume !(0 == ~E_7~0); 628228#L1114-1 assume !(0 == ~E_8~0); 628229#L1119-1 assume !(0 == ~E_9~0); 628292#L1124-1 assume !(0 == ~E_10~0); 627702#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 627703#L502 assume !(1 == ~m_pc~0); 627900#L502-2 is_master_triggered_~__retres1~0#1 := 0; 627832#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 627833#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 628670#L1273 assume !(0 != activate_threads_~tmp~1#1); 628671#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 629142#L521 assume !(1 == ~t1_pc~0); 629020#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 627763#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 627764#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 627905#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 627745#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 627746#L540 assume !(1 == ~t2_pc~0); 628569#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 628570#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 628934#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 628951#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 629009#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 628025#L559 assume !(1 == ~t3_pc~0); 628026#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 628311#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 628312#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 628475#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 627848#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 627849#L578 assume !(1 == ~t4_pc~0); 627972#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 628877#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 629276#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 629111#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 628654#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 628655#L597 assume !(1 == ~t5_pc~0); 628607#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 627782#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 627783#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 628416#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 628597#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 628598#L616 assume !(1 == ~t6_pc~0); 628617#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 628616#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 629097#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 628505#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 628437#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 628438#L635 assume 1 == ~t7_pc~0; 628658#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 627751#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 628133#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 628884#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 628590#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 628591#L654 assume !(1 == ~t8_pc~0); 628386#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 628387#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 629010#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 628867#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 628868#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 627997#L673 assume 1 == ~t9_pc~0; 627998#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 627695#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 629133#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 628822#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 628762#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 628763#L692 assume !(1 == ~t10_pc~0); 628699#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 628698#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 628599#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 628452#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 628453#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 628844#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 627908#L1142-2 assume !(1 == ~T1_E~0); 627909#L1147-1 assume !(1 == ~T2_E~0); 628825#L1152-1 assume !(1 == ~T3_E~0); 629250#L1157-1 assume !(1 == ~T4_E~0); 708852#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 628478#L1167-1 assume !(1 == ~T6_E~0); 628479#L1172-1 assume !(1 == ~T7_E~0); 629001#L1177-1 assume !(1 == ~T8_E~0); 708844#L1182-1 assume !(1 == ~T9_E~0); 708842#L1187-1 assume !(1 == ~T10_E~0); 628812#L1192-1 assume !(1 == ~E_M~0); 628181#L1197-1 assume !(1 == ~E_1~0); 628182#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 628574#L1207-1 assume !(1 == ~E_3~0); 628552#L1212-1 assume !(1 == ~E_4~0); 627767#L1217-1 assume !(1 == ~E_5~0); 627768#L1222-1 assume !(1 == ~E_6~0); 628548#L1227-1 assume !(1 == ~E_7~0); 628549#L1232-1 assume !(1 == ~E_8~0); 628634#L1237-1 assume !(1 == ~E_9~0); 716700#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 628618#L1247-1 assume { :end_inline_reset_delta_events } true; 628619#L1553-2 [2022-07-22 02:42:48,379 INFO L754 eck$LassoCheckResult]: Loop: 628619#L1553-2 assume !false; 720337#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 721700#L999 assume !false; 721699#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 721698#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 721687#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 721686#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 721685#L854 assume !(0 != eval_~tmp~0#1); 717821#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 717819#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 717817#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 717815#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 717813#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 717810#L1034-3 assume !(0 == ~T3_E~0); 717808#L1039-3 assume !(0 == ~T4_E~0); 717806#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 717803#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 717800#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 717798#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 717796#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 717794#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 717759#L1074-3 assume !(0 == ~E_M~0); 717746#L1079-3 assume !(0 == ~E_1~0); 717732#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 717721#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 717715#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 717658#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 717651#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 717644#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 717636#L1114-3 assume !(0 == ~E_8~0); 717632#L1119-3 assume !(0 == ~E_9~0); 717628#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 717623#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 717616#L502-36 assume !(1 == ~m_pc~0); 717611#L502-38 is_master_triggered_~__retres1~0#1 := 0; 717605#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 717586#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 717580#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 717542#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 717536#L521-36 assume !(1 == ~t1_pc~0); 717530#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 717522#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 717515#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 717509#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 717504#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 717500#L540-36 assume !(1 == ~t2_pc~0); 717499#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 717498#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 717497#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 717496#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 717495#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 717494#L559-36 assume !(1 == ~t3_pc~0); 630032#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 717493#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 717492#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 717491#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 717490#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 717489#L578-36 assume 1 == ~t4_pc~0; 717487#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 717485#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 717483#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 717481#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 717480#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 717479#L597-36 assume !(1 == ~t5_pc~0); 717478#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 717477#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 717476#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 717475#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 717474#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 717473#L616-36 assume 1 == ~t6_pc~0; 717471#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 717470#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 717469#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 717468#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 717467#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 717466#L635-36 assume 1 == ~t7_pc~0; 717464#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 717463#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 717462#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 717461#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 717460#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 717459#L654-36 assume !(1 == ~t8_pc~0); 717458#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 717456#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 717455#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 717454#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 717453#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 717452#L673-36 assume !(1 == ~t9_pc~0); 717450#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 717448#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 717446#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 717444#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 717442#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 717441#L692-36 assume 1 == ~t10_pc~0; 717438#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 717436#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 717434#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 717432#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 717430#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 717428#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 687625#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 717425#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 717423#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 687617#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 717420#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 717418#L1167-3 assume !(1 == ~T6_E~0); 717416#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 717414#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 717412#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 717410#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 717408#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 717024#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 717405#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 717403#L1207-3 assume !(1 == ~E_3~0); 717401#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 717399#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 717397#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 717395#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 717393#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 711357#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 717390#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 717387#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 717374#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 717372#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 717370#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 628610#L1572 assume !(0 == start_simulation_~tmp~3#1); 628611#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 720965#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 720951#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 720952#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 720945#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 720946#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 720939#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 720940#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 628619#L1553-2 [2022-07-22 02:42:48,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:48,380 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2022-07-22 02:42:48,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:48,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [945849706] [2022-07-22 02:42:48,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:48,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:48,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:48,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:48,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:48,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [945849706] [2022-07-22 02:42:48,411 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [945849706] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:48,411 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:48,411 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:48,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889238811] [2022-07-22 02:42:48,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:48,412 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:48,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:48,412 INFO L85 PathProgramCache]: Analyzing trace with hash 582698366, now seen corresponding path program 1 times [2022-07-22 02:42:48,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:48,413 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844064403] [2022-07-22 02:42:48,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:48,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:48,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:48,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:48,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:48,439 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1844064403] [2022-07-22 02:42:48,439 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1844064403] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:48,439 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:48,439 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:48,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474724431] [2022-07-22 02:42:48,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:48,440 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:48,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:48,441 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:48,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:48,441 INFO L87 Difference]: Start difference. First operand 115634 states and 165302 transitions. cyclomatic complexity: 49700 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:50,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:50,093 INFO L93 Difference]: Finished difference Result 282901 states and 401407 transitions. [2022-07-22 02:42:50,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:50,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 282901 states and 401407 transitions. [2022-07-22 02:42:51,222 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 276836 [2022-07-22 02:42:52,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 282901 states to 282901 states and 401407 transitions. [2022-07-22 02:42:52,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282901 [2022-07-22 02:42:52,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282901 [2022-07-22 02:42:52,584 INFO L73 IsDeterministic]: Start isDeterministic. Operand 282901 states and 401407 transitions. [2022-07-22 02:42:52,714 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:52,714 INFO L369 hiAutomatonCegarLoop]: Abstraction has 282901 states and 401407 transitions. [2022-07-22 02:42:52,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282901 states and 401407 transitions. [2022-07-22 02:42:55,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282901 to 224449. [2022-07-22 02:42:55,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224449 states, 224449 states have (on average 1.4233032893886808) internal successors, (319459), 224448 states have internal predecessors, (319459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:56,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224449 states to 224449 states and 319459 transitions. [2022-07-22 02:42:56,050 INFO L392 hiAutomatonCegarLoop]: Abstraction has 224449 states and 319459 transitions. [2022-07-22 02:42:56,050 INFO L374 stractBuchiCegarLoop]: Abstraction has 224449 states and 319459 transitions. [2022-07-22 02:42:56,050 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-22 02:42:56,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224449 states and 319459 transitions. [2022-07-22 02:42:57,341 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 223856 [2022-07-22 02:42:57,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:57,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:57,343 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:57,343 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:57,344 INFO L752 eck$LassoCheckResult]: Stem: 1027251#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1027252#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1026215#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1026216#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1027167#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 1026827#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1026828#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1027139#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1027337#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1027009#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1027010#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1026886#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1026887#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1027283#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1027239#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1027150#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1027151#L1024 assume !(0 == ~M_E~0); 1027463#L1024-2 assume !(0 == ~T1_E~0); 1026547#L1029-1 assume !(0 == ~T2_E~0); 1026548#L1034-1 assume !(0 == ~T3_E~0); 1026661#L1039-1 assume !(0 == ~T4_E~0); 1027627#L1044-1 assume !(0 == ~T5_E~0); 1026910#L1049-1 assume !(0 == ~T6_E~0); 1026911#L1054-1 assume !(0 == ~T7_E~0); 1027178#L1059-1 assume !(0 == ~T8_E~0); 1026598#L1064-1 assume !(0 == ~T9_E~0); 1026599#L1069-1 assume !(0 == ~T10_E~0); 1027424#L1074-1 assume !(0 == ~E_M~0); 1027509#L1079-1 assume !(0 == ~E_1~0); 1027465#L1084-1 assume !(0 == ~E_2~0); 1027466#L1089-1 assume !(0 == ~E_3~0); 1027537#L1094-1 assume !(0 == ~E_4~0); 1026997#L1099-1 assume !(0 == ~E_5~0); 1026998#L1104-1 assume !(0 == ~E_6~0); 1027306#L1109-1 assume !(0 == ~E_7~0); 1026779#L1114-1 assume !(0 == ~E_8~0); 1026780#L1119-1 assume !(0 == ~E_9~0); 1026838#L1124-1 assume !(0 == ~E_10~0); 1026248#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1026249#L502 assume !(1 == ~m_pc~0); 1026445#L502-2 is_master_triggered_~__retres1~0#1 := 0; 1026378#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1026379#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1027233#L1273 assume !(0 != activate_threads_~tmp~1#1); 1027234#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1027708#L521 assume !(1 == ~t1_pc~0); 1027579#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1026307#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1026308#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1026451#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 1026289#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1026290#L540 assume !(1 == ~t2_pc~0); 1027124#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1027125#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1027487#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1027505#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 1027570#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1026573#L559 assume !(1 == ~t3_pc~0); 1026574#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1026862#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1026863#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1027027#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 1026396#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1026397#L578 assume !(1 == ~t4_pc~0); 1026515#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1027428#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1027845#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1027683#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 1027216#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1027217#L597 assume !(1 == ~t5_pc~0); 1027161#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1026328#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1026329#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1026961#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 1027152#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1027153#L616 assume !(1 == ~t6_pc~0); 1027173#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1027172#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1027663#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1027060#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 1026989#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1026990#L635 assume !(1 == ~t7_pc~0); 1026296#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1026297#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1026682#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1027435#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 1027144#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1027145#L654 assume !(1 == ~t8_pc~0); 1026938#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1026939#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1027571#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1027420#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 1027421#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1026545#L673 assume 1 == ~t9_pc~0; 1026546#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1026239#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1027704#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1027382#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 1027319#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1027320#L692 assume !(1 == ~t10_pc~0); 1027255#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1027254#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1027156#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1027002#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 1027003#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1027399#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 1026455#L1142-2 assume !(1 == ~T1_E~0); 1026456#L1147-1 assume !(1 == ~T2_E~0); 1027815#L1152-1 assume !(1 == ~T3_E~0); 1027816#L1157-1 assume !(1 == ~T4_E~0); 1027475#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1027476#L1167-1 assume !(1 == ~T6_E~0); 1027560#L1172-1 assume !(1 == ~T7_E~0); 1027561#L1177-1 assume !(1 == ~T8_E~0); 1027198#L1182-1 assume !(1 == ~T9_E~0); 1027199#L1187-1 assume !(1 == ~T10_E~0); 1027370#L1192-1 assume !(1 == ~E_M~0); 1027371#L1197-1 assume !(1 == ~E_1~0); 1118165#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1118164#L1207-1 assume !(1 == ~E_3~0); 1118163#L1212-1 assume !(1 == ~E_4~0); 1118162#L1217-1 assume !(1 == ~E_5~0); 1118161#L1222-1 assume !(1 == ~E_6~0); 1118160#L1227-1 assume !(1 == ~E_7~0); 1118159#L1232-1 assume !(1 == ~E_8~0); 1027195#L1237-1 assume !(1 == ~E_9~0); 1118158#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1118156#L1247-1 assume { :end_inline_reset_delta_events } true; 1118153#L1553-2 [2022-07-22 02:42:57,344 INFO L754 eck$LassoCheckResult]: Loop: 1118153#L1553-2 assume !false; 1118151#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1118145#L999 assume !false; 1118143#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1118141#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1118129#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1118128#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1118125#L854 assume !(0 != eval_~tmp~0#1); 1118126#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1133877#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1133873#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1133869#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1133865#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1133861#L1034-3 assume !(0 == ~T3_E~0); 1133857#L1039-3 assume !(0 == ~T4_E~0); 1133853#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1133849#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1133842#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1133838#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1133834#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1133830#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1133821#L1074-3 assume !(0 == ~E_M~0); 1133819#L1079-3 assume !(0 == ~E_1~0); 1133816#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1133814#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1133812#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1133810#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1133808#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1133807#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1133806#L1114-3 assume !(0 == ~E_8~0); 1133804#L1119-3 assume !(0 == ~E_9~0); 1133802#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1133800#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1133798#L502-36 assume !(1 == ~m_pc~0); 1133796#L502-38 is_master_triggered_~__retres1~0#1 := 0; 1133794#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1133792#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1133789#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1133787#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1133785#L521-36 assume !(1 == ~t1_pc~0); 1133783#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1133780#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1133779#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1133778#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1133776#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1133774#L540-36 assume !(1 == ~t2_pc~0); 1133479#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1133771#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1133769#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1133767#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1133765#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1118403#L559-36 assume !(1 == ~t3_pc~0); 1118401#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1118399#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1118397#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1118395#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1118393#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1118391#L578-36 assume !(1 == ~t4_pc~0); 1118387#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1118385#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1118382#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1118380#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 1118377#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1118375#L597-36 assume !(1 == ~t5_pc~0); 1118373#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1118371#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1118370#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1118368#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 1118366#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1118364#L616-36 assume 1 == ~t6_pc~0; 1118361#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1118359#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1118358#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1118356#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1118354#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1118352#L635-36 assume !(1 == ~t7_pc~0); 1080581#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1118347#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1118345#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1118343#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1118341#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1118338#L654-36 assume !(1 == ~t8_pc~0); 1118336#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1118333#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1118331#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1118329#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1118327#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1118325#L673-36 assume 1 == ~t9_pc~0; 1118323#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1118320#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1118317#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1118315#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1118313#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1118311#L692-36 assume !(1 == ~t10_pc~0); 1118309#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1118306#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1118305#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1118303#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1118301#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1118299#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1093821#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1118294#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1118291#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1118287#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1118285#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1118283#L1167-3 assume !(1 == ~T6_E~0); 1118281#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1118279#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1118276#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1118274#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1118272#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1118240#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1118269#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1118267#L1207-3 assume !(1 == ~E_3~0); 1118264#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1118262#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1118260#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1118258#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1118256#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1118252#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1118250#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1118248#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1118226#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1118224#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1118222#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1118220#L1572 assume !(0 == start_simulation_~tmp~3#1); 1118217#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1118185#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1118174#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1118172#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1118170#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1118168#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1118166#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1118157#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 1118153#L1553-2 [2022-07-22 02:42:57,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:57,344 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2022-07-22 02:42:57,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:57,345 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977412751] [2022-07-22 02:42:57,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:57,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:57,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:57,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:57,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:57,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977412751] [2022-07-22 02:42:57,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [977412751] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:57,378 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:57,378 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:57,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160141141] [2022-07-22 02:42:57,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:57,379 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:57,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:57,380 INFO L85 PathProgramCache]: Analyzing trace with hash 1501245954, now seen corresponding path program 1 times [2022-07-22 02:42:57,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:57,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670448593] [2022-07-22 02:42:57,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:57,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:57,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:57,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:57,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:57,414 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670448593] [2022-07-22 02:42:57,414 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670448593] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:57,414 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:57,414 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:57,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2133602458] [2022-07-22 02:42:57,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:57,415 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:57,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:57,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:57,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:57,416 INFO L87 Difference]: Start difference. First operand 224449 states and 319459 transitions. cyclomatic complexity: 95042 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:59,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:59,944 INFO L93 Difference]: Finished difference Result 534336 states and 755904 transitions. [2022-07-22 02:42:59,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:59,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 534336 states and 755904 transitions. [2022-07-22 02:43:03,330 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 522480 [2022-07-22 02:43:05,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 534336 states to 534336 states and 755904 transitions. [2022-07-22 02:43:05,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 534336 [2022-07-22 02:43:05,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 534336 [2022-07-22 02:43:05,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 534336 states and 755904 transitions. [2022-07-22 02:43:05,673 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:05,673 INFO L369 hiAutomatonCegarLoop]: Abstraction has 534336 states and 755904 transitions. [2022-07-22 02:43:05,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534336 states and 755904 transitions. [2022-07-22 02:43:10,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534336 to 425552. [2022-07-22 02:43:11,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425552 states, 425552 states have (on average 1.4192954092566832) internal successors, (603984), 425551 states have internal predecessors, (603984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:13,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425552 states to 425552 states and 603984 transitions. [2022-07-22 02:43:13,238 INFO L392 hiAutomatonCegarLoop]: Abstraction has 425552 states and 603984 transitions. [2022-07-22 02:43:13,256 INFO L374 stractBuchiCegarLoop]: Abstraction has 425552 states and 603984 transitions. [2022-07-22 02:43:13,256 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-22 02:43:13,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425552 states and 603984 transitions. [2022-07-22 02:43:14,466 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 424576 [2022-07-22 02:43:14,467 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:14,467 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:14,470 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:14,470 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:14,470 INFO L752 eck$LassoCheckResult]: Stem: 1786037#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1786038#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1785008#L1516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1785009#L712 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1785954#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 1785617#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1785618#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1785926#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1786137#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1785796#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1785797#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1785674#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1785675#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1786084#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1786021#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1785934#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1785935#L1024 assume !(0 == ~M_E~0); 1786271#L1024-2 assume !(0 == ~T1_E~0); 1785339#L1029-1 assume !(0 == ~T2_E~0); 1785340#L1034-1 assume !(0 == ~T3_E~0); 1785449#L1039-1 assume !(0 == ~T4_E~0); 1786443#L1044-1 assume !(0 == ~T5_E~0); 1785697#L1049-1 assume !(0 == ~T6_E~0); 1785698#L1054-1 assume !(0 == ~T7_E~0); 1785962#L1059-1 assume !(0 == ~T8_E~0); 1785390#L1064-1 assume !(0 == ~T9_E~0); 1785391#L1069-1 assume !(0 == ~T10_E~0); 1786229#L1074-1 assume !(0 == ~E_M~0); 1786315#L1079-1 assume !(0 == ~E_1~0); 1786273#L1084-1 assume !(0 == ~E_2~0); 1786274#L1089-1 assume !(0 == ~E_3~0); 1786341#L1094-1 assume !(0 == ~E_4~0); 1785786#L1099-1 assume !(0 == ~E_5~0); 1785787#L1104-1 assume !(0 == ~E_6~0); 1786108#L1109-1 assume !(0 == ~E_7~0); 1785569#L1114-1 assume !(0 == ~E_8~0); 1785570#L1119-1 assume !(0 == ~E_9~0); 1785629#L1124-1 assume !(0 == ~E_10~0); 1785041#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1785042#L502 assume !(1 == ~m_pc~0); 1785240#L502-2 is_master_triggered_~__retres1~0#1 := 0; 1785171#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1785172#L514 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1786016#L1273 assume !(0 != activate_threads_~tmp~1#1); 1786017#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1786523#L521 assume !(1 == ~t1_pc~0); 1786393#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1785101#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1785102#L533 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1785246#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 1785082#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1785083#L540 assume !(1 == ~t2_pc~0); 1785909#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1785910#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1786296#L552 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1786311#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 1786382#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1785366#L559 assume !(1 == ~t3_pc~0); 1785367#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1785652#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1785653#L571 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1785813#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 1785189#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1785190#L578 assume !(1 == ~t4_pc~0); 1785310#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1786236#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1786660#L590 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1786494#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 1785998#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1785999#L597 assume !(1 == ~t5_pc~0); 1785948#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1785123#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1785124#L609 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1785747#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 1785936#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1785937#L616 assume !(1 == ~t6_pc~0); 1785958#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1785957#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1786480#L628 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1785845#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 1785776#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1785777#L635 assume !(1 == ~t7_pc~0); 1785090#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1785091#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1785470#L647 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1786244#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 1785930#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1785931#L654 assume !(1 == ~t8_pc~0); 1785724#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1785725#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1786383#L666 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1786225#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 1786226#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1785338#L673 assume !(1 == ~t9_pc~0); 1785031#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1785032#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1786513#L685 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1786177#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 1786119#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1786120#L692 assume !(1 == ~t10_pc~0); 1786046#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1786045#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1785939#L704 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1785790#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 1785791#L1353-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1786200#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 1785250#L1142-2 assume !(1 == ~T1_E~0); 1785251#L1147-1 assume !(1 == ~T2_E~0); 1786638#L1152-1 assume !(1 == ~T3_E~0); 1786639#L1157-1 assume !(1 == ~T4_E~0); 1786284#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1786285#L1167-1 assume !(1 == ~T6_E~0); 1786366#L1172-1 assume !(1 == ~T7_E~0); 1786367#L1177-1 assume !(1 == ~T8_E~0); 1785983#L1182-1 assume !(1 == ~T9_E~0); 1785984#L1187-1 assume !(1 == ~T10_E~0); 1786167#L1192-1 assume !(1 == ~E_M~0); 1785517#L1197-1 assume !(1 == ~E_1~0); 1785518#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1980059#L1207-1 assume !(1 == ~E_3~0); 1980058#L1212-1 assume !(1 == ~E_4~0); 1980057#L1217-1 assume !(1 == ~E_5~0); 1980056#L1222-1 assume !(1 == ~E_6~0); 1785885#L1227-1 assume !(1 == ~E_7~0); 1785886#L1232-1 assume !(1 == ~E_8~0); 1784975#L1237-1 assume !(1 == ~E_9~0); 1784976#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1785960#L1247-1 assume { :end_inline_reset_delta_events } true; 1785961#L1553-2 [2022-07-22 02:43:14,471 INFO L754 eck$LassoCheckResult]: Loop: 1785961#L1553-2 assume !false; 1982893#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1982880#L999 assume !false; 1982814#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1972083#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1972071#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1972070#L840 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1972065#L854 assume !(0 != eval_~tmp~0#1); 1972066#L1014 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2206962#L712-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2206960#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2206958#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2206955#L1029-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2206953#L1034-3 assume !(0 == ~T3_E~0); 2206951#L1039-3 assume !(0 == ~T4_E~0); 2206948#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2206945#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2206944#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2206942#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2206941#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2206940#L1069-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2206939#L1074-3 assume !(0 == ~E_M~0); 2206937#L1079-3 assume !(0 == ~E_1~0); 2206935#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2206934#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2206933#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2206931#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2206928#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2206926#L1109-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2206924#L1114-3 assume !(0 == ~E_8~0); 2206922#L1119-3 assume !(0 == ~E_9~0); 2206919#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2206917#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2206915#L502-36 assume !(1 == ~m_pc~0); 2206913#L502-38 is_master_triggered_~__retres1~0#1 := 0; 2206911#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2206908#L514-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2206906#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2206904#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2206902#L521-36 assume 1 == ~t1_pc~0; 2206899#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2206829#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2206826#L533-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2206824#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2206822#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2206820#L540-36 assume !(1 == ~t2_pc~0); 1976082#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2206816#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2206813#L552-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2206811#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2206809#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2206807#L559-36 assume !(1 == ~t3_pc~0); 1965785#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2206804#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2206803#L571-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2206801#L1297-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2206799#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2206797#L578-36 assume !(1 == ~t4_pc~0); 2206793#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2206791#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2206790#L590-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2206787#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 2206784#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2206738#L597-36 assume !(1 == ~t5_pc~0); 2206731#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2206724#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2206717#L609-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2206696#L1313-36 assume !(0 != activate_threads_~tmp___4~0#1); 1785519#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1785520#L616-36 assume 1 == ~t6_pc~0; 1786510#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1785037#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1785038#L628-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1785769#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1785770#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1786162#L635-36 assume !(1 == ~t7_pc~0); 1786655#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2202394#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2202392#L647-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2202390#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2202387#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2202385#L654-36 assume !(1 == ~t8_pc~0); 2202383#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2202380#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2202378#L666-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2202376#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1786524#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1785419#L673-36 assume !(1 == ~t9_pc~0); 1785420#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1785798#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1785799#L685-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1786257#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1784982#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1784983#L692-36 assume !(1 == ~t10_pc~0); 1785197#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1785198#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1785768#L704-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1785383#L1353-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1785384#L1353-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1785767#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1785938#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1786441#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1786442#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1785852#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1785853#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1786245#L1167-3 assume !(1 == ~T6_E~0); 1786417#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1785753#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1785648#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1785649#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1785663#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1785664#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2201194#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2201193#L1207-3 assume !(1 == ~E_3~0); 2201192#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2201191#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2201189#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2201186#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2201184#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1980577#L1237-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2201085#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2201083#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2030184#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2030161#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2030159#L840-1 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1785951#L1572 assume !(0 == start_simulation_~tmp~3#1); 1785952#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1982918#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1982907#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1982905#L840-2 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1982903#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1982901#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1982899#L1535 start_simulation_#t~ret30#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1982896#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 1785961#L1553-2 [2022-07-22 02:43:14,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:14,471 INFO L85 PathProgramCache]: Analyzing trace with hash -1513086067, now seen corresponding path program 1 times [2022-07-22 02:43:14,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:14,472 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838838274] [2022-07-22 02:43:14,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:14,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:14,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:14,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:14,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:14,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838838274] [2022-07-22 02:43:14,500 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838838274] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:14,500 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:14,500 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:43:14,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143347777] [2022-07-22 02:43:14,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:14,501 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:14,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:14,501 INFO L85 PathProgramCache]: Analyzing trace with hash -265119742, now seen corresponding path program 1 times [2022-07-22 02:43:14,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:14,502 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106941090] [2022-07-22 02:43:14,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:14,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:14,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:14,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:14,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:14,526 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106941090] [2022-07-22 02:43:14,527 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106941090] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:14,527 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:14,527 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:14,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601601373] [2022-07-22 02:43:14,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:14,527 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:14,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:14,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:14,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:14,528 INFO L87 Difference]: Start difference. First operand 425552 states and 603984 transitions. cyclomatic complexity: 178464 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)